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mt_ventoux: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Bartosz Golaszewski
Tom Rini
parent
8c2644ca69
commit
899dd71e9f
9 changed files with 0 additions and 877 deletions
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@ -3772,7 +3772,6 @@
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#define MACH_TYPE_IMXT_NAV 3829
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#define MACH_TYPE_IMXT_FULL 3830
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#define MACH_TYPE_AG09015 3831
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#define MACH_TYPE_AM3517_MT_VENTOUX 3832
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#define MACH_TYPE_DP1ARM9 3833
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#define MACH_TYPE_PICASSO_M 3834
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#define MACH_TYPE_VIDEO_GADGET 3835
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@ -34,11 +34,6 @@ config TARGET_AM3517_EVM
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select DM_SERIAL
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imply CMD_DM
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config TARGET_MT_VENTOUX
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bool "TeeJet Mt.Ventoux"
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select OMAP3_GPIO_4
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select OMAP3_GPIO_5 if USB_EHCI_HCD
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config TARGET_OMAP3_BEAGLE
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bool "TI OMAP3 BeagleBoard"
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select DM
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@ -189,7 +184,6 @@ config SYS_SOC
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default "omap3"
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source "board/logicpd/am3517evm/Kconfig"
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source "board/teejet/mt_ventoux/Kconfig"
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source "board/ti/beagle/Kconfig"
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source "board/compulab/cm_t35/Kconfig"
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source "board/timll/devkit8000/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_MT_VENTOUX
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config SYS_BOARD
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default "mt_ventoux"
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config SYS_VENDOR
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default "teejet"
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config SYS_CONFIG_NAME
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default "mt_ventoux"
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endif
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@ -1,6 +0,0 @@
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MT_VENTOUX BOARD
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M: Stefano Babic <sbabic@denx.de>
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S: Maintained
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F: board/teejet/mt_ventoux/
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F: include/configs/mt_ventoux.h
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F: configs/mt_ventoux_defconfig
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@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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#
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# Based on ti/evm/Makefile
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obj-y := mt_ventoux.o
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@ -1,342 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright (C) 2009 TechNexion Ltd.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fpga.h>
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#include <video_fb.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/dss.h>
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#include <asm/arch/clock.h>
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#include <i2c.h>
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#include <spartan3.h>
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#include <asm/gpio.h>
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#ifdef CONFIG_USB_EHCI_HCD
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#endif
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#include "mt_ventoux.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define BUZZER 140
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#define SPEAKER 141
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#define USB1_PWR 127
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#define USB2_PWR 149
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#ifndef CONFIG_FPGA
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#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
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#endif
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#define FPGA_RESET 62
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#define FPGA_PROG 116
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#define FPGA_CCLK 117
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#define FPGA_DIN 118
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#define FPGA_INIT 119
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#define FPGA_DONE 154
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#define LCD_PWR 138
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#define LCD_PON_PIN 139
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
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static struct {
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u32 xres;
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u32 yres;
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} panel_resolution[] = {
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{ 480, 272 },
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{ 800, 480 }
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};
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static struct panel_config lcd_cfg[] = {
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{
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.timing_h = PANEL_TIMING_H(40, 5, 2),
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.timing_v = PANEL_TIMING_V(8, 8, 2),
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.pol_freq = 0x00003000, /* Pol Freq */
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.divisor = 0x00010033, /* 9 Mhz Pixel Clock */
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.panel_type = 0x01, /* TFT */
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.data_lines = 0x03, /* 24 Bit RGB */
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.load_mode = 0x02, /* Frame Mode */
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.panel_color = 0,
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.gfx_format = GFXFORMAT_RGB24_UNPACKED,
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},
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{
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.timing_h = PANEL_TIMING_H(20, 192, 4),
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.timing_v = PANEL_TIMING_V(2, 20, 10),
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.pol_freq = 0x00004000, /* Pol Freq */
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.divisor = 0x0001000E, /* 36Mhz Pixel Clock */
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.panel_type = 0x01, /* TFT */
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.data_lines = 0x03, /* 24 Bit RGB */
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.load_mode = 0x02, /* Frame Mode */
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.panel_color = 0,
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.gfx_format = GFXFORMAT_RGB24_UNPACKED,
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}
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};
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#endif
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/* Timing definitions for FPGA */
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static const u32 gpmc_fpga[] = {
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FPGA_GPMC_CONFIG1,
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FPGA_GPMC_CONFIG2,
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FPGA_GPMC_CONFIG3,
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FPGA_GPMC_CONFIG4,
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FPGA_GPMC_CONFIG5,
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FPGA_GPMC_CONFIG6,
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};
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#ifdef CONFIG_USB_EHCI_HCD
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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static inline void fpga_reset(int nassert)
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{
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gpio_set_value(FPGA_RESET, !nassert);
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}
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int fpga_pgm_fn(int nassert, int nflush, int cookie)
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{
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debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
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gpio_set_value(FPGA_PROG, !nassert);
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return nassert;
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}
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int fpga_init_fn(int cookie)
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{
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return !gpio_get_value(FPGA_INIT);
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}
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int fpga_done_fn(int cookie)
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{
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return gpio_get_value(FPGA_DONE);
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}
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int fpga_pre_config_fn(int cookie)
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{
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debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
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/* Setting GPIOs for programming Mode */
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gpio_request(FPGA_RESET, "FPGA_RESET");
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gpio_direction_output(FPGA_RESET, 1);
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gpio_request(FPGA_PROG, "FPGA_PROG");
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gpio_direction_output(FPGA_PROG, 1);
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gpio_request(FPGA_CCLK, "FPGA_CCLK");
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gpio_direction_output(FPGA_CCLK, 1);
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gpio_request(FPGA_DIN, "FPGA_DIN");
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gpio_direction_output(FPGA_DIN, 0);
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gpio_request(FPGA_INIT, "FPGA_INIT");
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gpio_direction_input(FPGA_INIT);
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gpio_request(FPGA_DONE, "FPGA_DONE");
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gpio_direction_input(FPGA_DONE);
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/* Be sure that signal are deasserted */
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gpio_set_value(FPGA_RESET, 1);
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gpio_set_value(FPGA_PROG, 1);
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return 0;
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}
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int fpga_post_config_fn(int cookie)
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{
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debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
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fpga_reset(true);
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udelay(100);
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fpga_reset(false);
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return 0;
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}
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/* Write program to the FPGA */
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int fpga_wr_fn(int nassert_write, int flush, int cookie)
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{
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gpio_set_value(FPGA_DIN, nassert_write);
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return nassert_write;
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}
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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gpio_set_value(FPGA_CCLK, assert_clk);
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return assert_clk;
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}
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xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_clk_fn,
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fpga_init_fn,
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fpga_done_fn,
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fpga_wr_fn,
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fpga_post_config_fn,
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};
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xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
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(void *)&mt_ventoux_fpga_fns, 0);
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/* Initialize the FPGA */
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static void mt_ventoux_init_fpga(void)
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{
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fpga_pre_config_fn(0);
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/* Setting CS1 for FPGA access */
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enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
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FPGA_BASE_ADDR, GPMC_SIZE_128M);
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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mt_ventoux_init_fpga();
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/* GPIO_140: speaker #mute */
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MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
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/* GPIO_141: Buzz Hi */
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MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
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/* Turning off the buzzer */
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gpio_request(BUZZER, "BUZZER_MUTE");
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gpio_request(SPEAKER, "SPEAKER");
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gpio_direction_output(BUZZER, 0);
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gpio_direction_output(SPEAKER, 0);
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/* Activate USB power */
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gpio_request(USB1_PWR, "USB1_PWR");
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gpio_request(USB2_PWR, "USB2_PWR");
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gpio_direction_output(USB1_PWR, 1);
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gpio_direction_output(USB2_PWR, 1);
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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int misc_init_r(void)
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{
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char *eth_addr;
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struct tam3517_module_info info;
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int ret;
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TAM3517_READ_EEPROM(&info, ret);
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omap_die_id_display();
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if (ret)
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return 0;
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eth_addr = env_get("ethaddr");
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if (!eth_addr)
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TAM3517_READ_MAC_FROM_EEPROM(&info);
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TAM3517_PRINT_SOM_INFO(&info);
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return 0;
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}
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#endif
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_MT_VENTOUX();
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}
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int board_eth_init(bd_t *bis)
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{
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davinci_emac_initialize();
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return 0;
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}
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#if defined(CONFIG_MMC_OMAP_HS) && \
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!defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
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int board_video_init(void)
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{
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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struct panel_config *panel = &lcd_cfg[0];
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char *s;
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u32 index = 0;
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void *fb;
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fb = (void *)0x88000000;
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s = env_get("panel");
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if (s) {
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index = simple_strtoul(s, NULL, 10);
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if (index < ARRAY_SIZE(lcd_cfg))
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panel = &lcd_cfg[index];
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else
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return 0;
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}
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panel->frame_buffer = fb;
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printf("Panel: %dx%d\n", panel_resolution[index].xres,
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panel_resolution[index].yres);
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panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
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(panel_resolution[index].xres - 1);
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gpio_request(LCD_PWR, "LCD Power");
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gpio_request(LCD_PON_PIN, "LCD Pon");
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gpio_direction_output(LCD_PWR, 0);
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gpio_direction_output(LCD_PON_PIN, 1);
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setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
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setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
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omap3_dss_panel_config(panel);
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omap3_dss_enable();
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return 0;
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}
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#endif
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@ -1,403 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Stefano Babic <sbabic@denx.de>
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*
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* Author: Hardy Weng <hardy.weng@technexion.com>
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*
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* Copyright (C) 2010 TechNexion Ltd.
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*/
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#ifndef _MT_VENTOUX_H_
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#define _MT_VENTOUX_H_
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"Teejet MT_VENTOUX Board",
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"NAND",
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};
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/* FPGA CS1 configuration */
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#define FPGA_GPMC_CONFIG1 0x00001200
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#define FPGA_GPMC_CONFIG2 0x00161f00
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#define FPGA_GPMC_CONFIG3 0x00040400
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#define FPGA_GPMC_CONFIG4 0x120c1f08
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#define FPGA_GPMC_CONFIG5 0x001e161f
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#define FPGA_GPMC_CONFIG6 0x96080fcf
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#define FPGA_BASE_ADDR 0x20000000
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_MT_VENTOUX() \
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/* SDRC */\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_CKE0), (M0)) \
|
||||
MUX_VAL(CP(SDRC_CKE1), (M0)) \
|
||||
MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
|
||||
/* GPMC */\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
|
||||
/* GPIO 55 : NFS */\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \
|
||||
/*GPIO_62: FPGA_RESET */ \
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_64*/ \
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
|
||||
/* DSS */\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
|
||||
/* CAMERA */\
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
|
||||
/* MMC */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_126: CardDetect */\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
|
||||
/*GPIO_128 */ \
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
|
||||
/* GPIO_138: LCD_ENVD */\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \
|
||||
/* GPIO_139: LCD_PON */\
|
||||
/* McBSP */\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \
|
||||
/* GPIO_116: FPGA_PROG */ \
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
|
||||
/* GPIO_117: FPGA_CCLK */ \
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
|
||||
/* GPIO_118: FPGA_DIN */ \
|
||||
MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
|
||||
/* GPIO_119: FPGA_INIT */ \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \
|
||||
/*GPIO_152: Ignition Sense */ \
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \
|
||||
/*GPIO_153: Power Button Sense */ \
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \
|
||||
/* GPIO_154: FPGA_DONE */ \
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \
|
||||
/* GPIO_155: CA8_irq */ \
|
||||
/* UART */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_149: USB status 2 */\
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_150: USB status 1 */\
|
||||
\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \
|
||||
/* gpt9_pwm */\
|
||||
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \
|
||||
/* gpt10_pwm */\
|
||||
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \
|
||||
/* gpt8_pwm */\
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \
|
||||
/* gpt11_pwm */\
|
||||
\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \
|
||||
/*GPIO_163 : TS_PENIRQ*/ \
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \
|
||||
/*GPIO_164 : MMC */\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
|
||||
/* I2C */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
|
||||
/* McSPI */\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \
|
||||
/* CCDC */\
|
||||
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO94 */\
|
||||
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \
|
||||
/* GPIO95: #Enable Output */\
|
||||
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \
|
||||
/* GPIO 99: #SOM_PWR_OFF */\
|
||||
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \
|
||||
/* GPIO_100: #power out */\
|
||||
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \
|
||||
/* GPIO_102 */\
|
||||
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \
|
||||
/* RMII */\
|
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
|
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
|
||||
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
|
||||
/* HECC */\
|
||||
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
|
||||
/* HSUSB */\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
|
||||
/* HDQ */\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
|
||||
/* GPIO_170: auto update */\
|
||||
/* Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
|
||||
/* - GPIO30 */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
|
||||
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \
|
||||
/* gpio_10 */\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
|
||||
/* JTAG */\
|
||||
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
|
||||
MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
|
||||
/* ETK (ES2 onwards) */\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
|
||||
/* hsusb1_stp */ \
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
|
||||
/* hsusb1_clk */\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \
|
||||
/* gpio_24 */\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
|
||||
/* gpio_26 */\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
|
||||
/* gpio_29 */\
|
||||
/* Die to Die */\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
|
||||
#endif
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
# CONFIG_SYS_THUMB_BUILD is not set
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80008000
|
||||
CONFIG_TARGET_MT_VENTOUX=y
|
||||
CONFIG_EMIF4=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SPL=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL_TEXT_BASE=0x40200000
|
||||
# CONFIG_SPL_FS_EXT4 is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="mt_ventoux => "
|
||||
CONFIG_CMD_EEPROM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_SPARTAN3=y
|
||||
CONFIG_SYS_OMAP24_I2C_SPEED=400000
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||
CONFIG_SPL_NAND_SIMPLE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DRIVER_TI_EMAC=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO_OMAP3=y
|
||||
CONFIG_VIDEO=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2011
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
*
|
||||
* Configuration settings for the Teejet mt_ventoux board.
|
||||
*
|
||||
* Copyright (C) 2009 TechNexion Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "tam3517-common.h"
|
||||
|
||||
#undef CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
|
||||
6 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX
|
||||
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
|
||||
#define CONFIG_HOSTNAME "mt_ventoux"
|
||||
|
||||
/*
|
||||
* Set its own mtdparts, different from common
|
||||
*/
|
||||
|
||||
/*
|
||||
* FPGA
|
||||
*/
|
||||
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||||
#define CONFIG_SYS_FPGA_WAIT 10000
|
||||
#define CONFIG_MAX_FPGA_DEVICES 1
|
||||
#define CONFIG_FPGA_DELAY() udelay(1)
|
||||
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||||
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
|
||||
"bootcmd=run net_nfs\0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue