mirror of
https://github.com/AsahiLinux/u-boot
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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi
- Support Infineon S28HS02GT (Takahiro)
This commit is contained in:
Tom Rini
commit
8986be59e7
7 changed files with 119 additions and 154 deletions
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@ -331,18 +331,42 @@ static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy,
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u8 *val)
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{
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1),
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SPI_MEM_OP_ADDR(nor->addr_mode_nbytes, addr, 1),
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SPI_MEM_OP_DUMMY(dummy / 8, 1),
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SPI_MEM_OP_DATA_IN(1, NULL, 1));
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0),
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SPI_MEM_OP_ADDR(nor->addr_mode_nbytes, addr, 0),
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SPI_MEM_OP_DUMMY(dummy, 0),
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SPI_MEM_OP_DATA_IN(1, NULL, 0));
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u8 buf[2];
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int ret;
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return spi_nor_read_write_reg(nor, &op, val);
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spi_nor_setup_op(nor, &op, nor->reg_proto);
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/*
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* In Octal DTR mode, the number of address bytes is always 4 regardless
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* of addressing mode setting.
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*/
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if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR)
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op.addr.nbytes = 4;
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/*
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* We don't want to read only one byte in DTR mode. So, read 2 and then
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* discard the second byte.
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*/
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if (spi_nor_protocol_is_dtr(nor->reg_proto))
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op.data.nbytes = 2;
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ret = spi_nor_read_write_reg(nor, &op, buf);
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if (ret)
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return ret;
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*val = buf[0];
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return 0;
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}
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static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val)
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{
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1),
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
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SPI_MEM_OP_ADDR(nor->addr_mode_nbytes, addr, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1, NULL, 1));
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@ -714,7 +738,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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*/
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static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy)
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{
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u32 reg_addr = addr_base + SPINOR_REG_ADDR_STR1V;
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u32 reg_addr = addr_base + SPINOR_REG_CYPRESS_STR1V;
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u8 sr;
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int ret;
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@ -728,7 +752,7 @@ static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy)
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else
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dev_dbg(nor->dev, "Programming Error occurred\n");
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nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
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nor->write_reg(nor, SPINOR_OP_CYPRESS_CLPEF, NULL, 0);
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return -EIO;
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}
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@ -1856,7 +1880,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
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static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base,
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u8 dummy)
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{
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u32 addr = addr_base + SPINOR_REG_ADDR_CFR1V;
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u32 addr = addr_base + SPINOR_REG_CYPRESS_CFR1V;
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u8 cr;
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int ret;
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@ -3293,11 +3317,11 @@ static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info,
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* Read CR3V to check if uniform sector is selected. If not, assign an
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* erase hook that supports non-uniform erase.
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*/
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ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V,
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ret = spansion_read_any_reg(nor, SPINOR_REG_CYPRESS_CFR3V,
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S25FS_S_RDAR_DUMMY, &cfr3v);
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if (ret)
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return ret;
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if (!(cfr3v & CFR3V_UNHYSA))
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if (!(cfr3v & SPINOR_REG_CYPRESS_CFR3_UNISECT))
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nor->erase = s25fs_s_erase_non_uniform;
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return spi_nor_default_setup(nor, info, params);
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@ -3346,13 +3370,13 @@ static struct spi_nor_fixups s25fs_s_fixups = {
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.post_sfdp = s25fs_s_post_sfdp_fixup,
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};
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static int s25_mdp_ready(struct spi_nor *nor)
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static int s25_s28_mdp_ready(struct spi_nor *nor)
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{
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u32 addr;
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int ret;
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for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
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ret = spansion_sr_ready(nor, addr, 0);
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ret = spansion_sr_ready(nor, addr, nor->rdsr_dummy);
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if (!ret)
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return ret;
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}
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@ -3374,15 +3398,15 @@ static int s25_quad_enable(struct spi_nor *nor)
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return 0;
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}
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static int s25_erase_non_uniform(struct spi_nor *nor, loff_t addr)
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static int s25_s28_erase_non_uniform(struct spi_nor *nor, loff_t addr)
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{
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/* Support 32 x 4KB sectors at bottom */
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return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0,
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SZ_128K);
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}
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static int s25_setup(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params)
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static int s25_s28_setup(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params)
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{
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int ret;
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u8 cr;
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@ -3396,7 +3420,8 @@ static int s25_setup(struct spi_nor *nor, const struct flash_info *info,
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* uniform 128KB only due to complexity of non-uniform layout.
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*/
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if (nor->info->id[4] == S25FS256T_ID4) {
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ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_ARCFN, 8, &cr);
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ret = spansion_read_any_reg(nor, SPINOR_REG_CYPRESS_ARCFN, 8,
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&cr);
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if (ret)
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return ret;
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@ -3410,31 +3435,31 @@ static int s25_setup(struct spi_nor *nor, const struct flash_info *info,
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* Read CFR3V to check if uniform sector is selected. If not, assign an
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* erase hook that supports non-uniform erase.
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*/
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ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cr);
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ret = spansion_read_any_reg(nor, SPINOR_REG_CYPRESS_CFR3V, 0, &cr);
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if (ret)
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return ret;
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if (!(cr & CFR3V_UNHYSA))
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nor->erase = s25_erase_non_uniform;
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if (!(cr & SPINOR_REG_CYPRESS_CFR3_UNISECT))
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nor->erase = s25_s28_erase_non_uniform;
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/*
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* For the multi-die package parts, the ready() hook is needed to check
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* all dies' status via read any register.
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*/
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if (nor->mtd.size > SZ_128M)
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nor->ready = s25_mdp_ready;
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nor->ready = s25_s28_mdp_ready;
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return spi_nor_default_setup(nor, info, params);
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}
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static void s25_default_init(struct spi_nor *nor)
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{
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nor->setup = s25_setup;
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nor->setup = s25_s28_setup;
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}
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static int s25_post_bfpt_fixup(struct spi_nor *nor,
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const struct sfdp_parameter_header *header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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static int s25_s28_post_bfpt_fixup(struct spi_nor *nor,
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const struct sfdp_parameter_header *header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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int ret;
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u32 addr;
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@ -3474,12 +3499,13 @@ static int s25_post_bfpt_fixup(struct spi_nor *nor,
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* dies are configured to 512B buffer.
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*/
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for (addr = 0; addr < params->size; addr += SZ_128M) {
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ret = spansion_read_any_reg(nor, addr + SPINOR_REG_ADDR_CFR3V,
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0, &cfr3v);
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ret = spansion_read_any_reg(nor,
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addr + SPINOR_REG_CYPRESS_CFR3V, 0,
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&cfr3v);
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if (ret)
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return ret;
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if (!(cfr3v & CFR3V_PGMBUF)) {
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if (!(cfr3v & SPINOR_REG_CYPRESS_CFR3_PGSZ)) {
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params->page_size = 256;
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return 0;
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}
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@ -3507,7 +3533,7 @@ static void s25_post_sfdp_fixup(struct spi_nor *nor,
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static struct spi_nor_fixups s25_fixups = {
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.default_init = s25_default_init,
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.post_bfpt = s25_post_bfpt_fixup,
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.post_bfpt = s25_s28_post_bfpt_fixup,
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.post_sfdp = s25_post_sfdp_fixup,
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};
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@ -3539,97 +3565,57 @@ static struct spi_nor_fixups s25fl256l_fixups = {
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*/
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static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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u32 addr;
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u8 buf;
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u8 addr_width = 3;
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int ret;
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/* Use 24 dummy cycles for memory array reads. */
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ret = write_enable(nor);
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if (ret)
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return ret;
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buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24;
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op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
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SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1, &buf, 1));
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ret = spi_mem_exec_op(nor->spi, &op);
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if (ret) {
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dev_warn(nor->dev,
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"failed to set default memory latency value: %d\n",
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ret);
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return ret;
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}
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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/* Use 24 dummy cycles for memory array reads. */
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for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
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ret = spansion_read_any_reg(nor,
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addr + SPINOR_REG_CYPRESS_CFR2V, 0,
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&buf);
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if (ret)
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return ret;
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buf &= ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK;
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buf |= SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24;
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ret = spansion_write_any_reg(nor,
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addr + SPINOR_REG_CYPRESS_CFR2V,
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buf);
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if (ret) {
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dev_warn(nor->dev, "failed to set default memory latency value: %d\n", ret);
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return ret;
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}
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}
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nor->read_dummy = 24;
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/* Set the octal and DTR enable bits. */
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ret = write_enable(nor);
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if (ret)
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return ret;
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/* Set the octal and DTR enable bits. */
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buf = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;
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op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
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SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1, &buf, 1));
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ret = spi_mem_exec_op(nor->spi, &op);
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if (ret) {
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dev_warn(nor->dev, "Failed to enable octal DTR mode\n");
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return ret;
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for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
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ret = spansion_write_any_reg(nor,
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addr + SPINOR_REG_CYPRESS_CFR5V,
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buf);
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if (ret) {
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dev_warn(nor->dev, "Failed to enable octal DTR mode\n");
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return ret;
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}
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}
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return 0;
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}
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static int s28hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
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{
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/* Factory default configuration: 32 x 4 KiB sectors at bottom. */
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return spansion_erase_non_uniform(nor, addr, SPINOR_OP_S28_SE_4K,
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0, SZ_128K);
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}
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static int s28hx_t_setup(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params)
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{
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struct spi_mem_op op;
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u8 buf;
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u8 addr_width = 3;
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int ret;
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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/*
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* Check CFR3V to check if non-uniform sector mode is selected. If it
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* is, set the erase hook to the non-uniform erase procedure.
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*/
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
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SPI_MEM_OP_ADDR(addr_width,
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SPINOR_REG_CYPRESS_CFR3V, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(1, &buf, 1));
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ret = spi_mem_exec_op(nor->spi, &op);
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if (ret)
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return ret;
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if (!(buf & SPINOR_REG_CYPRESS_CFR3_UNISECT))
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nor->erase = s28hx_t_erase_non_uniform;
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return spi_nor_default_setup(nor, info, params);
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}
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static void s28hx_t_default_init(struct spi_nor *nor)
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{
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nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
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nor->setup = s28hx_t_setup;
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nor->setup = s25_s28_setup;
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}
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static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor,
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@ -3663,50 +3649,10 @@ static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor,
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params->rdsr_addr_nbytes = 4;
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}
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static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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struct spi_mem_op op;
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u8 buf;
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u8 addr_width = 3;
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int ret;
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/*
|
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* The BFPT table advertises a 512B page size but the page size is
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* actually configurable (with the default being 256B). Read from
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* CFR3V[4] and set the correct size.
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*/
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
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SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR3V, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(1, &buf, 1));
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ret = spi_mem_exec_op(nor->spi, &op);
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if (ret)
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return ret;
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if (buf & SPINOR_REG_CYPRESS_CFR3_PGSZ)
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params->page_size = 512;
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else
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params->page_size = 256;
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/*
|
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* The BFPT advertises that it supports 4k erases, and the datasheet
|
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* says the same. But 4k erases did not work when testing. So, use 256k
|
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* erases for now.
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*/
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nor->erase_opcode = SPINOR_OP_SE_4B;
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nor->mtd.erasesize = 0x40000;
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return 0;
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}
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static struct spi_nor_fixups s28hx_t_fixups = {
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.default_init = s28hx_t_default_init,
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.post_sfdp = s28hx_t_post_sfdp_fixup,
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.post_bfpt = s28hx_t_post_bfpt_fixup,
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.post_bfpt = s25_s28_post_bfpt_fixup,
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};
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#endif /* CONFIG_SPI_FLASH_S28HX_T */
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|
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@ -239,6 +239,8 @@ const struct flash_info spi_nor_ids[] = {
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
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SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
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{ INFO("is25lx512", 0x9d5a1a, 0, 64 * 1024, 1024,
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SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) },
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#endif
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#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
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/* Macronix */
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@ -381,6 +383,7 @@ const struct flash_info spi_nor_ids[] = {
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{ INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
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{ INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
|
||||
{ INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
|
||||
{ INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ) },
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_SPI_FLASH_SST /* SST */
|
||||
|
|
@ -554,6 +557,10 @@ const struct flash_info spi_nor_ids[] = {
|
|||
{ INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ INFO("XM25QH512C", 0x204020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ INFO("XM25QU512C", 0x204120, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
#endif
|
||||
#ifdef CONFIG_SPI_FLASH_XTX
|
||||
/* XTX Technology Limited */
|
||||
|
|
|
|||
|
|
@ -18,9 +18,6 @@
|
|||
#include "cadence_qspi.h"
|
||||
#include <dt-bindings/power/xlnx-versal-power.h>
|
||||
|
||||
#define CMD_4BYTE_READ 0x13
|
||||
#define CMD_4BYTE_FAST_READ 0x0C
|
||||
|
||||
int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -33,6 +33,10 @@
|
|||
#define CQSPI_DUMMY_BYTES_MAX 4
|
||||
#define CQSPI_DUMMY_CLKS_MAX 31
|
||||
|
||||
#define CMD_4BYTE_FAST_READ 0x0C
|
||||
#define CMD_4BYTE_OCTAL_READ 0x7c
|
||||
#define CMD_4BYTE_READ 0x13
|
||||
|
||||
/****************************************************************************
|
||||
* Controller's configuration and status register (offset from QSPI_BASE)
|
||||
****************************************************************************/
|
||||
|
|
|
|||
|
|
@ -469,6 +469,9 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv,
|
|||
else
|
||||
opcode = op->cmd.opcode;
|
||||
|
||||
if (opcode == CMD_4BYTE_OCTAL_READ && !priv->dtr)
|
||||
opcode = CMD_4BYTE_FAST_READ;
|
||||
|
||||
reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
|
||||
|
||||
/* Set up dummy cycles. */
|
||||
|
|
|
|||
|
|
@ -111,6 +111,9 @@
|
|||
#define SR_TX_ERR BIT(5)
|
||||
#define SR_DCOL BIT(6)
|
||||
|
||||
/* Bit field in RISR */
|
||||
#define RISR_INT_RXOI BIT(3)
|
||||
|
||||
#define RX_TIMEOUT 1000 /* timeout in ms */
|
||||
|
||||
struct dw_spi_plat {
|
||||
|
|
@ -588,7 +591,7 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
|
|||
struct dw_spi_priv *priv = dev_get_priv(bus);
|
||||
u8 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
|
||||
u8 op_buf[op_len];
|
||||
u32 cr0;
|
||||
u32 cr0, sts;
|
||||
|
||||
if (read)
|
||||
priv->tmode = CTRLR0_TMOD_EPROMREAD;
|
||||
|
|
@ -632,12 +635,21 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
|
|||
* them to fail because we are not reading/writing the fifo fast enough.
|
||||
*/
|
||||
if (read) {
|
||||
priv->rx = op->data.buf.in;
|
||||
void *prev_rx = priv->rx = op->data.buf.in;
|
||||
priv->rx_end = priv->rx + op->data.nbytes;
|
||||
|
||||
dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
|
||||
while (priv->rx != priv->rx_end)
|
||||
while (priv->rx != priv->rx_end) {
|
||||
dw_reader(priv);
|
||||
if (prev_rx == priv->rx) {
|
||||
sts = dw_read(priv, DW_SPI_RISR);
|
||||
if (sts & RISR_INT_RXOI) {
|
||||
dev_err(bus, "FIFO overflow on Rx\n");
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
prev_rx = priv->rx;
|
||||
}
|
||||
} else {
|
||||
u32 val;
|
||||
|
||||
|
|
|
|||
|
|
@ -136,14 +136,6 @@
|
|||
#define SPINOR_OP_BRRD 0x16 /* Bank register read */
|
||||
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
|
||||
#define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */
|
||||
#define SPINOR_OP_RDAR 0x65 /* Read any register */
|
||||
#define SPINOR_OP_WRAR 0x71 /* Write any register */
|
||||
#define SPINOR_REG_ADDR_STR1V 0x00800000
|
||||
#define SPINOR_REG_ADDR_CFR1V 0x00800002
|
||||
#define SPINOR_REG_ADDR_CFR3V 0x00800004
|
||||
#define SPINOR_REG_ADDR_ARCFN 0x00000006
|
||||
#define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */
|
||||
#define CFR3V_PGMBUF BIT(4) /* Program buffer size */
|
||||
|
||||
/* Used for Micron flashes only. */
|
||||
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
|
||||
|
|
@ -188,8 +180,12 @@
|
|||
/* For Cypress flash. */
|
||||
#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
|
||||
#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
|
||||
#define SPINOR_OP_S28_SE_4K 0x21
|
||||
#define SPINOR_OP_CYPRESS_CLPEF 0x82 /* Clear P/E err flag */
|
||||
#define SPINOR_REG_CYPRESS_ARCFN 0x00000006
|
||||
#define SPINOR_REG_CYPRESS_STR1V 0x00800000
|
||||
#define SPINOR_REG_CYPRESS_CFR1V 0x00800002
|
||||
#define SPINOR_REG_CYPRESS_CFR2V 0x00800003
|
||||
#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0)
|
||||
#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb
|
||||
#define SPINOR_REG_CYPRESS_CFR3V 0x00800004
|
||||
#define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */
|
||||
|
|
|
|||
Loading…
Reference in a new issue