serial: zynq: Change uart initialization logic

The commit a673025535 ("serial: zynq: Initialize uart only before
relocation") introduced code which detects relocation which is working for
single uart instance. With multiple instances in place there is a need to
enable and setup every instance. That's why detect if TX is enabled. If it
is then don't initialize uart again.
In post probe setbrg is called to setup baudrate but values should be the
same.

As a side effect of this change is that DECLARE_GLOBAL_DATA_PTR can be
removed completely.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2020-03-24 11:31:42 +01:00
parent 5028358a6a
commit 895a7866c2

View file

@ -17,8 +17,6 @@
#include <serial.h> #include <serial.h>
#include <linux/err.h> #include <linux/err.h>
DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
@ -45,7 +43,7 @@ struct zynq_uart_platdata {
struct uart_zynq *regs; struct uart_zynq *regs;
}; };
/* Set up the baud rate in gd struct */ /* Set up the baud rate */
static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
unsigned long clock, unsigned long baud) unsigned long clock, unsigned long baud)
{ {
@ -140,9 +138,12 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
static int zynq_serial_probe(struct udevice *dev) static int zynq_serial_probe(struct udevice *dev)
{ {
struct zynq_uart_platdata *platdata = dev_get_platdata(dev); struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
struct uart_zynq *regs = platdata->regs;
u32 val;
/* No need to reinitialize the UART after relocation */ /* No need to reinitialize the UART if TX already enabled */
if (gd->flags & GD_FLG_RELOC) val = readl(&regs->control);
if (val & ZYNQ_UART_CR_TX_EN)
return 0; return 0;
_uart_zynq_serial_init(platdata->regs); _uart_zynq_serial_init(platdata->regs);