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board: gateworks: venice: update GW74xx PMIC config

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Update the GW74xx PMIC configuration:
 - increase VDD_SOC DVS1 to 0.85V per datasheet
 - increase VDD_SOC DVS0 to 0.95V before first DRAM access
 - increase VDD_ARM DVS0 to 0.95V to support kernel overdrive voltage (OD)
 - remove unnecessary changes to VDD_DRAM as we don't use 3GHz DRAM
 - remove unnecessary change to LDO2 as it is unused

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
v2: update commit log with more detail
This commit is contained in:
Tim Harvey 2022-09-08 14:41:09 -07:00 • committed by Stefano Babic
parent 22adeef0f2
commit 880d5688f1
1 changed files with 7 additions and 9 deletions
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16
board/gateworks/venice/spl.c
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@ -156,17 +156,15 @@ static int power_init_board(void)
/* Buck 1 DVS control through PMIC_STBY_REQ */
dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
/* Set DVS1 to 0.8v for suspend */
dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
/* Set DVS1 to 0.85v for suspend */
dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
/* increase VDD_DRAM to 0.95v for 3Ghz DDR */
dm_i2c_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
/* increase VDD_SOC to 0.95V before first DRAM access */
dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
/* VDD_DRAM off in suspend: B1_ENMODE=10 */
dm_i2c_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
/* set VDD_SNVS_0V8 from default 0.85V */
dm_i2c_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
/* Kernel uses OD/OD freq for SOC */
/* To avoid timing risk from SOC to ARM, increase VDD_ARM to OD voltage 0.95v */
dm_i2c_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */
dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);