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Layerscape: Add crypto node in device tree

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LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Gaurav Jain 2022-03-24 11:50:34 +05:30 committed by Stefano Babic
parent cb5d0419f5
commit 88071ca2bb
7 changed files with 291 additions and 3 deletions
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46
arch/arm/dts/fsl-ls1012a.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor
*/
@ -71,6 +71,50 @@
bus-width = <4>;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <0 75 0x4>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 71 0x4>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 72 0x4>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 73 0x4>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 74 0x4>;
};
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;

45
arch/arm/dts/fsl-ls1043a.dtsi
View file

@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
@ -125,6 +125,49 @@
interrupts = <0 43 0x4>;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <0 75 0x4>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 71 0x4>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 72 0x4>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 73 0x4>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 74 0x4>;
};
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;

44
arch/arm/dts/fsl-ls1046a.dtsi
View file

@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
* Copyright 2021 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@ -124,6 +125,49 @@
interrupts = <0 43 0x4>;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <0 75 0x4>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 71 0x4>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 72 0x4>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 73 0x4>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 74 0x4>;
};
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;

39
arch/arm/dts/fsl-ls1088a.dtsi
View file

@ -174,6 +174,45 @@
dr_mode = "host";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x8000000 0x100000>;
reg = <0x00 0x8000000 0x0 0x100000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */

39
arch/arm/dts/fsl-ls2080a.dtsi
View file

@ -239,6 +239,45 @@
status = "disabled";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x8000000 0x100000>;
reg = <0x00 0x8000000 0x0 0x100000>;
interrupts = <0 139 0x4>; /* Level high type */
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 140 0x4>; /* Level high type */
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 141 0x4>; /* Level high type */
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 142 0x4>; /* Level high type */
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 143 0x4>; /* Level high type */
};
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc", "simple-mfd";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */

41
arch/arm/dts/fsl-lx2160a.dtsi
View file

@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
* Copyright 2018-2020 NXP
* Copyright 2018-2021 NXP
*
*/
@ -27,6 +27,45 @@
clock-output-names = "sysclk";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x8000000 0x100000>;
reg = <0x00 0x8000000 0x0 0x100000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;

40
arch/arm/dts/ls1021a.dtsi
View file

@ -3,6 +3,7 @@
* Freescale ls1021a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include "skeleton.dtsi"
@ -144,6 +145,45 @@
big-endian;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <7>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1700000 0x100000>;
ranges = <0x0 0x1700000 0x100000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
};
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;