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Merge git://git.denx.de/u-boot-uniphier

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This commit is contained in:
Tom Rini 2017-12-11 17:06:04 -05:00
commit 87f3dee22b
3 changed files with 14 additions and 9 deletions
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1
arch/arm/mach-uniphier/clk/Makefile
View file

@ -27,3 +27,4 @@ endif
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o

15
arch/arm/mach-uniphier/clk/pll-base-ld20.c
View file

@ -5,8 +5,10 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#include <linux/bitfield.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/sizes.h> #include <linux/sizes.h>
@ -18,7 +20,6 @@
#define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL_SSC_EN BIT(31)
#define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_NRSTDS BIT(28)
#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
#define SC_PLLCTRL3_REGI_SHIFT 16
#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
/* PLL type: VPLL27 */ /* PLL type: VPLL27 */
@ -41,13 +42,17 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
tmp = readl(base); /* SSCPLLCTRL */ tmp = readl(base); /* SSCPLLCTRL */
tmp &= ~SC_PLLCTRL_SSC_DK_MASK; tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
tmp |= (487 * freq * ssc_rate / divn / 512) & tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK,
SC_PLLCTRL_SSC_DK_MASK; DIV_ROUND_CLOSEST(487UL * freq * ssc_rate,
divn * 512));
writel(tmp, base); writel(tmp, base);
tmp = readl(base + 4); tmp = readl(base + 4);
tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK,
DIV_ROUND_CLOSEST(21431887UL * freq,
divn * 512));
writel(tmp, base + 4);
udelay(50); udelay(50);
} }
@ -90,7 +95,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp = readl(base + 8); /* SSCPLLCTRL3 */
tmp &= ~SC_PLLCTRL3_REGI_MASK; tmp &= ~SC_PLLCTRL3_REGI_MASK;
tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
writel(tmp, base + 8); writel(tmp, base + 8);
iounmap(base); iounmap(base);

7
drivers/mtd/nand/Kconfig
View file

@ -10,15 +10,14 @@ config SYS_NAND_SELF_INIT
NAND initialization process. NAND initialization process.
config NAND_DENALI config NAND_DENALI
bool "Support Denali NAND controller" bool
select SYS_NAND_SELF_INIT select SYS_NAND_SELF_INIT
imply CMD_NAND imply CMD_NAND
help
Enable support for the Denali NAND controller.
config NAND_DENALI_DT config NAND_DENALI_DT
bool "Support Denali NAND controller as a DT device" bool "Support Denali NAND controller as a DT device"
depends on NAND_DENALI && OF_CONTROL && DM select NAND_DENALI
depends on OF_CONTROL && DM
help help
Enable the driver for NAND flash on platforms using a Denali NAND Enable the driver for NAND flash on platforms using a Denali NAND
controller as a DT device. controller as a DT device.