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https://github.com/AsahiLinux/u-boot
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Update NetStar board
Patch by Ladislav Michl, 03 Nov 2005
This commit is contained in:
Wolfgang Denk
parent
029b6dc77c
commit
87a5c73d66
7 changed files with 103 additions and 41 deletions
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Update NetStar board
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Patch by Ladislav Michl, 03 Nov 2005
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* Make code better readable.
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Patch by Ladislav Michl, 14 Sep 2005
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@ -13,6 +13,7 @@
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* u32 - crc32
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*/
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#include <config.h>
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#include "crcek.h"
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/**
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@ -39,7 +40,7 @@
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.macro crcuj, offset, size
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mov r0, #0
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ldr r1, \offset
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ldr r2, [r1]
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ldr r2, [r1], #4
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cmp r2, r0 @ no data, no problem
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beq 2f
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tst r2, #3 @ unaligned size
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@ -47,7 +48,6 @@
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ldr r3, \size
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cmp r2, r3 @ bogus size
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bhi 2f
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add r1, r1, #4
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do_crc32
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ldr r1, [r1]
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2:
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@ -55,16 +55,71 @@
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.endm
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.macro wait, reg
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mov \reg, #0x1000
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mov \reg, #0x100000
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3:
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subs \reg, \reg, #0x1
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bne 3b
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.endm
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.text
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.globl crcek
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crcek:
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b crc2_bad
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/* Enable I-cache */
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mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
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mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
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mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
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orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
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mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
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mov r1, #0x00
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mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
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nop
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nop
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nop
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nop
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/* Setup clocking mode */
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ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
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ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
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bic r1, r1, #(7 << 11) @ clear clock select
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orr r1, r1, #(2 << 11) @ set synchronous scalable
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mov r2, #0
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loop:
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cmp r2, #1 @ this loop will wait for at least 100 cycles
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streqh r1, [r0, #0x18] @ before issuing next request from MPU
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add r2, r2, #1 @ on the 1st run code is loaded into I-cache
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cmp r2, #16 @ and second run will set clocking mode
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bne loop
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nop
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/* Setup clock dividers */
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ldr r1, CKCTL_VAL
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orr r1, r1, #0x2000 @ enable DSP clock
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strh r1, [r0] @ setup clock divisors
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/* Setup DPLL to generate requested freq */
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ldr r0, DPLL1_BASE @ base of DPLL1 register
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mov r1, #0x0010 @ set PLL_ENABLE
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orr r1, r1, #0x2000 @ set IOB to new locking
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orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
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orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
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strh r1, [r0] @ write
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locking:
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ldrh r1, [r0] @ get DPLL value
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tst r1, #0x01
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beq locking @ while LOCK not set
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/* Enable clock */
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ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
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mov r1, #(1 << 10) @ disable idle mode do not check
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@ nWAKEUP pin, other remain active
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strh r1, [r0, #0x04]
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ldr r1, EN_CLK_VAL
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strh r1, [r0, #0x08]
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mov r1, #0x003f @ FLASH.RP not enabled in idle and
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strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
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mov r6, #0
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crcuj _LOADER1_OFFSET, _LOADER_SIZE
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bne crc1_bad
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@ -76,9 +131,8 @@ crc1_bad:
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crc2_bad:
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ldr r3, _LOADER1_OFFSET
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ldr r4, _LOADER2_OFFSET
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b boot_2nd
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tst r6, #3
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beq one_is_bad @ one of them (or both) has bad crc
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teq r6, #3
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bne one_is_bad @ one of them (or both) has bad crc
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ldr r1, [r3, #4]
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ldr r2, [r4, #4]
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cmp r1, r2 @ boot 2nd loader if versions differ
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@ -90,6 +144,7 @@ one_is_bad:
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tst r6, #2
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bne boot_2nd
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@ We are doomed, so let user know.
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hell:
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ldr r0, GPIO_BASE @ configure GPIO pins
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ldr r1, GPIO_DIRECTION
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strh r1, [r0, #0x08]
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@ -171,6 +226,15 @@ CRC32_TABLE:
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GPIO_BASE:
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.word 0xfffce000
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MPU_CLKM_BASE:
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.word 0xfffece00
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DPLL1_BASE:
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.word 0xfffecf00
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CKCTL_VAL:
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.word OMAP5910_ARM_CKCTL
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EN_CLK_VAL:
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.word OMAP5910_ARM_EN_CLK
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GPIO_DIRECTION:
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.word 0x0000ffe7
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@ -77,7 +77,7 @@ int main(int argc, char **argv)
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} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
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char *endptr, *nptr = argv[2];
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unsigned ver = strtoul(nptr, &endptr, 0);
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if (nptr != '\0' && endptr == '\0')
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if (*nptr != '\0' && *endptr == '\0')
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return doit(argv[3], ver);
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}
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fprintf(stderr, "Usage: crcit [-v version] <image>\n");
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@ -213,3 +213,4 @@ int eeprom(int argc, char *argv[])
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return 0;
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}
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@ -57,10 +57,11 @@ static int netstar_nand_ready(struct mtd_info *mtd)
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void board_nand_init(struct nand_chip *nand)
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{
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nand->options = NAND_SAMSUNG_LP_OPTIONS;
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nand->options = NAND_SAMSUNG_LP_OPTIONS;
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nand->eccmode = NAND_ECC_SOFT;
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nand->hwcontrol = netstar_nand_hwcontrol;
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nand->hwcontrol = netstar_nand_hwcontrol;
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/* nand->dev_ready = netstar_nand_ready; */
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nand->chip_delay = 18;
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}
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#endif
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@ -27,7 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* arch number of NetStar board */
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/* TODO: use define from asm/mach-types.h */
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gd->bd->bi_arch_number = 692;
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/* adress of boot parameters */
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@ -51,16 +50,13 @@ int dram_init(void)
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return 0;
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}
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extern void partition_flash(void);
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int misc_init_r(void)
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{
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return 0;
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}
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extern void nand_init(void);
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int board_late_init(void)
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{
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return 0;
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}
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@ -58,10 +58,10 @@ VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0
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VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
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#endif
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VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
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VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
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VAL_EMIFF_MRS: .word 0x00000037
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/*
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/*
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* GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
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* GPIO07 - LAN91C111 reset
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*/
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@ -106,7 +106,7 @@ MUX_CONFIG_OFFSETS:
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.align 1
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.byte 0x00 @ FUNC_MUX_CTRL_0
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.byte 0x04 @ FUNC_MUX_CTRL_1
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.byte 0x08 @ FUNC_MUX_CTRL_2
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.byte 0x08 @ FUNC_MUX_CTRL_2
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.byte 0x10 @ FUNC_MUX_CTRL_3
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.byte 0x14 @ FUNC_MUX_CTRL_4
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.byte 0x18 @ FUNC_MUX_CTRL_5
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@ -145,25 +145,23 @@ lowlevel_init:
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nop
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/* Setup clocking mode */
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ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
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ldrh r1, [r0, #0x18] @ get reset status
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ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
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ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
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bic r1, r1, #(7 << 11) @ clear clock select
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orr r1, r1, #(2 << 11) @ set synchronous scalable
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mov r2, #0 @ set wait counter to 100 clock cycles
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icache_loop:
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cmp r2, #0x01
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streqh r1, [r0, #0x18]
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add r2, r2, #0x01
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cmp r2, #0x10
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bne icache_loop
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mov r2, #0
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loop:
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cmp r2, #1 @ this loop will wait for at least 100 cycles
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streqh r1, [r0, #0x18] @ before issuing next request from MPU
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add r2, r2, #1 @ on the 1st run code is loaded into I-cache
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cmp r2, #16 @ and second run will set clocking mode
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bne loop
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nop
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/* Setup clock divisors */
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ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
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/* Setup clock dividers */
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ldr r1, _OMAP5910_ARM_CKCTL
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orr r1, r1, #0x2000 @ enable DSP clock
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strh r1, [r0, #0x00] @ setup clock divisors
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strh r1, [r0] @ setup clock divisors
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/* Setup DPLL to generate requested freq */
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ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
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@ -182,18 +180,17 @@ locking:
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ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
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mov r1, #(1 << 10) @ disable idle mode do not check
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@ nWAKEUP pin, other remain active
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strh r1, [r0, #0x04]
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strh r1, [r0, #0x04]
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ldr r1, _OMAP5910_ARM_EN_CLK
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strh r1, [r0, #0x08]
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mov r1, #0x003f @ FLASH.RP not enabled in idle and
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@ max delayed ( 32 x CLKIN )
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strh r1, [r0, #0x0c]
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strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
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/* Configure 5910 pins functions to match our board. */
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ldr r0, MUX_CONFIG_BASE
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adr r1, MUX_CONFIG_VALUES
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adr r2, MUX_CONFIG_OFFSETS
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next_mux_cfg:
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next_mux_cfg:
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ldrb r3, [r2], #1
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ldr r4, [r1], #4
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cmp r3, #0xff
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@ -240,15 +237,15 @@ next_mux_cfg:
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strh r1, [r0, #0x34]
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/* Setup clock divisors */
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ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
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ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
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mov r1, #0x0010 @ set PLL_ENABLE
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orr r1, r1, #0x2000 @ set IOB to new locking
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strh r1, [r0] @ write
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orr r1, r1, #0x2000 @ set IOB to new locking
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strh r1, [r0] @ write
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ulocking:
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ldrh r1, [r0] @ get DPLL value
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tst r1, #1
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tst r1, #1
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beq ulocking @ while LOCK not set
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/* EMIF init */
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@ -257,7 +254,7 @@ ulocking:
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bic r1, r1, #0x0c @ pwr down disabled, flash WP
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orr r1, r1, #0x01
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str r1, [r0, #0x0c]
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ldr r1, VAL_EMIFS_CS0_CONFIG
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str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
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ldr r1, VAL_EMIFS_CS1_CONFIG
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