From 8ef2d7926f6973707164f4bd8f76bb94e80f336b Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Mon, 6 Nov 2023 08:13:15 +0900 Subject: [PATCH 1/8] clk: starfive: jh7110: Add watchdog clocks Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 watchdog device. Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/starfive/clk-jh7110.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a835541e48..a38694809a 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "i2c5_apb", "apb0", OFFSET(JH7110_SYSCLK_I2C5_APB))); + /* Watchdog clocks */ + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB), + starfive_clk_gate(priv->reg, + "wdt_apb", "apb0", + OFFSET(JH7110_SYSCLK_WDT_APB))); + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE), + starfive_clk_gate(priv->reg, + "wdt_core", "oscillator", + OFFSET(JH7110_SYSCLK_WDT_CORE))); /* enable noc_bus_stg_axi clock */ if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk)) From da264550980aee9d5ed4e6c18d4a4b027c2e242b Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Mon, 6 Nov 2023 08:13:16 +0900 Subject: [PATCH 2/8] watchdog: Add StarFive Watchdog driver Add to support StarFive watchdog driver. The driver is imported from linux kernel's drivers/watchdog/starfive-wdt.c without jh7100 support because there is no support of jh7100 SoC in u-boot yet. Howver, this patch has been kept the variant coding style because JH7100 can be added later and have a consistency with the linux driver. Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- drivers/watchdog/Kconfig | 7 + drivers/watchdog/Makefile | 1 + drivers/watchdog/starfive_wdt.c | 329 ++++++++++++++++++++++++++++++++ 3 files changed, 337 insertions(+) create mode 100644 drivers/watchdog/starfive_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 07fc4940e9..569726119c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -344,6 +344,13 @@ config WDT_STM32MP Enable the STM32 watchdog (IWDG) driver. Enable support to configure STM32's on-SoC watchdog. +config WDT_STARFIVE + bool "StarFive watchdog timer support" + depends on WDT + imply WATCHDOG + help + Enable support for the watchdog timer of StarFive JH7110 SoC. + config WDT_SUNXI bool "Allwinner sunxi watchdog timer support" depends on WDT && ARCH_SUNXI diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index eef786f5e7..5520d3d9ae 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o +obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c new file mode 100644 index 0000000000..ee9ec4cdc3 --- /dev/null +++ b/drivers/watchdog/starfive_wdt.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Starfive Watchdog driver + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include + +/* JH7110 Watchdog register define */ +#define STARFIVE_WDT_JH7110_LOAD 0x000 +#define STARFIVE_WDT_JH7110_VALUE 0x004 +#define STARFIVE_WDT_JH7110_CONTROL 0x008 /* + * [0]: reset enable; + * [1]: interrupt enable && watchdog enable + * [31:2]: reserved. + */ +#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */ +#define STARFIVE_WDT_JH7110_IMS 0x014 +#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */ + +/* WDOGCONTROL */ +#define STARFIVE_WDT_ENABLE 0x1 +#define STARFIVE_WDT_EN_SHIFT 0 +#define STARFIVE_WDT_RESET_EN 0x1 +#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1 + +/* WDOGLOCK */ +#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551 + +/* WDOGINTCLR */ +#define STARFIVE_WDT_INTCLR 0x1 +#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */ + +#define STARFIVE_WDT_MAXCNT 0xffffffff +#define STARFIVE_WDT_DEFAULT_TIME (15) +#define STARFIVE_WDT_DELAY_US 0 +#define STARFIVE_WDT_TIMEOUT_US 10000 + +/* module parameter */ +#define STARFIVE_WDT_EARLY_ENA 0 + +struct starfive_wdt_variant { + unsigned int control; /* Watchdog Control Resgister for reset enable */ + unsigned int load; /* Watchdog Load register */ + unsigned int reload; /* Watchdog Reload Control register */ + unsigned int enable; /* Watchdog Enable Register */ + unsigned int value; /* Watchdog Counter Value Register */ + unsigned int int_clr; /* Watchdog Interrupt Clear Register */ + unsigned int unlock; /* Watchdog Lock Register */ + unsigned int int_status; /* Watchdog Interrupt Status Register */ + + u32 unlock_key; + char enrst_shift; + char en_shift; + bool intclr_check; /* whether need to check it before clearing interrupt */ + char intclr_ava_shift; + bool double_timeout; /* The watchdog need twice timeout to reboot */ +}; + +struct starfive_wdt_priv { + void __iomem *base; + struct clk *core_clk; + struct clk *apb_clk; + struct reset_ctl_bulk *rst; + const struct starfive_wdt_variant *variant; + unsigned long freq; + u32 count; /* count of timeout */ + u32 reload; /* restore the count */ +}; + +/* Register layout and configuration for the JH7110 */ +static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = { + .control = STARFIVE_WDT_JH7110_CONTROL, + .load = STARFIVE_WDT_JH7110_LOAD, + .enable = STARFIVE_WDT_JH7110_CONTROL, + .value = STARFIVE_WDT_JH7110_VALUE, + .int_clr = STARFIVE_WDT_JH7110_INTCLR, + .unlock = STARFIVE_WDT_JH7110_LOCK, + .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY, + .int_status = STARFIVE_WDT_JH7110_IMS, + .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT, + .en_shift = STARFIVE_WDT_EN_SHIFT, + .intclr_check = false, + .double_timeout = true, +}; + +static int starfive_wdt_enable_clock(struct starfive_wdt_priv *wdt) +{ + int ret; + + ret = clk_enable(wdt->apb_clk); + if (ret) + return ret; + + ret = clk_enable(wdt->core_clk); + if (ret) { + clk_disable(wdt->apb_clk); + return ret; + } + + return 0; +} + +static void starfive_wdt_disable_clock(struct starfive_wdt_priv *wdt) +{ + clk_disable(wdt->core_clk); + clk_disable(wdt->apb_clk); +} + +/* Write unlock-key to unlock. Write other value to lock. */ +static void starfive_wdt_unlock(struct starfive_wdt_priv *wdt) +{ + writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); +} + +static void starfive_wdt_lock(struct starfive_wdt_priv *wdt) +{ + writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); +} + +/* enable watchdog interrupt to reset/reboot */ +static void starfive_wdt_enable_reset(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->control); + val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift; + writel(val, wdt->base + wdt->variant->control); +} + +/* waiting interrupt can be free to clear */ +static int starfive_wdt_wait_int_free(struct starfive_wdt_priv *wdt) +{ + u32 value; + + return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value, + !(value & BIT(wdt->variant->intclr_ava_shift)), + STARFIVE_WDT_TIMEOUT_US); +} + +/* clear interrupt signal before initialization or reload */ +static int starfive_wdt_int_clr(struct starfive_wdt_priv *wdt) +{ + int ret; + + if (wdt->variant->intclr_check) { + ret = starfive_wdt_wait_int_free(wdt); + if (ret) + return ret; + } + writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr); + + return 0; +} + +static inline void starfive_wdt_set_count(struct starfive_wdt_priv *wdt, + u32 val) +{ + writel(val, wdt->base + wdt->variant->load); +} + +/* enable watchdog */ +static inline void starfive_wdt_enable(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->enable); + val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift; + writel(val, wdt->base + wdt->variant->enable); +} + +/* disable watchdog */ +static inline void starfive_wdt_disable(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->enable); + val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift); + writel(val, wdt->base + wdt->variant->enable); +} + +static inline void starfive_wdt_set_reload_count(struct starfive_wdt_priv *wdt, + u32 count) +{ + starfive_wdt_set_count(wdt, count); + + /* 7100 need set any value to reload register and could reload value to counter */ + if (wdt->variant->reload) + writel(0x1, wdt->base + wdt->variant->reload); +} + +static int starfive_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + int ret; + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + /* disable watchdog, to be safe */ + starfive_wdt_disable(wdt); + + starfive_wdt_enable_reset(wdt); + ret = starfive_wdt_int_clr(wdt); + if (ret) + goto exit; + + wdt->count = (timeout_ms / 1000) * wdt->freq; + if (wdt->variant->double_timeout) + wdt->count /= 2; + + starfive_wdt_set_count(wdt, wdt->count); + starfive_wdt_enable(wdt); + +exit: + starfive_wdt_lock(wdt); + return ret; +} + +static int starfive_wdt_stop(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + starfive_wdt_disable(wdt); + starfive_wdt_lock(wdt); + + return 0; +} + +static int starfive_wdt_reset(struct udevice *dev) +{ + int ret; + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + ret = starfive_wdt_int_clr(wdt); + if (ret) + goto exit; + + starfive_wdt_set_reload_count(wdt, wdt->count); + +exit: + starfive_wdt_lock(wdt); + + return ret; +} + +static const struct wdt_ops starfive_wdt_ops = { + .start = starfive_wdt_start, + .stop = starfive_wdt_stop, + .reset = starfive_wdt_reset, +}; + +static int starfive_wdt_probe(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + int ret; + + ret = starfive_wdt_enable_clock(wdt); + if (ret) + return ret; + + ret = reset_deassert_bulk(wdt->rst); + if (ret) + goto err_reset; + + wdt->variant = (const struct starfive_wdt_variant *)dev_get_driver_data(dev); + + wdt->freq = clk_get_rate(wdt->core_clk); + if (!wdt->freq) { + ret = -EINVAL; + goto err_get_freq; + } + + return 0; + +err_get_freq: + reset_assert_bulk(wdt->rst); +err_reset: + starfive_wdt_disable_clock(wdt); + + return ret; +} + +static int starfive_wdt_of_to_plat(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + wdt->base = (void *)dev_read_addr(dev); + if (!wdt->base) + return -ENODEV; + + wdt->apb_clk = devm_clk_get(dev, "apb"); + if (IS_ERR(wdt->apb_clk)) + return -ENODEV; + + wdt->core_clk = devm_clk_get(dev, "core"); + if (IS_ERR(wdt->core_clk)) + return -ENODEV; + + wdt->rst = devm_reset_bulk_get(dev); + if (IS_ERR(wdt->rst)) + return -ENODEV; + + return 0; +} + +static const struct udevice_id starfive_wdt_ids[] = { + { + .compatible = "starfive,jh7110-wdt", + .data = (ulong)&starfive_wdt_jh7110_variant + }, { + /* sentinel */ + } +}; + +U_BOOT_DRIVER(starfive_wdt) = { + .name = "starfive_wdt", + .id = UCLASS_WDT, + .of_match = starfive_wdt_ids, + .priv_auto = sizeof(struct starfive_wdt_priv), + .probe = starfive_wdt_probe, + .of_to_plat = starfive_wdt_of_to_plat, + .ops = &starfive_wdt_ops, +}; From a31622cd645f6a159458df8181f86ee3f2798790 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Mon, 6 Nov 2023 08:13:17 +0900 Subject: [PATCH 3/8] riscv: dts: jh7110: Add watchdog device tree node Adds jh7110 watchdog device tree node. Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 13c47f7caa..6d2675d6ce 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -533,6 +533,16 @@ #gpio-cells = <2>; }; + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + mmc0: mmc@16010000 { compatible = "starfive,jh7110-mmc"; reg = <0x0 0x16010000 0x0 0x10000>; From 21ea9a9dd706378d914b387cc9f8ac5a000ce828 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Mon, 6 Nov 2023 08:13:18 +0900 Subject: [PATCH 4/8] configs: visionfive2: Enable watchdog driver Enables StarFive Watchdog driver and WDT command. Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- configs/starfive_visionfive2_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index b15e7d24db..7b39a63359 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -72,6 +72,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y @@ -133,3 +134,7 @@ CONFIG_USB_EHCI_PCI=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_PCI=y CONFIG_USB_KEYBOARD=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_STARFIVE=y From 3980baa41144b979da784cc83d9d3cc9126ca8c6 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 16 Nov 2023 11:22:51 +0100 Subject: [PATCH 5/8] risc-v: qemu: imply NVME_PCI CONFIG_NVME=y without CONFIG_NVME_PCI=y does not provide working NVMe support. Instead of implying CONFIG_NVME we must imply CONFIG_NVME_PCI which will select CONFIG_NVME. Fixes: e64db0d92e32 ("riscv: qemu: Enable e1000 and nvme support") Signed-off-by: Heinrich Schuchardt Reviewed-by: Mark Kettenis --- board/emulation/qemu-riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index d56b4b5bc1..c490dcfeab 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -54,8 +54,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SCSI_AHCI imply AHCI_PCI imply E1000 - imply NVME imply PCI + imply NVME_PCI imply PCIE_ECAM_GENERIC imply DM_RNG imply SCSI From d1b24a61404a2073034dc53a10c64434d706d998 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Thu, 16 Nov 2023 20:46:12 +0800 Subject: [PATCH 6/8] riscv: andes: Fix enable register settings of PLICSW On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin Reviewed-by: Randolph --- arch/riscv/lib/andes_plicsw.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 6a63661312..c09e5c69bc 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -21,41 +21,36 @@ #include /* pending register */ -#define PENDING_REG(base) ((ulong)(base) + 0x1000) +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32)) /* enable register */ -#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) +#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32)) /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) /* priority register */ #define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE) /* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */ -#define FIRST_AVAILABLE_BIT 0x2 -#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart)) #define PLICSW_PRIORITY_BASE 0x4 -#define PLICSW_INTERRUPT_PER_HART 0x1 DECLARE_GLOBAL_DATA_PTR; static int enable_ipi(int hart) { - unsigned int en; + u32 enable_bit = (hart + 1) % 32; - en = FIRST_AVAILABLE_BIT << hart; - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); + writel(BIT(enable_bit), (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); return 0; } static void init_priority_ipi(int hart_num) { - uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw); + u32 *priority = (void *)PRIORITY_REG(gd->arch.plicsw); - for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) { - writel(1, &priority[i]); - } + for (int i = 0; i < hart_num; i++) + writel(1, &priority[i]); - return; + return; } int riscv_init_ipi(void) @@ -104,9 +99,10 @@ int riscv_init_ipi(void) int riscv_send_ipi(int hart) { - unsigned int ipi = SEND_IPI_TO_HART(hart); + u32 interrupt_id = hart + 1; + u32 pending_bit = interrupt_id % 32; - writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw)); + writel(BIT(pending_bit), (void __iomem *)PENDING_REG(gd->arch.plicsw, hart)); return 0; } @@ -123,10 +119,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { - unsigned int ipi = SEND_IPI_TO_HART(hart); + u32 interrupt_id = hart + 1; + u32 pending_bit = interrupt_id % 32; - *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw)); - *pending = !!(*pending & ipi); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, hart)); + *pending = !!(*pending & BIT(pending_bit)); return 0; } From 866dcd88a01f95b313cdd0780ad5fea7d26bc137 Mon Sep 17 00:00:00 2001 From: Randolph Date: Fri, 17 Nov 2023 18:39:50 +0800 Subject: [PATCH 7/8] riscv: binman: fix the load field format Using /bits/ 64 prefix for 64 bits address Signed-off-by: Randolph Reviewed-by: Simon Glass --- arch/riscv/dts/binman.dtsi | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 6b4eb8dc7b..9271de0ddf 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -5,9 +5,6 @@ #include -#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff) -#define U64_TO_U32_L(addr) ((addr) & 0xffffffff) - / { binman: binman { multiple-images; @@ -36,8 +33,7 @@ os = "U-Boot"; arch = "riscv"; compression = "none"; - load = ; + load = /bits/ 64 ; uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; @@ -50,7 +46,7 @@ os = "Linux"; arch = "riscv"; compression = "none"; - load = ; + load = /bits/ 64 ; linux_blob: blob-ext { filename = "Image"; @@ -64,10 +60,8 @@ os = "opensbi"; arch = "riscv"; compression = "none"; - load = ; - entry = ; + load = /bits/ 64 ; + entry = /bits/ 64 ; opensbi_blob: opensbi { filename = "fw_dynamic.bin"; From 94533cd9c15a60b74420e53a725fab54d38dd555 Mon Sep 17 00:00:00 2001 From: John Clark Date: Mon, 20 Nov 2023 02:35:31 +0000 Subject: [PATCH 8/8] starfive: visionfive2: add device tree overlay support device tree overlay support requires fdtoverlay_addr_r to be set before ~~~~~~ Invalid fdtoverlay_addr_r for loading overlays after ~~~~~ Retrieving file: /boot/overlay/rtc-ds3231.dtbo Signed-off-by: John Clark Reviewed-by: Leo Yu-Chi Liang --- include/configs/starfive-visionfive2.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index ff43113f24..29c74470c7 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -40,6 +40,7 @@ "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ "fdt_addr_r=0x46000000\0" \ + "fdtoverlay_addr_r=0x45800000\0" \ "scriptaddr=0x43900000\0" \ "pxefile_addr_r=0x45900000\0" \ "ramdisk_addr_r=0x46100000\0" \