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https://github.com/AsahiLinux/u-boot
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85xx: Reworked initial processor init
Reworked the initial processor initialzation sequence: * introduced cpu_early_init_f that is run in address space 1 (AS=1) * Moved TLB/LAW and CCSR init into cpu_early_init_f() * Reworked initial asm code to do most of the core init before TLBs The main reasons for these changes are to allow handling of 36-bit phys addresses in the future and some of the issues that will exist when we do that. There are a few caveats on what can be initialized via the LAW and TLB static tables: * TLB entry 14/15 can't be initialized via the TLB table * any LAW that covers the implicit boot window (4G-8M to 4G) must map to the code that is currently executing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
44a23cfd63
commit
8716318057
2 changed files with 115 additions and 72 deletions
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@ -31,6 +31,7 @@
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#include <asm/processor.h>
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#include <ioports.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -123,6 +124,54 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
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}
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#endif
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/* We run cpu_init_early_f in AS = 1 */
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void cpu_init_early_f(void)
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{
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set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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1, 0, BOOKE_PAGESZ_4K, 0);
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/* set up CCSR if we want it moved */
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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{
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u32 temp;
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set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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1, 1, BOOKE_PAGESZ_4K, 0);
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temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
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out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12);
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temp = in_be32((volatile u32 *)CFG_CCSRBAR);
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}
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#endif
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init_laws();
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invalidate_tlb(0);
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#ifdef CONFIG_FSL_INIT_TLBS
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init_tlbs();
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#else
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{
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extern u32 tlb1_entry;
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u32 *tmp = &tlb1_entry;
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int i;
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int num = tmp[2];
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/* skip to actual table */
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tmp += 3;
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for (i = 0; i < num; i++, tmp += 4) {
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mtspr(MAS0, tmp[0]);
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mtspr(MAS1, tmp[1]);
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mtspr(MAS2, tmp[2]);
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mtspr(MAS3, tmp[3]);
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asm volatile("isync;msync;tlbwe;isync");
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}
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}
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#endif
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}
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/*
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* Breathe some life into the CPU...
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*
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@ -135,16 +184,15 @@ void cpu_init_f (void)
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volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
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extern void m8560_cpm_reset (void);
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disable_tlb(14);
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disable_tlb(15);
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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#ifdef CONFIG_FSL_LAW
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init_laws();
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#endif
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#ifdef CONFIG_CPM2
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config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
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#endif
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@ -143,67 +143,7 @@ _start_e500:
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li r1,0x0f00
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mtspr IVOR15,r1 /* 15: Debug */
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/*
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* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
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* 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
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* region before we can access any CCSR registers such as L2
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* registers, Local Access Registers,etc. We will also re-allocate
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* CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
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*
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* Please refer to board-specif directory for TLB1 entry configuration.
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* (e.g. board/<yourboard>/init.S)
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*
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*/
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bl tlb1_entry
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mr r5,r0
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lwzu r4,0(r5) /* how many TLB1 entries we actually use */
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mtctr r4
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0: lwzu r6,4(r5)
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lwzu r7,4(r5)
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lwzu r8,4(r5)
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lwzu r9,4(r5)
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mtspr MAS0,r6
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mtspr MAS1,r7
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mtspr MAS2,r8
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mtspr MAS3,r9
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isync
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msync
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tlbwe
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isync
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bdnz 0b
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1:
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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/* Special sequence needed to update CCSRBAR itself */
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lis r4,CFG_CCSRBAR_DEFAULT@h
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ori r4,r4,CFG_CCSRBAR_DEFAULT@l
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lis r5,CFG_CCSRBAR@h
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ori r5,r5,CFG_CCSRBAR@l
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srwi r6,r5,12
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stw r6,0(r4)
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isync
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lis r5,0xffff
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ori r5,r5,0xf000
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lwz r5,0(r5)
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isync
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lis r3,CFG_CCSRBAR@h
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lwz r5,CFG_CCSRBAR@l(r3)
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isync
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#endif
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/* set up local access windows, defined at board/<boardname>/init.S */
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lis r7,CFG_CCSRBAR@h
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ori r7,r7,CFG_CCSRBAR@l
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/* Clear and set up some registers. */
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li r0,0
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mtmsr r0
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li r0,0x0000
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lis r1,0xffff
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mtspr DEC,r0 /* prevent dec exceptions */
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@ -214,18 +154,13 @@ _start_e500:
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mtspr ESR,r0 /* clear exception syndrome register */
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mtspr MCSR,r0 /* machine check syndrome register */
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mtxer r0 /* clear integer exception register */
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lis r1,0x0002 /* set CE bit (Critical Exceptions) */
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ori r1,r1,0x1200 /* set ME/DE bit */
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mtmsr r1 /* change MSR */
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isync
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/* Enable Time Base and Select Time Base Clock */
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lis r0,HID0_EMCP@h /* Enable machine check */
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#if defined(CONFIG_ENABLE_36BIT_PHYS)
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ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */
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#else
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ori r0,r0,HID0_TBEN@l /* enable Timebase */
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ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
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#endif
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ori r0,r0,HID0_TBEN@l /* Enable Timebase */
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mtspr HID0,r0
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li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
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@ -246,6 +181,58 @@ _start_e500:
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mtspr DBCR0,r0
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#endif
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/* create a temp mapping in AS=1 to the boot window */
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lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
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ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
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lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
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ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
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lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
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ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
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lis r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
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ori r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
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mtspr MAS0,r6
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mtspr MAS1,r7
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mtspr MAS2,r8
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mtspr MAS3,r9
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isync
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msync
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tlbwe
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/* create a temp mapping in AS=1 to the stack */
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lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
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ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
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lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
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ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
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lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h
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ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l
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lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
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ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
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mtspr MAS0,r6
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mtspr MAS1,r7
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mtspr MAS2,r8
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mtspr MAS3,r9
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isync
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msync
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tlbwe
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lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h
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ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l
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lis r7,switch_as@h
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ori r7,r7,switch_as@l
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mtspr SPRN_SRR0,r7
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mtspr SPRN_SRR1,r6
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rfi
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switch_as:
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/* L1 DCache is used for initial RAM */
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/* Allocate Initial RAM in data cache.
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@ -305,6 +292,14 @@ _start_cont:
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stw r0,+12(r1) /* Save return addr (underflow vect) */
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GET_GOT
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bl cpu_init_early_f
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/* switch back to AS = 0 */
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lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
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ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
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mtmsr r3
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isync
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bl cpu_init_f
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bl board_init_f
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isync
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