Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-14 17:07:38 +00:00
Code Issues Projects Releases Packages Wiki Activity

clk: renesas: Synchronize R8A77970 V3M clock tables with Linux 6.5.3

Browse source 
Synchronize R-Car R8A77970 V3M clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2023-09-17 16:11:31 +02:00
parent e2c11b3c18
commit 86d2d706df
1 changed files with 9 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
drivers/clk/renesas/r8a77970-cpg-mssr.c
View file

@ -1,13 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas R8A77970 CPG MSSR driver
* r8a77970 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
* Copyright (C) 2017-2018 Cogent Embedded Inc.
*
* Based on the following driver from Linux kernel:
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
* Based on r8a7795-cpg-mssr.c
*
* Copyright (C) 2016 Glider bvba
* Copyright (C) 2015 Glider bvba
*/
#include <common.h>
@ -42,7 +41,7 @@ enum clk_ids {
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a77970_core_clks[] = {
static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@ -57,6 +56,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] = {
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1),
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@ -87,7 +87,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] = {
DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
};
static const struct mssr_mod_clk r8a77970_mod_clks[] = {
static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
@ -166,7 +166,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 192, 1, 96, 1, },
{ 1, 192, 1, 80, 1, },