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x86: coreboot: Add default TSC frequency in the device tree

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It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
This commit is contained in:
Bin Meng 2018-08-10 02:39:37 -07:00
parent 165db7c426
commit 864915561b
1 changed files with 4 additions and 0 deletions
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4
arch/x86/dts/coreboot.dts
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@ -30,6 +30,10 @@
stdout-path = "/serial"; stdout-path = "/serial";
}; };
tsc-timer {
clock-frequency = <1000000000>;
};
pci { pci {
compatible = "pci-x86"; compatible = "pci-x86";
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;