mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
8466647684
7 changed files with 31 additions and 45 deletions
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@ -34,6 +34,7 @@
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <ppc440.h>
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#include <watchdog.h>
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@ -59,7 +60,6 @@
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extern int denali_wait_for_dlllock(void);
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extern void denali_core_search_data_eye(void);
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extern void dcbz_area(u32 start_address, u32 num_bytes);
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extern void dflush(void);
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static u32 is_ecc_enabled(void)
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{
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@ -106,6 +106,7 @@ static void program_ecc(u32 start_address,
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{
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u32 val;
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u32 current_addr = start_address;
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u32 size;
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int bytes_remaining;
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sync();
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@ -123,12 +124,18 @@ static void program_ecc(u32 start_address,
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* watchdog.
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*/
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while (bytes_remaining > 0) {
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dcbz_area(current_addr, min((64 << 20), bytes_remaining));
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size = min((64 << 20), bytes_remaining);
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/* Write zero's to SDRAM */
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dcbz_area(current_addr, size);
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/* Write modified dcache lines back to memory */
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clean_dcache_range(current_addr, current_addr + size);
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current_addr += 64 << 20;
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bytes_remaining -= 64 << 20;
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WATCHDOG_RESET();
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}
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dflush();
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sync();
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wait_ddr_idle();
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@ -34,11 +34,11 @@
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <ppc440.h>
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void hcu_led_set(u32 value);
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void dcbz_area(u32 start_address, u32 num_bytes);
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void dflush(void);
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#define DDR_DCR_BASE 0x10
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#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
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@ -185,14 +185,14 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
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#endif
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sync();
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eieio();
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puts(str);
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/* ECC bit set method for cached memory */
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/* Fast method, no noticeable delay */
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dcbz_area(start_address, num_bytes);
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dflush();
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/* Write modified dcache lines back to memory */
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clean_dcache_range(start_address, start_address + num_bytes);
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blank_string(strlen(str));
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/* Clear error status */
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@ -40,6 +40,7 @@
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#if defined(CONFIG_SPD_EEPROM) && \
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(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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@ -237,7 +238,6 @@ static void DQS_calibration_process(void);
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static void ppc440sp_sdram_register_dump(void);
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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void dcbz_area(u32 start_address, u32 num_bytes);
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void dflush(void);
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static u32 mfdcr_any(u32 dcr)
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{
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@ -2355,7 +2355,8 @@ static void program_ecc_addr(unsigned long start_address,
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} else {
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/* ECC bit set method for cached memory */
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dcbz_area(start_address, num_bytes);
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dflush();
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/* Write modified dcache lines back to memory */
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clean_dcache_range(start_address, start_address + num_bytes);
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}
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blank_string(strlen(str));
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@ -45,6 +45,7 @@
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#if defined(CONFIG_SPD_EEPROM) && \
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(defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
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@ -92,7 +93,6 @@
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extern int denali_wait_for_dlllock(void);
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extern void denali_core_search_data_eye(void);
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extern void dcbz_area(u32 start_address, u32 num_bytes);
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extern void dflush(void);
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/*
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* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
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@ -1201,7 +1201,8 @@ long int initdram(int board_type)
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#else
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#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
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#endif
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dflush();
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/* Write modified dcache lines back to memory */
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clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
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debug("Completed\n");
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sync();
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remove_tlb(CFG_SDRAM_BASE, dram_size);
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@ -83,8 +83,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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bd->bi_intfreq, 1);
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do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
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do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
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do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
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sys_info.freqEBC, 1);
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if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
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do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
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sys_info.freqEBC, 1);
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else
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do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
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sys_info.freqEBC, 1);
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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/*
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@ -1675,35 +1675,6 @@ trap_reloc:
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sync
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blr
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function_epilog(dcbz_area)
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/*----------------------------------------------------------------------------+
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| dflush. Assume 32K at vector address is cachable.
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+----------------------------------------------------------------------------*/
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function_prolog(dflush)
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mfmsr r9
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rlwinm r8,r9,0,15,13
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rlwinm r8,r8,0,17,15
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mtmsr r8
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mfspr r8,dvlim
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addi r3,r0,0x0000
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mtspr dvlim,r3
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mfspr r3,ivpr
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addi r4,r0,1024
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mtctr r4
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..dflush_loop:
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lwz r6,0x0(r3)
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addi r3,r3,32
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bdnz ..dflush_loop
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addi r3,r3,-32
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mtctr r4
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..ag: dcbf r0,r3
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addi r3,r3,-32
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bdnz ..ag
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mtspr dvlim,r8
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sync
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mtmsr r9
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blr
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function_epilog(dflush)
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#endif /* CONFIG_440 */
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#endif /* CONFIG_NAND_SPL */
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@ -48,12 +48,8 @@
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
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#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
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@ -82,6 +78,10 @@
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#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_LEN + 1)
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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