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Merge branch 'master' of git://git.denx.de/u-boot-sh

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This commit is contained in:
Tom Rini 2018-10-19 07:12:46 -04:00
commit 83c18d4101
20 changed files with 106 additions and 170 deletions
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16
arch/arm/dts/Makefile
View file

@ -455,14 +455,14 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
r8a7796-m3ulcb.dtb \
r8a7796-salvator-x.dtb \
r8a77965-salvator-x.dtb \
r8a77970-eagle.dtb \
r8a77990-ebisu.dtb \
r8a77995-draak.dtb
r8a7795-h3ulcb-u-boot.dtb \
r8a7795-salvator-x-u-boot.dtb \
r8a7796-m3ulcb-u-boot.dtb \
r8a7796-salvator-x-u-boot.dtb \
r8a77965-salvator-x-u-boot.dtb \
r8a77970-eagle-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \

16
arch/arm/dts/r8a77990-ebisu.dts
View file

@ -65,6 +65,10 @@
};
};
&ehci0 {
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
@ -101,6 +105,18 @@
function = "sdhi3";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-name = "default";
status = "okay";
};
&sdhi0 {

38
arch/arm/dts/r8a77990.dtsi
View file

@ -7,6 +7,7 @@
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77990-sysc.h>
/ {
compatible = "renesas,r8a77990";
@ -165,6 +166,43 @@
resets = <&cpg 906>;
};
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
usb2_phy0: usb-phy@ee080200 {
compatible = "renesas,usb2-phy-r8a7790",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled";
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77990";
reg = <0 0xe6060000 0 0x508>;

1
arch/arm/mach-rmobile/Kconfig
View file

@ -12,6 +12,7 @@ config RCAR_GEN3
bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
select ARM64
select PHY
select CMD_CACHE
endchoice

61
arch/arm/mach-rmobile/cpu_info-rcar.c
View file

@ -11,7 +11,14 @@
#define R8A7796_REV_1_0 0x5200
#define R8A7796_REV_1_1 0x5210
static u32 rmobile_get_prr(void);
static u32 rmobile_get_prr(void)
{
#ifdef CONFIG_RCAR_GEN3
return readl(0xFFF00044);
#else
return readl(0xFF000044);
#endif
}
u32 rmobile_get_cpu_type(void)
{
@ -37,55 +44,3 @@ u32 rmobile_get_cpu_rev_fraction(void)
else
return prr & 0x0000000F;
}
#if !CONFIG_IS_ENABLED(DM) || !CONFIG_IS_ENABLED(SYSCON)
static u32 rmobile_get_prr(void)
{
/*
* On RCar/RMobile Gen2 and older systems, the PRR is always
* located at the address below. On newer systems, the PRR
* may be located at different address, but that information
* is obtained from DT. This code will be removed when all
* of the older systems get converted to DM and OF control.
*/
return readl(0xFF000044);
}
#else
#include <dm.h>
#include <syscon.h>
#include <regmap.h>
struct renesas_prr_priv {
fdt_addr_t regs;
};
enum {
PRR_RCAR,
};
static u32 rmobile_get_prr(void)
{
struct regmap *map;
map = syscon_get_regmap_by_driver_data(PRR_RCAR);
if (!map) {
printf("PRR regmap failed!\n");
hang();
}
return readl(map->ranges[0].start);
}
static const struct udevice_id renesas_prr_ids[] = {
{ .compatible = "renesas,prr", .data = PRR_RCAR },
{ }
};
U_BOOT_DRIVER(renesas_prr) = {
.name = "renesas_prr",
.id = UCLASS_SYSCON,
.of_match = renesas_prr_ids,
.flags = DM_FLAG_PRE_RELOC,
};
#endif

28
board/renesas/draak/draak.c
View file

@ -26,48 +26,24 @@
DECLARE_GLOBAL_DATA_PTR;
#define CPGWPCR 0xE6150904
#define CPGWPR 0xE615090C
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
writel(0xA5A50000, CPGWPCR);
writel(0xFFFFFFFF, CPGWPR);
}
#define GSX_MSTP112 BIT(12) /* 3DG */
#define TMU0_MSTP125 BIT(25) /* secure */
#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
/* TMU0,1 */ /* which use ? */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define SYSC_PWRSR2 0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define SYSC_PWRONCR2 0xE618010C
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
@ -84,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);

5
board/renesas/eagle/eagle.c
View file

@ -50,17 +50,12 @@ void s_init(void)
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}
#define TMU0_MSTP125 BIT(25) /* secure */
int board_early_init_f(void)
{
/* Unlock CPG access */
writel(0xA5A5FFFF, CPGWPR);
writel(0x5A5A0000, CPGWPCR);
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
return 0;
}

5
board/renesas/ebisu/ebisu.c
View file

@ -30,13 +30,8 @@ void s_init(void)
{
}
#define TMU0_MSTP125 BIT(25) /* secure */
int board_early_init_f(void)
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
return 0;
}

40
board/renesas/salvator-x/salvator-x.c
View file

@ -27,48 +27,23 @@
DECLARE_GLOBAL_DATA_PTR;
#define CPGWPCR 0xE6150904
#define CPGWPR 0xE615090C
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
writel(0xA5A50000, CPGWPCR);
writel(0xFFFFFFFF, CPGWPR);
}
#define GSX_MSTP112 BIT(12) /* 3DG */
#define TMU0_MSTP125 BIT(25) /* secure */
#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
/* TMU0,1 */ /* which use ? */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define SYSC_PWRSR2 0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define SYSC_PWRONCR2 0xE618010C
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
@ -78,25 +53,14 @@ int board_early_init_f(void)
int board_init(void)
{
u32 cpu_type = rmobile_get_cpu_type();
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
/* GSX: force power and clock supply */
writel(0x0000001F, SYSC_PWRONCR2);
while (readl(SYSC_PWRSR2) != 0x000003E0)
mdelay(20);
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
}
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);

28
board/renesas/ulcb/ulcb.c
View file

@ -26,48 +26,24 @@
DECLARE_GLOBAL_DATA_PTR;
#define CPGWPCR 0xE6150904
#define CPGWPR 0xE615090C
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
writel(0xA5A50000, CPGWPCR);
writel(0xFFFFFFFF, CPGWPR);
}
#define GSX_MSTP112 BIT(12) /* 3DG */
#define TMU0_MSTP125 BIT(25) /* secure */
#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
/* TMU0,1 */ /* which use ? */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define SYSC_PWRSR2 0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define SYSC_PWRONCR2 0xE618010C
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
@ -84,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);

3
configs/r8a7795_salvator-x_defconfig
View file

@ -8,7 +8,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
@ -21,6 +21,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y

2
configs/r8a7795_ulcb_defconfig
View file

@ -8,7 +8,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y

2
configs/r8a77965_salvator-x_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77965-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y

2
configs/r8a7796_salvator-x_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y

2
configs/r8a7796_ulcb_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y

2
configs/r8a77970_eagle_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
CONFIG_VERSION_VARIABLE=y

2
configs/r8a77990_ebisu_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200"
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
CONFIG_VERSION_VARIABLE=y

2
configs/r8a77995_draak_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
CONFIG_VERSION_VARIABLE=y

1
include/configs/draak.h
View file

@ -33,6 +33,5 @@
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#define CONFIG_CMD_CACHE
#endif /* __DRAAK_H */

20
include/dt-bindings/power/r8a77990-sysc.h Normal file
View file

@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77990_PD_CA53_CPU0 5
#define R8A77990_PD_CA53_SCU 21
/* Always-on power area */
#define R8A77990_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */