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- Enable the fastboot oem commands in stm32mp15 defconfig

Browse source 
- Fixes pinctrol for stmfx and stm32
 - Add support of I2C6_K in stm32mp15 clock driver
 - Alignment with Linux kernel device tree v5.11-rc2 for ST boards
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Merge tag 'u-boot-stm32-20210209' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Enable the fastboot oem commands in stm32mp15 defconfig
- Fixes pinctrol for stmfx and stm32
- Add support of I2C6_K in stm32mp15 clock driver
- Alignment with Linux kernel device tree v5.11-rc2 for ST boards
This commit is contained in:
Tom Rini 2021-02-09 17:06:44 -05:00
commit 8398d95ec2
16 changed files with 249 additions and 93 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
View file

@ -15,7 +15,7 @@
* Save Date: 2020.02.20, save Time: 18:45:20
*/
#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000

2
arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
View file

@ -15,7 +15,7 @@
* Save Date: 2020.02.20, save Time: 18:49:33
*/
#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz
#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz"
#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000

87
arch/arm/dts/stm32mp15-pinctrl.dtsi
View file

@ -349,6 +349,61 @@
};
};
fmc_pins_b: fmc-1 {
pins {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
<STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
<STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
<STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
<STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
<STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
<STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
<STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
<STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
<STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
<STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
<STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
fmc_sleep_pins_b: fmc-sleep-1 {
pins {
pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
<STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
<STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
<STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
<STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
<STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
<STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
<STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
<STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
<STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
<STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
<STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
<STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
<STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
<STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
<STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
<STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
<STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
<STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
<STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@ -1437,6 +1492,24 @@
};
};
sdmmc2_d47_pins_d: sdmmc2-d47-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
};
};
sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
<STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
};
};
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
@ -1588,9 +1661,9 @@
};
stusb1600_pins_a: stusb1600-0 {
pins {
pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
bias-pull-up;
pins {
pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
bias-pull-up;
};
};
@ -1721,6 +1794,14 @@
};
};
uart8_rtscts_pins_a: uart8rtscts-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
<STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
bias-disable;
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */

48
arch/arm/dts/stm32mp151.dtsi
View file

@ -41,6 +41,13 @@
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
interrupt-parent = <&intc>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -373,8 +380,10 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x40009000 0x400>;
interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
@ -1010,7 +1019,7 @@
dmamux1: dma-router@48002000 {
compatible = "st,stm32h7-dmamux";
reg = <0x48002000 0x1c>;
reg = <0x48002000 0x40>;
#dma-cells = <3>;
dma-requests = <128>;
dma-masters = <&dma1 &dma2>;
@ -1058,7 +1067,7 @@
sdmmc3: sdmmc@48004000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
@ -1079,9 +1088,9 @@
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
g-rx-fifo-size = <256>;
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
usb33d-supply = <&usb33>;
status = "disabled";
@ -1117,7 +1126,7 @@
resets = <&rcc CAMITF_R>;
clocks = <&rcc DCMI>;
clock-names = "mclk";
dmas = <&dmamux1 75 0x400 0x0d>;
dmas = <&dmamux1 75 0x400 0x01>;
dma-names = "tx";
status = "disabled";
};
@ -1175,8 +1184,10 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50021000 0x400>;
interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
@ -1202,8 +1213,10 @@
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50022000 0x400>;
interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
@ -1222,8 +1235,10 @@
lptimer4: timer@50023000 {
compatible = "st,stm32-lptimer";
reg = <0x50023000 0x400>;
interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
@ -1236,8 +1251,10 @@
lptimer5: timer@50024000 {
compatible = "st,stm32-lptimer";
reg = <0x50024000 0x400>;
interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
@ -1303,7 +1320,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
status = "disabled";
@ -1367,8 +1384,8 @@
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
<&mdma1 22 0x10 0x100008 0x0 0x0>;
dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
<&mdma1 22 0x2 0x100008 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
@ -1379,7 +1396,7 @@
sdmmc1: sdmmc@58005000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
@ -1394,7 +1411,7 @@
sdmmc2: sdmmc@58007000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
@ -1445,7 +1462,7 @@
status = "disabled";
};
usbh_ohci: usbh-ohci@5800c000 {
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
clocks = <&rcc USBH>;
@ -1454,7 +1471,7 @@
status = "disabled";
};
usbh_ehci: usbh-ehci@5800d000 {
usbh_ehci: usb@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&rcc USBH>;
@ -1587,6 +1604,11 @@
status = "disabled";
};
tamp: tamp@5c00a000 {
compatible = "st,stm32-tamp", "syscon", "simple-mfd";
reg = <0x5c00a000 0x400>;
};
/*
* Break node order to solve dependency probe issue between
* pinctrl and exti.
@ -1765,6 +1787,8 @@
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
status = "disabled";
};
};

6
arch/arm/dts/stm32mp153.dtsi
View file

@ -16,6 +16,12 @@
};
};
arm-pmu {
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";

4
arch/arm/dts/stm32mp157c-dk2.dts
View file

@ -29,6 +29,10 @@
};
};
&cryp1 {
status = "okay";
};
&dsi {
status = "okay";
phy-dsi-supply = <&reg18>;

27
arch/arm/dts/stm32mp157c-ed1.dts
View file

@ -89,6 +89,14 @@
states = <1800000 0x1>,
<2900000 0x0>;
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&adc {
@ -115,6 +123,14 @@
cpu-supply = <&vddcore>;
};
&crc1 {
status = "okay";
};
&cryp1 {
status = "okay";
};
&dac {
pinctrl-names = "default";
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
@ -136,6 +152,10 @@
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};
&i2c4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_pins_a>;
@ -158,11 +178,18 @@
regulators {
compatible = "st,stpmic1-regulators";
buck1-supply = <&vin>;
buck2-supply = <&vin>;
buck3-supply = <&vin>;
buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo4-supply = <&vin>;
ldo5-supply = <&v3v3>;
ldo6-supply = <&v3v3>;
vref_ddr-supply = <&vin>;
boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;

1
arch/arm/dts/stm32mp157c-ev1.dts
View file

@ -90,6 +90,7 @@
port {
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
bus-type = <5>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;

55
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View file

@ -76,61 +76,6 @@
pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
fmc_pins_b: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
<STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
<STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
<STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
<STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
<STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
<STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
<STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
<STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
<STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
<STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
<STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
fmc_sleep_pins_b: fmc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
<STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
<STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
<STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
<STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
<STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
<STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
<STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
<STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
<STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
<STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
<STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
<STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
<STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
<STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
<STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
<STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
<STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
<STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
<STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
};
};
mco2_pins_a: mco2-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */

47
arch/arm/dts/stm32mp15xx-dkx.dtsi
View file

@ -80,6 +80,14 @@
dais = <&sai2a_port &sai2b_port &i2s2_port>;
status = "okay";
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&adc {
@ -116,6 +124,10 @@
status = "okay";
};
&crc1 {
status = "okay";
};
&dts {
status = "okay";
};
@ -151,6 +163,10 @@
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
@ -238,21 +254,27 @@
/delete-property/dmas;
/delete-property/dma-names;
typec: stusb1600@28 {
stusb1600@28 {
compatible = "st,stusb1600";
reg = <0x28>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpioi>;
pinctrl-names = "default";
pinctrl-0 = <&stusb1600_pins_a>;
status = "okay";
vdd-supply = <&vin>;
typec_con: connector {
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "sink";
power-opmode = "default";
power-role = "dual";
typec-power-opmode = "default";
port {
con_usbotg_hs_ep: endpoint {
remote-endpoint = <&usbotg_hs_ep>;
};
};
};
};
@ -266,9 +288,18 @@
regulators {
compatible = "st,stpmic1-regulators";
buck1-supply = <&vin>;
buck2-supply = <&vin>;
buck3-supply = <&vin>;
buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&vin>;
ldo3-supply = <&vdd_ddr>;
ldo4-supply = <&vin>;
ldo5-supply = <&vin>;
ldo6-supply = <&v3v3>;
vref_ddr-supply = <&vin>;
boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
@ -657,6 +688,12 @@
phy-names = "usb2-phy";
usb-role-switch;
status = "okay";
port {
usbotg_hs_ep: endpoint {
remote-endpoint = <&con_usbotg_hs_ep>;
};
};
};
&usbphyc {

8
configs/stm32mp15_basic_defconfig
View file

@ -79,6 +79,14 @@ CONFIG_FASTBOOT_BUF_SIZE=0x02000000
CONFIG_FASTBOOT_USB_DEV=1
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y

8
configs/stm32mp15_trusted_defconfig
View file

@ -58,6 +58,14 @@ CONFIG_FASTBOOT_BUF_SIZE=0x02000000
CONFIG_FASTBOOT_USB_DEV=1
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0"
CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1"
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
CONFIG_FASTBOOT_MMC_USER_NAME="mmc1"
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y

1
drivers/clk/clk_stm32mp1.c
View file

@ -549,6 +549,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),

11
drivers/pinctrl/pinctrl-stmfx.c
View file

@ -343,18 +343,17 @@ static int stmfx_pinctrl_get_pins_count(struct udevice *dev)
}
/*
* STMFX pins[15:0] are called "stmfx_gpio[15:0]"
* and STMFX pins[23:16] are called "stmfx_agpio[7:0]"
* STMFX pins[15:0] are called "gpio[15:0]"
* and STMFX pins[23:16] are called "agpio[7:0]"
*/
#define MAX_PIN_NAME_LEN 7
static char pin_name[MAX_PIN_NAME_LEN];
static char pin_name[PINNAME_SIZE];
static const char *stmfx_pinctrl_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < STMFX_MAX_GPIO)
snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_gpio%u", selector);
snprintf(pin_name, PINNAME_SIZE, "gpio%u", selector);
else
snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_agpio%u", selector - 16);
snprintf(pin_name, PINNAME_SIZE, "agpio%u", selector - 16);
return pin_name;
}

21
drivers/pinctrl/pinctrl_stm32.c
View file

@ -56,7 +56,7 @@ static const char * const pinmux_bias[] = {
[STM32_GPIO_PUPD_DOWN] = "pull-down",
};
static const char * const pinmux_input[] = {
static const char * const pinmux_otype[] = {
[STM32_GPIO_OTYPE_PP] = "push-pull",
[STM32_GPIO_OTYPE_OD] = "open-drain",
};
@ -216,7 +216,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
selector, gpio_idx, mode);
priv = dev_get_priv(gpio_dev);
pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
switch (mode) {
case GPIOF_UNKNOWN:
@ -227,18 +227,16 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num,
pinmux_bias[pupd]);
snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
pinmux_otype[otype], pinmux_bias[pupd]);
break;
case GPIOF_OUTPUT:
snprintf(buf, size, "%s %s %s",
pinmux_mode[mode], pinmux_bias[pupd],
label ? label : "");
snprintf(buf, size, "%s %s %s %s",
pinmux_mode[mode], pinmux_otype[otype],
pinmux_bias[pupd], label ? label : "");
break;
case GPIOF_INPUT:
otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
snprintf(buf, size, "%s %s %s %s",
pinmux_mode[mode], pinmux_input[otype],
snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
pinmux_bias[pupd], label ? label : "");
break;
}
@ -411,6 +409,9 @@ static int stm32_pinctrl_bind(struct udevice *dev)
dev_for_each_subnode(node, dev) {
dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
if (!ofnode_is_enabled(node))
continue;
ofnode_get_property(node, "gpio-controller", &ret);
if (ret < 0)
continue;

14
include/configs/stm32mp1.h
View file

@ -132,6 +132,19 @@
"run distro_bootcmd;" \
"fi;\0"
#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT
/* eMMC default partitions for fastboot command: oem format */
#define PARTS_DEFAULT \
"partitions=" \
"name=ssbl,size=2M;" \
"name=bootfs,size=64MB,bootable;" \
"name=vendorfs,size=16M;" \
"name=rootfs,size=746M;" \
"name=userfs,size=-\0"
#else
#define PARTS_DEFAULT
#endif
#include <config_distro_bootcmd.h>
/*
@ -150,6 +163,7 @@
"altbootcmd=run bootcmd\0" \
"env_check=if env info -p -d -q; then env save; fi\0" \
STM32MP_BOOTCMD \
PARTS_DEFAULT \
BOOTENV \
"boot_net_usb_start=true\0"