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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-tegra

Browse source 
- Assorted updates
This commit is contained in:
Tom Rini 2020-12-05 15:41:18 -05:00
commit 837d034d9a
16 changed files with 73 additions and 21 deletions
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1
arch/arm/mach-tegra/tegra124/Kconfig
View file

@ -19,6 +19,7 @@ config TARGET_JETSON_TK1
config TARGET_CEI_TK1_SOM
bool "Colorado Engineering Inc Tegra124 TK1-som board"
select ARCH_SUPPORT_PSCI
select BOARD_LATE_INIT
select CPU_V7_HAS_NONSEC if !SPL_BUILD
select CPU_V7_HAS_VIRT if !SPL_BUILD

11
board/toradex/apalis_t30/pinmux-config-apalis_t30.h
View file

@ -11,7 +11,9 @@
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
/* TRISTATE here means output driver is tri-stated */ \
.tristate = PMUX_TRI_##_tri, \
/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_DEFAULT, \
.od = PMUX_PIN_OD_DEFAULT, \
@ -118,7 +120,8 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
/* UARTD RX, make sure we don't get input form a floating Pin */
DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
@ -187,12 +190,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
/* UARTB RX, make sure we don't get input form a floating Pin */
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
/* UARTC RX, make sure we don't get input form a floating Pin */
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT),

11
board/toradex/colibri_t30/colibri_t30.c
View file

@ -57,6 +57,17 @@ void pinmux_init(void)
ARRAY_SIZE(colibri_t30_padctrl));
}
/*
* Disable RS232 serial transceiver ForceOFF# pins on Iris
*/
void gpio_early_init_uart(void)
{
gpio_request(TEGRA_GPIO(X, 6), "Force OFF# X13");
gpio_direction_output(TEGRA_GPIO(X, 6), 1);
gpio_request(TEGRA_GPIO(X, 7), "Force OFF# X14");
gpio_direction_output(TEGRA_GPIO(X, 7), 1);
}
/*
* Enable AX88772B USB to LAN controller
*/

32
board/toradex/colibri_t30/pinmux-config-colibri_t30.h
View file

@ -11,7 +11,9 @@
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
/* TRISTATE here means output driver is tri-stated */ \
.tristate = PMUX_TRI_##_tri, \
/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_DEFAULT, \
.od = PMUX_PIN_OD_DEFAULT, \
@ -178,14 +180,16 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
/* UARTC RX, make sure we don't get input form a floating Pin */
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT),
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_TXD_PW6, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_RXD_PW7, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_CTS_N_PA1, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
@ -204,11 +208,11 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
/* UARTB RX, make sure we don't get input form a floating Pin */
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, UP, NORMAL, INPUT),
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT),
/* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT),
DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
@ -268,10 +272,10 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_MOSI_PX4, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_SCK_PX5, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, INPUT),
/* LAN_RESET */
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT),

1
configs/cei-tk1-som_defconfig
View file

@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_TEGRA124=y
CONFIG_TARGET_CEI_TK1_SOM=y
CONFIG_ARMV7_PSCI_0_1=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y

2
include/config_distro_bootcmd.h
View file

@ -118,8 +118,10 @@
"setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \
"fi; "
#else
#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK
#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
#endif
#endif
#define BOOTENV_SHARED_EFI \

9
include/configs/apalis_t30.h
View file

@ -12,7 +12,14 @@
#include "tegra30-common.h"
/* Board-specific serial config */
/*
* Board-specific serial config
*
* Apalis UART1: NVIDIA UARTA
* Apalis UART2: NVIDIA UARTD
* Apalis UART3: NVIDIA UARTB
* Apalis UART4: NVIDIA UARTC
*/
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE

2
include/configs/cei-tk1-som.h
View file

@ -28,8 +28,6 @@
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#define CONFIG_ARMV7_PSCI 1
#define CONFIG_ARMV7_PSCI_NR_CPUS 4
/* Reserve top 1M for secure RAM */
#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000

8
include/configs/colibri_t30.h
View file

@ -14,7 +14,13 @@
/* High-level configuration options */
/* Board-specific serial config */
/*
* Board-specific serial config
*
* Colibri UART-A: NVIDIA UARTA
* Colibri UART-B: NVIDIA UARTD
* Colibri UART-C: NVIDIA UARTB
*/
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE

6
include/configs/tegra-common.h
View file

@ -49,6 +49,12 @@
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#ifdef CONFIG_ARM64
#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
#else
#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/

1
include/configs/tegra114-common.h
View file

@ -50,6 +50,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"

1
include/configs/tegra124-common.h
View file

@ -52,6 +52,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"

6
include/configs/tegra186-common.h
View file

@ -20,6 +20,12 @@
/* Generic Interrupt Controller */
#define CONFIG_GICV2
#undef FDTFILE
#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \
"setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \
"fi; "
/*
* Memory layout for where various images get loaded by boot scripts:
*

1
include/configs/tegra20-common.h
View file

@ -51,6 +51,7 @@
"scriptaddr=0x10000000\0" \
"pxefile_addr_r=0x10100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x03000000\0" \
"ramdisk_addr_r=0x03100000\0"

1
include/configs/tegra210-common.h
View file

@ -46,6 +46,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83200000\0"

1
include/configs/tegra30-common.h
View file

@ -47,6 +47,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"