diff --git a/CHANGELOG b/CHANGELOG index 9f8c7cd477..d4cd8f121c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,460 @@ +commit 8e64d6efd8d778a5f83d8bff9cd273a86dcc182f +Author: Heiko Schocher +Date: Wed Mar 31 08:34:51 2010 +0200 + + net, doc: How to setup MAC address correctly + + As this seems unclear, document how the flow of setting up + the MAC address is correct. + + Signed-off-by: Heiko Schocher + + Text changed slightly, adding input from Mike Frysinger. + + Signed-off-by: Wolfgang Denk + +commit b78b48c6a0c34b2991e31fc4548aaf773d34f2b3 +Author: Heiko Schocher +Date: Wed Mar 31 08:34:46 2010 +0200 + + net, fec_mxc: only setup the device enetaddr with eeprom value + + Only fill the device enetaddr with the contents of the eeprom, + do not program it in MAC address registers + + Signed-off-by: Heiko Schocher + Acked-by: Ben Warren + +commit d5a64237d58ded31c2eed455c7a346e1c85f5565 +Author: Felix Radensky +Date: Tue Mar 30 15:02:13 2010 +0300 + + doc: Fix ramdisk examples in doc/uImage.FIT/multi.its + + The ramdisk sections in doc/uImage.FIT/multi.its lack + load address and entry point properties. Using examples + from this file will result in unbootable image, u-boot + will issue the following error messages: + + Can't get ramdisk subimage load address! + Ramdisk image is corrupt or invalid + + This patch adds missing properties to ramdisk sections. + + Signed-off-by: Felix Radensky + +commit 2d2018f3db5ed834bc1ee208a2c6212fdf00bca1 +Author: Heiko Schocher +Date: Wed Mar 24 13:22:50 2010 +0100 + + jffs2, suen3: Fix compiler warning + + $ ./MAKEALL suen3 + jffs2_1pass.c: In function 'get_fl_mem': + jffs2_1pass.c:399: warning: unused variable 'id' + jffs2_1pass.c: In function 'get_node_mem': + jffs2_1pass.c:423: warning: unused variable 'id' + + Signed-off-by: Heiko Schocher + Tested-by: Tom + +commit 9ff32d8ccf0e23b5577c25610f001af8d761b4a2 +Author: Timur Tabi +Date: Mon Mar 29 12:51:07 2010 -0500 + + mpc86xx: set the DDR BATs after calculating true DDR size + + After determining how much DDR is actually in the system, set DBAT0 and + IBAT0 accordingly. This ensures that the CPU won't attempt to access + (via speculation) addresses outside of actual memory. + + On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB + and kept that way. If the system has less than 2GB of memory (typical for + an MPC8610 HPCD), the CPU may attempt to access this memory during + speculation. The zlib code is notorious for generating such memory reads, + and indeed on the MPC8610, uncompressing the Linux kernel causes a machine + check (without this patch). + + Currently we are limited to power of two sized DDR since we only use a + single bat. If a non-power of two size is used that is less than + CONFIG_MAX_MEM_MAPPED u-boot will crash. + + Signed-off-by: Timur Tabi + Signed-off-by: Kumar Gala + +commit 33f57bd553edf29dffef5a6c7d76e169c79a6049 +Author: Kumar Gala +Date: Fri Mar 26 15:14:43 2010 -0500 + + 85xx: Fix enabling of L1 cache parity on secondary cores + + Use the same code between primary and secondary cores to init the + L1 cache. We were not enabling cache parity on the secondary cores. + + Also, reworked the L1 cache init code to match the e500mc L2 init code + that first invalidates the cache and locks. Than enables the cache and + makes sure its enabled before continuing. + + Signed-off-by: Kumar Gala + +commit 1a332da61df9c38b567359af114daeaaaefaead8 +Author: Stefan Roese +Date: Mon Mar 29 15:30:46 2010 +0200 + + ppc4xx: Fix problem with I2C bus >= 1 initialization + + This patch fixes a problem introduced with patch eb5eb2b0 + [ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C + base address to the "i2c" pointer inside of the controller loop. + Otherwise controller 0 is initialized multiple times instead of + initializing each I2C controller sequentially. + + Tested on Katmai. + + Signed-off-by: Stefan Roese + Acked-by: Heiko Schocher + +commit 24de2f4be00f81c58270d0df47296bf3a3601cef +Author: Heiko Schocher +Date: Mon Mar 29 13:15:48 2010 +0200 + + bootm, linux: fix booting Multi-File Image with "kernel+ramdisk+fdt" + + Booting a "Multi-File Image" including a linux kernel, ramdisk and + fdt, generated with + + mkimage -A ppc \ + -O linux \ + -T multi \ + -C gzip \ + -a 00000000 \ + -e 00000000 \ + -n "kernel-2.6+initrd+dtb" \ + -d "vmlinux.bin.gz:ramdisk_image.gz:board.dtb" \ + multi.bin + + actually fails, because ramdisk start and end addresses + didn;t get initialized. This patch fixes this issue. + + Tested on the KUP4K board. + + Signed-off-by: Heiko Schocher + +commit 2883cc2d48e99fd1873ef8af03fee7966611b735 +Author: Wolfgang Denk +Date: Sun Mar 28 00:25:14 2010 +0100 + + Prepare 2010.03-rc3 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk + +commit 060f28532b09dd3d2c78423bdd809ac768a27629 +Author: Wolfgang Denk +Date: Thu Mar 25 14:07:23 2010 +0100 + + cmd_usb.c: print debug messages only when DEBUG is defined + + Signed-off-by: Wolfgang Denk + +commit a574cff121b1479c8e962b7a2a29310020387260 +Author: Wolfgang Denk +Date: Wed Mar 24 12:19:19 2010 +0100 + + ml300: remove support for broken, orphaned board + + The ml300 board has a number of issues, but nobody cares about this + long-orphaned board any more. Remove it. + + Signed-off-by: Wolfgang Denk + Acked-by: Michal Simek + +commit 04387d24a17b1ee13024dd4779da4b84d47c65cc +Author: Wolfgang Denk +Date: Sat Mar 27 23:37:46 2010 +0100 + + mkimage: fix Segmentation Fault when run without "-n name" option + + The restructuring of the mkimage command in commit 89a4d6b1 ("tools: + mkimage: split code into core, default and FIT image specific") + introduced a bug that caused mkimage to segfault when run without + "-n name" option. Initialize the imagename entry to prevent that. + + Signed-off-by: Wolfgang Denk + +commit c40c94a3d20a8616264c2dfcda85279185d69aeb +Author: Renato Andreola +Date: Wed Mar 24 23:00:47 2010 +0800 + + cfi_flash: precision and underflow problem in tout calculation + + With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000. + + Signed-off-by: Renato Andreola + Signed-off-by: Alessandro Rubini + Signed-off-by: Thomas Chou + Signed-off-by: Stefan Roese + +commit c550afada5fcad426aa6a219a329feb9eedae8b2 +Author: Rupjyoti Sarmah +Date: Wed Mar 24 16:52:02 2010 +0530 + + ppc4xx fix unstable 440EPx bootstrap options + + 440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1. + This results in the PLLOUTB being greater than the CPU clock frequency + resulting unstable 440EPx operation resulting in various software hang + conditions. + + This patch reprograms the FWDVA satisfying the requirement of setting FWDVB + to a value greater than 1 while using one of the four deafult bootstrap options. + + Signed-off-by: Rupjyoti Sarmah + Acked-by : Victor Gallardo + Signed-off-by: Stefan Roese + +commit fb508b8b39a52a4063d098f5a9b4355bc5b30c14 +Author: Matthias Fuchs +Date: Wed Mar 24 10:16:20 2010 +0100 + + at91: Get rid of some warnings when building for otc570 + + The soft-i2c code for AT91 defines I2C_SOFT_DECLARATIONS + for direct access by dereferencing a pio pointer. + The OTC570 platform uses the AT91 gpio API so it does not + need the pio variable. + + Signed-off-by: Matthias Fuchs + +commit acb13868936a28502782a16e1edaec378e494a29 +Author: Alessandro Rubini +Date: Sat Mar 13 17:44:08 2010 +0100 + + lcd: make 16bpp work + + Support for 16bpp was supposed to be in the code but was not working. + This makes it work and has been tested in the nhk8815 board. + + Signed-off-by: Alessandro Rubini + Acked-by: Andrea Gallo + Signed-off-by: Anatolij Gustschin + +commit 152dda3d94e97ede7af3f9560a59a659384d4585 +Author: Wolfgang Denk +Date: Mon Mar 22 23:25:00 2010 +0100 + + Prepare v2010.03-rc2 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk + +commit d650da2dd4af99967aabc43cccbd8f160eb4cea6 +Author: Matthias Kaehlcke +Date: Tue Mar 9 22:13:33 2010 +0100 + + ep93xx timer: Fix resolution of get_ticks() + + ep93xx timer: Make get_ticks() return a value in CONFIG_SYS_HZ resolution, + as announced by get_tbclk() + + Signed-off-by: Matthias Kaehlcke + +commit 7e67fb5bf27a07d3b8d6b97c76f7195f7d68af58 +Author: Matthias Kaehlcke +Date: Tue Mar 9 22:13:20 2010 +0100 + + ep93xx timer: Fix possible overflow in usecs_to_ticks() + + ep93xx timer: Use 64-bit values in usecs_to_ticks() in order to avoid + overflows in intermediate values + + Signed-off-by: Matthias Kaehlcke + +commit daa989b47297c9f73426783599c286ef3a1f3f49 +Author: Asen Dimov +Date: Thu Mar 18 13:41:47 2010 +0200 + + correct a syntax typo in at91_matrix.h + + Signed-off-by: Asen Dimov + +commit 322ff395c9aec7b87a2211fe4333fdf44377c564 +Author: Jeff Angielski +Date: Wed Mar 17 15:09:26 2010 -0400 + + env: fix endian ordering in crc table + + The crc table was being built as little endian for big endian + targets. This would cause fw_printenv to always fail with + "Warning: Bad CRC, using default environment" messages. + + Signed-off-by: Jeff Angielski + Acked-by: Joakim Tjernlund + +commit 51c2ac9bb574c1420b993615268392b0c1f829f6 +Author: Anatolij Gustschin +Date: Tue Mar 16 17:10:08 2010 +0100 + + mpc5121: cpu/mpc512x/diu.c: fix warnings + + Fix warnings while compiling with CONFIG_VIDEO enabled: + + diu.c: In function 'video_hw_init': + diu.c:158: warning: 'return' with no value, in function returning non-void + diu.c:162: warning: format '%ld' expects type 'long int', but argument 6 has type 'int' + diu.c:162: warning: format '%ld' expects type 'long int', but argument 7 has type 'int' + + Signed-off-by: Anatolij Gustschin + +commit a74908161a1b37d780d3a826a86807bbc50a3857 +Author: Anatolij Gustschin +Date: Tue Mar 16 15:29:33 2010 +0100 + + console.c: fix problem with splashimage + + If a board uses cfb_console driver and splash image + and also defines CONFIG_SILENT_CONSOLE, the user is + locked out even if "silent" is not set. It is not + possible to get any output, neither on vga console + device nor on serial console after redirecting the + output to the serial console, since the GD_FLG_SILENT + flag remains set. + + Fix the problem by redirecting the output from frame + buffer to serial console if splashimage is used. + Only suppress the output if "silent" environment + variable was set and don't set the GD_FLG_SILENT + flag arbitrarily. + + Signed-off-by: Anatolij Gustschin + +commit 5647f78d04174b0b99857d2a7cbf25141bd14a45 +Author: Thomas Weber +Date: Sat Mar 13 23:14:45 2010 +0100 + + mod change 755 => 644 for multiple files + + I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;' + + Signed-off-by: Thomas Weber + Add some more: neither Makefile nor config.mk need execute permissions. + Signed-off-by: Wolfgang Denk + +commit 99c006a320ceb9ea19135ac1512e4a81e8bebb72 +Author: Stefano Babic +Date: Sat Mar 13 21:09:00 2010 +0100 + + mxcmmc: fix warnings due to access 32 bit registers with 16 bit accessors + + Some registers of the mxcmmc driver were accessed using + 16 bit accessor functions, because only the LSB is + significant. This is not needed and generates + warnings. + + Signed-off-by: Stefano Babic + +commit c96f86eefc215b67dd222694ce2b6f60e6a42b0b +Author: Wolfgang Denk +Date: Sun Jan 17 23:55:53 2010 +0100 + + TFTP: allow for adjustable retransmission timout + + So far, TFTP negotiated a fixed retransmission timeout of 5 seconds. + In some cases (busy networks, slow TFTP servers) this caused very + slow transfers. A new environment variable "tftptimeout" allows to + set this timeout. Lowering this value may make downloads succeed + faster in networks with high packet loss rates or with unreliable + TFTP servers. + + Signed-off-by: Wolfgang Denk + Cc: Ben Warren + Signed-off-by: Ben Warren + +commit 252b404d954f91499a4477a3e1064eb237ce5a1c +Author: Wolfgang Denk +Date: Tue Mar 9 14:27:25 2010 +0100 + + Fix PCI_BASE_ADDRESS_5 handling in pci_hose_config_device() + + Signed-off-by: FUJITA Kazutoshi + Signed-off-by: + Acked-by: Stefan Roese + +commit 9d90a93d367272ee65550c0c9f82615cec967c70 +Author: Frans Meulenbroeks +Date: Thu Feb 25 14:03:08 2010 +0100 + + cmd_mmc remove \n + + This patch removes the \n after the help message for mmcinfo. + This resulted in an empty line being displayed after the mmcinfo line + when the help command was given. + + Signed-off-by: Frans Meulenbroeks + +commit 67c7189dd35cb368ef665126fd17816581bd2e92 +Author: Renato Andreola +Date: Tue Mar 16 16:01:29 2010 -0400 + + nios2: Added support to YANU UART + + Signed-off-by: Scott McNutt + +commit 1e67fb32fbdae7949bb423c9e20b3f77c0a61663 +Author: Thomas Chou +Date: Tue Mar 16 12:12:48 2010 -0400 + + nios2: use generic unaligned.h + + Signed-off-by: Scott McNutt + +commit 05022629a2ca6c385dc390d32c20aa27cf5d915a +Author: Mike Frysinger +Date: Thu Jan 21 05:01:15 2010 -0500 + + asm-blackfin/unaligned.h: add for zlib code + + The new zlib code wants asm/unaligned.h, so have the Blackfin version pull + in the asm-generic/unaligned.h. + + Signed-off-by: Mike Frysinger + +commit 3adc1fda38a6aacd4aaf3c2c9cc62a1e69e6de17 +Author: Mike Frysinger +Date: Thu Jan 21 05:01:14 2010 -0500 + + asm-generic/unaligned.h: dynamic default unaligned accesses + + This is based on the asm-arm/unaligned.h, but made generic so all arches + that cannot do unaligned accesses can utilize it. + + Signed-off-by: Mike Frysinger + +commit be129aa71882421ad0b50cd3762915d10ace27ad +Author: Matthias Weisser +Date: Tue Jan 12 12:06:31 2010 +0100 + + video: Fix console display when splashscreen is used + + If a splashscreen is used the console scrolling used the + scroll size as needed when a logo was displayed. This + patch sets the scroll size to the whole screen if + a splashscreen is shown. + + Signed-off-by: Matthias Weisser + +commit 93910edb595a88d394da3eb2cf5148096155dfe9 +Author: Wolfgang Denk +Date: Fri Mar 12 23:06:04 2010 +0100 + + Prepare v2010.03-rc1 + + Coding style cleanup, update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit 4e72fb15c9073129e05820cc9c54f54bc4985835 Author: Wolfgang Denk Date: Fri Mar 12 22:11:00 2010 +0100 diff --git a/CREDITS b/CREDITS index 2471029fc5..4f3cdbb231 100644 --- a/CREDITS +++ b/CREDITS @@ -437,7 +437,7 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor N: Andre Schwarz E: andre.schwarz@matrix-vision.de -D: Support for Matrix Vision boards (MVBLM7/MVBC_P) +D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR) N: Robert Schwebel E: r.schwebel@pengutronix.de @@ -511,6 +511,11 @@ N: Martin Winistoerfer E: martinwinistoerfer@gmx.ch D: Port to MPC555/556 microcontrollers and support for cmi board +N: David Wu +E: support@arcturusnetworks.com +D: Mercury Security EP2500 +W: http://www.arcturusnetworks.com + N: Ming-Len Wu E: minglen_wu@techware.com.tw D: Motorola MX1ADS board support diff --git a/MAINTAINERS b/MAINTAINERS index 092ebecc01..0e759c95da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -80,7 +80,6 @@ Torsten Demke Wolfgang Denk - IceCube_5100 MGT5100 IceCube_5200 MPC5200 ARIA MPC5121e @@ -423,6 +422,7 @@ Andre Schwarz mvbc_p MPC5200 mvblm7 MPC8343 + mvsmr MPC5200 Jon Smirl @@ -734,6 +734,10 @@ Jens Scharsig eb_cpux9k2 ARM920T (AT91RM9200 SoC) +Heiko Schocher + + magnesium i.MX27 + Robert Schwebel csb226 xscale @@ -897,6 +901,10 @@ TsiChung Liew M5475EVB mcf547x_8x M5485EVB mcf547x_8x +Wolfgang Wegner + + astro_mcf5373l MCF5373L + ######################################################################### # AVR32 Systems: # # # @@ -1012,6 +1020,10 @@ Anton Shurpin BF561-ACVILON BF561 +Brent Kandetzki + + IP04 BF532 + ######################################################################### # End of MAINTAINERS list # ######################################################################### diff --git a/MAKEALL b/MAKEALL index beacb5f517..b15d407faf 100755 --- a/MAKEALL +++ b/MAKEALL @@ -61,7 +61,6 @@ LIST_5xxx=" \ EVAL5200 \ fo300 \ galaxy5200 \ - icecube_5100 \ icecube_5200 \ inka4x0 \ ipek01 \ @@ -71,12 +70,12 @@ LIST_5xxx=" \ motionpro \ munices \ MVBC_P \ + MVSMR \ o2dnt \ pcm030 \ pf5200 \ PM520 \ TB5200 \ - Total5100 \ Total5200 \ Total5200_Rev2 \ TQM5200 \ @@ -238,7 +237,6 @@ LIST_4xx=" \ MIP405 \ MIP405T \ ML2 \ - ml300 \ ml507 \ ml507_flash \ neo \ @@ -564,6 +562,7 @@ LIST_ARM9=" \ edb9315a \ imx27lite \ lpd7a400 \ + magnesium \ mv88f6281gtw_ge \ mx1ads \ mx1fs2 \ @@ -841,6 +840,7 @@ LIST_microblaze=" \ ######################################################################### LIST_coldfire=" \ + astro_mcf5373l \ cobra5272 \ EB+MCF-EV123 \ EB+MCF-EV123_internal \ @@ -907,6 +907,7 @@ LIST_blackfin=" \ cm-bf548 \ cm-bf561 \ ibf-dsp561 \ + ip04 \ tcm-bf518 \ tcm-bf537 \ " diff --git a/Makefile b/Makefile index d801e2597a..8b4e0b9381 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2009 +# (C) Copyright 2000-2010 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,7 +24,7 @@ VERSION = 2010 PATCHLEVEL = 03 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else @@ -169,33 +169,33 @@ include $(TOPDIR)/config.mk ######################################################################### # U-Boot objects....order is important (i.e. start must be first) -OBJS = cpu/$(CPU)/start.o +OBJS = $(CPUDIR)/start.o ifeq ($(CPU),i386) -OBJS += cpu/$(CPU)/start16.o -OBJS += cpu/$(CPU)/resetvec.o +OBJS += $(CPUDIR)/start16.o +OBJS += $(CPUDIR)/resetvec.o endif ifeq ($(CPU),ppc4xx) -OBJS += cpu/$(CPU)/resetvec.o +OBJS += $(CPUDIR)/resetvec.o endif ifeq ($(CPU),mpc85xx) -OBJS += cpu/$(CPU)/resetvec.o +OBJS += $(CPUDIR)/resetvec.o endif OBJS := $(addprefix $(obj),$(OBJS)) -LIBS = lib_generic/libgeneric.a -LIBS += lib_generic/lzma/liblzma.a -LIBS += lib_generic/lzo/liblzo.a +LIBS = lib/libgeneric.a +LIBS += lib/lzma/liblzma.a +LIBS += lib/lzo/liblzo.a LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \ "board/$(VENDOR)/common/lib$(VENDOR).a"; fi) -LIBS += cpu/$(CPU)/lib$(CPU).a +LIBS += $(CPUDIR)/lib$(CPU).a ifdef SOC -LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a +LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).a endif ifeq ($(CPU),ixp) -LIBS += cpu/ixp/npe/libnpe.a +LIBS += arch/arm/cpu/ixp/npe/libnpe.a endif -LIBS += lib_$(ARCH)/lib$(ARCH).a +LIBS += arch/$(ARCH)/lib/lib$(ARCH).a LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \ fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a fs/yaffs2/libyaffs2.a \ fs/ubifs/libubifs.a @@ -227,12 +227,12 @@ LIBS += drivers/qe/qe.a endif ifeq ($(CPU),mpc85xx) LIBS += drivers/qe/qe.a -LIBS += cpu/mpc8xxx/ddr/libddr.a -LIBS += cpu/mpc8xxx/lib8xxx.a +LIBS += arch/ppc/cpu/mpc8xxx/ddr/libddr.a +LIBS += arch/ppc/cpu/mpc8xxx/lib8xxx.a endif ifeq ($(CPU),mpc86xx) -LIBS += cpu/mpc8xxx/ddr/libddr.a -LIBS += cpu/mpc8xxx/lib8xxx.a +LIBS += arch/ppc/cpu/mpc8xxx/ddr/libddr.a +LIBS += arch/ppc/cpu/mpc8xxx/lib8xxx.a endif LIBS += drivers/rtc/librtc.a LIBS += drivers/serial/libserial.a @@ -244,7 +244,7 @@ LIBS += drivers/usb/phy/libusb_phy.a LIBS += drivers/video/libvideo.a LIBS += drivers/watchdog/libwatchdog.a LIBS += common/libcommon.a -LIBS += libfdt/libfdt.a +LIBS += lib/libfdt/libfdt.a LIBS += api/libapi.a LIBS += post/libpost.a @@ -257,7 +257,7 @@ LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) # Add GCC lib ifdef USE_PRIVATE_LIBGCC ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") -PLATFORM_LIBGCC = -L $(OBJTREE)/lib_$(ARCH) -lgcc +PLATFORM_LIBGCC = -L $(OBJTREE)/arch/$(ARCH)/lib -lgcc else PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc endif @@ -354,7 +354,7 @@ ifeq ($(CONFIG_KALLSYMS),y) endif $(OBJS): depend - $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@)) + $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)) $(LIBS): depend $(SUBDIRS) $(MAKE) -C $(dir $(subst $(obj),,$@)) @@ -404,7 +404,7 @@ env: # Explicitly make _depend in subdirs containing multiple targets to prevent # parallel sub-makes creating .depend files simultaneously. depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk - for dir in $(SUBDIRS) cpu/$(CPU) $(dir $(LDSCRIPT)) ; do \ + for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \ $(MAKE) -C $$dir _depend ; done TAG_SUBDIRS = $(SUBDIRS) @@ -548,8 +548,7 @@ icecube_5200_LOWBOOT_config \ icecube_5200_LOWBOOT08_config \ icecube_5200_DDR_config \ icecube_5200_DDR_LOWBOOT_config \ -icecube_5200_DDR_LOWBOOT08_config \ -icecube_5100_config: unconfig +icecube_5200_DDR_LOWBOOT08_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/icecube @[ -z "$(findstring LOWBOOT_,$@)" ] || \ @@ -568,14 +567,6 @@ icecube_5100_config: unconfig { echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \ $(XECHO) "... DDR memory revision" ; \ } - @[ -z "$(findstring 5200,$@)" ] || \ - { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \ - $(XECHO) "... with MPC5200 processor" ; \ - } - @[ -z "$(findstring 5100,$@)" ] || \ - { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \ - $(XECHO) "... with MGT5100 processor" ; \ - } @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube jupiter_config: unconfig @@ -594,7 +585,6 @@ lite5200b_LOWBOOT_config: unconfig @mkdir -p $(obj)board/icecube @ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h @ $(XECHO) "... DDR memory revision" - @ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h @ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h @[ -z "$(findstring _PM_,$@)" ] || \ { echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \ @@ -604,7 +594,6 @@ lite5200b_LOWBOOT_config: unconfig { echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \ $(XECHO) "... with LOWBOOT configuration" ; \ } - @ $(XECHO) "... with MPC5200B processor" @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube mcc200_config \ @@ -675,6 +664,11 @@ MVBC_P_config: unconfig { echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h; } @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision +MVSMR_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/matrix_vision/mvsmr + @$(MKCONFIG) $(@:_config=) ppc mpc5xxx mvsmr matrix_vision + o2dnt_config: unconfig @$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt @@ -728,21 +722,12 @@ TOP5200_config: unconfig @ echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h @$(MKCONFIG) -n $@ -a TOP5200 ppc mpc5xxx top5200 emk -Total5100_config \ Total5200_config \ Total5200_lowboot_config \ Total5200_Rev2_config \ Total5200_Rev2_lowboot_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/total5200 - @[ -z "$(findstring 5100,$@)" ] || \ - { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \ - $(XECHO) "... with MGT5100 processor" ; \ - } - @[ -z "$(findstring 5200,$@)" ] || \ - { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \ - $(XECHO) "... with MPC5200 processor" ; \ - } @[ -n "$(findstring Rev,$@)" ] || \ { echo "#define CONFIG_TOTAL5200_REV 1" >>$(obj)include/config.h ; \ $(XECHO) "... revision 1 board" ; \ @@ -1435,9 +1420,6 @@ MIP405T_config: unconfig ML2_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml2 -ml300_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx - ml507_flash_config: unconfig @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic @mkdir -p $(obj)include $(obj)board/xilinx/ml507 @@ -1996,6 +1978,10 @@ ZPC1900_config: unconfig ## Coldfire ######################################################################### +astro_mcf5373l_config \ +astro_mcf5373l_RAM_config : unconfig + @$(MKCONFIG) -t $(@:_config=) astro_mcf5373l m68k mcf532x mcf5373l astro + M5208EVBE_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5208evbe freescale @@ -2064,6 +2050,9 @@ EB+MCF-EV123_internal_config : unconfig @echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk @$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS +EP2500_config: unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 ep2500 Mercury + idmr_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr @@ -2952,6 +2941,7 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci +magnesium_config \ imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 @@ -3570,7 +3560,7 @@ BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 \ tcm-bf518 tcm-bf537 # Misc third party boards -BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp +BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp ip04 # I-SYST Micromodule BFIN_BOARDS += ibf-dsp561 @@ -3754,9 +3744,9 @@ clean: $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \ $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \ - $(obj)lib_blackfin/u-boot.lds \ + $(obj)arch/blackfin/lib/u-boot.lds \ $(obj)u-boot.lds \ - $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] + $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] @rm -f $(obj)include/bmp_logo.h @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map} @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map} @@ -3779,7 +3769,7 @@ clobber: clean @rm -f $(obj)u-boot.kwb @rm -f $(obj)u-boot.imx @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} - @rm -f $(obj)cpu/mpc824x/bedbug_603e.c + @rm -f $(obj)arch/ppc/cpu/mpc824x/bedbug_603e.c @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f diff --git a/README b/README index 940b507942..99320abadd 100644 --- a/README +++ b/README @@ -138,68 +138,91 @@ U-Boot will always have a patchlevel of "0". Directory Hierarchy: ==================== -- api Machine/arch independent API for external apps -- board Board dependent files -- common Misc architecture independent functions -- cpu CPU specific files - - 74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs - - arm720t Files specific to ARM 720 CPUs - - arm920t Files specific to ARM 920 CPUs - - at91rm9200 Files specific to Atmel AT91RM9200 CPU - - imx Files specific to Freescale MC9328 i.MX CPUs - - s3c24x0 Files specific to Samsung S3C24X0 CPUs - - arm925t Files specific to ARM 925 CPUs - - arm926ejs Files specific to ARM 926 CPUs - - arm1136 Files specific to ARM 1136 CPUs - - at32ap Files specific to Atmel AVR32 AP CPUs - - blackfin Files specific to Analog Devices Blackfin CPUs - - i386 Files specific to i386 CPUs - - ixp Files specific to Intel XScale IXP CPUs - - leon2 Files specific to Gaisler LEON2 SPARC CPU - - leon3 Files specific to Gaisler LEON3 SPARC CPU - - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs - - mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs - - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs - - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs - - mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs - - mips Files specific to MIPS CPUs - - mpc5xx Files specific to Freescale MPC5xx CPUs - - mpc5xxx Files specific to Freescale MPC5xxx CPUs - - mpc8xx Files specific to Freescale MPC8xx CPUs - - mpc8220 Files specific to Freescale MPC8220 CPUs - - mpc824x Files specific to Freescale MPC824x CPUs - - mpc8260 Files specific to Freescale MPC8260 CPUs - - mpc85xx Files specific to Freescale MPC85xx CPUs - - nios Files specific to Altera NIOS CPUs - - nios2 Files specific to Altera Nios-II CPUs - - ppc4xx Files specific to AMCC PowerPC 4xx CPUs - - pxa Files specific to Intel XScale PXA CPUs - - s3c44b0 Files specific to Samsung S3C44B0 CPUs - - sa1100 Files specific to Intel StrongARM SA1100 CPUs -- disk Code for disk drive partition handling -- doc Documentation (don't expect too much) -- drivers Commonly used device drivers -- examples Example code for standalone applications, etc. -- fs Filesystem code (cramfs, ext2, jffs2, etc.) -- include Header Files -- lib_arm Files generic to ARM architecture -- lib_avr32 Files generic to AVR32 architecture -- lib_blackfin Files generic to Blackfin architecture -- lib_generic Files generic to all architectures -- lib_i386 Files generic to i386 architecture -- lib_m68k Files generic to m68k architecture -- lib_microblaze Files generic to microblaze architecture -- lib_mips Files generic to MIPS architecture -- lib_nios Files generic to NIOS architecture -- lib_nios2 Files generic to NIOS2 architecture -- lib_ppc Files generic to PowerPC architecture -- lib_sh Files generic to SH architecture -- lib_sparc Files generic to SPARC architecture -- libfdt Library files to support flattened device trees -- net Networking code -- post Power On Self Test -- rtc Real Time Clock drivers -- tools Tools to build S-Record or U-Boot images, etc. +/arch Architecture specific files + /arm Files generic to ARM architecture + /cpu CPU specific files + /arm720t Files specific to ARM 720 CPUs + /arm920t Files specific to ARM 920 CPUs + /at91rm9200 Files specific to Atmel AT91RM9200 CPU + /imx Files specific to Freescale MC9328 i.MX CPUs + /s3c24x0 Files specific to Samsung S3C24X0 CPUs + /arm925t Files specific to ARM 925 CPUs + /arm926ejs Files specific to ARM 926 CPUs + /arm1136 Files specific to ARM 1136 CPUs + /ixp Files specific to Intel XScale IXP CPUs + /pxa Files specific to Intel XScale PXA CPUs + /s3c44b0 Files specific to Samsung S3C44B0 CPUs + /sa1100 Files specific to Intel StrongARM SA1100 CPUs + /lib Architecture specific library files + /avr32 Files generic to AVR32 architecture + /cpu CPU specific files + /lib Architecture specific library files + /blackfin Files generic to Analog Devices Blackfin architecture + /cpu CPU specific files + /lib Architecture specific library files + /i386 Files generic to i386 architecture + /cpu CPU specific files + /lib Architecture specific library files + /m68k Files generic to m68k architecture + /cpu CPU specific files + /mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs + /mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs + /mcf532x Files specific to Freescale ColdFire MCF5329 CPUs + /mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs + /mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs + /lib Architecture specific library files + /microblaze Files generic to microblaze architecture + /cpu CPU specific files + /lib Architecture specific library files + /mips Files generic to MIPS architecture + /cpu CPU specific files + /lib Architecture specific library files + /nios Files generic to Altera NIOS architecture + /cpu CPU specific files + /lib Architecture specific library files + /nios2 Files generic to Altera NIOS2 architecture + /cpu CPU specific files + /lib Architecture specific library files + /ppc Files generic to PowerPC architecture + /cpu CPU specific files + /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs + /mpc5xx Files specific to Freescale MPC5xx CPUs + /mpc5xxx Files specific to Freescale MPC5xxx CPUs + /mpc8xx Files specific to Freescale MPC8xx CPUs + /mpc8220 Files specific to Freescale MPC8220 CPUs + /mpc824x Files specific to Freescale MPC824x CPUs + /mpc8260 Files specific to Freescale MPC8260 CPUs + /mpc85xx Files specific to Freescale MPC85xx CPUs + /ppc4xx Files specific to AMCC PowerPC 4xx CPUs + /lib Architecture specific library files + /sh Files generic to SH architecture + /cpu CPU specific files + /sh2 Files specific to sh2 CPUs + /sh3 Files specific to sh3 CPUs + /sh4 Files specific to sh4 CPUs + /lib Architecture specific library files + /sparc Files generic to SPARC architecture + /cpu CPU specific files + /leon2 Files specific to Gaisler LEON2 SPARC CPU + /leon3 Files specific to Gaisler LEON3 SPARC CPU + /lib Architecture specific library files +/api Machine/arch independent API for external apps +/board Board dependent files +/common Misc architecture independent functions +/disk Code for disk drive partition handling +/doc Documentation (don't expect too much) +/drivers Commonly used device drivers +/examples Example code for standalone applications, etc. +/fs Filesystem code (cramfs, ext2, jffs2, etc.) +/include Header Files +/lib Files generic to all architectures + /libfdt Library files to support flattened device trees + /lzma Library files to support LZMA decompression + /lzo Library files to support LZO decompression +/net Networking code +/post Power On Self Test +/rtc Real Time Clock drivers +/tools Tools to build S-Record or U-Boot images, etc. Software Configuration: ======================= @@ -1133,6 +1156,12 @@ The following options need to be configured: images, gzipped BMP images can be displayed via the splashscreen support or the bmp command. +- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8 + + If this option is set, 8-bit RLE compressed BMP images + can be displayed via the splashscreen support or the + bmp command. + - Compression support: CONFIG_BZIP2 @@ -1387,10 +1416,11 @@ The following options need to be configured: to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie the CPU's i2c node address). - Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c) - sets the CPU up as a master node and so its address should - therefore be cleared to 0 (See, eg, MPC823e User's Manual - p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0. + Now, the u-boot i2c code for the mpc8xx + (arch/ppc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node + and so its address should therefore be cleared to 0 (See, + eg, MPC823e User's Manual p.16-473). So, set + CONFIG_SYS_I2C_SLAVE to 0. CONFIG_SYS_I2C_INIT_MPC5XXX @@ -1934,9 +1964,9 @@ Legacy uImage format: 13 common/image.c Start multifile image verification 14 common/image.c No initial ramdisk, no multifile, continue. - 15 lib_/bootm.c All preparation done, transferring control to OS + 15 arch//lib/bootm.c All preparation done, transferring control to OS - -30 lib_ppc/board.c Fatal error, hang the system + -30 arch/ppc/lib/board.c Fatal error, hang the system -31 post/post.c POST test failed, detected by post_output_backlog() -32 post/post.c POST test failed, detected by post_run_single() @@ -2697,7 +2727,7 @@ Low Level (hardware related) configuration options: CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL, CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE, CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only) - Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. + Overrides the default PCI memory map in arch/ppc/cpu/mpc8260/pci.c if set. - CONFIG_PCI_DISABLE_PCIE: Disable PCI-Express on systems where it is supported but not diff --git a/arch/arm/config.mk b/arch/arm/config.mk new file mode 100644 index 0000000000..e10dafca58 --- /dev/null +++ b/arch/arm/config.mk @@ -0,0 +1,66 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CROSS_COMPILE ?= arm-linux- + +ifeq ($(BOARD),omap2420h4) +STANDALONE_LOAD_ADDR = 0x80300000 +else +ifeq ($(SOC),omap3) +STANDALONE_LOAD_ADDR = 0x80300000 +else +STANDALONE_LOAD_ADDR = 0xc100000 +endif +endif + +PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ + +# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: +PLATFORM_CPPFLAGS += $(call cc-option,-marm,) + +# Try if EABI is supported, else fall back to old API, +# i. e. for example: +# - with ELDK 4.2 (EABI supported), use: +# -mabi=aapcs-linux -mno-thumb-interwork +# - with ELDK 4.1 (gcc 4.x, no EABI), use: +# -mabi=apcs-gnu -mno-thumb-interwork +# - with ELDK 3.1 (gcc 3.x), use: +# -mapcs-32 -mno-thumb-interwork +PLATFORM_CPPFLAGS += $(call cc-option,\ + -mabi=aapcs-linux -mno-thumb-interwork,\ + $(call cc-option,\ + -mapcs-32,\ + $(call cc-option,\ + -mabi=apcs-gnu,\ + )\ + ) $(call cc-option,-mno-thumb-interwork,)\ + ) + +# For EABI, make sure to provide raise() +ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) +# This file is parsed several times; make sure to add only once. +ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS))) +PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o +endif +endif +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile similarity index 100% rename from cpu/arm1136/Makefile rename to arch/arm/cpu/arm1136/Makefile diff --git a/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk similarity index 100% rename from cpu/arm1136/config.mk rename to arch/arm/cpu/arm1136/config.mk diff --git a/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c similarity index 100% rename from cpu/arm1136/cpu.c rename to arch/arm/cpu/arm1136/cpu.c diff --git a/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile similarity index 100% rename from cpu/arm1136/mx31/Makefile rename to arch/arm/cpu/arm1136/mx31/Makefile diff --git a/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c similarity index 100% rename from cpu/arm1136/mx31/devices.c rename to arch/arm/cpu/arm1136/mx31/devices.c diff --git a/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c similarity index 100% rename from cpu/arm1136/mx31/generic.c rename to arch/arm/cpu/arm1136/mx31/generic.c diff --git a/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c similarity index 100% rename from cpu/arm1136/mx31/timer.c rename to arch/arm/cpu/arm1136/mx31/timer.c diff --git a/cpu/arm1136/omap24xx/Makefile b/arch/arm/cpu/arm1136/omap24xx/Makefile similarity index 100% rename from cpu/arm1136/omap24xx/Makefile rename to arch/arm/cpu/arm1136/omap24xx/Makefile diff --git a/cpu/arm1136/omap24xx/reset.S b/arch/arm/cpu/arm1136/omap24xx/reset.S similarity index 100% rename from cpu/arm1136/omap24xx/reset.S rename to arch/arm/cpu/arm1136/omap24xx/reset.S diff --git a/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c similarity index 100% rename from cpu/arm1136/omap24xx/timer.c rename to arch/arm/cpu/arm1136/omap24xx/timer.c diff --git a/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S similarity index 100% rename from cpu/arm1136/start.S rename to arch/arm/cpu/arm1136/start.S diff --git a/arch/arm/cpu/arm1136/u-boot.lds b/arch/arm/cpu/arm1136/u-boot.lds new file mode 100644 index 0000000000..e7eefc972c --- /dev/null +++ b/arch/arm/cpu/arm1136/u-boot.lds @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2009 + * Ilya Yanok, Emcraft Systems Ltd, + * + * Copyright (C) 2005-2007 Samsung Electronics + * Kyungin Park + * + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile similarity index 100% rename from cpu/arm1176/Makefile rename to arch/arm/cpu/arm1176/Makefile diff --git a/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk similarity index 100% rename from cpu/arm1176/config.mk rename to arch/arm/cpu/arm1176/config.mk diff --git a/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c similarity index 100% rename from cpu/arm1176/cpu.c rename to arch/arm/cpu/arm1176/cpu.c diff --git a/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile similarity index 100% rename from cpu/arm1176/s3c64xx/Makefile rename to arch/arm/cpu/arm1176/s3c64xx/Makefile diff --git a/cpu/arm1176/s3c64xx/config.mk b/arch/arm/cpu/arm1176/s3c64xx/config.mk similarity index 100% rename from cpu/arm1176/s3c64xx/config.mk rename to arch/arm/cpu/arm1176/s3c64xx/config.mk diff --git a/cpu/arm1176/s3c64xx/cpu_init.S b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S similarity index 100% rename from cpu/arm1176/s3c64xx/cpu_init.S rename to arch/arm/cpu/arm1176/s3c64xx/cpu_init.S diff --git a/cpu/arm1176/s3c64xx/reset.S b/arch/arm/cpu/arm1176/s3c64xx/reset.S similarity index 100% rename from cpu/arm1176/s3c64xx/reset.S rename to arch/arm/cpu/arm1176/s3c64xx/reset.S diff --git a/cpu/arm1176/s3c64xx/speed.c b/arch/arm/cpu/arm1176/s3c64xx/speed.c similarity index 100% rename from cpu/arm1176/s3c64xx/speed.c rename to arch/arm/cpu/arm1176/s3c64xx/speed.c diff --git a/cpu/arm1176/s3c64xx/timer.c b/arch/arm/cpu/arm1176/s3c64xx/timer.c similarity index 100% rename from cpu/arm1176/s3c64xx/timer.c rename to arch/arm/cpu/arm1176/s3c64xx/timer.c diff --git a/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S similarity index 100% rename from cpu/arm1176/start.S rename to arch/arm/cpu/arm1176/start.S diff --git a/arch/arm/cpu/arm1176/u-boot.lds b/arch/arm/cpu/arm1176/u-boot.lds new file mode 100644 index 0000000000..8969587e8c --- /dev/null +++ b/arch/arm/cpu/arm1176/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm1176/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile similarity index 100% rename from cpu/arm720t/Makefile rename to arch/arm/cpu/arm720t/Makefile diff --git a/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk similarity index 100% rename from cpu/arm720t/config.mk rename to arch/arm/cpu/arm720t/config.mk diff --git a/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c similarity index 100% rename from cpu/arm720t/cpu.c rename to arch/arm/cpu/arm720t/cpu.c diff --git a/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c similarity index 100% rename from cpu/arm720t/interrupts.c rename to arch/arm/cpu/arm720t/interrupts.c diff --git a/cpu/arm720t/lpc2292/Makefile b/arch/arm/cpu/arm720t/lpc2292/Makefile similarity index 100% rename from cpu/arm720t/lpc2292/Makefile rename to arch/arm/cpu/arm720t/lpc2292/Makefile diff --git a/cpu/arm720t/lpc2292/flash.c b/arch/arm/cpu/arm720t/lpc2292/flash.c similarity index 100% rename from cpu/arm720t/lpc2292/flash.c rename to arch/arm/cpu/arm720t/lpc2292/flash.c diff --git a/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S similarity index 100% rename from cpu/arm720t/lpc2292/iap_entry.S rename to arch/arm/cpu/arm720t/lpc2292/iap_entry.S diff --git a/cpu/arm720t/lpc2292/mmc.c b/arch/arm/cpu/arm720t/lpc2292/mmc.c similarity index 100% rename from cpu/arm720t/lpc2292/mmc.c rename to arch/arm/cpu/arm720t/lpc2292/mmc.c diff --git a/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c similarity index 100% rename from cpu/arm720t/lpc2292/mmc_hw.c rename to arch/arm/cpu/arm720t/lpc2292/mmc_hw.c diff --git a/cpu/arm720t/lpc2292/mmc_hw.h b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h similarity index 100% rename from cpu/arm720t/lpc2292/mmc_hw.h rename to arch/arm/cpu/arm720t/lpc2292/mmc_hw.h diff --git a/cpu/arm720t/lpc2292/spi.c b/arch/arm/cpu/arm720t/lpc2292/spi.c similarity index 100% rename from cpu/arm720t/lpc2292/spi.c rename to arch/arm/cpu/arm720t/lpc2292/spi.c diff --git a/cpu/arm720t/s3c4510b/Makefile b/arch/arm/cpu/arm720t/s3c4510b/Makefile similarity index 100% rename from cpu/arm720t/s3c4510b/Makefile rename to arch/arm/cpu/arm720t/s3c4510b/Makefile diff --git a/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c similarity index 100% rename from cpu/arm720t/s3c4510b/cache.c rename to arch/arm/cpu/arm720t/s3c4510b/cache.c diff --git a/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S similarity index 100% rename from cpu/arm720t/start.S rename to arch/arm/cpu/arm720t/start.S diff --git a/arch/arm/cpu/arm720t/u-boot.lds b/arch/arm/cpu/arm720t/u-boot.lds new file mode 100644 index 0000000000..c975fc3d5e --- /dev/null +++ b/arch/arm/cpu/arm720t/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile similarity index 100% rename from cpu/arm920t/Makefile rename to arch/arm/cpu/arm920t/Makefile diff --git a/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile similarity index 100% rename from cpu/arm920t/a320/Makefile rename to arch/arm/cpu/arm920t/a320/Makefile diff --git a/cpu/arm920t/a320/ftsmc020.c b/arch/arm/cpu/arm920t/a320/ftsmc020.c similarity index 100% rename from cpu/arm920t/a320/ftsmc020.c rename to arch/arm/cpu/arm920t/a320/ftsmc020.c diff --git a/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S similarity index 100% rename from cpu/arm920t/a320/reset.S rename to arch/arm/cpu/arm920t/a320/reset.S diff --git a/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c similarity index 100% rename from cpu/arm920t/a320/timer.c rename to arch/arm/cpu/arm920t/a320/timer.c diff --git a/cpu/arm920t/at91/Makefile b/arch/arm/cpu/arm920t/at91/Makefile similarity index 100% rename from cpu/arm920t/at91/Makefile rename to arch/arm/cpu/arm920t/at91/Makefile diff --git a/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S similarity index 100% rename from cpu/arm920t/at91/lowlevel_init.S rename to arch/arm/cpu/arm920t/at91/lowlevel_init.S diff --git a/cpu/arm920t/at91/reset.c b/arch/arm/cpu/arm920t/at91/reset.c similarity index 100% rename from cpu/arm920t/at91/reset.c rename to arch/arm/cpu/arm920t/at91/reset.c diff --git a/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c similarity index 100% rename from cpu/arm920t/at91/timer.c rename to arch/arm/cpu/arm920t/at91/timer.c diff --git a/cpu/arm920t/at91rm9200/Makefile b/arch/arm/cpu/arm920t/at91rm9200/Makefile similarity index 100% rename from cpu/arm920t/at91rm9200/Makefile rename to arch/arm/cpu/arm920t/at91rm9200/Makefile diff --git a/cpu/arm920t/at91rm9200/bcm5221.c b/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c similarity index 100% rename from cpu/arm920t/at91rm9200/bcm5221.c rename to arch/arm/cpu/arm920t/at91rm9200/bcm5221.c diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/arch/arm/cpu/arm920t/at91rm9200/dm9161.c similarity index 100% rename from cpu/arm920t/at91rm9200/dm9161.c rename to arch/arm/cpu/arm920t/at91rm9200/dm9161.c diff --git a/cpu/arm920t/at91rm9200/ether.c b/arch/arm/cpu/arm920t/at91rm9200/ether.c similarity index 100% rename from cpu/arm920t/at91rm9200/ether.c rename to arch/arm/cpu/arm920t/at91rm9200/ether.c diff --git a/cpu/arm920t/at91rm9200/i2c.c b/arch/arm/cpu/arm920t/at91rm9200/i2c.c similarity index 100% rename from cpu/arm920t/at91rm9200/i2c.c rename to arch/arm/cpu/arm920t/at91rm9200/i2c.c diff --git a/cpu/arm920t/at91rm9200/ks8721.c b/arch/arm/cpu/arm920t/at91rm9200/ks8721.c similarity index 100% rename from cpu/arm920t/at91rm9200/ks8721.c rename to arch/arm/cpu/arm920t/at91rm9200/ks8721.c diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S similarity index 100% rename from cpu/arm920t/at91rm9200/lowlevel_init.S rename to arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c similarity index 100% rename from cpu/arm920t/at91rm9200/lxt972.c rename to arch/arm/cpu/arm920t/at91rm9200/lxt972.c diff --git a/cpu/arm920t/at91rm9200/reset.c b/arch/arm/cpu/arm920t/at91rm9200/reset.c similarity index 100% rename from cpu/arm920t/at91rm9200/reset.c rename to arch/arm/cpu/arm920t/at91rm9200/reset.c diff --git a/cpu/arm920t/at91rm9200/spi.c b/arch/arm/cpu/arm920t/at91rm9200/spi.c similarity index 100% rename from cpu/arm920t/at91rm9200/spi.c rename to arch/arm/cpu/arm920t/at91rm9200/spi.c diff --git a/cpu/arm920t/at91rm9200/timer.c b/arch/arm/cpu/arm920t/at91rm9200/timer.c similarity index 100% rename from cpu/arm920t/at91rm9200/timer.c rename to arch/arm/cpu/arm920t/at91rm9200/timer.c diff --git a/cpu/arm920t/at91rm9200/usb.c b/arch/arm/cpu/arm920t/at91rm9200/usb.c similarity index 100% rename from cpu/arm920t/at91rm9200/usb.c rename to arch/arm/cpu/arm920t/at91rm9200/usb.c diff --git a/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk similarity index 100% rename from cpu/arm920t/config.mk rename to arch/arm/cpu/arm920t/config.mk diff --git a/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c similarity index 100% rename from cpu/arm920t/cpu.c rename to arch/arm/cpu/arm920t/cpu.c diff --git a/cpu/arm920t/ep93xx/Makefile b/arch/arm/cpu/arm920t/ep93xx/Makefile similarity index 100% rename from cpu/arm920t/ep93xx/Makefile rename to arch/arm/cpu/arm920t/ep93xx/Makefile diff --git a/cpu/arm920t/ep93xx/cpu.c b/arch/arm/cpu/arm920t/ep93xx/cpu.c similarity index 100% rename from cpu/arm920t/ep93xx/cpu.c rename to arch/arm/cpu/arm920t/ep93xx/cpu.c diff --git a/cpu/arm920t/ep93xx/led.c b/arch/arm/cpu/arm920t/ep93xx/led.c similarity index 100% rename from cpu/arm920t/ep93xx/led.c rename to arch/arm/cpu/arm920t/ep93xx/led.c diff --git a/cpu/arm920t/ep93xx/lowlevel_init.S b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S similarity index 100% rename from cpu/arm920t/ep93xx/lowlevel_init.S rename to arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S diff --git a/cpu/arm920t/ep93xx/speed.c b/arch/arm/cpu/arm920t/ep93xx/speed.c similarity index 100% rename from cpu/arm920t/ep93xx/speed.c rename to arch/arm/cpu/arm920t/ep93xx/speed.c diff --git a/arch/arm/cpu/arm920t/ep93xx/timer.c b/arch/arm/cpu/arm920t/ep93xx/timer.c new file mode 100644 index 0000000000..4a0ce4da64 --- /dev/null +++ b/arch/arm/cpu/arm920t/ep93xx/timer.c @@ -0,0 +1,143 @@ +/* + * Cirrus Logic EP93xx timer support. + * + * Copyright (C) 2009, 2010 Matthias Kaehlcke + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support, + * author unknown. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#define TIMER_CLKSEL (1 << 3) +#define TIMER_ENABLE (1 << 7) + +#define TIMER_FREQ 508469 /* ticks / second */ +#define TIMER_MAX_VAL 0xFFFFFFFF + +static struct ep93xx_timer +{ + unsigned long long ticks; + unsigned long last_read; +} timer; + +static inline unsigned long long usecs_to_ticks(unsigned long usecs) +{ + unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ; + do_div(ticks, 1000 * 1000); + + return ticks; +} + +static inline void read_timer(void) +{ + struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; + const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value); + + if (now >= timer.last_read) + timer.ticks += now - timer.last_read; + else + /* an overflow occurred */ + timer.ticks += TIMER_MAX_VAL - timer.last_read + now; + + timer.last_read = now; +} + +/* + * Get the number of ticks (in CONFIG_SYS_HZ resolution) + */ +unsigned long long get_ticks(void) +{ + unsigned long long sys_ticks; + + read_timer(); + + sys_ticks = timer.ticks * CONFIG_SYS_HZ; + do_div(sys_ticks, TIMER_FREQ); + + return sys_ticks; +} + +unsigned long get_timer_masked(void) +{ + return get_ticks(); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked() - base; +} + +void reset_timer_masked(void) +{ + read_timer(); + timer.ticks = 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +void __udelay(unsigned long usec) +{ + unsigned long long target; + + read_timer(); + + target = timer.ticks + usecs_to_ticks(usec); + + while (timer.ticks < target) + read_timer(); +} + +int timer_init(void) +{ + struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; + + /* use timer 3 with 508KHz and free running, not enabled now */ + writel(TIMER_CLKSEL, &timer_regs->timer3.control); + + /* set initial timer value */ + writel(TIMER_MAX_VAL, &timer_regs->timer3.load); + + /* Enable the timer */ + writel(TIMER_ENABLE | TIMER_CLKSEL, + &timer_regs->timer3.control); + + reset_timer_masked(); + + return 0; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +unsigned long get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds new file mode 100644 index 0000000000..5bfcb02317 --- /dev/null +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm920t/start.o (.text) + /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ + . = 0x1000; + LONG(0x53555243) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/cpu/arm920t/imx/Makefile b/arch/arm/cpu/arm920t/imx/Makefile similarity index 100% rename from cpu/arm920t/imx/Makefile rename to arch/arm/cpu/arm920t/imx/Makefile diff --git a/cpu/arm920t/imx/generic.c b/arch/arm/cpu/arm920t/imx/generic.c similarity index 100% rename from cpu/arm920t/imx/generic.c rename to arch/arm/cpu/arm920t/imx/generic.c diff --git a/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c similarity index 100% rename from cpu/arm920t/imx/speed.c rename to arch/arm/cpu/arm920t/imx/speed.c diff --git a/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c similarity index 100% rename from cpu/arm920t/imx/timer.c rename to arch/arm/cpu/arm920t/imx/timer.c diff --git a/cpu/arm920t/interrupts.c b/arch/arm/cpu/arm920t/interrupts.c similarity index 100% rename from cpu/arm920t/interrupts.c rename to arch/arm/cpu/arm920t/interrupts.c diff --git a/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile similarity index 100% rename from cpu/arm920t/ks8695/Makefile rename to arch/arm/cpu/arm920t/ks8695/Makefile diff --git a/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S similarity index 100% rename from cpu/arm920t/ks8695/lowlevel_init.S rename to arch/arm/cpu/arm920t/ks8695/lowlevel_init.S diff --git a/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c similarity index 100% rename from cpu/arm920t/ks8695/timer.c rename to arch/arm/cpu/arm920t/ks8695/timer.c diff --git a/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile similarity index 100% rename from cpu/arm920t/s3c24x0/Makefile rename to arch/arm/cpu/arm920t/s3c24x0/Makefile diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/arch/arm/cpu/arm920t/s3c24x0/interrupts.c similarity index 100% rename from cpu/arm920t/s3c24x0/interrupts.c rename to arch/arm/cpu/arm920t/s3c24x0/interrupts.c diff --git a/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c similarity index 100% rename from cpu/arm920t/s3c24x0/speed.c rename to arch/arm/cpu/arm920t/s3c24x0/speed.c diff --git a/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c similarity index 100% rename from cpu/arm920t/s3c24x0/timer.c rename to arch/arm/cpu/arm920t/s3c24x0/timer.c diff --git a/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c similarity index 100% rename from cpu/arm920t/s3c24x0/usb.c rename to arch/arm/cpu/arm920t/s3c24x0/usb.c diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c similarity index 100% rename from cpu/arm920t/s3c24x0/usb_ohci.c rename to arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c diff --git a/cpu/arm920t/s3c24x0/usb_ohci.h b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h similarity index 100% rename from cpu/arm920t/s3c24x0/usb_ohci.h rename to arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h diff --git a/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S similarity index 100% rename from cpu/arm920t/start.S rename to arch/arm/cpu/arm920t/start.S diff --git a/arch/arm/cpu/arm920t/u-boot.lds b/arch/arm/cpu/arm920t/u-boot.lds new file mode 100644 index 0000000000..a7decfcd7d --- /dev/null +++ b/arch/arm/cpu/arm920t/u-boot.lds @@ -0,0 +1,64 @@ +/* + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * Ming-Len Wu + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm925t/Makefile b/arch/arm/cpu/arm925t/Makefile similarity index 100% rename from cpu/arm925t/Makefile rename to arch/arm/cpu/arm925t/Makefile diff --git a/cpu/arm925t/config.mk b/arch/arm/cpu/arm925t/config.mk similarity index 100% rename from cpu/arm925t/config.mk rename to arch/arm/cpu/arm925t/config.mk diff --git a/cpu/arm925t/cpu.c b/arch/arm/cpu/arm925t/cpu.c similarity index 100% rename from cpu/arm925t/cpu.c rename to arch/arm/cpu/arm925t/cpu.c diff --git a/cpu/arm925t/omap925.c b/arch/arm/cpu/arm925t/omap925.c similarity index 100% rename from cpu/arm925t/omap925.c rename to arch/arm/cpu/arm925t/omap925.c diff --git a/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S similarity index 100% rename from cpu/arm925t/start.S rename to arch/arm/cpu/arm925t/start.S diff --git a/cpu/arm925t/timer.c b/arch/arm/cpu/arm925t/timer.c similarity index 100% rename from cpu/arm925t/timer.c rename to arch/arm/cpu/arm925t/timer.c diff --git a/arch/arm/cpu/arm925t/u-boot.lds b/arch/arm/cpu/arm925t/u-boot.lds new file mode 100644 index 0000000000..e21d6dc5a7 --- /dev/null +++ b/arch/arm/cpu/arm925t/u-boot.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm925t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile similarity index 100% rename from cpu/arm926ejs/Makefile rename to arch/arm/cpu/arm926ejs/Makefile diff --git a/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile similarity index 100% rename from cpu/arm926ejs/at91/Makefile rename to arch/arm/cpu/arm926ejs/at91/Makefile diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c similarity index 100% rename from cpu/arm926ejs/at91/at91cap9_devices.c rename to arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c similarity index 100% rename from cpu/arm926ejs/at91/at91sam9260_devices.c rename to arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c similarity index 100% rename from cpu/arm926ejs/at91/at91sam9261_devices.c rename to arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c similarity index 100% rename from cpu/arm926ejs/at91/at91sam9263_devices.c rename to arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c similarity index 100% rename from cpu/arm926ejs/at91/at91sam9m10g45_devices.c rename to arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c similarity index 100% rename from cpu/arm926ejs/at91/at91sam9rl_devices.c rename to arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c new file mode 100644 index 0000000000..ecf91f5187 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -0,0 +1,216 @@ +/* + * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] + * + * Copyright (C) 2005 David Brownell + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +static unsigned long cpu_clk_rate_hz; +static unsigned long main_clk_rate_hz; +static unsigned long mck_rate_hz; +static unsigned long plla_rate_hz; +static unsigned long pllb_rate_hz; +static u32 at91_pllb_usb_init; + +unsigned long get_cpu_clk_rate(void) +{ + return cpu_clk_rate_hz; +} + +unsigned long get_main_clk_rate(void) +{ + return main_clk_rate_hz; +} + +unsigned long get_mck_clk_rate(void) +{ + return mck_rate_hz; +} + +unsigned long get_plla_clk_rate(void) +{ + return plla_rate_hz; +} + +unsigned long get_pllb_clk_rate(void) +{ + return pllb_rate_hz; +} + +u32 get_pllb_init(void) +{ + return at91_pllb_usb_init; +} + +static unsigned long at91_css_to_rate(unsigned long css) +{ + switch (css) { + case AT91_PMC_MCKR_CSS_SLOW: + return AT91_SLOW_CLOCK; + case AT91_PMC_MCKR_CSS_MAIN: + return main_clk_rate_hz; + case AT91_PMC_MCKR_CSS_PLLA: + return plla_rate_hz; + case AT91_PMC_MCKR_CSS_PLLB: + return pllb_rate_hz; + } + + return 0; +} + +#ifdef CONFIG_USB_ATMEL +static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) +{ + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; +#if defined(CONFIG_AT91SAM9G20) + if (input < 2000000) + continue; +#endif + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; +#if defined(CONFIG_AT91SAM9G20) + if (mul > 63) + continue; +#endif + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; +fail: + return 0; +} +#endif + +static u32 at91_pll_rate(u32 freq, u32 reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; + + return freq; +} + +int at91_clock_init(unsigned long main_clock) +{ + unsigned freq, mckr; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK + unsigned tmp; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = readl(&pmc->mcfr); + } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); + tmp &= AT91_PMC_MCFR_MAINF_MASK; + main_clock = tmp * (AT91_SLOW_CLOCK / 16); + } +#endif + main_clk_rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); + +#ifdef CONFIG_USB_ATMEL + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | + AT91_PMC_PLLBR_USBDIV_2; + pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init); +#endif + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = readl(&pmc->mckr); +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) + /* plla divisor by 2 */ + plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); +#endif + mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = mck_rate_hz; + + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ +#if defined(CONFIG_AT91RM9200) + /* mdiv */ + mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); +#elif defined(CONFIG_AT91SAM9G20) + /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? + freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; + if (mckr & AT91_PMC_MCKR_MDIV_MASK) + freq /= 2; /* processor clock division */ +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == + (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) + ? freq / 3 + : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); +#else + mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); +#endif + cpu_clk_rate_hz = freq; + + return 0; +} diff --git a/cpu/arm926ejs/at91/config.mk b/arch/arm/cpu/arm926ejs/at91/config.mk similarity index 100% rename from cpu/arm926ejs/at91/config.mk rename to arch/arm/cpu/arm926ejs/at91/config.mk diff --git a/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c similarity index 100% rename from cpu/arm926ejs/at91/cpu.c rename to arch/arm/cpu/arm926ejs/at91/cpu.c diff --git a/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c similarity index 100% rename from cpu/arm926ejs/at91/led.c rename to arch/arm/cpu/arm926ejs/at91/led.c diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S similarity index 100% rename from cpu/arm926ejs/at91/lowlevel_init.S rename to arch/arm/cpu/arm926ejs/at91/lowlevel_init.S diff --git a/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c similarity index 100% rename from cpu/arm926ejs/at91/reset.c rename to arch/arm/cpu/arm926ejs/at91/reset.c diff --git a/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c similarity index 100% rename from cpu/arm926ejs/at91/timer.c rename to arch/arm/cpu/arm926ejs/at91/timer.c diff --git a/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk similarity index 100% rename from cpu/arm926ejs/config.mk rename to arch/arm/cpu/arm926ejs/config.mk diff --git a/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c similarity index 100% rename from cpu/arm926ejs/cpu.c rename to arch/arm/cpu/arm926ejs/cpu.c diff --git a/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile similarity index 100% rename from cpu/arm926ejs/davinci/Makefile rename to arch/arm/cpu/arm926ejs/davinci/Makefile diff --git a/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk similarity index 100% rename from cpu/arm926ejs/davinci/config.mk rename to arch/arm/cpu/arm926ejs/davinci/config.mk diff --git a/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c similarity index 100% rename from cpu/arm926ejs/davinci/cpu.c rename to arch/arm/cpu/arm926ejs/davinci/cpu.c diff --git a/cpu/arm926ejs/davinci/dm355.c b/arch/arm/cpu/arm926ejs/davinci/dm355.c similarity index 100% rename from cpu/arm926ejs/davinci/dm355.c rename to arch/arm/cpu/arm926ejs/davinci/dm355.c diff --git a/cpu/arm926ejs/davinci/dm365.c b/arch/arm/cpu/arm926ejs/davinci/dm365.c similarity index 100% rename from cpu/arm926ejs/davinci/dm365.c rename to arch/arm/cpu/arm926ejs/davinci/dm365.c diff --git a/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/cpu/arm926ejs/davinci/dm644x.c similarity index 100% rename from cpu/arm926ejs/davinci/dm644x.c rename to arch/arm/cpu/arm926ejs/davinci/dm644x.c diff --git a/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/cpu/arm926ejs/davinci/dm646x.c similarity index 100% rename from cpu/arm926ejs/davinci/dm646x.c rename to arch/arm/cpu/arm926ejs/davinci/dm646x.c diff --git a/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/cpu/arm926ejs/davinci/dp83848.c similarity index 100% rename from cpu/arm926ejs/davinci/dp83848.c rename to arch/arm/cpu/arm926ejs/davinci/dp83848.c diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S similarity index 100% rename from cpu/arm926ejs/davinci/lowlevel_init.S rename to arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S diff --git a/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c similarity index 100% rename from cpu/arm926ejs/davinci/lxt972.c rename to arch/arm/cpu/arm926ejs/davinci/lxt972.c diff --git a/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c similarity index 100% rename from cpu/arm926ejs/davinci/psc.c rename to arch/arm/cpu/arm926ejs/davinci/psc.c diff --git a/cpu/arm926ejs/davinci/reset.S b/arch/arm/cpu/arm926ejs/davinci/reset.S similarity index 100% rename from cpu/arm926ejs/davinci/reset.S rename to arch/arm/cpu/arm926ejs/davinci/reset.S diff --git a/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c similarity index 100% rename from cpu/arm926ejs/davinci/timer.c rename to arch/arm/cpu/arm926ejs/davinci/timer.c diff --git a/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile similarity index 100% rename from cpu/arm926ejs/kirkwood/Makefile rename to arch/arm/cpu/arm926ejs/kirkwood/Makefile diff --git a/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c similarity index 100% rename from cpu/arm926ejs/kirkwood/cpu.c rename to arch/arm/cpu/arm926ejs/kirkwood/cpu.c diff --git a/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c similarity index 100% rename from cpu/arm926ejs/kirkwood/dram.c rename to arch/arm/cpu/arm926ejs/kirkwood/dram.c diff --git a/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c similarity index 100% rename from cpu/arm926ejs/kirkwood/mpp.c rename to arch/arm/cpu/arm926ejs/kirkwood/mpp.c diff --git a/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c similarity index 100% rename from cpu/arm926ejs/kirkwood/timer.c rename to arch/arm/cpu/arm926ejs/kirkwood/timer.c diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile new file mode 100644 index 0000000000..76f01791a0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx25/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = generic.o timer.o +MX27OBJS = reset.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS += $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c similarity index 100% rename from cpu/arm926ejs/mx25/generic.c rename to arch/arm/cpu/arm926ejs/mx25/generic.c diff --git a/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c similarity index 100% rename from cpu/arm926ejs/mx25/reset.c rename to arch/arm/cpu/arm926ejs/mx25/reset.c diff --git a/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c similarity index 100% rename from cpu/arm926ejs/mx25/timer.c rename to arch/arm/cpu/arm926ejs/mx25/timer.c diff --git a/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile similarity index 100% rename from cpu/arm926ejs/mx27/Makefile rename to arch/arm/cpu/arm926ejs/mx27/Makefile diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c new file mode 100644 index 0000000000..ae2ce5841c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2008 Eric Jarrige + * Copyright (c) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_MXC_MMC +#include +#endif + +/* + * get the system pll clock in Hz + * + * mfi + mfn / (mfd +1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) +{ + unsigned int mfi = (pll >> 10) & 0xf; + unsigned int mfn = pll & 0x3ff; + unsigned int mfd = (pll >> 16) & 0x3ff; + unsigned int pd = (pll >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + + return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn), + (mfd + 1) * (pd + 1)); +} + +static ulong clk_in_32k(void) +{ + return 1024 * CONFIG_MX27_CLK32; +} + +static ulong clk_in_26m(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { + /* divide by 1.5 */ + return 26000000 * 2 / 3; + } else { + return 26000000; + } +} + +ulong imx_get_mpllclk(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + ulong cscr = readl(&pll->cscr); + ulong fref; + + if (cscr & CSCR_MCU_SEL) + fref = clk_in_26m(); + else + fref = clk_in_32k(); + + return imx_decode_pll(readl(&pll->mpctl0), fref); +} + +ulong imx_get_armclk(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + ulong cscr = readl(&pll->cscr); + ulong fref = imx_get_mpllclk(); + ulong div; + + if (!(cscr & CSCR_ARM_SRC_MPLL)) + fref = lldiv((fref * 2), 3); + + div = ((cscr >> 12) & 0x3) + 1; + + return lldiv(fref, div); +} + +ulong imx_get_ahbclk(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + ulong cscr = readl(&pll->cscr); + ulong fref = imx_get_mpllclk(); + ulong div; + + div = ((cscr >> 8) & 0x3) + 1; + + return lldiv(fref * 2, 3 * div); +} + +ulong imx_get_spllclk(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + ulong cscr = readl(&pll->cscr); + ulong fref; + + if (cscr & CSCR_SP_SEL) + fref = clk_in_26m(); + else + fref = clk_in_32k(); + + return imx_decode_pll(readl(&pll->spctl0), fref); +} + +static ulong imx_decode_perclk(ulong div) +{ + return lldiv((imx_get_mpllclk() * 2), (div * 3)); +} + +ulong imx_get_perclk1(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); +} + +ulong imx_get_perclk2(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); +} + +ulong imx_get_perclk3(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); +} + +ulong imx_get_perclk4(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1); +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo (void) +{ + char buf[32]; + + printf("CPU: Freescale i.MX27 at %s MHz\n\n", + strmhz(buf, imx_get_mpllclk())); + return 0; +} +#endif + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FEC_MXC) + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + /* enable FEC clock */ + writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); + writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); + return fecmxc_initialize(bis); +#else + return 0; +#endif +} + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_MXC_MMC + return mxc_mmc_init(bis); +#else + return 0; +#endif +} + +void imx_gpio_mode(int gpio_mode) +{ + struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; + unsigned int pin = gpio_mode & GPIO_PIN_MASK; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; + unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT; + unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT; + unsigned int tmp; + + /* Pullup enable */ + if (gpio_mode & GPIO_PUEN) { + writel(readl(®s->port[port].puen) | (1 << pin), + ®s->port[port].puen); + } else { + writel(readl(®s->port[port].puen) & ~(1 << pin), + ®s->port[port].puen); + } + + /* Data direction */ + if (gpio_mode & GPIO_OUT) { + writel(readl(®s->port[port].ddir) | 1 << pin, + ®s->port[port].ddir); + } else { + writel(readl(®s->port[port].ddir) & ~(1 << pin), + ®s->port[port].ddir); + } + + /* Primary / alternate function */ + if (gpio_mode & GPIO_AF) { + writel(readl(®s->port[port].gpr) | (1 << pin), + ®s->port[port].gpr); + } else { + writel(readl(®s->port[port].gpr) & ~(1 << pin), + ®s->port[port].gpr); + } + + /* use as gpio? */ + if (!(gpio_mode & (GPIO_PF | GPIO_AF))) { + writel(readl(®s->port[port].gius) | (1 << pin), + ®s->port[port].gius); + } else { + writel(readl(®s->port[port].gius) & ~(1 << pin), + ®s->port[port].gius); + } + + /* Output / input configuration */ + if (pin < 16) { + tmp = readl(®s->port[port].ocr1); + tmp &= ~(3 << (pin * 2)); + tmp |= (ocr << (pin * 2)); + writel(tmp, ®s->port[port].ocr1); + + writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)), + ®s->port[port].iconfa1); + writel(readl(®s->port[port].iconfa1) | aout << (pin * 2), + ®s->port[port].iconfa1); + writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)), + ®s->port[port].iconfb1); + writel(readl(®s->port[port].iconfb1) | bout << (pin * 2), + ®s->port[port].iconfb1); + } else { + pin -= 16; + + tmp = readl(®s->port[port].ocr2); + tmp &= ~(3 << (pin * 2)); + tmp |= (ocr << (pin * 2)); + writel(tmp, ®s->port[port].ocr2); + + writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)), + ®s->port[port].iconfa2); + writel(readl(®s->port[port].iconfa2) | aout << (pin * 2), + ®s->port[port].iconfa2); + writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)), + ®s->port[port].iconfb2); + writel(readl(®s->port[port].iconfb2) | bout << (pin * 2), + ®s->port[port].iconfb2); + } +} + +#ifdef CONFIG_MXC_UART +void mx27_uart_init_pins(void) +{ + int i; + unsigned int mode[] = { + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +} +#endif /* CONFIG_MXC_UART */ + +#ifdef CONFIG_FEC_MXC +void mx27_fec_init_pins(void) +{ + int i; + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_CLR, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); +} +#endif /* CONFIG_FEC_MXC */ + +#ifdef CONFIG_MXC_MMC +void mx27_sd1_init_pins(void) +{ + int i; + unsigned int mode[] = { + PE18_PF_SD1_D0, + PE19_PF_SD1_D1, + PE20_PF_SD1_D2, + PE21_PF_SD1_D3, + PE22_PF_SD1_CMD, + PE23_PF_SD1_CLK, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +} + +void mx27_sd2_init_pins(void) +{ + int i; + unsigned int mode[] = { + PB4_PF_SD2_D0, + PB5_PF_SD2_D1, + PB6_PF_SD2_D2, + PB7_PF_SD2_D3, + PB8_PF_SD2_CMD, + PB9_PF_SD2_CLK, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +} +#endif /* CONFIG_MXC_MMC */ diff --git a/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c similarity index 100% rename from cpu/arm926ejs/mx27/reset.c rename to arch/arm/cpu/arm926ejs/mx27/reset.c diff --git a/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c similarity index 100% rename from cpu/arm926ejs/mx27/timer.c rename to arch/arm/cpu/arm926ejs/mx27/timer.c diff --git a/cpu/arm926ejs/nomadik/Makefile b/arch/arm/cpu/arm926ejs/nomadik/Makefile similarity index 100% rename from cpu/arm926ejs/nomadik/Makefile rename to arch/arm/cpu/arm926ejs/nomadik/Makefile diff --git a/cpu/arm926ejs/nomadik/gpio.c b/arch/arm/cpu/arm926ejs/nomadik/gpio.c similarity index 100% rename from cpu/arm926ejs/nomadik/gpio.c rename to arch/arm/cpu/arm926ejs/nomadik/gpio.c diff --git a/cpu/arm926ejs/nomadik/reset.S b/arch/arm/cpu/arm926ejs/nomadik/reset.S similarity index 100% rename from cpu/arm926ejs/nomadik/reset.S rename to arch/arm/cpu/arm926ejs/nomadik/reset.S diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/cpu/arm926ejs/nomadik/timer.c new file mode 100644 index 0000000000..1d98ef3eb3 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/nomadik/timer.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * The timer is a decrementer, we'll left it free running at 2.4MHz. + * We have 2.4 ticks per microsecond and an overflow in almost 30min + */ +#define TIMER_CLOCK (24 * 100 * 1000) +#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */ +#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */ +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) + +/* macro to read the decrementing 32 bit timer as an increasing count */ +#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) + +/* Configure a free-running, auto-wrap counter with no prescaler */ +int timer_init(void) +{ + writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, + CONFIG_SYS_TIMERBASE + MTU_CR(0)); + reset_timer(); + return 0; +} + +/* Restart counting from 0 */ +void reset_timer(void) +{ + ulong val; + writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); + /* + * The load-register isn't really immediate: it changes on clock + * edges, so we must wait for our newly-written value to appear. + * Since we might miss reading 0, wait for any change in value. + */ + val = READ_TIMER(); + while (READ_TIMER() == val) + ; +} + +/* Return how many HZ passed since "base" */ +ulong get_timer(ulong base) +{ + return TICKS_TO_HZ(READ_TIMER()) - base; +} + +/* Delay x useconds */ +void __udelay(unsigned long usec) +{ + ulong ini, end; + + ini = READ_TIMER(); + end = ini + USEC_TO_COUNT(usec); + while ((signed)(end - READ_TIMER()) > 0) + ; +} diff --git a/cpu/arm926ejs/omap/Makefile b/arch/arm/cpu/arm926ejs/omap/Makefile similarity index 100% rename from cpu/arm926ejs/omap/Makefile rename to arch/arm/cpu/arm926ejs/omap/Makefile diff --git a/cpu/arm926ejs/omap/cpuinfo.c b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c similarity index 100% rename from cpu/arm926ejs/omap/cpuinfo.c rename to arch/arm/cpu/arm926ejs/omap/cpuinfo.c diff --git a/cpu/arm926ejs/omap/reset.S b/arch/arm/cpu/arm926ejs/omap/reset.S similarity index 100% rename from cpu/arm926ejs/omap/reset.S rename to arch/arm/cpu/arm926ejs/omap/reset.S diff --git a/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c similarity index 100% rename from cpu/arm926ejs/omap/timer.c rename to arch/arm/cpu/arm926ejs/omap/timer.c diff --git a/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile similarity index 100% rename from cpu/arm926ejs/spear/Makefile rename to arch/arm/cpu/arm926ejs/spear/Makefile diff --git a/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c similarity index 100% rename from cpu/arm926ejs/spear/reset.c rename to arch/arm/cpu/arm926ejs/spear/reset.c diff --git a/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c similarity index 100% rename from cpu/arm926ejs/spear/timer.c rename to arch/arm/cpu/arm926ejs/spear/timer.c diff --git a/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S similarity index 100% rename from cpu/arm926ejs/start.S rename to arch/arm/cpu/arm926ejs/start.S diff --git a/arch/arm/cpu/arm926ejs/u-boot.lds b/arch/arm/cpu/arm926ejs/u-boot.lds new file mode 100644 index 0000000000..ecbc58c7c2 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm926ejs/versatile/Makefile b/arch/arm/cpu/arm926ejs/versatile/Makefile similarity index 100% rename from cpu/arm926ejs/versatile/Makefile rename to arch/arm/cpu/arm926ejs/versatile/Makefile diff --git a/cpu/arm926ejs/versatile/reset.S b/arch/arm/cpu/arm926ejs/versatile/reset.S similarity index 100% rename from cpu/arm926ejs/versatile/reset.S rename to arch/arm/cpu/arm926ejs/versatile/reset.S diff --git a/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c similarity index 100% rename from cpu/arm926ejs/versatile/timer.c rename to arch/arm/cpu/arm926ejs/versatile/timer.c diff --git a/cpu/arm946es/Makefile b/arch/arm/cpu/arm946es/Makefile similarity index 100% rename from cpu/arm946es/Makefile rename to arch/arm/cpu/arm946es/Makefile diff --git a/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk similarity index 100% rename from cpu/arm946es/config.mk rename to arch/arm/cpu/arm946es/config.mk diff --git a/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c similarity index 100% rename from cpu/arm946es/cpu.c rename to arch/arm/cpu/arm946es/cpu.c diff --git a/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S similarity index 100% rename from cpu/arm946es/start.S rename to arch/arm/cpu/arm946es/start.S diff --git a/arch/arm/cpu/arm946es/u-boot.lds b/arch/arm/cpu/arm946es/u-boot.lds new file mode 100644 index 0000000000..fef21c7587 --- /dev/null +++ b/arch/arm/cpu/arm946es/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm946es/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm_cortexa8/Makefile b/arch/arm/cpu/arm_cortexa8/Makefile similarity index 100% rename from cpu/arm_cortexa8/Makefile rename to arch/arm/cpu/arm_cortexa8/Makefile diff --git a/cpu/arm_cortexa8/config.mk b/arch/arm/cpu/arm_cortexa8/config.mk similarity index 100% rename from cpu/arm_cortexa8/config.mk rename to arch/arm/cpu/arm_cortexa8/config.mk diff --git a/cpu/arm_cortexa8/cpu.c b/arch/arm/cpu/arm_cortexa8/cpu.c similarity index 100% rename from cpu/arm_cortexa8/cpu.c rename to arch/arm/cpu/arm_cortexa8/cpu.c diff --git a/cpu/arm_cortexa8/mx51/Makefile b/arch/arm/cpu/arm_cortexa8/mx51/Makefile similarity index 100% rename from cpu/arm_cortexa8/mx51/Makefile rename to arch/arm/cpu/arm_cortexa8/mx51/Makefile diff --git a/cpu/arm_cortexa8/mx51/clock.c b/arch/arm/cpu/arm_cortexa8/mx51/clock.c similarity index 100% rename from cpu/arm_cortexa8/mx51/clock.c rename to arch/arm/cpu/arm_cortexa8/mx51/clock.c diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/arch/arm/cpu/arm_cortexa8/mx51/iomux.c similarity index 100% rename from cpu/arm_cortexa8/mx51/iomux.c rename to arch/arm/cpu/arm_cortexa8/mx51/iomux.c diff --git a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S b/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S new file mode 100644 index 0000000000..783c81f72a --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S @@ -0,0 +1,291 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + cmp r3, #0x10 /* r3 contains the silicon rev */ + + /* disable write combine for TO 2 and lower revs */ + orrls r0, r0, #(1 << 25) + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ +.endm /* init_aips */ + +/* M4IF setup */ +.macro init_m4if + /* VPU and IPU given higher priority (0x4) + * IPU accesses with ID=0x1 given highest priority (=0xA) + */ + ldr r0, =M4IF_BASE_ADDR + + ldr r1, =0x00000203 + str r1, [r0, #0x40] + + ldr r1, =0x0 + str r1, [r0, #0x44] + + ldr r1, =0x00120125 + str r1, [r0, #0x9C] + + ldr r1, =0x001901A3 + str r1, [r0, #0x48] + +.endm /* init_m4if */ + +.macro setup_pll pll, freq + ldr r2, =\pll + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + mov r1, #0x2 + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + str r3, [r2, #PLL_DP_OP] + str r3, [r2, #PLL_DP_HFS_OP] + + str r4, [r2, #PLL_DP_MFD] + str r4, [r2, #PLL_DP_HFS_MFD] + + str r5, [r2, #PLL_DP_MFN] + str r5, [r2, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] +1: ldr r1, [r2, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + ldr r1, =0x0 + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x00000300 + str r1, [r0, #CLKCTL_CCGR6] + + /* Disable IPU and HSC dividers */ + mov r1, #0x60000 + str r1, [r0, #CLKCTL_CCDR] + + /* Make sure to switch the DDR away from PLL 1 */ + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + mov r3, #DP_OP_800 + mov r4, #DP_MFD_800 + mov r5, #DP_MFN_800 + setup_pll PLL1_BASE_ADDR + + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL3_BASE_ADDR + + /* Switch peripheral to PLL 3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x000010C0 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x13239145 + str r1, [r0, #CLKCTL_CBCDR] + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL2_BASE_ADDR + + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + ldr r1, =0x000020C0 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + str r1, [r0, #CLKCTL_CBCMR] + + mov r3, #DP_OP_216 + mov r4, #DP_MFD_216 + mov r5, #DP_MFN_216 + setup_pll PLL3_BASE_ADDR + + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000725 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + + /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 + movls r1, #0x1 + movhi r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1 */ + mov r1, #0 + str r1, [r0, #CLKCTL_CCSR] + + /* setup the rest */ + /* Use lp_apm (24MHz) source for perclk */ + ldr r1, =0x000020C2 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + str r1, [r0, #CLKCTL_CBCMR] + /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ + ldr r1, =CONFIG_SYS_CLKTL_CBCDR + str r1, [r0, #CLKCTL_CBCDR] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + + /* Use PLL 2 for UART's, get 66.5MHz from it */ + ldr r1, =0xA5A2A020 + str r1, [r0, #CLKCTL_CSCMR1] + ldr r1, =0x00C30321 + str r1, [r0, #CLKCTL_CSCDR1] + + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.macro setup_wdog + ldr r0, =WDOG1_BASE_ADDR + mov r1, #0x30 + strh r1, [r0] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + ldr r0, =GPIO1_BASE_ADDR + ldr r1, [r0, #0x0] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x0] + ldr r1, [r0, #0x4] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x4] + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + init_l2cc + + init_aips + + init_m4if + + init_clock + + /* r12 saved upper lr*/ + mov pc,lr + +/* Board level setting value */ +DDR_PERCHARGE_CMD: .word 0x04008008 +DDR_REFRESH_CMD: .word 0x00008010 +DDR_LMR1_W: .word 0x00338018 +DDR_LMR_CMD: .word 0xB2220000 +DDR_TIMING_W: .word 0xB02567A9 +DDR_MISC_W: .word 0x000A0104 diff --git a/cpu/arm_cortexa8/mx51/soc.c b/arch/arm/cpu/arm_cortexa8/mx51/soc.c similarity index 100% rename from cpu/arm_cortexa8/mx51/soc.c rename to arch/arm/cpu/arm_cortexa8/mx51/soc.c diff --git a/cpu/arm_cortexa8/mx51/speed.c b/arch/arm/cpu/arm_cortexa8/mx51/speed.c similarity index 100% rename from cpu/arm_cortexa8/mx51/speed.c rename to arch/arm/cpu/arm_cortexa8/mx51/speed.c diff --git a/cpu/arm_cortexa8/mx51/timer.c b/arch/arm/cpu/arm_cortexa8/mx51/timer.c similarity index 100% rename from cpu/arm_cortexa8/mx51/timer.c rename to arch/arm/cpu/arm_cortexa8/mx51/timer.c diff --git a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds b/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds new file mode 100644 index 0000000000..2953b93632 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds @@ -0,0 +1,61 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm_cortexa8/start.o + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile similarity index 100% rename from cpu/arm_cortexa8/omap3/Makefile rename to arch/arm/cpu/arm_cortexa8/omap3/Makefile diff --git a/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/arm_cortexa8/omap3/board.c similarity index 100% rename from cpu/arm_cortexa8/omap3/board.c rename to arch/arm/cpu/arm_cortexa8/omap3/board.c diff --git a/cpu/arm_cortexa8/omap3/cache.S b/arch/arm/cpu/arm_cortexa8/omap3/cache.S similarity index 100% rename from cpu/arm_cortexa8/omap3/cache.S rename to arch/arm/cpu/arm_cortexa8/omap3/cache.S diff --git a/cpu/arm_cortexa8/omap3/clock.c b/arch/arm/cpu/arm_cortexa8/omap3/clock.c similarity index 100% rename from cpu/arm_cortexa8/omap3/clock.c rename to arch/arm/cpu/arm_cortexa8/omap3/clock.c diff --git a/cpu/arm_cortexa8/omap3/gpio.c b/arch/arm/cpu/arm_cortexa8/omap3/gpio.c similarity index 100% rename from cpu/arm_cortexa8/omap3/gpio.c rename to arch/arm/cpu/arm_cortexa8/omap3/gpio.c diff --git a/cpu/arm_cortexa8/omap3/lowlevel_init.S b/arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S similarity index 100% rename from cpu/arm_cortexa8/omap3/lowlevel_init.S rename to arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S diff --git a/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/arm_cortexa8/omap3/mem.c similarity index 100% rename from cpu/arm_cortexa8/omap3/mem.c rename to arch/arm/cpu/arm_cortexa8/omap3/mem.c diff --git a/cpu/arm_cortexa8/omap3/reset.S b/arch/arm/cpu/arm_cortexa8/omap3/reset.S similarity index 100% rename from cpu/arm_cortexa8/omap3/reset.S rename to arch/arm/cpu/arm_cortexa8/omap3/reset.S diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c similarity index 100% rename from cpu/arm_cortexa8/omap3/sys_info.c rename to arch/arm/cpu/arm_cortexa8/omap3/sys_info.c diff --git a/cpu/arm_cortexa8/omap3/syslib.c b/arch/arm/cpu/arm_cortexa8/omap3/syslib.c similarity index 100% rename from cpu/arm_cortexa8/omap3/syslib.c rename to arch/arm/cpu/arm_cortexa8/omap3/syslib.c diff --git a/cpu/arm_cortexa8/omap3/timer.c b/arch/arm/cpu/arm_cortexa8/omap3/timer.c similarity index 100% rename from cpu/arm_cortexa8/omap3/timer.c rename to arch/arm/cpu/arm_cortexa8/omap3/timer.c diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile similarity index 100% rename from cpu/arm_cortexa8/s5pc1xx/Makefile rename to arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S b/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S new file mode 100644 index 0000000000..906118d820 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang + * + * based on arch/arm/cpu/arm_cortexa8/omap3/cache.S + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.align 5 +.global invalidate_dcache +.global l2_cache_enable +.global l2_cache_disable + +/* + * invalidate_dcache() + * Invalidate the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + */ +invalidate_dcache: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + cmp r0, #0xC100 @ check if the cpu is s5pc100 + + beq finished_inval @ s5pc100 doesn't need this + @ routine + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + +l2_cache_enable: + push {r0, r1, r2, lr} + mrc 15, 0, r3, cr1, cr0, 1 + orr r3, r3, #2 + mcr 15, 0, r3, cr1, cr0, 1 + pop {r1, r2, r3, pc} + +l2_cache_disable: + push {r0, r1, r2, lr} + mrc 15, 0, r3, cr1, cr0, 1 + bic r3, r3, #2 + mcr 15, 0, r3, cr1, cr0, 1 + pop {r1, r2, r3, pc} diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c similarity index 100% rename from cpu/arm_cortexa8/s5pc1xx/clock.c rename to arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c diff --git a/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c similarity index 100% rename from cpu/arm_cortexa8/s5pc1xx/cpu_info.c rename to arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c diff --git a/cpu/arm_cortexa8/s5pc1xx/reset.S b/arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S similarity index 100% rename from cpu/arm_cortexa8/s5pc1xx/reset.S rename to arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c similarity index 100% rename from cpu/arm_cortexa8/s5pc1xx/sromc.c rename to arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c diff --git a/cpu/arm_cortexa8/s5pc1xx/timer.c b/arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c similarity index 100% rename from cpu/arm_cortexa8/s5pc1xx/timer.c rename to arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c diff --git a/cpu/arm_cortexa8/start.S b/arch/arm/cpu/arm_cortexa8/start.S similarity index 100% rename from cpu/arm_cortexa8/start.S rename to arch/arm/cpu/arm_cortexa8/start.S diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/arch/arm/cpu/arm_cortexa8/u-boot.lds new file mode 100644 index 0000000000..820e3a1043 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/cpu/arm_intcm/Makefile b/arch/arm/cpu/arm_intcm/Makefile similarity index 100% rename from cpu/arm_intcm/Makefile rename to arch/arm/cpu/arm_intcm/Makefile diff --git a/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk similarity index 100% rename from cpu/arm_intcm/config.mk rename to arch/arm/cpu/arm_intcm/config.mk diff --git a/cpu/arm_intcm/cpu.c b/arch/arm/cpu/arm_intcm/cpu.c similarity index 100% rename from cpu/arm_intcm/cpu.c rename to arch/arm/cpu/arm_intcm/cpu.c diff --git a/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S similarity index 100% rename from cpu/arm_intcm/start.S rename to arch/arm/cpu/arm_intcm/start.S diff --git a/arch/arm/cpu/arm_intcm/u-boot.lds b/arch/arm/cpu/arm_intcm/u-boot.lds new file mode 100644 index 0000000000..4ed7d8906d --- /dev/null +++ b/arch/arm/cpu/arm_intcm/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm_intcm/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile similarity index 100% rename from cpu/ixp/Makefile rename to arch/arm/cpu/ixp/Makefile diff --git a/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk similarity index 100% rename from cpu/ixp/config.mk rename to arch/arm/cpu/ixp/config.mk diff --git a/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c similarity index 100% rename from cpu/ixp/cpu.c rename to arch/arm/cpu/ixp/cpu.c diff --git a/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c similarity index 100% rename from cpu/ixp/interrupts.c rename to arch/arm/cpu/ixp/interrupts.c diff --git a/cpu/ixp/npe/IxEthAcc.c b/arch/arm/cpu/ixp/npe/IxEthAcc.c similarity index 100% rename from cpu/ixp/npe/IxEthAcc.c rename to arch/arm/cpu/ixp/npe/IxEthAcc.c diff --git a/cpu/ixp/npe/IxEthAccCommon.c b/arch/arm/cpu/ixp/npe/IxEthAccCommon.c similarity index 100% rename from cpu/ixp/npe/IxEthAccCommon.c rename to arch/arm/cpu/ixp/npe/IxEthAccCommon.c diff --git a/cpu/ixp/npe/IxEthAccControlInterface.c b/arch/arm/cpu/ixp/npe/IxEthAccControlInterface.c similarity index 100% rename from cpu/ixp/npe/IxEthAccControlInterface.c rename to arch/arm/cpu/ixp/npe/IxEthAccControlInterface.c diff --git a/cpu/ixp/npe/IxEthAccDataPlane.c b/arch/arm/cpu/ixp/npe/IxEthAccDataPlane.c similarity index 100% rename from cpu/ixp/npe/IxEthAccDataPlane.c rename to arch/arm/cpu/ixp/npe/IxEthAccDataPlane.c diff --git a/cpu/ixp/npe/IxEthAccMac.c b/arch/arm/cpu/ixp/npe/IxEthAccMac.c similarity index 100% rename from cpu/ixp/npe/IxEthAccMac.c rename to arch/arm/cpu/ixp/npe/IxEthAccMac.c diff --git a/cpu/ixp/npe/IxEthAccMii.c b/arch/arm/cpu/ixp/npe/IxEthAccMii.c similarity index 100% rename from cpu/ixp/npe/IxEthAccMii.c rename to arch/arm/cpu/ixp/npe/IxEthAccMii.c diff --git a/cpu/ixp/npe/IxEthDBAPI.c b/arch/arm/cpu/ixp/npe/IxEthDBAPI.c similarity index 100% rename from cpu/ixp/npe/IxEthDBAPI.c rename to arch/arm/cpu/ixp/npe/IxEthDBAPI.c diff --git a/cpu/ixp/npe/IxEthDBAPISupport.c b/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c similarity index 100% rename from cpu/ixp/npe/IxEthDBAPISupport.c rename to arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c diff --git a/cpu/ixp/npe/IxEthDBCore.c b/arch/arm/cpu/ixp/npe/IxEthDBCore.c similarity index 100% rename from cpu/ixp/npe/IxEthDBCore.c rename to arch/arm/cpu/ixp/npe/IxEthDBCore.c diff --git a/cpu/ixp/npe/IxEthDBEvents.c b/arch/arm/cpu/ixp/npe/IxEthDBEvents.c similarity index 100% rename from cpu/ixp/npe/IxEthDBEvents.c rename to arch/arm/cpu/ixp/npe/IxEthDBEvents.c diff --git a/cpu/ixp/npe/IxEthDBFeatures.c b/arch/arm/cpu/ixp/npe/IxEthDBFeatures.c similarity index 100% rename from cpu/ixp/npe/IxEthDBFeatures.c rename to arch/arm/cpu/ixp/npe/IxEthDBFeatures.c diff --git a/cpu/ixp/npe/IxEthDBFirewall.c b/arch/arm/cpu/ixp/npe/IxEthDBFirewall.c similarity index 100% rename from cpu/ixp/npe/IxEthDBFirewall.c rename to arch/arm/cpu/ixp/npe/IxEthDBFirewall.c diff --git a/cpu/ixp/npe/IxEthDBHashtable.c b/arch/arm/cpu/ixp/npe/IxEthDBHashtable.c similarity index 100% rename from cpu/ixp/npe/IxEthDBHashtable.c rename to arch/arm/cpu/ixp/npe/IxEthDBHashtable.c diff --git a/cpu/ixp/npe/IxEthDBLearning.c b/arch/arm/cpu/ixp/npe/IxEthDBLearning.c similarity index 100% rename from cpu/ixp/npe/IxEthDBLearning.c rename to arch/arm/cpu/ixp/npe/IxEthDBLearning.c diff --git a/cpu/ixp/npe/IxEthDBMem.c b/arch/arm/cpu/ixp/npe/IxEthDBMem.c similarity index 100% rename from cpu/ixp/npe/IxEthDBMem.c rename to arch/arm/cpu/ixp/npe/IxEthDBMem.c diff --git a/cpu/ixp/npe/IxEthDBNPEAdaptor.c b/arch/arm/cpu/ixp/npe/IxEthDBNPEAdaptor.c similarity index 100% rename from cpu/ixp/npe/IxEthDBNPEAdaptor.c rename to arch/arm/cpu/ixp/npe/IxEthDBNPEAdaptor.c diff --git a/cpu/ixp/npe/IxEthDBPortUpdate.c b/arch/arm/cpu/ixp/npe/IxEthDBPortUpdate.c similarity index 100% rename from cpu/ixp/npe/IxEthDBPortUpdate.c rename to arch/arm/cpu/ixp/npe/IxEthDBPortUpdate.c diff --git a/cpu/ixp/npe/IxEthDBReports.c b/arch/arm/cpu/ixp/npe/IxEthDBReports.c similarity index 100% rename from cpu/ixp/npe/IxEthDBReports.c rename to arch/arm/cpu/ixp/npe/IxEthDBReports.c diff --git a/cpu/ixp/npe/IxEthDBSearch.c b/arch/arm/cpu/ixp/npe/IxEthDBSearch.c similarity index 100% rename from cpu/ixp/npe/IxEthDBSearch.c rename to arch/arm/cpu/ixp/npe/IxEthDBSearch.c diff --git a/cpu/ixp/npe/IxEthDBSpanningTree.c b/arch/arm/cpu/ixp/npe/IxEthDBSpanningTree.c similarity index 100% rename from cpu/ixp/npe/IxEthDBSpanningTree.c rename to arch/arm/cpu/ixp/npe/IxEthDBSpanningTree.c diff --git a/cpu/ixp/npe/IxEthDBUtil.c b/arch/arm/cpu/ixp/npe/IxEthDBUtil.c similarity index 100% rename from cpu/ixp/npe/IxEthDBUtil.c rename to arch/arm/cpu/ixp/npe/IxEthDBUtil.c diff --git a/cpu/ixp/npe/IxEthDBVlan.c b/arch/arm/cpu/ixp/npe/IxEthDBVlan.c similarity index 100% rename from cpu/ixp/npe/IxEthDBVlan.c rename to arch/arm/cpu/ixp/npe/IxEthDBVlan.c diff --git a/cpu/ixp/npe/IxEthDBWiFi.c b/arch/arm/cpu/ixp/npe/IxEthDBWiFi.c similarity index 100% rename from cpu/ixp/npe/IxEthDBWiFi.c rename to arch/arm/cpu/ixp/npe/IxEthDBWiFi.c diff --git a/cpu/ixp/npe/IxEthMii.c b/arch/arm/cpu/ixp/npe/IxEthMii.c similarity index 100% rename from cpu/ixp/npe/IxEthMii.c rename to arch/arm/cpu/ixp/npe/IxEthMii.c diff --git a/cpu/ixp/npe/IxFeatureCtrl.c b/arch/arm/cpu/ixp/npe/IxFeatureCtrl.c similarity index 100% rename from cpu/ixp/npe/IxFeatureCtrl.c rename to arch/arm/cpu/ixp/npe/IxFeatureCtrl.c diff --git a/cpu/ixp/npe/IxNpeDl.c b/arch/arm/cpu/ixp/npe/IxNpeDl.c similarity index 100% rename from cpu/ixp/npe/IxNpeDl.c rename to arch/arm/cpu/ixp/npe/IxNpeDl.c diff --git a/cpu/ixp/npe/IxNpeDlImageMgr.c b/arch/arm/cpu/ixp/npe/IxNpeDlImageMgr.c similarity index 100% rename from cpu/ixp/npe/IxNpeDlImageMgr.c rename to arch/arm/cpu/ixp/npe/IxNpeDlImageMgr.c diff --git a/cpu/ixp/npe/IxNpeDlNpeMgr.c b/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c similarity index 100% rename from cpu/ixp/npe/IxNpeDlNpeMgr.c rename to arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c diff --git a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c b/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c similarity index 100% rename from cpu/ixp/npe/IxNpeDlNpeMgrUtils.c rename to arch/arm/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c diff --git a/cpu/ixp/npe/IxNpeMh.c b/arch/arm/cpu/ixp/npe/IxNpeMh.c similarity index 100% rename from cpu/ixp/npe/IxNpeMh.c rename to arch/arm/cpu/ixp/npe/IxNpeMh.c diff --git a/cpu/ixp/npe/IxNpeMhConfig.c b/arch/arm/cpu/ixp/npe/IxNpeMhConfig.c similarity index 100% rename from cpu/ixp/npe/IxNpeMhConfig.c rename to arch/arm/cpu/ixp/npe/IxNpeMhConfig.c diff --git a/cpu/ixp/npe/IxNpeMhReceive.c b/arch/arm/cpu/ixp/npe/IxNpeMhReceive.c similarity index 100% rename from cpu/ixp/npe/IxNpeMhReceive.c rename to arch/arm/cpu/ixp/npe/IxNpeMhReceive.c diff --git a/cpu/ixp/npe/IxNpeMhSend.c b/arch/arm/cpu/ixp/npe/IxNpeMhSend.c similarity index 100% rename from cpu/ixp/npe/IxNpeMhSend.c rename to arch/arm/cpu/ixp/npe/IxNpeMhSend.c diff --git a/cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c b/arch/arm/cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c similarity index 100% rename from cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c rename to arch/arm/cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c diff --git a/cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c b/arch/arm/cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c similarity index 100% rename from cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c rename to arch/arm/cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c diff --git a/cpu/ixp/npe/IxOsalBufferMgt.c b/arch/arm/cpu/ixp/npe/IxOsalBufferMgt.c similarity index 100% rename from cpu/ixp/npe/IxOsalBufferMgt.c rename to arch/arm/cpu/ixp/npe/IxOsalBufferMgt.c diff --git a/cpu/ixp/npe/IxOsalIoMem.c b/arch/arm/cpu/ixp/npe/IxOsalIoMem.c similarity index 100% rename from cpu/ixp/npe/IxOsalIoMem.c rename to arch/arm/cpu/ixp/npe/IxOsalIoMem.c diff --git a/cpu/ixp/npe/IxOsalOsCacheMMU.c b/arch/arm/cpu/ixp/npe/IxOsalOsCacheMMU.c similarity index 100% rename from cpu/ixp/npe/IxOsalOsCacheMMU.c rename to arch/arm/cpu/ixp/npe/IxOsalOsCacheMMU.c diff --git a/cpu/ixp/npe/IxOsalOsMsgQ.c b/arch/arm/cpu/ixp/npe/IxOsalOsMsgQ.c similarity index 100% rename from cpu/ixp/npe/IxOsalOsMsgQ.c rename to arch/arm/cpu/ixp/npe/IxOsalOsMsgQ.c diff --git a/cpu/ixp/npe/IxOsalOsSemaphore.c b/arch/arm/cpu/ixp/npe/IxOsalOsSemaphore.c similarity index 100% rename from cpu/ixp/npe/IxOsalOsSemaphore.c rename to arch/arm/cpu/ixp/npe/IxOsalOsSemaphore.c diff --git a/cpu/ixp/npe/IxOsalOsServices.c b/arch/arm/cpu/ixp/npe/IxOsalOsServices.c similarity index 100% rename from cpu/ixp/npe/IxOsalOsServices.c rename to arch/arm/cpu/ixp/npe/IxOsalOsServices.c diff --git a/cpu/ixp/npe/IxOsalOsThread.c b/arch/arm/cpu/ixp/npe/IxOsalOsThread.c similarity index 100% rename from cpu/ixp/npe/IxOsalOsThread.c rename to arch/arm/cpu/ixp/npe/IxOsalOsThread.c diff --git a/cpu/ixp/npe/IxQMgrAqmIf.c b/arch/arm/cpu/ixp/npe/IxQMgrAqmIf.c similarity index 100% rename from cpu/ixp/npe/IxQMgrAqmIf.c rename to arch/arm/cpu/ixp/npe/IxQMgrAqmIf.c diff --git a/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c similarity index 100% rename from cpu/ixp/npe/IxQMgrDispatcher.c rename to arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c diff --git a/cpu/ixp/npe/IxQMgrInit.c b/arch/arm/cpu/ixp/npe/IxQMgrInit.c similarity index 100% rename from cpu/ixp/npe/IxQMgrInit.c rename to arch/arm/cpu/ixp/npe/IxQMgrInit.c diff --git a/cpu/ixp/npe/IxQMgrQAccess.c b/arch/arm/cpu/ixp/npe/IxQMgrQAccess.c similarity index 100% rename from cpu/ixp/npe/IxQMgrQAccess.c rename to arch/arm/cpu/ixp/npe/IxQMgrQAccess.c diff --git a/cpu/ixp/npe/IxQMgrQCfg.c b/arch/arm/cpu/ixp/npe/IxQMgrQCfg.c similarity index 100% rename from cpu/ixp/npe/IxQMgrQCfg.c rename to arch/arm/cpu/ixp/npe/IxQMgrQCfg.c diff --git a/arch/arm/cpu/ixp/npe/Makefile b/arch/arm/cpu/ixp/npe/Makefile new file mode 100644 index 0000000000..e1f970062d --- /dev/null +++ b/arch/arm/cpu/ixp/npe/Makefile @@ -0,0 +1,98 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libnpe.a + +LOCAL_CFLAGS += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux +CFLAGS += $(LOCAL_CFLAGS) +HOSTCFLAGS += $(LOCAL_CFLAGS) + +COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \ + miiphy.o \ + IxOsalBufferMgt.o \ + IxOsalIoMem.o \ + IxOsalOsCacheMMU.o \ + IxOsalOsMsgQ.o \ + IxOsalOsSemaphore.o \ + IxOsalOsServices.o \ + IxOsalOsThread.o \ + IxEthAcc.o \ + IxEthAccCommon.o \ + IxEthAccControlInterface.o \ + IxEthAccDataPlane.o \ + IxEthAccMac.o \ + IxEthAccMii.o \ + IxEthDBAPI.o \ + IxEthDBAPISupport.o \ + IxEthDBCore.o \ + IxEthDBEvents.o \ + IxEthDBFeatures.o \ + IxEthDBFirewall.o \ + IxEthDBHashtable.o \ + IxEthDBLearning.o \ + IxEthDBMem.o \ + IxEthDBNPEAdaptor.o \ + IxEthDBPortUpdate.o \ + IxEthDBReports.o \ + IxEthDBSearch.o \ + IxEthDBSpanningTree.o \ + IxEthDBUtil.o \ + IxEthDBVlan.o \ + IxEthDBWiFi.o \ + IxEthMii.o \ + IxQMgrAqmIf.o \ + IxQMgrDispatcher.o \ + IxQMgrInit.o \ + IxQMgrQAccess.o \ + IxQMgrQCfg.o \ + IxFeatureCtrl.o \ + IxNpeDl.o \ + IxNpeDlImageMgr.o \ + IxNpeDlNpeMgr.o \ + IxNpeDlNpeMgrUtils.o \ + IxNpeMh.o \ + IxNpeMhConfig.o \ + IxNpeMhReceive.o \ + IxNpeMhSend.o \ + IxNpeMhSolicitedCbMgr.o \ + IxNpeMhUnsolicitedCbMgr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/ixp/npe/include/IxAssert.h b/arch/arm/cpu/ixp/npe/include/IxAssert.h similarity index 100% rename from cpu/ixp/npe/include/IxAssert.h rename to arch/arm/cpu/ixp/npe/include/IxAssert.h diff --git a/cpu/ixp/npe/include/IxAtmSch.h b/arch/arm/cpu/ixp/npe/include/IxAtmSch.h similarity index 100% rename from cpu/ixp/npe/include/IxAtmSch.h rename to arch/arm/cpu/ixp/npe/include/IxAtmSch.h diff --git a/cpu/ixp/npe/include/IxAtmTypes.h b/arch/arm/cpu/ixp/npe/include/IxAtmTypes.h similarity index 100% rename from cpu/ixp/npe/include/IxAtmTypes.h rename to arch/arm/cpu/ixp/npe/include/IxAtmTypes.h diff --git a/cpu/ixp/npe/include/IxAtmdAcc.h b/arch/arm/cpu/ixp/npe/include/IxAtmdAcc.h similarity index 100% rename from cpu/ixp/npe/include/IxAtmdAcc.h rename to arch/arm/cpu/ixp/npe/include/IxAtmdAcc.h diff --git a/cpu/ixp/npe/include/IxAtmdAccCtrl.h b/arch/arm/cpu/ixp/npe/include/IxAtmdAccCtrl.h similarity index 100% rename from cpu/ixp/npe/include/IxAtmdAccCtrl.h rename to arch/arm/cpu/ixp/npe/include/IxAtmdAccCtrl.h diff --git a/cpu/ixp/npe/include/IxAtmm.h b/arch/arm/cpu/ixp/npe/include/IxAtmm.h similarity index 100% rename from cpu/ixp/npe/include/IxAtmm.h rename to arch/arm/cpu/ixp/npe/include/IxAtmm.h diff --git a/cpu/ixp/npe/include/IxDmaAcc.h b/arch/arm/cpu/ixp/npe/include/IxDmaAcc.h similarity index 100% rename from cpu/ixp/npe/include/IxDmaAcc.h rename to arch/arm/cpu/ixp/npe/include/IxDmaAcc.h diff --git a/cpu/ixp/npe/include/IxEthAcc.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc.h similarity index 100% rename from cpu/ixp/npe/include/IxEthAcc.h rename to arch/arm/cpu/ixp/npe/include/IxEthAcc.h diff --git a/cpu/ixp/npe/include/IxEthAccDataPlane_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAccDataPlane_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthAccDataPlane_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthAccDataPlane_p.h diff --git a/cpu/ixp/npe/include/IxEthAccMac_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAccMac_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthAccMac_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthAccMac_p.h diff --git a/cpu/ixp/npe/include/IxEthAccMii_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAccMii_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthAccMii_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthAccMii_p.h diff --git a/cpu/ixp/npe/include/IxEthAccQueueAssign_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAccQueueAssign_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthAccQueueAssign_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthAccQueueAssign_p.h diff --git a/cpu/ixp/npe/include/IxEthAcc_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthAcc_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h diff --git a/cpu/ixp/npe/include/IxEthDB.h b/arch/arm/cpu/ixp/npe/include/IxEthDB.h similarity index 100% rename from cpu/ixp/npe/include/IxEthDB.h rename to arch/arm/cpu/ixp/npe/include/IxEthDB.h diff --git a/cpu/ixp/npe/include/IxEthDBLocks_p.h b/arch/arm/cpu/ixp/npe/include/IxEthDBLocks_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthDBLocks_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthDBLocks_p.h diff --git a/cpu/ixp/npe/include/IxEthDBLog_p.h b/arch/arm/cpu/ixp/npe/include/IxEthDBLog_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthDBLog_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthDBLog_p.h diff --git a/cpu/ixp/npe/include/IxEthDBMessages_p.h b/arch/arm/cpu/ixp/npe/include/IxEthDBMessages_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthDBMessages_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthDBMessages_p.h diff --git a/cpu/ixp/npe/include/IxEthDBPortDefs.h b/arch/arm/cpu/ixp/npe/include/IxEthDBPortDefs.h similarity index 100% rename from cpu/ixp/npe/include/IxEthDBPortDefs.h rename to arch/arm/cpu/ixp/npe/include/IxEthDBPortDefs.h diff --git a/cpu/ixp/npe/include/IxEthDBQoS.h b/arch/arm/cpu/ixp/npe/include/IxEthDBQoS.h similarity index 100% rename from cpu/ixp/npe/include/IxEthDBQoS.h rename to arch/arm/cpu/ixp/npe/include/IxEthDBQoS.h diff --git a/cpu/ixp/npe/include/IxEthDB_p.h b/arch/arm/cpu/ixp/npe/include/IxEthDB_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthDB_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthDB_p.h diff --git a/cpu/ixp/npe/include/IxEthMii.h b/arch/arm/cpu/ixp/npe/include/IxEthMii.h similarity index 100% rename from cpu/ixp/npe/include/IxEthMii.h rename to arch/arm/cpu/ixp/npe/include/IxEthMii.h diff --git a/cpu/ixp/npe/include/IxEthMii_p.h b/arch/arm/cpu/ixp/npe/include/IxEthMii_p.h similarity index 100% rename from cpu/ixp/npe/include/IxEthMii_p.h rename to arch/arm/cpu/ixp/npe/include/IxEthMii_p.h diff --git a/cpu/ixp/npe/include/IxEthNpe.h b/arch/arm/cpu/ixp/npe/include/IxEthNpe.h similarity index 100% rename from cpu/ixp/npe/include/IxEthNpe.h rename to arch/arm/cpu/ixp/npe/include/IxEthNpe.h diff --git a/cpu/ixp/npe/include/IxFeatureCtrl.h b/arch/arm/cpu/ixp/npe/include/IxFeatureCtrl.h similarity index 100% rename from cpu/ixp/npe/include/IxFeatureCtrl.h rename to arch/arm/cpu/ixp/npe/include/IxFeatureCtrl.h diff --git a/cpu/ixp/npe/include/IxHssAcc.h b/arch/arm/cpu/ixp/npe/include/IxHssAcc.h similarity index 100% rename from cpu/ixp/npe/include/IxHssAcc.h rename to arch/arm/cpu/ixp/npe/include/IxHssAcc.h diff --git a/cpu/ixp/npe/include/IxI2cDrv.h b/arch/arm/cpu/ixp/npe/include/IxI2cDrv.h similarity index 100% rename from cpu/ixp/npe/include/IxI2cDrv.h rename to arch/arm/cpu/ixp/npe/include/IxI2cDrv.h diff --git a/cpu/ixp/npe/include/IxNpeA.h b/arch/arm/cpu/ixp/npe/include/IxNpeA.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeA.h rename to arch/arm/cpu/ixp/npe/include/IxNpeA.h diff --git a/cpu/ixp/npe/include/IxNpeDl.h b/arch/arm/cpu/ixp/npe/include/IxNpeDl.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeDl.h rename to arch/arm/cpu/ixp/npe/include/IxNpeDl.h diff --git a/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeDlImageMgr_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h diff --git a/cpu/ixp/npe/include/IxNpeDlMacros_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlMacros_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeDlMacros_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeDlMacros_p.h diff --git a/cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h diff --git a/cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h diff --git a/cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h diff --git a/cpu/ixp/npe/include/IxNpeMh.h b/arch/arm/cpu/ixp/npe/include/IxNpeMh.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeMh.h rename to arch/arm/cpu/ixp/npe/include/IxNpeMh.h diff --git a/cpu/ixp/npe/include/IxNpeMhConfig_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhConfig_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeMhConfig_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeMhConfig_p.h diff --git a/cpu/ixp/npe/include/IxNpeMhMacros_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhMacros_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeMhMacros_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeMhMacros_p.h diff --git a/cpu/ixp/npe/include/IxNpeMhReceive_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhReceive_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeMhReceive_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeMhReceive_p.h diff --git a/cpu/ixp/npe/include/IxNpeMhSend_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhSend_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeMhSend_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeMhSend_p.h diff --git a/cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h diff --git a/cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h b/arch/arm/cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h rename to arch/arm/cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h diff --git a/cpu/ixp/npe/include/IxNpeMicrocode.h b/arch/arm/cpu/ixp/npe/include/IxNpeMicrocode.h similarity index 100% rename from cpu/ixp/npe/include/IxNpeMicrocode.h rename to arch/arm/cpu/ixp/npe/include/IxNpeMicrocode.h diff --git a/cpu/ixp/npe/include/IxOsBufLib.h b/arch/arm/cpu/ixp/npe/include/IxOsBufLib.h similarity index 100% rename from cpu/ixp/npe/include/IxOsBufLib.h rename to arch/arm/cpu/ixp/npe/include/IxOsBufLib.h diff --git a/cpu/ixp/npe/include/IxOsBuffMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsBuffMgt.h similarity index 100% rename from cpu/ixp/npe/include/IxOsBuffMgt.h rename to arch/arm/cpu/ixp/npe/include/IxOsBuffMgt.h diff --git a/cpu/ixp/npe/include/IxOsBuffPoolMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsBuffPoolMgt.h similarity index 100% rename from cpu/ixp/npe/include/IxOsBuffPoolMgt.h rename to arch/arm/cpu/ixp/npe/include/IxOsBuffPoolMgt.h diff --git a/cpu/ixp/npe/include/IxOsCacheMMU.h b/arch/arm/cpu/ixp/npe/include/IxOsCacheMMU.h similarity index 100% rename from cpu/ixp/npe/include/IxOsCacheMMU.h rename to arch/arm/cpu/ixp/npe/include/IxOsCacheMMU.h diff --git a/cpu/ixp/npe/include/IxOsPrintf.h b/arch/arm/cpu/ixp/npe/include/IxOsPrintf.h similarity index 100% rename from cpu/ixp/npe/include/IxOsPrintf.h rename to arch/arm/cpu/ixp/npe/include/IxOsPrintf.h diff --git a/cpu/ixp/npe/include/IxOsServices.h b/arch/arm/cpu/ixp/npe/include/IxOsServices.h similarity index 100% rename from cpu/ixp/npe/include/IxOsServices.h rename to arch/arm/cpu/ixp/npe/include/IxOsServices.h diff --git a/cpu/ixp/npe/include/IxOsServicesComponents.h b/arch/arm/cpu/ixp/npe/include/IxOsServicesComponents.h similarity index 100% rename from cpu/ixp/npe/include/IxOsServicesComponents.h rename to arch/arm/cpu/ixp/npe/include/IxOsServicesComponents.h diff --git a/cpu/ixp/npe/include/IxOsServicesEndianess.h b/arch/arm/cpu/ixp/npe/include/IxOsServicesEndianess.h similarity index 100% rename from cpu/ixp/npe/include/IxOsServicesEndianess.h rename to arch/arm/cpu/ixp/npe/include/IxOsServicesEndianess.h diff --git a/cpu/ixp/npe/include/IxOsServicesMemAccess.h b/arch/arm/cpu/ixp/npe/include/IxOsServicesMemAccess.h similarity index 100% rename from cpu/ixp/npe/include/IxOsServicesMemAccess.h rename to arch/arm/cpu/ixp/npe/include/IxOsServicesMemAccess.h diff --git a/cpu/ixp/npe/include/IxOsServicesMemMap.h b/arch/arm/cpu/ixp/npe/include/IxOsServicesMemMap.h similarity index 100% rename from cpu/ixp/npe/include/IxOsServicesMemMap.h rename to arch/arm/cpu/ixp/npe/include/IxOsServicesMemMap.h diff --git a/cpu/ixp/npe/include/IxOsal.h b/arch/arm/cpu/ixp/npe/include/IxOsal.h similarity index 100% rename from cpu/ixp/npe/include/IxOsal.h rename to arch/arm/cpu/ixp/npe/include/IxOsal.h diff --git a/cpu/ixp/npe/include/IxOsalAssert.h b/arch/arm/cpu/ixp/npe/include/IxOsalAssert.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalAssert.h rename to arch/arm/cpu/ixp/npe/include/IxOsalAssert.h diff --git a/cpu/ixp/npe/include/IxOsalBackward.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackward.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBackward.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBackward.h diff --git a/cpu/ixp/npe/include/IxOsalBackwardAssert.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardAssert.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBackwardAssert.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBackwardAssert.h diff --git a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h diff --git a/cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h diff --git a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardMemMap.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBackwardMemMap.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBackwardMemMap.h diff --git a/cpu/ixp/npe/include/IxOsalBackwardOsServices.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOsServices.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBackwardOsServices.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBackwardOsServices.h diff --git a/cpu/ixp/npe/include/IxOsalBackwardOssl.h b/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOssl.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBackwardOssl.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBackwardOssl.h diff --git a/cpu/ixp/npe/include/IxOsalBufferMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgt.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBufferMgt.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBufferMgt.h diff --git a/cpu/ixp/npe/include/IxOsalBufferMgtDefault.h b/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgtDefault.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalBufferMgtDefault.h rename to arch/arm/cpu/ixp/npe/include/IxOsalBufferMgtDefault.h diff --git a/cpu/ixp/npe/include/IxOsalConfig.h b/arch/arm/cpu/ixp/npe/include/IxOsalConfig.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalConfig.h rename to arch/arm/cpu/ixp/npe/include/IxOsalConfig.h diff --git a/cpu/ixp/npe/include/IxOsalEndianess.h b/arch/arm/cpu/ixp/npe/include/IxOsalEndianess.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalEndianess.h rename to arch/arm/cpu/ixp/npe/include/IxOsalEndianess.h diff --git a/cpu/ixp/npe/include/IxOsalIoMem.h b/arch/arm/cpu/ixp/npe/include/IxOsalIoMem.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalIoMem.h rename to arch/arm/cpu/ixp/npe/include/IxOsalIoMem.h diff --git a/cpu/ixp/npe/include/IxOsalMemAccess.h b/arch/arm/cpu/ixp/npe/include/IxOsalMemAccess.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalMemAccess.h rename to arch/arm/cpu/ixp/npe/include/IxOsalMemAccess.h diff --git a/cpu/ixp/npe/include/IxOsalOem.h b/arch/arm/cpu/ixp/npe/include/IxOsalOem.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalOem.h rename to arch/arm/cpu/ixp/npe/include/IxOsalOem.h diff --git a/cpu/ixp/npe/include/IxOsalOs.h b/arch/arm/cpu/ixp/npe/include/IxOsalOs.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalOs.h rename to arch/arm/cpu/ixp/npe/include/IxOsalOs.h diff --git a/cpu/ixp/npe/include/IxOsalOsAssert.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsAssert.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalOsAssert.h rename to arch/arm/cpu/ixp/npe/include/IxOsalOsAssert.h diff --git a/cpu/ixp/npe/include/IxOsalOsBufferMgt.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsBufferMgt.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalOsBufferMgt.h rename to arch/arm/cpu/ixp/npe/include/IxOsalOsBufferMgt.h diff --git a/cpu/ixp/npe/include/IxOsalOsIxp400.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalOsIxp400.h rename to arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400.h diff --git a/cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h rename to arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h diff --git a/cpu/ixp/npe/include/IxOsalOsTypes.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsTypes.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalOsTypes.h rename to arch/arm/cpu/ixp/npe/include/IxOsalOsTypes.h diff --git a/cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h b/arch/arm/cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h rename to arch/arm/cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h diff --git a/cpu/ixp/npe/include/IxOsalTypes.h b/arch/arm/cpu/ixp/npe/include/IxOsalTypes.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalTypes.h rename to arch/arm/cpu/ixp/npe/include/IxOsalTypes.h diff --git a/cpu/ixp/npe/include/IxOsalUtilitySymbols.h b/arch/arm/cpu/ixp/npe/include/IxOsalUtilitySymbols.h similarity index 100% rename from cpu/ixp/npe/include/IxOsalUtilitySymbols.h rename to arch/arm/cpu/ixp/npe/include/IxOsalUtilitySymbols.h diff --git a/cpu/ixp/npe/include/IxParityENAcc.h b/arch/arm/cpu/ixp/npe/include/IxParityENAcc.h similarity index 100% rename from cpu/ixp/npe/include/IxParityENAcc.h rename to arch/arm/cpu/ixp/npe/include/IxParityENAcc.h diff --git a/cpu/ixp/npe/include/IxPerfProfAcc.h b/arch/arm/cpu/ixp/npe/include/IxPerfProfAcc.h similarity index 100% rename from cpu/ixp/npe/include/IxPerfProfAcc.h rename to arch/arm/cpu/ixp/npe/include/IxPerfProfAcc.h diff --git a/cpu/ixp/npe/include/IxQMgr.h b/arch/arm/cpu/ixp/npe/include/IxQMgr.h similarity index 100% rename from cpu/ixp/npe/include/IxQMgr.h rename to arch/arm/cpu/ixp/npe/include/IxQMgr.h diff --git a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrAqmIf_p.h similarity index 100% rename from cpu/ixp/npe/include/IxQMgrAqmIf_p.h rename to arch/arm/cpu/ixp/npe/include/IxQMgrAqmIf_p.h diff --git a/cpu/ixp/npe/include/IxQMgrDefines_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrDefines_p.h similarity index 100% rename from cpu/ixp/npe/include/IxQMgrDefines_p.h rename to arch/arm/cpu/ixp/npe/include/IxQMgrDefines_p.h diff --git a/cpu/ixp/npe/include/IxQMgrDispatcher_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h similarity index 100% rename from cpu/ixp/npe/include/IxQMgrDispatcher_p.h rename to arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h diff --git a/cpu/ixp/npe/include/IxQMgrLog_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrLog_p.h similarity index 100% rename from cpu/ixp/npe/include/IxQMgrLog_p.h rename to arch/arm/cpu/ixp/npe/include/IxQMgrLog_p.h diff --git a/cpu/ixp/npe/include/IxQMgrQAccess_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrQAccess_p.h similarity index 100% rename from cpu/ixp/npe/include/IxQMgrQAccess_p.h rename to arch/arm/cpu/ixp/npe/include/IxQMgrQAccess_p.h diff --git a/cpu/ixp/npe/include/IxQMgrQCfg_p.h b/arch/arm/cpu/ixp/npe/include/IxQMgrQCfg_p.h similarity index 100% rename from cpu/ixp/npe/include/IxQMgrQCfg_p.h rename to arch/arm/cpu/ixp/npe/include/IxQMgrQCfg_p.h diff --git a/cpu/ixp/npe/include/IxQueueAssignments.h b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h similarity index 100% rename from cpu/ixp/npe/include/IxQueueAssignments.h rename to arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h diff --git a/cpu/ixp/npe/include/IxSspAcc.h b/arch/arm/cpu/ixp/npe/include/IxSspAcc.h similarity index 100% rename from cpu/ixp/npe/include/IxSspAcc.h rename to arch/arm/cpu/ixp/npe/include/IxSspAcc.h diff --git a/cpu/ixp/npe/include/IxTimeSyncAcc.h b/arch/arm/cpu/ixp/npe/include/IxTimeSyncAcc.h similarity index 100% rename from cpu/ixp/npe/include/IxTimeSyncAcc.h rename to arch/arm/cpu/ixp/npe/include/IxTimeSyncAcc.h diff --git a/cpu/ixp/npe/include/IxTimerCtrl.h b/arch/arm/cpu/ixp/npe/include/IxTimerCtrl.h similarity index 100% rename from cpu/ixp/npe/include/IxTimerCtrl.h rename to arch/arm/cpu/ixp/npe/include/IxTimerCtrl.h diff --git a/cpu/ixp/npe/include/IxTypes.h b/arch/arm/cpu/ixp/npe/include/IxTypes.h similarity index 100% rename from cpu/ixp/npe/include/IxTypes.h rename to arch/arm/cpu/ixp/npe/include/IxTypes.h diff --git a/cpu/ixp/npe/include/IxUART.h b/arch/arm/cpu/ixp/npe/include/IxUART.h similarity index 100% rename from cpu/ixp/npe/include/IxUART.h rename to arch/arm/cpu/ixp/npe/include/IxUART.h diff --git a/cpu/ixp/npe/include/IxVersionId.h b/arch/arm/cpu/ixp/npe/include/IxVersionId.h similarity index 100% rename from cpu/ixp/npe/include/IxVersionId.h rename to arch/arm/cpu/ixp/npe/include/IxVersionId.h diff --git a/cpu/ixp/npe/include/ix_error.h b/arch/arm/cpu/ixp/npe/include/ix_error.h similarity index 100% rename from cpu/ixp/npe/include/ix_error.h rename to arch/arm/cpu/ixp/npe/include/ix_error.h diff --git a/cpu/ixp/npe/include/ix_macros.h b/arch/arm/cpu/ixp/npe/include/ix_macros.h similarity index 100% rename from cpu/ixp/npe/include/ix_macros.h rename to arch/arm/cpu/ixp/npe/include/ix_macros.h diff --git a/cpu/ixp/npe/include/ix_os_type.h b/arch/arm/cpu/ixp/npe/include/ix_os_type.h similarity index 100% rename from cpu/ixp/npe/include/ix_os_type.h rename to arch/arm/cpu/ixp/npe/include/ix_os_type.h diff --git a/cpu/ixp/npe/include/ix_ossl.h b/arch/arm/cpu/ixp/npe/include/ix_ossl.h similarity index 100% rename from cpu/ixp/npe/include/ix_ossl.h rename to arch/arm/cpu/ixp/npe/include/ix_ossl.h diff --git a/cpu/ixp/npe/include/ix_symbols.h b/arch/arm/cpu/ixp/npe/include/ix_symbols.h similarity index 100% rename from cpu/ixp/npe/include/ix_symbols.h rename to arch/arm/cpu/ixp/npe/include/ix_symbols.h diff --git a/cpu/ixp/npe/include/ix_types.h b/arch/arm/cpu/ixp/npe/include/ix_types.h similarity index 100% rename from cpu/ixp/npe/include/ix_types.h rename to arch/arm/cpu/ixp/npe/include/ix_types.h diff --git a/cpu/ixp/npe/include/npe.h b/arch/arm/cpu/ixp/npe/include/npe.h similarity index 100% rename from cpu/ixp/npe/include/npe.h rename to arch/arm/cpu/ixp/npe/include/npe.h diff --git a/cpu/ixp/npe/include/os_datatypes.h b/arch/arm/cpu/ixp/npe/include/os_datatypes.h similarity index 100% rename from cpu/ixp/npe/include/os_datatypes.h rename to arch/arm/cpu/ixp/npe/include/os_datatypes.h diff --git a/cpu/ixp/npe/miiphy.c b/arch/arm/cpu/ixp/npe/miiphy.c similarity index 100% rename from cpu/ixp/npe/miiphy.c rename to arch/arm/cpu/ixp/npe/miiphy.c diff --git a/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c similarity index 100% rename from cpu/ixp/npe/npe.c rename to arch/arm/cpu/ixp/npe/npe.c diff --git a/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S similarity index 100% rename from cpu/ixp/start.S rename to arch/arm/cpu/ixp/start.S diff --git a/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c similarity index 100% rename from cpu/ixp/timer.c rename to arch/arm/cpu/ixp/timer.c diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds new file mode 100644 index 0000000000..b8ff2eed5c --- /dev/null +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/ixp/start.o(.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/lh7a40x/Makefile b/arch/arm/cpu/lh7a40x/Makefile similarity index 100% rename from cpu/lh7a40x/Makefile rename to arch/arm/cpu/lh7a40x/Makefile diff --git a/cpu/lh7a40x/config.mk b/arch/arm/cpu/lh7a40x/config.mk similarity index 100% rename from cpu/lh7a40x/config.mk rename to arch/arm/cpu/lh7a40x/config.mk diff --git a/cpu/lh7a40x/cpu.c b/arch/arm/cpu/lh7a40x/cpu.c similarity index 100% rename from cpu/lh7a40x/cpu.c rename to arch/arm/cpu/lh7a40x/cpu.c diff --git a/cpu/lh7a40x/speed.c b/arch/arm/cpu/lh7a40x/speed.c similarity index 100% rename from cpu/lh7a40x/speed.c rename to arch/arm/cpu/lh7a40x/speed.c diff --git a/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S similarity index 100% rename from cpu/lh7a40x/start.S rename to arch/arm/cpu/lh7a40x/start.S diff --git a/cpu/lh7a40x/timer.c b/arch/arm/cpu/lh7a40x/timer.c similarity index 100% rename from cpu/lh7a40x/timer.c rename to arch/arm/cpu/lh7a40x/timer.c diff --git a/arch/arm/cpu/lh7a40x/u-boot.lds b/arch/arm/cpu/lh7a40x/u-boot.lds new file mode 100644 index 0000000000..5a8ccf5888 --- /dev/null +++ b/arch/arm/cpu/lh7a40x/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/lh7a40x/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile similarity index 100% rename from cpu/pxa/Makefile rename to arch/arm/cpu/pxa/Makefile diff --git a/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk similarity index 100% rename from cpu/pxa/config.mk rename to arch/arm/cpu/pxa/config.mk diff --git a/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c similarity index 100% rename from cpu/pxa/cpu.c rename to arch/arm/cpu/pxa/cpu.c diff --git a/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c similarity index 100% rename from cpu/pxa/i2c.c rename to arch/arm/cpu/pxa/i2c.c diff --git a/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c similarity index 100% rename from cpu/pxa/pxafb.c rename to arch/arm/cpu/pxa/pxafb.c diff --git a/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S similarity index 100% rename from cpu/pxa/start.S rename to arch/arm/cpu/pxa/start.S diff --git a/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c similarity index 100% rename from cpu/pxa/timer.c rename to arch/arm/cpu/pxa/timer.c diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds new file mode 100644 index 0000000000..d4e85ef550 --- /dev/null +++ b/arch/arm/cpu/pxa/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c similarity index 100% rename from cpu/pxa/usb.c rename to arch/arm/cpu/pxa/usb.c diff --git a/cpu/s3c44b0/Makefile b/arch/arm/cpu/s3c44b0/Makefile similarity index 100% rename from cpu/s3c44b0/Makefile rename to arch/arm/cpu/s3c44b0/Makefile diff --git a/cpu/s3c44b0/cache.c b/arch/arm/cpu/s3c44b0/cache.c similarity index 100% rename from cpu/s3c44b0/cache.c rename to arch/arm/cpu/s3c44b0/cache.c diff --git a/cpu/s3c44b0/config.mk b/arch/arm/cpu/s3c44b0/config.mk similarity index 100% rename from cpu/s3c44b0/config.mk rename to arch/arm/cpu/s3c44b0/config.mk diff --git a/cpu/s3c44b0/cpu.c b/arch/arm/cpu/s3c44b0/cpu.c similarity index 100% rename from cpu/s3c44b0/cpu.c rename to arch/arm/cpu/s3c44b0/cpu.c diff --git a/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S similarity index 100% rename from cpu/s3c44b0/start.S rename to arch/arm/cpu/s3c44b0/start.S diff --git a/cpu/s3c44b0/timer.c b/arch/arm/cpu/s3c44b0/timer.c similarity index 100% rename from cpu/s3c44b0/timer.c rename to arch/arm/cpu/s3c44b0/timer.c diff --git a/arch/arm/cpu/s3c44b0/u-boot.lds b/arch/arm/cpu/s3c44b0/u-boot.lds new file mode 100644 index 0000000000..267d94c083 --- /dev/null +++ b/arch/arm/cpu/s3c44b0/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/s3c44b0/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/sa1100/Makefile b/arch/arm/cpu/sa1100/Makefile similarity index 100% rename from cpu/sa1100/Makefile rename to arch/arm/cpu/sa1100/Makefile diff --git a/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk similarity index 100% rename from cpu/sa1100/config.mk rename to arch/arm/cpu/sa1100/config.mk diff --git a/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c similarity index 100% rename from cpu/sa1100/cpu.c rename to arch/arm/cpu/sa1100/cpu.c diff --git a/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S similarity index 100% rename from cpu/sa1100/start.S rename to arch/arm/cpu/sa1100/start.S diff --git a/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c similarity index 100% rename from cpu/sa1100/timer.c rename to arch/arm/cpu/sa1100/timer.c diff --git a/arch/arm/cpu/sa1100/u-boot.lds b/arch/arm/cpu/sa1100/u-boot.lds new file mode 100644 index 0000000000..f6197acd81 --- /dev/null +++ b/arch/arm/cpu/sa1100/u-boot.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2003-2004 + * MontaVista Software, Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/include/asm-arm/arch-a320/a320.h b/arch/arm/include/asm/arch-a320/a320.h similarity index 100% rename from include/asm-arm/arch-a320/a320.h rename to arch/arm/include/asm/arch-a320/a320.h diff --git a/include/asm-arm/arch-a320/ftpmu010.h b/arch/arm/include/asm/arch-a320/ftpmu010.h similarity index 100% rename from include/asm-arm/arch-a320/ftpmu010.h rename to arch/arm/include/asm/arch-a320/ftpmu010.h diff --git a/include/asm-arm/arch-a320/ftsdmc020.h b/arch/arm/include/asm/arch-a320/ftsdmc020.h similarity index 100% rename from include/asm-arm/arch-a320/ftsdmc020.h rename to arch/arm/include/asm/arch-a320/ftsdmc020.h diff --git a/include/asm-arm/arch-a320/ftsmc020.h b/arch/arm/include/asm/arch-a320/ftsmc020.h similarity index 100% rename from include/asm-arm/arch-a320/ftsmc020.h rename to arch/arm/include/asm/arch-a320/ftsmc020.h diff --git a/include/asm-arm/arch-a320/fttmr010.h b/arch/arm/include/asm/arch-a320/fttmr010.h similarity index 100% rename from include/asm-arm/arch-a320/fttmr010.h rename to arch/arm/include/asm/arch-a320/fttmr010.h diff --git a/arch/arm/include/asm/arch-arm720t/hardware.h b/arch/arm/include/asm/arch-arm720t/hardware.h new file mode 100644 index 0000000000..9bee19ffbb --- /dev/null +++ b/arch/arm/include/asm/arch-arm720t/hardware.h @@ -0,0 +1,41 @@ +#ifndef __ARM7_HW_H +#define __ARM7_HW_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_NETARM) +#include +#elif defined(CONFIG_IMPA7) +/* include IMPA7 specific hardware file if there was one */ +#elif defined(CONFIG_EP7312) +/* include EP7312 specific hardware file if there was one */ +#elif defined(CONFIG_ARMADILLO) +/* include armadillo specific hardware file if there was one */ +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +/* include IntegratorCP/CM720T specific hardware file if there was one */ +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ARM7_HW_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_dma_module.h b/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h similarity index 100% rename from include/asm-arm/arch-arm720t/netarm_dma_module.h rename to arch/arm/include/asm/arch-arm720t/netarm_dma_module.h diff --git a/include/asm-arm/arch-arm720t/netarm_eni_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h similarity index 100% rename from include/asm-arm/arch-arm720t/netarm_eni_module.h rename to arch/arm/include/asm/arch-arm720t/netarm_eni_module.h diff --git a/include/asm-arm/arch-arm720t/netarm_eth_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h similarity index 100% rename from include/asm-arm/arch-arm720t/netarm_eth_module.h rename to arch/arm/include/asm/arch-arm720t/netarm_eth_module.h diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h similarity index 100% rename from include/asm-arm/arch-arm720t/netarm_gen_module.h rename to arch/arm/include/asm/arch-arm720t/netarm_gen_module.h diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h similarity index 100% rename from include/asm-arm/arch-arm720t/netarm_mem_module.h rename to arch/arm/include/asm/arch-arm720t/netarm_mem_module.h diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/arch/arm/include/asm/arch-arm720t/netarm_registers.h similarity index 100% rename from include/asm-arm/arch-arm720t/netarm_registers.h rename to arch/arm/include/asm/arch-arm720t/netarm_registers.h diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h similarity index 100% rename from include/asm-arm/arch-arm720t/netarm_ser_module.h rename to arch/arm/include/asm/arch-arm720t/netarm_ser_module.h diff --git a/include/asm-arm/arch-arm925t/sizes.h b/arch/arm/include/asm/arch-arm925t/sizes.h similarity index 100% rename from include/asm-arm/arch-arm925t/sizes.h rename to arch/arm/include/asm/arch-arm925t/sizes.h diff --git a/include/asm-arm/arch-arm926ejs/sizes.h b/arch/arm/include/asm/arch-arm926ejs/sizes.h similarity index 100% rename from include/asm-arm/arch-arm926ejs/sizes.h rename to arch/arm/include/asm/arch-arm926ejs/sizes.h diff --git a/include/asm-arm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h similarity index 100% rename from include/asm-arm/arch-at91/at91_common.h rename to arch/arm/include/asm/arch-at91/at91_common.h diff --git a/include/asm-arm/arch-at91/at91_emac.h b/arch/arm/include/asm/arch-at91/at91_emac.h similarity index 100% rename from include/asm-arm/arch-at91/at91_emac.h rename to arch/arm/include/asm/arch-at91/at91_emac.h diff --git a/include/asm-arm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h similarity index 100% rename from include/asm-arm/arch-at91/at91_matrix.h rename to arch/arm/include/asm/arch-at91/at91_matrix.h diff --git a/include/asm-arm/arch-at91/at91_mc.h b/arch/arm/include/asm/arch-at91/at91_mc.h similarity index 100% rename from include/asm-arm/arch-at91/at91_mc.h rename to arch/arm/include/asm/arch-at91/at91_mc.h diff --git a/include/asm-arm/arch-at91/at91_pdc.h b/arch/arm/include/asm/arch-at91/at91_pdc.h similarity index 100% rename from include/asm-arm/arch-at91/at91_pdc.h rename to arch/arm/include/asm/arch-at91/at91_pdc.h diff --git a/include/asm-arm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h similarity index 100% rename from include/asm-arm/arch-at91/at91_pio.h rename to arch/arm/include/asm/arch-at91/at91_pio.h diff --git a/include/asm-arm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h similarity index 100% rename from include/asm-arm/arch-at91/at91_pit.h rename to arch/arm/include/asm/arch-at91/at91_pit.h diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h new file mode 100644 index 0000000000..5b1a85d051 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -0,0 +1,227 @@ +/* + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) + * + * Power Management Controller (PMC) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PMC_H +#define AT91_PMC_H + +#define AT91_ASM_PMC_MOR (AT91_PMC_BASE + 0x20) +#define AT91_ASM_PMC_PLLAR (AT91_PMC_BASE + 0x28) +#define AT91_ASM_PMC_PLLBR (AT91_PMC_BASE + 0x2c) +#define AT91_ASM_PMC_MCKR (AT91_PMC_BASE + 0x30) +#define AT91_ASM_PMC_SR (AT91_PMC_BASE + 0x68) + +#ifndef __ASSEMBLY__ + +#include + +typedef struct at91_pmc { + u32 scer; /* 0x00 System Clock Enable Register */ + u32 scdr; /* 0x04 System Clock Disable Register */ + u32 scsr; /* 0x08 System Clock Status Register */ + u32 reserved0; + u32 pcer; /* 0x10 Peripheral Clock Enable Register */ + u32 pcdr; /* 0x14 Peripheral Clock Disable Register */ + u32 pcsr; /* 0x18 Peripheral Clock Status Register */ + u32 reserved1; + u32 mor; /* 0x20 Main Oscilator Register */ + u32 mcfr; /* 0x24 Main Clock Frequency Register */ + u32 pllar; /* 0x28 PLL A Register */ + u32 pllbr; /* 0x2C PLL B Register */ + u32 mckr; /* 0x30 Master Clock Register */ + u32 reserved2[3]; + u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */ + u32 reserved3[4]; + u32 ier; /* 0x60 Interrupt Enable Register */ + u32 idr; /* 0x64 Interrupt Disable Register */ + u32 sr; /* 0x68 Status Register */ + u32 imr; /* 0x6C Interrupt Mask Register */ + u32 reserved4[4]; + u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */ + u32 reserved5[21]; + u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ + u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ + u32 reserved8[5]; +} at91_pmc_t; + +#endif /* end not assembly */ + +#define AT91_PMC_MOR_MOSCEN 0x01 +#define AT91_PMC_MOR_OSCBYPASS 0x02 +#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) + +#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) +#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) +#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) +#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) +#define AT91_PMC_PLLAR_29 0x20000000 +#define AT91_PMC_PLLBR_USBDIV_1 0x00000000 +#define AT91_PMC_PLLBR_USBDIV_2 0x10000000 +#define AT91_PMC_PLLBR_USBDIV_4 0x20000000 + +#define AT91_PMC_MCFR_MAINRDY 0x00010000 +#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF + +#define AT91_PMC_MCKR_CSS_SLOW 0x00000000 +#define AT91_PMC_MCKR_CSS_MAIN 0x00000001 +#define AT91_PMC_MCKR_CSS_PLLA 0x00000002 +#define AT91_PMC_MCKR_CSS_PLLB 0x00000003 +#define AT91_PMC_MCKR_CSS_MASK 0x00000003 + +#define AT91_PMC_MCKR_PRES_1 0x00000000 +#define AT91_PMC_MCKR_PRES_2 0x00000004 +#define AT91_PMC_MCKR_PRES_4 0x00000008 +#define AT91_PMC_MCKR_PRES_8 0x0000000C +#define AT91_PMC_MCKR_PRES_16 0x00000010 +#define AT91_PMC_MCKR_PRES_32 0x00000014 +#define AT91_PMC_MCKR_PRES_64 0x00000018 +#define AT91_PMC_MCKR_PRES_MASK 0x0000001C + +#define AT91_PMC_MCKR_MDIV_1 0x00000000 +#define AT91_PMC_MCKR_MDIV_2 0x00000100 +#define AT91_PMC_MCKR_MDIV_4 0x00000200 +#define AT91_PMC_MCKR_MDIV_MASK 0x00000300 + +#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 +#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 + +#define AT91_PMC_IXR_MOSCS 0x00000001 +#define AT91_PMC_IXR_LOCKA 0x00000002 +#define AT91_PMC_IXR_LOCKB 0x00000004 +#define AT91_PMC_IXR_MCKRDY 0x00000008 +#define AT91_PMC_IXR_LOCKU 0x00000040 +#define AT91_PMC_IXR_PCKRDY0 0x00000100 +#define AT91_PMC_IXR_PCKRDY1 0x00000200 +#define AT91_PMC_IXR_PCKRDY2 0x00000400 +#define AT91_PMC_IXR_PCKRDY3 0x00000800 + +#ifdef CONFIG_AT91_LEGACY +#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ +#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ + +#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#endif + +#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ +#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ +#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ +#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ +#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ +#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ +#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ + +#ifdef CONFIG_AT91_LEGACY +#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ + +#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#endif + +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ + +#ifdef CONFIG_AT91_LEGACY +#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +#endif +#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ +#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ +#ifdef CONFIG_AT91_LEGACY +#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#endif +#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ +#ifdef CONFIG_AT91_LEGACY +#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ +#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#endif +#define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ +#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ +#define AT91_PMC_USBDIV_1 (0 << 28) +#define AT91_PMC_USBDIV_2 (1 << 28) +#define AT91_PMC_USBDIV_4 (2 << 28) +#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ +#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ + +#ifdef CONFIG_AT91_LEGACY +#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#endif +#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ +#define AT91_PMC_CSS_SLOW (0 << 0) +#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_PLLA (2 << 0) +#define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ +#define AT91_PMC_PRES_1 (0 << 2) +#define AT91_PMC_PRES_2 (1 << 2) +#define AT91_PMC_PRES_4 (2 << 2) +#define AT91_PMC_PRES_8 (3 << 2) +#define AT91_PMC_PRES_16 (4 << 2) +#define AT91_PMC_PRES_32 (5 << 2) +#define AT91_PMC_PRES_64 (6 << 2) +#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ +#define AT91SAM9_PMC_MDIV_6 (3 << 8) +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) + +#ifdef CONFIG_AT91_LEGACY +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ + +#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ +#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ +#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#endif +#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ +#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ +#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ +#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ +#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#ifdef CONFIG_AT91_LEGACY +#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ + +#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#endif +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ +#ifdef CONFIG_AT91_LEGACY +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ +#endif /* CONFIG_AT91_LEGACY */ +#endif diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h similarity index 100% rename from include/asm-arm/arch-at91/at91_rstc.h rename to arch/arm/include/asm/arch-at91/at91_rstc.h diff --git a/include/asm-arm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h similarity index 100% rename from include/asm-arm/arch-at91/at91_spi.h rename to arch/arm/include/asm/arch-at91/at91_spi.h diff --git a/include/asm-arm/arch-at91/at91_st.h b/arch/arm/include/asm/arch-at91/at91_st.h similarity index 100% rename from include/asm-arm/arch-at91/at91_st.h rename to arch/arm/include/asm/arch-at91/at91_st.h diff --git a/include/asm-arm/arch-at91/at91_tc.h b/arch/arm/include/asm/arch-at91/at91_tc.h similarity index 100% rename from include/asm-arm/arch-at91/at91_tc.h rename to arch/arm/include/asm/arch-at91/at91_tc.h diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h similarity index 100% rename from include/asm-arm/arch-at91/at91_wdt.h rename to arch/arm/include/asm/arch-at91/at91_wdt.h diff --git a/include/asm-arm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h similarity index 100% rename from include/asm-arm/arch-at91/at91cap9.h rename to arch/arm/include/asm/arch-at91/at91cap9.h diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h similarity index 100% rename from include/asm-arm/arch-at91/at91cap9_matrix.h rename to arch/arm/include/asm/arch-at91/at91cap9_matrix.h diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/arch/arm/include/asm/arch-at91/at91rm9200.h similarity index 100% rename from include/asm-arm/arch-at91/at91rm9200.h rename to arch/arm/include/asm/arch-at91/at91rm9200.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h new file mode 100644 index 0000000000..ec04318036 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -0,0 +1,149 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] + * + * (C) 2006 Andrew Victor + * + * Common definitions. + * Based on AT91SAM9260 datasheet revision A (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9260_H +#define AT91SAM9260_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ +#define AT91SAM9260_ID_US0 6 /* USART 0 */ +#define AT91SAM9260_ID_US1 7 /* USART 1 */ +#define AT91SAM9260_ID_US2 8 /* USART 2 */ +#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ +#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9260_ID_UHP 20 /* USB Host port */ +#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ +#define AT91SAM9260_ID_US3 23 /* USART 3 */ +#define AT91SAM9260_ID_US4 24 /* USART 4 */ +#define AT91SAM9260_ID_US5 25 /* USART 5 */ +#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ +#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ +#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ +#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ + +#define AT91_EMAC_BASE 0xfffc4000 +#define AT91_SDRAMC_BASE 0xffffea00 +#define AT91_SMC_BASE 0xffffec00 +#define AT91_MATRIX_BASE 0xffffee00 +#define AT91_PIO_BASE 0xfffff400 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_RTT_BASE 0xfffffd20 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 +#define AT91_GPR_BASE 0xfffffd50 + +#ifdef CONFIG_AT91_LEGACY + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9260_BASE_TCB0 0xfffa0000 +#define AT91SAM9260_BASE_TC0 0xfffa0000 +#define AT91SAM9260_BASE_TC1 0xfffa0040 +#define AT91SAM9260_BASE_TC2 0xfffa0080 +#define AT91SAM9260_BASE_UDP 0xfffa4000 +#define AT91SAM9260_BASE_MCI 0xfffa8000 +#define AT91SAM9260_BASE_TWI 0xfffac000 +#define AT91SAM9260_BASE_US0 0xfffb0000 +#define AT91SAM9260_BASE_US1 0xfffb4000 +#define AT91SAM9260_BASE_US2 0xfffb8000 +#define AT91SAM9260_BASE_SSC 0xfffbc000 +#define AT91SAM9260_BASE_ISI 0xfffc0000 +#define AT91SAM9260_BASE_EMAC 0xfffc4000 +#define AT91SAM9260_BASE_SPI0 0xfffc8000 +#define AT91SAM9260_BASE_SPI1 0xfffcc000 +#define AT91SAM9260_BASE_US3 0xfffd0000 +#define AT91SAM9260_BASE_US4 0xfffd4000 +#define AT91SAM9260_BASE_US5 0xfffd8000 +#define AT91SAM9260_BASE_TCB1 0xfffdc000 +#define AT91SAM9260_BASE_TC3 0xfffdc000 +#define AT91SAM9260_BASE_TC4 0xfffdc040 +#define AT91SAM9260_BASE_TC5 0xfffdc080 +#define AT91SAM9260_BASE_ADC 0xfffe0000 +#define AT91_BASE_SYS 0xffffe800 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9260_BASE_US0 +#define AT91_USART1 AT91SAM9260_BASE_US1 +#define AT91_USART2 AT91SAM9260_BASE_US2 +#define AT91_USART3 AT91SAM9260_BASE_US3 +#define AT91_USART4 AT91SAM9260_BASE_US4 +#define AT91_USART5 AT91SAM9260_BASE_US5 + +#endif /* CONFIG_AT91_LEGACY */ + +/* + * Internal Memory. + */ +#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ +#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ +#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ +#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ + +#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ + +#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ +#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ + +/* + * Cpu Name + */ +#if defined(CONFIG_AT91SAM9260) +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" +#elif defined(CONFIG_AT91SAM9G20) +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" +#endif + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9260_matrix.h rename to arch/arm/include/asm/arch-at91/at91sam9260_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h new file mode 100644 index 0000000000..7ca0283135 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -0,0 +1,121 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] + * + * Copyright (C) SAN People + * + * Common definitions. + * Based on AT91SAM9261 datasheet revision E. (Preliminary) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9261_H +#define AT91SAM9261_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9261_ID_US0 6 /* USART 0 */ +#define AT91SAM9261_ID_US1 7 /* USART 1 */ +#define AT91SAM9261_ID_US2 8 /* USART 2 */ +#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9261_ID_UHP 20 /* USB Host port */ +#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ +#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ + +#define AT91_SDRAMC_BASE 0xffffea00 +#define AT91_SMC_BASE 0xffffec00 +#define AT91_MATRIX_BASE 0xffffee00 +#define AT91_PIO_BASE 0xfffff400 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_RTT_BASE 0xfffffd20 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 +#define AT91_GPBR_BASE 0xfffffd50 + +#ifdef CONFIG_AT91_LEGACY + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9261_BASE_TCB0 0xfffa0000 +#define AT91SAM9261_BASE_TC0 0xfffa0000 +#define AT91SAM9261_BASE_TC1 0xfffa0040 +#define AT91SAM9261_BASE_TC2 0xfffa0080 +#define AT91SAM9261_BASE_UDP 0xfffa4000 +#define AT91SAM9261_BASE_MCI 0xfffa8000 +#define AT91SAM9261_BASE_TWI 0xfffac000 +#define AT91SAM9261_BASE_US0 0xfffb0000 +#define AT91SAM9261_BASE_US1 0xfffb4000 +#define AT91SAM9261_BASE_US2 0xfffb8000 +#define AT91SAM9261_BASE_SSC0 0xfffbc000 +#define AT91SAM9261_BASE_SSC1 0xfffc0000 +#define AT91SAM9261_BASE_SSC2 0xfffc4000 +#define AT91SAM9261_BASE_SPI0 0xfffc8000 +#define AT91SAM9261_BASE_SPI1 0xfffcc000 +#define AT91_BASE_SYS 0xffffea00 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9261_BASE_US0 +#define AT91_USART1 AT91SAM9261_BASE_US1 +#define AT91_USART2 AT91SAM9261_BASE_US2 + +#endif /* CONFIG_AT91_LEGACY */ + +/* + * Internal Memory. + */ +#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ + +#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ +#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ + +/* + * Cpu Name + */ +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9261_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9261_matrix.h rename to arch/arm/include/asm/arch-at91/at91sam9261_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h new file mode 100644 index 0000000000..4ada1ceaf8 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -0,0 +1,155 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] + * + * (C) 2007 Atmel Corporation. + * + * Common definitions. + * Based on AT91SAM9263 datasheet revision B (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9263_H +#define AT91SAM9263_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ +#define AT91SAM9263_ID_US0 7 /* USART 0 */ +#define AT91SAM9263_ID_US1 8 /* USART 1 */ +#define AT91SAM9263_ID_US2 9 /* USART 2 */ +#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ +#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ +#define AT91SAM9263_ID_CAN 12 /* CAN */ +#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ +#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ +#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ +#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ +#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ +#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ +#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ +#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ +#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ +#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ +#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ +#define AT91SAM9263_ID_UHP 29 /* USB Host port */ +#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ + +#define AT91_EMAC_BASE 0xfffbc000 +#define AT91_ECC0_BASE 0xffffe000 +#define AT91_SDRAMC0_BASE 0xffffe200 +#define AT91_SMC0_BASE 0xffffe400 +#define AT91_ECC1_BASE 0xffffe600 +#define AT91_SDRAMC1_BASE 0xffffe800 +#define AT91_SMC1_BASE 0xffffea00 +#define AT91_MATRIX_BASE 0xffffec00 +#define AT91_CCFG_BASE 0xffffed10 +#define AT91_DBGU_BASE 0xffffee00 +#define AT91_AIC_BASE 0xfffff000 +#define AT91_PIO_BASE 0xfffff200 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_RTT0_BASE 0xfffffd20 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 +#define AT91_RTT1_BASE 0xfffffd50 +#define AT91_GPBR_BASE 0xfffffd60 + +#ifdef CONFIG_AT91_LEGACY + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9263_BASE_UDP 0xfff78000 +#define AT91SAM9263_BASE_TCB0 0xfff7c000 +#define AT91SAM9263_BASE_TC0 0xfff7c000 +#define AT91SAM9263_BASE_TC1 0xfff7c040 +#define AT91SAM9263_BASE_TC2 0xfff7c080 +#define AT91SAM9263_BASE_MCI0 0xfff80000 +#define AT91SAM9263_BASE_MCI1 0xfff84000 +#define AT91SAM9263_BASE_TWI 0xfff88000 +#define AT91SAM9263_BASE_US0 0xfff8c000 +#define AT91SAM9263_BASE_US1 0xfff90000 +#define AT91SAM9263_BASE_US2 0xfff94000 +#define AT91SAM9263_BASE_SSC0 0xfff98000 +#define AT91SAM9263_BASE_SSC1 0xfff9c000 +#define AT91SAM9263_BASE_AC97C 0xfffa0000 +#define AT91SAM9263_BASE_SPI0 0xfffa4000 +#define AT91SAM9263_BASE_SPI1 0xfffa8000 +#define AT91SAM9263_BASE_CAN 0xfffac000 +#define AT91SAM9263_BASE_PWMC 0xfffb8000 +#define AT91SAM9263_BASE_EMAC 0xfffbc000 +#define AT91SAM9263_BASE_ISI 0xfffc4000 +#define AT91SAM9263_BASE_2DGE 0xfffc8000 +#define AT91_BASE_SYS 0xffffe000 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) +#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) +#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) +#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) +#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) +#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9263_BASE_US0 +#define AT91_USART1 AT91SAM9263_BASE_US1 +#define AT91_USART2 AT91SAM9263_BASE_US2 + +#define AT91_SMC AT91_SMC0 +#define AT91_SDRAMC AT91_SDRAMC0 + +#endif /* CONFIG_AT91_LEGACY */ + +/* + * Internal Memory. + */ +#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ +#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ + +#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ + +#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ +#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ + +#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ +#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ +#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ + +/* + * Cpu Name + */ +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9263_matrix.h rename to arch/arm/include/asm/arch-at91/at91sam9263_matrix.h diff --git a/include/asm-arm/arch-at91/at91sam9_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9_matrix.h rename to arch/arm/include/asm/arch-at91/at91sam9_matrix.h diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9_sdramc.h rename to arch/arm/include/asm/arch-at91/at91sam9_sdramc.h diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9_smc.h rename to arch/arm/include/asm/arch-at91/at91sam9_smc.h diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9g45.h rename to arch/arm/include/asm/arch-at91/at91sam9g45.h diff --git a/include/asm-arm/arch-at91/at91sam9g45_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9g45_matrix.h rename to arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9rl.h rename to arch/arm/include/asm/arch-at91/at91sam9rl.h diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h similarity index 100% rename from include/asm-arm/arch-at91/at91sam9rl_matrix.h rename to arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h diff --git a/include/asm-arm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h similarity index 100% rename from include/asm-arm/arch-at91/clk.h rename to arch/arm/include/asm/arch-at91/clk.h diff --git a/include/asm-arm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h similarity index 100% rename from include/asm-arm/arch-at91/gpio.h rename to arch/arm/include/asm/arch-at91/gpio.h diff --git a/include/asm-arm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h similarity index 100% rename from include/asm-arm/arch-at91/hardware.h rename to arch/arm/include/asm/arch-at91/hardware.h diff --git a/include/asm-arm/arch-at91/io.h b/arch/arm/include/asm/arch-at91/io.h similarity index 100% rename from include/asm-arm/arch-at91/io.h rename to arch/arm/include/asm/arch-at91/io.h diff --git a/include/asm-arm/arch-at91/memory-map.h b/arch/arm/include/asm/arch-at91/memory-map.h similarity index 100% rename from include/asm-arm/arch-at91/memory-map.h rename to arch/arm/include/asm/arch-at91/memory-map.h diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h similarity index 100% rename from include/asm-arm/arch-at91rm9200/AT91RM9200.h rename to arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/arch/arm/include/asm/arch-at91rm9200/hardware.h similarity index 100% rename from include/asm-arm/arch-at91rm9200/hardware.h rename to arch/arm/include/asm/arch-at91rm9200/hardware.h diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h similarity index 100% rename from include/asm-arm/arch-davinci/emac_defs.h rename to arch/arm/include/asm/arch-davinci/emac_defs.h diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h new file mode 100644 index 0000000000..b48ec17e97 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/emif_defs.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_ + +#include + +struct davinci_emif_regs { + u_int32_t ercsr; + u_int32_t awccr; + u_int32_t sdbcr; + u_int32_t sdrcr; + u_int32_t ab1cr; + u_int32_t ab2cr; + u_int32_t ab3cr; + u_int32_t ab4cr; + u_int32_t sdtimr; + u_int32_t ddrsr; + u_int32_t ddrphycr; + u_int32_t ddrphysr; + u_int32_t totar; + u_int32_t totactr; + u_int32_t ddrphyid_rev; + u_int32_t sdsretr; + u_int32_t eirr; + u_int32_t eimr; + u_int32_t eimsr; + u_int32_t eimcr; + u_int32_t ioctrlr; + u_int32_t iostatr; + u_int8_t rsvd0[8]; + u_int32_t nandfcr; + u_int32_t nandfsr; + u_int8_t rsvd1[8]; + u_int32_t nandfecc[4]; + u_int8_t rsvd2[60]; + u_int32_t nand4biteccload; + u_int32_t nand4bitecc[4]; + u_int32_t nanderradd1; + u_int32_t nanderradd2; + u_int32_t nanderrval1; + u_int32_t nanderrval2; +}; + +#define davinci_emif_regs \ + ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) + +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) + +/* Chip Select setup */ +#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) +#define DAVINCI_ABCR_EXT_WAIT (1 << 30) +#define DAVINCI_ABCR_WSETUP(n) (n << 26) +#define DAVINCI_ABCR_WSTROBE(n) (n << 20) +#define DAVINCI_ABCR_WHOLD(n) (n << 17) +#define DAVINCI_ABCR_RSETUP(n) (n << 13) +#define DAVINCI_ABCR_RSTROBE(n) (n << 7) +#define DAVINCI_ABCR_RHOLD(n) (n << 4) +#define DAVINCI_ABCR_TA(n) (n << 2) +#define DAVINCI_ABCR_ASIZE_16BIT 1 +#define DAVINCI_ABCR_ASIZE_8BIT 0 + +#endif diff --git a/include/asm-arm/arch-davinci/gpio_defs.h b/arch/arm/include/asm/arch-davinci/gpio_defs.h similarity index 100% rename from include/asm-arm/arch-davinci/gpio_defs.h rename to arch/arm/include/asm/arch-davinci/gpio_defs.h diff --git a/include/asm-arm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h similarity index 100% rename from include/asm-arm/arch-davinci/hardware.h rename to arch/arm/include/asm/arch-davinci/hardware.h diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/arch/arm/include/asm/arch-davinci/i2c_defs.h similarity index 100% rename from include/asm-arm/arch-davinci/i2c_defs.h rename to arch/arm/include/asm/arch-davinci/i2c_defs.h diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h similarity index 100% rename from include/asm-arm/arch-davinci/nand_defs.h rename to arch/arm/include/asm/arch-davinci/nand_defs.h diff --git a/include/asm-arm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h similarity index 100% rename from include/asm-arm/arch-ep93xx/ep93xx.h rename to arch/arm/include/asm/arch-ep93xx/ep93xx.h diff --git a/include/asm-arm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h similarity index 100% rename from include/asm-arm/arch-imx/imx-regs.h rename to arch/arm/include/asm/arch-imx/imx-regs.h diff --git a/include/asm-arm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h similarity index 100% rename from include/asm-arm/arch-ixp/ixp425.h rename to arch/arm/include/asm/arch-ixp/ixp425.h diff --git a/include/asm-arm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h similarity index 100% rename from include/asm-arm/arch-ixp/ixp425pci.h rename to arch/arm/include/asm/arch-ixp/ixp425pci.h diff --git a/include/asm-arm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h similarity index 100% rename from include/asm-arm/arch-kirkwood/cpu.h rename to arch/arm/include/asm/arch-kirkwood/cpu.h diff --git a/include/asm-arm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h similarity index 100% rename from include/asm-arm/arch-kirkwood/gpio.h rename to arch/arm/include/asm/arch-kirkwood/gpio.h diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h similarity index 100% rename from include/asm-arm/arch-kirkwood/kirkwood.h rename to arch/arm/include/asm/arch-kirkwood/kirkwood.h diff --git a/include/asm-arm/arch-kirkwood/kw88f6192.h b/arch/arm/include/asm/arch-kirkwood/kw88f6192.h similarity index 100% rename from include/asm-arm/arch-kirkwood/kw88f6192.h rename to arch/arm/include/asm/arch-kirkwood/kw88f6192.h diff --git a/include/asm-arm/arch-kirkwood/kw88f6281.h b/arch/arm/include/asm/arch-kirkwood/kw88f6281.h similarity index 100% rename from include/asm-arm/arch-kirkwood/kw88f6281.h rename to arch/arm/include/asm/arch-kirkwood/kw88f6281.h diff --git a/include/asm-arm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h similarity index 100% rename from include/asm-arm/arch-kirkwood/mpp.h rename to arch/arm/include/asm/arch-kirkwood/mpp.h diff --git a/include/asm-arm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h similarity index 100% rename from include/asm-arm/arch-kirkwood/spi.h rename to arch/arm/include/asm/arch-kirkwood/spi.h diff --git a/include/asm-arm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h similarity index 100% rename from include/asm-arm/arch-ks8695/platform.h rename to arch/arm/include/asm/arch-ks8695/platform.h diff --git a/arch/arm/include/asm/arch-lpc2292/hardware.h b/arch/arm/include/asm/arch-lpc2292/hardware.h new file mode 100644 index 0000000000..5e227e367c --- /dev/null +++ b/arch/arm/include/asm/arch-lpc2292/hardware.h @@ -0,0 +1,33 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_LPC2292) +#include +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-lpc2292/lpc2292_registers.h b/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h similarity index 100% rename from include/asm-arm/arch-lpc2292/lpc2292_registers.h rename to arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h diff --git a/include/asm-arm/arch-lpc2292/spi.h b/arch/arm/include/asm/arch-lpc2292/spi.h similarity index 100% rename from include/asm-arm/arch-lpc2292/spi.h rename to arch/arm/include/asm/arch-lpc2292/spi.h diff --git a/include/asm-arm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h similarity index 100% rename from include/asm-arm/arch-mx25/clock.h rename to arch/arm/include/asm/arch-mx25/clock.h diff --git a/include/asm-arm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h similarity index 100% rename from include/asm-arm/arch-mx25/imx-regs.h rename to arch/arm/include/asm/arch-mx25/imx-regs.h diff --git a/include/asm-arm/arch-mx25/imx25-pinmux.h b/arch/arm/include/asm/arch-mx25/imx25-pinmux.h similarity index 100% rename from include/asm-arm/arch-mx25/imx25-pinmux.h rename to arch/arm/include/asm/arch-mx25/imx25-pinmux.h diff --git a/include/asm-arm/arch-mx27/asm-offsets.h b/arch/arm/include/asm/arch-mx27/asm-offsets.h similarity index 100% rename from include/asm-arm/arch-mx27/asm-offsets.h rename to arch/arm/include/asm/arch-mx27/asm-offsets.h diff --git a/include/asm-arm/arch-mx27/clock.h b/arch/arm/include/asm/arch-mx27/clock.h similarity index 100% rename from include/asm-arm/arch-mx27/clock.h rename to arch/arm/include/asm/arch-mx27/clock.h diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h new file mode 100644 index 0000000000..6ecddaae85 --- /dev/null +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -0,0 +1,520 @@ +/* + * (c) 2007 Pengutronix, Sascha Hauer + * (c) 2009 Ilya Yanok, Emcraft Systems + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_REGS_H +#define _IMX_REGS_H + +#ifndef __ASSEMBLY__ + +extern void imx_gpio_mode (int gpio_mode); + +#ifdef CONFIG_MXC_UART +extern void mx27_uart_init_pins(void); +#endif /* CONFIG_MXC_UART */ + +#ifdef CONFIG_FEC_MXC +extern void mx27_fec_init_pins(void); +#endif /* CONFIG_FEC_MXC */ + +#ifdef CONFIG_MXC_MMC +extern void mx27_sd1_init_pins(void); +extern void mx27_sd2_init_pins(void); +#endif /* CONFIG_MXC_MMC */ + +/* AIPI */ +struct aipi_regs { + u32 psr0; + u32 psr1; +}; + +/* System Control */ +struct system_control_regs { + u32 res[5]; + u32 fmcr; + u32 gpcr; + u32 wbcr; + u32 dscr1; + u32 dscr2; + u32 dscr3; + u32 dscr4; + u32 dscr5; + u32 dscr6; + u32 dscr7; + u32 dscr8; + u32 dscr9; + u32 dscr10; + u32 dscr11; + u32 dscr12; + u32 dscr13; + u32 pscr; + u32 pmcr; + u32 res1; + u32 dcvr0; + u32 dcvr1; + u32 dcvr2; + u32 dcvr3; +}; + +/* Chip Select Registers */ +struct weim_regs { + u32 cs0u; /* Chip Select 0 Upper Register */ + u32 cs0l; /* Chip Select 0 Lower Register */ + u32 cs0a; /* Chip Select 0 Addition Register */ + u32 pad0; + u32 cs1u; /* Chip Select 1 Upper Register */ + u32 cs1l; /* Chip Select 1 Lower Register */ + u32 cs1a; /* Chip Select 1 Addition Register */ + u32 pad1; + u32 cs2u; /* Chip Select 2 Upper Register */ + u32 cs2l; /* Chip Select 2 Lower Register */ + u32 cs2a; /* Chip Select 2 Addition Register */ + u32 pad2; + u32 cs3u; /* Chip Select 3 Upper Register */ + u32 cs3l; /* Chip Select 3 Lower Register */ + u32 cs3a; /* Chip Select 3 Addition Register */ + u32 pad3; + u32 cs4u; /* Chip Select 4 Upper Register */ + u32 cs4l; /* Chip Select 4 Lower Register */ + u32 cs4a; /* Chip Select 4 Addition Register */ + u32 pad4; + u32 cs5u; /* Chip Select 5 Upper Register */ + u32 cs5l; /* Chip Select 5 Lower Register */ + u32 cs5a; /* Chip Select 5 Addition Register */ + u32 pad5; + u32 eim; /* WEIM Configuration Register */ +}; + +/* SDRAM Controller registers */ +struct esdramc_regs { +/* Enhanced SDRAM Control Register 0 */ + u32 esdctl0; +/* Enhanced SDRAM Configuration Register 0 */ + u32 esdcfg0; +/* Enhanced SDRAM Control Register 1 */ + u32 esdctl1; +/* Enhanced SDRAM Configuration Register 1 */ + u32 esdcfg1; +/* Enhanced SDRAM Miscellanious Register */ + u32 esdmisc; +}; + +/* Watchdog Registers*/ +struct wdog_regs { + u32 wcr; + u32 wsr; + u32 wstr; +}; + +/* PLL registers */ +struct pll_regs { + u32 cscr; /* Clock Source Control Register */ + u32 mpctl0; /* MCU PLL Control Register 0 */ + u32 mpctl1; /* MCU PLL Control Register 1 */ + u32 spctl0; /* System PLL Control Register 0 */ + u32 spctl1; /* System PLL Control Register 1 */ + u32 osc26mctl; /* Oscillator 26M Register */ + u32 pcdr0; /* Peripheral Clock Divider Register 0 */ + u32 pcdr1; /* Peripheral Clock Divider Register 1 */ + u32 pccr0; /* Peripheral Clock Control Register 0 */ + u32 pccr1; /* Peripheral Clock Control Register 1 */ + u32 ccsr; /* Clock Control Status Register */ +}; + +/* + * Definitions for the clocksource registers + */ +struct gpt_regs { + u32 gpt_tctl; + u32 gpt_tprer; + u32 gpt_tcmp; + u32 gpt_tcr; + u32 gpt_tcn; + u32 gpt_tstat; +}; + +/* + * GPIO Module and I/O Multiplexer + */ +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTD 3 +#define PORTE 4 +#define PORTF 5 + +struct gpio_regs { + struct { + u32 ddir; + u32 ocr1; + u32 ocr2; + u32 iconfa1; + u32 iconfa2; + u32 iconfb1; + u32 iconfb2; + u32 dr; + u32 gius; + u32 ssr; + u32 icr1; + u32 icr2; + u32 imr; + u32 isr; + u32 gpr; + u32 swr; + u32 puen; + u32 res[0x2f]; + } port[6]; +}; + +/* IIM Control Registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; + u32 res[0x1F0]; + u32 iim_bank_area0[0x100]; +}; +#endif + +#define IMX_IO_BASE 0x10000000 + +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) +#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) +#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) +#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) +#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) +#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) +#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) +#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) +#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) +#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE) +#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) +#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) +#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) +#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) + +#define IMX_ESD_BASE (0xD8001000) +#define IMX_WEIM_BASE (0xD8002000) + +/* FMCR System Control bit definition*/ +#define UART4_RXD_CTL (1 << 25) +#define UART4_RTS_CTL (1 << 24) +#define KP_COL6_CTL (1 << 18) +#define KP_ROW7_CTL (1 << 17) +#define KP_ROW6_CTL (1 << 16) +#define PC_WAIT_B_CTL (1 << 14) +#define PC_READY_CTL (1 << 13) +#define PC_VS1_CTL (1 << 12) +#define PC_VS2_CTL (1 << 11) +#define PC_BVD1_CTL (1 << 10) +#define PC_BVD2_CTL (1 << 9) +#define IOS16_CTL (1 << 8) +#define NF_FMS (1 << 5) +#define NF_16BIT_SEL (1 << 4) +#define SLCDC_SEL (1 << 2) +#define SDCS1_SEL (1 << 1) +#define SDCS0_SEL (1 << 0) + + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +#define CSCR_MPEN (1 << 0) +#define CSCR_SPEN (1 << 1) +#define CSCR_FPM_EN (1 << 2) +#define CSCR_OSC26M_DIS (1 << 3) +#define CSCR_OSC26M_DIV1P5 (1 << 4) +#define CSCR_AHB_DIV +#define CSCR_ARM_DIV +#define CSCR_ARM_SRC_MPLL (1 << 15) +#define CSCR_MCU_SEL (1 << 16) +#define CSCR_SP_SEL (1 << 17) +#define CSCR_MPLL_RESTART (1 << 18) +#define CSCR_SPLL_RESTART (1 << 19) +#define CSCR_MSHC_SEL (1 << 20) +#define CSCR_H264_SEL (1 << 21) +#define CSCR_SSI1_SEL (1 << 22) +#define CSCR_SSI2_SEL (1 << 23) +#define CSCR_SD_CNT +#define CSCR_USB_DIV +#define CSCR_UPDATE_DIS (1 << 31) + +#define MPCTL1_BRMO (1 << 6) +#define MPCTL1_LF (1 << 15) + +#define PCCR0_SSI2_EN (1 << 0) +#define PCCR0_SSI1_EN (1 << 1) +#define PCCR0_SLCDC_EN (1 << 2) +#define PCCR0_SDHC3_EN (1 << 3) +#define PCCR0_SDHC2_EN (1 << 4) +#define PCCR0_SDHC1_EN (1 << 5) +#define PCCR0_SDC_EN (1 << 6) +#define PCCR0_SAHARA_EN (1 << 7) +#define PCCR0_RTIC_EN (1 << 8) +#define PCCR0_RTC_EN (1 << 9) +#define PCCR0_PWM_EN (1 << 11) +#define PCCR0_OWIRE_EN (1 << 12) +#define PCCR0_MSHC_EN (1 << 13) +#define PCCR0_LCDC_EN (1 << 14) +#define PCCR0_KPP_EN (1 << 15) +#define PCCR0_IIM_EN (1 << 16) +#define PCCR0_I2C2_EN (1 << 17) +#define PCCR0_I2C1_EN (1 << 18) +#define PCCR0_GPT6_EN (1 << 19) +#define PCCR0_GPT5_EN (1 << 20) +#define PCCR0_GPT4_EN (1 << 21) +#define PCCR0_GPT3_EN (1 << 22) +#define PCCR0_GPT2_EN (1 << 23) +#define PCCR0_GPT1_EN (1 << 24) +#define PCCR0_GPIO_EN (1 << 25) +#define PCCR0_FEC_EN (1 << 26) +#define PCCR0_EMMA_EN (1 << 27) +#define PCCR0_DMA_EN (1 << 28) +#define PCCR0_CSPI3_EN (1 << 29) +#define PCCR0_CSPI2_EN (1 << 30) +#define PCCR0_CSPI1_EN (1 << 31) + +#define PCCR1_MSHC_BAUDEN (1 << 2) +#define PCCR1_NFC_BAUDEN (1 << 3) +#define PCCR1_SSI2_BAUDEN (1 << 4) +#define PCCR1_SSI1_BAUDEN (1 << 5) +#define PCCR1_H264_BAUDEN (1 << 6) +#define PCCR1_PERCLK4_EN (1 << 7) +#define PCCR1_PERCLK3_EN (1 << 8) +#define PCCR1_PERCLK2_EN (1 << 9) +#define PCCR1_PERCLK1_EN (1 << 10) +#define PCCR1_HCLK_USB (1 << 11) +#define PCCR1_HCLK_SLCDC (1 << 12) +#define PCCR1_HCLK_SAHARA (1 << 13) +#define PCCR1_HCLK_RTIC (1 << 14) +#define PCCR1_HCLK_LCDC (1 << 15) +#define PCCR1_HCLK_H264 (1 << 16) +#define PCCR1_HCLK_FEC (1 << 17) +#define PCCR1_HCLK_EMMA (1 << 18) +#define PCCR1_HCLK_EMI (1 << 19) +#define PCCR1_HCLK_DMA (1 << 20) +#define PCCR1_HCLK_CSI (1 << 21) +#define PCCR1_HCLK_BROM (1 << 22) +#define PCCR1_HCLK_ATA (1 << 23) +#define PCCR1_WDT_EN (1 << 24) +#define PCCR1_USB_EN (1 << 25) +#define PCCR1_UART6_EN (1 << 26) +#define PCCR1_UART5_EN (1 << 27) +#define PCCR1_UART4_EN (1 << 28) +#define PCCR1_UART3_EN (1 << 29) +#define PCCR1_UART2_EN (1 << 30) +#define PCCR1_UART1_EN (1 << 31) + +/* SDRAM Controller registers bitfields */ +#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) +#define ESDCTL_BL (1 << 7) +#define ESDCTL_FP (1 << 8) +#define ESDCTL_PWDT(x) (((x) & 3) << 10) +#define ESDCTL_SREFR(x) (((x) & 7) << 13) +#define ESDCTL_DSIZ_16_UPPER (0 << 16) +#define ESDCTL_DSIZ_16_LOWER (1 << 16) +#define ESDCTL_DSIZ_32 (2 << 16) +#define ESDCTL_COL8 (0 << 20) +#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL10 (2 << 20) +#define ESDCTL_ROW11 (0 << 24) +#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW13 (2 << 24) +#define ESDCTL_ROW14 (3 << 24) +#define ESDCTL_ROW15 (4 << 24) +#define ESDCTL_SP (1 << 27) +#define ESDCTL_SMODE_NORMAL (0 << 28) +#define ESDCTL_SMODE_PRECHARGE (1 << 28) +#define ESDCTL_SMODE_AUTO_REF (2 << 28) +#define ESDCTL_SMODE_LOAD_MODE (3 << 28) +#define ESDCTL_SMODE_MAN_REF (4 << 28) +#define ESDCTL_SDE (1 << 31) + +#define ESDCFG_TRC(x) (((x) & 0xf) << 0) +#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) +#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) +#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) +#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) +#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) +#define ESDCFG_TRP(x) (((x) & 0x3) << 18) +#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TXP(x) (((x) & 0x3) << 21) + +#define ESDMISC_RST (1 << 1) +#define ESDMISC_MDDREN (1 << 2) +#define ESDMISC_MDDR_DL_RST (1 << 3) +#define ESDMISC_MDDR_MDIS (1 << 4) +#define ESDMISC_LHD (1 << 5) +#define ESDMISC_MA10_SHARE (1 << 6) +#define ESDMISC_SDRAM_RDY (1 << 31) + +#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) +#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) + +#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) +#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) +#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) +#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) +#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) +#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) +#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) +#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) +#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) +#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) +#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) +#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) +#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) +#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) +#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) +#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) +#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) +#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) + +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) +#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) +#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) +#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) +#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) +#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) +#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) +#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) +#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) +#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) +#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) +#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) +#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) +#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) +#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) +#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) +#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) +#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) +#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) +#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) +#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) +#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) +#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) + +/* Clocksource Bitfields */ +#define TCTL_SWR (1 << 15) /* Software reset */ +#define TCTL_FRR (1 << 8) /* Freerun / restart */ +#define TCTL_CAP (3 << 6) /* Capture Edge */ +#define TCTL_OM (1 << 5) /* output mode */ +#define TCTL_IRQEN (1 << 4) /* interrupt enable */ +#define TCTL_CLKSOURCE 1 /* Clock source bit position */ +#define TCTL_TEN 1 /* Timer enable */ +#define TPRER_PRES 0xff /* Prescale */ +#define TSTAT_CAPT (1 << 1) /* Capture event */ +#define TSTAT_COMP 1 /* Compare event */ + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) +#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) +#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) +#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) +#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) +#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) + +#define GPIO_OUT (1 << 8) +#define GPIO_IN (0 << 8) +#define GPIO_PUEN (1 << 9) + +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) + +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) + +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) + +/* Definitions for i.MX27 TO2 */ +#define IIM0_MAC 5 +#define IIM0_SCC_KEY 11 +#define IIM1_SUID 1 + +#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h similarity index 100% rename from include/asm-arm/arch-mx27/mxcmmc.h rename to arch/arm/include/asm/arch-mx27/mxcmmc.h diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h similarity index 100% rename from include/asm-arm/arch-mx31/mx31-regs.h rename to arch/arm/include/asm/arch-mx31/mx31-regs.h diff --git a/include/asm-arm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h similarity index 100% rename from include/asm-arm/arch-mx31/mx31.h rename to arch/arm/include/asm/arch-mx31/mx31.h diff --git a/arch/arm/include/asm/arch-mx51/asm-offsets.h b/arch/arm/include/asm/arch-mx51/asm-offsets.h new file mode 100644 index 0000000000..fbba412aab --- /dev/null +++ b/arch/arm/include/asm/arch-mx51/asm-offsets.h @@ -0,0 +1,50 @@ +/* + * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S + * + * These should be auto-generated + */ +/* CCM */ +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CMEOR 0x84 + +/* DPLL */ +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 diff --git a/include/asm-arm/arch-mx51/clock.h b/arch/arm/include/asm/arch-mx51/clock.h similarity index 100% rename from include/asm-arm/arch-mx51/clock.h rename to arch/arm/include/asm/arch-mx51/clock.h diff --git a/include/asm-arm/arch-mx51/crm_regs.h b/arch/arm/include/asm/arch-mx51/crm_regs.h similarity index 100% rename from include/asm-arm/arch-mx51/crm_regs.h rename to arch/arm/include/asm/arch-mx51/crm_regs.h diff --git a/include/asm-arm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx51/imx-regs.h similarity index 100% rename from include/asm-arm/arch-mx51/imx-regs.h rename to arch/arm/include/asm/arch-mx51/imx-regs.h diff --git a/include/asm-arm/arch-mx51/iomux.h b/arch/arm/include/asm/arch-mx51/iomux.h similarity index 100% rename from include/asm-arm/arch-mx51/iomux.h rename to arch/arm/include/asm/arch-mx51/iomux.h diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx51/mx51_pins.h similarity index 100% rename from include/asm-arm/arch-mx51/mx51_pins.h rename to arch/arm/include/asm/arch-mx51/mx51_pins.h diff --git a/include/asm-arm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx51/sys_proto.h similarity index 100% rename from include/asm-arm/arch-mx51/sys_proto.h rename to arch/arm/include/asm/arch-mx51/sys_proto.h diff --git a/include/asm-arm/arch-nomadik/gpio.h b/arch/arm/include/asm/arch-nomadik/gpio.h similarity index 100% rename from include/asm-arm/arch-nomadik/gpio.h rename to arch/arm/include/asm/arch-nomadik/gpio.h diff --git a/include/asm-arm/arch-nomadik/mtu.h b/arch/arm/include/asm/arch-nomadik/mtu.h similarity index 100% rename from include/asm-arm/arch-nomadik/mtu.h rename to arch/arm/include/asm/arch-nomadik/mtu.h diff --git a/include/asm-arm/arch-omap/sizes.h b/arch/arm/include/asm/arch-omap/sizes.h similarity index 100% rename from include/asm-arm/arch-omap/sizes.h rename to arch/arm/include/asm/arch-omap/sizes.h diff --git a/include/asm-arm/arch-omap24xx/bits.h b/arch/arm/include/asm/arch-omap24xx/bits.h similarity index 100% rename from include/asm-arm/arch-omap24xx/bits.h rename to arch/arm/include/asm/arch-omap24xx/bits.h diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/arch/arm/include/asm/arch-omap24xx/clocks.h similarity index 100% rename from include/asm-arm/arch-omap24xx/clocks.h rename to arch/arm/include/asm/arch-omap24xx/clocks.h diff --git a/include/asm-arm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h similarity index 100% rename from include/asm-arm/arch-omap24xx/i2c.h rename to arch/arm/include/asm/arch-omap24xx/i2c.h diff --git a/include/asm-arm/arch-omap24xx/mem.h b/arch/arm/include/asm/arch-omap24xx/mem.h similarity index 100% rename from include/asm-arm/arch-omap24xx/mem.h rename to arch/arm/include/asm/arch-omap24xx/mem.h diff --git a/include/asm-arm/arch-omap24xx/mux.h b/arch/arm/include/asm/arch-omap24xx/mux.h similarity index 100% rename from include/asm-arm/arch-omap24xx/mux.h rename to arch/arm/include/asm/arch-omap24xx/mux.h diff --git a/include/asm-arm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h similarity index 100% rename from include/asm-arm/arch-omap24xx/omap2420.h rename to arch/arm/include/asm/arch-omap24xx/omap2420.h diff --git a/include/asm-arm/arch-omap24xx/sizes.h b/arch/arm/include/asm/arch-omap24xx/sizes.h similarity index 100% rename from include/asm-arm/arch-omap24xx/sizes.h rename to arch/arm/include/asm/arch-omap24xx/sizes.h diff --git a/include/asm-arm/arch-omap24xx/sys_info.h b/arch/arm/include/asm/arch-omap24xx/sys_info.h similarity index 100% rename from include/asm-arm/arch-omap24xx/sys_info.h rename to arch/arm/include/asm/arch-omap24xx/sys_info.h diff --git a/include/asm-arm/arch-omap24xx/sys_proto.h b/arch/arm/include/asm/arch-omap24xx/sys_proto.h similarity index 100% rename from include/asm-arm/arch-omap24xx/sys_proto.h rename to arch/arm/include/asm/arch-omap24xx/sys_proto.h diff --git a/include/asm-arm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clocks.h similarity index 100% rename from include/asm-arm/arch-omap3/clocks.h rename to arch/arm/include/asm/arch-omap3/clocks.h diff --git a/include/asm-arm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h similarity index 100% rename from include/asm-arm/arch-omap3/clocks_omap3.h rename to arch/arm/include/asm/arch-omap3/clocks_omap3.h diff --git a/include/asm-arm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h similarity index 100% rename from include/asm-arm/arch-omap3/cpu.h rename to arch/arm/include/asm/arch-omap3/cpu.h diff --git a/include/asm-arm/arch-omap3/gpio.h b/arch/arm/include/asm/arch-omap3/gpio.h similarity index 100% rename from include/asm-arm/arch-omap3/gpio.h rename to arch/arm/include/asm/arch-omap3/gpio.h diff --git a/include/asm-arm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h similarity index 100% rename from include/asm-arm/arch-omap3/i2c.h rename to arch/arm/include/asm/arch-omap3/i2c.h diff --git a/include/asm-arm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h similarity index 100% rename from include/asm-arm/arch-omap3/mem.h rename to arch/arm/include/asm/arch-omap3/mem.h diff --git a/include/asm-arm/arch-omap3/mmc.h b/arch/arm/include/asm/arch-omap3/mmc.h similarity index 100% rename from include/asm-arm/arch-omap3/mmc.h rename to arch/arm/include/asm/arch-omap3/mmc.h diff --git a/include/asm-arm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h similarity index 100% rename from include/asm-arm/arch-omap3/mmc_host_def.h rename to arch/arm/include/asm/arch-omap3/mmc_host_def.h diff --git a/include/asm-arm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h similarity index 100% rename from include/asm-arm/arch-omap3/mux.h rename to arch/arm/include/asm/arch-omap3/mux.h diff --git a/include/asm-arm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h similarity index 100% rename from include/asm-arm/arch-omap3/omap3.h rename to arch/arm/include/asm/arch-omap3/omap3.h diff --git a/include/asm-arm/arch-omap3/omap_gpmc.h b/arch/arm/include/asm/arch-omap3/omap_gpmc.h similarity index 100% rename from include/asm-arm/arch-omap3/omap_gpmc.h rename to arch/arm/include/asm/arch-omap3/omap_gpmc.h diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h similarity index 100% rename from include/asm-arm/arch-omap3/sys_proto.h rename to arch/arm/include/asm/arch-omap3/sys_proto.h diff --git a/include/asm-arm/arch-pxa/bitfield.h b/arch/arm/include/asm/arch-pxa/bitfield.h similarity index 100% rename from include/asm-arm/arch-pxa/bitfield.h rename to arch/arm/include/asm/arch-pxa/bitfield.h diff --git a/include/asm-arm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h similarity index 100% rename from include/asm-arm/arch-pxa/hardware.h rename to arch/arm/include/asm/arch-pxa/hardware.h diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h similarity index 100% rename from include/asm-arm/arch-pxa/pxa-regs.h rename to arch/arm/include/asm/arch-pxa/pxa-regs.h diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/arch/arm/include/asm/arch-s3c24x0/memory.h similarity index 100% rename from include/asm-arm/arch-s3c24x0/memory.h rename to arch/arm/include/asm/arch-s3c24x0/memory.h diff --git a/include/asm-arm/arch-s3c24x0/s3c2400.h b/arch/arm/include/asm/arch-s3c24x0/s3c2400.h similarity index 100% rename from include/asm-arm/arch-s3c24x0/s3c2400.h rename to arch/arm/include/asm/arch-s3c24x0/s3c2400.h diff --git a/include/asm-arm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h similarity index 100% rename from include/asm-arm/arch-s3c24x0/s3c2410.h rename to arch/arm/include/asm/arch-s3c24x0/s3c2410.h diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h similarity index 100% rename from include/asm-arm/arch-s3c24x0/s3c24x0.h rename to arch/arm/include/asm/arch-s3c24x0/s3c24x0.h diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h similarity index 100% rename from include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h rename to arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h diff --git a/include/asm-arm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h similarity index 100% rename from include/asm-arm/arch-s3c44b0/hardware.h rename to arch/arm/include/asm/arch-s3c44b0/hardware.h diff --git a/include/asm-arm/arch-s3c4510b/hardware.h b/arch/arm/include/asm/arch-s3c4510b/hardware.h similarity index 100% rename from include/asm-arm/arch-s3c4510b/hardware.h rename to arch/arm/include/asm/arch-s3c4510b/hardware.h diff --git a/include/asm-arm/arch-s3c64xx/hardware.h b/arch/arm/include/asm/arch-s3c64xx/hardware.h similarity index 100% rename from include/asm-arm/arch-s3c64xx/hardware.h rename to arch/arm/include/asm/arch-s3c64xx/hardware.h diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h similarity index 100% rename from include/asm-arm/arch-s3c64xx/s3c6400.h rename to arch/arm/include/asm/arch-s3c64xx/s3c6400.h diff --git a/include/asm-arm/arch-s3c64xx/s3c64x0.h b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h similarity index 100% rename from include/asm-arm/arch-s3c64xx/s3c64x0.h rename to arch/arm/include/asm/arch-s3c64xx/s3c64x0.h diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/arch/arm/include/asm/arch-s5pc1xx/clk.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/clk.h rename to arch/arm/include/asm/arch-s5pc1xx/clk.h diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/arch/arm/include/asm/arch-s5pc1xx/clock.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/clock.h rename to arch/arm/include/asm/arch-s5pc1xx/clock.h diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/cpu.h rename to arch/arm/include/asm/arch-s5pc1xx/cpu.h diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/gpio.h rename to arch/arm/include/asm/arch-s5pc1xx/gpio.h diff --git a/include/asm-arm/arch-s5pc1xx/power.h b/arch/arm/include/asm/arch-s5pc1xx/power.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/power.h rename to arch/arm/include/asm/arch-s5pc1xx/power.h diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/pwm.h rename to arch/arm/include/asm/arch-s5pc1xx/pwm.h diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/arch/arm/include/asm/arch-s5pc1xx/smc.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/smc.h rename to arch/arm/include/asm/arch-s5pc1xx/smc.h diff --git a/include/asm-arm/arch-s5pc1xx/sys_proto.h b/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/sys_proto.h rename to arch/arm/include/asm/arch-s5pc1xx/sys_proto.h diff --git a/include/asm-arm/arch-s5pc1xx/uart.h b/arch/arm/include/asm/arch-s5pc1xx/uart.h similarity index 100% rename from include/asm-arm/arch-s5pc1xx/uart.h rename to arch/arm/include/asm/arch-s5pc1xx/uart.h diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/arch/arm/include/asm/arch-sa1100/bitfield.h similarity index 100% rename from include/asm-arm/arch-sa1100/bitfield.h rename to arch/arm/include/asm/arch-sa1100/bitfield.h diff --git a/include/asm-arm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h similarity index 100% rename from include/asm-arm/arch-spear/hardware.h rename to arch/arm/include/asm/arch-spear/hardware.h diff --git a/include/asm-arm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h similarity index 100% rename from include/asm-arm/arch-spear/spr_defs.h rename to arch/arm/include/asm/arch-spear/spr_defs.h diff --git a/include/asm-arm/arch-spear/spr_emi.h b/arch/arm/include/asm/arch-spear/spr_emi.h similarity index 100% rename from include/asm-arm/arch-spear/spr_emi.h rename to arch/arm/include/asm/arch-spear/spr_emi.h diff --git a/include/asm-arm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h similarity index 100% rename from include/asm-arm/arch-spear/spr_gpt.h rename to arch/arm/include/asm/arch-spear/spr_gpt.h diff --git a/include/asm-arm/arch-spear/spr_i2c.h b/arch/arm/include/asm/arch-spear/spr_i2c.h similarity index 100% rename from include/asm-arm/arch-spear/spr_i2c.h rename to arch/arm/include/asm/arch-spear/spr_i2c.h diff --git a/include/asm-arm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h similarity index 100% rename from include/asm-arm/arch-spear/spr_misc.h rename to arch/arm/include/asm/arch-spear/spr_misc.h diff --git a/include/asm-arm/arch-spear/spr_nand.h b/arch/arm/include/asm/arch-spear/spr_nand.h similarity index 100% rename from include/asm-arm/arch-spear/spr_nand.h rename to arch/arm/include/asm/arch-spear/spr_nand.h diff --git a/include/asm-arm/arch-spear/spr_smi.h b/arch/arm/include/asm/arch-spear/spr_smi.h similarity index 100% rename from include/asm-arm/arch-spear/spr_smi.h rename to arch/arm/include/asm/arch-spear/spr_smi.h diff --git a/include/asm-arm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h similarity index 100% rename from include/asm-arm/arch-spear/spr_syscntl.h rename to arch/arm/include/asm/arch-spear/spr_syscntl.h diff --git a/include/asm-arm/arch-spear/spr_xloader_table.h b/arch/arm/include/asm/arch-spear/spr_xloader_table.h similarity index 100% rename from include/asm-arm/arch-spear/spr_xloader_table.h rename to arch/arm/include/asm/arch-spear/spr_xloader_table.h diff --git a/include/asm-arm/atomic.h b/arch/arm/include/asm/atomic.h similarity index 100% rename from include/asm-arm/atomic.h rename to arch/arm/include/asm/atomic.h diff --git a/include/asm-arm/bitops.h b/arch/arm/include/asm/bitops.h similarity index 100% rename from include/asm-arm/bitops.h rename to arch/arm/include/asm/bitops.h diff --git a/include/asm-arm/byteorder.h b/arch/arm/include/asm/byteorder.h similarity index 100% rename from include/asm-arm/byteorder.h rename to arch/arm/include/asm/byteorder.h diff --git a/include/asm-arm/cache.h b/arch/arm/include/asm/cache.h similarity index 100% rename from include/asm-arm/cache.h rename to arch/arm/include/asm/cache.h diff --git a/include/asm-arm/config.h b/arch/arm/include/asm/config.h similarity index 100% rename from include/asm-arm/config.h rename to arch/arm/include/asm/config.h diff --git a/include/asm-arm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h similarity index 100% rename from include/asm-arm/dma-mapping.h rename to arch/arm/include/asm/dma-mapping.h diff --git a/include/asm-arm/errno.h b/arch/arm/include/asm/errno.h similarity index 100% rename from include/asm-arm/errno.h rename to arch/arm/include/asm/errno.h diff --git a/include/asm-arm/global_data.h b/arch/arm/include/asm/global_data.h similarity index 100% rename from include/asm-arm/global_data.h rename to arch/arm/include/asm/global_data.h diff --git a/include/asm-arm/hardware.h b/arch/arm/include/asm/hardware.h similarity index 100% rename from include/asm-arm/hardware.h rename to arch/arm/include/asm/hardware.h diff --git a/include/asm-arm/io.h b/arch/arm/include/asm/io.h similarity index 100% rename from include/asm-arm/io.h rename to arch/arm/include/asm/io.h diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h new file mode 100644 index 0000000000..b33e97b5fa --- /dev/null +++ b/arch/arm/include/asm/mach-types.h @@ -0,0 +1,35917 @@ +/* + * This was automagically generated from arch/arm/tools/mach-types! + * Do NOT edit + */ + +#ifndef __ASM_ARM_MACH_TYPE_H +#define __ASM_ARM_MACH_TYPE_H + +#ifndef __ASSEMBLY__ +/* The type of machine we're running on */ +extern unsigned int __machine_arch_type; +#endif + +/* see arch/arm/kernel/arch.c for a description of these */ +#define MACH_TYPE_EBSA110 0 +#define MACH_TYPE_RISCPC 1 +#define MACH_TYPE_NEXUSPCI 3 +#define MACH_TYPE_EBSA285 4 +#define MACH_TYPE_NETWINDER 5 +#define MACH_TYPE_CATS 6 +#define MACH_TYPE_TBOX 7 +#define MACH_TYPE_CO285 8 +#define MACH_TYPE_CLPS7110 9 +#define MACH_TYPE_ARCHIMEDES 10 +#define MACH_TYPE_A5K 11 +#define MACH_TYPE_ETOILE 12 +#define MACH_TYPE_LACIE_NAS 13 +#define MACH_TYPE_CLPS7500 14 +#define MACH_TYPE_SHARK 15 +#define MACH_TYPE_BRUTUS 16 +#define MACH_TYPE_PERSONAL_SERVER 17 +#define MACH_TYPE_ITSY 18 +#define MACH_TYPE_L7200 19 +#define MACH_TYPE_PLEB 20 +#define MACH_TYPE_INTEGRATOR 21 +#define MACH_TYPE_H3600 22 +#define MACH_TYPE_IXP1200 23 +#define MACH_TYPE_P720T 24 +#define MACH_TYPE_ASSABET 25 +#define MACH_TYPE_VICTOR 26 +#define MACH_TYPE_LART 27 +#define MACH_TYPE_RANGER 28 +#define MACH_TYPE_GRAPHICSCLIENT 29 +#define MACH_TYPE_XP860 30 +#define MACH_TYPE_CERF 31 +#define MACH_TYPE_NANOENGINE 32 +#define MACH_TYPE_FPIC 33 +#define MACH_TYPE_EXTENEX1 34 +#define MACH_TYPE_SHERMAN 35 +#define MACH_TYPE_ACCELENT_SA 36 +#define MACH_TYPE_ACCELENT_L7200 37 +#define MACH_TYPE_NETPORT 38 +#define MACH_TYPE_PANGOLIN 39 +#define MACH_TYPE_YOPY 40 +#define MACH_TYPE_COOLIDGE 41 +#define MACH_TYPE_HUW_WEBPANEL 42 +#define MACH_TYPE_SPOTME 43 +#define MACH_TYPE_FREEBIRD 44 +#define MACH_TYPE_TI925 45 +#define MACH_TYPE_RISCSTATION 46 +#define MACH_TYPE_CAVY 47 +#define MACH_TYPE_JORNADA720 48 +#define MACH_TYPE_OMNIMETER 49 +#define MACH_TYPE_EDB7211 50 +#define MACH_TYPE_CITYGO 51 +#define MACH_TYPE_PFS168 52 +#define MACH_TYPE_SPOT 53 +#define MACH_TYPE_FLEXANET 54 +#define MACH_TYPE_WEBPAL 55 +#define MACH_TYPE_LINPDA 56 +#define MACH_TYPE_ANAKIN 57 +#define MACH_TYPE_MVI 58 +#define MACH_TYPE_JUPITER 59 +#define MACH_TYPE_PSIONW 60 +#define MACH_TYPE_ALN 61 +#define MACH_TYPE_CAMELOT 62 +#define MACH_TYPE_GDS2200 63 +#define MACH_TYPE_PSION_SERIES7 64 +#define MACH_TYPE_XFILE 65 +#define MACH_TYPE_ACCELENT_EP9312 66 +#define MACH_TYPE_IC200 67 +#define MACH_TYPE_CREDITLART 68 +#define MACH_TYPE_HTM 69 +#define MACH_TYPE_IQ80310 70 +#define MACH_TYPE_FREEBOT 71 +#define MACH_TYPE_ENTEL 72 +#define MACH_TYPE_ENP3510 73 +#define MACH_TYPE_TRIZEPS 74 +#define MACH_TYPE_NESA 75 +#define MACH_TYPE_VENUS 76 +#define MACH_TYPE_TARDIS 77 +#define MACH_TYPE_MERCURY 78 +#define MACH_TYPE_EMPEG 79 +#define MACH_TYPE_I80200FCC 80 +#define MACH_TYPE_ITT_CPB 81 +#define MACH_TYPE_SVC 82 +#define MACH_TYPE_ALPHA2 84 +#define MACH_TYPE_ALPHA1 85 +#define MACH_TYPE_NETARM 86 +#define MACH_TYPE_SIMPAD 87 +#define MACH_TYPE_PDA1 88 +#define MACH_TYPE_LUBBOCK 89 +#define MACH_TYPE_ANIKO 90 +#define MACH_TYPE_CLEP7212 91 +#define MACH_TYPE_CS89712 92 +#define MACH_TYPE_WEARARM 93 +#define MACH_TYPE_POSSIO_PX 94 +#define MACH_TYPE_SIDEARM 95 +#define MACH_TYPE_STORK 96 +#define MACH_TYPE_SHANNON 97 +#define MACH_TYPE_ACE 98 +#define MACH_TYPE_BALLYARM 99 +#define MACH_TYPE_SIMPUTER 100 +#define MACH_TYPE_NEXTERM 101 +#define MACH_TYPE_SA1100_ELF 102 +#define MACH_TYPE_GATOR 103 +#define MACH_TYPE_GRANITE 104 +#define MACH_TYPE_CONSUS 105 +#define MACH_TYPE_AAED2000 106 +#define MACH_TYPE_CDB89712 107 +#define MACH_TYPE_GRAPHICSMASTER 108 +#define MACH_TYPE_ADSBITSY 109 +#define MACH_TYPE_PXA_IDP 110 +#define MACH_TYPE_PLCE 111 +#define MACH_TYPE_PT_SYSTEM3 112 +#define MACH_TYPE_MEDALB 113 +#define MACH_TYPE_EAGLE 114 +#define MACH_TYPE_DSC21 115 +#define MACH_TYPE_DSC24 116 +#define MACH_TYPE_TI5472 117 +#define MACH_TYPE_AUTCPU12 118 +#define MACH_TYPE_UENGINE 119 +#define MACH_TYPE_BLUESTEM 120 +#define MACH_TYPE_XINGU8 121 +#define MACH_TYPE_BUSHSTB 122 +#define MACH_TYPE_EPSILON1 123 +#define MACH_TYPE_BALLOON 124 +#define MACH_TYPE_PUPPY 125 +#define MACH_TYPE_ELROY 126 +#define MACH_TYPE_GMS720 127 +#define MACH_TYPE_S24X 128 +#define MACH_TYPE_JTEL_CLEP7312 129 +#define MACH_TYPE_CX821XX 130 +#define MACH_TYPE_EDB7312 131 +#define MACH_TYPE_BSA1110 132 +#define MACH_TYPE_POWERPIN 133 +#define MACH_TYPE_OPENARM 134 +#define MACH_TYPE_WHITECHAPEL 135 +#define MACH_TYPE_H3100 136 +#define MACH_TYPE_H3800 137 +#define MACH_TYPE_BLUE_V1 138 +#define MACH_TYPE_PXA_CERF 139 +#define MACH_TYPE_ARM7TEVB 140 +#define MACH_TYPE_D7400 141 +#define MACH_TYPE_PIRANHA 142 +#define MACH_TYPE_SBCAMELOT 143 +#define MACH_TYPE_KINGS 144 +#define MACH_TYPE_SMDK2400 145 +#define MACH_TYPE_COLLIE 146 +#define MACH_TYPE_IDR 147 +#define MACH_TYPE_BADGE4 148 +#define MACH_TYPE_WEBNET 149 +#define MACH_TYPE_D7300 150 +#define MACH_TYPE_CEP 151 +#define MACH_TYPE_FORTUNET 152 +#define MACH_TYPE_VC547X 153 +#define MACH_TYPE_FILEWALKER 154 +#define MACH_TYPE_NETGATEWAY 155 +#define MACH_TYPE_SYMBOL2800 156 +#define MACH_TYPE_SUNS 157 +#define MACH_TYPE_FRODO 158 +#define MACH_TYPE_MACH_TYTE_MS301 159 +#define MACH_TYPE_MX1ADS 160 +#define MACH_TYPE_H7201 161 +#define MACH_TYPE_H7202 162 +#define MACH_TYPE_AMICO 163 +#define MACH_TYPE_IAM 164 +#define MACH_TYPE_TT530 165 +#define MACH_TYPE_SAM2400 166 +#define MACH_TYPE_JORNADA56X 167 +#define MACH_TYPE_ACTIVE 168 +#define MACH_TYPE_IQ80321 169 +#define MACH_TYPE_WID 170 +#define MACH_TYPE_SABINAL 171 +#define MACH_TYPE_IXP425_MATACUMBE 172 +#define MACH_TYPE_MINIPRINT 173 +#define MACH_TYPE_ADM510X 174 +#define MACH_TYPE_SVS200 175 +#define MACH_TYPE_ATG_TCU 176 +#define MACH_TYPE_JORNADA820 177 +#define MACH_TYPE_S3C44B0 178 +#define MACH_TYPE_MARGIS2 179 +#define MACH_TYPE_KS8695 180 +#define MACH_TYPE_BRH 181 +#define MACH_TYPE_S3C2410 182 +#define MACH_TYPE_POSSIO_PX30 183 +#define MACH_TYPE_S3C2800 184 +#define MACH_TYPE_FLEETWOOD 185 +#define MACH_TYPE_OMAHA 186 +#define MACH_TYPE_TA7 187 +#define MACH_TYPE_NOVA 188 +#define MACH_TYPE_HMK 189 +#define MACH_TYPE_KARO 190 +#define MACH_TYPE_FESTER 191 +#define MACH_TYPE_GPI 192 +#define MACH_TYPE_SMDK2410 193 +#define MACH_TYPE_I519 194 +#define MACH_TYPE_NEXIO 195 +#define MACH_TYPE_BITBOX 196 +#define MACH_TYPE_G200 197 +#define MACH_TYPE_GILL 198 +#define MACH_TYPE_PXA_MERCURY 199 +#define MACH_TYPE_CEIVA 200 +#define MACH_TYPE_FRET 201 +#define MACH_TYPE_EMAILPHONE 202 +#define MACH_TYPE_H3900 203 +#define MACH_TYPE_PXA1 204 +#define MACH_TYPE_KOAN369 205 +#define MACH_TYPE_COGENT 206 +#define MACH_TYPE_ESL_SIMPUTER 207 +#define MACH_TYPE_ESL_SIMPUTER_CLR 208 +#define MACH_TYPE_ESL_SIMPUTER_BW 209 +#define MACH_TYPE_HHP_CRADLE 210 +#define MACH_TYPE_HE500 211 +#define MACH_TYPE_INHANDELF2 212 +#define MACH_TYPE_INHANDFTIP 213 +#define MACH_TYPE_DNP1110 214 +#define MACH_TYPE_PNP1110 215 +#define MACH_TYPE_CSB226 216 +#define MACH_TYPE_ARNOLD 217 +#define MACH_TYPE_VOICEBLUE 218 +#define MACH_TYPE_JZ8028 219 +#define MACH_TYPE_H5400 220 +#define MACH_TYPE_FORTE 221 +#define MACH_TYPE_ACAM 222 +#define MACH_TYPE_ABOX 223 +#define MACH_TYPE_ATMEL 224 +#define MACH_TYPE_SITSANG 225 +#define MACH_TYPE_CPU1110LCDNET 226 +#define MACH_TYPE_MPL_VCMA9 227 +#define MACH_TYPE_OPUS_A1 228 +#define MACH_TYPE_DAYTONA 229 +#define MACH_TYPE_KILLBEAR 230 +#define MACH_TYPE_YOHO 231 +#define MACH_TYPE_JASPER 232 +#define MACH_TYPE_DSC25 233 +#define MACH_TYPE_OMAP_INNOVATOR 234 +#define MACH_TYPE_RAMSES 235 +#define MACH_TYPE_S28X 236 +#define MACH_TYPE_MPORT3 237 +#define MACH_TYPE_PXA_EAGLE250 238 +#define MACH_TYPE_PDB 239 +#define MACH_TYPE_BLUE_2G 240 +#define MACH_TYPE_BLUEARCH 241 +#define MACH_TYPE_IXDP2400 242 +#define MACH_TYPE_IXDP2800 243 +#define MACH_TYPE_EXPLORER 244 +#define MACH_TYPE_IXDP425 245 +#define MACH_TYPE_CHIMP 246 +#define MACH_TYPE_STORK_NEST 247 +#define MACH_TYPE_STORK_EGG 248 +#define MACH_TYPE_WISMO 249 +#define MACH_TYPE_EZLINX 250 +#define MACH_TYPE_AT91RM9200 251 +#define MACH_TYPE_ADTECH_ORION 252 +#define MACH_TYPE_NEPTUNE 253 +#define MACH_TYPE_HACKKIT 254 +#define MACH_TYPE_PXA_WINS30 255 +#define MACH_TYPE_LAVINNA 256 +#define MACH_TYPE_PXA_UENGINE 257 +#define MACH_TYPE_INNOKOM 258 +#define MACH_TYPE_BMS 259 +#define MACH_TYPE_IXCDP1100 260 +#define MACH_TYPE_PRPMC1100 261 +#define MACH_TYPE_AT91RM9200DK 262 +#define MACH_TYPE_ARMSTICK 263 +#define MACH_TYPE_ARMONIE 264 +#define MACH_TYPE_MPORT1 265 +#define MACH_TYPE_S3C5410 266 +#define MACH_TYPE_ZCP320A 267 +#define MACH_TYPE_I_BOX 268 +#define MACH_TYPE_STLC1502 269 +#define MACH_TYPE_SIREN 270 +#define MACH_TYPE_GREENLAKE 271 +#define MACH_TYPE_ARGUS 272 +#define MACH_TYPE_COMBADGE 273 +#define MACH_TYPE_ROKEPXA 274 +#define MACH_TYPE_CINTEGRATOR 275 +#define MACH_TYPE_GUIDEA07 276 +#define MACH_TYPE_TAT257 277 +#define MACH_TYPE_IGP2425 278 +#define MACH_TYPE_BLUEGRAMMA 279 +#define MACH_TYPE_IPOD 280 +#define MACH_TYPE_ADSBITSYX 281 +#define MACH_TYPE_TRIZEPS2 282 +#define MACH_TYPE_VIPER 283 +#define MACH_TYPE_ADSBITSYPLUS 284 +#define MACH_TYPE_ADSAGC 285 +#define MACH_TYPE_STP7312 286 +#define MACH_TYPE_NX_PHNX 287 +#define MACH_TYPE_WEP_EP250 288 +#define MACH_TYPE_INHANDELF3 289 +#define MACH_TYPE_ADI_COYOTE 290 +#define MACH_TYPE_IYONIX 291 +#define MACH_TYPE_DAMICAM_SA1110 292 +#define MACH_TYPE_MEG03 293 +#define MACH_TYPE_PXA_WHITECHAPEL 294 +#define MACH_TYPE_NWSC 295 +#define MACH_TYPE_NWLARM 296 +#define MACH_TYPE_IXP425_MGUARD 297 +#define MACH_TYPE_PXA_NETDCU4 298 +#define MACH_TYPE_IXDP2401 299 +#define MACH_TYPE_IXDP2801 300 +#define MACH_TYPE_ZODIAC 301 +#define MACH_TYPE_ARMMODUL 302 +#define MACH_TYPE_KETOP 303 +#define MACH_TYPE_AV7200 304 +#define MACH_TYPE_ARCH_TI925 305 +#define MACH_TYPE_ACQ200 306 +#define MACH_TYPE_PT_DAFIT 307 +#define MACH_TYPE_IHBA 308 +#define MACH_TYPE_QUINQUE 309 +#define MACH_TYPE_NIMBRAONE 310 +#define MACH_TYPE_NIMBRA29X 311 +#define MACH_TYPE_NIMBRA210 312 +#define MACH_TYPE_HHP_D95XX 313 +#define MACH_TYPE_LABARM 314 +#define MACH_TYPE_M825XX 315 +#define MACH_TYPE_M7100 316 +#define MACH_TYPE_NIPC2 317 +#define MACH_TYPE_FU7202 318 +#define MACH_TYPE_ADSAGX 319 +#define MACH_TYPE_PXA_POOH 320 +#define MACH_TYPE_BANDON 321 +#define MACH_TYPE_PCM7210 322 +#define MACH_TYPE_NMS9200 323 +#define MACH_TYPE_LOGODL 324 +#define MACH_TYPE_M7140 325 +#define MACH_TYPE_KOREBOT 326 +#define MACH_TYPE_IQ31244 327 +#define MACH_TYPE_KOAN393 328 +#define MACH_TYPE_INHANDFTIP3 329 +#define MACH_TYPE_GONZO 330 +#define MACH_TYPE_BAST 331 +#define MACH_TYPE_SCANPASS 332 +#define MACH_TYPE_EP7312_POOH 333 +#define MACH_TYPE_TA7S 334 +#define MACH_TYPE_TA7V 335 +#define MACH_TYPE_ICARUS 336 +#define MACH_TYPE_H1900 337 +#define MACH_TYPE_GEMINI 338 +#define MACH_TYPE_AXIM 339 +#define MACH_TYPE_AUDIOTRON 340 +#define MACH_TYPE_H2200 341 +#define MACH_TYPE_LOOX600 342 +#define MACH_TYPE_NIOP 343 +#define MACH_TYPE_DM310 344 +#define MACH_TYPE_SEEDPXA_C2 345 +#define MACH_TYPE_IXP4XX_MGUARD_PCI 346 +#define MACH_TYPE_H1940 347 +#define MACH_TYPE_SCORPIO 348 +#define MACH_TYPE_VIVA 349 +#define MACH_TYPE_PXA_XCARD 350 +#define MACH_TYPE_CSB335 351 +#define MACH_TYPE_IXRD425 352 +#define MACH_TYPE_IQ80315 353 +#define MACH_TYPE_NMP7312 354 +#define MACH_TYPE_CX861XX 355 +#define MACH_TYPE_ENP2611 356 +#define MACH_TYPE_XDA 357 +#define MACH_TYPE_CSIR_IMS 358 +#define MACH_TYPE_IXP421_DNAEETH 359 +#define MACH_TYPE_POCKETSERV9200 360 +#define MACH_TYPE_TOTO 361 +#define MACH_TYPE_S3C2440 362 +#define MACH_TYPE_KS8695P 363 +#define MACH_TYPE_SE4000 364 +#define MACH_TYPE_QUADRICEPS 365 +#define MACH_TYPE_BRONCO 366 +#define MACH_TYPE_ESL_WIRELESS_TAB 367 +#define MACH_TYPE_ESL_SOFCOMP 368 +#define MACH_TYPE_S5C7375 369 +#define MACH_TYPE_SPEARHEAD 370 +#define MACH_TYPE_PANTERA 371 +#define MACH_TYPE_PRAYOGLITE 372 +#define MACH_TYPE_GUMSTIX 373 +#define MACH_TYPE_RCUBE 374 +#define MACH_TYPE_REA_OLV 375 +#define MACH_TYPE_PXA_IPHONE 376 +#define MACH_TYPE_S3C3410 377 +#define MACH_TYPE_ESPD_4510B 378 +#define MACH_TYPE_MP1X 379 +#define MACH_TYPE_AT91RM9200TB 380 +#define MACH_TYPE_ADSVGX 381 +#define MACH_TYPE_OMAP_H2 382 +#define MACH_TYPE_PELEE 383 +#define MACH_TYPE_E740 384 +#define MACH_TYPE_IQ80331 385 +#define MACH_TYPE_VERSATILE_PB 387 +#define MACH_TYPE_KEV7A400 388 +#define MACH_TYPE_LPD7A400 389 +#define MACH_TYPE_LPD7A404 390 +#define MACH_TYPE_FUJITSU_CAMELOT 391 +#define MACH_TYPE_JANUS2M 392 +#define MACH_TYPE_EMBTF 393 +#define MACH_TYPE_HPM 394 +#define MACH_TYPE_SMDK2410TK 395 +#define MACH_TYPE_SMDK2410AJ 396 +#define MACH_TYPE_STREETRACER 397 +#define MACH_TYPE_EFRAME 398 +#define MACH_TYPE_CSB337 399 +#define MACH_TYPE_PXA_LARK 400 +#define MACH_TYPE_PNP2110 401 +#define MACH_TYPE_TCC72X 402 +#define MACH_TYPE_ALTAIR 403 +#define MACH_TYPE_KC3 404 +#define MACH_TYPE_SINTEFTD 405 +#define MACH_TYPE_MAINSTONE 406 +#define MACH_TYPE_ADAY4X 407 +#define MACH_TYPE_LITE300 408 +#define MACH_TYPE_S5C7376 409 +#define MACH_TYPE_MT02 410 +#define MACH_TYPE_MPORT3S 411 +#define MACH_TYPE_RA_ALPHA 412 +#define MACH_TYPE_XCEP 413 +#define MACH_TYPE_ARCOM_VULCAN 414 +#define MACH_TYPE_STARGATE 415 +#define MACH_TYPE_ARMADILLOJ 416 +#define MACH_TYPE_ELROY_JACK 417 +#define MACH_TYPE_BACKEND 418 +#define MACH_TYPE_S5LINBOX 419 +#define MACH_TYPE_NOMADIK 420 +#define MACH_TYPE_IA_CPU_9200 421 +#define MACH_TYPE_AT91_BJA1 422 +#define MACH_TYPE_CORGI 423 +#define MACH_TYPE_POODLE 424 +#define MACH_TYPE_TEN 425 +#define MACH_TYPE_ROVERP5P 426 +#define MACH_TYPE_SC2700 427 +#define MACH_TYPE_EX_EAGLE 428 +#define MACH_TYPE_NX_PXA12 429 +#define MACH_TYPE_NX_PXA5 430 +#define MACH_TYPE_BLACKBOARD2 431 +#define MACH_TYPE_I819 432 +#define MACH_TYPE_IXMB995E 433 +#define MACH_TYPE_SKYRIDER 434 +#define MACH_TYPE_SKYHAWK 435 +#define MACH_TYPE_ENTERPRISE 436 +#define MACH_TYPE_DEP2410 437 +#define MACH_TYPE_ARMCORE 438 +#define MACH_TYPE_HOBBIT 439 +#define MACH_TYPE_H7210 440 +#define MACH_TYPE_PXA_NETDCU5 441 +#define MACH_TYPE_ACC 442 +#define MACH_TYPE_ESL_SARVA 443 +#define MACH_TYPE_XM250 444 +#define MACH_TYPE_T6TC1XB 445 +#define MACH_TYPE_ESS710 446 +#define MACH_TYPE_MX31ADS 447 +#define MACH_TYPE_HIMALAYA 448 +#define MACH_TYPE_BOLFENK 449 +#define MACH_TYPE_AT91RM9200KR 450 +#define MACH_TYPE_EDB9312 451 +#define MACH_TYPE_OMAP_GENERIC 452 +#define MACH_TYPE_AXIMX3 453 +#define MACH_TYPE_EB67XDIP 454 +#define MACH_TYPE_WEBTXS 455 +#define MACH_TYPE_HAWK 456 +#define MACH_TYPE_CCAT91SBC001 457 +#define MACH_TYPE_EXPRESSO 458 +#define MACH_TYPE_H4000 459 +#define MACH_TYPE_DINO 460 +#define MACH_TYPE_ML675K 461 +#define MACH_TYPE_EDB9301 462 +#define MACH_TYPE_EDB9315 463 +#define MACH_TYPE_RECIVA_TT 464 +#define MACH_TYPE_CSTCB01 465 +#define MACH_TYPE_CSTCB1 466 +#define MACH_TYPE_SHADWELL 467 +#define MACH_TYPE_GOEPEL263 468 +#define MACH_TYPE_ACQ100 469 +#define MACH_TYPE_MX1FS2 470 +#define MACH_TYPE_HIPTOP_G1 471 +#define MACH_TYPE_SPARKY 472 +#define MACH_TYPE_NS9750 473 +#define MACH_TYPE_PHOENIX 474 +#define MACH_TYPE_VR1000 475 +#define MACH_TYPE_DEISTERPXA 476 +#define MACH_TYPE_BCM1160 477 +#define MACH_TYPE_PCM022 478 +#define MACH_TYPE_ADSGCX 479 +#define MACH_TYPE_DREADNAUGHT 480 +#define MACH_TYPE_DM320 481 +#define MACH_TYPE_MARKOV 482 +#define MACH_TYPE_COS7A400 483 +#define MACH_TYPE_MILANO 484 +#define MACH_TYPE_UE9328 485 +#define MACH_TYPE_UEX255 486 +#define MACH_TYPE_UE2410 487 +#define MACH_TYPE_A620 488 +#define MACH_TYPE_OCELOT 489 +#define MACH_TYPE_CHEETAH 490 +#define MACH_TYPE_OMAP_PERSEUS2 491 +#define MACH_TYPE_ZVUE 492 +#define MACH_TYPE_ROVERP1 493 +#define MACH_TYPE_ASIDIAL2 494 +#define MACH_TYPE_S3C24A0 495 +#define MACH_TYPE_E800 496 +#define MACH_TYPE_E750 497 +#define MACH_TYPE_S3C5500 498 +#define MACH_TYPE_SMDK5500 499 +#define MACH_TYPE_SIGNALSYNC 500 +#define MACH_TYPE_NBC 501 +#define MACH_TYPE_KODIAK 502 +#define MACH_TYPE_NETBOOKPRO 503 +#define MACH_TYPE_HW90200 504 +#define MACH_TYPE_CONDOR 505 +#define MACH_TYPE_CUP 506 +#define MACH_TYPE_KITE 507 +#define MACH_TYPE_SCB9328 508 +#define MACH_TYPE_OMAP_H3 509 +#define MACH_TYPE_OMAP_H4 510 +#define MACH_TYPE_N10 511 +#define MACH_TYPE_MONTAJADE 512 +#define MACH_TYPE_SG560 513 +#define MACH_TYPE_DP1000 514 +#define MACH_TYPE_OMAP_OSK 515 +#define MACH_TYPE_RG100V3 516 +#define MACH_TYPE_MX2ADS 517 +#define MACH_TYPE_PXA_KILO 518 +#define MACH_TYPE_IXP4XX_EAGLE 519 +#define MACH_TYPE_TOSA 520 +#define MACH_TYPE_MB2520F 521 +#define MACH_TYPE_EMC1000 522 +#define MACH_TYPE_TIDSC25 523 +#define MACH_TYPE_AKCPMXL 524 +#define MACH_TYPE_AV3XX 525 +#define MACH_TYPE_AVILA 526 +#define MACH_TYPE_PXA_MPM10 527 +#define MACH_TYPE_PXA_KYANITE 528 +#define MACH_TYPE_SGOLD 529 +#define MACH_TYPE_OSCAR 530 +#define MACH_TYPE_EPXA4USB2 531 +#define MACH_TYPE_XSENGINE 532 +#define MACH_TYPE_IP600 533 +#define MACH_TYPE_MCAN2 534 +#define MACH_TYPE_DDI_BLUERIDGE 535 +#define MACH_TYPE_SKYMINDER 536 +#define MACH_TYPE_LPD79520 537 +#define MACH_TYPE_EDB9302 538 +#define MACH_TYPE_HW90340 539 +#define MACH_TYPE_CIP_BOX 540 +#define MACH_TYPE_IVPN 541 +#define MACH_TYPE_RSOC2 542 +#define MACH_TYPE_HUSKY 543 +#define MACH_TYPE_BOXER 544 +#define MACH_TYPE_SHEPHERD 545 +#define MACH_TYPE_AML42800AA 546 +#define MACH_TYPE_LPC2294 548 +#define MACH_TYPE_SWITCHGRASS 549 +#define MACH_TYPE_ENS_CMU 550 +#define MACH_TYPE_MM6_SDB 551 +#define MACH_TYPE_SATURN 552 +#define MACH_TYPE_I30030EVB 553 +#define MACH_TYPE_MXC27530EVB 554 +#define MACH_TYPE_SMDK2800 555 +#define MACH_TYPE_MTWILSON 556 +#define MACH_TYPE_ZITI 557 +#define MACH_TYPE_GRANDFATHER 558 +#define MACH_TYPE_TENGINE 559 +#define MACH_TYPE_S3C2460 560 +#define MACH_TYPE_PDM 561 +#define MACH_TYPE_H4700 562 +#define MACH_TYPE_H6300 563 +#define MACH_TYPE_RZ1700 564 +#define MACH_TYPE_A716 565 +#define MACH_TYPE_ESTK2440A 566 +#define MACH_TYPE_ATWIXP425 567 +#define MACH_TYPE_CSB336 568 +#define MACH_TYPE_RIRM2 569 +#define MACH_TYPE_CX23518 570 +#define MACH_TYPE_CX2351X 571 +#define MACH_TYPE_COMPUTIME 572 +#define MACH_TYPE_IZARUS 573 +#define MACH_TYPE_RTS 574 +#define MACH_TYPE_SE5100 575 +#define MACH_TYPE_S3C2510 576 +#define MACH_TYPE_CSB437TL 577 +#define MACH_TYPE_SLAUSON 578 +#define MACH_TYPE_PEARLRIVER 579 +#define MACH_TYPE_TDC_P210 580 +#define MACH_TYPE_SG580 581 +#define MACH_TYPE_WRSBCARM7 582 +#define MACH_TYPE_IPD 583 +#define MACH_TYPE_PXA_DNP2110 584 +#define MACH_TYPE_XAENIAX 585 +#define MACH_TYPE_SOMN4250 586 +#define MACH_TYPE_PLEB2 587 +#define MACH_TYPE_CORNWALLIS 588 +#define MACH_TYPE_GURNEY_DRV 589 +#define MACH_TYPE_CHAFFEE 590 +#define MACH_TYPE_RMS101 591 +#define MACH_TYPE_RX3715 592 +#define MACH_TYPE_SWIFT 593 +#define MACH_TYPE_ROVERP7 594 +#define MACH_TYPE_PR818S 595 +#define MACH_TYPE_TRXPRO 596 +#define MACH_TYPE_NSLU2 597 +#define MACH_TYPE_E400 598 +#define MACH_TYPE_TRAB 599 +#define MACH_TYPE_CMC_PU2 600 +#define MACH_TYPE_FULCRUM 601 +#define MACH_TYPE_NETGATE42X 602 +#define MACH_TYPE_STR710 603 +#define MACH_TYPE_IXDPG425 604 +#define MACH_TYPE_TOMTOMGO 605 +#define MACH_TYPE_VERSATILE_AB 606 +#define MACH_TYPE_EDB9307 607 +#define MACH_TYPE_SG565 608 +#define MACH_TYPE_LPD79524 609 +#define MACH_TYPE_LPD79525 610 +#define MACH_TYPE_RMS100 611 +#define MACH_TYPE_KB9200 612 +#define MACH_TYPE_SX1 613 +#define MACH_TYPE_HMS39C7092 614 +#define MACH_TYPE_ARMADILLO 615 +#define MACH_TYPE_IPCU 616 +#define MACH_TYPE_LOOX720 617 +#define MACH_TYPE_IXDP465 618 +#define MACH_TYPE_IXDP2351 619 +#define MACH_TYPE_ADSVIX 620 +#define MACH_TYPE_DM270 621 +#define MACH_TYPE_SOCLTPLUS 622 +#define MACH_TYPE_ECIA 623 +#define MACH_TYPE_CM4008 624 +#define MACH_TYPE_P2001 625 +#define MACH_TYPE_TWISTER 626 +#define MACH_TYPE_MUDSHARK 627 +#define MACH_TYPE_HB2 628 +#define MACH_TYPE_IQ80332 629 +#define MACH_TYPE_SENDT 630 +#define MACH_TYPE_MX2JAZZ 631 +#define MACH_TYPE_MULTIIO 632 +#define MACH_TYPE_HRDISPLAY 633 +#define MACH_TYPE_MXC27530ADS 634 +#define MACH_TYPE_TRIZEPS3 635 +#define MACH_TYPE_ZEFEERDZA 636 +#define MACH_TYPE_ZEFEERDZB 637 +#define MACH_TYPE_ZEFEERDZG 638 +#define MACH_TYPE_ZEFEERDZN 639 +#define MACH_TYPE_ZEFEERDZQ 640 +#define MACH_TYPE_GTWX5715 641 +#define MACH_TYPE_ASTRO_JACK 643 +#define MACH_TYPE_TIP03 644 +#define MACH_TYPE_A9200EC 645 +#define MACH_TYPE_PNX0105 646 +#define MACH_TYPE_ADCPOECPU 647 +#define MACH_TYPE_CSB637 648 +#define MACH_TYPE_MB9200 650 +#define MACH_TYPE_KULUN 651 +#define MACH_TYPE_SNAPPER 652 +#define MACH_TYPE_OPTIMA 653 +#define MACH_TYPE_DLHSBC 654 +#define MACH_TYPE_X30 655 +#define MACH_TYPE_N30 656 +#define MACH_TYPE_MANGA_KS8695 657 +#define MACH_TYPE_AJAX 658 +#define MACH_TYPE_NEC_MP900 659 +#define MACH_TYPE_VVTK1000 661 +#define MACH_TYPE_KAFA 662 +#define MACH_TYPE_VVTK3000 663 +#define MACH_TYPE_PIMX1 664 +#define MACH_TYPE_OLLIE 665 +#define MACH_TYPE_SKYMAX 666 +#define MACH_TYPE_JAZZ 667 +#define MACH_TYPE_TEL_T3 668 +#define MACH_TYPE_AISINO_FCR255 669 +#define MACH_TYPE_BTWEB 670 +#define MACH_TYPE_DBG_LH79520 671 +#define MACH_TYPE_CM41XX 672 +#define MACH_TYPE_TS72XX 673 +#define MACH_TYPE_NGGPXA 674 +#define MACH_TYPE_CSB535 675 +#define MACH_TYPE_CSB536 676 +#define MACH_TYPE_PXA_TRAKPOD 677 +#define MACH_TYPE_PRAXIS 678 +#define MACH_TYPE_LH75411 679 +#define MACH_TYPE_OTOM 680 +#define MACH_TYPE_NEXCODER_2440 681 +#define MACH_TYPE_LOOX410 682 +#define MACH_TYPE_WESTLAKE 683 +#define MACH_TYPE_NSB 684 +#define MACH_TYPE_ESL_SARVA_STN 685 +#define MACH_TYPE_ESL_SARVA_TFT 686 +#define MACH_TYPE_ESL_SARVA_IAD 687 +#define MACH_TYPE_ESL_SARVA_ACC 688 +#define MACH_TYPE_TYPHOON 689 +#define MACH_TYPE_CNAV 690 +#define MACH_TYPE_A730 691 +#define MACH_TYPE_NETSTAR 692 +#define MACH_TYPE_PHASEFALE_SUPERCON 693 +#define MACH_TYPE_SHIVA1100 694 +#define MACH_TYPE_ETEXSC 695 +#define MACH_TYPE_IXDPG465 696 +#define MACH_TYPE_A9M2410 697 +#define MACH_TYPE_A9M2440 698 +#define MACH_TYPE_A9M9750 699 +#define MACH_TYPE_A9M9360 700 +#define MACH_TYPE_UNC90 701 +#define MACH_TYPE_ECO920 702 +#define MACH_TYPE_SATVIEW 703 +#define MACH_TYPE_ROADRUNNER 704 +#define MACH_TYPE_AT91RM9200EK 705 +#define MACH_TYPE_GP32 706 +#define MACH_TYPE_GEM 707 +#define MACH_TYPE_I858 708 +#define MACH_TYPE_HX2750 709 +#define MACH_TYPE_MXC91131EVB 710 +#define MACH_TYPE_P700 711 +#define MACH_TYPE_CPE 712 +#define MACH_TYPE_SPITZ 713 +#define MACH_TYPE_NIMBRA340 714 +#define MACH_TYPE_LPC22XX 715 +#define MACH_TYPE_COMET3 716 +#define MACH_TYPE_COMET4 717 +#define MACH_TYPE_CSB625 718 +#define MACH_TYPE_FORTUNET2 719 +#define MACH_TYPE_S5H2200 720 +#define MACH_TYPE_OPTORM920 721 +#define MACH_TYPE_ADSBITSYXB 722 +#define MACH_TYPE_ADSSPHERE 723 +#define MACH_TYPE_ADSPORTAL 724 +#define MACH_TYPE_LN2410SBC 725 +#define MACH_TYPE_CB3RUFC 726 +#define MACH_TYPE_MP2USB 727 +#define MACH_TYPE_NTNP425C 728 +#define MACH_TYPE_COLIBRI 729 +#define MACH_TYPE_PCM7220 730 +#define MACH_TYPE_GATEWAY7001 731 +#define MACH_TYPE_PCM027 732 +#define MACH_TYPE_CMPXA 733 +#define MACH_TYPE_ANUBIS 734 +#define MACH_TYPE_ITE8152 735 +#define MACH_TYPE_LPC3XXX 736 +#define MACH_TYPE_PUPPETEER 737 +#define MACH_TYPE_E570 739 +#define MACH_TYPE_X50 740 +#define MACH_TYPE_RECON 741 +#define MACH_TYPE_XBOARDGP8 742 +#define MACH_TYPE_FPIC2 743 +#define MACH_TYPE_AKITA 744 +#define MACH_TYPE_A81 745 +#define MACH_TYPE_SVM_SC25X 746 +#define MACH_TYPE_VADATECH020 747 +#define MACH_TYPE_TLI 748 +#define MACH_TYPE_EDB9315LC 749 +#define MACH_TYPE_PASSEC 750 +#define MACH_TYPE_DS_TIGER 751 +#define MACH_TYPE_E310 752 +#define MACH_TYPE_E330 753 +#define MACH_TYPE_RT3000 754 +#define MACH_TYPE_NOKIA770 755 +#define MACH_TYPE_PNX0106 756 +#define MACH_TYPE_HX21XX 757 +#define MACH_TYPE_FARADAY 758 +#define MACH_TYPE_SBC9312 759 +#define MACH_TYPE_BATMAN 760 +#define MACH_TYPE_JPD201 761 +#define MACH_TYPE_MIPSA 762 +#define MACH_TYPE_KACOM 763 +#define MACH_TYPE_SWARCOCPU 764 +#define MACH_TYPE_SWARCODSL 765 +#define MACH_TYPE_BLUEANGEL 766 +#define MACH_TYPE_HAIRYGRAMA 767 +#define MACH_TYPE_BANFF 768 +#define MACH_TYPE_CARMEVA 769 +#define MACH_TYPE_SAM255 770 +#define MACH_TYPE_PPM10 771 +#define MACH_TYPE_EDB9315A 772 +#define MACH_TYPE_SUNSET 773 +#define MACH_TYPE_STARGATE2 774 +#define MACH_TYPE_INTELMOTE2 775 +#define MACH_TYPE_TRIZEPS4 776 +#define MACH_TYPE_MAINSTONE2 777 +#define MACH_TYPE_EZ_IXP42X 778 +#define MACH_TYPE_TAPWAVE_ZODIAC 779 +#define MACH_TYPE_UNIVERSALMETER 780 +#define MACH_TYPE_HICOARM9 781 +#define MACH_TYPE_PNX4008 782 +#define MACH_TYPE_KWS6000 783 +#define MACH_TYPE_PORTUX920T 784 +#define MACH_TYPE_EZ_X5 785 +#define MACH_TYPE_OMAP_RUDOLPH 786 +#define MACH_TYPE_CPUAT91 787 +#define MACH_TYPE_REA9200 788 +#define MACH_TYPE_ACTS_PUNE_SA1110 789 +#define MACH_TYPE_IXP425 790 +#define MACH_TYPE_I30030ADS 791 +#define MACH_TYPE_PERCH 792 +#define MACH_TYPE_EIS05R1 793 +#define MACH_TYPE_PEPPERPAD 794 +#define MACH_TYPE_SB3010 795 +#define MACH_TYPE_RM9200 796 +#define MACH_TYPE_DMA03 797 +#define MACH_TYPE_ROAD_S101 798 +#define MACH_TYPE_IQ81340SC 799 +#define MACH_TYPE_IQ_NEXTGEN_B 800 +#define MACH_TYPE_IQ81340MC 801 +#define MACH_TYPE_IQ_NEXTGEN_D 802 +#define MACH_TYPE_IQ_NEXTGEN_E 803 +#define MACH_TYPE_MALLOW_AT91 804 +#define MACH_TYPE_CYBERTRACKER_I 805 +#define MACH_TYPE_GESBC931X 806 +#define MACH_TYPE_CENTIPAD 807 +#define MACH_TYPE_ARMSOC 808 +#define MACH_TYPE_SE4200 809 +#define MACH_TYPE_EMS197A 810 +#define MACH_TYPE_MICRO9 811 +#define MACH_TYPE_MICRO9L 812 +#define MACH_TYPE_UC5471DSP 813 +#define MACH_TYPE_SJ5471ENG 814 +#define MACH_TYPE_CMPXA26X 815 +#define MACH_TYPE_NC 816 +#define MACH_TYPE_OMAP_PALMTE 817 +#define MACH_TYPE_AJAX52X 818 +#define MACH_TYPE_SIRIUSTAR 819 +#define MACH_TYPE_IODATA_HDLG 820 +#define MACH_TYPE_AT91RM9200UTL 821 +#define MACH_TYPE_BIOSAFE 822 +#define MACH_TYPE_MP1000 823 +#define MACH_TYPE_PARSY 824 +#define MACH_TYPE_CCXP 825 +#define MACH_TYPE_OMAP_GSAMPLE 826 +#define MACH_TYPE_REALVIEW_EB 827 +#define MACH_TYPE_SAMOA 828 +#define MACH_TYPE_PALMT3 829 +#define MACH_TYPE_I878 830 +#define MACH_TYPE_BORZOI 831 +#define MACH_TYPE_GECKO 832 +#define MACH_TYPE_DS101 833 +#define MACH_TYPE_OMAP_PALMTT2 834 +#define MACH_TYPE_PALMLD 835 +#define MACH_TYPE_CC9C 836 +#define MACH_TYPE_SBC1670 837 +#define MACH_TYPE_IXDP28X5 838 +#define MACH_TYPE_OMAP_PALMTT 839 +#define MACH_TYPE_ML696K 840 +#define MACH_TYPE_ARCOM_ZEUS 841 +#define MACH_TYPE_OSIRIS 842 +#define MACH_TYPE_MAESTRO 843 +#define MACH_TYPE_PALMTE2 844 +#define MACH_TYPE_IXBBM 845 +#define MACH_TYPE_MX27ADS 846 +#define MACH_TYPE_AX8004 847 +#define MACH_TYPE_AT91SAM9261EK 848 +#define MACH_TYPE_LOFT 849 +#define MACH_TYPE_MAGPIE 850 +#define MACH_TYPE_MX21ADS 851 +#define MACH_TYPE_MB87M3400 852 +#define MACH_TYPE_MGUARD_DELTA 853 +#define MACH_TYPE_DAVINCI_DVDP 854 +#define MACH_TYPE_HTCUNIVERSAL 855 +#define MACH_TYPE_TPAD 856 +#define MACH_TYPE_ROVERP3 857 +#define MACH_TYPE_JORNADA928 858 +#define MACH_TYPE_MV88FXX81 859 +#define MACH_TYPE_STMP36XX 860 +#define MACH_TYPE_SXNI79524 861 +#define MACH_TYPE_AMS_DELTA 862 +#define MACH_TYPE_URANIUM 863 +#define MACH_TYPE_UCON 864 +#define MACH_TYPE_NAS100D 865 +#define MACH_TYPE_L083_1000 866 +#define MACH_TYPE_EZX 867 +#define MACH_TYPE_PNX5220 868 +#define MACH_TYPE_BUTTE 869 +#define MACH_TYPE_SRM2 870 +#define MACH_TYPE_DSBR 871 +#define MACH_TYPE_CRYSTALBALL 872 +#define MACH_TYPE_TINYPXA27X 873 +#define MACH_TYPE_HERBIE 874 +#define MACH_TYPE_MAGICIAN 875 +#define MACH_TYPE_CM4002 876 +#define MACH_TYPE_B4 877 +#define MACH_TYPE_MAUI 878 +#define MACH_TYPE_CYBERTRACKER_G 879 +#define MACH_TYPE_NXDKN 880 +#define MACH_TYPE_MIO8390 881 +#define MACH_TYPE_OMI_BOARD 882 +#define MACH_TYPE_MX21CIV 883 +#define MACH_TYPE_MAHI_CDAC 884 +#define MACH_TYPE_PALMTX 885 +#define MACH_TYPE_S3C2413 887 +#define MACH_TYPE_SAMSYS_EP0 888 +#define MACH_TYPE_WG302V1 889 +#define MACH_TYPE_WG302V2 890 +#define MACH_TYPE_EB42X 891 +#define MACH_TYPE_IQ331ES 892 +#define MACH_TYPE_COSYDSP 893 +#define MACH_TYPE_UPLAT7D 894 +#define MACH_TYPE_PTDAVINCI 895 +#define MACH_TYPE_MBUS 896 +#define MACH_TYPE_NADIA2VB 897 +#define MACH_TYPE_R1000 898 +#define MACH_TYPE_HW90250 899 +#define MACH_TYPE_OMAP_2430SDP 900 +#define MACH_TYPE_DAVINCI_EVM 901 +#define MACH_TYPE_OMAP_TORNADO 902 +#define MACH_TYPE_OLOCREEK 903 +#define MACH_TYPE_PALMZ72 904 +#define MACH_TYPE_NXDB500 905 +#define MACH_TYPE_APF9328 906 +#define MACH_TYPE_OMAP_WIPOQ 907 +#define MACH_TYPE_OMAP_TWIP 908 +#define MACH_TYPE_TREO650 909 +#define MACH_TYPE_ACUMEN 910 +#define MACH_TYPE_XP100 911 +#define MACH_TYPE_FS2410 912 +#define MACH_TYPE_PXA270_CERF 913 +#define MACH_TYPE_SQ2FTLPALM 914 +#define MACH_TYPE_BSEMSERVER 915 +#define MACH_TYPE_NETCLIENT 916 +#define MACH_TYPE_PALMT5 917 +#define MACH_TYPE_PALMTC 918 +#define MACH_TYPE_OMAP_APOLLON 919 +#define MACH_TYPE_MXC30030EVB 920 +#define MACH_TYPE_REA_2D 921 +#define MACH_TYPE_TI3E524 922 +#define MACH_TYPE_ATEB9200 923 +#define MACH_TYPE_AUCKLAND 924 +#define MACH_TYPE_AK3320M 925 +#define MACH_TYPE_DURAMAX 926 +#define MACH_TYPE_N35 927 +#define MACH_TYPE_PRONGHORN 928 +#define MACH_TYPE_FUNDY 929 +#define MACH_TYPE_LOGICPD_PXA270 930 +#define MACH_TYPE_CPU777 931 +#define MACH_TYPE_SIMICON9201 932 +#define MACH_TYPE_LEAP2_HPM 933 +#define MACH_TYPE_CM922TXA10 934 +#define MACH_TYPE_PXA 935 +#define MACH_TYPE_SANDGATE2 936 +#define MACH_TYPE_SANDGATE2G 937 +#define MACH_TYPE_SANDGATE2P 938 +#define MACH_TYPE_FRED_JACK 939 +#define MACH_TYPE_TTG_COLOR1 940 +#define MACH_TYPE_NXEB500HMI 941 +#define MACH_TYPE_NETDCU8 942 +#define MACH_TYPE_NG_FVX538 944 +#define MACH_TYPE_NG_FVS338 945 +#define MACH_TYPE_PNX4103 946 +#define MACH_TYPE_HESDB 947 +#define MACH_TYPE_XSILO 948 +#define MACH_TYPE_ESPRESSO 949 +#define MACH_TYPE_EMLC 950 +#define MACH_TYPE_SISTERON 951 +#define MACH_TYPE_RX1950 952 +#define MACH_TYPE_TSC_VENUS 953 +#define MACH_TYPE_DS101J 954 +#define MACH_TYPE_MXC30030ADS 955 +#define MACH_TYPE_FUJITSU_WIMAXSOC 956 +#define MACH_TYPE_DUALPCMODEM 957 +#define MACH_TYPE_GESBC9312 958 +#define MACH_TYPE_HTCAPACHE 959 +#define MACH_TYPE_IXDP435 960 +#define MACH_TYPE_CATPROVT100 961 +#define MACH_TYPE_PICOTUX1XX 962 +#define MACH_TYPE_PICOTUX2XX 963 +#define MACH_TYPE_DSMG600 964 +#define MACH_TYPE_EMPC2 965 +#define MACH_TYPE_VENTURA 966 +#define MACH_TYPE_PHIDGET_SBC 967 +#define MACH_TYPE_IJ3K 968 +#define MACH_TYPE_PISGAH 969 +#define MACH_TYPE_OMAP_FSAMPLE 970 +#define MACH_TYPE_SG720 971 +#define MACH_TYPE_REDFOX 972 +#define MACH_TYPE_MYSH_EP9315_1 973 +#define MACH_TYPE_TPF106 974 +#define MACH_TYPE_AT91RM9200KG 975 +#define MACH_TYPE_SLEDB 976 +#define MACH_TYPE_ONTRACK 977 +#define MACH_TYPE_PM1200 978 +#define MACH_TYPE_ESS24XXX 979 +#define MACH_TYPE_COREMP7 980 +#define MACH_TYPE_NEXCODER_6446 981 +#define MACH_TYPE_STVC8380 982 +#define MACH_TYPE_TEKLYNX 983 +#define MACH_TYPE_CARBONADO 984 +#define MACH_TYPE_SYSMOS_MP730 985 +#define MACH_TYPE_SNAPPER_CL15 986 +#define MACH_TYPE_PGIGIM 987 +#define MACH_TYPE_PTX9160P2 988 +#define MACH_TYPE_DCORE1 989 +#define MACH_TYPE_VICTORPXA 990 +#define MACH_TYPE_MX2DTB 991 +#define MACH_TYPE_PXA_IREX_ER0100 992 +#define MACH_TYPE_OMAP_PALMZ71 993 +#define MACH_TYPE_BARTEC_DEG 994 +#define MACH_TYPE_HW50251 995 +#define MACH_TYPE_IBOX 996 +#define MACH_TYPE_ATLASLH7A404 997 +#define MACH_TYPE_PT2026 998 +#define MACH_TYPE_HTCALPINE 999 +#define MACH_TYPE_BARTEC_VTU 1000 +#define MACH_TYPE_VCOREII 1001 +#define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_HTCBEETLES 1003 +#define MACH_TYPE_S3C6400 1004 +#define MACH_TYPE_S3C2443 1005 +#define MACH_TYPE_OMAP_LDK 1006 +#define MACH_TYPE_SMDK2460 1007 +#define MACH_TYPE_SMDK2440 1008 +#define MACH_TYPE_SMDK2412 1009 +#define MACH_TYPE_WEBBOX 1010 +#define MACH_TYPE_CWWNDP 1011 +#define MACH_TYPE_DRAGON 1012 +#define MACH_TYPE_OPENDO_CPU_BOARD 1013 +#define MACH_TYPE_CCM2200 1014 +#define MACH_TYPE_ETWARM 1015 +#define MACH_TYPE_M93030 1016 +#define MACH_TYPE_CC7U 1017 +#define MACH_TYPE_MTT_RANGER 1018 +#define MACH_TYPE_NEXUS 1019 +#define MACH_TYPE_DESMAN 1020 +#define MACH_TYPE_BKDE303 1021 +#define MACH_TYPE_SMDK2413 1022 +#define MACH_TYPE_AML_M7200 1023 +#define MACH_TYPE_AML_M5900 1024 +#define MACH_TYPE_SG640 1025 +#define MACH_TYPE_EDG79524 1026 +#define MACH_TYPE_AI2410 1027 +#define MACH_TYPE_IXP465 1028 +#define MACH_TYPE_BALLOON3 1029 +#define MACH_TYPE_HEINS 1030 +#define MACH_TYPE_MPLUSEVA 1031 +#define MACH_TYPE_RT042 1032 +#define MACH_TYPE_CWIEM 1033 +#define MACH_TYPE_CM_X270 1034 +#define MACH_TYPE_CM_X255 1035 +#define MACH_TYPE_ESH_AT91 1036 +#define MACH_TYPE_SANDGATE3 1037 +#define MACH_TYPE_PRIMO 1038 +#define MACH_TYPE_GEMSTONE 1039 +#define MACH_TYPE_PRONGHORNMETRO 1040 +#define MACH_TYPE_SIDEWINDER 1041 +#define MACH_TYPE_PICOMOD1 1042 +#define MACH_TYPE_SG590 1043 +#define MACH_TYPE_AKAI9307 1044 +#define MACH_TYPE_FONTAINE 1045 +#define MACH_TYPE_WOMBAT 1046 +#define MACH_TYPE_ACQ300 1047 +#define MACH_TYPE_MOD_270 1048 +#define MACH_TYPE_VC0820 1049 +#define MACH_TYPE_ANI_AIM 1050 +#define MACH_TYPE_JELLYFISH 1051 +#define MACH_TYPE_AMANITA 1052 +#define MACH_TYPE_VLINK 1053 +#define MACH_TYPE_DEXFLEX 1054 +#define MACH_TYPE_EIGEN_TTQ 1055 +#define MACH_TYPE_ARCOM_TITAN 1056 +#define MACH_TYPE_TABLA 1057 +#define MACH_TYPE_MDIRAC3 1058 +#define MACH_TYPE_MRHFBP2 1059 +#define MACH_TYPE_AT91RM9200RB 1060 +#define MACH_TYPE_ANI_APM 1061 +#define MACH_TYPE_ELLA1 1062 +#define MACH_TYPE_INHAND_PXA27X 1063 +#define MACH_TYPE_INHAND_PXA25X 1064 +#define MACH_TYPE_EMPOS_XM 1065 +#define MACH_TYPE_EMPOS 1066 +#define MACH_TYPE_EMPOS_TINY 1067 +#define MACH_TYPE_EMPOS_SM 1068 +#define MACH_TYPE_EGRET 1069 +#define MACH_TYPE_OSTRICH 1070 +#define MACH_TYPE_N50 1071 +#define MACH_TYPE_ECBAT91 1072 +#define MACH_TYPE_STAREAST 1073 +#define MACH_TYPE_DSPG_DW 1074 +#define MACH_TYPE_ONEARM 1075 +#define MACH_TYPE_MRG110_6 1076 +#define MACH_TYPE_WRT300NV2 1077 +#define MACH_TYPE_XM_BULVERDE 1078 +#define MACH_TYPE_MSM6100 1079 +#define MACH_TYPE_ETI_B1 1080 +#define MACH_TYPE_ZILOG_ZA9L 1081 +#define MACH_TYPE_BIT2440 1082 +#define MACH_TYPE_NBI 1083 +#define MACH_TYPE_SMDK2443 1084 +#define MACH_TYPE_VDAVINCI 1085 +#define MACH_TYPE_ATC6 1086 +#define MACH_TYPE_MULTMDW 1087 +#define MACH_TYPE_MBA2440 1088 +#define MACH_TYPE_ECSD 1089 +#define MACH_TYPE_PALMZ31 1090 +#define MACH_TYPE_FSG 1091 +#define MACH_TYPE_RAZOR101 1092 +#define MACH_TYPE_OPERA_TDM 1093 +#define MACH_TYPE_COMCERTO 1094 +#define MACH_TYPE_TB0319 1095 +#define MACH_TYPE_KWS8000 1096 +#define MACH_TYPE_B2 1097 +#define MACH_TYPE_LCL54 1098 +#define MACH_TYPE_AT91SAM9260EK 1099 +#define MACH_TYPE_GLANTANK 1100 +#define MACH_TYPE_N2100 1101 +#define MACH_TYPE_N4100 1102 +#define MACH_TYPE_VERTICAL_RSC4 1103 +#define MACH_TYPE_SG8100 1104 +#define MACH_TYPE_IM42XX 1105 +#define MACH_TYPE_FTXX 1106 +#define MACH_TYPE_LWFUSION 1107 +#define MACH_TYPE_QT2410 1108 +#define MACH_TYPE_KIXRP435 1109 +#define MACH_TYPE_CCW9C 1110 +#define MACH_TYPE_DABHS 1111 +#define MACH_TYPE_GZMX 1112 +#define MACH_TYPE_IPNW100AP 1113 +#define MACH_TYPE_CC9P9360DEV 1114 +#define MACH_TYPE_CC9P9750DEV 1115 +#define MACH_TYPE_CC9P9360VAL 1116 +#define MACH_TYPE_CC9P9750VAL 1117 +#define MACH_TYPE_NX70V 1118 +#define MACH_TYPE_AT91RM9200DF 1119 +#define MACH_TYPE_SE_PILOT2 1120 +#define MACH_TYPE_MTCN_T800 1121 +#define MACH_TYPE_VCMX212 1122 +#define MACH_TYPE_LYNX 1123 +#define MACH_TYPE_AT91SAM9260ID 1124 +#define MACH_TYPE_HW86052 1125 +#define MACH_TYPE_PILZ_PMI3 1126 +#define MACH_TYPE_EDB9302A 1127 +#define MACH_TYPE_EDB9307A 1128 +#define MACH_TYPE_CT_DFS 1129 +#define MACH_TYPE_PILZ_PMI4 1130 +#define MACH_TYPE_XCEEDNP_IXP 1131 +#define MACH_TYPE_SMDK2442B 1132 +#define MACH_TYPE_XNODE 1133 +#define MACH_TYPE_AIDX270 1134 +#define MACH_TYPE_REMA 1135 +#define MACH_TYPE_BPS1000 1136 +#define MACH_TYPE_HW90350 1137 +#define MACH_TYPE_OMAP_3430SDP 1138 +#define MACH_TYPE_BLUETOUCH 1139 +#define MACH_TYPE_VSTMS 1140 +#define MACH_TYPE_XSBASE270 1141 +#define MACH_TYPE_AT91SAM9260EK_CN 1142 +#define MACH_TYPE_ADSTURBOXB 1143 +#define MACH_TYPE_OTI4110 1144 +#define MACH_TYPE_HME_PXA 1145 +#define MACH_TYPE_DEISTERDCA 1146 +#define MACH_TYPE_CES_SSEM2 1147 +#define MACH_TYPE_CES_MTR 1148 +#define MACH_TYPE_TDS_AVNG_SBC 1149 +#define MACH_TYPE_EVEREST 1150 +#define MACH_TYPE_PNX4010 1151 +#define MACH_TYPE_OXNAS 1152 +#define MACH_TYPE_FIORI 1153 +#define MACH_TYPE_ML1200 1154 +#define MACH_TYPE_PECOS 1155 +#define MACH_TYPE_NB2XXX 1156 +#define MACH_TYPE_HW6900 1157 +#define MACH_TYPE_CDCS_QUOLL 1158 +#define MACH_TYPE_QUICKSILVER 1159 +#define MACH_TYPE_UPLAT926 1160 +#define MACH_TYPE_DEP2410_THOMAS 1161 +#define MACH_TYPE_DTK2410 1162 +#define MACH_TYPE_CHILI 1163 +#define MACH_TYPE_DEMETER 1164 +#define MACH_TYPE_DIONYSUS 1165 +#define MACH_TYPE_AS352X 1166 +#define MACH_TYPE_SERVICE 1167 +#define MACH_TYPE_CS_E9301 1168 +#define MACH_TYPE_MICRO9M 1169 +#define MACH_TYPE_IA_MOSPCK 1170 +#define MACH_TYPE_QL201B 1171 +#define MACH_TYPE_BBM 1174 +#define MACH_TYPE_EXXX 1175 +#define MACH_TYPE_WMA11B 1176 +#define MACH_TYPE_PELCO_ATLAS 1177 +#define MACH_TYPE_G500 1178 +#define MACH_TYPE_BUG 1179 +#define MACH_TYPE_MX33ADS 1180 +#define MACH_TYPE_CHUB 1181 +#define MACH_TYPE_NEO1973_GTA01 1182 +#define MACH_TYPE_W90N740 1183 +#define MACH_TYPE_MEDALLION_SA2410 1184 +#define MACH_TYPE_IA_CPU_9200_2 1185 +#define MACH_TYPE_DIMMRM9200 1186 +#define MACH_TYPE_PM9261 1187 +#define MACH_TYPE_ML7304 1189 +#define MACH_TYPE_UCP250 1190 +#define MACH_TYPE_INTBOARD 1191 +#define MACH_TYPE_GULFSTREAM 1192 +#define MACH_TYPE_LABQUEST 1193 +#define MACH_TYPE_VCMX313 1194 +#define MACH_TYPE_URG200 1195 +#define MACH_TYPE_CPUX255LCDNET 1196 +#define MACH_TYPE_NETDCU9 1197 +#define MACH_TYPE_NETDCU10 1198 +#define MACH_TYPE_DSPG_DGA 1199 +#define MACH_TYPE_DSPG_DVW 1200 +#define MACH_TYPE_SOLOS 1201 +#define MACH_TYPE_AT91SAM9263EK 1202 +#define MACH_TYPE_OSSTBOX 1203 +#define MACH_TYPE_KBAT9261 1204 +#define MACH_TYPE_CT1100 1205 +#define MACH_TYPE_AKCPPXA 1206 +#define MACH_TYPE_OCHAYA1020 1207 +#define MACH_TYPE_HITRACK 1208 +#define MACH_TYPE_SYME1 1209 +#define MACH_TYPE_SYHL1 1210 +#define MACH_TYPE_EMPCA400 1211 +#define MACH_TYPE_EM7210 1212 +#define MACH_TYPE_HTCHERMES 1213 +#define MACH_TYPE_ETI_C1 1214 +#define MACH_TYPE_AC100 1216 +#define MACH_TYPE_SNEETCH 1217 +#define MACH_TYPE_STUDENTMATE 1218 +#define MACH_TYPE_ZIR2410 1219 +#define MACH_TYPE_ZIR2413 1220 +#define MACH_TYPE_DLONIP3 1221 +#define MACH_TYPE_INSTREAM 1222 +#define MACH_TYPE_AMBARELLA 1223 +#define MACH_TYPE_NEVIS 1224 +#define MACH_TYPE_HTC_TRINITY 1225 +#define MACH_TYPE_QL202B 1226 +#define MACH_TYPE_VPAC270 1227 +#define MACH_TYPE_RD129 1228 +#define MACH_TYPE_HTCWIZARD 1229 +#define MACH_TYPE_TREO680 1230 +#define MACH_TYPE_TECON_TMEZON 1231 +#define MACH_TYPE_ZYLONITE 1233 +#define MACH_TYPE_GENE1270 1234 +#define MACH_TYPE_ZIR2412 1235 +#define MACH_TYPE_MX31LITE 1236 +#define MACH_TYPE_T700WX 1237 +#define MACH_TYPE_VF100 1238 +#define MACH_TYPE_NSB2 1239 +#define MACH_TYPE_NXHMI_BB 1240 +#define MACH_TYPE_NXHMI_RE 1241 +#define MACH_TYPE_N4100PRO 1242 +#define MACH_TYPE_SAM9260 1243 +#define MACH_TYPE_OMAP_TREO600 1244 +#define MACH_TYPE_INDY2410 1245 +#define MACH_TYPE_NELT_A 1246 +#define MACH_TYPE_N311 1248 +#define MACH_TYPE_AT91SAM9260VGK 1249 +#define MACH_TYPE_AT91LEPPE 1250 +#define MACH_TYPE_AT91LEPCCN 1251 +#define MACH_TYPE_APC7100 1252 +#define MACH_TYPE_STARGAZER 1253 +#define MACH_TYPE_SONATA 1254 +#define MACH_TYPE_SCHMOOGIE 1255 +#define MACH_TYPE_AZTOOL 1256 +#define MACH_TYPE_MIOA701 1257 +#define MACH_TYPE_SXNI9260 1258 +#define MACH_TYPE_MXC27520EVB 1259 +#define MACH_TYPE_ARMADILLO5X0 1260 +#define MACH_TYPE_MB9260 1261 +#define MACH_TYPE_MB9263 1262 +#define MACH_TYPE_IPAC9302 1263 +#define MACH_TYPE_CC9P9360JS 1264 +#define MACH_TYPE_GALLIUM 1265 +#define MACH_TYPE_MSC2410 1266 +#define MACH_TYPE_GHI270 1267 +#define MACH_TYPE_DAVINCI_LEONARDO 1268 +#define MACH_TYPE_OIAB 1269 +#define MACH_TYPE_SMDK6400 1270 +#define MACH_TYPE_NOKIA_N800 1271 +#define MACH_TYPE_GREENPHONE 1272 +#define MACH_TYPE_COMPEXWP18 1273 +#define MACH_TYPE_XMATE 1274 +#define MACH_TYPE_ENERGIZER 1275 +#define MACH_TYPE_IME1 1276 +#define MACH_TYPE_SWEDATMS 1277 +#define MACH_TYPE_NTNP435C 1278 +#define MACH_TYPE_SPECTRO2 1279 +#define MACH_TYPE_H6039 1280 +#define MACH_TYPE_EP80219 1281 +#define MACH_TYPE_SAMOA_II 1282 +#define MACH_TYPE_CWMXL 1283 +#define MACH_TYPE_AS9200 1284 +#define MACH_TYPE_SFX1149 1285 +#define MACH_TYPE_NAVI010 1286 +#define MACH_TYPE_MULTMDP 1287 +#define MACH_TYPE_SCB9520 1288 +#define MACH_TYPE_HTCATHENA 1289 +#define MACH_TYPE_XP179 1290 +#define MACH_TYPE_H4300 1291 +#define MACH_TYPE_GORAMO_MLR 1292 +#define MACH_TYPE_MXC30020EVB 1293 +#define MACH_TYPE_ADSBITSYG5 1294 +#define MACH_TYPE_ADSPORTALPLUS 1295 +#define MACH_TYPE_MMSP2PLUS 1296 +#define MACH_TYPE_EM_X270 1297 +#define MACH_TYPE_TPP302 1298 +#define MACH_TYPE_TPM104 1299 +#define MACH_TYPE_TPM102 1300 +#define MACH_TYPE_TPM109 1301 +#define MACH_TYPE_FBXO1 1302 +#define MACH_TYPE_HXD8 1303 +#define MACH_TYPE_NEO1973_GTA02 1304 +#define MACH_TYPE_EMTEST 1305 +#define MACH_TYPE_AD6900 1306 +#define MACH_TYPE_EUROPA 1307 +#define MACH_TYPE_METROCONNECT 1308 +#define MACH_TYPE_EZ_S2410 1309 +#define MACH_TYPE_EZ_S2440 1310 +#define MACH_TYPE_EZ_EP9312 1311 +#define MACH_TYPE_EZ_EP9315 1312 +#define MACH_TYPE_EZ_X7 1313 +#define MACH_TYPE_GODOTDB 1314 +#define MACH_TYPE_MISTRAL 1315 +#define MACH_TYPE_MSM 1316 +#define MACH_TYPE_CT5910 1317 +#define MACH_TYPE_CT5912 1318 +#define MACH_TYPE_HYNET_INE 1319 +#define MACH_TYPE_HYNET_APP 1320 +#define MACH_TYPE_MSM7200 1321 +#define MACH_TYPE_MSM7600 1322 +#define MACH_TYPE_CEB255 1323 +#define MACH_TYPE_CIEL 1324 +#define MACH_TYPE_SLM5650 1325 +#define MACH_TYPE_AT91SAM9RLEK 1326 +#define MACH_TYPE_COMTECH_ROUTER 1327 +#define MACH_TYPE_SBC2410X 1328 +#define MACH_TYPE_AT4X0BD 1329 +#define MACH_TYPE_CBIFR 1330 +#define MACH_TYPE_ARCOM_QUANTUM 1331 +#define MACH_TYPE_MATRIX520 1332 +#define MACH_TYPE_MATRIX510 1333 +#define MACH_TYPE_MATRIX500 1334 +#define MACH_TYPE_M501 1335 +#define MACH_TYPE_AAEON1270 1336 +#define MACH_TYPE_MATRIX500EV 1337 +#define MACH_TYPE_PAC500 1338 +#define MACH_TYPE_PNX8181 1339 +#define MACH_TYPE_COLIBRI320 1340 +#define MACH_TYPE_AZTOOLBB 1341 +#define MACH_TYPE_AZTOOLG2 1342 +#define MACH_TYPE_DVLHOST 1343 +#define MACH_TYPE_ZIR9200 1344 +#define MACH_TYPE_ZIR9260 1345 +#define MACH_TYPE_COCOPAH 1346 +#define MACH_TYPE_NDS 1347 +#define MACH_TYPE_ROSENCRANTZ 1348 +#define MACH_TYPE_FTTX_ODSC 1349 +#define MACH_TYPE_CLASSE_R6904 1350 +#define MACH_TYPE_CAM60 1351 +#define MACH_TYPE_MXC30031ADS 1352 +#define MACH_TYPE_DATACALL 1353 +#define MACH_TYPE_AT91EB01 1354 +#define MACH_TYPE_RTY 1355 +#define MACH_TYPE_DWL2100 1356 +#define MACH_TYPE_VINSI 1357 +#define MACH_TYPE_DB88F5281 1358 +#define MACH_TYPE_CSB726 1359 +#define MACH_TYPE_TIK27 1360 +#define MACH_TYPE_MX_UC7420 1361 +#define MACH_TYPE_RIRM3 1362 +#define MACH_TYPE_PELCO_ODYSSEY 1363 +#define MACH_TYPE_ADX_ABOX 1365 +#define MACH_TYPE_ADX_TPID 1366 +#define MACH_TYPE_MINICHECK 1367 +#define MACH_TYPE_IDAM 1368 +#define MACH_TYPE_MARIO_MX 1369 +#define MACH_TYPE_VI1888 1370 +#define MACH_TYPE_ZR4230 1371 +#define MACH_TYPE_T1_IX_BLUE 1372 +#define MACH_TYPE_SYHQ2 1373 +#define MACH_TYPE_COMPUTIME_R3 1374 +#define MACH_TYPE_ORATIS 1375 +#define MACH_TYPE_MIKKO 1376 +#define MACH_TYPE_HOLON 1377 +#define MACH_TYPE_OLIP8 1378 +#define MACH_TYPE_GHI270HG 1379 +#define MACH_TYPE_DAVINCI_DM6467_EVM 1380 +#define MACH_TYPE_DAVINCI_DM355_EVM 1381 +#define MACH_TYPE_BLACKRIVER 1383 +#define MACH_TYPE_SANDGATEWP 1384 +#define MACH_TYPE_CDOTBWSG 1385 +#define MACH_TYPE_QUARK963 1386 +#define MACH_TYPE_CSB735 1387 +#define MACH_TYPE_LITTLETON 1388 +#define MACH_TYPE_MIO_P550 1389 +#define MACH_TYPE_MOTION2440 1390 +#define MACH_TYPE_IMM500 1391 +#define MACH_TYPE_HOMEMATIC 1392 +#define MACH_TYPE_ERMINE 1393 +#define MACH_TYPE_KB9202B 1394 +#define MACH_TYPE_HS1XX 1395 +#define MACH_TYPE_STUDENTMATE2440 1396 +#define MACH_TYPE_ARVOO_L1_Z1 1397 +#define MACH_TYPE_DEP2410K 1398 +#define MACH_TYPE_XXSVIDEO 1399 +#define MACH_TYPE_IM4004 1400 +#define MACH_TYPE_OCHAYA1050 1401 +#define MACH_TYPE_LEP9261 1402 +#define MACH_TYPE_SVENMEB 1403 +#define MACH_TYPE_FORTUNET2NE 1404 +#define MACH_TYPE_NXHX 1406 +#define MACH_TYPE_REALVIEW_PB11MP 1407 +#define MACH_TYPE_IDS500 1408 +#define MACH_TYPE_ORS_N725 1409 +#define MACH_TYPE_HSDARM 1410 +#define MACH_TYPE_SHA_PON003 1411 +#define MACH_TYPE_SHA_PON004 1412 +#define MACH_TYPE_SHA_PON007 1413 +#define MACH_TYPE_SHA_PON011 1414 +#define MACH_TYPE_H6042 1415 +#define MACH_TYPE_H6043 1416 +#define MACH_TYPE_LOOXC550 1417 +#define MACH_TYPE_CNTY_TITAN 1418 +#define MACH_TYPE_APP3XX 1419 +#define MACH_TYPE_SIDEOATSGRAMA 1420 +#define MACH_TYPE_TREO700P 1421 +#define MACH_TYPE_TREO700W 1422 +#define MACH_TYPE_TREO750 1423 +#define MACH_TYPE_TREO755P 1424 +#define MACH_TYPE_EZREGANUT9200 1425 +#define MACH_TYPE_SARGE 1426 +#define MACH_TYPE_A696 1427 +#define MACH_TYPE_TURTLE 1428 +#define MACH_TYPE_MX27_3DS 1430 +#define MACH_TYPE_BISHOP 1431 +#define MACH_TYPE_PXX 1432 +#define MACH_TYPE_REDWOOD 1433 +#define MACH_TYPE_OMAP_2430DLP 1436 +#define MACH_TYPE_OMAP_2430OSK 1437 +#define MACH_TYPE_SARDINE 1438 +#define MACH_TYPE_HALIBUT 1439 +#define MACH_TYPE_TROUT 1440 +#define MACH_TYPE_GOLDFISH 1441 +#define MACH_TYPE_GESBC2440 1442 +#define MACH_TYPE_NOMAD 1443 +#define MACH_TYPE_ROSALIND 1444 +#define MACH_TYPE_CC9P9215 1445 +#define MACH_TYPE_CC9P9210 1446 +#define MACH_TYPE_CC9P9215JS 1447 +#define MACH_TYPE_CC9P9210JS 1448 +#define MACH_TYPE_NASFFE 1449 +#define MACH_TYPE_TN2X0BD 1450 +#define MACH_TYPE_GWMPXA 1451 +#define MACH_TYPE_EXYPLUS 1452 +#define MACH_TYPE_JADOO21 1453 +#define MACH_TYPE_LOOXN560 1454 +#define MACH_TYPE_BONSAI 1455 +#define MACH_TYPE_ADSMILGATO 1456 +#define MACH_TYPE_GBA 1457 +#define MACH_TYPE_H6044 1458 +#define MACH_TYPE_APP 1459 +#define MACH_TYPE_TCT_HAMMER 1460 +#define MACH_TYPE_HERALD 1461 +#define MACH_TYPE_ARTEMIS 1462 +#define MACH_TYPE_HTCTITAN 1463 +#define MACH_TYPE_QRANIUM 1464 +#define MACH_TYPE_ADX_WSC2 1465 +#define MACH_TYPE_ADX_MEDCOM 1466 +#define MACH_TYPE_BBOARD 1467 +#define MACH_TYPE_CAMBRIA 1468 +#define MACH_TYPE_MT7XXX 1469 +#define MACH_TYPE_MATRIX512 1470 +#define MACH_TYPE_MATRIX522 1471 +#define MACH_TYPE_IPAC5010 1472 +#define MACH_TYPE_SAKURA 1473 +#define MACH_TYPE_GROCX 1474 +#define MACH_TYPE_PM9263 1475 +#define MACH_TYPE_SIM_ONE 1476 +#define MACH_TYPE_ACQ132 1477 +#define MACH_TYPE_DATR 1478 +#define MACH_TYPE_ACTUX1 1479 +#define MACH_TYPE_ACTUX2 1480 +#define MACH_TYPE_ACTUX3 1481 +#define MACH_TYPE_FLEXIT 1482 +#define MACH_TYPE_BH2X0BD 1483 +#define MACH_TYPE_ATB2002 1484 +#define MACH_TYPE_XENON 1485 +#define MACH_TYPE_FM607 1486 +#define MACH_TYPE_MATRIX514 1487 +#define MACH_TYPE_MATRIX524 1488 +#define MACH_TYPE_INPOD 1489 +#define MACH_TYPE_JIVE 1490 +#define MACH_TYPE_TLL_MX21 1491 +#define MACH_TYPE_SBC2800 1492 +#define MACH_TYPE_CC7UCAMRY 1493 +#define MACH_TYPE_UBISYS_P9_SC15 1494 +#define MACH_TYPE_UBISYS_P9_SSC2D10 1495 +#define MACH_TYPE_UBISYS_P9_RCU3 1496 +#define MACH_TYPE_AML_M8000 1497 +#define MACH_TYPE_SNAPPER_270 1498 +#define MACH_TYPE_OMAP_BBX 1499 +#define MACH_TYPE_UCN2410 1500 +#define MACH_TYPE_SAM9_L9260 1501 +#define MACH_TYPE_ETI_C2 1502 +#define MACH_TYPE_AVALANCHE 1503 +#define MACH_TYPE_REALVIEW_PB1176 1504 +#define MACH_TYPE_DP1500 1505 +#define MACH_TYPE_APPLE_IPHONE 1506 +#define MACH_TYPE_YL9200 1507 +#define MACH_TYPE_RD88F5182 1508 +#define MACH_TYPE_KUROBOX_PRO 1509 +#define MACH_TYPE_SE_POET 1510 +#define MACH_TYPE_MX31_3DS 1511 +#define MACH_TYPE_R270 1512 +#define MACH_TYPE_ARMOUR21 1513 +#define MACH_TYPE_DT2 1514 +#define MACH_TYPE_VT4 1515 +#define MACH_TYPE_TYCO320 1516 +#define MACH_TYPE_ADMA 1517 +#define MACH_TYPE_WP188 1518 +#define MACH_TYPE_CORSICA 1519 +#define MACH_TYPE_BIGEYE 1520 +#define MACH_TYPE_TLL5000 1522 +#define MACH_TYPE_BEBOT 1523 +#define MACH_TYPE_QONG 1524 +#define MACH_TYPE_TCOMPACT 1525 +#define MACH_TYPE_PUMA5 1526 +#define MACH_TYPE_ELARA 1527 +#define MACH_TYPE_ELLINGTON 1528 +#define MACH_TYPE_XDA_ATOM 1529 +#define MACH_TYPE_ENERGIZER2 1530 +#define MACH_TYPE_ODIN 1531 +#define MACH_TYPE_ACTUX4 1532 +#define MACH_TYPE_ESL_OMAP 1533 +#define MACH_TYPE_OMAP2EVM 1534 +#define MACH_TYPE_OMAP3EVM 1535 +#define MACH_TYPE_ADX_PCU57 1536 +#define MACH_TYPE_MONACO 1537 +#define MACH_TYPE_LEVANTE 1538 +#define MACH_TYPE_TMXIPX425 1539 +#define MACH_TYPE_LEEP 1540 +#define MACH_TYPE_RAAD 1541 +#define MACH_TYPE_DNS323 1542 +#define MACH_TYPE_AP1000 1543 +#define MACH_TYPE_A9SAM6432 1544 +#define MACH_TYPE_SHINY 1545 +#define MACH_TYPE_OMAP3_BEAGLE 1546 +#define MACH_TYPE_CSR_BDB2 1547 +#define MACH_TYPE_NOKIA_N810 1548 +#define MACH_TYPE_C270 1549 +#define MACH_TYPE_SENTRY 1550 +#define MACH_TYPE_PCM038 1551 +#define MACH_TYPE_ANC300 1552 +#define MACH_TYPE_HTCKAISER 1553 +#define MACH_TYPE_SBAT100 1554 +#define MACH_TYPE_MODUNORM 1555 +#define MACH_TYPE_PELOS_TWARM 1556 +#define MACH_TYPE_FLANK 1557 +#define MACH_TYPE_SIRLOIN 1558 +#define MACH_TYPE_BRISKET 1559 +#define MACH_TYPE_CHUCK 1560 +#define MACH_TYPE_OTTER 1561 +#define MACH_TYPE_DAVINCI_LDK 1562 +#define MACH_TYPE_PHREEDOM 1563 +#define MACH_TYPE_SG310 1564 +#define MACH_TYPE_TS209 1565 +#define MACH_TYPE_AT91CAP9ADK 1566 +#define MACH_TYPE_TION9315 1567 +#define MACH_TYPE_MAST 1568 +#define MACH_TYPE_PFW 1569 +#define MACH_TYPE_YL_P2440 1570 +#define MACH_TYPE_ZSBC32 1571 +#define MACH_TYPE_OMAP_PACE2 1572 +#define MACH_TYPE_IMX_PACE2 1573 +#define MACH_TYPE_MX31MOBOARD 1574 +#define MACH_TYPE_MX37_3DS 1575 +#define MACH_TYPE_RCC 1576 +#define MACH_TYPE_ARM9 1577 +#define MACH_TYPE_VISION_EP9307 1578 +#define MACH_TYPE_SCLY1000 1579 +#define MACH_TYPE_FONTEL_EP 1580 +#define MACH_TYPE_VOICEBLUE3G 1581 +#define MACH_TYPE_TT9200 1582 +#define MACH_TYPE_DIGI2410 1583 +#define MACH_TYPE_TERASTATION_PRO2 1584 +#define MACH_TYPE_LINKSTATION_PRO 1585 +#define MACH_TYPE_MOTOROLA_A780 1587 +#define MACH_TYPE_MOTOROLA_E6 1588 +#define MACH_TYPE_MOTOROLA_E2 1589 +#define MACH_TYPE_MOTOROLA_E680 1590 +#define MACH_TYPE_UR2410 1591 +#define MACH_TYPE_TAS9261 1592 +#define MACH_TYPE_HERMES_HD 1593 +#define MACH_TYPE_PERSEO_HD 1594 +#define MACH_TYPE_STARGAZER2 1595 +#define MACH_TYPE_E350 1596 +#define MACH_TYPE_WPCM450 1597 +#define MACH_TYPE_CARTESIO 1598 +#define MACH_TYPE_TOYBOX 1599 +#define MACH_TYPE_TX27 1600 +#define MACH_TYPE_TS409 1601 +#define MACH_TYPE_P300 1602 +#define MACH_TYPE_XDACOMET 1603 +#define MACH_TYPE_DEXFLEX2 1604 +#define MACH_TYPE_OW 1605 +#define MACH_TYPE_ARMEBS3 1606 +#define MACH_TYPE_U3 1607 +#define MACH_TYPE_SMDK2450 1608 +#define MACH_TYPE_RSI_EWS 1609 +#define MACH_TYPE_TNB 1610 +#define MACH_TYPE_TOEPATH 1611 +#define MACH_TYPE_KB9263 1612 +#define MACH_TYPE_MT7108 1613 +#define MACH_TYPE_SMTR2440 1614 +#define MACH_TYPE_MANAO 1615 +#define MACH_TYPE_CM_X300 1616 +#define MACH_TYPE_GULFSTREAM_KP 1617 +#define MACH_TYPE_LANREADYFN522 1618 +#define MACH_TYPE_ARMA37 1619 +#define MACH_TYPE_MENDEL 1620 +#define MACH_TYPE_PELCO_ILIAD 1621 +#define MACH_TYPE_UNIT2P 1622 +#define MACH_TYPE_INC20OTTER 1623 +#define MACH_TYPE_AT91SAM9G20EK 1624 +#define MACH_TYPE_STORCENTER 1625 +#define MACH_TYPE_SMDK6410 1626 +#define MACH_TYPE_U300 1627 +#define MACH_TYPE_U500 1628 +#define MACH_TYPE_DS9260 1629 +#define MACH_TYPE_RIVERROCK 1630 +#define MACH_TYPE_SCIBATH 1631 +#define MACH_TYPE_AT91SAM7SE512EK 1632 +#define MACH_TYPE_WRT350N_V2 1633 +#define MACH_TYPE_MULTIMEDIA 1634 +#define MACH_TYPE_MARVIN 1635 +#define MACH_TYPE_X500 1636 +#define MACH_TYPE_AWLUG4LCU 1637 +#define MACH_TYPE_PALERMOC 1638 +#define MACH_TYPE_OMAP_LDP 1639 +#define MACH_TYPE_IP500 1640 +#define MACH_TYPE_ASE2 1642 +#define MACH_TYPE_MX35EVB 1643 +#define MACH_TYPE_AML_M8050 1644 +#define MACH_TYPE_MX35_3DS 1645 +#define MACH_TYPE_MARS 1646 +#define MACH_TYPE_NEUROS_OSD2 1647 +#define MACH_TYPE_BADGER 1648 +#define MACH_TYPE_TRIZEPS4WL 1649 +#define MACH_TYPE_TRIZEPS5 1650 +#define MACH_TYPE_MARLIN 1651 +#define MACH_TYPE_TS78XX 1652 +#define MACH_TYPE_HPIPAQ214 1653 +#define MACH_TYPE_AT572D940DCM 1654 +#define MACH_TYPE_NE1BOARD 1655 +#define MACH_TYPE_ZANTE 1656 +#define MACH_TYPE_SFFSDR 1657 +#define MACH_TYPE_TW2662 1658 +#define MACH_TYPE_VF10XX 1659 +#define MACH_TYPE_ZORAN43XX 1660 +#define MACH_TYPE_SONIX926 1661 +#define MACH_TYPE_CELESTIALSEMI 1662 +#define MACH_TYPE_CC9M2443JS 1663 +#define MACH_TYPE_TW5334 1664 +#define MACH_TYPE_HTCARTEMIS 1665 +#define MACH_TYPE_NAL_HLITE 1666 +#define MACH_TYPE_HTCVOGUE 1667 +#define MACH_TYPE_SMARTWEB 1668 +#define MACH_TYPE_MV86XX 1669 +#define MACH_TYPE_MV87XX 1670 +#define MACH_TYPE_SONGYOUNGHO 1671 +#define MACH_TYPE_YOUNGHOTEMA 1672 +#define MACH_TYPE_PCM037 1673 +#define MACH_TYPE_MMVP 1674 +#define MACH_TYPE_MMAP 1675 +#define MACH_TYPE_PTID2410 1676 +#define MACH_TYPE_JAMES_926 1677 +#define MACH_TYPE_FM6000 1678 +#define MACH_TYPE_DB88F6281_BP 1680 +#define MACH_TYPE_RD88F6192_NAS 1681 +#define MACH_TYPE_RD88F6281 1682 +#define MACH_TYPE_DB78X00_BP 1683 +#define MACH_TYPE_SMDK2416 1685 +#define MACH_TYPE_OCE_SPIDER_SI 1686 +#define MACH_TYPE_OCE_SPIDER_SK 1687 +#define MACH_TYPE_ROVERN6 1688 +#define MACH_TYPE_PELCO_EVOLUTION 1689 +#define MACH_TYPE_WBD111 1690 +#define MACH_TYPE_ELARACPE 1691 +#define MACH_TYPE_MABV3 1692 +#define MACH_TYPE_MV2120 1693 +#define MACH_TYPE_CSB737 1695 +#define MACH_TYPE_MX51_3DS 1696 +#define MACH_TYPE_G900 1697 +#define MACH_TYPE_APF27 1698 +#define MACH_TYPE_GGUS2000 1699 +#define MACH_TYPE_OMAP_2430_MIMIC 1700 +#define MACH_TYPE_IMX27LITE 1701 +#define MACH_TYPE_ALMEX 1702 +#define MACH_TYPE_CONTROL 1703 +#define MACH_TYPE_MBA2410 1704 +#define MACH_TYPE_VOLCANO 1705 +#define MACH_TYPE_ZENITH 1706 +#define MACH_TYPE_MUCHIP 1707 +#define MACH_TYPE_MAGELLAN 1708 +#define MACH_TYPE_USB_A9260 1709 +#define MACH_TYPE_USB_A9263 1710 +#define MACH_TYPE_QIL_A9260 1711 +#define MACH_TYPE_CME9210 1712 +#define MACH_TYPE_HCZH4 1713 +#define MACH_TYPE_SPEARBASIC 1714 +#define MACH_TYPE_DEP2440 1715 +#define MACH_TYPE_HDL_GXR 1716 +#define MACH_TYPE_HDL_GT 1717 +#define MACH_TYPE_HDL_4G 1718 +#define MACH_TYPE_S3C6000 1719 +#define MACH_TYPE_MMSP2_MDK 1720 +#define MACH_TYPE_MPX220 1721 +#define MACH_TYPE_KZM_ARM11_01 1722 +#define MACH_TYPE_HTC_POLARIS 1723 +#define MACH_TYPE_HTC_KAISER 1724 +#define MACH_TYPE_LG_KS20 1725 +#define MACH_TYPE_HHGPS 1726 +#define MACH_TYPE_NOKIA_N810_WIMAX 1727 +#define MACH_TYPE_INSIGHT 1728 +#define MACH_TYPE_SAPPHIRE 1729 +#define MACH_TYPE_CSB637XO 1730 +#define MACH_TYPE_EVISIONG 1731 +#define MACH_TYPE_STMP37XX 1732 +#define MACH_TYPE_STMP378X 1733 +#define MACH_TYPE_TNT 1734 +#define MACH_TYPE_TBXT 1735 +#define MACH_TYPE_PLAYMATE 1736 +#define MACH_TYPE_PNS10 1737 +#define MACH_TYPE_EZNAVI 1738 +#define MACH_TYPE_PS4000 1739 +#define MACH_TYPE_EZX_A780 1740 +#define MACH_TYPE_EZX_E680 1741 +#define MACH_TYPE_EZX_A1200 1742 +#define MACH_TYPE_EZX_E6 1743 +#define MACH_TYPE_EZX_E2 1744 +#define MACH_TYPE_EZX_A910 1745 +#define MACH_TYPE_CWMX31 1746 +#define MACH_TYPE_SL2312 1747 +#define MACH_TYPE_BLENNY 1748 +#define MACH_TYPE_DS107 1749 +#define MACH_TYPE_DSX07 1750 +#define MACH_TYPE_PICOCOM1 1751 +#define MACH_TYPE_LYNX_WOLVERINE 1752 +#define MACH_TYPE_UBISYS_P9_SC19 1753 +#define MACH_TYPE_KRATOS_LOW 1754 +#define MACH_TYPE_M700 1755 +#define MACH_TYPE_EDMINI_V2 1756 +#define MACH_TYPE_ZIPIT2 1757 +#define MACH_TYPE_HSLFEMTOCELL 1758 +#define MACH_TYPE_DAINTREE_AT91 1759 +#define MACH_TYPE_SG560USB 1760 +#define MACH_TYPE_OMAP3_PANDORA 1761 +#define MACH_TYPE_USR8200 1762 +#define MACH_TYPE_S1S65K 1763 +#define MACH_TYPE_S2S65A 1764 +#define MACH_TYPE_ICORE 1765 +#define MACH_TYPE_MSS2 1766 +#define MACH_TYPE_BELMONT 1767 +#define MACH_TYPE_ASUSP525 1768 +#define MACH_TYPE_LB88RC8480 1769 +#define MACH_TYPE_HIPXA 1770 +#define MACH_TYPE_MX25_3DS 1771 +#define MACH_TYPE_M800 1772 +#define MACH_TYPE_OMAP3530_LV_SOM 1773 +#define MACH_TYPE_PRIMA_EVB 1774 +#define MACH_TYPE_MX31BT1 1775 +#define MACH_TYPE_ATLAS4_EVB 1776 +#define MACH_TYPE_MX31CICADA 1777 +#define MACH_TYPE_MI424WR 1778 +#define MACH_TYPE_AXS_ULTRAX 1779 +#define MACH_TYPE_AT572D940DEB 1780 +#define MACH_TYPE_DAVINCI_DA830_EVM 1781 +#define MACH_TYPE_EP9302 1782 +#define MACH_TYPE_AT572D940HFEB 1783 +#define MACH_TYPE_CYBOOK3 1784 +#define MACH_TYPE_WDG002 1785 +#define MACH_TYPE_SG560ADSL 1786 +#define MACH_TYPE_NEXTIO_N2800_ICA 1787 +#define MACH_TYPE_DOVE_DB 1788 +#define MACH_TYPE_MARVELL_NEWDB 1789 +#define MACH_TYPE_VANDIHUD 1790 +#define MACH_TYPE_MAGX_E8 1791 +#define MACH_TYPE_MAGX_Z6 1792 +#define MACH_TYPE_MAGX_V8 1793 +#define MACH_TYPE_MAGX_U9 1794 +#define MACH_TYPE_TOUGHCF08 1795 +#define MACH_TYPE_ZW4400 1796 +#define MACH_TYPE_MARAT91 1797 +#define MACH_TYPE_OVERO 1798 +#define MACH_TYPE_AT2440EVB 1799 +#define MACH_TYPE_NEOCORE926 1800 +#define MACH_TYPE_WNR854T 1801 +#define MACH_TYPE_IMX27 1802 +#define MACH_TYPE_MOOSE_DB 1803 +#define MACH_TYPE_FAB4 1804 +#define MACH_TYPE_HTCDIAMOND 1805 +#define MACH_TYPE_FIONA 1806 +#define MACH_TYPE_MXC30030_X 1807 +#define MACH_TYPE_BMP1000 1808 +#define MACH_TYPE_LOGI9200 1809 +#define MACH_TYPE_TQMA31 1810 +#define MACH_TYPE_CCW9P9215JS 1811 +#define MACH_TYPE_RD88F5181L_GE 1812 +#define MACH_TYPE_SIFMAIN 1813 +#define MACH_TYPE_SAM9_L9261 1814 +#define MACH_TYPE_CC9M2443 1815 +#define MACH_TYPE_XARIA300 1816 +#define MACH_TYPE_IT9200 1817 +#define MACH_TYPE_RD88F5181L_FXO 1818 +#define MACH_TYPE_KRISS_SENSOR 1819 +#define MACH_TYPE_PILZ_PMI5 1820 +#define MACH_TYPE_JADE 1821 +#define MACH_TYPE_KS8695_SOFTPLC 1822 +#define MACH_TYPE_GPRISC3 1823 +#define MACH_TYPE_STAMP9G20 1824 +#define MACH_TYPE_SMDK6430 1825 +#define MACH_TYPE_SMDKC100 1826 +#define MACH_TYPE_TAVOREVB 1827 +#define MACH_TYPE_SAAR 1828 +#define MACH_TYPE_DEISTER_EYECAM 1829 +#define MACH_TYPE_AT91SAM9M10G45EK 1830 +#define MACH_TYPE_LINKSTATION_PRODUO 1831 +#define MACH_TYPE_HIT_B0 1832 +#define MACH_TYPE_ADX_RMU 1833 +#define MACH_TYPE_XG_CPE_MAIN 1834 +#define MACH_TYPE_EDB9407A 1835 +#define MACH_TYPE_DTB9608 1836 +#define MACH_TYPE_EM104V1 1837 +#define MACH_TYPE_DEMO 1838 +#define MACH_TYPE_LOGI9260 1839 +#define MACH_TYPE_MX31_EXM32 1840 +#define MACH_TYPE_USB_A9G20 1841 +#define MACH_TYPE_PICPROJE2008 1842 +#define MACH_TYPE_CS_E9315 1843 +#define MACH_TYPE_QIL_A9G20 1844 +#define MACH_TYPE_SHA_PON020 1845 +#define MACH_TYPE_NAD 1846 +#define MACH_TYPE_SBC35_A9260 1847 +#define MACH_TYPE_SBC35_A9G20 1848 +#define MACH_TYPE_DAVINCI_BEGINNING 1849 +#define MACH_TYPE_UWC 1850 +#define MACH_TYPE_MXLADS 1851 +#define MACH_TYPE_HTCNIKE 1852 +#define MACH_TYPE_DEISTER_PXA270 1853 +#define MACH_TYPE_CME9210JS 1854 +#define MACH_TYPE_CC9P9360 1855 +#define MACH_TYPE_MOCHA 1856 +#define MACH_TYPE_WAPD170AG 1857 +#define MACH_TYPE_LINKSTATION_MINI 1858 +#define MACH_TYPE_AFEB9260 1859 +#define MACH_TYPE_W90X900 1860 +#define MACH_TYPE_W90X700 1861 +#define MACH_TYPE_KT300IP 1862 +#define MACH_TYPE_KT300IP_G20 1863 +#define MACH_TYPE_SRCM 1864 +#define MACH_TYPE_WLNX_9260 1865 +#define MACH_TYPE_OPENMOKO_GTA03 1866 +#define MACH_TYPE_OSPREY2 1867 +#define MACH_TYPE_KBIO9260 1868 +#define MACH_TYPE_GINZA 1869 +#define MACH_TYPE_A636N 1870 +#define MACH_TYPE_IMX27IPCAM 1871 +#define MACH_TYPE_NEMOC 1872 +#define MACH_TYPE_GENEVA 1873 +#define MACH_TYPE_HTCPHAROS 1874 +#define MACH_TYPE_NEONC 1875 +#define MACH_TYPE_NAS7100 1876 +#define MACH_TYPE_TEUPHONE 1877 +#define MACH_TYPE_ANNAX_ETH2 1878 +#define MACH_TYPE_CSB733 1879 +#define MACH_TYPE_BK3 1880 +#define MACH_TYPE_OMAP_EM32 1881 +#define MACH_TYPE_ET9261CP 1882 +#define MACH_TYPE_JASPERC 1883 +#define MACH_TYPE_ISSI_ARM9 1884 +#define MACH_TYPE_UED 1885 +#define MACH_TYPE_ESIBLADE 1886 +#define MACH_TYPE_EYE02 1887 +#define MACH_TYPE_IMX27KBD 1888 +#define MACH_TYPE_SST61VC010_FPGA 1889 +#define MACH_TYPE_KIXVP435 1890 +#define MACH_TYPE_KIXNP435 1891 +#define MACH_TYPE_AFRICA 1892 +#define MACH_TYPE_NH233 1893 +#define MACH_TYPE_RD88F6183AP_GE 1894 +#define MACH_TYPE_BCM4760 1895 +#define MACH_TYPE_EDDY_V2 1896 +#define MACH_TYPE_REALVIEW_PBA8 1897 +#define MACH_TYPE_HID_A7 1898 +#define MACH_TYPE_HERO 1899 +#define MACH_TYPE_OMAP_POSEIDON 1900 +#define MACH_TYPE_REALVIEW_PBX 1901 +#define MACH_TYPE_MICRO9S 1902 +#define MACH_TYPE_MAKO 1903 +#define MACH_TYPE_XDAFLAME 1904 +#define MACH_TYPE_PHIDGET_SBC2 1905 +#define MACH_TYPE_LIMESTONE 1906 +#define MACH_TYPE_IPROBE_C32 1907 +#define MACH_TYPE_RUT100 1908 +#define MACH_TYPE_ASUSP535 1909 +#define MACH_TYPE_HTCRAPHAEL 1910 +#define MACH_TYPE_SYGDG1 1911 +#define MACH_TYPE_SYGDG2 1912 +#define MACH_TYPE_SEOUL 1913 +#define MACH_TYPE_SALERNO 1914 +#define MACH_TYPE_UCN_S3C64XX 1915 +#define MACH_TYPE_MSM7201A 1916 +#define MACH_TYPE_LPR1 1917 +#define MACH_TYPE_ARMADILLO500FX 1918 +#define MACH_TYPE_G3EVM 1919 +#define MACH_TYPE_Z3_DM355 1920 +#define MACH_TYPE_W90P910EVB 1921 +#define MACH_TYPE_W90P920EVB 1922 +#define MACH_TYPE_W90P950EVB 1923 +#define MACH_TYPE_W90N960EVB 1924 +#define MACH_TYPE_CAMHD 1925 +#define MACH_TYPE_MVC100 1926 +#define MACH_TYPE_ELECTRUM_200 1927 +#define MACH_TYPE_HTCJADE 1928 +#define MACH_TYPE_MEMPHIS 1929 +#define MACH_TYPE_IMX27SBC 1930 +#define MACH_TYPE_LEXTAR 1931 +#define MACH_TYPE_MV88F6281GTW_GE 1932 +#define MACH_TYPE_NCP 1933 +#define MACH_TYPE_Z32AN 1934 +#define MACH_TYPE_TMQ_CAPD 1935 +#define MACH_TYPE_OMAP3_WL 1936 +#define MACH_TYPE_CHUMBY 1937 +#define MACH_TYPE_ATSARM9 1938 +#define MACH_TYPE_DAVINCI_DM365_EVM 1939 +#define MACH_TYPE_BAHAMAS 1940 +#define MACH_TYPE_DAS 1941 +#define MACH_TYPE_MINIDAS 1942 +#define MACH_TYPE_VK1000 1943 +#define MACH_TYPE_CENTRO 1944 +#define MACH_TYPE_CTERA_2BAY 1945 +#define MACH_TYPE_EDGECONNECT 1946 +#define MACH_TYPE_ND27000 1947 +#define MACH_TYPE_GEMALTO_COBRA 1948 +#define MACH_TYPE_INGELABS_COMET 1949 +#define MACH_TYPE_POLLUX_WIZ 1950 +#define MACH_TYPE_BLACKSTONE 1951 +#define MACH_TYPE_TOPAZ 1952 +#define MACH_TYPE_AIXLE 1953 +#define MACH_TYPE_MW998 1954 +#define MACH_TYPE_NOKIA_RX51 1955 +#define MACH_TYPE_VSC5605EV 1956 +#define MACH_TYPE_NT98700DK 1957 +#define MACH_TYPE_ICONTACT 1958 +#define MACH_TYPE_SWARCO_FRCPU 1959 +#define MACH_TYPE_SWARCO_SCPU 1960 +#define MACH_TYPE_BBOX_P16 1961 +#define MACH_TYPE_BSTD 1962 +#define MACH_TYPE_SBC2440II 1963 +#define MACH_TYPE_PCM034 1964 +#define MACH_TYPE_NESO 1965 +#define MACH_TYPE_WLNX_9G20 1966 +#define MACH_TYPE_OMAP_ZOOM2 1967 +#define MACH_TYPE_TOTEMNOVA 1968 +#define MACH_TYPE_C5000 1969 +#define MACH_TYPE_UNIPO_AT91SAM9263 1970 +#define MACH_TYPE_ETHERNUT5 1971 +#define MACH_TYPE_ARM11 1972 +#define MACH_TYPE_CPUAT9260 1973 +#define MACH_TYPE_CPUPXA255 1974 +#define MACH_TYPE_CPUIMX27 1975 +#define MACH_TYPE_CHEFLUX 1976 +#define MACH_TYPE_EB_CPUX9K2 1977 +#define MACH_TYPE_OPCOTEC 1978 +#define MACH_TYPE_YT 1979 +#define MACH_TYPE_MOTOQ 1980 +#define MACH_TYPE_BSB1 1981 +#define MACH_TYPE_ACS5K 1982 +#define MACH_TYPE_MILAN 1983 +#define MACH_TYPE_QUARTZV2 1984 +#define MACH_TYPE_RSVP 1985 +#define MACH_TYPE_RMP200 1986 +#define MACH_TYPE_SNAPPER_9260 1987 +#define MACH_TYPE_DSM320 1988 +#define MACH_TYPE_ADSGCM 1989 +#define MACH_TYPE_ASE2_400 1990 +#define MACH_TYPE_PIZZA 1991 +#define MACH_TYPE_SPOT_NGPL 1992 +#define MACH_TYPE_ARMATA 1993 +#define MACH_TYPE_EXEDA 1994 +#define MACH_TYPE_MX31SF005 1995 +#define MACH_TYPE_F5D8231_4_V2 1996 +#define MACH_TYPE_Q2440 1997 +#define MACH_TYPE_QQ2440 1998 +#define MACH_TYPE_MINI2440 1999 +#define MACH_TYPE_COLIBRI300 2000 +#define MACH_TYPE_JADES 2001 +#define MACH_TYPE_SPARK 2002 +#define MACH_TYPE_BENZINA 2003 +#define MACH_TYPE_BLAZE 2004 +#define MACH_TYPE_LINKSTATION_LS_HGL 2005 +#define MACH_TYPE_HTCVENUS 2006 +#define MACH_TYPE_SONY_PRS505 2007 +#define MACH_TYPE_HANLIN_V3 2008 +#define MACH_TYPE_SAPPHIRA 2009 +#define MACH_TYPE_DACK_SDA_01 2010 +#define MACH_TYPE_ARMBOX 2011 +#define MACH_TYPE_HARRIS_RVP 2012 +#define MACH_TYPE_RIBALDO 2013 +#define MACH_TYPE_AGORA 2014 +#define MACH_TYPE_OMAP3_MINI 2015 +#define MACH_TYPE_A9SAM6432_B 2016 +#define MACH_TYPE_USG2410 2017 +#define MACH_TYPE_PC72052_I10_REVB 2018 +#define MACH_TYPE_MX35_EXM32 2019 +#define MACH_TYPE_TOPAS910 2020 +#define MACH_TYPE_HYENA 2021 +#define MACH_TYPE_POSPAX 2022 +#define MACH_TYPE_HDL_GX 2023 +#define MACH_TYPE_CTERA_4BAY 2024 +#define MACH_TYPE_CTERA_PLUG_C 2025 +#define MACH_TYPE_CRWEA_PLUG_I 2026 +#define MACH_TYPE_EGAUGE2 2027 +#define MACH_TYPE_DIDJ 2028 +#define MACH_TYPE_MEISTER 2029 +#define MACH_TYPE_HTCBLACKSTONE 2030 +#define MACH_TYPE_CPUAT9G20 2031 +#define MACH_TYPE_SMDK6440 2032 +#define MACH_TYPE_OMAP_35XX_MVP 2033 +#define MACH_TYPE_CTERA_PLUG_I 2034 +#define MACH_TYPE_PVG610 2035 +#define MACH_TYPE_HPRW6815 2036 +#define MACH_TYPE_OMAP3_OSWALD 2037 +#define MACH_TYPE_NAS4220B 2038 +#define MACH_TYPE_HTCRAPHAEL_CDMA 2039 +#define MACH_TYPE_HTCDIAMOND_CDMA 2040 +#define MACH_TYPE_SCALER 2041 +#define MACH_TYPE_ZYLONITE2 2042 +#define MACH_TYPE_ASPENITE 2043 +#define MACH_TYPE_TETON 2044 +#define MACH_TYPE_TTC_DKB 2045 +#define MACH_TYPE_BISHOP2 2046 +#define MACH_TYPE_IPPV5 2047 +#define MACH_TYPE_FARM926 2048 +#define MACH_TYPE_MMCCPU 2049 +#define MACH_TYPE_SGMSFL 2050 +#define MACH_TYPE_TT8000 2051 +#define MACH_TYPE_ZRN4300LP 2052 +#define MACH_TYPE_MPTC 2053 +#define MACH_TYPE_H6051 2054 +#define MACH_TYPE_PVG610_101 2055 +#define MACH_TYPE_STAMP9261_PC_EVB 2056 +#define MACH_TYPE_PELCO_ODYSSEUS 2057 +#define MACH_TYPE_TNY_A9260 2058 +#define MACH_TYPE_TNY_A9G20 2059 +#define MACH_TYPE_AESOP_MP2530F 2060 +#define MACH_TYPE_DX900 2061 +#define MACH_TYPE_CPODC2 2062 +#define MACH_TYPE_TILT_8925 2063 +#define MACH_TYPE_DAVINCI_DM357_EVM 2064 +#define MACH_TYPE_SWORDFISH 2065 +#define MACH_TYPE_CORVUS 2066 +#define MACH_TYPE_TAURUS 2067 +#define MACH_TYPE_AXM 2068 +#define MACH_TYPE_AXC 2069 +#define MACH_TYPE_BABY 2070 +#define MACH_TYPE_MP200 2071 +#define MACH_TYPE_PCM043 2072 +#define MACH_TYPE_HANLIN_V3C 2073 +#define MACH_TYPE_KBK9G20 2074 +#define MACH_TYPE_ADSTURBOG5 2075 +#define MACH_TYPE_AVENGER_LITE1 2076 +#define MACH_TYPE_SUC 2077 +#define MACH_TYPE_AT91SAM7S256 2078 +#define MACH_TYPE_MENDOZA 2079 +#define MACH_TYPE_KIRA 2080 +#define MACH_TYPE_MX1HBM 2081 +#define MACH_TYPE_QUATRO43XX 2082 +#define MACH_TYPE_QUATRO4230 2083 +#define MACH_TYPE_NSB400 2084 +#define MACH_TYPE_DRP255 2085 +#define MACH_TYPE_THOTH 2086 +#define MACH_TYPE_FIRESTONE 2087 +#define MACH_TYPE_ASUSP750 2088 +#define MACH_TYPE_CTERA_DL 2089 +#define MACH_TYPE_SOCR 2090 +#define MACH_TYPE_HTCOXYGEN 2091 +#define MACH_TYPE_HEROC 2092 +#define MACH_TYPE_ZENO6800 2093 +#define MACH_TYPE_SC2MCS 2094 +#define MACH_TYPE_GENE100 2095 +#define MACH_TYPE_AS353X 2096 +#define MACH_TYPE_SHEEVAPLUG 2097 +#define MACH_TYPE_AT91SAM9G20 2098 +#define MACH_TYPE_MV88F6192GTW_FE 2099 +#define MACH_TYPE_CC9200 2100 +#define MACH_TYPE_SM9200 2101 +#define MACH_TYPE_TP9200 2102 +#define MACH_TYPE_SNAPPERDV 2103 +#define MACH_TYPE_AVENGERS_LITE 2104 +#define MACH_TYPE_AVENGERS_LITE1 2105 +#define MACH_TYPE_OMAP3AXON 2106 +#define MACH_TYPE_MA8XX 2107 +#define MACH_TYPE_MP201EK 2108 +#define MACH_TYPE_DAVINCI_TUX 2109 +#define MACH_TYPE_MPA1600 2110 +#define MACH_TYPE_PELCO_TROY 2111 +#define MACH_TYPE_NSB667 2112 +#define MACH_TYPE_ROVERS5_4MPIX 2113 +#define MACH_TYPE_TWOCOM 2114 +#define MACH_TYPE_UBISYS_P9_RCU3R2 2115 +#define MACH_TYPE_HERO_ESPRESSO 2116 +#define MACH_TYPE_AFEUSB 2117 +#define MACH_TYPE_T830 2118 +#define MACH_TYPE_SPD8020_CC 2119 +#define MACH_TYPE_OM_3D7K 2120 +#define MACH_TYPE_PICOCOM2 2121 +#define MACH_TYPE_UWG4MX27 2122 +#define MACH_TYPE_UWG4MX31 2123 +#define MACH_TYPE_CHERRY 2124 +#define MACH_TYPE_MX51_BABBAGE 2125 +#define MACH_TYPE_S3C2440TURKIYE 2126 +#define MACH_TYPE_TX37 2127 +#define MACH_TYPE_SBC2800_9G20 2128 +#define MACH_TYPE_BENZGLB 2129 +#define MACH_TYPE_BENZTD 2130 +#define MACH_TYPE_CARTESIO_PLUS 2131 +#define MACH_TYPE_SOLRAD_G20 2132 +#define MACH_TYPE_MX27WALLACE 2133 +#define MACH_TYPE_FMZWEBMODUL 2134 +#define MACH_TYPE_RD78X00_MASA 2135 +#define MACH_TYPE_SMALLOGGER 2136 +#define MACH_TYPE_CCW9P9215 2137 +#define MACH_TYPE_DM355_LEOPARD 2138 +#define MACH_TYPE_TS219 2139 +#define MACH_TYPE_TNY_A9263 2140 +#define MACH_TYPE_APOLLO 2141 +#define MACH_TYPE_AT91CAP9STK 2142 +#define MACH_TYPE_SPC300 2143 +#define MACH_TYPE_EKO 2144 +#define MACH_TYPE_CCW9M2443 2145 +#define MACH_TYPE_CCW9M2443JS 2146 +#define MACH_TYPE_M2M_ROUTER_DEVICE 2147 +#define MACH_TYPE_STAR9104NAS 2148 +#define MACH_TYPE_PCA100 2149 +#define MACH_TYPE_Z3_DM365_MOD_01 2150 +#define MACH_TYPE_HIPOX 2151 +#define MACH_TYPE_OMAP3_PITEDS 2152 +#define MACH_TYPE_BM150R 2153 +#define MACH_TYPE_TBONE 2154 +#define MACH_TYPE_MERLIN 2155 +#define MACH_TYPE_FALCON 2156 +#define MACH_TYPE_DAVINCI_DA850_EVM 2157 +#define MACH_TYPE_S5P6440 2158 +#define MACH_TYPE_AT91SAM9G10EK 2159 +#define MACH_TYPE_OMAP_4430SDP 2160 +#define MACH_TYPE_LPC313X 2161 +#define MACH_TYPE_MAGX_ZN5 2162 +#define MACH_TYPE_MAGX_EM30 2163 +#define MACH_TYPE_MAGX_VE66 2164 +#define MACH_TYPE_MEESC 2165 +#define MACH_TYPE_OTC570 2166 +#define MACH_TYPE_BCU2412 2167 +#define MACH_TYPE_BEACON 2168 +#define MACH_TYPE_ACTIA_TGW 2169 +#define MACH_TYPE_E4430 2170 +#define MACH_TYPE_QL300 2171 +#define MACH_TYPE_BTMAVB101 2172 +#define MACH_TYPE_BTMAWB101 2173 +#define MACH_TYPE_SQ201 2174 +#define MACH_TYPE_QUATRO45XX 2175 +#define MACH_TYPE_OPENPAD 2176 +#define MACH_TYPE_TX25 2177 +#define MACH_TYPE_OMAP3_TORPEDO 2178 +#define MACH_TYPE_HTCRAPHAEL_K 2179 +#define MACH_TYPE_LAL43 2181 +#define MACH_TYPE_HTCRAPHAEL_CDMA500 2182 +#define MACH_TYPE_ANW6410 2183 +#define MACH_TYPE_HTCPROPHET 2185 +#define MACH_TYPE_CFA_10022 2186 +#define MACH_TYPE_IMX27_VISSTRIM_M10 2187 +#define MACH_TYPE_PX2IMX27 2188 +#define MACH_TYPE_STM3210E_EVAL 2189 +#define MACH_TYPE_DVS10 2190 +#define MACH_TYPE_PORTUXG20 2191 +#define MACH_TYPE_ARM_SPV 2192 +#define MACH_TYPE_SMDKC110 2193 +#define MACH_TYPE_CABESPRESSO 2194 +#define MACH_TYPE_HMC800 2195 +#define MACH_TYPE_SHOLES 2196 +#define MACH_TYPE_BTMXC31 2197 +#define MACH_TYPE_DT501 2198 +#define MACH_TYPE_KTX 2199 +#define MACH_TYPE_OMAP3517EVM 2200 +#define MACH_TYPE_NETSPACE_V2 2201 +#define MACH_TYPE_NETSPACE_MAX_V2 2202 +#define MACH_TYPE_D2NET_V2 2203 +#define MACH_TYPE_NET2BIG_V2 2204 +#define MACH_TYPE_NET4BIG_V2 2205 +#define MACH_TYPE_NET5BIG_V2 2206 +#define MACH_TYPE_ENDB2443 2207 +#define MACH_TYPE_INETSPACE_V2 2208 +#define MACH_TYPE_TROS 2209 +#define MACH_TYPE_PELCO_HOMER 2210 +#define MACH_TYPE_OFSP8 2211 +#define MACH_TYPE_AT91SAM9G45EKES 2212 +#define MACH_TYPE_GUF_CUPID 2213 +#define MACH_TYPE_EAB1R 2214 +#define MACH_TYPE_DESIREC 2215 +#define MACH_TYPE_CORDOBA 2216 +#define MACH_TYPE_IRVINE 2217 +#define MACH_TYPE_SFF772 2218 +#define MACH_TYPE_PELCO_MILANO 2219 +#define MACH_TYPE_PC7302 2220 +#define MACH_TYPE_BIP6000 2221 +#define MACH_TYPE_SILVERMOON 2222 +#define MACH_TYPE_VC0830 2223 +#define MACH_TYPE_DT430 2224 +#define MACH_TYPE_JI42PF 2225 +#define MACH_TYPE_GNET_KSM 2226 +#define MACH_TYPE_GNET_SGM 2227 +#define MACH_TYPE_GNET_SGR 2228 +#define MACH_TYPE_OMAP3_ICETEKEVM 2229 +#define MACH_TYPE_PNP 2230 +#define MACH_TYPE_CTERA_2BAY_K 2231 +#define MACH_TYPE_CTERA_2BAY_U 2232 +#define MACH_TYPE_SAS_C 2233 +#define MACH_TYPE_VMA2315 2234 +#define MACH_TYPE_VCS 2235 +#define MACH_TYPE_SPEAR600 2236 +#define MACH_TYPE_SPEAR300 2237 +#define MACH_TYPE_SPEAR1300 2238 +#define MACH_TYPE_LILLY1131 2239 +#define MACH_TYPE_ARVOO_AX301 2240 +#define MACH_TYPE_MAPPHONE 2241 +#define MACH_TYPE_LEGEND 2242 +#define MACH_TYPE_SALSA 2243 +#define MACH_TYPE_LOUNGE 2244 +#define MACH_TYPE_VISION 2245 +#define MACH_TYPE_VMB20 2246 +#define MACH_TYPE_HY2410 2247 +#define MACH_TYPE_HY9315 2248 +#define MACH_TYPE_BULLWINKLE 2249 +#define MACH_TYPE_ARM_ULTIMATOR2 2250 +#define MACH_TYPE_VS_V210 2252 +#define MACH_TYPE_VS_V212 2253 +#define MACH_TYPE_HMT 2254 +#define MACH_TYPE_SUEN3 2255 +#define MACH_TYPE_VESPER 2256 +#define MACH_TYPE_STR9 2257 +#define MACH_TYPE_OMAP3_WL_FF 2258 +#define MACH_TYPE_SIMCOM 2259 +#define MACH_TYPE_MCWEBIO 2260 +#define MACH_TYPE_OMAP3_PHRAZER 2261 +#define MACH_TYPE_DARWIN 2262 +#define MACH_TYPE_ORATISCOMU 2263 +#define MACH_TYPE_RTSBC20 2264 +#define MACH_TYPE_I780 2265 +#define MACH_TYPE_GEMINI324 2266 +#define MACH_TYPE_ORATISLAN 2267 +#define MACH_TYPE_ORATISALOG 2268 +#define MACH_TYPE_ORATISMADI 2269 +#define MACH_TYPE_ORATISOT16 2270 +#define MACH_TYPE_ORATISDESK 2271 +#define MACH_TYPE_VEXPRESS 2272 +#define MACH_TYPE_SINTEXO 2273 +#define MACH_TYPE_CM3389 2274 +#define MACH_TYPE_OMAP3_CIO 2275 +#define MACH_TYPE_SGH_I900 2276 +#define MACH_TYPE_BST100 2277 +#define MACH_TYPE_PASSION 2278 +#define MACH_TYPE_INDESIGN_AT91SAM 2279 +#define MACH_TYPE_C4_BADGER 2280 +#define MACH_TYPE_C4_VIPER 2281 +#define MACH_TYPE_D2NET 2282 +#define MACH_TYPE_BIGDISK 2283 +#define MACH_TYPE_NOTALVISION 2284 +#define MACH_TYPE_OMAP3_KBOC 2285 +#define MACH_TYPE_CYCLONE 2286 +#define MACH_TYPE_NINJA 2287 +#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 +#define MACH_TYPE_BCMRING 2289 +#define MACH_TYPE_RESOL_DL2 2290 +#define MACH_TYPE_IFOSW 2291 +#define MACH_TYPE_HTCRHODIUM 2292 +#define MACH_TYPE_HTCTOPAZ 2293 +#define MACH_TYPE_MATRIX504 2294 +#define MACH_TYPE_MRFSA 2295 +#define MACH_TYPE_SC_P270 2296 +#define MACH_TYPE_ATLAS5_EVB 2297 +#define MACH_TYPE_PELCO_LOBOX 2298 +#define MACH_TYPE_DILAX_PCU200 2299 +#define MACH_TYPE_LEONARDO 2300 +#define MACH_TYPE_ZORAN_APPROACH7 2301 +#define MACH_TYPE_DP6XX 2302 +#define MACH_TYPE_BCM2153_VESPER 2303 +#define MACH_TYPE_MAHIMAHI 2304 +#define MACH_TYPE_CLICKC 2305 +#define MACH_TYPE_ZB_GATEWAY 2306 +#define MACH_TYPE_TAZCARD 2307 +#define MACH_TYPE_TAZDEV 2308 +#define MACH_TYPE_ANNAX_CB_ARM 2309 +#define MACH_TYPE_ANNAX_DM3 2310 +#define MACH_TYPE_CEREBRIC 2311 +#define MACH_TYPE_ORCA 2312 +#define MACH_TYPE_PC9260 2313 +#define MACH_TYPE_EMS285A 2314 +#define MACH_TYPE_GEC2410 2315 +#define MACH_TYPE_GEC2440 2316 +#define MACH_TYPE_ARCH_MW903 2317 +#define MACH_TYPE_MW2440 2318 +#define MACH_TYPE_ECAC2378 2319 +#define MACH_TYPE_TAZKIOSK 2320 +#define MACH_TYPE_WHITERABBIT_MCH 2321 +#define MACH_TYPE_SBOX9263 2322 +#define MACH_TYPE_OREO 2323 +#define MACH_TYPE_SMDK6442 2324 +#define MACH_TYPE_OPENRD_BASE 2325 +#define MACH_TYPE_INCREDIBLE 2326 +#define MACH_TYPE_INCREDIBLEC 2327 +#define MACH_TYPE_HEROCT 2328 +#define MACH_TYPE_MMNET1000 2329 +#define MACH_TYPE_DEVKIT8000 2330 +#define MACH_TYPE_DEVKIT9000 2331 +#define MACH_TYPE_MX31TXTR 2332 +#define MACH_TYPE_U380 2333 +#define MACH_TYPE_HUALU_BOARD 2334 +#define MACH_TYPE_NPCMX50 2335 +#define MACH_TYPE_MX51_LANGE51 2336 +#define MACH_TYPE_MX51_LANGE52 2337 +#define MACH_TYPE_RIOM 2338 +#define MACH_TYPE_COMCAS 2339 +#define MACH_TYPE_WSI_MX27 2340 +#define MACH_TYPE_CM_T35 2341 +#define MACH_TYPE_NET2BIG 2342 +#define MACH_TYPE_MOTOROLA_A1600 2343 +#define MACH_TYPE_IGEP0020 2344 +#define MACH_TYPE_IGEP0010 2345 +#define MACH_TYPE_MV6281GTWGE2 2346 +#define MACH_TYPE_SCAT100 2347 +#define MACH_TYPE_SANMINA 2348 +#define MACH_TYPE_MOMENTO 2349 +#define MACH_TYPE_NUC9XX 2350 +#define MACH_TYPE_NUC910EVB 2351 +#define MACH_TYPE_NUC920EVB 2352 +#define MACH_TYPE_NUC950EVB 2353 +#define MACH_TYPE_NUC945EVB 2354 +#define MACH_TYPE_NUC960EVB 2355 +#define MACH_TYPE_NUC932EVB 2356 +#define MACH_TYPE_NUC900 2357 +#define MACH_TYPE_SD1SOC 2358 +#define MACH_TYPE_LN2440BC 2359 +#define MACH_TYPE_RSBC 2360 +#define MACH_TYPE_OPENRD_CLIENT 2361 +#define MACH_TYPE_HPIPAQ11X 2362 +#define MACH_TYPE_WAYLAND 2363 +#define MACH_TYPE_ACNBSX102 2364 +#define MACH_TYPE_HWAT91 2365 +#define MACH_TYPE_AT91SAM9263CS 2366 +#define MACH_TYPE_CSB732 2367 +#define MACH_TYPE_U8500 2368 +#define MACH_TYPE_HUQIU 2369 +#define MACH_TYPE_MX51_KUNLUN 2370 +#define MACH_TYPE_PMT1G 2371 +#define MACH_TYPE_HTCELF 2372 +#define MACH_TYPE_ARMADILLO420 2373 +#define MACH_TYPE_ARMADILLO440 2374 +#define MACH_TYPE_U_CHIP_DUAL_ARM 2375 +#define MACH_TYPE_CSR_BDB3 2376 +#define MACH_TYPE_DOLBY_CAT1018 2377 +#define MACH_TYPE_HY9307 2378 +#define MACH_TYPE_A_ES 2379 +#define MACH_TYPE_DAVINCI_IRIF 2380 +#define MACH_TYPE_AGAMA9263 2381 +#define MACH_TYPE_MARVELL_JASPER 2382 +#define MACH_TYPE_FLINT 2383 +#define MACH_TYPE_TAVOREVB3 2384 +#define MACH_TYPE_SCH_M490 2386 +#define MACH_TYPE_RBL01 2387 +#define MACH_TYPE_OMNIFI 2388 +#define MACH_TYPE_OTAVALO 2389 +#define MACH_TYPE_SIENNA 2390 +#define MACH_TYPE_HTC_EXCALIBUR_S620 2391 +#define MACH_TYPE_HTC_OPAL 2392 +#define MACH_TYPE_TOUCHBOOK 2393 +#define MACH_TYPE_LATTE 2394 +#define MACH_TYPE_XA200 2395 +#define MACH_TYPE_NIMROD 2396 +#define MACH_TYPE_CC9P9215_3G 2397 +#define MACH_TYPE_CC9P9215_3GJS 2398 +#define MACH_TYPE_TK71 2399 +#define MACH_TYPE_COMHAM3525 2400 +#define MACH_TYPE_MX31EREBUS 2401 +#define MACH_TYPE_MCARDMX27 2402 +#define MACH_TYPE_PARADISE 2403 +#define MACH_TYPE_TIDE 2404 +#define MACH_TYPE_WZL2440 2405 +#define MACH_TYPE_SDRDEMO 2406 +#define MACH_TYPE_ETHERCAN2 2407 +#define MACH_TYPE_ECMIMG20 2408 +#define MACH_TYPE_OMAP_DRAGON 2409 +#define MACH_TYPE_HALO 2410 +#define MACH_TYPE_HUANGSHAN 2411 +#define MACH_TYPE_VL_MA2SC 2412 +#define MACH_TYPE_RAUMFELD_RC 2413 +#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 +#define MACH_TYPE_RAUMFELD_SPEAKER 2415 +#define MACH_TYPE_MULTIBUS_MASTER 2416 +#define MACH_TYPE_MULTIBUS_PBK 2417 +#define MACH_TYPE_TNETV107X 2418 +#define MACH_TYPE_SNAKE 2419 +#define MACH_TYPE_CWMX27 2420 +#define MACH_TYPE_SCH_M480 2421 +#define MACH_TYPE_PLATYPUS 2422 +#define MACH_TYPE_PSS2 2423 +#define MACH_TYPE_DAVINCI_APM150 2424 +#define MACH_TYPE_STR9100 2425 +#define MACH_TYPE_NET5BIG 2426 +#define MACH_TYPE_SEABED9263 2427 +#define MACH_TYPE_MX51_M2ID 2428 +#define MACH_TYPE_OCTVOCPLUS_EB 2429 +#define MACH_TYPE_KLK_FIREFOX 2430 +#define MACH_TYPE_KLK_WIRMA_MODULE 2431 +#define MACH_TYPE_KLK_WIRMA_MMI 2432 +#define MACH_TYPE_SUPERSONIC 2433 +#define MACH_TYPE_LIBERTY 2434 +#define MACH_TYPE_MH355 2435 +#define MACH_TYPE_PC7802 2436 +#define MACH_TYPE_GNET_SGC 2437 +#define MACH_TYPE_EINSTEIN15 2438 +#define MACH_TYPE_CMPD 2439 +#define MACH_TYPE_DAVINCI_HASE1 2440 +#define MACH_TYPE_LGEINCITEPHONE 2441 +#define MACH_TYPE_EA313X 2442 +#define MACH_TYPE_FWBD_39064 2443 +#define MACH_TYPE_FWBD_390128 2444 +#define MACH_TYPE_PELCO_MOE 2445 +#define MACH_TYPE_MINIMIX27 2446 +#define MACH_TYPE_OMAP3_THUNDER 2447 +#define MACH_TYPE_PASSIONC 2448 +#define MACH_TYPE_MX27AMATA 2449 +#define MACH_TYPE_BGAT1 2450 +#define MACH_TYPE_BUZZ 2451 +#define MACH_TYPE_MB9G20 2452 +#define MACH_TYPE_YUSHAN 2453 +#define MACH_TYPE_LIZARD 2454 +#define MACH_TYPE_OMAP3POLYCOM 2455 +#define MACH_TYPE_SMDKV210 2456 +#define MACH_TYPE_BRAVO 2457 +#define MACH_TYPE_SIOGENTOO1 2458 +#define MACH_TYPE_SIOGENTOO2 2459 +#define MACH_TYPE_SM3K 2460 +#define MACH_TYPE_ACER_TEMPO_F900 2461 +#define MACH_TYPE_SST61VC010_DEV 2462 +#define MACH_TYPE_GLITTERTIND 2463 +#define MACH_TYPE_OMAP_ZOOM3 2464 +#define MACH_TYPE_OMAP_3630SDP 2465 +#define MACH_TYPE_CYBOOK2440 2466 +#define MACH_TYPE_TORINO_S 2467 +#define MACH_TYPE_HAVANA 2468 +#define MACH_TYPE_BEAUMONT_11 2469 +#define MACH_TYPE_VANGUARD 2470 +#define MACH_TYPE_S5PC110_DRACO 2471 +#define MACH_TYPE_CARTESIO_TWO 2472 +#define MACH_TYPE_ASTER 2473 +#define MACH_TYPE_VOGUESV210 2474 +#define MACH_TYPE_ACM500X 2475 +#define MACH_TYPE_KM9260 2476 +#define MACH_TYPE_NIDEFLEXG1 2477 +#define MACH_TYPE_CTERA_PLUG_IO 2478 +#define MACH_TYPE_SMARTQ7 2479 +#define MACH_TYPE_AT91SAM9G10EK2 2480 +#define MACH_TYPE_ASUSP527 2481 +#define MACH_TYPE_AT91SAM9G20MPM2 2482 +#define MACH_TYPE_TOPASA900 2483 +#define MACH_TYPE_ELECTRUM_100 2484 +#define MACH_TYPE_MX51GRB 2485 +#define MACH_TYPE_XEA300 2486 +#define MACH_TYPE_HTCSTARTREK 2487 +#define MACH_TYPE_LIMA 2488 +#define MACH_TYPE_CSB740 2489 +#define MACH_TYPE_USB_S8815 2490 +#define MACH_TYPE_WATSON_EFM_PLUGIN 2491 +#define MACH_TYPE_MILKYWAY 2492 +#define MACH_TYPE_G4EVM 2493 +#define MACH_TYPE_PICOMOD6 2494 +#define MACH_TYPE_OMAPL138_HAWKBOARD 2495 +#define MACH_TYPE_IP6000 2496 +#define MACH_TYPE_IP6010 2497 +#define MACH_TYPE_UTM400 2498 +#define MACH_TYPE_OMAP3_ZYBEX 2499 +#define MACH_TYPE_WIRELESS_SPACE 2500 +#define MACH_TYPE_SX560 2501 +#define MACH_TYPE_TS41X 2502 +#define MACH_TYPE_ELPHEL10373 2503 +#define MACH_TYPE_RHOBOT 2504 +#define MACH_TYPE_MX51_REFRESH 2505 +#define MACH_TYPE_LS9260 2506 +#define MACH_TYPE_SHANK 2507 +#define MACH_TYPE_QSD8X50_ST1 2508 +#define MACH_TYPE_AT91SAM9M10EKES 2509 +#define MACH_TYPE_HIRAM 2510 +#define MACH_TYPE_PHY3250 2511 +#define MACH_TYPE_EA3250 2512 +#define MACH_TYPE_FDI3250 2513 +#define MACH_TYPE_WHITESTONE 2514 +#define MACH_TYPE_AT91SAM9263NIT 2515 +#define MACH_TYPE_CCMX51 2516 +#define MACH_TYPE_CCMX51JS 2517 +#define MACH_TYPE_CCWMX51 2518 +#define MACH_TYPE_CCWMX51JS 2519 +#define MACH_TYPE_MINI6410 2520 +#define MACH_TYPE_TINY6410 2521 +#define MACH_TYPE_NANO6410 2522 +#define MACH_TYPE_AT572D940HFNLDB 2523 +#define MACH_TYPE_HTCLEO 2524 +#define MACH_TYPE_AVP13 2525 +#define MACH_TYPE_XXSVIDEOD 2526 +#define MACH_TYPE_VPNEXT 2527 +#define MACH_TYPE_SWARCO_ITC3 2528 +#define MACH_TYPE_TX51 2529 +#define MACH_TYPE_DOLBY_CAT1021 2530 +#define MACH_TYPE_MX28EVK 2531 +#define MACH_TYPE_PHOENIX260 2532 +#define MACH_TYPE_UVACA_STORK 2533 +#define MACH_TYPE_SMARTQ5 2534 +#define MACH_TYPE_ALL3078 2535 +#define MACH_TYPE_CTERA_2BAY_DS 2536 +#define MACH_TYPE_SIOGENTOO3 2537 +#define MACH_TYPE_EPB5000 2538 +#define MACH_TYPE_HY9263 2539 +#define MACH_TYPE_ACER_TEMPO_M900 2540 +#define MACH_TYPE_ACER_TEMPO_DX900 2541 +#define MACH_TYPE_ACER_TEMPO_X960 2542 +#define MACH_TYPE_ACER_ETEN_V900 2543 +#define MACH_TYPE_ACER_ETEN_X900 2544 +#define MACH_TYPE_BONNELL 2545 +#define MACH_TYPE_OHT_MX27 2546 +#define MACH_TYPE_HTCQUARTZ 2547 +#define MACH_TYPE_DAVINCI_DM6467TEVM 2548 +#define MACH_TYPE_C3AX03 2549 +#define MACH_TYPE_MXT_TD60 2550 +#define MACH_TYPE_ESYX 2551 +#define MACH_TYPE_DOVE_DB2 2552 +#define MACH_TYPE_BULLDOG 2553 +#define MACH_TYPE_DERELL_ME2000 2554 +#define MACH_TYPE_BCMRING_BASE 2555 +#define MACH_TYPE_BCMRING_EVM 2556 +#define MACH_TYPE_BCMRING_EVM_JAZZ 2557 +#define MACH_TYPE_BCMRING_SP 2558 +#define MACH_TYPE_BCMRING_SV 2559 +#define MACH_TYPE_BCMRING_SV_JAZZ 2560 +#define MACH_TYPE_BCMRING_TABLET 2561 +#define MACH_TYPE_BCMRING_VP 2562 +#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563 +#define MACH_TYPE_BCMRING_SP_WQVGA 2564 +#define MACH_TYPE_BCMRING_CUSTOM 2565 +#define MACH_TYPE_ACER_S200 2566 +#define MACH_TYPE_BT270 2567 +#define MACH_TYPE_ISEO 2568 +#define MACH_TYPE_CEZANNE 2569 +#define MACH_TYPE_LUCCA 2570 +#define MACH_TYPE_SUPERSMART 2571 +#define MACH_TYPE_CS_MISANO 2572 +#define MACH_TYPE_MAGNOLIA2 2573 +#define MACH_TYPE_EMXX 2574 +#define MACH_TYPE_OUTLAW 2575 +#define MACH_TYPE_RIOT_BEI2 2576 +#define MACH_TYPE_RIOT_VOX 2577 +#define MACH_TYPE_RIOT_X37 2578 +#define MACH_TYPE_MEGA25MX 2579 +#define MACH_TYPE_BENZINA2 2580 +#define MACH_TYPE_IGNITE 2581 +#define MACH_TYPE_FOGGIA 2582 +#define MACH_TYPE_AREZZO 2583 +#define MACH_TYPE_LEICA_SKYWALKER 2584 +#define MACH_TYPE_JACINTO2_JAMR 2585 +#define MACH_TYPE_GTS_NOVA 2586 +#define MACH_TYPE_P3600 2587 +#define MACH_TYPE_DLT2 2588 +#define MACH_TYPE_DF3120 2589 +#define MACH_TYPE_ECUCORE_9G20 2590 +#define MACH_TYPE_NAUTEL_LPC3240 2591 +#define MACH_TYPE_GLACIER 2592 +#define MACH_TYPE_PHRAZER_BULLDOG 2593 +#define MACH_TYPE_OMAP3_BULLDOG 2594 +#define MACH_TYPE_PCA101 2595 +#define MACH_TYPE_BUZZC 2596 +#define MACH_TYPE_SASIE2 2597 +#define MACH_TYPE_DAVINCI_CIO 2598 +#define MACH_TYPE_SMARTMETER_DL 2599 +#define MACH_TYPE_WZL6410 2600 +#define MACH_TYPE_WZL6410M 2601 +#define MACH_TYPE_WZL6410F 2602 +#define MACH_TYPE_WZL6410I 2603 +#define MACH_TYPE_SPACECOM1 2604 +#define MACH_TYPE_PINGU920 2605 +#define MACH_TYPE_BRAVOC 2606 +#define MACH_TYPE_CYBO2440 2607 +#define MACH_TYPE_VDSSW 2608 +#define MACH_TYPE_ROMULUS 2609 +#define MACH_TYPE_OMAP_MAGIC 2610 +#define MACH_TYPE_ELTD100 2611 +#define MACH_TYPE_CAPC7117 2612 +#define MACH_TYPE_SWAN 2613 +#define MACH_TYPE_VEU 2614 +#define MACH_TYPE_RM2 2615 +#define MACH_TYPE_TT2100 2616 +#define MACH_TYPE_VENICE 2617 +#define MACH_TYPE_PC7323 2618 +#define MACH_TYPE_MASP 2619 +#define MACH_TYPE_FUJITSU_TVSTBSOC 2620 +#define MACH_TYPE_FUJITSU_TVSTBSOC1 2621 +#define MACH_TYPE_LEXIKON 2622 +#define MACH_TYPE_MINI2440V2 2623 +#define MACH_TYPE_ICONTROL 2624 +#define MACH_TYPE_SHEEVAD 2625 +#define MACH_TYPE_QSD8X50A_ST1_1 2626 +#define MACH_TYPE_QSD8X50A_ST1_5 2627 +#define MACH_TYPE_BEE 2628 +#define MACH_TYPE_MX23EVK 2629 +#define MACH_TYPE_AP4EVB 2630 +#define MACH_TYPE_STOCKHOLM 2631 +#define MACH_TYPE_LPC_H3131 2632 +#define MACH_TYPE_STINGRAY 2633 +#define MACH_TYPE_KRAKEN 2634 +#define MACH_TYPE_GW2388 2635 +#define MACH_TYPE_JADECPU 2636 +#define MACH_TYPE_CARLISLE 2637 +#define MACH_TYPE_LUX_SFT9 2638 +#define MACH_TYPE_NEMID_TB 2639 +#define MACH_TYPE_TERRIER 2640 +#define MACH_TYPE_TURBOT 2641 +#define MACH_TYPE_SANDDAB 2642 +#define MACH_TYPE_MX35_CICADA 2643 +#define MACH_TYPE_GHI2703D 2644 +#define MACH_TYPE_LUX_SFX9 2645 +#define MACH_TYPE_LUX_SF9G 2646 +#define MACH_TYPE_LUX_EDK9 2647 +#define MACH_TYPE_HW90240 2648 +#define MACH_TYPE_DM365_LEOPARD 2649 +#define MACH_TYPE_MITYOMAPL138 2650 +#define MACH_TYPE_SCAT110 2651 +#define MACH_TYPE_ACER_A1 2652 +#define MACH_TYPE_CMCONTROL 2653 +#define MACH_TYPE_PELCO_LAMAR 2654 +#define MACH_TYPE_RFP43 2655 +#define MACH_TYPE_SK86R0301 2656 +#define MACH_TYPE_CTPXA 2657 +#define MACH_TYPE_EPB_ARM9_A 2658 +#define MACH_TYPE_GURUPLUG 2659 +#define MACH_TYPE_SPEAR310 2660 +#define MACH_TYPE_SPEAR320 2661 +#define MACH_TYPE_ROBOTX 2662 +#define MACH_TYPE_LSXHL 2663 +#define MACH_TYPE_SMARTLITE 2664 +#define MACH_TYPE_CWS2 2665 +#define MACH_TYPE_M619 2666 +#define MACH_TYPE_SMARTVIEW 2667 +#define MACH_TYPE_LSA_SALSA 2668 +#define MACH_TYPE_KIZBOX 2669 +#define MACH_TYPE_HTCCHARMER 2670 +#define MACH_TYPE_GUF_NESO_LT 2671 +#define MACH_TYPE_PM9G45 2672 +#define MACH_TYPE_HTCPANTHER 2673 +#define MACH_TYPE_HTCPANTHER_CDMA 2674 +#define MACH_TYPE_REB01 2675 +#define MACH_TYPE_AQUILA 2676 +#define MACH_TYPE_SPARK_SLS_HW2 2677 +#define MACH_TYPE_ESATA_SHEEVAPLUG 2678 +#define MACH_TYPE_MSM7X30_SURF 2679 +#define MACH_TYPE_MICRO2440 2680 +#define MACH_TYPE_AM2440 2681 +#define MACH_TYPE_TQ2440 2682 +#define MACH_TYPE_LPC2478OEM 2683 +#define MACH_TYPE_AK880X 2684 +#define MACH_TYPE_COBRA3530 2685 +#define MACH_TYPE_PMPPB 2686 +#define MACH_TYPE_U6715 2687 +#define MACH_TYPE_AXAR1500_SENDER 2688 +#define MACH_TYPE_G30_DVB 2689 +#define MACH_TYPE_VC088X 2690 +#define MACH_TYPE_MIOA702 2691 +#define MACH_TYPE_HPMIN 2692 +#define MACH_TYPE_AK880XAK 2693 +#define MACH_TYPE_ARM926TOMAP850 2694 +#define MACH_TYPE_LKEVM 2695 +#define MACH_TYPE_MW6410 2696 +#define MACH_TYPE_TERASTATION_WXL 2697 +#define MACH_TYPE_CPU8000E 2698 +#define MACH_TYPE_CATANIA 2699 +#define MACH_TYPE_TOKYO 2700 +#define MACH_TYPE_MSM7201A_SURF 2701 +#define MACH_TYPE_MSM7201A_FFA 2702 +#define MACH_TYPE_MSM7X25_SURF 2703 +#define MACH_TYPE_MSM7X25_FFA 2704 +#define MACH_TYPE_MSM7X27_SURF 2705 +#define MACH_TYPE_MSM7X27_FFA 2706 +#define MACH_TYPE_MSM7X30_FFA 2707 +#define MACH_TYPE_QSD8X50_SURF 2708 +#define MACH_TYPE_QSD8X50_COMET 2709 +#define MACH_TYPE_QSD8X50_FFA 2710 +#define MACH_TYPE_QSD8X50A_SURF 2711 +#define MACH_TYPE_QSD8X50A_FFA 2712 +#define MACH_TYPE_ADX_XGCP10 2713 +#define MACH_TYPE_MCGWUMTS2A 2714 +#define MACH_TYPE_MOBIKT 2715 +#define MACH_TYPE_MX53_EVK 2716 +#define MACH_TYPE_IGEP0030 2717 +#define MACH_TYPE_AXELL_H40_H50_CTRL 2718 +#define MACH_TYPE_DTCOMMOD 2719 +#define MACH_TYPE_GOULD 2720 +#define MACH_TYPE_SIBERIA 2721 +#define MACH_TYPE_SBC3530 2722 +#define MACH_TYPE_QARM 2723 +#define MACH_TYPE_MIPS 2724 +#define MACH_TYPE_MX27GRB 2725 +#define MACH_TYPE_SBC8100 2726 +#define MACH_TYPE_SAARB 2727 +#define MACH_TYPE_OMAP3MINI 2728 +#define MACH_TYPE_CNMBOOK7SE 2729 +#define MACH_TYPE_CATAN 2730 +#define MACH_TYPE_HARMONY 2731 +#define MACH_TYPE_TONGA 2732 +#define MACH_TYPE_CYBOOK_ORIZON 2733 +#define MACH_TYPE_HTCRHODIUMCDMA 2734 +#define MACH_TYPE_EPC_G45 2735 +#define MACH_TYPE_EPC_LPC3250 2736 +#define MACH_TYPE_MXC91341EVB 2737 +#define MACH_TYPE_RTW1000 2738 +#define MACH_TYPE_BOBCAT 2739 +#define MACH_TYPE_TRIZEPS6 2740 +#define MACH_TYPE_MSM7X30_FLUID 2741 +#define MACH_TYPE_NEDAP9263 2742 +#define MACH_TYPE_NETGEAR_MS2110 2743 +#define MACH_TYPE_BMX 2744 +#define MACH_TYPE_NETSTREAM 2745 +#define MACH_TYPE_VPNEXT_RCU 2746 +#define MACH_TYPE_VPNEXT_MPU 2747 +#define MACH_TYPE_BCMRING_TABLET_V1 2748 +#define MACH_TYPE_SGARM10 2749 +#define MACH_TYPE_CM_T3517 2750 +#define MACH_TYPE_OMAP3_CPS 2751 +#define MACH_TYPE_AXAR1500_RECEIVER 2752 +#define MACH_TYPE_WBD222 2753 +#define MACH_TYPE_MT65XX 2754 +#define MACH_TYPE_MSM8X60_SURF 2755 +#define MACH_TYPE_MSM8X60_SIM 2756 +#define MACH_TYPE_VMC300 2757 +#define MACH_TYPE_TCC8000_SDK 2758 +#define MACH_TYPE_NANOS 2759 +#define MACH_TYPE_STAMP9G10 2760 +#define MACH_TYPE_STAMP9G45 2761 +#define MACH_TYPE_H6053 2762 +#define MACH_TYPE_SMINT01 2763 +#define MACH_TYPE_PRTLVT2 2764 +#define MACH_TYPE_AP420 2765 +#define MACH_TYPE_HTCSHIFT 2766 +#define MACH_TYPE_DAVINCI_DM365_FC 2767 +#define MACH_TYPE_MSM8X55_SURF 2768 +#define MACH_TYPE_MSM8X55_FFA 2769 +#define MACH_TYPE_ESL_VAMANA 2770 +#define MACH_TYPE_SBC35 2771 +#define MACH_TYPE_MPX6446 2772 +#define MACH_TYPE_OREO_CONTROLLER 2773 +#define MACH_TYPE_KOPIN_MODELS 2774 +#define MACH_TYPE_TTC_VISION2 2775 +#define MACH_TYPE_CNS3420VB 2776 +#define MACH_TYPE_LPC2 2777 +#define MACH_TYPE_OLYMPUS 2778 +#define MACH_TYPE_VORTEX 2779 +#define MACH_TYPE_S5PC200 2780 +#define MACH_TYPE_ECUCORE_9263 2781 +#define MACH_TYPE_SMDKC200 2782 +#define MACH_TYPE_EMSISO_SX27 2783 +#define MACH_TYPE_APX_SOM9G45_EK 2784 +#define MACH_TYPE_SONGSHAN 2785 +#define MACH_TYPE_TIANSHAN 2786 +#define MACH_TYPE_VPX500 2787 +#define MACH_TYPE_AM3517SAM 2788 +#define MACH_TYPE_SKAT91_SIM508 2789 +#define MACH_TYPE_SKAT91_S3E 2790 +#define MACH_TYPE_OMAP4_PANDA 2791 +#define MACH_TYPE_DF7220 2792 + +#ifdef CONFIG_ARCH_EBSA110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EBSA110 +# endif +# define machine_is_ebsa110() (machine_arch_type == MACH_TYPE_EBSA110) +#else +# define machine_is_ebsa110() (0) +#endif + +#ifdef CONFIG_ARCH_RPC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RISCPC +# endif +# define machine_is_riscpc() (machine_arch_type == MACH_TYPE_RISCPC) +#else +# define machine_is_riscpc() (0) +#endif + +#ifdef CONFIG_ARCH_NEXUSPCI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXUSPCI +# endif +# define machine_is_nexuspci() (machine_arch_type == MACH_TYPE_NEXUSPCI) +#else +# define machine_is_nexuspci() (0) +#endif + +#ifdef CONFIG_ARCH_EBSA285 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EBSA285 +# endif +# define machine_is_ebsa285() (machine_arch_type == MACH_TYPE_EBSA285) +#else +# define machine_is_ebsa285() (0) +#endif + +#ifdef CONFIG_ARCH_NETWINDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETWINDER +# endif +# define machine_is_netwinder() (machine_arch_type == MACH_TYPE_NETWINDER) +#else +# define machine_is_netwinder() (0) +#endif + +#ifdef CONFIG_ARCH_CATS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATS +# endif +# define machine_is_cats() (machine_arch_type == MACH_TYPE_CATS) +#else +# define machine_is_cats() (0) +#endif + +#ifdef CONFIG_ARCH_TBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TBOX +# endif +# define machine_is_tbox() (machine_arch_type == MACH_TYPE_TBOX) +#else +# define machine_is_tbox() (0) +#endif + +#ifdef CONFIG_ARCH_CO285 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CO285 +# endif +# define machine_is_co285() (machine_arch_type == MACH_TYPE_CO285) +#else +# define machine_is_co285() (0) +#endif + +#ifdef CONFIG_ARCH_CLPS7110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLPS7110 +# endif +# define machine_is_clps7110() (machine_arch_type == MACH_TYPE_CLPS7110) +#else +# define machine_is_clps7110() (0) +#endif + +#ifdef CONFIG_ARCH_ARC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCHIMEDES +# endif +# define machine_is_archimedes() (machine_arch_type == MACH_TYPE_ARCHIMEDES) +#else +# define machine_is_archimedes() (0) +#endif + +#ifdef CONFIG_ARCH_A5K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A5K +# endif +# define machine_is_a5k() (machine_arch_type == MACH_TYPE_A5K) +#else +# define machine_is_a5k() (0) +#endif + +#ifdef CONFIG_ARCH_ETOILE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETOILE +# endif +# define machine_is_etoile() (machine_arch_type == MACH_TYPE_ETOILE) +#else +# define machine_is_etoile() (0) +#endif + +#ifdef CONFIG_ARCH_LACIE_NAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LACIE_NAS +# endif +# define machine_is_lacie_nas() (machine_arch_type == MACH_TYPE_LACIE_NAS) +#else +# define machine_is_lacie_nas() (0) +#endif + +#ifdef CONFIG_ARCH_CLPS7500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLPS7500 +# endif +# define machine_is_clps7500() (machine_arch_type == MACH_TYPE_CLPS7500) +#else +# define machine_is_clps7500() (0) +#endif + +#ifdef CONFIG_ARCH_SHARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHARK +# endif +# define machine_is_shark() (machine_arch_type == MACH_TYPE_SHARK) +#else +# define machine_is_shark() (0) +#endif + +#ifdef CONFIG_SA1100_BRUTUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRUTUS +# endif +# define machine_is_brutus() (machine_arch_type == MACH_TYPE_BRUTUS) +#else +# define machine_is_brutus() (0) +#endif + +#ifdef CONFIG_ARCH_PERSONAL_SERVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PERSONAL_SERVER +# endif +# define machine_is_personal_server() (machine_arch_type == MACH_TYPE_PERSONAL_SERVER) +#else +# define machine_is_personal_server() (0) +#endif + +#ifdef CONFIG_SA1100_ITSY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ITSY +# endif +# define machine_is_itsy() (machine_arch_type == MACH_TYPE_ITSY) +#else +# define machine_is_itsy() (0) +#endif + +#ifdef CONFIG_ARCH_L7200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_L7200 +# endif +# define machine_is_l7200() (machine_arch_type == MACH_TYPE_L7200) +#else +# define machine_is_l7200() (0) +#endif + +#ifdef CONFIG_SA1100_PLEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLEB +# endif +# define machine_is_pleb() (machine_arch_type == MACH_TYPE_PLEB) +#else +# define machine_is_pleb() (0) +#endif + +#ifdef CONFIG_ARCH_INTEGRATOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INTEGRATOR +# endif +# define machine_is_integrator() (machine_arch_type == MACH_TYPE_INTEGRATOR) +#else +# define machine_is_integrator() (0) +#endif + +#ifdef CONFIG_SA1100_H3600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H3600 +# endif +# define machine_is_h3600() (machine_arch_type == MACH_TYPE_H3600) +#else +# define machine_is_h3600() (0) +#endif + +#ifdef CONFIG_ARCH_IXP1200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP1200 +# endif +# define machine_is_ixp1200() (machine_arch_type == MACH_TYPE_IXP1200) +#else +# define machine_is_ixp1200() (0) +#endif + +#ifdef CONFIG_ARCH_P720T +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P720T +# endif +# define machine_is_p720t() (machine_arch_type == MACH_TYPE_P720T) +#else +# define machine_is_p720t() (0) +#endif + +#ifdef CONFIG_SA1100_ASSABET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASSABET +# endif +# define machine_is_assabet() (machine_arch_type == MACH_TYPE_ASSABET) +#else +# define machine_is_assabet() (0) +#endif + +#ifdef CONFIG_SA1100_VICTOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VICTOR +# endif +# define machine_is_victor() (machine_arch_type == MACH_TYPE_VICTOR) +#else +# define machine_is_victor() (0) +#endif + +#ifdef CONFIG_SA1100_LART +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LART +# endif +# define machine_is_lart() (machine_arch_type == MACH_TYPE_LART) +#else +# define machine_is_lart() (0) +#endif + +#ifdef CONFIG_SA1100_RANGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RANGER +# endif +# define machine_is_ranger() (machine_arch_type == MACH_TYPE_RANGER) +#else +# define machine_is_ranger() (0) +#endif + +#ifdef CONFIG_SA1100_GRAPHICSCLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GRAPHICSCLIENT +# endif +# define machine_is_graphicsclient() (machine_arch_type == MACH_TYPE_GRAPHICSCLIENT) +#else +# define machine_is_graphicsclient() (0) +#endif + +#ifdef CONFIG_SA1100_XP860 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XP860 +# endif +# define machine_is_xp860() (machine_arch_type == MACH_TYPE_XP860) +#else +# define machine_is_xp860() (0) +#endif + +#ifdef CONFIG_SA1100_CERF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CERF +# endif +# define machine_is_cerf() (machine_arch_type == MACH_TYPE_CERF) +#else +# define machine_is_cerf() (0) +#endif + +#ifdef CONFIG_SA1100_NANOENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANOENGINE +# endif +# define machine_is_nanoengine() (machine_arch_type == MACH_TYPE_NANOENGINE) +#else +# define machine_is_nanoengine() (0) +#endif + +#ifdef CONFIG_SA1100_FPIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FPIC +# endif +# define machine_is_fpic() (machine_arch_type == MACH_TYPE_FPIC) +#else +# define machine_is_fpic() (0) +#endif + +#ifdef CONFIG_SA1100_EXTENEX1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXTENEX1 +# endif +# define machine_is_extenex1() (machine_arch_type == MACH_TYPE_EXTENEX1) +#else +# define machine_is_extenex1() (0) +#endif + +#ifdef CONFIG_SA1100_SHERMAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHERMAN +# endif +# define machine_is_sherman() (machine_arch_type == MACH_TYPE_SHERMAN) +#else +# define machine_is_sherman() (0) +#endif + +#ifdef CONFIG_SA1100_ACCELENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACCELENT_SA +# endif +# define machine_is_accelent_sa() (machine_arch_type == MACH_TYPE_ACCELENT_SA) +#else +# define machine_is_accelent_sa() (0) +#endif + +#ifdef CONFIG_ARCH_L7200_ACCELENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACCELENT_L7200 +# endif +# define machine_is_accelent_l7200() (machine_arch_type == MACH_TYPE_ACCELENT_L7200) +#else +# define machine_is_accelent_l7200() (0) +#endif + +#ifdef CONFIG_SA1100_NETPORT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETPORT +# endif +# define machine_is_netport() (machine_arch_type == MACH_TYPE_NETPORT) +#else +# define machine_is_netport() (0) +#endif + +#ifdef CONFIG_SA1100_PANGOLIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PANGOLIN +# endif +# define machine_is_pangolin() (machine_arch_type == MACH_TYPE_PANGOLIN) +#else +# define machine_is_pangolin() (0) +#endif + +#ifdef CONFIG_SA1100_YOPY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YOPY +# endif +# define machine_is_yopy() (machine_arch_type == MACH_TYPE_YOPY) +#else +# define machine_is_yopy() (0) +#endif + +#ifdef CONFIG_SA1100_COOLIDGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COOLIDGE +# endif +# define machine_is_coolidge() (machine_arch_type == MACH_TYPE_COOLIDGE) +#else +# define machine_is_coolidge() (0) +#endif + +#ifdef CONFIG_SA1100_HUW_WEBPANEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUW_WEBPANEL +# endif +# define machine_is_huw_webpanel() (machine_arch_type == MACH_TYPE_HUW_WEBPANEL) +#else +# define machine_is_huw_webpanel() (0) +#endif + +#ifdef CONFIG_ARCH_SPOTME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPOTME +# endif +# define machine_is_spotme() (machine_arch_type == MACH_TYPE_SPOTME) +#else +# define machine_is_spotme() (0) +#endif + +#ifdef CONFIG_ARCH_FREEBIRD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FREEBIRD +# endif +# define machine_is_freebird() (machine_arch_type == MACH_TYPE_FREEBIRD) +#else +# define machine_is_freebird() (0) +#endif + +#ifdef CONFIG_ARCH_TI925 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI925 +# endif +# define machine_is_ti925() (machine_arch_type == MACH_TYPE_TI925) +#else +# define machine_is_ti925() (0) +#endif + +#ifdef CONFIG_ARCH_RISCSTATION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RISCSTATION +# endif +# define machine_is_riscstation() (machine_arch_type == MACH_TYPE_RISCSTATION) +#else +# define machine_is_riscstation() (0) +#endif + +#ifdef CONFIG_SA1100_CAVY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAVY +# endif +# define machine_is_cavy() (machine_arch_type == MACH_TYPE_CAVY) +#else +# define machine_is_cavy() (0) +#endif + +#ifdef CONFIG_SA1100_JORNADA720 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JORNADA720 +# endif +# define machine_is_jornada720() (machine_arch_type == MACH_TYPE_JORNADA720) +#else +# define machine_is_jornada720() (0) +#endif + +#ifdef CONFIG_SA1100_OMNIMETER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMNIMETER +# endif +# define machine_is_omnimeter() (machine_arch_type == MACH_TYPE_OMNIMETER) +#else +# define machine_is_omnimeter() (0) +#endif + +#ifdef CONFIG_ARCH_EDB7211 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB7211 +# endif +# define machine_is_edb7211() (machine_arch_type == MACH_TYPE_EDB7211) +#else +# define machine_is_edb7211() (0) +#endif + +#ifdef CONFIG_SA1100_CITYGO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CITYGO +# endif +# define machine_is_citygo() (machine_arch_type == MACH_TYPE_CITYGO) +#else +# define machine_is_citygo() (0) +#endif + +#ifdef CONFIG_SA1100_PFS168 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PFS168 +# endif +# define machine_is_pfs168() (machine_arch_type == MACH_TYPE_PFS168) +#else +# define machine_is_pfs168() (0) +#endif + +#ifdef CONFIG_SA1100_SPOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPOT +# endif +# define machine_is_spot() (machine_arch_type == MACH_TYPE_SPOT) +#else +# define machine_is_spot() (0) +#endif + +#ifdef CONFIG_SA1100_FLEXANET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLEXANET +# endif +# define machine_is_flexanet() (machine_arch_type == MACH_TYPE_FLEXANET) +#else +# define machine_is_flexanet() (0) +#endif + +#ifdef CONFIG_ARCH_WEBPAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEBPAL +# endif +# define machine_is_webpal() (machine_arch_type == MACH_TYPE_WEBPAL) +#else +# define machine_is_webpal() (0) +#endif + +#ifdef CONFIG_SA1100_LINPDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINPDA +# endif +# define machine_is_linpda() (machine_arch_type == MACH_TYPE_LINPDA) +#else +# define machine_is_linpda() (0) +#endif + +#ifdef CONFIG_ARCH_ANAKIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANAKIN +# endif +# define machine_is_anakin() (machine_arch_type == MACH_TYPE_ANAKIN) +#else +# define machine_is_anakin() (0) +#endif + +#ifdef CONFIG_SA1100_MVI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MVI +# endif +# define machine_is_mvi() (machine_arch_type == MACH_TYPE_MVI) +#else +# define machine_is_mvi() (0) +#endif + +#ifdef CONFIG_SA1100_JUPITER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JUPITER +# endif +# define machine_is_jupiter() (machine_arch_type == MACH_TYPE_JUPITER) +#else +# define machine_is_jupiter() (0) +#endif + +#ifdef CONFIG_ARCH_PSIONW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PSIONW +# endif +# define machine_is_psionw() (machine_arch_type == MACH_TYPE_PSIONW) +#else +# define machine_is_psionw() (0) +#endif + +#ifdef CONFIG_SA1100_ALN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALN +# endif +# define machine_is_aln() (machine_arch_type == MACH_TYPE_ALN) +#else +# define machine_is_aln() (0) +#endif + +#ifdef CONFIG_ARCH_CAMELOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAMELOT +# endif +# define machine_is_epxa() (machine_arch_type == MACH_TYPE_CAMELOT) +#else +# define machine_is_epxa() (0) +#endif + +#ifdef CONFIG_SA1100_GDS2200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GDS2200 +# endif +# define machine_is_gds2200() (machine_arch_type == MACH_TYPE_GDS2200) +#else +# define machine_is_gds2200() (0) +#endif + +#ifdef CONFIG_SA1100_PSION_SERIES7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PSION_SERIES7 +# endif +# define machine_is_netbook() (machine_arch_type == MACH_TYPE_PSION_SERIES7) +#else +# define machine_is_netbook() (0) +#endif + +#ifdef CONFIG_SA1100_XFILE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XFILE +# endif +# define machine_is_xfile() (machine_arch_type == MACH_TYPE_XFILE) +#else +# define machine_is_xfile() (0) +#endif + +#ifdef CONFIG_ARCH_ACCELENT_EP9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACCELENT_EP9312 +# endif +# define machine_is_accelent_ep9312() (machine_arch_type == MACH_TYPE_ACCELENT_EP9312) +#else +# define machine_is_accelent_ep9312() (0) +#endif + +#ifdef CONFIG_ARCH_IC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IC200 +# endif +# define machine_is_ic200() (machine_arch_type == MACH_TYPE_IC200) +#else +# define machine_is_ic200() (0) +#endif + +#ifdef CONFIG_SA1100_CREDITLART +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CREDITLART +# endif +# define machine_is_creditlart() (machine_arch_type == MACH_TYPE_CREDITLART) +#else +# define machine_is_creditlart() (0) +#endif + +#ifdef CONFIG_SA1100_HTM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTM +# endif +# define machine_is_htm() (machine_arch_type == MACH_TYPE_HTM) +#else +# define machine_is_htm() (0) +#endif + +#ifdef CONFIG_ARCH_IQ80310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80310 +# endif +# define machine_is_iq80310() (machine_arch_type == MACH_TYPE_IQ80310) +#else +# define machine_is_iq80310() (0) +#endif + +#ifdef CONFIG_SA1100_FREEBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FREEBOT +# endif +# define machine_is_freebot() (machine_arch_type == MACH_TYPE_FREEBOT) +#else +# define machine_is_freebot() (0) +#endif + +#ifdef CONFIG_ARCH_ENTEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENTEL +# endif +# define machine_is_entel() (machine_arch_type == MACH_TYPE_ENTEL) +#else +# define machine_is_entel() (0) +#endif + +#ifdef CONFIG_ARCH_ENP3510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENP3510 +# endif +# define machine_is_enp3510() (machine_arch_type == MACH_TYPE_ENP3510) +#else +# define machine_is_enp3510() (0) +#endif + +#ifdef CONFIG_SA1100_TRIZEPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS +# endif +# define machine_is_trizeps() (machine_arch_type == MACH_TYPE_TRIZEPS) +#else +# define machine_is_trizeps() (0) +#endif + +#ifdef CONFIG_SA1100_NESA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NESA +# endif +# define machine_is_nesa() (machine_arch_type == MACH_TYPE_NESA) +#else +# define machine_is_nesa() (0) +#endif + +#ifdef CONFIG_ARCH_VENUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENUS +# endif +# define machine_is_venus() (machine_arch_type == MACH_TYPE_VENUS) +#else +# define machine_is_venus() (0) +#endif + +#ifdef CONFIG_ARCH_TARDIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TARDIS +# endif +# define machine_is_tardis() (machine_arch_type == MACH_TYPE_TARDIS) +#else +# define machine_is_tardis() (0) +#endif + +#ifdef CONFIG_ARCH_MERCURY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MERCURY +# endif +# define machine_is_mercury() (machine_arch_type == MACH_TYPE_MERCURY) +#else +# define machine_is_mercury() (0) +#endif + +#ifdef CONFIG_SA1100_EMPEG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMPEG +# endif +# define machine_is_empeg() (machine_arch_type == MACH_TYPE_EMPEG) +#else +# define machine_is_empeg() (0) +#endif + +#ifdef CONFIG_ARCH_I80200FCC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I80200FCC +# endif +# define machine_is_adi_evb() (machine_arch_type == MACH_TYPE_I80200FCC) +#else +# define machine_is_adi_evb() (0) +#endif + +#ifdef CONFIG_SA1100_ITT_CPB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ITT_CPB +# endif +# define machine_is_itt_cpb() (machine_arch_type == MACH_TYPE_ITT_CPB) +#else +# define machine_is_itt_cpb() (0) +#endif + +#ifdef CONFIG_SA1100_SVC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVC +# endif +# define machine_is_svc() (machine_arch_type == MACH_TYPE_SVC) +#else +# define machine_is_svc() (0) +#endif + +#ifdef CONFIG_SA1100_ALPHA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALPHA2 +# endif +# define machine_is_alpha2() (machine_arch_type == MACH_TYPE_ALPHA2) +#else +# define machine_is_alpha2() (0) +#endif + +#ifdef CONFIG_SA1100_ALPHA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALPHA1 +# endif +# define machine_is_alpha1() (machine_arch_type == MACH_TYPE_ALPHA1) +#else +# define machine_is_alpha1() (0) +#endif + +#ifdef CONFIG_ARCH_NETARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETARM +# endif +# define machine_is_netarm() (machine_arch_type == MACH_TYPE_NETARM) +#else +# define machine_is_netarm() (0) +#endif + +#ifdef CONFIG_SA1100_SIMPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMPAD +# endif +# define machine_is_simpad() (machine_arch_type == MACH_TYPE_SIMPAD) +#else +# define machine_is_simpad() (0) +#endif + +#ifdef CONFIG_ARCH_PDA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDA1 +# endif +# define machine_is_pda1() (machine_arch_type == MACH_TYPE_PDA1) +#else +# define machine_is_pda1() (0) +#endif + +#ifdef CONFIG_ARCH_LUBBOCK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUBBOCK +# endif +# define machine_is_lubbock() (machine_arch_type == MACH_TYPE_LUBBOCK) +#else +# define machine_is_lubbock() (0) +#endif + +#ifdef CONFIG_ARCH_ANIKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANIKO +# endif +# define machine_is_aniko() (machine_arch_type == MACH_TYPE_ANIKO) +#else +# define machine_is_aniko() (0) +#endif + +#ifdef CONFIG_ARCH_CLEP7212 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLEP7212 +# endif +# define machine_is_clep7212() (machine_arch_type == MACH_TYPE_CLEP7212) +#else +# define machine_is_clep7212() (0) +#endif + +#ifdef CONFIG_ARCH_CS89712 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS89712 +# endif +# define machine_is_cs89712() (machine_arch_type == MACH_TYPE_CS89712) +#else +# define machine_is_cs89712() (0) +#endif + +#ifdef CONFIG_SA1100_WEARARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEARARM +# endif +# define machine_is_weararm() (machine_arch_type == MACH_TYPE_WEARARM) +#else +# define machine_is_weararm() (0) +#endif + +#ifdef CONFIG_SA1100_POSSIO_PX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POSSIO_PX +# endif +# define machine_is_possio_px() (machine_arch_type == MACH_TYPE_POSSIO_PX) +#else +# define machine_is_possio_px() (0) +#endif + +#ifdef CONFIG_SA1100_SIDEARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIDEARM +# endif +# define machine_is_sidearm() (machine_arch_type == MACH_TYPE_SIDEARM) +#else +# define machine_is_sidearm() (0) +#endif + +#ifdef CONFIG_SA1100_STORK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STORK +# endif +# define machine_is_stork() (machine_arch_type == MACH_TYPE_STORK) +#else +# define machine_is_stork() (0) +#endif + +#ifdef CONFIG_SA1100_SHANNON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHANNON +# endif +# define machine_is_shannon() (machine_arch_type == MACH_TYPE_SHANNON) +#else +# define machine_is_shannon() (0) +#endif + +#ifdef CONFIG_ARCH_ACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACE +# endif +# define machine_is_ace() (machine_arch_type == MACH_TYPE_ACE) +#else +# define machine_is_ace() (0) +#endif + +#ifdef CONFIG_SA1100_BALLYARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BALLYARM +# endif +# define machine_is_ballyarm() (machine_arch_type == MACH_TYPE_BALLYARM) +#else +# define machine_is_ballyarm() (0) +#endif + +#ifdef CONFIG_SA1100_SIMPUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMPUTER +# endif +# define machine_is_simputer() (machine_arch_type == MACH_TYPE_SIMPUTER) +#else +# define machine_is_simputer() (0) +#endif + +#ifdef CONFIG_SA1100_NEXTERM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXTERM +# endif +# define machine_is_nexterm() (machine_arch_type == MACH_TYPE_NEXTERM) +#else +# define machine_is_nexterm() (0) +#endif + +#ifdef CONFIG_SA1100_SA1100_ELF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SA1100_ELF +# endif +# define machine_is_sa1100_elf() (machine_arch_type == MACH_TYPE_SA1100_ELF) +#else +# define machine_is_sa1100_elf() (0) +#endif + +#ifdef CONFIG_SA1100_GATOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GATOR +# endif +# define machine_is_gator() (machine_arch_type == MACH_TYPE_GATOR) +#else +# define machine_is_gator() (0) +#endif + +#ifdef CONFIG_ARCH_GRANITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GRANITE +# endif +# define machine_is_granite() (machine_arch_type == MACH_TYPE_GRANITE) +#else +# define machine_is_granite() (0) +#endif + +#ifdef CONFIG_SA1100_CONSUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CONSUS +# endif +# define machine_is_consus() (machine_arch_type == MACH_TYPE_CONSUS) +#else +# define machine_is_consus() (0) +#endif + +#ifdef CONFIG_ARCH_AAED2000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AAED2000 +# endif +# define machine_is_aaed2000() (machine_arch_type == MACH_TYPE_AAED2000) +#else +# define machine_is_aaed2000() (0) +#endif + +#ifdef CONFIG_ARCH_CDB89712 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CDB89712 +# endif +# define machine_is_cdb89712() (machine_arch_type == MACH_TYPE_CDB89712) +#else +# define machine_is_cdb89712() (0) +#endif + +#ifdef CONFIG_SA1100_GRAPHICSMASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GRAPHICSMASTER +# endif +# define machine_is_graphicsmaster() (machine_arch_type == MACH_TYPE_GRAPHICSMASTER) +#else +# define machine_is_graphicsmaster() (0) +#endif + +#ifdef CONFIG_SA1100_ADSBITSY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSY +# endif +# define machine_is_adsbitsy() (machine_arch_type == MACH_TYPE_ADSBITSY) +#else +# define machine_is_adsbitsy() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_IDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_IDP +# endif +# define machine_is_pxa_idp() (machine_arch_type == MACH_TYPE_PXA_IDP) +#else +# define machine_is_pxa_idp() (0) +#endif + +#ifdef CONFIG_ARCH_PLCE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLCE +# endif +# define machine_is_plce() (machine_arch_type == MACH_TYPE_PLCE) +#else +# define machine_is_plce() (0) +#endif + +#ifdef CONFIG_SA1100_PT_SYSTEM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PT_SYSTEM3 +# endif +# define machine_is_pt_system3() (machine_arch_type == MACH_TYPE_PT_SYSTEM3) +#else +# define machine_is_pt_system3() (0) +#endif + +#ifdef CONFIG_ARCH_MEDALB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEDALB +# endif +# define machine_is_murphy() (machine_arch_type == MACH_TYPE_MEDALB) +#else +# define machine_is_murphy() (0) +#endif + +#ifdef CONFIG_ARCH_EAGLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EAGLE +# endif +# define machine_is_eagle() (machine_arch_type == MACH_TYPE_EAGLE) +#else +# define machine_is_eagle() (0) +#endif + +#ifdef CONFIG_ARCH_DSC21 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSC21 +# endif +# define machine_is_dsc21() (machine_arch_type == MACH_TYPE_DSC21) +#else +# define machine_is_dsc21() (0) +#endif + +#ifdef CONFIG_ARCH_DSC24 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSC24 +# endif +# define machine_is_dsc24() (machine_arch_type == MACH_TYPE_DSC24) +#else +# define machine_is_dsc24() (0) +#endif + +#ifdef CONFIG_ARCH_TI5472 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI5472 +# endif +# define machine_is_ti5472() (machine_arch_type == MACH_TYPE_TI5472) +#else +# define machine_is_ti5472() (0) +#endif + +#ifdef CONFIG_ARCH_AUTCPU12 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUTCPU12 +# endif +# define machine_is_autcpu12() (machine_arch_type == MACH_TYPE_AUTCPU12) +#else +# define machine_is_autcpu12() (0) +#endif + +#ifdef CONFIG_ARCH_UENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UENGINE +# endif +# define machine_is_uengine() (machine_arch_type == MACH_TYPE_UENGINE) +#else +# define machine_is_uengine() (0) +#endif + +#ifdef CONFIG_SA1100_BLUESTEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUESTEM +# endif +# define machine_is_bluestem() (machine_arch_type == MACH_TYPE_BLUESTEM) +#else +# define machine_is_bluestem() (0) +#endif + +#ifdef CONFIG_ARCH_XINGU8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XINGU8 +# endif +# define machine_is_xingu8() (machine_arch_type == MACH_TYPE_XINGU8) +#else +# define machine_is_xingu8() (0) +#endif + +#ifdef CONFIG_ARCH_BUSHSTB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUSHSTB +# endif +# define machine_is_bushstb() (machine_arch_type == MACH_TYPE_BUSHSTB) +#else +# define machine_is_bushstb() (0) +#endif + +#ifdef CONFIG_SA1100_EPSILON1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPSILON1 +# endif +# define machine_is_epsilon1() (machine_arch_type == MACH_TYPE_EPSILON1) +#else +# define machine_is_epsilon1() (0) +#endif + +#ifdef CONFIG_SA1100_BALLOON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BALLOON +# endif +# define machine_is_balloon() (machine_arch_type == MACH_TYPE_BALLOON) +#else +# define machine_is_balloon() (0) +#endif + +#ifdef CONFIG_ARCH_PUPPY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PUPPY +# endif +# define machine_is_puppy() (machine_arch_type == MACH_TYPE_PUPPY) +#else +# define machine_is_puppy() (0) +#endif + +#ifdef CONFIG_SA1100_ELROY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELROY +# endif +# define machine_is_elroy() (machine_arch_type == MACH_TYPE_ELROY) +#else +# define machine_is_elroy() (0) +#endif + +#ifdef CONFIG_ARCH_GMS720 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GMS720 +# endif +# define machine_is_gms720() (machine_arch_type == MACH_TYPE_GMS720) +#else +# define machine_is_gms720() (0) +#endif + +#ifdef CONFIG_ARCH_S24X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S24X +# endif +# define machine_is_s24x() (machine_arch_type == MACH_TYPE_S24X) +#else +# define machine_is_s24x() (0) +#endif + +#ifdef CONFIG_ARCH_JTEL_CLEP7312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JTEL_CLEP7312 +# endif +# define machine_is_jtel_clep7312() (machine_arch_type == MACH_TYPE_JTEL_CLEP7312) +#else +# define machine_is_jtel_clep7312() (0) +#endif + +#ifdef CONFIG_ARCH_CX821XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CX821XX +# endif +# define machine_is_cx821xx() (machine_arch_type == MACH_TYPE_CX821XX) +#else +# define machine_is_cx821xx() (0) +#endif + +#ifdef CONFIG_ARCH_EDB7312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB7312 +# endif +# define machine_is_edb7312() (machine_arch_type == MACH_TYPE_EDB7312) +#else +# define machine_is_edb7312() (0) +#endif + +#ifdef CONFIG_SA1100_BSA1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSA1110 +# endif +# define machine_is_bsa1110() (machine_arch_type == MACH_TYPE_BSA1110) +#else +# define machine_is_bsa1110() (0) +#endif + +#ifdef CONFIG_ARCH_POWERPIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POWERPIN +# endif +# define machine_is_powerpin() (machine_arch_type == MACH_TYPE_POWERPIN) +#else +# define machine_is_powerpin() (0) +#endif + +#ifdef CONFIG_ARCH_OPENARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENARM +# endif +# define machine_is_openarm() (machine_arch_type == MACH_TYPE_OPENARM) +#else +# define machine_is_openarm() (0) +#endif + +#ifdef CONFIG_SA1100_WHITECHAPEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITECHAPEL +# endif +# define machine_is_whitechapel() (machine_arch_type == MACH_TYPE_WHITECHAPEL) +#else +# define machine_is_whitechapel() (0) +#endif + +#ifdef CONFIG_SA1100_H3100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H3100 +# endif +# define machine_is_h3100() (machine_arch_type == MACH_TYPE_H3100) +#else +# define machine_is_h3100() (0) +#endif + +#ifdef CONFIG_SA1100_H3800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H3800 +# endif +# define machine_is_h3800() (machine_arch_type == MACH_TYPE_H3800) +#else +# define machine_is_h3800() (0) +#endif + +#ifdef CONFIG_ARCH_BLUE_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUE_V1 +# endif +# define machine_is_blue_v1() (machine_arch_type == MACH_TYPE_BLUE_V1) +#else +# define machine_is_blue_v1() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_CERF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_CERF +# endif +# define machine_is_pxa_cerf() (machine_arch_type == MACH_TYPE_PXA_CERF) +#else +# define machine_is_pxa_cerf() (0) +#endif + +#ifdef CONFIG_ARCH_ARM7TEVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM7TEVB +# endif +# define machine_is_arm7tevb() (machine_arch_type == MACH_TYPE_ARM7TEVB) +#else +# define machine_is_arm7tevb() (0) +#endif + +#ifdef CONFIG_SA1100_D7400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D7400 +# endif +# define machine_is_d7400() (machine_arch_type == MACH_TYPE_D7400) +#else +# define machine_is_d7400() (0) +#endif + +#ifdef CONFIG_ARCH_PIRANHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PIRANHA +# endif +# define machine_is_piranha() (machine_arch_type == MACH_TYPE_PIRANHA) +#else +# define machine_is_piranha() (0) +#endif + +#ifdef CONFIG_SA1100_SBCAMELOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBCAMELOT +# endif +# define machine_is_sbcamelot() (machine_arch_type == MACH_TYPE_SBCAMELOT) +#else +# define machine_is_sbcamelot() (0) +#endif + +#ifdef CONFIG_SA1100_KINGS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KINGS +# endif +# define machine_is_kings() (machine_arch_type == MACH_TYPE_KINGS) +#else +# define machine_is_kings() (0) +#endif + +#ifdef CONFIG_ARCH_SMDK2400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2400 +# endif +# define machine_is_smdk2400() (machine_arch_type == MACH_TYPE_SMDK2400) +#else +# define machine_is_smdk2400() (0) +#endif + +#ifdef CONFIG_SA1100_COLLIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLLIE +# endif +# define machine_is_collie() (machine_arch_type == MACH_TYPE_COLLIE) +#else +# define machine_is_collie() (0) +#endif + +#ifdef CONFIG_ARCH_IDR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IDR +# endif +# define machine_is_idr() (machine_arch_type == MACH_TYPE_IDR) +#else +# define machine_is_idr() (0) +#endif + +#ifdef CONFIG_SA1100_BADGE4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BADGE4 +# endif +# define machine_is_badge4() (machine_arch_type == MACH_TYPE_BADGE4) +#else +# define machine_is_badge4() (0) +#endif + +#ifdef CONFIG_ARCH_WEBNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEBNET +# endif +# define machine_is_webnet() (machine_arch_type == MACH_TYPE_WEBNET) +#else +# define machine_is_webnet() (0) +#endif + +#ifdef CONFIG_SA1100_D7300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D7300 +# endif +# define machine_is_d7300() (machine_arch_type == MACH_TYPE_D7300) +#else +# define machine_is_d7300() (0) +#endif + +#ifdef CONFIG_SA1100_CEP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEP +# endif +# define machine_is_cep() (machine_arch_type == MACH_TYPE_CEP) +#else +# define machine_is_cep() (0) +#endif + +#ifdef CONFIG_ARCH_FORTUNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FORTUNET +# endif +# define machine_is_fortunet() (machine_arch_type == MACH_TYPE_FORTUNET) +#else +# define machine_is_fortunet() (0) +#endif + +#ifdef CONFIG_ARCH_VC547X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC547X +# endif +# define machine_is_vc547x() (machine_arch_type == MACH_TYPE_VC547X) +#else +# define machine_is_vc547x() (0) +#endif + +#ifdef CONFIG_SA1100_FILEWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FILEWALKER +# endif +# define machine_is_filewalker() (machine_arch_type == MACH_TYPE_FILEWALKER) +#else +# define machine_is_filewalker() (0) +#endif + +#ifdef CONFIG_SA1100_NETGATEWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETGATEWAY +# endif +# define machine_is_netgateway() (machine_arch_type == MACH_TYPE_NETGATEWAY) +#else +# define machine_is_netgateway() (0) +#endif + +#ifdef CONFIG_SA1100_SYMBOL2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYMBOL2800 +# endif +# define machine_is_symbol2800() (machine_arch_type == MACH_TYPE_SYMBOL2800) +#else +# define machine_is_symbol2800() (0) +#endif + +#ifdef CONFIG_SA1100_SUNS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUNS +# endif +# define machine_is_suns() (machine_arch_type == MACH_TYPE_SUNS) +#else +# define machine_is_suns() (0) +#endif + +#ifdef CONFIG_SA1100_FRODO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FRODO +# endif +# define machine_is_frodo() (machine_arch_type == MACH_TYPE_FRODO) +#else +# define machine_is_frodo() (0) +#endif + +#ifdef CONFIG_SA1100_MACH_TYTE_MS301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MACH_TYTE_MS301 +# endif +# define machine_is_ms301() (machine_arch_type == MACH_TYPE_MACH_TYTE_MS301) +#else +# define machine_is_ms301() (0) +#endif + +#ifdef CONFIG_ARCH_MX1ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX1ADS +# endif +# define machine_is_mx1ads() (machine_arch_type == MACH_TYPE_MX1ADS) +#else +# define machine_is_mx1ads() (0) +#endif + +#ifdef CONFIG_ARCH_H7201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H7201 +# endif +# define machine_is_h7201() (machine_arch_type == MACH_TYPE_H7201) +#else +# define machine_is_h7201() (0) +#endif + +#ifdef CONFIG_ARCH_H7202 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H7202 +# endif +# define machine_is_h7202() (machine_arch_type == MACH_TYPE_H7202) +#else +# define machine_is_h7202() (0) +#endif + +#ifdef CONFIG_ARCH_AMICO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AMICO +# endif +# define machine_is_amico() (machine_arch_type == MACH_TYPE_AMICO) +#else +# define machine_is_amico() (0) +#endif + +#ifdef CONFIG_SA1100_IAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IAM +# endif +# define machine_is_iam() (machine_arch_type == MACH_TYPE_IAM) +#else +# define machine_is_iam() (0) +#endif + +#ifdef CONFIG_SA1100_TT530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT530 +# endif +# define machine_is_tt530() (machine_arch_type == MACH_TYPE_TT530) +#else +# define machine_is_tt530() (0) +#endif + +#ifdef CONFIG_ARCH_SAM2400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAM2400 +# endif +# define machine_is_sam2400() (machine_arch_type == MACH_TYPE_SAM2400) +#else +# define machine_is_sam2400() (0) +#endif + +#ifdef CONFIG_SA1100_JORNADA56X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JORNADA56X +# endif +# define machine_is_jornada56x() (machine_arch_type == MACH_TYPE_JORNADA56X) +#else +# define machine_is_jornada56x() (0) +#endif + +#ifdef CONFIG_SA1100_ACTIVE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTIVE +# endif +# define machine_is_active() (machine_arch_type == MACH_TYPE_ACTIVE) +#else +# define machine_is_active() (0) +#endif + +#ifdef CONFIG_ARCH_IQ80321 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80321 +# endif +# define machine_is_iq80321() (machine_arch_type == MACH_TYPE_IQ80321) +#else +# define machine_is_iq80321() (0) +#endif + +#ifdef CONFIG_SA1100_WID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WID +# endif +# define machine_is_wid() (machine_arch_type == MACH_TYPE_WID) +#else +# define machine_is_wid() (0) +#endif + +#ifdef CONFIG_ARCH_SABINAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SABINAL +# endif +# define machine_is_sabinal() (machine_arch_type == MACH_TYPE_SABINAL) +#else +# define machine_is_sabinal() (0) +#endif + +#ifdef CONFIG_ARCH_IXP425_MATACUMBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP425_MATACUMBE +# endif +# define machine_is_ixp425_matacumbe() (machine_arch_type == MACH_TYPE_IXP425_MATACUMBE) +#else +# define machine_is_ixp425_matacumbe() (0) +#endif + +#ifdef CONFIG_SA1100_MINIPRINT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIPRINT +# endif +# define machine_is_miniprint() (machine_arch_type == MACH_TYPE_MINIPRINT) +#else +# define machine_is_miniprint() (0) +#endif + +#ifdef CONFIG_ARCH_ADM510X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADM510X +# endif +# define machine_is_adm510x() (machine_arch_type == MACH_TYPE_ADM510X) +#else +# define machine_is_adm510x() (0) +#endif + +#ifdef CONFIG_SA1100_SVS200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVS200 +# endif +# define machine_is_svs200() (machine_arch_type == MACH_TYPE_SVS200) +#else +# define machine_is_svs200() (0) +#endif + +#ifdef CONFIG_ARCH_ATG_TCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATG_TCU +# endif +# define machine_is_atg_tcu() (machine_arch_type == MACH_TYPE_ATG_TCU) +#else +# define machine_is_atg_tcu() (0) +#endif + +#ifdef CONFIG_SA1100_JORNADA820 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JORNADA820 +# endif +# define machine_is_jornada820() (machine_arch_type == MACH_TYPE_JORNADA820) +#else +# define machine_is_jornada820() (0) +#endif + +#ifdef CONFIG_ARCH_S3C44B0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C44B0 +# endif +# define machine_is_s3c44b0() (machine_arch_type == MACH_TYPE_S3C44B0) +#else +# define machine_is_s3c44b0() (0) +#endif + +#ifdef CONFIG_ARCH_MARGIS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARGIS2 +# endif +# define machine_is_margis2() (machine_arch_type == MACH_TYPE_MARGIS2) +#else +# define machine_is_margis2() (0) +#endif + +#ifdef CONFIG_ARCH_KS8695 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KS8695 +# endif +# define machine_is_ks8695() (machine_arch_type == MACH_TYPE_KS8695) +#else +# define machine_is_ks8695() (0) +#endif + +#ifdef CONFIG_ARCH_BRH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRH +# endif +# define machine_is_brh() (machine_arch_type == MACH_TYPE_BRH) +#else +# define machine_is_brh() (0) +#endif + +#ifdef CONFIG_ARCH_S3C2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2410 +# endif +# define machine_is_s3c2410() (machine_arch_type == MACH_TYPE_S3C2410) +#else +# define machine_is_s3c2410() (0) +#endif + +#ifdef CONFIG_ARCH_POSSIO_PX30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POSSIO_PX30 +# endif +# define machine_is_possio_px30() (machine_arch_type == MACH_TYPE_POSSIO_PX30) +#else +# define machine_is_possio_px30() (0) +#endif + +#ifdef CONFIG_ARCH_S3C2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2800 +# endif +# define machine_is_s3c2800() (machine_arch_type == MACH_TYPE_S3C2800) +#else +# define machine_is_s3c2800() (0) +#endif + +#ifdef CONFIG_SA1100_FLEETWOOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLEETWOOD +# endif +# define machine_is_fleetwood() (machine_arch_type == MACH_TYPE_FLEETWOOD) +#else +# define machine_is_fleetwood() (0) +#endif + +#ifdef CONFIG_ARCH_OMAHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAHA +# endif +# define machine_is_omaha() (machine_arch_type == MACH_TYPE_OMAHA) +#else +# define machine_is_omaha() (0) +#endif + +#ifdef CONFIG_ARCH_TA7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TA7 +# endif +# define machine_is_ta7() (machine_arch_type == MACH_TYPE_TA7) +#else +# define machine_is_ta7() (0) +#endif + +#ifdef CONFIG_SA1100_NOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOVA +# endif +# define machine_is_nova() (machine_arch_type == MACH_TYPE_NOVA) +#else +# define machine_is_nova() (0) +#endif + +#ifdef CONFIG_ARCH_HMK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMK +# endif +# define machine_is_hmk() (machine_arch_type == MACH_TYPE_HMK) +#else +# define machine_is_hmk() (0) +#endif + +#ifdef CONFIG_ARCH_KARO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KARO +# endif +# define machine_is_karo() (machine_arch_type == MACH_TYPE_KARO) +#else +# define machine_is_karo() (0) +#endif + +#ifdef CONFIG_SA1100_FESTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FESTER +# endif +# define machine_is_fester() (machine_arch_type == MACH_TYPE_FESTER) +#else +# define machine_is_fester() (0) +#endif + +#ifdef CONFIG_ARCH_GPI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GPI +# endif +# define machine_is_gpi() (machine_arch_type == MACH_TYPE_GPI) +#else +# define machine_is_gpi() (0) +#endif + +#ifdef CONFIG_ARCH_SMDK2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2410 +# endif +# define machine_is_smdk2410() (machine_arch_type == MACH_TYPE_SMDK2410) +#else +# define machine_is_smdk2410() (0) +#endif + +#ifdef CONFIG_ARCH_I519 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I519 +# endif +# define machine_is_i519() (machine_arch_type == MACH_TYPE_I519) +#else +# define machine_is_i519() (0) +#endif + +#ifdef CONFIG_SA1100_NEXIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXIO +# endif +# define machine_is_nexio() (machine_arch_type == MACH_TYPE_NEXIO) +#else +# define machine_is_nexio() (0) +#endif + +#ifdef CONFIG_SA1100_BITBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BITBOX +# endif +# define machine_is_bitbox() (machine_arch_type == MACH_TYPE_BITBOX) +#else +# define machine_is_bitbox() (0) +#endif + +#ifdef CONFIG_SA1100_G200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G200 +# endif +# define machine_is_g200() (machine_arch_type == MACH_TYPE_G200) +#else +# define machine_is_g200() (0) +#endif + +#ifdef CONFIG_SA1100_GILL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GILL +# endif +# define machine_is_gill() (machine_arch_type == MACH_TYPE_GILL) +#else +# define machine_is_gill() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_MERCURY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_MERCURY +# endif +# define machine_is_pxa_mercury() (machine_arch_type == MACH_TYPE_PXA_MERCURY) +#else +# define machine_is_pxa_mercury() (0) +#endif + +#ifdef CONFIG_ARCH_CEIVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEIVA +# endif +# define machine_is_ceiva() (machine_arch_type == MACH_TYPE_CEIVA) +#else +# define machine_is_ceiva() (0) +#endif + +#ifdef CONFIG_SA1100_FRET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FRET +# endif +# define machine_is_fret() (machine_arch_type == MACH_TYPE_FRET) +#else +# define machine_is_fret() (0) +#endif + +#ifdef CONFIG_SA1100_EMAILPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMAILPHONE +# endif +# define machine_is_emailphone() (machine_arch_type == MACH_TYPE_EMAILPHONE) +#else +# define machine_is_emailphone() (0) +#endif + +#ifdef CONFIG_ARCH_H3900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H3900 +# endif +# define machine_is_h3900() (machine_arch_type == MACH_TYPE_H3900) +#else +# define machine_is_h3900() (0) +#endif + +#ifdef CONFIG_ARCH_PXA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA1 +# endif +# define machine_is_pxa1() (machine_arch_type == MACH_TYPE_PXA1) +#else +# define machine_is_pxa1() (0) +#endif + +#ifdef CONFIG_SA1100_KOAN369 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOAN369 +# endif +# define machine_is_koan369() (machine_arch_type == MACH_TYPE_KOAN369) +#else +# define machine_is_koan369() (0) +#endif + +#ifdef CONFIG_ARCH_COGENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COGENT +# endif +# define machine_is_cogent() (machine_arch_type == MACH_TYPE_COGENT) +#else +# define machine_is_cogent() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_SIMPUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SIMPUTER +# endif +# define machine_is_esl_simputer() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER) +#else +# define machine_is_esl_simputer() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_SIMPUTER_CLR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_CLR +# endif +# define machine_is_esl_simputer_clr() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_CLR) +#else +# define machine_is_esl_simputer_clr() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_SIMPUTER_BW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_BW +# endif +# define machine_is_esl_simputer_bw() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_BW) +#else +# define machine_is_esl_simputer_bw() (0) +#endif + +#ifdef CONFIG_ARCH_HHP_CRADLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HHP_CRADLE +# endif +# define machine_is_hhp_cradle() (machine_arch_type == MACH_TYPE_HHP_CRADLE) +#else +# define machine_is_hhp_cradle() (0) +#endif + +#ifdef CONFIG_ARCH_HE500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HE500 +# endif +# define machine_is_he500() (machine_arch_type == MACH_TYPE_HE500) +#else +# define machine_is_he500() (0) +#endif + +#ifdef CONFIG_SA1100_INHANDELF2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHANDELF2 +# endif +# define machine_is_inhandelf2() (machine_arch_type == MACH_TYPE_INHANDELF2) +#else +# define machine_is_inhandelf2() (0) +#endif + +#ifdef CONFIG_SA1100_INHANDFTIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHANDFTIP +# endif +# define machine_is_inhandftip() (machine_arch_type == MACH_TYPE_INHANDFTIP) +#else +# define machine_is_inhandftip() (0) +#endif + +#ifdef CONFIG_SA1100_DNP1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DNP1110 +# endif +# define machine_is_dnp1110() (machine_arch_type == MACH_TYPE_DNP1110) +#else +# define machine_is_dnp1110() (0) +#endif + +#ifdef CONFIG_SA1100_PNP1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNP1110 +# endif +# define machine_is_pnp1110() (machine_arch_type == MACH_TYPE_PNP1110) +#else +# define machine_is_pnp1110() (0) +#endif + +#ifdef CONFIG_ARCH_CSB226 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB226 +# endif +# define machine_is_csb226() (machine_arch_type == MACH_TYPE_CSB226) +#else +# define machine_is_csb226() (0) +#endif + +#ifdef CONFIG_SA1100_ARNOLD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARNOLD +# endif +# define machine_is_arnold() (machine_arch_type == MACH_TYPE_ARNOLD) +#else +# define machine_is_arnold() (0) +#endif + +#ifdef CONFIG_MACH_VOICEBLUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOICEBLUE +# endif +# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE) +#else +# define machine_is_voiceblue() (0) +#endif + +#ifdef CONFIG_ARCH_JZ8028 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JZ8028 +# endif +# define machine_is_jz8028() (machine_arch_type == MACH_TYPE_JZ8028) +#else +# define machine_is_jz8028() (0) +#endif + +#ifdef CONFIG_ARCH_H5400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H5400 +# endif +# define machine_is_h5400() (machine_arch_type == MACH_TYPE_H5400) +#else +# define machine_is_h5400() (0) +#endif + +#ifdef CONFIG_SA1100_FORTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FORTE +# endif +# define machine_is_forte() (machine_arch_type == MACH_TYPE_FORTE) +#else +# define machine_is_forte() (0) +#endif + +#ifdef CONFIG_SA1100_ACAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACAM +# endif +# define machine_is_acam() (machine_arch_type == MACH_TYPE_ACAM) +#else +# define machine_is_acam() (0) +#endif + +#ifdef CONFIG_SA1100_ABOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ABOX +# endif +# define machine_is_abox() (machine_arch_type == MACH_TYPE_ABOX) +#else +# define machine_is_abox() (0) +#endif + +#ifdef CONFIG_ARCH_ATMEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATMEL +# endif +# define machine_is_atmel() (machine_arch_type == MACH_TYPE_ATMEL) +#else +# define machine_is_atmel() (0) +#endif + +#ifdef CONFIG_ARCH_SITSANG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SITSANG +# endif +# define machine_is_sitsang() (machine_arch_type == MACH_TYPE_SITSANG) +#else +# define machine_is_sitsang() (0) +#endif + +#ifdef CONFIG_SA1100_CPU1110LCDNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPU1110LCDNET +# endif +# define machine_is_cpu1110lcdnet() (machine_arch_type == MACH_TYPE_CPU1110LCDNET) +#else +# define machine_is_cpu1110lcdnet() (0) +#endif + +#ifdef CONFIG_ARCH_MPL_VCMA9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPL_VCMA9 +# endif +# define machine_is_mpl_vcma9() (machine_arch_type == MACH_TYPE_MPL_VCMA9) +#else +# define machine_is_mpl_vcma9() (0) +#endif + +#ifdef CONFIG_ARCH_OPUS_A1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPUS_A1 +# endif +# define machine_is_opus_a1() (machine_arch_type == MACH_TYPE_OPUS_A1) +#else +# define machine_is_opus_a1() (0) +#endif + +#ifdef CONFIG_ARCH_DAYTONA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAYTONA +# endif +# define machine_is_daytona() (machine_arch_type == MACH_TYPE_DAYTONA) +#else +# define machine_is_daytona() (0) +#endif + +#ifdef CONFIG_SA1100_KILLBEAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KILLBEAR +# endif +# define machine_is_killbear() (machine_arch_type == MACH_TYPE_KILLBEAR) +#else +# define machine_is_killbear() (0) +#endif + +#ifdef CONFIG_ARCH_YOHO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YOHO +# endif +# define machine_is_yoho() (machine_arch_type == MACH_TYPE_YOHO) +#else +# define machine_is_yoho() (0) +#endif + +#ifdef CONFIG_ARCH_JASPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JASPER +# endif +# define machine_is_jasper() (machine_arch_type == MACH_TYPE_JASPER) +#else +# define machine_is_jasper() (0) +#endif + +#ifdef CONFIG_ARCH_DSC25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSC25 +# endif +# define machine_is_dsc25() (machine_arch_type == MACH_TYPE_DSC25) +#else +# define machine_is_dsc25() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_INNOVATOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_INNOVATOR +# endif +# define machine_is_omap_innovator() (machine_arch_type == MACH_TYPE_OMAP_INNOVATOR) +#else +# define machine_is_omap_innovator() (0) +#endif + +#ifdef CONFIG_ARCH_RAMSES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAMSES +# endif +# define machine_is_mnci() (machine_arch_type == MACH_TYPE_RAMSES) +#else +# define machine_is_mnci() (0) +#endif + +#ifdef CONFIG_ARCH_S28X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S28X +# endif +# define machine_is_s28x() (machine_arch_type == MACH_TYPE_S28X) +#else +# define machine_is_s28x() (0) +#endif + +#ifdef CONFIG_ARCH_MPORT3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPORT3 +# endif +# define machine_is_mport3() (machine_arch_type == MACH_TYPE_MPORT3) +#else +# define machine_is_mport3() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_EAGLE250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_EAGLE250 +# endif +# define machine_is_pxa_eagle250() (machine_arch_type == MACH_TYPE_PXA_EAGLE250) +#else +# define machine_is_pxa_eagle250() (0) +#endif + +#ifdef CONFIG_ARCH_PDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDB +# endif +# define machine_is_pdb() (machine_arch_type == MACH_TYPE_PDB) +#else +# define machine_is_pdb() (0) +#endif + +#ifdef CONFIG_SA1100_BLUE_2G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUE_2G +# endif +# define machine_is_blue_2g() (machine_arch_type == MACH_TYPE_BLUE_2G) +#else +# define machine_is_blue_2g() (0) +#endif + +#ifdef CONFIG_SA1100_BLUEARCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUEARCH +# endif +# define machine_is_bluearch() (machine_arch_type == MACH_TYPE_BLUEARCH) +#else +# define machine_is_bluearch() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP2400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2400 +# endif +# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400) +#else +# define machine_is_ixdp2400() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2800 +# endif +# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800) +#else +# define machine_is_ixdp2800() (0) +#endif + +#ifdef CONFIG_SA1100_EXPLORER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXPLORER +# endif +# define machine_is_explorer() (machine_arch_type == MACH_TYPE_EXPLORER) +#else +# define machine_is_explorer() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP425 +# endif +# define machine_is_ixdp425() (machine_arch_type == MACH_TYPE_IXDP425) +#else +# define machine_is_ixdp425() (0) +#endif + +#ifdef CONFIG_ARCH_CHIMP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHIMP +# endif +# define machine_is_chimp() (machine_arch_type == MACH_TYPE_CHIMP) +#else +# define machine_is_chimp() (0) +#endif + +#ifdef CONFIG_ARCH_STORK_NEST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STORK_NEST +# endif +# define machine_is_stork_nest() (machine_arch_type == MACH_TYPE_STORK_NEST) +#else +# define machine_is_stork_nest() (0) +#endif + +#ifdef CONFIG_ARCH_STORK_EGG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STORK_EGG +# endif +# define machine_is_stork_egg() (machine_arch_type == MACH_TYPE_STORK_EGG) +#else +# define machine_is_stork_egg() (0) +#endif + +#ifdef CONFIG_SA1100_WISMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WISMO +# endif +# define machine_is_wismo() (machine_arch_type == MACH_TYPE_WISMO) +#else +# define machine_is_wismo() (0) +#endif + +#ifdef CONFIG_ARCH_EZLINX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZLINX +# endif +# define machine_is_ezlinx() (machine_arch_type == MACH_TYPE_EZLINX) +#else +# define machine_is_ezlinx() (0) +#endif + +#ifdef CONFIG_ARCH_AT91RM9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200 +# endif +# define machine_is_at91rm9200() (machine_arch_type == MACH_TYPE_AT91RM9200) +#else +# define machine_is_at91rm9200() (0) +#endif + +#ifdef CONFIG_ARCH_ADTECH_ORION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADTECH_ORION +# endif +# define machine_is_adtech_orion() (machine_arch_type == MACH_TYPE_ADTECH_ORION) +#else +# define machine_is_adtech_orion() (0) +#endif + +#ifdef CONFIG_ARCH_NEPTUNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEPTUNE +# endif +# define machine_is_neptune() (machine_arch_type == MACH_TYPE_NEPTUNE) +#else +# define machine_is_neptune() (0) +#endif + +#ifdef CONFIG_SA1100_HACKKIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HACKKIT +# endif +# define machine_is_hackkit() (machine_arch_type == MACH_TYPE_HACKKIT) +#else +# define machine_is_hackkit() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_WINS30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_WINS30 +# endif +# define machine_is_pxa_wins30() (machine_arch_type == MACH_TYPE_PXA_WINS30) +#else +# define machine_is_pxa_wins30() (0) +#endif + +#ifdef CONFIG_SA1100_LAVINNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LAVINNA +# endif +# define machine_is_lavinna() (machine_arch_type == MACH_TYPE_LAVINNA) +#else +# define machine_is_lavinna() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_UENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_UENGINE +# endif +# define machine_is_pxa_uengine() (machine_arch_type == MACH_TYPE_PXA_UENGINE) +#else +# define machine_is_pxa_uengine() (0) +#endif + +#ifdef CONFIG_ARCH_INNOKOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INNOKOM +# endif +# define machine_is_innokom() (machine_arch_type == MACH_TYPE_INNOKOM) +#else +# define machine_is_innokom() (0) +#endif + +#ifdef CONFIG_ARCH_BMS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BMS +# endif +# define machine_is_bms() (machine_arch_type == MACH_TYPE_BMS) +#else +# define machine_is_bms() (0) +#endif + +#ifdef CONFIG_ARCH_IXCDP1100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXCDP1100 +# endif +# define machine_is_ixcdp1100() (machine_arch_type == MACH_TYPE_IXCDP1100) +#else +# define machine_is_ixcdp1100() (0) +#endif + +#ifdef CONFIG_ARCH_PRPMC1100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRPMC1100 +# endif +# define machine_is_prpmc1100() (machine_arch_type == MACH_TYPE_PRPMC1100) +#else +# define machine_is_prpmc1100() (0) +#endif + +#ifdef CONFIG_ARCH_AT91RM9200DK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200DK +# endif +# define machine_is_at91rm9200dk() (machine_arch_type == MACH_TYPE_AT91RM9200DK) +#else +# define machine_is_at91rm9200dk() (0) +#endif + +#ifdef CONFIG_ARCH_ARMSTICK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMSTICK +# endif +# define machine_is_armstick() (machine_arch_type == MACH_TYPE_ARMSTICK) +#else +# define machine_is_armstick() (0) +#endif + +#ifdef CONFIG_ARCH_ARMONIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMONIE +# endif +# define machine_is_armonie() (machine_arch_type == MACH_TYPE_ARMONIE) +#else +# define machine_is_armonie() (0) +#endif + +#ifdef CONFIG_ARCH_MPORT1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPORT1 +# endif +# define machine_is_mport1() (machine_arch_type == MACH_TYPE_MPORT1) +#else +# define machine_is_mport1() (0) +#endif + +#ifdef CONFIG_ARCH_S3C5410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C5410 +# endif +# define machine_is_s3c5410() (machine_arch_type == MACH_TYPE_S3C5410) +#else +# define machine_is_s3c5410() (0) +#endif + +#ifdef CONFIG_ARCH_ZCP320A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZCP320A +# endif +# define machine_is_zcp320a() (machine_arch_type == MACH_TYPE_ZCP320A) +#else +# define machine_is_zcp320a() (0) +#endif + +#ifdef CONFIG_ARCH_I_BOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I_BOX +# endif +# define machine_is_i_box() (machine_arch_type == MACH_TYPE_I_BOX) +#else +# define machine_is_i_box() (0) +#endif + +#ifdef CONFIG_ARCH_STLC1502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STLC1502 +# endif +# define machine_is_stlc1502() (machine_arch_type == MACH_TYPE_STLC1502) +#else +# define machine_is_stlc1502() (0) +#endif + +#ifdef CONFIG_ARCH_SIREN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIREN +# endif +# define machine_is_siren() (machine_arch_type == MACH_TYPE_SIREN) +#else +# define machine_is_siren() (0) +#endif + +#ifdef CONFIG_ARCH_GREENLAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GREENLAKE +# endif +# define machine_is_greenlake() (machine_arch_type == MACH_TYPE_GREENLAKE) +#else +# define machine_is_greenlake() (0) +#endif + +#ifdef CONFIG_ARCH_ARGUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARGUS +# endif +# define machine_is_argus() (machine_arch_type == MACH_TYPE_ARGUS) +#else +# define machine_is_argus() (0) +#endif + +#ifdef CONFIG_SA1100_COMBADGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMBADGE +# endif +# define machine_is_combadge() (machine_arch_type == MACH_TYPE_COMBADGE) +#else +# define machine_is_combadge() (0) +#endif + +#ifdef CONFIG_ARCH_ROKEPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROKEPXA +# endif +# define machine_is_rokepxa() (machine_arch_type == MACH_TYPE_ROKEPXA) +#else +# define machine_is_rokepxa() (0) +#endif + +#ifdef CONFIG_ARCH_CINTEGRATOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CINTEGRATOR +# endif +# define machine_is_cintegrator() (machine_arch_type == MACH_TYPE_CINTEGRATOR) +#else +# define machine_is_cintegrator() (0) +#endif + +#ifdef CONFIG_ARCH_GUIDEA07 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUIDEA07 +# endif +# define machine_is_guidea07() (machine_arch_type == MACH_TYPE_GUIDEA07) +#else +# define machine_is_guidea07() (0) +#endif + +#ifdef CONFIG_ARCH_TAT257 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAT257 +# endif +# define machine_is_tat257() (machine_arch_type == MACH_TYPE_TAT257) +#else +# define machine_is_tat257() (0) +#endif + +#ifdef CONFIG_ARCH_IGP2425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGP2425 +# endif +# define machine_is_igp2425() (machine_arch_type == MACH_TYPE_IGP2425) +#else +# define machine_is_igp2425() (0) +#endif + +#ifdef CONFIG_ARCH_BLUEGRAMMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUEGRAMMA +# endif +# define machine_is_bluegrama() (machine_arch_type == MACH_TYPE_BLUEGRAMMA) +#else +# define machine_is_bluegrama() (0) +#endif + +#ifdef CONFIG_ARCH_IPOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPOD +# endif +# define machine_is_ipod() (machine_arch_type == MACH_TYPE_IPOD) +#else +# define machine_is_ipod() (0) +#endif + +#ifdef CONFIG_ARCH_ADSBITSYX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSYX +# endif +# define machine_is_adsbitsyx() (machine_arch_type == MACH_TYPE_ADSBITSYX) +#else +# define machine_is_adsbitsyx() (0) +#endif + +#ifdef CONFIG_ARCH_TRIZEPS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS2 +# endif +# define machine_is_trizeps2() (machine_arch_type == MACH_TYPE_TRIZEPS2) +#else +# define machine_is_trizeps2() (0) +#endif + +#ifdef CONFIG_ARCH_VIPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIPER +# endif +# define machine_is_viper() (machine_arch_type == MACH_TYPE_VIPER) +#else +# define machine_is_viper() (0) +#endif + +#ifdef CONFIG_SA1100_ADSBITSYPLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSYPLUS +# endif +# define machine_is_adsbitsyplus() (machine_arch_type == MACH_TYPE_ADSBITSYPLUS) +#else +# define machine_is_adsbitsyplus() (0) +#endif + +#ifdef CONFIG_SA1100_ADSAGC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSAGC +# endif +# define machine_is_adsagc() (machine_arch_type == MACH_TYPE_ADSAGC) +#else +# define machine_is_adsagc() (0) +#endif + +#ifdef CONFIG_ARCH_STP7312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STP7312 +# endif +# define machine_is_stp7312() (machine_arch_type == MACH_TYPE_STP7312) +#else +# define machine_is_stp7312() (0) +#endif + +#ifdef CONFIG_MACH_NX_PHNX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NX_PHNX +# endif +# define machine_is_nx_phnx() (machine_arch_type == MACH_TYPE_NX_PHNX) +#else +# define machine_is_nx_phnx() (0) +#endif + +#ifdef CONFIG_ARCH_WEP_EP250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEP_EP250 +# endif +# define machine_is_wep_ep250() (machine_arch_type == MACH_TYPE_WEP_EP250) +#else +# define machine_is_wep_ep250() (0) +#endif + +#ifdef CONFIG_ARCH_INHANDELF3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHANDELF3 +# endif +# define machine_is_inhandelf3() (machine_arch_type == MACH_TYPE_INHANDELF3) +#else +# define machine_is_inhandelf3() (0) +#endif + +#ifdef CONFIG_ARCH_ADI_COYOTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADI_COYOTE +# endif +# define machine_is_adi_coyote() (machine_arch_type == MACH_TYPE_ADI_COYOTE) +#else +# define machine_is_adi_coyote() (0) +#endif + +#ifdef CONFIG_ARCH_IYONIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IYONIX +# endif +# define machine_is_iyonix() (machine_arch_type == MACH_TYPE_IYONIX) +#else +# define machine_is_iyonix() (0) +#endif + +#ifdef CONFIG_ARCH_DAMICAM_SA1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAMICAM_SA1110 +# endif +# define machine_is_damicam1() (machine_arch_type == MACH_TYPE_DAMICAM_SA1110) +#else +# define machine_is_damicam1() (0) +#endif + +#ifdef CONFIG_ARCH_MEG03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEG03 +# endif +# define machine_is_meg03() (machine_arch_type == MACH_TYPE_MEG03) +#else +# define machine_is_meg03() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_WHITECHAPEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_WHITECHAPEL +# endif +# define machine_is_pxa_whitechapel() (machine_arch_type == MACH_TYPE_PXA_WHITECHAPEL) +#else +# define machine_is_pxa_whitechapel() (0) +#endif + +#ifdef CONFIG_ARCH_NWSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NWSC +# endif +# define machine_is_nwsc() (machine_arch_type == MACH_TYPE_NWSC) +#else +# define machine_is_nwsc() (0) +#endif + +#ifdef CONFIG_ARCH_NWLARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NWLARM +# endif +# define machine_is_nwlarm() (machine_arch_type == MACH_TYPE_NWLARM) +#else +# define machine_is_nwlarm() (0) +#endif + +#ifdef CONFIG_ARCH_IXP425_MGUARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP425_MGUARD +# endif +# define machine_is_ixp425_mguard() (machine_arch_type == MACH_TYPE_IXP425_MGUARD) +#else +# define machine_is_ixp425_mguard() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_NETDCU4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_NETDCU4 +# endif +# define machine_is_pxa_netdcu4() (machine_arch_type == MACH_TYPE_PXA_NETDCU4) +#else +# define machine_is_pxa_netdcu4() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP2401 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2401 +# endif +# define machine_is_ixdp2401() (machine_arch_type == MACH_TYPE_IXDP2401) +#else +# define machine_is_ixdp2401() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP2801 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2801 +# endif +# define machine_is_ixdp2801() (machine_arch_type == MACH_TYPE_IXDP2801) +#else +# define machine_is_ixdp2801() (0) +#endif + +#ifdef CONFIG_ARCH_ZODIAC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZODIAC +# endif +# define machine_is_zodiac() (machine_arch_type == MACH_TYPE_ZODIAC) +#else +# define machine_is_zodiac() (0) +#endif + +#ifdef CONFIG_ARCH_ARMMODUL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMMODUL +# endif +# define machine_is_armmodul() (machine_arch_type == MACH_TYPE_ARMMODUL) +#else +# define machine_is_armmodul() (0) +#endif + +#ifdef CONFIG_SA1100_KETOP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KETOP +# endif +# define machine_is_ketop() (machine_arch_type == MACH_TYPE_KETOP) +#else +# define machine_is_ketop() (0) +#endif + +#ifdef CONFIG_ARCH_AV7200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AV7200 +# endif +# define machine_is_av7200() (machine_arch_type == MACH_TYPE_AV7200) +#else +# define machine_is_av7200() (0) +#endif + +#ifdef CONFIG_ARCH_ARCH_TI925 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCH_TI925 +# endif +# define machine_is_arch_ti925() (machine_arch_type == MACH_TYPE_ARCH_TI925) +#else +# define machine_is_arch_ti925() (0) +#endif + +#ifdef CONFIG_ARCH_ACQ200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACQ200 +# endif +# define machine_is_acq200() (machine_arch_type == MACH_TYPE_ACQ200) +#else +# define machine_is_acq200() (0) +#endif + +#ifdef CONFIG_SA1100_PT_DAFIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PT_DAFIT +# endif +# define machine_is_pt_dafit() (machine_arch_type == MACH_TYPE_PT_DAFIT) +#else +# define machine_is_pt_dafit() (0) +#endif + +#ifdef CONFIG_ARCH_IHBA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IHBA +# endif +# define machine_is_ihba() (machine_arch_type == MACH_TYPE_IHBA) +#else +# define machine_is_ihba() (0) +#endif + +#ifdef CONFIG_ARCH_QUINQUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUINQUE +# endif +# define machine_is_quinque() (machine_arch_type == MACH_TYPE_QUINQUE) +#else +# define machine_is_quinque() (0) +#endif + +#ifdef CONFIG_ARCH_NIMBRAONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRAONE +# endif +# define machine_is_nimbraone() (machine_arch_type == MACH_TYPE_NIMBRAONE) +#else +# define machine_is_nimbraone() (0) +#endif + +#ifdef CONFIG_ARCH_NIMBRA29X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRA29X +# endif +# define machine_is_nimbra29x() (machine_arch_type == MACH_TYPE_NIMBRA29X) +#else +# define machine_is_nimbra29x() (0) +#endif + +#ifdef CONFIG_ARCH_NIMBRA210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRA210 +# endif +# define machine_is_nimbra210() (machine_arch_type == MACH_TYPE_NIMBRA210) +#else +# define machine_is_nimbra210() (0) +#endif + +#ifdef CONFIG_ARCH_HHP_D95XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HHP_D95XX +# endif +# define machine_is_hhp_d95xx() (machine_arch_type == MACH_TYPE_HHP_D95XX) +#else +# define machine_is_hhp_d95xx() (0) +#endif + +#ifdef CONFIG_ARCH_LABARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LABARM +# endif +# define machine_is_labarm() (machine_arch_type == MACH_TYPE_LABARM) +#else +# define machine_is_labarm() (0) +#endif + +#ifdef CONFIG_ARCH_M825XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M825XX +# endif +# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) +#else +# define machine_is_m825xx() (0) +#endif + +#ifdef CONFIG_SA1100_M7100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M7100 +# endif +# define machine_is_m7100() (machine_arch_type == MACH_TYPE_M7100) +#else +# define machine_is_m7100() (0) +#endif + +#ifdef CONFIG_ARCH_NIPC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIPC2 +# endif +# define machine_is_nipc2() (machine_arch_type == MACH_TYPE_NIPC2) +#else +# define machine_is_nipc2() (0) +#endif + +#ifdef CONFIG_ARCH_FU7202 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FU7202 +# endif +# define machine_is_fu7202() (machine_arch_type == MACH_TYPE_FU7202) +#else +# define machine_is_fu7202() (0) +#endif + +#ifdef CONFIG_ARCH_ADSAGX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSAGX +# endif +# define machine_is_adsagx() (machine_arch_type == MACH_TYPE_ADSAGX) +#else +# define machine_is_adsagx() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_POOH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_POOH +# endif +# define machine_is_pxa_pooh() (machine_arch_type == MACH_TYPE_PXA_POOH) +#else +# define machine_is_pxa_pooh() (0) +#endif + +#ifdef CONFIG_ARCH_BANDON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BANDON +# endif +# define machine_is_bandon() (machine_arch_type == MACH_TYPE_BANDON) +#else +# define machine_is_bandon() (0) +#endif + +#ifdef CONFIG_ARCH_PCM7210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM7210 +# endif +# define machine_is_pcm7210() (machine_arch_type == MACH_TYPE_PCM7210) +#else +# define machine_is_pcm7210() (0) +#endif + +#ifdef CONFIG_ARCH_NMS9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NMS9200 +# endif +# define machine_is_nms9200() (machine_arch_type == MACH_TYPE_NMS9200) +#else +# define machine_is_nms9200() (0) +#endif + +#ifdef CONFIG_ARCH_LOGODL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOGODL +# endif +# define machine_is_logodl() (machine_arch_type == MACH_TYPE_LOGODL) +#else +# define machine_is_logodl() (0) +#endif + +#ifdef CONFIG_SA1100_M7140 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M7140 +# endif +# define machine_is_m7140() (machine_arch_type == MACH_TYPE_M7140) +#else +# define machine_is_m7140() (0) +#endif + +#ifdef CONFIG_ARCH_KOREBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOREBOT +# endif +# define machine_is_korebot() (machine_arch_type == MACH_TYPE_KOREBOT) +#else +# define machine_is_korebot() (0) +#endif + +#ifdef CONFIG_ARCH_IQ31244 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ31244 +# endif +# define machine_is_iq31244() (machine_arch_type == MACH_TYPE_IQ31244) +#else +# define machine_is_iq31244() (0) +#endif + +#ifdef CONFIG_SA1100_KOAN393 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOAN393 +# endif +# define machine_is_koan393() (machine_arch_type == MACH_TYPE_KOAN393) +#else +# define machine_is_koan393() (0) +#endif + +#ifdef CONFIG_ARCH_INHANDFTIP3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHANDFTIP3 +# endif +# define machine_is_inhandftip3() (machine_arch_type == MACH_TYPE_INHANDFTIP3) +#else +# define machine_is_inhandftip3() (0) +#endif + +#ifdef CONFIG_ARCH_GONZO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GONZO +# endif +# define machine_is_gonzo() (machine_arch_type == MACH_TYPE_GONZO) +#else +# define machine_is_gonzo() (0) +#endif + +#ifdef CONFIG_ARCH_BAST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BAST +# endif +# define machine_is_bast() (machine_arch_type == MACH_TYPE_BAST) +#else +# define machine_is_bast() (0) +#endif + +#ifdef CONFIG_ARCH_SCANPASS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCANPASS +# endif +# define machine_is_scanpass() (machine_arch_type == MACH_TYPE_SCANPASS) +#else +# define machine_is_scanpass() (0) +#endif + +#ifdef CONFIG_ARCH_EP7312_POOH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EP7312_POOH +# endif +# define machine_is_ep7312_pooh() (machine_arch_type == MACH_TYPE_EP7312_POOH) +#else +# define machine_is_ep7312_pooh() (0) +#endif + +#ifdef CONFIG_ARCH_TA7S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TA7S +# endif +# define machine_is_ta7s() (machine_arch_type == MACH_TYPE_TA7S) +#else +# define machine_is_ta7s() (0) +#endif + +#ifdef CONFIG_ARCH_TA7V +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TA7V +# endif +# define machine_is_ta7v() (machine_arch_type == MACH_TYPE_TA7V) +#else +# define machine_is_ta7v() (0) +#endif + +#ifdef CONFIG_SA1100_ICARUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICARUS +# endif +# define machine_is_icarus() (machine_arch_type == MACH_TYPE_ICARUS) +#else +# define machine_is_icarus() (0) +#endif + +#ifdef CONFIG_ARCH_H1900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H1900 +# endif +# define machine_is_h1900() (machine_arch_type == MACH_TYPE_H1900) +#else +# define machine_is_h1900() (0) +#endif + +#ifdef CONFIG_SA1100_GEMINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMINI +# endif +# define machine_is_gemini() (machine_arch_type == MACH_TYPE_GEMINI) +#else +# define machine_is_gemini() (0) +#endif + +#ifdef CONFIG_ARCH_AXIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXIM +# endif +# define machine_is_axim() (machine_arch_type == MACH_TYPE_AXIM) +#else +# define machine_is_axim() (0) +#endif + +#ifdef CONFIG_ARCH_AUDIOTRON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUDIOTRON +# endif +# define machine_is_audiotron() (machine_arch_type == MACH_TYPE_AUDIOTRON) +#else +# define machine_is_audiotron() (0) +#endif + +#ifdef CONFIG_ARCH_H2200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H2200 +# endif +# define machine_is_h2200() (machine_arch_type == MACH_TYPE_H2200) +#else +# define machine_is_h2200() (0) +#endif + +#ifdef CONFIG_ARCH_LOOX600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOX600 +# endif +# define machine_is_loox600() (machine_arch_type == MACH_TYPE_LOOX600) +#else +# define machine_is_loox600() (0) +#endif + +#ifdef CONFIG_ARCH_NIOP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIOP +# endif +# define machine_is_niop() (machine_arch_type == MACH_TYPE_NIOP) +#else +# define machine_is_niop() (0) +#endif + +#ifdef CONFIG_ARCH_DM310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM310 +# endif +# define machine_is_dm310() (machine_arch_type == MACH_TYPE_DM310) +#else +# define machine_is_dm310() (0) +#endif + +#ifdef CONFIG_ARCH_SEEDPXA_C2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEEDPXA_C2 +# endif +# define machine_is_seedpxa_c2() (machine_arch_type == MACH_TYPE_SEEDPXA_C2) +#else +# define machine_is_seedpxa_c2() (0) +#endif + +#ifdef CONFIG_ARCH_IXP4XX_MGUARD_PCI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP4XX_MGUARD_PCI +# endif +# define machine_is_ixp4xx_mguardpci() (machine_arch_type == MACH_TYPE_IXP4XX_MGUARD_PCI) +#else +# define machine_is_ixp4xx_mguardpci() (0) +#endif + +#ifdef CONFIG_ARCH_H1940 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H1940 +# endif +# define machine_is_h1940() (machine_arch_type == MACH_TYPE_H1940) +#else +# define machine_is_h1940() (0) +#endif + +#ifdef CONFIG_ARCH_SCORPIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCORPIO +# endif +# define machine_is_scorpio() (machine_arch_type == MACH_TYPE_SCORPIO) +#else +# define machine_is_scorpio() (0) +#endif + +#ifdef CONFIG_ARCH_VIVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIVA +# endif +# define machine_is_viva() (machine_arch_type == MACH_TYPE_VIVA) +#else +# define machine_is_viva() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_XCARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_XCARD +# endif +# define machine_is_pxa_xcard() (machine_arch_type == MACH_TYPE_PXA_XCARD) +#else +# define machine_is_pxa_xcard() (0) +#endif + +#ifdef CONFIG_ARCH_CSB335 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB335 +# endif +# define machine_is_csb335() (machine_arch_type == MACH_TYPE_CSB335) +#else +# define machine_is_csb335() (0) +#endif + +#ifdef CONFIG_ARCH_IXRD425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXRD425 +# endif +# define machine_is_ixrd425() (machine_arch_type == MACH_TYPE_IXRD425) +#else +# define machine_is_ixrd425() (0) +#endif + +#ifdef CONFIG_ARCH_IQ80315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80315 +# endif +# define machine_is_iq80315() (machine_arch_type == MACH_TYPE_IQ80315) +#else +# define machine_is_iq80315() (0) +#endif + +#ifdef CONFIG_ARCH_NMP7312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NMP7312 +# endif +# define machine_is_nmp7312() (machine_arch_type == MACH_TYPE_NMP7312) +#else +# define machine_is_nmp7312() (0) +#endif + +#ifdef CONFIG_ARCH_CX861XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CX861XX +# endif +# define machine_is_cx861xx() (machine_arch_type == MACH_TYPE_CX861XX) +#else +# define machine_is_cx861xx() (0) +#endif + +#ifdef CONFIG_ARCH_ENP2611 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENP2611 +# endif +# define machine_is_enp2611() (machine_arch_type == MACH_TYPE_ENP2611) +#else +# define machine_is_enp2611() (0) +#endif + +#ifdef CONFIG_SA1100_XDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XDA +# endif +# define machine_is_xda() (machine_arch_type == MACH_TYPE_XDA) +#else +# define machine_is_xda() (0) +#endif + +#ifdef CONFIG_ARCH_CSIR_IMS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSIR_IMS +# endif +# define machine_is_csir_ims() (machine_arch_type == MACH_TYPE_CSIR_IMS) +#else +# define machine_is_csir_ims() (0) +#endif + +#ifdef CONFIG_ARCH_IXP421_DNAEETH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP421_DNAEETH +# endif +# define machine_is_ixp421_dnaeeth() (machine_arch_type == MACH_TYPE_IXP421_DNAEETH) +#else +# define machine_is_ixp421_dnaeeth() (0) +#endif + +#ifdef CONFIG_ARCH_POCKETSERV9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POCKETSERV9200 +# endif +# define machine_is_pocketserv9200() (machine_arch_type == MACH_TYPE_POCKETSERV9200) +#else +# define machine_is_pocketserv9200() (0) +#endif + +#ifdef CONFIG_ARCH_TOTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOTO +# endif +# define machine_is_toto() (machine_arch_type == MACH_TYPE_TOTO) +#else +# define machine_is_toto() (0) +#endif + +#ifdef CONFIG_ARCH_S3C2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2440 +# endif +# define machine_is_s3c2440() (machine_arch_type == MACH_TYPE_S3C2440) +#else +# define machine_is_s3c2440() (0) +#endif + +#ifdef CONFIG_ARCH_KS8695P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KS8695P +# endif +# define machine_is_ks8695p() (machine_arch_type == MACH_TYPE_KS8695P) +#else +# define machine_is_ks8695p() (0) +#endif + +#ifdef CONFIG_ARCH_SE4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SE4000 +# endif +# define machine_is_se4000() (machine_arch_type == MACH_TYPE_SE4000) +#else +# define machine_is_se4000() (0) +#endif + +#ifdef CONFIG_ARCH_QUADRICEPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUADRICEPS +# endif +# define machine_is_quadriceps() (machine_arch_type == MACH_TYPE_QUADRICEPS) +#else +# define machine_is_quadriceps() (0) +#endif + +#ifdef CONFIG_ARCH_BRONCO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRONCO +# endif +# define machine_is_bronco() (machine_arch_type == MACH_TYPE_BRONCO) +#else +# define machine_is_bronco() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_WIRELESS_TAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_WIRELESS_TAB +# endif +# define machine_is_esl_wireless_tab() (machine_arch_type == MACH_TYPE_ESL_WIRELESS_TAB) +#else +# define machine_is_esl_wireless_tab() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_SOFCOMP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SOFCOMP +# endif +# define machine_is_esl_sofcomp() (machine_arch_type == MACH_TYPE_ESL_SOFCOMP) +#else +# define machine_is_esl_sofcomp() (0) +#endif + +#ifdef CONFIG_ARCH_S5C7375 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5C7375 +# endif +# define machine_is_s5c7375() (machine_arch_type == MACH_TYPE_S5C7375) +#else +# define machine_is_s5c7375() (0) +#endif + +#ifdef CONFIG_ARCH_SPEARHEAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEARHEAD +# endif +# define machine_is_spearhead() (machine_arch_type == MACH_TYPE_SPEARHEAD) +#else +# define machine_is_spearhead() (0) +#endif + +#ifdef CONFIG_ARCH_PANTERA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PANTERA +# endif +# define machine_is_pantera() (machine_arch_type == MACH_TYPE_PANTERA) +#else +# define machine_is_pantera() (0) +#endif + +#ifdef CONFIG_ARCH_PRAYOGLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRAYOGLITE +# endif +# define machine_is_prayoglite() (machine_arch_type == MACH_TYPE_PRAYOGLITE) +#else +# define machine_is_prayoglite() (0) +#endif + +#ifdef CONFIG_ARCH_GUMSTIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUMSTIX +# endif +# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIX) +#else +# define machine_is_gumstix() (0) +#endif + +#ifdef CONFIG_ARCH_RCUBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RCUBE +# endif +# define machine_is_rcube() (machine_arch_type == MACH_TYPE_RCUBE) +#else +# define machine_is_rcube() (0) +#endif + +#ifdef CONFIG_ARCH_REA_OLV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REA_OLV +# endif +# define machine_is_rea_olv() (machine_arch_type == MACH_TYPE_REA_OLV) +#else +# define machine_is_rea_olv() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_IPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_IPHONE +# endif +# define machine_is_pxa_iphone() (machine_arch_type == MACH_TYPE_PXA_IPHONE) +#else +# define machine_is_pxa_iphone() (0) +#endif + +#ifdef CONFIG_ARCH_S3C3410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C3410 +# endif +# define machine_is_s3c3410() (machine_arch_type == MACH_TYPE_S3C3410) +#else +# define machine_is_s3c3410() (0) +#endif + +#ifdef CONFIG_ARCH_ESPD_4510B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESPD_4510B +# endif +# define machine_is_espd_4510b() (machine_arch_type == MACH_TYPE_ESPD_4510B) +#else +# define machine_is_espd_4510b() (0) +#endif + +#ifdef CONFIG_ARCH_MP1X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP1X +# endif +# define machine_is_mp1x() (machine_arch_type == MACH_TYPE_MP1X) +#else +# define machine_is_mp1x() (0) +#endif + +#ifdef CONFIG_ARCH_AT91RM9200TB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200TB +# endif +# define machine_is_at91rm9200tb() (machine_arch_type == MACH_TYPE_AT91RM9200TB) +#else +# define machine_is_at91rm9200tb() (0) +#endif + +#ifdef CONFIG_ARCH_ADSVGX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSVGX +# endif +# define machine_is_adsvgx() (machine_arch_type == MACH_TYPE_ADSVGX) +#else +# define machine_is_adsvgx() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_H2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_H2 +# endif +# define machine_is_omap_h2() (machine_arch_type == MACH_TYPE_OMAP_H2) +#else +# define machine_is_omap_h2() (0) +#endif + +#ifdef CONFIG_ARCH_PELEE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELEE +# endif +# define machine_is_pelee() (machine_arch_type == MACH_TYPE_PELEE) +#else +# define machine_is_pelee() (0) +#endif + +#ifdef CONFIG_MACH_E740 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E740 +# endif +# define machine_is_e740() (machine_arch_type == MACH_TYPE_E740) +#else +# define machine_is_e740() (0) +#endif + +#ifdef CONFIG_ARCH_IQ80331 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80331 +# endif +# define machine_is_iq80331() (machine_arch_type == MACH_TYPE_IQ80331) +#else +# define machine_is_iq80331() (0) +#endif + +#ifdef CONFIG_ARCH_VERSATILE_PB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VERSATILE_PB +# endif +# define machine_is_versatile_pb() (machine_arch_type == MACH_TYPE_VERSATILE_PB) +#else +# define machine_is_versatile_pb() (0) +#endif + +#ifdef CONFIG_MACH_KEV7A400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KEV7A400 +# endif +# define machine_is_kev7a400() (machine_arch_type == MACH_TYPE_KEV7A400) +#else +# define machine_is_kev7a400() (0) +#endif + +#ifdef CONFIG_MACH_LPD7A400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD7A400 +# endif +# define machine_is_lpd7a400() (machine_arch_type == MACH_TYPE_LPD7A400) +#else +# define machine_is_lpd7a400() (0) +#endif + +#ifdef CONFIG_MACH_LPD7A404 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD7A404 +# endif +# define machine_is_lpd7a404() (machine_arch_type == MACH_TYPE_LPD7A404) +#else +# define machine_is_lpd7a404() (0) +#endif + +#ifdef CONFIG_ARCH_FUJITSU_CAMELOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_CAMELOT +# endif +# define machine_is_fujitsu_camelot() (machine_arch_type == MACH_TYPE_FUJITSU_CAMELOT) +#else +# define machine_is_fujitsu_camelot() (0) +#endif + +#ifdef CONFIG_ARCH_JANUS2M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JANUS2M +# endif +# define machine_is_janus2m() (machine_arch_type == MACH_TYPE_JANUS2M) +#else +# define machine_is_janus2m() (0) +#endif + +#ifdef CONFIG_MACH_EMBTF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMBTF +# endif +# define machine_is_embtf() (machine_arch_type == MACH_TYPE_EMBTF) +#else +# define machine_is_embtf() (0) +#endif + +#ifdef CONFIG_MACH_HPM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPM +# endif +# define machine_is_hpm() (machine_arch_type == MACH_TYPE_HPM) +#else +# define machine_is_hpm() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2410TK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2410TK +# endif +# define machine_is_smdk2410tk() (machine_arch_type == MACH_TYPE_SMDK2410TK) +#else +# define machine_is_smdk2410tk() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2410AJ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2410AJ +# endif +# define machine_is_smdk2410aj() (machine_arch_type == MACH_TYPE_SMDK2410AJ) +#else +# define machine_is_smdk2410aj() (0) +#endif + +#ifdef CONFIG_MACH_STREETRACER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STREETRACER +# endif +# define machine_is_streetracer() (machine_arch_type == MACH_TYPE_STREETRACER) +#else +# define machine_is_streetracer() (0) +#endif + +#ifdef CONFIG_MACH_EFRAME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EFRAME +# endif +# define machine_is_eframe() (machine_arch_type == MACH_TYPE_EFRAME) +#else +# define machine_is_eframe() (0) +#endif + +#ifdef CONFIG_MACH_CSB337 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB337 +# endif +# define machine_is_csb337() (machine_arch_type == MACH_TYPE_CSB337) +#else +# define machine_is_csb337() (0) +#endif + +#ifdef CONFIG_MACH_PXA_LARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_LARK +# endif +# define machine_is_pxa_lark() (machine_arch_type == MACH_TYPE_PXA_LARK) +#else +# define machine_is_pxa_lark() (0) +#endif + +#ifdef CONFIG_MACH_PNP2110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNP2110 +# endif +# define machine_is_pxa_pnp2110() (machine_arch_type == MACH_TYPE_PNP2110) +#else +# define machine_is_pxa_pnp2110() (0) +#endif + +#ifdef CONFIG_MACH_TCC72X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TCC72X +# endif +# define machine_is_tcc72x() (machine_arch_type == MACH_TYPE_TCC72X) +#else +# define machine_is_tcc72x() (0) +#endif + +#ifdef CONFIG_MACH_ALTAIR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALTAIR +# endif +# define machine_is_altair() (machine_arch_type == MACH_TYPE_ALTAIR) +#else +# define machine_is_altair() (0) +#endif + +#ifdef CONFIG_MACH_KC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KC3 +# endif +# define machine_is_kc3() (machine_arch_type == MACH_TYPE_KC3) +#else +# define machine_is_kc3() (0) +#endif + +#ifdef CONFIG_MACH_SINTEFTD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SINTEFTD +# endif +# define machine_is_sinteftd() (machine_arch_type == MACH_TYPE_SINTEFTD) +#else +# define machine_is_sinteftd() (0) +#endif + +#ifdef CONFIG_MACH_MAINSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAINSTONE +# endif +# define machine_is_mainstone() (machine_arch_type == MACH_TYPE_MAINSTONE) +#else +# define machine_is_mainstone() (0) +#endif + +#ifdef CONFIG_MACH_ADAY4X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADAY4X +# endif +# define machine_is_aday4x() (machine_arch_type == MACH_TYPE_ADAY4X) +#else +# define machine_is_aday4x() (0) +#endif + +#ifdef CONFIG_MACH_LITE300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LITE300 +# endif +# define machine_is_lite300() (machine_arch_type == MACH_TYPE_LITE300) +#else +# define machine_is_lite300() (0) +#endif + +#ifdef CONFIG_MACH_S5C7376 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5C7376 +# endif +# define machine_is_s5c7376() (machine_arch_type == MACH_TYPE_S5C7376) +#else +# define machine_is_s5c7376() (0) +#endif + +#ifdef CONFIG_MACH_MT02 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT02 +# endif +# define machine_is_mt02() (machine_arch_type == MACH_TYPE_MT02) +#else +# define machine_is_mt02() (0) +#endif + +#ifdef CONFIG_MACH_MPORT3S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPORT3S +# endif +# define machine_is_mport3s() (machine_arch_type == MACH_TYPE_MPORT3S) +#else +# define machine_is_mport3s() (0) +#endif + +#ifdef CONFIG_MACH_RA_ALPHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RA_ALPHA +# endif +# define machine_is_ra_alpha() (machine_arch_type == MACH_TYPE_RA_ALPHA) +#else +# define machine_is_ra_alpha() (0) +#endif + +#ifdef CONFIG_MACH_XCEP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XCEP +# endif +# define machine_is_xcep() (machine_arch_type == MACH_TYPE_XCEP) +#else +# define machine_is_xcep() (0) +#endif + +#ifdef CONFIG_MACH_ARCOM_VULCAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCOM_VULCAN +# endif +# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) +#else +# define machine_is_arcom_vulcan() (0) +#endif + +#ifdef CONFIG_MACH_STARGATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STARGATE +# endif +# define machine_is_stargate() (machine_arch_type == MACH_TYPE_STARGATE) +#else +# define machine_is_stargate() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLOJ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLOJ +# endif +# define machine_is_armadilloj() (machine_arch_type == MACH_TYPE_ARMADILLOJ) +#else +# define machine_is_armadilloj() (0) +#endif + +#ifdef CONFIG_MACH_ELROY_JACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELROY_JACK +# endif +# define machine_is_elroy_jack() (machine_arch_type == MACH_TYPE_ELROY_JACK) +#else +# define machine_is_elroy_jack() (0) +#endif + +#ifdef CONFIG_MACH_BACKEND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BACKEND +# endif +# define machine_is_backend() (machine_arch_type == MACH_TYPE_BACKEND) +#else +# define machine_is_backend() (0) +#endif + +#ifdef CONFIG_MACH_S5LINBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5LINBOX +# endif +# define machine_is_s5linbox() (machine_arch_type == MACH_TYPE_S5LINBOX) +#else +# define machine_is_s5linbox() (0) +#endif + +#ifdef CONFIG_MACH_NOMADIK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOMADIK +# endif +# define machine_is_nomadik() (machine_arch_type == MACH_TYPE_NOMADIK) +#else +# define machine_is_nomadik() (0) +#endif + +#ifdef CONFIG_MACH_IA_CPU_9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IA_CPU_9200 +# endif +# define machine_is_ia_cpu_9200() (machine_arch_type == MACH_TYPE_IA_CPU_9200) +#else +# define machine_is_ia_cpu_9200() (0) +#endif + +#ifdef CONFIG_MACH_AT91_BJA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91_BJA1 +# endif +# define machine_is_at91_bja1() (machine_arch_type == MACH_TYPE_AT91_BJA1) +#else +# define machine_is_at91_bja1() (0) +#endif + +#ifdef CONFIG_MACH_CORGI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORGI +# endif +# define machine_is_corgi() (machine_arch_type == MACH_TYPE_CORGI) +#else +# define machine_is_corgi() (0) +#endif + +#ifdef CONFIG_MACH_POODLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POODLE +# endif +# define machine_is_poodle() (machine_arch_type == MACH_TYPE_POODLE) +#else +# define machine_is_poodle() (0) +#endif + +#ifdef CONFIG_MACH_TEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEN +# endif +# define machine_is_ten() (machine_arch_type == MACH_TYPE_TEN) +#else +# define machine_is_ten() (0) +#endif + +#ifdef CONFIG_MACH_ROVERP5P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERP5P +# endif +# define machine_is_roverp5p() (machine_arch_type == MACH_TYPE_ROVERP5P) +#else +# define machine_is_roverp5p() (0) +#endif + +#ifdef CONFIG_MACH_SC2700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC2700 +# endif +# define machine_is_sc2700() (machine_arch_type == MACH_TYPE_SC2700) +#else +# define machine_is_sc2700() (0) +#endif + +#ifdef CONFIG_MACH_EX_EAGLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EX_EAGLE +# endif +# define machine_is_ex_eagle() (machine_arch_type == MACH_TYPE_EX_EAGLE) +#else +# define machine_is_ex_eagle() (0) +#endif + +#ifdef CONFIG_MACH_NX_PXA12 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NX_PXA12 +# endif +# define machine_is_nx_pxa12() (machine_arch_type == MACH_TYPE_NX_PXA12) +#else +# define machine_is_nx_pxa12() (0) +#endif + +#ifdef CONFIG_MACH_NX_PXA5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NX_PXA5 +# endif +# define machine_is_nx_pxa5() (machine_arch_type == MACH_TYPE_NX_PXA5) +#else +# define machine_is_nx_pxa5() (0) +#endif + +#ifdef CONFIG_MACH_BLACKBOARD2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLACKBOARD2 +# endif +# define machine_is_blackboard2() (machine_arch_type == MACH_TYPE_BLACKBOARD2) +#else +# define machine_is_blackboard2() (0) +#endif + +#ifdef CONFIG_MACH_I819 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I819 +# endif +# define machine_is_i819() (machine_arch_type == MACH_TYPE_I819) +#else +# define machine_is_i819() (0) +#endif + +#ifdef CONFIG_MACH_IXMB995E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXMB995E +# endif +# define machine_is_ixmb995e() (machine_arch_type == MACH_TYPE_IXMB995E) +#else +# define machine_is_ixmb995e() (0) +#endif + +#ifdef CONFIG_MACH_SKYRIDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYRIDER +# endif +# define machine_is_skyrider() (machine_arch_type == MACH_TYPE_SKYRIDER) +#else +# define machine_is_skyrider() (0) +#endif + +#ifdef CONFIG_MACH_SKYHAWK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYHAWK +# endif +# define machine_is_skyhawk() (machine_arch_type == MACH_TYPE_SKYHAWK) +#else +# define machine_is_skyhawk() (0) +#endif + +#ifdef CONFIG_MACH_ENTERPRISE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENTERPRISE +# endif +# define machine_is_enterprise() (machine_arch_type == MACH_TYPE_ENTERPRISE) +#else +# define machine_is_enterprise() (0) +#endif + +#ifdef CONFIG_MACH_DEP2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEP2410 +# endif +# define machine_is_dep2410() (machine_arch_type == MACH_TYPE_DEP2410) +#else +# define machine_is_dep2410() (0) +#endif + +#ifdef CONFIG_MACH_ARMCORE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMCORE +# endif +# define machine_is_armcore() (machine_arch_type == MACH_TYPE_ARMCORE) +#else +# define machine_is_armcore() (0) +#endif + +#ifdef CONFIG_MACH_HOBBIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HOBBIT +# endif +# define machine_is_hobbit() (machine_arch_type == MACH_TYPE_HOBBIT) +#else +# define machine_is_hobbit() (0) +#endif + +#ifdef CONFIG_MACH_H7210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H7210 +# endif +# define machine_is_h7210() (machine_arch_type == MACH_TYPE_H7210) +#else +# define machine_is_h7210() (0) +#endif + +#ifdef CONFIG_MACH_PXA_NETDCU5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_NETDCU5 +# endif +# define machine_is_pxa_netdcu5() (machine_arch_type == MACH_TYPE_PXA_NETDCU5) +#else +# define machine_is_pxa_netdcu5() (0) +#endif + +#ifdef CONFIG_MACH_ACC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACC +# endif +# define machine_is_acc() (machine_arch_type == MACH_TYPE_ACC) +#else +# define machine_is_acc() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA +# endif +# define machine_is_esl_sarva() (machine_arch_type == MACH_TYPE_ESL_SARVA) +#else +# define machine_is_esl_sarva() (0) +#endif + +#ifdef CONFIG_MACH_XM250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XM250 +# endif +# define machine_is_xm250() (machine_arch_type == MACH_TYPE_XM250) +#else +# define machine_is_xm250() (0) +#endif + +#ifdef CONFIG_MACH_T6TC1XB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T6TC1XB +# endif +# define machine_is_t6tc1xb() (machine_arch_type == MACH_TYPE_T6TC1XB) +#else +# define machine_is_t6tc1xb() (0) +#endif + +#ifdef CONFIG_MACH_ESS710 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESS710 +# endif +# define machine_is_ess710() (machine_arch_type == MACH_TYPE_ESS710) +#else +# define machine_is_ess710() (0) +#endif + +#ifdef CONFIG_MACH_MX31ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31ADS +# endif +# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) +#else +# define machine_is_mx31ads() (0) +#endif + +#ifdef CONFIG_MACH_HIMALAYA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIMALAYA +# endif +# define machine_is_himalaya() (machine_arch_type == MACH_TYPE_HIMALAYA) +#else +# define machine_is_himalaya() (0) +#endif + +#ifdef CONFIG_MACH_BOLFENK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BOLFENK +# endif +# define machine_is_bolfenk() (machine_arch_type == MACH_TYPE_BOLFENK) +#else +# define machine_is_bolfenk() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200KR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200KR +# endif +# define machine_is_at91rm9200kr() (machine_arch_type == MACH_TYPE_AT91RM9200KR) +#else +# define machine_is_at91rm9200kr() (0) +#endif + +#ifdef CONFIG_MACH_EDB9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9312 +# endif +# define machine_is_edb9312() (machine_arch_type == MACH_TYPE_EDB9312) +#else +# define machine_is_edb9312() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_GENERIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_GENERIC +# endif +# define machine_is_omap_generic() (machine_arch_type == MACH_TYPE_OMAP_GENERIC) +#else +# define machine_is_omap_generic() (0) +#endif + +#ifdef CONFIG_MACH_AXIMX3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXIMX3 +# endif +# define machine_is_aximx3() (machine_arch_type == MACH_TYPE_AXIMX3) +#else +# define machine_is_aximx3() (0) +#endif + +#ifdef CONFIG_MACH_EB67XDIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EB67XDIP +# endif +# define machine_is_eb67xdip() (machine_arch_type == MACH_TYPE_EB67XDIP) +#else +# define machine_is_eb67xdip() (0) +#endif + +#ifdef CONFIG_MACH_WEBTXS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEBTXS +# endif +# define machine_is_webtxs() (machine_arch_type == MACH_TYPE_WEBTXS) +#else +# define machine_is_webtxs() (0) +#endif + +#ifdef CONFIG_MACH_HAWK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAWK +# endif +# define machine_is_hawk() (machine_arch_type == MACH_TYPE_HAWK) +#else +# define machine_is_hawk() (0) +#endif + +#ifdef CONFIG_MACH_CCAT91SBC001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCAT91SBC001 +# endif +# define machine_is_ccat91sbc001() (machine_arch_type == MACH_TYPE_CCAT91SBC001) +#else +# define machine_is_ccat91sbc001() (0) +#endif + +#ifdef CONFIG_MACH_EXPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXPRESSO +# endif +# define machine_is_expresso() (machine_arch_type == MACH_TYPE_EXPRESSO) +#else +# define machine_is_expresso() (0) +#endif + +#ifdef CONFIG_MACH_H4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H4000 +# endif +# define machine_is_h4000() (machine_arch_type == MACH_TYPE_H4000) +#else +# define machine_is_h4000() (0) +#endif + +#ifdef CONFIG_MACH_DINO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DINO +# endif +# define machine_is_dino() (machine_arch_type == MACH_TYPE_DINO) +#else +# define machine_is_dino() (0) +#endif + +#ifdef CONFIG_MACH_ML675K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML675K +# endif +# define machine_is_ml675k() (machine_arch_type == MACH_TYPE_ML675K) +#else +# define machine_is_ml675k() (0) +#endif + +#ifdef CONFIG_MACH_EDB9301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9301 +# endif +# define machine_is_edb9301() (machine_arch_type == MACH_TYPE_EDB9301) +#else +# define machine_is_edb9301() (0) +#endif + +#ifdef CONFIG_MACH_EDB9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9315 +# endif +# define machine_is_edb9315() (machine_arch_type == MACH_TYPE_EDB9315) +#else +# define machine_is_edb9315() (0) +#endif + +#ifdef CONFIG_MACH_RECIVA_TT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RECIVA_TT +# endif +# define machine_is_reciva_tt() (machine_arch_type == MACH_TYPE_RECIVA_TT) +#else +# define machine_is_reciva_tt() (0) +#endif + +#ifdef CONFIG_MACH_CSTCB01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSTCB01 +# endif +# define machine_is_cstcb01() (machine_arch_type == MACH_TYPE_CSTCB01) +#else +# define machine_is_cstcb01() (0) +#endif + +#ifdef CONFIG_MACH_CSTCB1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSTCB1 +# endif +# define machine_is_cstcb1() (machine_arch_type == MACH_TYPE_CSTCB1) +#else +# define machine_is_cstcb1() (0) +#endif + +#ifdef CONFIG_MACH_SHADWELL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHADWELL +# endif +# define machine_is_shadwell() (machine_arch_type == MACH_TYPE_SHADWELL) +#else +# define machine_is_shadwell() (0) +#endif + +#ifdef CONFIG_MACH_GOEPEL263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GOEPEL263 +# endif +# define machine_is_goepel263() (machine_arch_type == MACH_TYPE_GOEPEL263) +#else +# define machine_is_goepel263() (0) +#endif + +#ifdef CONFIG_MACH_ACQ100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACQ100 +# endif +# define machine_is_acq100() (machine_arch_type == MACH_TYPE_ACQ100) +#else +# define machine_is_acq100() (0) +#endif + +#ifdef CONFIG_MACH_MX1FS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX1FS2 +# endif +# define machine_is_mx1fs2() (machine_arch_type == MACH_TYPE_MX1FS2) +#else +# define machine_is_mx1fs2() (0) +#endif + +#ifdef CONFIG_MACH_HIPTOP_G1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIPTOP_G1 +# endif +# define machine_is_hiptop_g1() (machine_arch_type == MACH_TYPE_HIPTOP_G1) +#else +# define machine_is_hiptop_g1() (0) +#endif + +#ifdef CONFIG_MACH_SPARKY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARKY +# endif +# define machine_is_sparky() (machine_arch_type == MACH_TYPE_SPARKY) +#else +# define machine_is_sparky() (0) +#endif + +#ifdef CONFIG_MACH_NS9750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NS9750 +# endif +# define machine_is_ns9750() (machine_arch_type == MACH_TYPE_NS9750) +#else +# define machine_is_ns9750() (0) +#endif + +#ifdef CONFIG_MACH_PHOENIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHOENIX +# endif +# define machine_is_phoenix() (machine_arch_type == MACH_TYPE_PHOENIX) +#else +# define machine_is_phoenix() (0) +#endif + +#ifdef CONFIG_MACH_VR1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VR1000 +# endif +# define machine_is_vr1000() (machine_arch_type == MACH_TYPE_VR1000) +#else +# define machine_is_vr1000() (0) +#endif + +#ifdef CONFIG_MACH_DEISTERPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEISTERPXA +# endif +# define machine_is_deisterpxa() (machine_arch_type == MACH_TYPE_DEISTERPXA) +#else +# define machine_is_deisterpxa() (0) +#endif + +#ifdef CONFIG_MACH_BCM1160 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM1160 +# endif +# define machine_is_bcm1160() (machine_arch_type == MACH_TYPE_BCM1160) +#else +# define machine_is_bcm1160() (0) +#endif + +#ifdef CONFIG_MACH_PCM022 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM022 +# endif +# define machine_is_pcm022() (machine_arch_type == MACH_TYPE_PCM022) +#else +# define machine_is_pcm022() (0) +#endif + +#ifdef CONFIG_MACH_ADSGCX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSGCX +# endif +# define machine_is_adsgcx() (machine_arch_type == MACH_TYPE_ADSGCX) +#else +# define machine_is_adsgcx() (0) +#endif + +#ifdef CONFIG_MACH_DREADNAUGHT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DREADNAUGHT +# endif +# define machine_is_dreadnaught() (machine_arch_type == MACH_TYPE_DREADNAUGHT) +#else +# define machine_is_dreadnaught() (0) +#endif + +#ifdef CONFIG_MACH_DM320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM320 +# endif +# define machine_is_dm320() (machine_arch_type == MACH_TYPE_DM320) +#else +# define machine_is_dm320() (0) +#endif + +#ifdef CONFIG_MACH_MARKOV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARKOV +# endif +# define machine_is_markov() (machine_arch_type == MACH_TYPE_MARKOV) +#else +# define machine_is_markov() (0) +#endif + +#ifdef CONFIG_MACH_COS7A400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COS7A400 +# endif +# define machine_is_cos7a400() (machine_arch_type == MACH_TYPE_COS7A400) +#else +# define machine_is_cos7a400() (0) +#endif + +#ifdef CONFIG_MACH_MILANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILANO +# endif +# define machine_is_milano() (machine_arch_type == MACH_TYPE_MILANO) +#else +# define machine_is_milano() (0) +#endif + +#ifdef CONFIG_MACH_UE9328 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UE9328 +# endif +# define machine_is_ue9328() (machine_arch_type == MACH_TYPE_UE9328) +#else +# define machine_is_ue9328() (0) +#endif + +#ifdef CONFIG_MACH_UEX255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UEX255 +# endif +# define machine_is_uex255() (machine_arch_type == MACH_TYPE_UEX255) +#else +# define machine_is_uex255() (0) +#endif + +#ifdef CONFIG_MACH_UE2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UE2410 +# endif +# define machine_is_ue2410() (machine_arch_type == MACH_TYPE_UE2410) +#else +# define machine_is_ue2410() (0) +#endif + +#ifdef CONFIG_MACH_A620 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A620 +# endif +# define machine_is_a620() (machine_arch_type == MACH_TYPE_A620) +#else +# define machine_is_a620() (0) +#endif + +#ifdef CONFIG_MACH_OCELOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCELOT +# endif +# define machine_is_ocelot() (machine_arch_type == MACH_TYPE_OCELOT) +#else +# define machine_is_ocelot() (0) +#endif + +#ifdef CONFIG_MACH_CHEETAH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHEETAH +# endif +# define machine_is_cheetah() (machine_arch_type == MACH_TYPE_CHEETAH) +#else +# define machine_is_cheetah() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PERSEUS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PERSEUS2 +# endif +# define machine_is_omap_perseus2() (machine_arch_type == MACH_TYPE_OMAP_PERSEUS2) +#else +# define machine_is_omap_perseus2() (0) +#endif + +#ifdef CONFIG_MACH_ZVUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZVUE +# endif +# define machine_is_zvue() (machine_arch_type == MACH_TYPE_ZVUE) +#else +# define machine_is_zvue() (0) +#endif + +#ifdef CONFIG_MACH_ROVERP1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERP1 +# endif +# define machine_is_roverp1() (machine_arch_type == MACH_TYPE_ROVERP1) +#else +# define machine_is_roverp1() (0) +#endif + +#ifdef CONFIG_MACH_ASIDIAL2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASIDIAL2 +# endif +# define machine_is_asidial2() (machine_arch_type == MACH_TYPE_ASIDIAL2) +#else +# define machine_is_asidial2() (0) +#endif + +#ifdef CONFIG_MACH_S3C24A0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C24A0 +# endif +# define machine_is_s3c24a0() (machine_arch_type == MACH_TYPE_S3C24A0) +#else +# define machine_is_s3c24a0() (0) +#endif + +#ifdef CONFIG_MACH_E800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E800 +# endif +# define machine_is_e800() (machine_arch_type == MACH_TYPE_E800) +#else +# define machine_is_e800() (0) +#endif + +#ifdef CONFIG_MACH_E750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E750 +# endif +# define machine_is_e750() (machine_arch_type == MACH_TYPE_E750) +#else +# define machine_is_e750() (0) +#endif + +#ifdef CONFIG_MACH_S3C5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C5500 +# endif +# define machine_is_s3c5500() (machine_arch_type == MACH_TYPE_S3C5500) +#else +# define machine_is_s3c5500() (0) +#endif + +#ifdef CONFIG_MACH_SMDK5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK5500 +# endif +# define machine_is_smdk5500() (machine_arch_type == MACH_TYPE_SMDK5500) +#else +# define machine_is_smdk5500() (0) +#endif + +#ifdef CONFIG_MACH_SIGNALSYNC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIGNALSYNC +# endif +# define machine_is_signalsync() (machine_arch_type == MACH_TYPE_SIGNALSYNC) +#else +# define machine_is_signalsync() (0) +#endif + +#ifdef CONFIG_MACH_NBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NBC +# endif +# define machine_is_nbc() (machine_arch_type == MACH_TYPE_NBC) +#else +# define machine_is_nbc() (0) +#endif + +#ifdef CONFIG_MACH_KODIAK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KODIAK +# endif +# define machine_is_kodiak() (machine_arch_type == MACH_TYPE_KODIAK) +#else +# define machine_is_kodiak() (0) +#endif + +#ifdef CONFIG_MACH_NETBOOKPRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETBOOKPRO +# endif +# define machine_is_netbookpro() (machine_arch_type == MACH_TYPE_NETBOOKPRO) +#else +# define machine_is_netbookpro() (0) +#endif + +#ifdef CONFIG_MACH_HW90200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90200 +# endif +# define machine_is_hw90200() (machine_arch_type == MACH_TYPE_HW90200) +#else +# define machine_is_hw90200() (0) +#endif + +#ifdef CONFIG_MACH_CONDOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CONDOR +# endif +# define machine_is_condor() (machine_arch_type == MACH_TYPE_CONDOR) +#else +# define machine_is_condor() (0) +#endif + +#ifdef CONFIG_MACH_CUP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CUP +# endif +# define machine_is_cup() (machine_arch_type == MACH_TYPE_CUP) +#else +# define machine_is_cup() (0) +#endif + +#ifdef CONFIG_MACH_KITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KITE +# endif +# define machine_is_kite() (machine_arch_type == MACH_TYPE_KITE) +#else +# define machine_is_kite() (0) +#endif + +#ifdef CONFIG_MACH_SCB9328 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCB9328 +# endif +# define machine_is_scb9328() (machine_arch_type == MACH_TYPE_SCB9328) +#else +# define machine_is_scb9328() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_H3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_H3 +# endif +# define machine_is_omap_h3() (machine_arch_type == MACH_TYPE_OMAP_H3) +#else +# define machine_is_omap_h3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_H4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_H4 +# endif +# define machine_is_omap_h4() (machine_arch_type == MACH_TYPE_OMAP_H4) +#else +# define machine_is_omap_h4() (0) +#endif + +#ifdef CONFIG_MACH_N10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N10 +# endif +# define machine_is_n10() (machine_arch_type == MACH_TYPE_N10) +#else +# define machine_is_n10() (0) +#endif + +#ifdef CONFIG_MACH_MONTAJADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MONTAJADE +# endif +# define machine_is_montejade() (machine_arch_type == MACH_TYPE_MONTAJADE) +#else +# define machine_is_montejade() (0) +#endif + +#ifdef CONFIG_MACH_SG560 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG560 +# endif +# define machine_is_sg560() (machine_arch_type == MACH_TYPE_SG560) +#else +# define machine_is_sg560() (0) +#endif + +#ifdef CONFIG_MACH_DP1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DP1000 +# endif +# define machine_is_dp1000() (machine_arch_type == MACH_TYPE_DP1000) +#else +# define machine_is_dp1000() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_OSK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_OSK +# endif +# define machine_is_omap_osk() (machine_arch_type == MACH_TYPE_OMAP_OSK) +#else +# define machine_is_omap_osk() (0) +#endif + +#ifdef CONFIG_MACH_RG100V3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RG100V3 +# endif +# define machine_is_rg100v3() (machine_arch_type == MACH_TYPE_RG100V3) +#else +# define machine_is_rg100v3() (0) +#endif + +#ifdef CONFIG_MACH_MX2ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX2ADS +# endif +# define machine_is_mx2ads() (machine_arch_type == MACH_TYPE_MX2ADS) +#else +# define machine_is_mx2ads() (0) +#endif + +#ifdef CONFIG_MACH_PXA_KILO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_KILO +# endif +# define machine_is_pxa_kilo() (machine_arch_type == MACH_TYPE_PXA_KILO) +#else +# define machine_is_pxa_kilo() (0) +#endif + +#ifdef CONFIG_MACH_IXP4XX_EAGLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP4XX_EAGLE +# endif +# define machine_is_ixp4xx_eagle() (machine_arch_type == MACH_TYPE_IXP4XX_EAGLE) +#else +# define machine_is_ixp4xx_eagle() (0) +#endif + +#ifdef CONFIG_MACH_TOSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOSA +# endif +# define machine_is_tosa() (machine_arch_type == MACH_TYPE_TOSA) +#else +# define machine_is_tosa() (0) +#endif + +#ifdef CONFIG_MACH_MB2520F +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB2520F +# endif +# define machine_is_mb2520f() (machine_arch_type == MACH_TYPE_MB2520F) +#else +# define machine_is_mb2520f() (0) +#endif + +#ifdef CONFIG_MACH_EMC1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMC1000 +# endif +# define machine_is_emc1000() (machine_arch_type == MACH_TYPE_EMC1000) +#else +# define machine_is_emc1000() (0) +#endif + +#ifdef CONFIG_MACH_TIDSC25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIDSC25 +# endif +# define machine_is_tidsc25() (machine_arch_type == MACH_TYPE_TIDSC25) +#else +# define machine_is_tidsc25() (0) +#endif + +#ifdef CONFIG_MACH_AKCPMXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AKCPMXL +# endif +# define machine_is_akcpmxl() (machine_arch_type == MACH_TYPE_AKCPMXL) +#else +# define machine_is_akcpmxl() (0) +#endif + +#ifdef CONFIG_MACH_AV3XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AV3XX +# endif +# define machine_is_av3xx() (machine_arch_type == MACH_TYPE_AV3XX) +#else +# define machine_is_av3xx() (0) +#endif + +#ifdef CONFIG_MACH_AVILA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVILA +# endif +# define machine_is_avila() (machine_arch_type == MACH_TYPE_AVILA) +#else +# define machine_is_avila() (0) +#endif + +#ifdef CONFIG_MACH_PXA_MPM10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_MPM10 +# endif +# define machine_is_pxa_mpm10() (machine_arch_type == MACH_TYPE_PXA_MPM10) +#else +# define machine_is_pxa_mpm10() (0) +#endif + +#ifdef CONFIG_MACH_PXA_KYANITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_KYANITE +# endif +# define machine_is_pxa_kyanite() (machine_arch_type == MACH_TYPE_PXA_KYANITE) +#else +# define machine_is_pxa_kyanite() (0) +#endif + +#ifdef CONFIG_MACH_SGOLD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGOLD +# endif +# define machine_is_sgold() (machine_arch_type == MACH_TYPE_SGOLD) +#else +# define machine_is_sgold() (0) +#endif + +#ifdef CONFIG_MACH_OSCAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OSCAR +# endif +# define machine_is_oscar() (machine_arch_type == MACH_TYPE_OSCAR) +#else +# define machine_is_oscar() (0) +#endif + +#ifdef CONFIG_MACH_EPXA4USB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPXA4USB2 +# endif +# define machine_is_epxa4usb2() (machine_arch_type == MACH_TYPE_EPXA4USB2) +#else +# define machine_is_epxa4usb2() (0) +#endif + +#ifdef CONFIG_MACH_XSENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSENGINE +# endif +# define machine_is_xsengine() (machine_arch_type == MACH_TYPE_XSENGINE) +#else +# define machine_is_xsengine() (0) +#endif + +#ifdef CONFIG_MACH_IP600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP600 +# endif +# define machine_is_ip600() (machine_arch_type == MACH_TYPE_IP600) +#else +# define machine_is_ip600() (0) +#endif + +#ifdef CONFIG_MACH_MCAN2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCAN2 +# endif +# define machine_is_mcan2() (machine_arch_type == MACH_TYPE_MCAN2) +#else +# define machine_is_mcan2() (0) +#endif + +#ifdef CONFIG_MACH_DDI_BLUERIDGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DDI_BLUERIDGE +# endif +# define machine_is_ddi_blueridge() (machine_arch_type == MACH_TYPE_DDI_BLUERIDGE) +#else +# define machine_is_ddi_blueridge() (0) +#endif + +#ifdef CONFIG_MACH_SKYMINDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYMINDER +# endif +# define machine_is_skyminder() (machine_arch_type == MACH_TYPE_SKYMINDER) +#else +# define machine_is_skyminder() (0) +#endif + +#ifdef CONFIG_MACH_LPD79520 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD79520 +# endif +# define machine_is_lpd79520() (machine_arch_type == MACH_TYPE_LPD79520) +#else +# define machine_is_lpd79520() (0) +#endif + +#ifdef CONFIG_MACH_EDB9302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9302 +# endif +# define machine_is_edb9302() (machine_arch_type == MACH_TYPE_EDB9302) +#else +# define machine_is_edb9302() (0) +#endif + +#ifdef CONFIG_MACH_HW90340 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90340 +# endif +# define machine_is_hw90340() (machine_arch_type == MACH_TYPE_HW90340) +#else +# define machine_is_hw90340() (0) +#endif + +#ifdef CONFIG_MACH_CIP_BOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CIP_BOX +# endif +# define machine_is_cip_box() (machine_arch_type == MACH_TYPE_CIP_BOX) +#else +# define machine_is_cip_box() (0) +#endif + +#ifdef CONFIG_MACH_IVPN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IVPN +# endif +# define machine_is_ivpn() (machine_arch_type == MACH_TYPE_IVPN) +#else +# define machine_is_ivpn() (0) +#endif + +#ifdef CONFIG_MACH_RSOC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSOC2 +# endif +# define machine_is_rsoc2() (machine_arch_type == MACH_TYPE_RSOC2) +#else +# define machine_is_rsoc2() (0) +#endif + +#ifdef CONFIG_MACH_HUSKY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUSKY +# endif +# define machine_is_husky() (machine_arch_type == MACH_TYPE_HUSKY) +#else +# define machine_is_husky() (0) +#endif + +#ifdef CONFIG_MACH_BOXER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BOXER +# endif +# define machine_is_boxer() (machine_arch_type == MACH_TYPE_BOXER) +#else +# define machine_is_boxer() (0) +#endif + +#ifdef CONFIG_MACH_SHEPHERD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHEPHERD +# endif +# define machine_is_shepherd() (machine_arch_type == MACH_TYPE_SHEPHERD) +#else +# define machine_is_shepherd() (0) +#endif + +#ifdef CONFIG_MACH_AML42800AA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AML42800AA +# endif +# define machine_is_aml42800aa() (machine_arch_type == MACH_TYPE_AML42800AA) +#else +# define machine_is_aml42800aa() (0) +#endif + +#ifdef CONFIG_MACH_LPC2294 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2294 +# endif +# define machine_is_lpc2294() (machine_arch_type == MACH_TYPE_LPC2294) +#else +# define machine_is_lpc2294() (0) +#endif + +#ifdef CONFIG_MACH_SWITCHGRASS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWITCHGRASS +# endif +# define machine_is_switchgrass() (machine_arch_type == MACH_TYPE_SWITCHGRASS) +#else +# define machine_is_switchgrass() (0) +#endif + +#ifdef CONFIG_MACH_ENS_CMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENS_CMU +# endif +# define machine_is_ens_cmu() (machine_arch_type == MACH_TYPE_ENS_CMU) +#else +# define machine_is_ens_cmu() (0) +#endif + +#ifdef CONFIG_MACH_MM6_SDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MM6_SDB +# endif +# define machine_is_mm6_sdb() (machine_arch_type == MACH_TYPE_MM6_SDB) +#else +# define machine_is_mm6_sdb() (0) +#endif + +#ifdef CONFIG_MACH_SATURN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SATURN +# endif +# define machine_is_saturn() (machine_arch_type == MACH_TYPE_SATURN) +#else +# define machine_is_saturn() (0) +#endif + +#ifdef CONFIG_MACH_I30030EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I30030EVB +# endif +# define machine_is_i30030evb() (machine_arch_type == MACH_TYPE_I30030EVB) +#else +# define machine_is_i30030evb() (0) +#endif + +#ifdef CONFIG_MACH_MXC27530EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC27530EVB +# endif +# define machine_is_mxc27530evb() (machine_arch_type == MACH_TYPE_MXC27530EVB) +#else +# define machine_is_mxc27530evb() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2800 +# endif +# define machine_is_smdk2800() (machine_arch_type == MACH_TYPE_SMDK2800) +#else +# define machine_is_smdk2800() (0) +#endif + +#ifdef CONFIG_MACH_MTWILSON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MTWILSON +# endif +# define machine_is_mtwilson() (machine_arch_type == MACH_TYPE_MTWILSON) +#else +# define machine_is_mtwilson() (0) +#endif + +#ifdef CONFIG_MACH_ZITI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZITI +# endif +# define machine_is_ziti() (machine_arch_type == MACH_TYPE_ZITI) +#else +# define machine_is_ziti() (0) +#endif + +#ifdef CONFIG_MACH_GRANDFATHER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GRANDFATHER +# endif +# define machine_is_grandfather() (machine_arch_type == MACH_TYPE_GRANDFATHER) +#else +# define machine_is_grandfather() (0) +#endif + +#ifdef CONFIG_MACH_TENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TENGINE +# endif +# define machine_is_tengine() (machine_arch_type == MACH_TYPE_TENGINE) +#else +# define machine_is_tengine() (0) +#endif + +#ifdef CONFIG_MACH_S3C2460 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2460 +# endif +# define machine_is_s3c2460() (machine_arch_type == MACH_TYPE_S3C2460) +#else +# define machine_is_s3c2460() (0) +#endif + +#ifdef CONFIG_MACH_PDM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDM +# endif +# define machine_is_pdm() (machine_arch_type == MACH_TYPE_PDM) +#else +# define machine_is_pdm() (0) +#endif + +#ifdef CONFIG_MACH_H4700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H4700 +# endif +# define machine_is_h4700() (machine_arch_type == MACH_TYPE_H4700) +#else +# define machine_is_h4700() (0) +#endif + +#ifdef CONFIG_MACH_H6300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6300 +# endif +# define machine_is_h6300() (machine_arch_type == MACH_TYPE_H6300) +#else +# define machine_is_h6300() (0) +#endif + +#ifdef CONFIG_MACH_RZ1700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RZ1700 +# endif +# define machine_is_rz1700() (machine_arch_type == MACH_TYPE_RZ1700) +#else +# define machine_is_rz1700() (0) +#endif + +#ifdef CONFIG_MACH_A716 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A716 +# endif +# define machine_is_a716() (machine_arch_type == MACH_TYPE_A716) +#else +# define machine_is_a716() (0) +#endif + +#ifdef CONFIG_MACH_ESTK2440A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESTK2440A +# endif +# define machine_is_estk2440a() (machine_arch_type == MACH_TYPE_ESTK2440A) +#else +# define machine_is_estk2440a() (0) +#endif + +#ifdef CONFIG_MACH_ATWIXP425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATWIXP425 +# endif +# define machine_is_atwixp425() (machine_arch_type == MACH_TYPE_ATWIXP425) +#else +# define machine_is_atwixp425() (0) +#endif + +#ifdef CONFIG_MACH_CSB336 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB336 +# endif +# define machine_is_csb336() (machine_arch_type == MACH_TYPE_CSB336) +#else +# define machine_is_csb336() (0) +#endif + +#ifdef CONFIG_MACH_RIRM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIRM2 +# endif +# define machine_is_rirm2() (machine_arch_type == MACH_TYPE_RIRM2) +#else +# define machine_is_rirm2() (0) +#endif + +#ifdef CONFIG_MACH_CX23518 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CX23518 +# endif +# define machine_is_cx23518() (machine_arch_type == MACH_TYPE_CX23518) +#else +# define machine_is_cx23518() (0) +#endif + +#ifdef CONFIG_MACH_CX2351X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CX2351X +# endif +# define machine_is_cx2351x() (machine_arch_type == MACH_TYPE_CX2351X) +#else +# define machine_is_cx2351x() (0) +#endif + +#ifdef CONFIG_MACH_COMPUTIME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMPUTIME +# endif +# define machine_is_computime() (machine_arch_type == MACH_TYPE_COMPUTIME) +#else +# define machine_is_computime() (0) +#endif + +#ifdef CONFIG_MACH_IZARUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IZARUS +# endif +# define machine_is_izarus() (machine_arch_type == MACH_TYPE_IZARUS) +#else +# define machine_is_izarus() (0) +#endif + +#ifdef CONFIG_MACH_RTS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTS +# endif +# define machine_is_pxa_rts() (machine_arch_type == MACH_TYPE_RTS) +#else +# define machine_is_pxa_rts() (0) +#endif + +#ifdef CONFIG_MACH_SE5100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SE5100 +# endif +# define machine_is_se5100() (machine_arch_type == MACH_TYPE_SE5100) +#else +# define machine_is_se5100() (0) +#endif + +#ifdef CONFIG_MACH_S3C2510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2510 +# endif +# define machine_is_s3c2510() (machine_arch_type == MACH_TYPE_S3C2510) +#else +# define machine_is_s3c2510() (0) +#endif + +#ifdef CONFIG_MACH_CSB437TL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB437TL +# endif +# define machine_is_csb437tl() (machine_arch_type == MACH_TYPE_CSB437TL) +#else +# define machine_is_csb437tl() (0) +#endif + +#ifdef CONFIG_MACH_SLAUSON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SLAUSON +# endif +# define machine_is_slauson() (machine_arch_type == MACH_TYPE_SLAUSON) +#else +# define machine_is_slauson() (0) +#endif + +#ifdef CONFIG_MACH_PEARLRIVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEARLRIVER +# endif +# define machine_is_pearlriver() (machine_arch_type == MACH_TYPE_PEARLRIVER) +#else +# define machine_is_pearlriver() (0) +#endif + +#ifdef CONFIG_MACH_TDC_P210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TDC_P210 +# endif +# define machine_is_tdc_p210() (machine_arch_type == MACH_TYPE_TDC_P210) +#else +# define machine_is_tdc_p210() (0) +#endif + +#ifdef CONFIG_MACH_SG580 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG580 +# endif +# define machine_is_sg580() (machine_arch_type == MACH_TYPE_SG580) +#else +# define machine_is_sg580() (0) +#endif + +#ifdef CONFIG_MACH_WRSBCARM7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WRSBCARM7 +# endif +# define machine_is_wrsbcarm7() (machine_arch_type == MACH_TYPE_WRSBCARM7) +#else +# define machine_is_wrsbcarm7() (0) +#endif + +#ifdef CONFIG_MACH_IPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPD +# endif +# define machine_is_ipd() (machine_arch_type == MACH_TYPE_IPD) +#else +# define machine_is_ipd() (0) +#endif + +#ifdef CONFIG_MACH_PXA_DNP2110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_DNP2110 +# endif +# define machine_is_pxa_dnp2110() (machine_arch_type == MACH_TYPE_PXA_DNP2110) +#else +# define machine_is_pxa_dnp2110() (0) +#endif + +#ifdef CONFIG_MACH_XAENIAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XAENIAX +# endif +# define machine_is_xaeniax() (machine_arch_type == MACH_TYPE_XAENIAX) +#else +# define machine_is_xaeniax() (0) +#endif + +#ifdef CONFIG_MACH_SOMN4250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOMN4250 +# endif +# define machine_is_somn4250() (machine_arch_type == MACH_TYPE_SOMN4250) +#else +# define machine_is_somn4250() (0) +#endif + +#ifdef CONFIG_MACH_PLEB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLEB2 +# endif +# define machine_is_pleb2() (machine_arch_type == MACH_TYPE_PLEB2) +#else +# define machine_is_pleb2() (0) +#endif + +#ifdef CONFIG_MACH_CORNWALLIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORNWALLIS +# endif +# define machine_is_cornwallis() (machine_arch_type == MACH_TYPE_CORNWALLIS) +#else +# define machine_is_cornwallis() (0) +#endif + +#ifdef CONFIG_MACH_GURNEY_DRV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GURNEY_DRV +# endif +# define machine_is_gurney_drv() (machine_arch_type == MACH_TYPE_GURNEY_DRV) +#else +# define machine_is_gurney_drv() (0) +#endif + +#ifdef CONFIG_MACH_CHAFFEE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHAFFEE +# endif +# define machine_is_chaffee() (machine_arch_type == MACH_TYPE_CHAFFEE) +#else +# define machine_is_chaffee() (0) +#endif + +#ifdef CONFIG_MACH_RMS101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RMS101 +# endif +# define machine_is_rms101() (machine_arch_type == MACH_TYPE_RMS101) +#else +# define machine_is_rms101() (0) +#endif + +#ifdef CONFIG_MACH_RX3715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RX3715 +# endif +# define machine_is_rx3715() (machine_arch_type == MACH_TYPE_RX3715) +#else +# define machine_is_rx3715() (0) +#endif + +#ifdef CONFIG_MACH_SWIFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWIFT +# endif +# define machine_is_swift() (machine_arch_type == MACH_TYPE_SWIFT) +#else +# define machine_is_swift() (0) +#endif + +#ifdef CONFIG_MACH_ROVERP7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERP7 +# endif +# define machine_is_roverp7() (machine_arch_type == MACH_TYPE_ROVERP7) +#else +# define machine_is_roverp7() (0) +#endif + +#ifdef CONFIG_MACH_PR818S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PR818S +# endif +# define machine_is_pr818s() (machine_arch_type == MACH_TYPE_PR818S) +#else +# define machine_is_pr818s() (0) +#endif + +#ifdef CONFIG_MACH_TRXPRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRXPRO +# endif +# define machine_is_trxpro() (machine_arch_type == MACH_TYPE_TRXPRO) +#else +# define machine_is_trxpro() (0) +#endif + +#ifdef CONFIG_MACH_NSLU2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSLU2 +# endif +# define machine_is_nslu2() (machine_arch_type == MACH_TYPE_NSLU2) +#else +# define machine_is_nslu2() (0) +#endif + +#ifdef CONFIG_MACH_E400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E400 +# endif +# define machine_is_e400() (machine_arch_type == MACH_TYPE_E400) +#else +# define machine_is_e400() (0) +#endif + +#ifdef CONFIG_MACH_TRAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRAB +# endif +# define machine_is_trab() (machine_arch_type == MACH_TYPE_TRAB) +#else +# define machine_is_trab() (0) +#endif + +#ifdef CONFIG_MACH_CMC_PU2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMC_PU2 +# endif +# define machine_is_cmc_pu2() (machine_arch_type == MACH_TYPE_CMC_PU2) +#else +# define machine_is_cmc_pu2() (0) +#endif + +#ifdef CONFIG_MACH_FULCRUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FULCRUM +# endif +# define machine_is_fulcrum() (machine_arch_type == MACH_TYPE_FULCRUM) +#else +# define machine_is_fulcrum() (0) +#endif + +#ifdef CONFIG_MACH_NETGATE42X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETGATE42X +# endif +# define machine_is_netgate42x() (machine_arch_type == MACH_TYPE_NETGATE42X) +#else +# define machine_is_netgate42x() (0) +#endif + +#ifdef CONFIG_MACH_STR710 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR710 +# endif +# define machine_is_str710() (machine_arch_type == MACH_TYPE_STR710) +#else +# define machine_is_str710() (0) +#endif + +#ifdef CONFIG_MACH_IXDPG425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDPG425 +# endif +# define machine_is_ixdpg425() (machine_arch_type == MACH_TYPE_IXDPG425) +#else +# define machine_is_ixdpg425() (0) +#endif + +#ifdef CONFIG_MACH_TOMTOMGO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOMTOMGO +# endif +# define machine_is_tomtomgo() (machine_arch_type == MACH_TYPE_TOMTOMGO) +#else +# define machine_is_tomtomgo() (0) +#endif + +#ifdef CONFIG_MACH_VERSATILE_AB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VERSATILE_AB +# endif +# define machine_is_versatile_ab() (machine_arch_type == MACH_TYPE_VERSATILE_AB) +#else +# define machine_is_versatile_ab() (0) +#endif + +#ifdef CONFIG_MACH_EDB9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9307 +# endif +# define machine_is_edb9307() (machine_arch_type == MACH_TYPE_EDB9307) +#else +# define machine_is_edb9307() (0) +#endif + +#ifdef CONFIG_MACH_SG565 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG565 +# endif +# define machine_is_sg565() (machine_arch_type == MACH_TYPE_SG565) +#else +# define machine_is_sg565() (0) +#endif + +#ifdef CONFIG_MACH_LPD79524 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD79524 +# endif +# define machine_is_lpd79524() (machine_arch_type == MACH_TYPE_LPD79524) +#else +# define machine_is_lpd79524() (0) +#endif + +#ifdef CONFIG_MACH_LPD79525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD79525 +# endif +# define machine_is_lpd79525() (machine_arch_type == MACH_TYPE_LPD79525) +#else +# define machine_is_lpd79525() (0) +#endif + +#ifdef CONFIG_MACH_RMS100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RMS100 +# endif +# define machine_is_rms100() (machine_arch_type == MACH_TYPE_RMS100) +#else +# define machine_is_rms100() (0) +#endif + +#ifdef CONFIG_MACH_KB9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KB9200 +# endif +# define machine_is_kb9200() (machine_arch_type == MACH_TYPE_KB9200) +#else +# define machine_is_kb9200() (0) +#endif + +#ifdef CONFIG_MACH_SX1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SX1 +# endif +# define machine_is_sx1() (machine_arch_type == MACH_TYPE_SX1) +#else +# define machine_is_sx1() (0) +#endif + +#ifdef CONFIG_MACH_HMS39C7092 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMS39C7092 +# endif +# define machine_is_hms39c7092() (machine_arch_type == MACH_TYPE_HMS39C7092) +#else +# define machine_is_hms39c7092() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO +# endif +# define machine_is_armadillo() (machine_arch_type == MACH_TYPE_ARMADILLO) +#else +# define machine_is_armadillo() (0) +#endif + +#ifdef CONFIG_MACH_IPCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPCU +# endif +# define machine_is_ipcu() (machine_arch_type == MACH_TYPE_IPCU) +#else +# define machine_is_ipcu() (0) +#endif + +#ifdef CONFIG_MACH_LOOX720 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOX720 +# endif +# define machine_is_loox720() (machine_arch_type == MACH_TYPE_LOOX720) +#else +# define machine_is_loox720() (0) +#endif + +#ifdef CONFIG_MACH_IXDP465 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP465 +# endif +# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465) +#else +# define machine_is_ixdp465() (0) +#endif + +#ifdef CONFIG_MACH_IXDP2351 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2351 +# endif +# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351) +#else +# define machine_is_ixdp2351() (0) +#endif + +#ifdef CONFIG_MACH_ADSVIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSVIX +# endif +# define machine_is_adsvix() (machine_arch_type == MACH_TYPE_ADSVIX) +#else +# define machine_is_adsvix() (0) +#endif + +#ifdef CONFIG_MACH_DM270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM270 +# endif +# define machine_is_dm270() (machine_arch_type == MACH_TYPE_DM270) +#else +# define machine_is_dm270() (0) +#endif + +#ifdef CONFIG_MACH_SOCLTPLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOCLTPLUS +# endif +# define machine_is_socltplus() (machine_arch_type == MACH_TYPE_SOCLTPLUS) +#else +# define machine_is_socltplus() (0) +#endif + +#ifdef CONFIG_MACH_ECIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECIA +# endif +# define machine_is_ecia() (machine_arch_type == MACH_TYPE_ECIA) +#else +# define machine_is_ecia() (0) +#endif + +#ifdef CONFIG_MACH_CM4008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM4008 +# endif +# define machine_is_cm4008() (machine_arch_type == MACH_TYPE_CM4008) +#else +# define machine_is_cm4008() (0) +#endif + +#ifdef CONFIG_MACH_P2001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P2001 +# endif +# define machine_is_p2001() (machine_arch_type == MACH_TYPE_P2001) +#else +# define machine_is_p2001() (0) +#endif + +#ifdef CONFIG_MACH_TWISTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TWISTER +# endif +# define machine_is_twister() (machine_arch_type == MACH_TYPE_TWISTER) +#else +# define machine_is_twister() (0) +#endif + +#ifdef CONFIG_MACH_MUDSHARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MUDSHARK +# endif +# define machine_is_mudshark() (machine_arch_type == MACH_TYPE_MUDSHARK) +#else +# define machine_is_mudshark() (0) +#endif + +#ifdef CONFIG_MACH_HB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HB2 +# endif +# define machine_is_hb2() (machine_arch_type == MACH_TYPE_HB2) +#else +# define machine_is_hb2() (0) +#endif + +#ifdef CONFIG_MACH_IQ80332 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80332 +# endif +# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332) +#else +# define machine_is_iq80332() (0) +#endif + +#ifdef CONFIG_MACH_SENDT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SENDT +# endif +# define machine_is_sendt() (machine_arch_type == MACH_TYPE_SENDT) +#else +# define machine_is_sendt() (0) +#endif + +#ifdef CONFIG_MACH_MX2JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX2JAZZ +# endif +# define machine_is_mx2jazz() (machine_arch_type == MACH_TYPE_MX2JAZZ) +#else +# define machine_is_mx2jazz() (0) +#endif + +#ifdef CONFIG_MACH_MULTIIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIIO +# endif +# define machine_is_multiio() (machine_arch_type == MACH_TYPE_MULTIIO) +#else +# define machine_is_multiio() (0) +#endif + +#ifdef CONFIG_MACH_HRDISPLAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HRDISPLAY +# endif +# define machine_is_hrdisplay() (machine_arch_type == MACH_TYPE_HRDISPLAY) +#else +# define machine_is_hrdisplay() (0) +#endif + +#ifdef CONFIG_MACH_MXC27530ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC27530ADS +# endif +# define machine_is_mxc27530ads() (machine_arch_type == MACH_TYPE_MXC27530ADS) +#else +# define machine_is_mxc27530ads() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS3 +# endif +# define machine_is_trizeps3() (machine_arch_type == MACH_TYPE_TRIZEPS3) +#else +# define machine_is_trizeps3() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZA +# endif +# define machine_is_zefeerdza() (machine_arch_type == MACH_TYPE_ZEFEERDZA) +#else +# define machine_is_zefeerdza() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZB +# endif +# define machine_is_zefeerdzb() (machine_arch_type == MACH_TYPE_ZEFEERDZB) +#else +# define machine_is_zefeerdzb() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZG +# endif +# define machine_is_zefeerdzg() (machine_arch_type == MACH_TYPE_ZEFEERDZG) +#else +# define machine_is_zefeerdzg() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZN +# endif +# define machine_is_zefeerdzn() (machine_arch_type == MACH_TYPE_ZEFEERDZN) +#else +# define machine_is_zefeerdzn() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZQ +# endif +# define machine_is_zefeerdzq() (machine_arch_type == MACH_TYPE_ZEFEERDZQ) +#else +# define machine_is_zefeerdzq() (0) +#endif + +#ifdef CONFIG_MACH_GTWX5715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTWX5715 +# endif +# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715) +#else +# define machine_is_gtwx5715() (0) +#endif + +#ifdef CONFIG_MACH_ASTRO_JACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASTRO_JACK +# endif +# define machine_is_astro_jack() (machine_arch_type == MACH_TYPE_ASTRO_JACK) +#else +# define machine_is_astro_jack() (0) +#endif + +#ifdef CONFIG_MACH_TIP03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIP03 +# endif +# define machine_is_tip03() (machine_arch_type == MACH_TYPE_TIP03) +#else +# define machine_is_tip03() (0) +#endif + +#ifdef CONFIG_MACH_A9200EC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9200EC +# endif +# define machine_is_a9200ec() (machine_arch_type == MACH_TYPE_A9200EC) +#else +# define machine_is_a9200ec() (0) +#endif + +#ifdef CONFIG_MACH_PNX0105 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX0105 +# endif +# define machine_is_pnx0105() (machine_arch_type == MACH_TYPE_PNX0105) +#else +# define machine_is_pnx0105() (0) +#endif + +#ifdef CONFIG_MACH_ADCPOECPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADCPOECPU +# endif +# define machine_is_adcpoecpu() (machine_arch_type == MACH_TYPE_ADCPOECPU) +#else +# define machine_is_adcpoecpu() (0) +#endif + +#ifdef CONFIG_MACH_CSB637 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB637 +# endif +# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637) +#else +# define machine_is_csb637() (0) +#endif + +#ifdef CONFIG_MACH_MB9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9200 +# endif +# define machine_is_mb9200() (machine_arch_type == MACH_TYPE_MB9200) +#else +# define machine_is_mb9200() (0) +#endif + +#ifdef CONFIG_MACH_KULUN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KULUN +# endif +# define machine_is_kulun() (machine_arch_type == MACH_TYPE_KULUN) +#else +# define machine_is_kulun() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER +# endif +# define machine_is_snapper() (machine_arch_type == MACH_TYPE_SNAPPER) +#else +# define machine_is_snapper() (0) +#endif + +#ifdef CONFIG_MACH_OPTIMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPTIMA +# endif +# define machine_is_optima() (machine_arch_type == MACH_TYPE_OPTIMA) +#else +# define machine_is_optima() (0) +#endif + +#ifdef CONFIG_MACH_DLHSBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DLHSBC +# endif +# define machine_is_dlhsbc() (machine_arch_type == MACH_TYPE_DLHSBC) +#else +# define machine_is_dlhsbc() (0) +#endif + +#ifdef CONFIG_MACH_X30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_X30 +# endif +# define machine_is_x30() (machine_arch_type == MACH_TYPE_X30) +#else +# define machine_is_x30() (0) +#endif + +#ifdef CONFIG_MACH_N30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N30 +# endif +# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30) +#else +# define machine_is_n30() (0) +#endif + +#ifdef CONFIG_MACH_MANGA_KS8695 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MANGA_KS8695 +# endif +# define machine_is_manga_ks8695() (machine_arch_type == MACH_TYPE_MANGA_KS8695) +#else +# define machine_is_manga_ks8695() (0) +#endif + +#ifdef CONFIG_MACH_AJAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AJAX +# endif +# define machine_is_ajax() (machine_arch_type == MACH_TYPE_AJAX) +#else +# define machine_is_ajax() (0) +#endif + +#ifdef CONFIG_MACH_NEC_MP900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEC_MP900 +# endif +# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900) +#else +# define machine_is_nec_mp900() (0) +#endif + +#ifdef CONFIG_MACH_VVTK1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVTK1000 +# endif +# define machine_is_vvtk1000() (machine_arch_type == MACH_TYPE_VVTK1000) +#else +# define machine_is_vvtk1000() (0) +#endif + +#ifdef CONFIG_MACH_KAFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KAFA +# endif +# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA) +#else +# define machine_is_kafa() (0) +#endif + +#ifdef CONFIG_MACH_VVTK3000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVTK3000 +# endif +# define machine_is_vvtk3000() (machine_arch_type == MACH_TYPE_VVTK3000) +#else +# define machine_is_vvtk3000() (0) +#endif + +#ifdef CONFIG_MACH_PIMX1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PIMX1 +# endif +# define machine_is_pimx1() (machine_arch_type == MACH_TYPE_PIMX1) +#else +# define machine_is_pimx1() (0) +#endif + +#ifdef CONFIG_MACH_OLLIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLLIE +# endif +# define machine_is_ollie() (machine_arch_type == MACH_TYPE_OLLIE) +#else +# define machine_is_ollie() (0) +#endif + +#ifdef CONFIG_MACH_SKYMAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYMAX +# endif +# define machine_is_skymax() (machine_arch_type == MACH_TYPE_SKYMAX) +#else +# define machine_is_skymax() (0) +#endif + +#ifdef CONFIG_MACH_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JAZZ +# endif +# define machine_is_jazz() (machine_arch_type == MACH_TYPE_JAZZ) +#else +# define machine_is_jazz() (0) +#endif + +#ifdef CONFIG_MACH_TEL_T3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEL_T3 +# endif +# define machine_is_tel_t3() (machine_arch_type == MACH_TYPE_TEL_T3) +#else +# define machine_is_tel_t3() (0) +#endif + +#ifdef CONFIG_MACH_AISINO_FCR255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AISINO_FCR255 +# endif +# define machine_is_aisino_fcr255() (machine_arch_type == MACH_TYPE_AISINO_FCR255) +#else +# define machine_is_aisino_fcr255() (0) +#endif + +#ifdef CONFIG_MACH_BTWEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTWEB +# endif +# define machine_is_btweb() (machine_arch_type == MACH_TYPE_BTWEB) +#else +# define machine_is_btweb() (0) +#endif + +#ifdef CONFIG_MACH_DBG_LH79520 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DBG_LH79520 +# endif +# define machine_is_dbg_lh79520() (machine_arch_type == MACH_TYPE_DBG_LH79520) +#else +# define machine_is_dbg_lh79520() (0) +#endif + +#ifdef CONFIG_MACH_CM41XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM41XX +# endif +# define machine_is_cm41xx() (machine_arch_type == MACH_TYPE_CM41XX) +#else +# define machine_is_cm41xx() (0) +#endif + +#ifdef CONFIG_MACH_TS72XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS72XX +# endif +# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX) +#else +# define machine_is_ts72xx() (0) +#endif + +#ifdef CONFIG_MACH_NGGPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NGGPXA +# endif +# define machine_is_nggpxa() (machine_arch_type == MACH_TYPE_NGGPXA) +#else +# define machine_is_nggpxa() (0) +#endif + +#ifdef CONFIG_MACH_CSB535 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB535 +# endif +# define machine_is_csb535() (machine_arch_type == MACH_TYPE_CSB535) +#else +# define machine_is_csb535() (0) +#endif + +#ifdef CONFIG_MACH_CSB536 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB536 +# endif +# define machine_is_csb536() (machine_arch_type == MACH_TYPE_CSB536) +#else +# define machine_is_csb536() (0) +#endif + +#ifdef CONFIG_MACH_PXA_TRAKPOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_TRAKPOD +# endif +# define machine_is_pxa_trakpod() (machine_arch_type == MACH_TYPE_PXA_TRAKPOD) +#else +# define machine_is_pxa_trakpod() (0) +#endif + +#ifdef CONFIG_MACH_PRAXIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRAXIS +# endif +# define machine_is_praxis() (machine_arch_type == MACH_TYPE_PRAXIS) +#else +# define machine_is_praxis() (0) +#endif + +#ifdef CONFIG_MACH_LH75411 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LH75411 +# endif +# define machine_is_lh75411() (machine_arch_type == MACH_TYPE_LH75411) +#else +# define machine_is_lh75411() (0) +#endif + +#ifdef CONFIG_MACH_OTOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTOM +# endif +# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM) +#else +# define machine_is_otom() (0) +#endif + +#ifdef CONFIG_MACH_NEXCODER_2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXCODER_2440 +# endif +# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440) +#else +# define machine_is_nexcoder_2440() (0) +#endif + +#ifdef CONFIG_MACH_LOOX410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOX410 +# endif +# define machine_is_loox410() (machine_arch_type == MACH_TYPE_LOOX410) +#else +# define machine_is_loox410() (0) +#endif + +#ifdef CONFIG_MACH_WESTLAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WESTLAKE +# endif +# define machine_is_westlake() (machine_arch_type == MACH_TYPE_WESTLAKE) +#else +# define machine_is_westlake() (0) +#endif + +#ifdef CONFIG_MACH_NSB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB +# endif +# define machine_is_nsb() (machine_arch_type == MACH_TYPE_NSB) +#else +# define machine_is_nsb() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_STN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_STN +# endif +# define machine_is_esl_sarva_stn() (machine_arch_type == MACH_TYPE_ESL_SARVA_STN) +#else +# define machine_is_esl_sarva_stn() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_TFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_TFT +# endif +# define machine_is_esl_sarva_tft() (machine_arch_type == MACH_TYPE_ESL_SARVA_TFT) +#else +# define machine_is_esl_sarva_tft() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_IAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_IAD +# endif +# define machine_is_esl_sarva_iad() (machine_arch_type == MACH_TYPE_ESL_SARVA_IAD) +#else +# define machine_is_esl_sarva_iad() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_ACC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_ACC +# endif +# define machine_is_esl_sarva_acc() (machine_arch_type == MACH_TYPE_ESL_SARVA_ACC) +#else +# define machine_is_esl_sarva_acc() (0) +#endif + +#ifdef CONFIG_MACH_TYPHOON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TYPHOON +# endif +# define machine_is_typhoon() (machine_arch_type == MACH_TYPE_TYPHOON) +#else +# define machine_is_typhoon() (0) +#endif + +#ifdef CONFIG_MACH_CNAV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNAV +# endif +# define machine_is_cnav() (machine_arch_type == MACH_TYPE_CNAV) +#else +# define machine_is_cnav() (0) +#endif + +#ifdef CONFIG_MACH_A730 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A730 +# endif +# define machine_is_a730() (machine_arch_type == MACH_TYPE_A730) +#else +# define machine_is_a730() (0) +#endif + +#ifdef CONFIG_MACH_NETSTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSTAR +# endif +# define machine_is_netstar() (machine_arch_type == MACH_TYPE_NETSTAR) +#else +# define machine_is_netstar() (0) +#endif + +#ifdef CONFIG_MACH_PHASEFALE_SUPERCON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHASEFALE_SUPERCON +# endif +# define machine_is_supercon() (machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON) +#else +# define machine_is_supercon() (0) +#endif + +#ifdef CONFIG_MACH_SHIVA1100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHIVA1100 +# endif +# define machine_is_shiva1100() (machine_arch_type == MACH_TYPE_SHIVA1100) +#else +# define machine_is_shiva1100() (0) +#endif + +#ifdef CONFIG_MACH_ETEXSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETEXSC +# endif +# define machine_is_etexsc() (machine_arch_type == MACH_TYPE_ETEXSC) +#else +# define machine_is_etexsc() (0) +#endif + +#ifdef CONFIG_MACH_IXDPG465 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDPG465 +# endif +# define machine_is_ixdpg465() (machine_arch_type == MACH_TYPE_IXDPG465) +#else +# define machine_is_ixdpg465() (0) +#endif + +#ifdef CONFIG_MACH_A9M2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M2410 +# endif +# define machine_is_a9m2410() (machine_arch_type == MACH_TYPE_A9M2410) +#else +# define machine_is_a9m2410() (0) +#endif + +#ifdef CONFIG_MACH_A9M2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M2440 +# endif +# define machine_is_a9m2440() (machine_arch_type == MACH_TYPE_A9M2440) +#else +# define machine_is_a9m2440() (0) +#endif + +#ifdef CONFIG_MACH_A9M9750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M9750 +# endif +# define machine_is_a9m9750() (machine_arch_type == MACH_TYPE_A9M9750) +#else +# define machine_is_a9m9750() (0) +#endif + +#ifdef CONFIG_MACH_A9M9360 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M9360 +# endif +# define machine_is_a9m9360() (machine_arch_type == MACH_TYPE_A9M9360) +#else +# define machine_is_a9m9360() (0) +#endif + +#ifdef CONFIG_MACH_UNC90 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNC90 +# endif +# define machine_is_unc90() (machine_arch_type == MACH_TYPE_UNC90) +#else +# define machine_is_unc90() (0) +#endif + +#ifdef CONFIG_MACH_ECO920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECO920 +# endif +# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920) +#else +# define machine_is_eco920() (0) +#endif + +#ifdef CONFIG_MACH_SATVIEW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SATVIEW +# endif +# define machine_is_satview() (machine_arch_type == MACH_TYPE_SATVIEW) +#else +# define machine_is_satview() (0) +#endif + +#ifdef CONFIG_MACH_ROADRUNNER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROADRUNNER +# endif +# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER) +#else +# define machine_is_roadrunner() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200EK +# endif +# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK) +#else +# define machine_is_at91rm9200ek() (0) +#endif + +#ifdef CONFIG_MACH_GP32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GP32 +# endif +# define machine_is_gp32() (machine_arch_type == MACH_TYPE_GP32) +#else +# define machine_is_gp32() (0) +#endif + +#ifdef CONFIG_MACH_GEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEM +# endif +# define machine_is_gem() (machine_arch_type == MACH_TYPE_GEM) +#else +# define machine_is_gem() (0) +#endif + +#ifdef CONFIG_MACH_I858 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I858 +# endif +# define machine_is_i858() (machine_arch_type == MACH_TYPE_I858) +#else +# define machine_is_i858() (0) +#endif + +#ifdef CONFIG_MACH_HX2750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HX2750 +# endif +# define machine_is_hx2750() (machine_arch_type == MACH_TYPE_HX2750) +#else +# define machine_is_hx2750() (0) +#endif + +#ifdef CONFIG_MACH_MXC91131EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC91131EVB +# endif +# define machine_is_mxc91131evb() (machine_arch_type == MACH_TYPE_MXC91131EVB) +#else +# define machine_is_mxc91131evb() (0) +#endif + +#ifdef CONFIG_MACH_P700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P700 +# endif +# define machine_is_p700() (machine_arch_type == MACH_TYPE_P700) +#else +# define machine_is_p700() (0) +#endif + +#ifdef CONFIG_MACH_CPE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPE +# endif +# define machine_is_cpe() (machine_arch_type == MACH_TYPE_CPE) +#else +# define machine_is_cpe() (0) +#endif + +#ifdef CONFIG_MACH_SPITZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPITZ +# endif +# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ) +#else +# define machine_is_spitz() (0) +#endif + +#ifdef CONFIG_MACH_NIMBRA340 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRA340 +# endif +# define machine_is_nimbra340() (machine_arch_type == MACH_TYPE_NIMBRA340) +#else +# define machine_is_nimbra340() (0) +#endif + +#ifdef CONFIG_MACH_LPC22XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC22XX +# endif +# define machine_is_lpc22xx() (machine_arch_type == MACH_TYPE_LPC22XX) +#else +# define machine_is_lpc22xx() (0) +#endif + +#ifdef CONFIG_MACH_COMET3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMET3 +# endif +# define machine_is_omap_comet3() (machine_arch_type == MACH_TYPE_COMET3) +#else +# define machine_is_omap_comet3() (0) +#endif + +#ifdef CONFIG_MACH_COMET4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMET4 +# endif +# define machine_is_omap_comet4() (machine_arch_type == MACH_TYPE_COMET4) +#else +# define machine_is_omap_comet4() (0) +#endif + +#ifdef CONFIG_MACH_CSB625 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB625 +# endif +# define machine_is_csb625() (machine_arch_type == MACH_TYPE_CSB625) +#else +# define machine_is_csb625() (0) +#endif + +#ifdef CONFIG_MACH_FORTUNET2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FORTUNET2 +# endif +# define machine_is_fortunet2() (machine_arch_type == MACH_TYPE_FORTUNET2) +#else +# define machine_is_fortunet2() (0) +#endif + +#ifdef CONFIG_MACH_S5H2200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5H2200 +# endif +# define machine_is_s5h2200() (machine_arch_type == MACH_TYPE_S5H2200) +#else +# define machine_is_s5h2200() (0) +#endif + +#ifdef CONFIG_MACH_OPTORM920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPTORM920 +# endif +# define machine_is_optorm920() (machine_arch_type == MACH_TYPE_OPTORM920) +#else +# define machine_is_optorm920() (0) +#endif + +#ifdef CONFIG_MACH_ADSBITSYXB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSYXB +# endif +# define machine_is_adsbitsyxb() (machine_arch_type == MACH_TYPE_ADSBITSYXB) +#else +# define machine_is_adsbitsyxb() (0) +#endif + +#ifdef CONFIG_MACH_ADSSPHERE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSSPHERE +# endif +# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE) +#else +# define machine_is_adssphere() (0) +#endif + +#ifdef CONFIG_MACH_ADSPORTAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSPORTAL +# endif +# define machine_is_adsportal() (machine_arch_type == MACH_TYPE_ADSPORTAL) +#else +# define machine_is_adsportal() (0) +#endif + +#ifdef CONFIG_MACH_LN2410SBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LN2410SBC +# endif +# define machine_is_ln2410sbc() (machine_arch_type == MACH_TYPE_LN2410SBC) +#else +# define machine_is_ln2410sbc() (0) +#endif + +#ifdef CONFIG_MACH_CB3RUFC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CB3RUFC +# endif +# define machine_is_cb3rufc() (machine_arch_type == MACH_TYPE_CB3RUFC) +#else +# define machine_is_cb3rufc() (0) +#endif + +#ifdef CONFIG_MACH_MP2USB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP2USB +# endif +# define machine_is_mp2usb() (machine_arch_type == MACH_TYPE_MP2USB) +#else +# define machine_is_mp2usb() (0) +#endif + +#ifdef CONFIG_MACH_NTNP425C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NTNP425C +# endif +# define machine_is_ntnp425c() (machine_arch_type == MACH_TYPE_NTNP425C) +#else +# define machine_is_ntnp425c() (0) +#endif + +#ifdef CONFIG_MACH_COLIBRI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI +# endif +# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) +#else +# define machine_is_colibri() (0) +#endif + +#ifdef CONFIG_MACH_PCM7220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM7220 +# endif +# define machine_is_pcm7220() (machine_arch_type == MACH_TYPE_PCM7220) +#else +# define machine_is_pcm7220() (0) +#endif + +#ifdef CONFIG_MACH_GATEWAY7001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GATEWAY7001 +# endif +# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) +#else +# define machine_is_gateway7001() (0) +#endif + +#ifdef CONFIG_MACH_PCM027 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM027 +# endif +# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) +#else +# define machine_is_pcm027() (0) +#endif + +#ifdef CONFIG_MACH_CMPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMPXA +# endif +# define machine_is_cmpxa() (machine_arch_type == MACH_TYPE_CMPXA) +#else +# define machine_is_cmpxa() (0) +#endif + +#ifdef CONFIG_MACH_ANUBIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANUBIS +# endif +# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) +#else +# define machine_is_anubis() (0) +#endif + +#ifdef CONFIG_MACH_ITE8152 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ITE8152 +# endif +# define machine_is_ite8152() (machine_arch_type == MACH_TYPE_ITE8152) +#else +# define machine_is_ite8152() (0) +#endif + +#ifdef CONFIG_MACH_LPC3XXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC3XXX +# endif +# define machine_is_lpc3xxx() (machine_arch_type == MACH_TYPE_LPC3XXX) +#else +# define machine_is_lpc3xxx() (0) +#endif + +#ifdef CONFIG_MACH_PUPPETEER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PUPPETEER +# endif +# define machine_is_puppeteer() (machine_arch_type == MACH_TYPE_PUPPETEER) +#else +# define machine_is_puppeteer() (0) +#endif + +#ifdef CONFIG_MACH_E570 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E570 +# endif +# define machine_is_e570() (machine_arch_type == MACH_TYPE_E570) +#else +# define machine_is_e570() (0) +#endif + +#ifdef CONFIG_MACH_X50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_X50 +# endif +# define machine_is_x50() (machine_arch_type == MACH_TYPE_X50) +#else +# define machine_is_x50() (0) +#endif + +#ifdef CONFIG_MACH_RECON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RECON +# endif +# define machine_is_recon() (machine_arch_type == MACH_TYPE_RECON) +#else +# define machine_is_recon() (0) +#endif + +#ifdef CONFIG_MACH_XBOARDGP8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XBOARDGP8 +# endif +# define machine_is_xboardgp8() (machine_arch_type == MACH_TYPE_XBOARDGP8) +#else +# define machine_is_xboardgp8() (0) +#endif + +#ifdef CONFIG_MACH_FPIC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FPIC2 +# endif +# define machine_is_fpic2() (machine_arch_type == MACH_TYPE_FPIC2) +#else +# define machine_is_fpic2() (0) +#endif + +#ifdef CONFIG_MACH_AKITA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AKITA +# endif +# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) +#else +# define machine_is_akita() (0) +#endif + +#ifdef CONFIG_MACH_A81 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A81 +# endif +# define machine_is_a81() (machine_arch_type == MACH_TYPE_A81) +#else +# define machine_is_a81() (0) +#endif + +#ifdef CONFIG_MACH_SVM_SC25X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVM_SC25X +# endif +# define machine_is_svm_sc25x() (machine_arch_type == MACH_TYPE_SVM_SC25X) +#else +# define machine_is_svm_sc25x() (0) +#endif + +#ifdef CONFIG_MACH_VADATECH020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VADATECH020 +# endif +# define machine_is_vt020() (machine_arch_type == MACH_TYPE_VADATECH020) +#else +# define machine_is_vt020() (0) +#endif + +#ifdef CONFIG_MACH_TLI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TLI +# endif +# define machine_is_tli() (machine_arch_type == MACH_TYPE_TLI) +#else +# define machine_is_tli() (0) +#endif + +#ifdef CONFIG_MACH_EDB9315LC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9315LC +# endif +# define machine_is_edb9315lc() (machine_arch_type == MACH_TYPE_EDB9315LC) +#else +# define machine_is_edb9315lc() (0) +#endif + +#ifdef CONFIG_MACH_PASSEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSEC +# endif +# define machine_is_passec() (machine_arch_type == MACH_TYPE_PASSEC) +#else +# define machine_is_passec() (0) +#endif + +#ifdef CONFIG_MACH_DS_TIGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS_TIGER +# endif +# define machine_is_ds_tiger() (machine_arch_type == MACH_TYPE_DS_TIGER) +#else +# define machine_is_ds_tiger() (0) +#endif + +#ifdef CONFIG_MACH_E310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E310 +# endif +# define machine_is_e310() (machine_arch_type == MACH_TYPE_E310) +#else +# define machine_is_e310() (0) +#endif + +#ifdef CONFIG_MACH_E330 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E330 +# endif +# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) +#else +# define machine_is_e330() (0) +#endif + +#ifdef CONFIG_MACH_RT3000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RT3000 +# endif +# define machine_is_rt3000() (machine_arch_type == MACH_TYPE_RT3000) +#else +# define machine_is_rt3000() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA770 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA770 +# endif +# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) +#else +# define machine_is_nokia770() (0) +#endif + +#ifdef CONFIG_MACH_PNX0106 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX0106 +# endif +# define machine_is_pnx0106() (machine_arch_type == MACH_TYPE_PNX0106) +#else +# define machine_is_pnx0106() (0) +#endif + +#ifdef CONFIG_MACH_HX21XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HX21XX +# endif +# define machine_is_hx21xx() (machine_arch_type == MACH_TYPE_HX21XX) +#else +# define machine_is_hx21xx() (0) +#endif + +#ifdef CONFIG_MACH_FARADAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FARADAY +# endif +# define machine_is_faraday() (machine_arch_type == MACH_TYPE_FARADAY) +#else +# define machine_is_faraday() (0) +#endif + +#ifdef CONFIG_MACH_SBC9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC9312 +# endif +# define machine_is_sbc9312() (machine_arch_type == MACH_TYPE_SBC9312) +#else +# define machine_is_sbc9312() (0) +#endif + +#ifdef CONFIG_MACH_BATMAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BATMAN +# endif +# define machine_is_batman() (machine_arch_type == MACH_TYPE_BATMAN) +#else +# define machine_is_batman() (0) +#endif + +#ifdef CONFIG_MACH_JPD201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JPD201 +# endif +# define machine_is_jpd201() (machine_arch_type == MACH_TYPE_JPD201) +#else +# define machine_is_jpd201() (0) +#endif + +#ifdef CONFIG_MACH_MIPSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIPSA +# endif +# define machine_is_mipsa() (machine_arch_type == MACH_TYPE_MIPSA) +#else +# define machine_is_mipsa() (0) +#endif + +#ifdef CONFIG_MACH_KACOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KACOM +# endif +# define machine_is_kacom() (machine_arch_type == MACH_TYPE_KACOM) +#else +# define machine_is_kacom() (0) +#endif + +#ifdef CONFIG_MACH_SWARCOCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCOCPU +# endif +# define machine_is_swarcocpu() (machine_arch_type == MACH_TYPE_SWARCOCPU) +#else +# define machine_is_swarcocpu() (0) +#endif + +#ifdef CONFIG_MACH_SWARCODSL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCODSL +# endif +# define machine_is_swarcodsl() (machine_arch_type == MACH_TYPE_SWARCODSL) +#else +# define machine_is_swarcodsl() (0) +#endif + +#ifdef CONFIG_MACH_BLUEANGEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUEANGEL +# endif +# define machine_is_blueangel() (machine_arch_type == MACH_TYPE_BLUEANGEL) +#else +# define machine_is_blueangel() (0) +#endif + +#ifdef CONFIG_MACH_HAIRYGRAMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAIRYGRAMA +# endif +# define machine_is_hairygrama() (machine_arch_type == MACH_TYPE_HAIRYGRAMA) +#else +# define machine_is_hairygrama() (0) +#endif + +#ifdef CONFIG_MACH_BANFF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BANFF +# endif +# define machine_is_banff() (machine_arch_type == MACH_TYPE_BANFF) +#else +# define machine_is_banff() (0) +#endif + +#ifdef CONFIG_MACH_CARMEVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARMEVA +# endif +# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) +#else +# define machine_is_carmeva() (0) +#endif + +#ifdef CONFIG_MACH_SAM255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAM255 +# endif +# define machine_is_sam255() (machine_arch_type == MACH_TYPE_SAM255) +#else +# define machine_is_sam255() (0) +#endif + +#ifdef CONFIG_MACH_PPM10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PPM10 +# endif +# define machine_is_ppm10() (machine_arch_type == MACH_TYPE_PPM10) +#else +# define machine_is_ppm10() (0) +#endif + +#ifdef CONFIG_MACH_EDB9315A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9315A +# endif +# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) +#else +# define machine_is_edb9315a() (0) +#endif + +#ifdef CONFIG_MACH_SUNSET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUNSET +# endif +# define machine_is_sunset() (machine_arch_type == MACH_TYPE_SUNSET) +#else +# define machine_is_sunset() (0) +#endif + +#ifdef CONFIG_MACH_STARGATE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STARGATE2 +# endif +# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) +#else +# define machine_is_stargate2() (0) +#endif + +#ifdef CONFIG_MACH_INTELMOTE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INTELMOTE2 +# endif +# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) +#else +# define machine_is_intelmote2() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS4 +# endif +# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) +#else +# define machine_is_trizeps4() (0) +#endif + +#ifdef CONFIG_MACH_MAINSTONE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAINSTONE2 +# endif +# define machine_is_mainstone2() (machine_arch_type == MACH_TYPE_MAINSTONE2) +#else +# define machine_is_mainstone2() (0) +#endif + +#ifdef CONFIG_MACH_EZ_IXP42X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_IXP42X +# endif +# define machine_is_ez_ixp42x() (machine_arch_type == MACH_TYPE_EZ_IXP42X) +#else +# define machine_is_ez_ixp42x() (0) +#endif + +#ifdef CONFIG_MACH_TAPWAVE_ZODIAC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAPWAVE_ZODIAC +# endif +# define machine_is_tapwave_zodiac() (machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC) +#else +# define machine_is_tapwave_zodiac() (0) +#endif + +#ifdef CONFIG_MACH_UNIVERSALMETER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIVERSALMETER +# endif +# define machine_is_universalmeter() (machine_arch_type == MACH_TYPE_UNIVERSALMETER) +#else +# define machine_is_universalmeter() (0) +#endif + +#ifdef CONFIG_MACH_HICOARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HICOARM9 +# endif +# define machine_is_hicoarm9() (machine_arch_type == MACH_TYPE_HICOARM9) +#else +# define machine_is_hicoarm9() (0) +#endif + +#ifdef CONFIG_MACH_PNX4008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX4008 +# endif +# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) +#else +# define machine_is_pnx4008() (0) +#endif + +#ifdef CONFIG_MACH_KWS6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KWS6000 +# endif +# define machine_is_kws6000() (machine_arch_type == MACH_TYPE_KWS6000) +#else +# define machine_is_kws6000() (0) +#endif + +#ifdef CONFIG_MACH_PORTUX920T +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PORTUX920T +# endif +# define machine_is_portux920t() (machine_arch_type == MACH_TYPE_PORTUX920T) +#else +# define machine_is_portux920t() (0) +#endif + +#ifdef CONFIG_MACH_EZ_X5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_X5 +# endif +# define machine_is_ez_x5() (machine_arch_type == MACH_TYPE_EZ_X5) +#else +# define machine_is_ez_x5() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_RUDOLPH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_RUDOLPH +# endif +# define machine_is_omap_rudolph() (machine_arch_type == MACH_TYPE_OMAP_RUDOLPH) +#else +# define machine_is_omap_rudolph() (0) +#endif + +#ifdef CONFIG_MACH_CPUAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUAT91 +# endif +# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) +#else +# define machine_is_cpuat91() (0) +#endif + +#ifdef CONFIG_MACH_REA9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REA9200 +# endif +# define machine_is_rea9200() (machine_arch_type == MACH_TYPE_REA9200) +#else +# define machine_is_rea9200() (0) +#endif + +#ifdef CONFIG_MACH_ACTS_PUNE_SA1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTS_PUNE_SA1110 +# endif +# define machine_is_acts_pune_sa1110() (machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110) +#else +# define machine_is_acts_pune_sa1110() (0) +#endif + +#ifdef CONFIG_MACH_IXP425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP425 +# endif +# define machine_is_ixp425() (machine_arch_type == MACH_TYPE_IXP425) +#else +# define machine_is_ixp425() (0) +#endif + +#ifdef CONFIG_MACH_I30030ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I30030ADS +# endif +# define machine_is_i30030ads() (machine_arch_type == MACH_TYPE_I30030ADS) +#else +# define machine_is_i30030ads() (0) +#endif + +#ifdef CONFIG_MACH_PERCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PERCH +# endif +# define machine_is_perch() (machine_arch_type == MACH_TYPE_PERCH) +#else +# define machine_is_perch() (0) +#endif + +#ifdef CONFIG_MACH_EIS05R1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EIS05R1 +# endif +# define machine_is_eis05r1() (machine_arch_type == MACH_TYPE_EIS05R1) +#else +# define machine_is_eis05r1() (0) +#endif + +#ifdef CONFIG_MACH_PEPPERPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEPPERPAD +# endif +# define machine_is_pepperpad() (machine_arch_type == MACH_TYPE_PEPPERPAD) +#else +# define machine_is_pepperpad() (0) +#endif + +#ifdef CONFIG_MACH_SB3010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SB3010 +# endif +# define machine_is_sb3010() (machine_arch_type == MACH_TYPE_SB3010) +#else +# define machine_is_sb3010() (0) +#endif + +#ifdef CONFIG_MACH_RM9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RM9200 +# endif +# define machine_is_rm9200() (machine_arch_type == MACH_TYPE_RM9200) +#else +# define machine_is_rm9200() (0) +#endif + +#ifdef CONFIG_MACH_DMA03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DMA03 +# endif +# define machine_is_dma03() (machine_arch_type == MACH_TYPE_DMA03) +#else +# define machine_is_dma03() (0) +#endif + +#ifdef CONFIG_MACH_ROAD_S101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROAD_S101 +# endif +# define machine_is_road_s101() (machine_arch_type == MACH_TYPE_ROAD_S101) +#else +# define machine_is_road_s101() (0) +#endif + +#ifdef CONFIG_MACH_IQ81340SC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ81340SC +# endif +# define machine_is_iq81340sc() (machine_arch_type == MACH_TYPE_IQ81340SC) +#else +# define machine_is_iq81340sc() (0) +#endif + +#ifdef CONFIG_MACH_IQ_NEXTGEN_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_B +# endif +# define machine_is_iq_nextgen_b() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B) +#else +# define machine_is_iq_nextgen_b() (0) +#endif + +#ifdef CONFIG_MACH_IQ81340MC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ81340MC +# endif +# define machine_is_iq81340mc() (machine_arch_type == MACH_TYPE_IQ81340MC) +#else +# define machine_is_iq81340mc() (0) +#endif + +#ifdef CONFIG_MACH_IQ_NEXTGEN_D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_D +# endif +# define machine_is_iq_nextgen_d() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D) +#else +# define machine_is_iq_nextgen_d() (0) +#endif + +#ifdef CONFIG_MACH_IQ_NEXTGEN_E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_E +# endif +# define machine_is_iq_nextgen_e() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E) +#else +# define machine_is_iq_nextgen_e() (0) +#endif + +#ifdef CONFIG_MACH_MALLOW_AT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MALLOW_AT91 +# endif +# define machine_is_mallow_at91() (machine_arch_type == MACH_TYPE_MALLOW_AT91) +#else +# define machine_is_mallow_at91() (0) +#endif + +#ifdef CONFIG_MACH_CYBERTRACKER_I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBERTRACKER_I +# endif +# define machine_is_cybertracker_i() (machine_arch_type == MACH_TYPE_CYBERTRACKER_I) +#else +# define machine_is_cybertracker_i() (0) +#endif + +#ifdef CONFIG_MACH_GESBC931X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GESBC931X +# endif +# define machine_is_gesbc931x() (machine_arch_type == MACH_TYPE_GESBC931X) +#else +# define machine_is_gesbc931x() (0) +#endif + +#ifdef CONFIG_MACH_CENTIPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CENTIPAD +# endif +# define machine_is_centipad() (machine_arch_type == MACH_TYPE_CENTIPAD) +#else +# define machine_is_centipad() (0) +#endif + +#ifdef CONFIG_MACH_ARMSOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMSOC +# endif +# define machine_is_armsoc() (machine_arch_type == MACH_TYPE_ARMSOC) +#else +# define machine_is_armsoc() (0) +#endif + +#ifdef CONFIG_MACH_SE4200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SE4200 +# endif +# define machine_is_se4200() (machine_arch_type == MACH_TYPE_SE4200) +#else +# define machine_is_se4200() (0) +#endif + +#ifdef CONFIG_MACH_EMS197A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMS197A +# endif +# define machine_is_ems197a() (machine_arch_type == MACH_TYPE_EMS197A) +#else +# define machine_is_ems197a() (0) +#endif + +#ifdef CONFIG_MACH_MICRO9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO9 +# endif +# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) +#else +# define machine_is_micro9() (0) +#endif + +#ifdef CONFIG_MACH_MICRO9L +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO9L +# endif +# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) +#else +# define machine_is_micro9l() (0) +#endif + +#ifdef CONFIG_MACH_UC5471DSP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UC5471DSP +# endif +# define machine_is_uc5471dsp() (machine_arch_type == MACH_TYPE_UC5471DSP) +#else +# define machine_is_uc5471dsp() (0) +#endif + +#ifdef CONFIG_MACH_SJ5471ENG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SJ5471ENG +# endif +# define machine_is_sj5471eng() (machine_arch_type == MACH_TYPE_SJ5471ENG) +#else +# define machine_is_sj5471eng() (0) +#endif + +#ifdef CONFIG_MACH_CMPXA26X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMPXA26X +# endif +# define machine_is_none() (machine_arch_type == MACH_TYPE_CMPXA26X) +#else +# define machine_is_none() (0) +#endif + +#ifdef CONFIG_MACH_NC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NC +# endif +# define machine_is_nc1() (machine_arch_type == MACH_TYPE_NC) +#else +# define machine_is_nc1() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PALMTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PALMTE +# endif +# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) +#else +# define machine_is_omap_palmte() (0) +#endif + +#ifdef CONFIG_MACH_AJAX52X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AJAX52X +# endif +# define machine_is_ajax52x() (machine_arch_type == MACH_TYPE_AJAX52X) +#else +# define machine_is_ajax52x() (0) +#endif + +#ifdef CONFIG_MACH_SIRIUSTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIRIUSTAR +# endif +# define machine_is_siriustar() (machine_arch_type == MACH_TYPE_SIRIUSTAR) +#else +# define machine_is_siriustar() (0) +#endif + +#ifdef CONFIG_MACH_IODATA_HDLG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IODATA_HDLG +# endif +# define machine_is_iodata_hdlg() (machine_arch_type == MACH_TYPE_IODATA_HDLG) +#else +# define machine_is_iodata_hdlg() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200UTL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200UTL +# endif +# define machine_is_at91rm9200utl() (machine_arch_type == MACH_TYPE_AT91RM9200UTL) +#else +# define machine_is_at91rm9200utl() (0) +#endif + +#ifdef CONFIG_MACH_BIOSAFE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIOSAFE +# endif +# define machine_is_biosafe() (machine_arch_type == MACH_TYPE_BIOSAFE) +#else +# define machine_is_biosafe() (0) +#endif + +#ifdef CONFIG_MACH_MP1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP1000 +# endif +# define machine_is_mp1000() (machine_arch_type == MACH_TYPE_MP1000) +#else +# define machine_is_mp1000() (0) +#endif + +#ifdef CONFIG_MACH_PARSY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PARSY +# endif +# define machine_is_parsy() (machine_arch_type == MACH_TYPE_PARSY) +#else +# define machine_is_parsy() (0) +#endif + +#ifdef CONFIG_MACH_CCXP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCXP +# endif +# define machine_is_ccxp270() (machine_arch_type == MACH_TYPE_CCXP) +#else +# define machine_is_ccxp270() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_GSAMPLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_GSAMPLE +# endif +# define machine_is_omap_gsample() (machine_arch_type == MACH_TYPE_OMAP_GSAMPLE) +#else +# define machine_is_omap_gsample() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_EB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_EB +# endif +# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) +#else +# define machine_is_realview_eb() (0) +#endif + +#ifdef CONFIG_MACH_SAMOA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAMOA +# endif +# define machine_is_samoa() (machine_arch_type == MACH_TYPE_SAMOA) +#else +# define machine_is_samoa() (0) +#endif + +#ifdef CONFIG_MACH_PALMT3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMT3 +# endif +# define machine_is_palmt3() (machine_arch_type == MACH_TYPE_PALMT3) +#else +# define machine_is_palmt3() (0) +#endif + +#ifdef CONFIG_MACH_I878 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I878 +# endif +# define machine_is_i878() (machine_arch_type == MACH_TYPE_I878) +#else +# define machine_is_i878() (0) +#endif + +#ifdef CONFIG_MACH_BORZOI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BORZOI +# endif +# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) +#else +# define machine_is_borzoi() (0) +#endif + +#ifdef CONFIG_MACH_GECKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GECKO +# endif +# define machine_is_gecko() (machine_arch_type == MACH_TYPE_GECKO) +#else +# define machine_is_gecko() (0) +#endif + +#ifdef CONFIG_MACH_DS101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS101 +# endif +# define machine_is_ds101() (machine_arch_type == MACH_TYPE_DS101) +#else +# define machine_is_ds101() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PALMTT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PALMTT2 +# endif +# define machine_is_omap_palmtt2() (machine_arch_type == MACH_TYPE_OMAP_PALMTT2) +#else +# define machine_is_omap_palmtt2() (0) +#endif + +#ifdef CONFIG_MACH_PALMLD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMLD +# endif +# define machine_is_palmld() (machine_arch_type == MACH_TYPE_PALMLD) +#else +# define machine_is_palmld() (0) +#endif + +#ifdef CONFIG_MACH_CC9C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9C +# endif +# define machine_is_cc9c() (machine_arch_type == MACH_TYPE_CC9C) +#else +# define machine_is_cc9c() (0) +#endif + +#ifdef CONFIG_MACH_SBC1670 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC1670 +# endif +# define machine_is_sbc1670() (machine_arch_type == MACH_TYPE_SBC1670) +#else +# define machine_is_sbc1670() (0) +#endif + +#ifdef CONFIG_MACH_IXDP28X5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP28X5 +# endif +# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) +#else +# define machine_is_ixdp28x5() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PALMTT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PALMTT +# endif +# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) +#else +# define machine_is_omap_palmtt() (0) +#endif + +#ifdef CONFIG_MACH_ML696K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML696K +# endif +# define machine_is_ml696k() (machine_arch_type == MACH_TYPE_ML696K) +#else +# define machine_is_ml696k() (0) +#endif + +#ifdef CONFIG_MACH_ARCOM_ZEUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCOM_ZEUS +# endif +# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) +#else +# define machine_is_arcom_zeus() (0) +#endif + +#ifdef CONFIG_MACH_OSIRIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OSIRIS +# endif +# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) +#else +# define machine_is_osiris() (0) +#endif + +#ifdef CONFIG_MACH_MAESTRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAESTRO +# endif +# define machine_is_maestro() (machine_arch_type == MACH_TYPE_MAESTRO) +#else +# define machine_is_maestro() (0) +#endif + +#ifdef CONFIG_MACH_PALMTE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMTE2 +# endif +# define machine_is_palmte2() (machine_arch_type == MACH_TYPE_PALMTE2) +#else +# define machine_is_palmte2() (0) +#endif + +#ifdef CONFIG_MACH_IXBBM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXBBM +# endif +# define machine_is_ixbbm() (machine_arch_type == MACH_TYPE_IXBBM) +#else +# define machine_is_ixbbm() (0) +#endif + +#ifdef CONFIG_MACH_MX27ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27ADS +# endif +# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27ADS) +#else +# define machine_is_mx27ads() (0) +#endif + +#ifdef CONFIG_MACH_AX8004 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AX8004 +# endif +# define machine_is_ax8004() (machine_arch_type == MACH_TYPE_AX8004) +#else +# define machine_is_ax8004() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9261EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9261EK +# endif +# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) +#else +# define machine_is_at91sam9261ek() (0) +#endif + +#ifdef CONFIG_MACH_LOFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOFT +# endif +# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) +#else +# define machine_is_loft() (0) +#endif + +#ifdef CONFIG_MACH_MAGPIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGPIE +# endif +# define machine_is_magpie() (machine_arch_type == MACH_TYPE_MAGPIE) +#else +# define machine_is_magpie() (0) +#endif + +#ifdef CONFIG_MACH_MX21ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX21ADS +# endif +# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21ADS) +#else +# define machine_is_mx21ads() (0) +#endif + +#ifdef CONFIG_MACH_MB87M3400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB87M3400 +# endif +# define machine_is_mb87m3400() (machine_arch_type == MACH_TYPE_MB87M3400) +#else +# define machine_is_mb87m3400() (0) +#endif + +#ifdef CONFIG_MACH_MGUARD_DELTA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MGUARD_DELTA +# endif +# define machine_is_mguard_delta() (machine_arch_type == MACH_TYPE_MGUARD_DELTA) +#else +# define machine_is_mguard_delta() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DVDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DVDP +# endif +# define machine_is_davinci_dvdp() (machine_arch_type == MACH_TYPE_DAVINCI_DVDP) +#else +# define machine_is_davinci_dvdp() (0) +#endif + +#ifdef CONFIG_MACH_HTCUNIVERSAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCUNIVERSAL +# endif +# define machine_is_htcuniversal() (machine_arch_type == MACH_TYPE_HTCUNIVERSAL) +#else +# define machine_is_htcuniversal() (0) +#endif + +#ifdef CONFIG_MACH_TPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TPAD +# endif +# define machine_is_tpad() (machine_arch_type == MACH_TYPE_TPAD) +#else +# define machine_is_tpad() (0) +#endif + +#ifdef CONFIG_MACH_ROVERP3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERP3 +# endif +# define machine_is_roverp3() (machine_arch_type == MACH_TYPE_ROVERP3) +#else +# define machine_is_roverp3() (0) +#endif + +#ifdef CONFIG_MACH_JORNADA928 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JORNADA928 +# endif +# define machine_is_jornada928() (machine_arch_type == MACH_TYPE_JORNADA928) +#else +# define machine_is_jornada928() (0) +#endif + +#ifdef CONFIG_MACH_MV88FXX81 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV88FXX81 +# endif +# define machine_is_mv88fxx81() (machine_arch_type == MACH_TYPE_MV88FXX81) +#else +# define machine_is_mv88fxx81() (0) +#endif + +#ifdef CONFIG_MACH_STMP36XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STMP36XX +# endif +# define machine_is_stmp36xx() (machine_arch_type == MACH_TYPE_STMP36XX) +#else +# define machine_is_stmp36xx() (0) +#endif + +#ifdef CONFIG_MACH_SXNI79524 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SXNI79524 +# endif +# define machine_is_sxni79524() (machine_arch_type == MACH_TYPE_SXNI79524) +#else +# define machine_is_sxni79524() (0) +#endif + +#ifdef CONFIG_MACH_AMS_DELTA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AMS_DELTA +# endif +# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) +#else +# define machine_is_ams_delta() (0) +#endif + +#ifdef CONFIG_MACH_URANIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_URANIUM +# endif +# define machine_is_uranium() (machine_arch_type == MACH_TYPE_URANIUM) +#else +# define machine_is_uranium() (0) +#endif + +#ifdef CONFIG_MACH_UCON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UCON +# endif +# define machine_is_ucon() (machine_arch_type == MACH_TYPE_UCON) +#else +# define machine_is_ucon() (0) +#endif + +#ifdef CONFIG_MACH_NAS100D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAS100D +# endif +# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) +#else +# define machine_is_nas100d() (0) +#endif + +#ifdef CONFIG_MACH_L083_1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_L083_1000 +# endif +# define machine_is_l083() (machine_arch_type == MACH_TYPE_L083_1000) +#else +# define machine_is_l083() (0) +#endif + +#ifdef CONFIG_MACH_EZX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX +# endif +# define machine_is_ezx() (machine_arch_type == MACH_TYPE_EZX) +#else +# define machine_is_ezx() (0) +#endif + +#ifdef CONFIG_MACH_PNX5220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX5220 +# endif +# define machine_is_pnx5220() (machine_arch_type == MACH_TYPE_PNX5220) +#else +# define machine_is_pnx5220() (0) +#endif + +#ifdef CONFIG_MACH_BUTTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUTTE +# endif +# define machine_is_butte() (machine_arch_type == MACH_TYPE_BUTTE) +#else +# define machine_is_butte() (0) +#endif + +#ifdef CONFIG_MACH_SRM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SRM2 +# endif +# define machine_is_srm2() (machine_arch_type == MACH_TYPE_SRM2) +#else +# define machine_is_srm2() (0) +#endif + +#ifdef CONFIG_MACH_DSBR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSBR +# endif +# define machine_is_dsbr() (machine_arch_type == MACH_TYPE_DSBR) +#else +# define machine_is_dsbr() (0) +#endif + +#ifdef CONFIG_MACH_CRYSTALBALL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRYSTALBALL +# endif +# define machine_is_crystalball() (machine_arch_type == MACH_TYPE_CRYSTALBALL) +#else +# define machine_is_crystalball() (0) +#endif + +#ifdef CONFIG_MACH_TINYPXA27X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINYPXA27X +# endif +# define machine_is_tinypxa27x() (machine_arch_type == MACH_TYPE_TINYPXA27X) +#else +# define machine_is_tinypxa27x() (0) +#endif + +#ifdef CONFIG_MACH_HERBIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERBIE +# endif +# define machine_is_herbie() (machine_arch_type == MACH_TYPE_HERBIE) +#else +# define machine_is_herbie() (0) +#endif + +#ifdef CONFIG_MACH_MAGICIAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGICIAN +# endif +# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) +#else +# define machine_is_magician() (0) +#endif + +#ifdef CONFIG_MACH_CM4002 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM4002 +# endif +# define machine_is_cm4002() (machine_arch_type == MACH_TYPE_CM4002) +#else +# define machine_is_cm4002() (0) +#endif + +#ifdef CONFIG_MACH_B4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_B4 +# endif +# define machine_is_b4() (machine_arch_type == MACH_TYPE_B4) +#else +# define machine_is_b4() (0) +#endif + +#ifdef CONFIG_MACH_MAUI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAUI +# endif +# define machine_is_maui() (machine_arch_type == MACH_TYPE_MAUI) +#else +# define machine_is_maui() (0) +#endif + +#ifdef CONFIG_MACH_CYBERTRACKER_G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBERTRACKER_G +# endif +# define machine_is_cybertracker_g() (machine_arch_type == MACH_TYPE_CYBERTRACKER_G) +#else +# define machine_is_cybertracker_g() (0) +#endif + +#ifdef CONFIG_MACH_NXDKN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXDKN +# endif +# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) +#else +# define machine_is_nxdkn() (0) +#endif + +#ifdef CONFIG_MACH_MIO8390 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIO8390 +# endif +# define machine_is_mio8390() (machine_arch_type == MACH_TYPE_MIO8390) +#else +# define machine_is_mio8390() (0) +#endif + +#ifdef CONFIG_MACH_OMI_BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMI_BOARD +# endif +# define machine_is_omi_board() (machine_arch_type == MACH_TYPE_OMI_BOARD) +#else +# define machine_is_omi_board() (0) +#endif + +#ifdef CONFIG_MACH_MX21CIV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX21CIV +# endif +# define machine_is_mx21civ() (machine_arch_type == MACH_TYPE_MX21CIV) +#else +# define machine_is_mx21civ() (0) +#endif + +#ifdef CONFIG_MACH_MAHI_CDAC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAHI_CDAC +# endif +# define machine_is_mahi_cdac() (machine_arch_type == MACH_TYPE_MAHI_CDAC) +#else +# define machine_is_mahi_cdac() (0) +#endif + +#ifdef CONFIG_MACH_PALMTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMTX +# endif +# define machine_is_palmtx() (machine_arch_type == MACH_TYPE_PALMTX) +#else +# define machine_is_palmtx() (0) +#endif + +#ifdef CONFIG_MACH_S3C2413 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2413 +# endif +# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) +#else +# define machine_is_s3c2413() (0) +#endif + +#ifdef CONFIG_MACH_SAMSYS_EP0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAMSYS_EP0 +# endif +# define machine_is_samsys_ep0() (machine_arch_type == MACH_TYPE_SAMSYS_EP0) +#else +# define machine_is_samsys_ep0() (0) +#endif + +#ifdef CONFIG_MACH_WG302V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WG302V1 +# endif +# define machine_is_wg302v1() (machine_arch_type == MACH_TYPE_WG302V1) +#else +# define machine_is_wg302v1() (0) +#endif + +#ifdef CONFIG_MACH_WG302V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WG302V2 +# endif +# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) +#else +# define machine_is_wg302v2() (0) +#endif + +#ifdef CONFIG_MACH_EB42X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EB42X +# endif +# define machine_is_eb42x() (machine_arch_type == MACH_TYPE_EB42X) +#else +# define machine_is_eb42x() (0) +#endif + +#ifdef CONFIG_MACH_IQ331ES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ331ES +# endif +# define machine_is_iq331es() (machine_arch_type == MACH_TYPE_IQ331ES) +#else +# define machine_is_iq331es() (0) +#endif + +#ifdef CONFIG_MACH_COSYDSP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COSYDSP +# endif +# define machine_is_cosydsp() (machine_arch_type == MACH_TYPE_COSYDSP) +#else +# define machine_is_cosydsp() (0) +#endif + +#ifdef CONFIG_MACH_UPLAT7D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UPLAT7D +# endif +# define machine_is_uplat7d_proto() (machine_arch_type == MACH_TYPE_UPLAT7D) +#else +# define machine_is_uplat7d_proto() (0) +#endif + +#ifdef CONFIG_MACH_PTDAVINCI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTDAVINCI +# endif +# define machine_is_ptdavinci() (machine_arch_type == MACH_TYPE_PTDAVINCI) +#else +# define machine_is_ptdavinci() (0) +#endif + +#ifdef CONFIG_MACH_MBUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MBUS +# endif +# define machine_is_mbus() (machine_arch_type == MACH_TYPE_MBUS) +#else +# define machine_is_mbus() (0) +#endif + +#ifdef CONFIG_MACH_NADIA2VB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NADIA2VB +# endif +# define machine_is_nadia2vb() (machine_arch_type == MACH_TYPE_NADIA2VB) +#else +# define machine_is_nadia2vb() (0) +#endif + +#ifdef CONFIG_MACH_R1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_R1000 +# endif +# define machine_is_r1000() (machine_arch_type == MACH_TYPE_R1000) +#else +# define machine_is_r1000() (0) +#endif + +#ifdef CONFIG_MACH_HW90250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90250 +# endif +# define machine_is_hw90250() (machine_arch_type == MACH_TYPE_HW90250) +#else +# define machine_is_hw90250() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_2430SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_2430SDP +# endif +# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) +#else +# define machine_is_omap_2430sdp() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_EVM +# endif +# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) +#else +# define machine_is_davinci_evm() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_TORNADO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_TORNADO +# endif +# define machine_is_omap_tornado() (machine_arch_type == MACH_TYPE_OMAP_TORNADO) +#else +# define machine_is_omap_tornado() (0) +#endif + +#ifdef CONFIG_MACH_OLOCREEK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLOCREEK +# endif +# define machine_is_olocreek() (machine_arch_type == MACH_TYPE_OLOCREEK) +#else +# define machine_is_olocreek() (0) +#endif + +#ifdef CONFIG_MACH_PALMZ72 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMZ72 +# endif +# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) +#else +# define machine_is_palmz72() (0) +#endif + +#ifdef CONFIG_MACH_NXDB500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXDB500 +# endif +# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) +#else +# define machine_is_nxdb500() (0) +#endif + +#ifdef CONFIG_MACH_APF9328 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APF9328 +# endif +# define machine_is_apf9328() (machine_arch_type == MACH_TYPE_APF9328) +#else +# define machine_is_apf9328() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_WIPOQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_WIPOQ +# endif +# define machine_is_omap_wipoq() (machine_arch_type == MACH_TYPE_OMAP_WIPOQ) +#else +# define machine_is_omap_wipoq() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_TWIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_TWIP +# endif +# define machine_is_omap_twip() (machine_arch_type == MACH_TYPE_OMAP_TWIP) +#else +# define machine_is_omap_twip() (0) +#endif + +#ifdef CONFIG_MACH_TREO650 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TREO650 +# endif +# define machine_is_treo650() (machine_arch_type == MACH_TYPE_TREO650) +#else +# define machine_is_treo650() (0) +#endif + +#ifdef CONFIG_MACH_ACUMEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACUMEN +# endif +# define machine_is_acumen() (machine_arch_type == MACH_TYPE_ACUMEN) +#else +# define machine_is_acumen() (0) +#endif + +#ifdef CONFIG_MACH_XP100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XP100 +# endif +# define machine_is_xp100() (machine_arch_type == MACH_TYPE_XP100) +#else +# define machine_is_xp100() (0) +#endif + +#ifdef CONFIG_MACH_FS2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FS2410 +# endif +# define machine_is_fs2410() (machine_arch_type == MACH_TYPE_FS2410) +#else +# define machine_is_fs2410() (0) +#endif + +#ifdef CONFIG_MACH_PXA270_CERF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA270_CERF +# endif +# define machine_is_pxa270_cerf() (machine_arch_type == MACH_TYPE_PXA270_CERF) +#else +# define machine_is_pxa270_cerf() (0) +#endif + +#ifdef CONFIG_MACH_SQ2FTLPALM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SQ2FTLPALM +# endif +# define machine_is_sq2ftlpalm() (machine_arch_type == MACH_TYPE_SQ2FTLPALM) +#else +# define machine_is_sq2ftlpalm() (0) +#endif + +#ifdef CONFIG_MACH_BSEMSERVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSEMSERVER +# endif +# define machine_is_bsemserver() (machine_arch_type == MACH_TYPE_BSEMSERVER) +#else +# define machine_is_bsemserver() (0) +#endif + +#ifdef CONFIG_MACH_NETCLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETCLIENT +# endif +# define machine_is_netclient() (machine_arch_type == MACH_TYPE_NETCLIENT) +#else +# define machine_is_netclient() (0) +#endif + +#ifdef CONFIG_MACH_PALMT5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMT5 +# endif +# define machine_is_palmt5() (machine_arch_type == MACH_TYPE_PALMT5) +#else +# define machine_is_palmt5() (0) +#endif + +#ifdef CONFIG_MACH_PALMTC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMTC +# endif +# define machine_is_palmtc() (machine_arch_type == MACH_TYPE_PALMTC) +#else +# define machine_is_palmtc() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_APOLLON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_APOLLON +# endif +# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) +#else +# define machine_is_omap_apollon() (0) +#endif + +#ifdef CONFIG_MACH_MXC30030EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC30030EVB +# endif +# define machine_is_mxc30030evb() (machine_arch_type == MACH_TYPE_MXC30030EVB) +#else +# define machine_is_mxc30030evb() (0) +#endif + +#ifdef CONFIG_MACH_REA_2D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REA_2D +# endif +# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D) +#else +# define machine_is_rea_cpu2() (0) +#endif + +#ifdef CONFIG_MACH_TI3E524 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI3E524 +# endif +# define machine_is_eti3e524() (machine_arch_type == MACH_TYPE_TI3E524) +#else +# define machine_is_eti3e524() (0) +#endif + +#ifdef CONFIG_MACH_ATEB9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATEB9200 +# endif +# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) +#else +# define machine_is_ateb9200() (0) +#endif + +#ifdef CONFIG_MACH_AUCKLAND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUCKLAND +# endif +# define machine_is_auckland() (machine_arch_type == MACH_TYPE_AUCKLAND) +#else +# define machine_is_auckland() (0) +#endif + +#ifdef CONFIG_MACH_AK3320M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK3320M +# endif +# define machine_is_ak3220m() (machine_arch_type == MACH_TYPE_AK3320M) +#else +# define machine_is_ak3220m() (0) +#endif + +#ifdef CONFIG_MACH_DURAMAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DURAMAX +# endif +# define machine_is_duramax() (machine_arch_type == MACH_TYPE_DURAMAX) +#else +# define machine_is_duramax() (0) +#endif + +#ifdef CONFIG_MACH_N35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N35 +# endif +# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) +#else +# define machine_is_n35() (0) +#endif + +#ifdef CONFIG_MACH_PRONGHORN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRONGHORN +# endif +# define machine_is_pronghorn() (machine_arch_type == MACH_TYPE_PRONGHORN) +#else +# define machine_is_pronghorn() (0) +#endif + +#ifdef CONFIG_MACH_FUNDY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUNDY +# endif +# define machine_is_fundy() (machine_arch_type == MACH_TYPE_FUNDY) +#else +# define machine_is_fundy() (0) +#endif + +#ifdef CONFIG_MACH_LOGICPD_PXA270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 +# endif +# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) +#else +# define machine_is_logicpd_pxa270() (0) +#endif + +#ifdef CONFIG_MACH_CPU777 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPU777 +# endif +# define machine_is_cpu777() (machine_arch_type == MACH_TYPE_CPU777) +#else +# define machine_is_cpu777() (0) +#endif + +#ifdef CONFIG_MACH_SIMICON9201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMICON9201 +# endif +# define machine_is_simicon9201() (machine_arch_type == MACH_TYPE_SIMICON9201) +#else +# define machine_is_simicon9201() (0) +#endif + +#ifdef CONFIG_MACH_LEAP2_HPM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEAP2_HPM +# endif +# define machine_is_leap2_hpm() (machine_arch_type == MACH_TYPE_LEAP2_HPM) +#else +# define machine_is_leap2_hpm() (0) +#endif + +#ifdef CONFIG_MACH_CM922TXA10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM922TXA10 +# endif +# define machine_is_cm922txa10() (machine_arch_type == MACH_TYPE_CM922TXA10) +#else +# define machine_is_cm922txa10() (0) +#endif + +#ifdef CONFIG_MACH_PXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA +# endif +# define machine_is_sandgate() (machine_arch_type == MACH_TYPE_PXA) +#else +# define machine_is_sandgate() (0) +#endif + +#ifdef CONFIG_MACH_SANDGATE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDGATE2 +# endif +# define machine_is_sandgate2() (machine_arch_type == MACH_TYPE_SANDGATE2) +#else +# define machine_is_sandgate2() (0) +#endif + +#ifdef CONFIG_MACH_SANDGATE2G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDGATE2G +# endif +# define machine_is_sandgate2g() (machine_arch_type == MACH_TYPE_SANDGATE2G) +#else +# define machine_is_sandgate2g() (0) +#endif + +#ifdef CONFIG_MACH_SANDGATE2P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDGATE2P +# endif +# define machine_is_sandgate2p() (machine_arch_type == MACH_TYPE_SANDGATE2P) +#else +# define machine_is_sandgate2p() (0) +#endif + +#ifdef CONFIG_MACH_FRED_JACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FRED_JACK +# endif +# define machine_is_fred_jack() (machine_arch_type == MACH_TYPE_FRED_JACK) +#else +# define machine_is_fred_jack() (0) +#endif + +#ifdef CONFIG_MACH_TTG_COLOR1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TTG_COLOR1 +# endif +# define machine_is_ttg_color1() (machine_arch_type == MACH_TYPE_TTG_COLOR1) +#else +# define machine_is_ttg_color1() (0) +#endif + +#ifdef CONFIG_MACH_NXEB500HMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXEB500HMI +# endif +# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) +#else +# define machine_is_nxeb500hmi() (0) +#endif + +#ifdef CONFIG_MACH_NETDCU8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETDCU8 +# endif +# define machine_is_netdcu8() (machine_arch_type == MACH_TYPE_NETDCU8) +#else +# define machine_is_netdcu8() (0) +#endif + +#ifdef CONFIG_MACH_NG_FVX538 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NG_FVX538 +# endif +# define machine_is_ng_fvx538() (machine_arch_type == MACH_TYPE_NG_FVX538) +#else +# define machine_is_ng_fvx538() (0) +#endif + +#ifdef CONFIG_MACH_NG_FVS338 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NG_FVS338 +# endif +# define machine_is_ng_fvs338() (machine_arch_type == MACH_TYPE_NG_FVS338) +#else +# define machine_is_ng_fvs338() (0) +#endif + +#ifdef CONFIG_MACH_PNX4103 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX4103 +# endif +# define machine_is_pnx4103() (machine_arch_type == MACH_TYPE_PNX4103) +#else +# define machine_is_pnx4103() (0) +#endif + +#ifdef CONFIG_MACH_HESDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HESDB +# endif +# define machine_is_hesdb() (machine_arch_type == MACH_TYPE_HESDB) +#else +# define machine_is_hesdb() (0) +#endif + +#ifdef CONFIG_MACH_XSILO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSILO +# endif +# define machine_is_xsilo() (machine_arch_type == MACH_TYPE_XSILO) +#else +# define machine_is_xsilo() (0) +#endif + +#ifdef CONFIG_MACH_ESPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESPRESSO +# endif +# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) +#else +# define machine_is_espresso() (0) +#endif + +#ifdef CONFIG_MACH_EMLC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMLC +# endif +# define machine_is_emlc() (machine_arch_type == MACH_TYPE_EMLC) +#else +# define machine_is_emlc() (0) +#endif + +#ifdef CONFIG_MACH_SISTERON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SISTERON +# endif +# define machine_is_sisteron() (machine_arch_type == MACH_TYPE_SISTERON) +#else +# define machine_is_sisteron() (0) +#endif + +#ifdef CONFIG_MACH_RX1950 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RX1950 +# endif +# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) +#else +# define machine_is_rx1950() (0) +#endif + +#ifdef CONFIG_MACH_TSC_VENUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TSC_VENUS +# endif +# define machine_is_tsc_venus() (machine_arch_type == MACH_TYPE_TSC_VENUS) +#else +# define machine_is_tsc_venus() (0) +#endif + +#ifdef CONFIG_MACH_DS101J +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS101J +# endif +# define machine_is_ds101j() (machine_arch_type == MACH_TYPE_DS101J) +#else +# define machine_is_ds101j() (0) +#endif + +#ifdef CONFIG_MACH_MXC30030ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC30030ADS +# endif +# define machine_is_mxc30030ads() (machine_arch_type == MACH_TYPE_MXC30030ADS) +#else +# define machine_is_mxc30030ads() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_WIMAXSOC +# endif +# define machine_is_fujitsu_wimaxsoc() (machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC) +#else +# define machine_is_fujitsu_wimaxsoc() (0) +#endif + +#ifdef CONFIG_MACH_DUALPCMODEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DUALPCMODEM +# endif +# define machine_is_dualpcmodem() (machine_arch_type == MACH_TYPE_DUALPCMODEM) +#else +# define machine_is_dualpcmodem() (0) +#endif + +#ifdef CONFIG_MACH_GESBC9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GESBC9312 +# endif +# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) +#else +# define machine_is_gesbc9312() (0) +#endif + +#ifdef CONFIG_MACH_HTCAPACHE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCAPACHE +# endif +# define machine_is_htcapache() (machine_arch_type == MACH_TYPE_HTCAPACHE) +#else +# define machine_is_htcapache() (0) +#endif + +#ifdef CONFIG_MACH_IXDP435 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP435 +# endif +# define machine_is_ixdp435() (machine_arch_type == MACH_TYPE_IXDP435) +#else +# define machine_is_ixdp435() (0) +#endif + +#ifdef CONFIG_MACH_CATPROVT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATPROVT100 +# endif +# define machine_is_catprovt100() (machine_arch_type == MACH_TYPE_CATPROVT100) +#else +# define machine_is_catprovt100() (0) +#endif + +#ifdef CONFIG_MACH_PICOTUX1XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOTUX1XX +# endif +# define machine_is_picotux1xx() (machine_arch_type == MACH_TYPE_PICOTUX1XX) +#else +# define machine_is_picotux1xx() (0) +#endif + +#ifdef CONFIG_MACH_PICOTUX2XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOTUX2XX +# endif +# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX) +#else +# define machine_is_picotux2xx() (0) +#endif + +#ifdef CONFIG_MACH_DSMG600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSMG600 +# endif +# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600) +#else +# define machine_is_dsmg600() (0) +#endif + +#ifdef CONFIG_MACH_EMPC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMPC2 +# endif +# define machine_is_empc2() (machine_arch_type == MACH_TYPE_EMPC2) +#else +# define machine_is_empc2() (0) +#endif + +#ifdef CONFIG_MACH_VENTURA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENTURA +# endif +# define machine_is_ventura() (machine_arch_type == MACH_TYPE_VENTURA) +#else +# define machine_is_ventura() (0) +#endif + +#ifdef CONFIG_MACH_PHIDGET_SBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHIDGET_SBC +# endif +# define machine_is_phidget_sbc() (machine_arch_type == MACH_TYPE_PHIDGET_SBC) +#else +# define machine_is_phidget_sbc() (0) +#endif + +#ifdef CONFIG_MACH_IJ3K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IJ3K +# endif +# define machine_is_ij3k() (machine_arch_type == MACH_TYPE_IJ3K) +#else +# define machine_is_ij3k() (0) +#endif + +#ifdef CONFIG_MACH_PISGAH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PISGAH +# endif +# define machine_is_pisgah() (machine_arch_type == MACH_TYPE_PISGAH) +#else +# define machine_is_pisgah() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_FSAMPLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE +# endif +# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE) +#else +# define machine_is_omap_fsample() (0) +#endif + +#ifdef CONFIG_MACH_SG720 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG720 +# endif +# define machine_is_sg720() (machine_arch_type == MACH_TYPE_SG720) +#else +# define machine_is_sg720() (0) +#endif + +#ifdef CONFIG_MACH_REDFOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REDFOX +# endif +# define machine_is_redfox() (machine_arch_type == MACH_TYPE_REDFOX) +#else +# define machine_is_redfox() (0) +#endif + +#ifdef CONFIG_MACH_MYSH_EP9315_1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MYSH_EP9315_1 +# endif +# define machine_is_mysh_ep9315_1() (machine_arch_type == MACH_TYPE_MYSH_EP9315_1) +#else +# define machine_is_mysh_ep9315_1() (0) +#endif + +#ifdef CONFIG_MACH_TPF106 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TPF106 +# endif +# define machine_is_tpf106() (machine_arch_type == MACH_TYPE_TPF106) +#else +# define machine_is_tpf106() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200KG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200KG +# endif +# define machine_is_at91rm9200kg() (machine_arch_type == MACH_TYPE_AT91RM9200KG) +#else +# define machine_is_at91rm9200kg() (0) +#endif + +#ifdef CONFIG_MACH_SLEDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SLEDB +# endif +# define machine_is_rcmt2() (machine_arch_type == MACH_TYPE_SLEDB) +#else +# define machine_is_rcmt2() (0) +#endif + +#ifdef CONFIG_MACH_ONTRACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ONTRACK +# endif +# define machine_is_ontrack() (machine_arch_type == MACH_TYPE_ONTRACK) +#else +# define machine_is_ontrack() (0) +#endif + +#ifdef CONFIG_MACH_PM1200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PM1200 +# endif +# define machine_is_pm1200() (machine_arch_type == MACH_TYPE_PM1200) +#else +# define machine_is_pm1200() (0) +#endif + +#ifdef CONFIG_MACH_ESS24XXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESS24XXX +# endif +# define machine_is_ess24562() (machine_arch_type == MACH_TYPE_ESS24XXX) +#else +# define machine_is_ess24562() (0) +#endif + +#ifdef CONFIG_MACH_COREMP7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COREMP7 +# endif +# define machine_is_coremp7() (machine_arch_type == MACH_TYPE_COREMP7) +#else +# define machine_is_coremp7() (0) +#endif + +#ifdef CONFIG_MACH_NEXCODER_6446 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXCODER_6446 +# endif +# define machine_is_nexcoder_6446() (machine_arch_type == MACH_TYPE_NEXCODER_6446) +#else +# define machine_is_nexcoder_6446() (0) +#endif + +#ifdef CONFIG_MACH_STVC8380 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STVC8380 +# endif +# define machine_is_stvc8380() (machine_arch_type == MACH_TYPE_STVC8380) +#else +# define machine_is_stvc8380() (0) +#endif + +#ifdef CONFIG_MACH_TEKLYNX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEKLYNX +# endif +# define machine_is_teklynx() (machine_arch_type == MACH_TYPE_TEKLYNX) +#else +# define machine_is_teklynx() (0) +#endif + +#ifdef CONFIG_MACH_CARBONADO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARBONADO +# endif +# define machine_is_carbonado() (machine_arch_type == MACH_TYPE_CARBONADO) +#else +# define machine_is_carbonado() (0) +#endif + +#ifdef CONFIG_MACH_SYSMOS_MP730 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYSMOS_MP730 +# endif +# define machine_is_sysmos_mp730() (machine_arch_type == MACH_TYPE_SYSMOS_MP730) +#else +# define machine_is_sysmos_mp730() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER_CL15 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER_CL15 +# endif +# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15) +#else +# define machine_is_snapper_cl15() (0) +#endif + +#ifdef CONFIG_MACH_PGIGIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PGIGIM +# endif +# define machine_is_pgigim() (machine_arch_type == MACH_TYPE_PGIGIM) +#else +# define machine_is_pgigim() (0) +#endif + +#ifdef CONFIG_MACH_PTX9160P2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTX9160P2 +# endif +# define machine_is_ptx9160p2() (machine_arch_type == MACH_TYPE_PTX9160P2) +#else +# define machine_is_ptx9160p2() (0) +#endif + +#ifdef CONFIG_MACH_DCORE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DCORE1 +# endif +# define machine_is_dcore1() (machine_arch_type == MACH_TYPE_DCORE1) +#else +# define machine_is_dcore1() (0) +#endif + +#ifdef CONFIG_MACH_VICTORPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VICTORPXA +# endif +# define machine_is_victorpxa() (machine_arch_type == MACH_TYPE_VICTORPXA) +#else +# define machine_is_victorpxa() (0) +#endif + +#ifdef CONFIG_MACH_MX2DTB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX2DTB +# endif +# define machine_is_mx2dtb() (machine_arch_type == MACH_TYPE_MX2DTB) +#else +# define machine_is_mx2dtb() (0) +#endif + +#ifdef CONFIG_MACH_PXA_IREX_ER0100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_IREX_ER0100 +# endif +# define machine_is_pxa_irex_er0100() (machine_arch_type == MACH_TYPE_PXA_IREX_ER0100) +#else +# define machine_is_pxa_irex_er0100() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PALMZ71 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PALMZ71 +# endif +# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71) +#else +# define machine_is_omap_palmz71() (0) +#endif + +#ifdef CONFIG_MACH_BARTEC_DEG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BARTEC_DEG +# endif +# define machine_is_bartec_deg() (machine_arch_type == MACH_TYPE_BARTEC_DEG) +#else +# define machine_is_bartec_deg() (0) +#endif + +#ifdef CONFIG_MACH_HW50251 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW50251 +# endif +# define machine_is_hw50251() (machine_arch_type == MACH_TYPE_HW50251) +#else +# define machine_is_hw50251() (0) +#endif + +#ifdef CONFIG_MACH_IBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IBOX +# endif +# define machine_is_ibox() (machine_arch_type == MACH_TYPE_IBOX) +#else +# define machine_is_ibox() (0) +#endif + +#ifdef CONFIG_MACH_ATLASLH7A404 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLASLH7A404 +# endif +# define machine_is_atlaslh7a404() (machine_arch_type == MACH_TYPE_ATLASLH7A404) +#else +# define machine_is_atlaslh7a404() (0) +#endif + +#ifdef CONFIG_MACH_PT2026 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PT2026 +# endif +# define machine_is_pt2026() (machine_arch_type == MACH_TYPE_PT2026) +#else +# define machine_is_pt2026() (0) +#endif + +#ifdef CONFIG_MACH_HTCALPINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCALPINE +# endif +# define machine_is_htcalpine() (machine_arch_type == MACH_TYPE_HTCALPINE) +#else +# define machine_is_htcalpine() (0) +#endif + +#ifdef CONFIG_MACH_BARTEC_VTU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BARTEC_VTU +# endif +# define machine_is_bartec_vtu() (machine_arch_type == MACH_TYPE_BARTEC_VTU) +#else +# define machine_is_bartec_vtu() (0) +#endif + +#ifdef CONFIG_MACH_VCOREII +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VCOREII +# endif +# define machine_is_vcoreii() (machine_arch_type == MACH_TYPE_VCOREII) +#else +# define machine_is_vcoreii() (0) +#endif + +#ifdef CONFIG_MACH_PDNB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDNB3 +# endif +# define machine_is_pdnb3() (machine_arch_type == MACH_TYPE_PDNB3) +#else +# define machine_is_pdnb3() (0) +#endif + +#ifdef CONFIG_MACH_HTCBEETLES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCBEETLES +# endif +# define machine_is_htcbeetles() (machine_arch_type == MACH_TYPE_HTCBEETLES) +#else +# define machine_is_htcbeetles() (0) +#endif + +#ifdef CONFIG_MACH_S3C6400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C6400 +# endif +# define machine_is_s3c6400() (machine_arch_type == MACH_TYPE_S3C6400) +#else +# define machine_is_s3c6400() (0) +#endif + +#ifdef CONFIG_MACH_S3C2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2443 +# endif +# define machine_is_s3c2443() (machine_arch_type == MACH_TYPE_S3C2443) +#else +# define machine_is_s3c2443() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_LDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_LDK +# endif +# define machine_is_omap_ldk() (machine_arch_type == MACH_TYPE_OMAP_LDK) +#else +# define machine_is_omap_ldk() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2460 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2460 +# endif +# define machine_is_smdk2460() (machine_arch_type == MACH_TYPE_SMDK2460) +#else +# define machine_is_smdk2460() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2440 +# endif +# define machine_is_smdk2440() (machine_arch_type == MACH_TYPE_SMDK2440) +#else +# define machine_is_smdk2440() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2412 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2412 +# endif +# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412) +#else +# define machine_is_smdk2412() (0) +#endif + +#ifdef CONFIG_MACH_WEBBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEBBOX +# endif +# define machine_is_webbox() (machine_arch_type == MACH_TYPE_WEBBOX) +#else +# define machine_is_webbox() (0) +#endif + +#ifdef CONFIG_MACH_CWWNDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWWNDP +# endif +# define machine_is_cwwndp() (machine_arch_type == MACH_TYPE_CWWNDP) +#else +# define machine_is_cwwndp() (0) +#endif + +#ifdef CONFIG_MACH_DRAGON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DRAGON +# endif +# define machine_is_i839() (machine_arch_type == MACH_TYPE_DRAGON) +#else +# define machine_is_i839() (0) +#endif + +#ifdef CONFIG_MACH_OPENDO_CPU_BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENDO_CPU_BOARD +# endif +# define machine_is_opendo_cpu_board() (machine_arch_type == MACH_TYPE_OPENDO_CPU_BOARD) +#else +# define machine_is_opendo_cpu_board() (0) +#endif + +#ifdef CONFIG_MACH_CCM2200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCM2200 +# endif +# define machine_is_ccm2200() (machine_arch_type == MACH_TYPE_CCM2200) +#else +# define machine_is_ccm2200() (0) +#endif + +#ifdef CONFIG_MACH_ETWARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETWARM +# endif +# define machine_is_etwarm() (machine_arch_type == MACH_TYPE_ETWARM) +#else +# define machine_is_etwarm() (0) +#endif + +#ifdef CONFIG_MACH_M93030 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M93030 +# endif +# define machine_is_m93030() (machine_arch_type == MACH_TYPE_M93030) +#else +# define machine_is_m93030() (0) +#endif + +#ifdef CONFIG_MACH_CC7U +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC7U +# endif +# define machine_is_cc7u() (machine_arch_type == MACH_TYPE_CC7U) +#else +# define machine_is_cc7u() (0) +#endif + +#ifdef CONFIG_MACH_MTT_RANGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MTT_RANGER +# endif +# define machine_is_mtt_ranger() (machine_arch_type == MACH_TYPE_MTT_RANGER) +#else +# define machine_is_mtt_ranger() (0) +#endif + +#ifdef CONFIG_MACH_NEXUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXUS +# endif +# define machine_is_nexus() (machine_arch_type == MACH_TYPE_NEXUS) +#else +# define machine_is_nexus() (0) +#endif + +#ifdef CONFIG_MACH_DESMAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DESMAN +# endif +# define machine_is_desman() (machine_arch_type == MACH_TYPE_DESMAN) +#else +# define machine_is_desman() (0) +#endif + +#ifdef CONFIG_MACH_BKDE303 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BKDE303 +# endif +# define machine_is_bkde303() (machine_arch_type == MACH_TYPE_BKDE303) +#else +# define machine_is_bkde303() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2413 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2413 +# endif +# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413) +#else +# define machine_is_smdk2413() (0) +#endif + +#ifdef CONFIG_MACH_AML_M7200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AML_M7200 +# endif +# define machine_is_aml_m7200() (machine_arch_type == MACH_TYPE_AML_M7200) +#else +# define machine_is_aml_m7200() (0) +#endif + +#ifdef CONFIG_MACH_AML_M5900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AML_M5900 +# endif +# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900) +#else +# define machine_is_aml_m5900() (0) +#endif + +#ifdef CONFIG_MACH_SG640 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG640 +# endif +# define machine_is_sg640() (machine_arch_type == MACH_TYPE_SG640) +#else +# define machine_is_sg640() (0) +#endif + +#ifdef CONFIG_MACH_EDG79524 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDG79524 +# endif +# define machine_is_edg79524() (machine_arch_type == MACH_TYPE_EDG79524) +#else +# define machine_is_edg79524() (0) +#endif + +#ifdef CONFIG_MACH_AI2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AI2410 +# endif +# define machine_is_ai2410() (machine_arch_type == MACH_TYPE_AI2410) +#else +# define machine_is_ai2410() (0) +#endif + +#ifdef CONFIG_MACH_IXP465 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP465 +# endif +# define machine_is_ixp465() (machine_arch_type == MACH_TYPE_IXP465) +#else +# define machine_is_ixp465() (0) +#endif + +#ifdef CONFIG_MACH_BALLOON3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BALLOON3 +# endif +# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) +#else +# define machine_is_balloon3() (0) +#endif + +#ifdef CONFIG_MACH_HEINS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HEINS +# endif +# define machine_is_heins() (machine_arch_type == MACH_TYPE_HEINS) +#else +# define machine_is_heins() (0) +#endif + +#ifdef CONFIG_MACH_MPLUSEVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPLUSEVA +# endif +# define machine_is_mpluseva() (machine_arch_type == MACH_TYPE_MPLUSEVA) +#else +# define machine_is_mpluseva() (0) +#endif + +#ifdef CONFIG_MACH_RT042 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RT042 +# endif +# define machine_is_rt042() (machine_arch_type == MACH_TYPE_RT042) +#else +# define machine_is_rt042() (0) +#endif + +#ifdef CONFIG_MACH_CWIEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWIEM +# endif +# define machine_is_cwiem() (machine_arch_type == MACH_TYPE_CWIEM) +#else +# define machine_is_cwiem() (0) +#endif + +#ifdef CONFIG_MACH_CM_X270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_X270 +# endif +# define machine_is_cm_x270() (machine_arch_type == MACH_TYPE_CM_X270) +#else +# define machine_is_cm_x270() (0) +#endif + +#ifdef CONFIG_MACH_CM_X255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_X255 +# endif +# define machine_is_cm_x255() (machine_arch_type == MACH_TYPE_CM_X255) +#else +# define machine_is_cm_x255() (0) +#endif + +#ifdef CONFIG_MACH_ESH_AT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESH_AT91 +# endif +# define machine_is_esh_at91() (machine_arch_type == MACH_TYPE_ESH_AT91) +#else +# define machine_is_esh_at91() (0) +#endif + +#ifdef CONFIG_MACH_SANDGATE3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDGATE3 +# endif +# define machine_is_sandgate3() (machine_arch_type == MACH_TYPE_SANDGATE3) +#else +# define machine_is_sandgate3() (0) +#endif + +#ifdef CONFIG_MACH_PRIMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRIMO +# endif +# define machine_is_primo() (machine_arch_type == MACH_TYPE_PRIMO) +#else +# define machine_is_primo() (0) +#endif + +#ifdef CONFIG_MACH_GEMSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMSTONE +# endif +# define machine_is_gemstone() (machine_arch_type == MACH_TYPE_GEMSTONE) +#else +# define machine_is_gemstone() (0) +#endif + +#ifdef CONFIG_MACH_PRONGHORNMETRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRONGHORNMETRO +# endif +# define machine_is_pronghorn_metro() (machine_arch_type == MACH_TYPE_PRONGHORNMETRO) +#else +# define machine_is_pronghorn_metro() (0) +#endif + +#ifdef CONFIG_MACH_SIDEWINDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIDEWINDER +# endif +# define machine_is_sidewinder() (machine_arch_type == MACH_TYPE_SIDEWINDER) +#else +# define machine_is_sidewinder() (0) +#endif + +#ifdef CONFIG_MACH_PICOMOD1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOMOD1 +# endif +# define machine_is_picomod1() (machine_arch_type == MACH_TYPE_PICOMOD1) +#else +# define machine_is_picomod1() (0) +#endif + +#ifdef CONFIG_MACH_SG590 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG590 +# endif +# define machine_is_sg590() (machine_arch_type == MACH_TYPE_SG590) +#else +# define machine_is_sg590() (0) +#endif + +#ifdef CONFIG_MACH_AKAI9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AKAI9307 +# endif +# define machine_is_akai9307() (machine_arch_type == MACH_TYPE_AKAI9307) +#else +# define machine_is_akai9307() (0) +#endif + +#ifdef CONFIG_MACH_FONTAINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FONTAINE +# endif +# define machine_is_fontaine() (machine_arch_type == MACH_TYPE_FONTAINE) +#else +# define machine_is_fontaine() (0) +#endif + +#ifdef CONFIG_MACH_WOMBAT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WOMBAT +# endif +# define machine_is_wombat() (machine_arch_type == MACH_TYPE_WOMBAT) +#else +# define machine_is_wombat() (0) +#endif + +#ifdef CONFIG_MACH_ACQ300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACQ300 +# endif +# define machine_is_acq300() (machine_arch_type == MACH_TYPE_ACQ300) +#else +# define machine_is_acq300() (0) +#endif + +#ifdef CONFIG_MACH_MOD_270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOD_270 +# endif +# define machine_is_mod272() (machine_arch_type == MACH_TYPE_MOD_270) +#else +# define machine_is_mod272() (0) +#endif + +#ifdef CONFIG_MACH_VC0820 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC0820 +# endif +# define machine_is_vmc_vc0820() (machine_arch_type == MACH_TYPE_VC0820) +#else +# define machine_is_vmc_vc0820() (0) +#endif + +#ifdef CONFIG_MACH_ANI_AIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANI_AIM +# endif +# define machine_is_ani_aim() (machine_arch_type == MACH_TYPE_ANI_AIM) +#else +# define machine_is_ani_aim() (0) +#endif + +#ifdef CONFIG_MACH_JELLYFISH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JELLYFISH +# endif +# define machine_is_jellyfish() (machine_arch_type == MACH_TYPE_JELLYFISH) +#else +# define machine_is_jellyfish() (0) +#endif + +#ifdef CONFIG_MACH_AMANITA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AMANITA +# endif +# define machine_is_amanita() (machine_arch_type == MACH_TYPE_AMANITA) +#else +# define machine_is_amanita() (0) +#endif + +#ifdef CONFIG_MACH_VLINK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VLINK +# endif +# define machine_is_vlink() (machine_arch_type == MACH_TYPE_VLINK) +#else +# define machine_is_vlink() (0) +#endif + +#ifdef CONFIG_MACH_DEXFLEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEXFLEX +# endif +# define machine_is_dexflex() (machine_arch_type == MACH_TYPE_DEXFLEX) +#else +# define machine_is_dexflex() (0) +#endif + +#ifdef CONFIG_MACH_EIGEN_TTQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EIGEN_TTQ +# endif +# define machine_is_eigen_ttq() (machine_arch_type == MACH_TYPE_EIGEN_TTQ) +#else +# define machine_is_eigen_ttq() (0) +#endif + +#ifdef CONFIG_MACH_ARCOM_TITAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCOM_TITAN +# endif +# define machine_is_arcom_titan() (machine_arch_type == MACH_TYPE_ARCOM_TITAN) +#else +# define machine_is_arcom_titan() (0) +#endif + +#ifdef CONFIG_MACH_TABLA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TABLA +# endif +# define machine_is_tabla() (machine_arch_type == MACH_TYPE_TABLA) +#else +# define machine_is_tabla() (0) +#endif + +#ifdef CONFIG_MACH_MDIRAC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MDIRAC3 +# endif +# define machine_is_mdirac3() (machine_arch_type == MACH_TYPE_MDIRAC3) +#else +# define machine_is_mdirac3() (0) +#endif + +#ifdef CONFIG_MACH_MRHFBP2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MRHFBP2 +# endif +# define machine_is_mrhfbp2() (machine_arch_type == MACH_TYPE_MRHFBP2) +#else +# define machine_is_mrhfbp2() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200RB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200RB +# endif +# define machine_is_at91rm9200rb() (machine_arch_type == MACH_TYPE_AT91RM9200RB) +#else +# define machine_is_at91rm9200rb() (0) +#endif + +#ifdef CONFIG_MACH_ANI_APM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANI_APM +# endif +# define machine_is_ani_apm() (machine_arch_type == MACH_TYPE_ANI_APM) +#else +# define machine_is_ani_apm() (0) +#endif + +#ifdef CONFIG_MACH_ELLA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELLA1 +# endif +# define machine_is_ella1() (machine_arch_type == MACH_TYPE_ELLA1) +#else +# define machine_is_ella1() (0) +#endif + +#ifdef CONFIG_MACH_INHAND_PXA27X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHAND_PXA27X +# endif +# define machine_is_inhand_pxa27x() (machine_arch_type == MACH_TYPE_INHAND_PXA27X) +#else +# define machine_is_inhand_pxa27x() (0) +#endif + +#ifdef CONFIG_MACH_INHAND_PXA25X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHAND_PXA25X +# endif +# define machine_is_inhand_pxa25x() (machine_arch_type == MACH_TYPE_INHAND_PXA25X) +#else +# define machine_is_inhand_pxa25x() (0) +#endif + +#ifdef CONFIG_MACH_EMPOS_XM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMPOS_XM +# endif +# define machine_is_empos_xm() (machine_arch_type == MACH_TYPE_EMPOS_XM) +#else +# define machine_is_empos_xm() (0) +#endif + +#ifdef CONFIG_MACH_EMPOS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMPOS +# endif +# define machine_is_empos() (machine_arch_type == MACH_TYPE_EMPOS) +#else +# define machine_is_empos() (0) +#endif + +#ifdef CONFIG_MACH_EMPOS_TINY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMPOS_TINY +# endif +# define machine_is_empos_tiny() (machine_arch_type == MACH_TYPE_EMPOS_TINY) +#else +# define machine_is_empos_tiny() (0) +#endif + +#ifdef CONFIG_MACH_EMPOS_SM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMPOS_SM +# endif +# define machine_is_empos_sm() (machine_arch_type == MACH_TYPE_EMPOS_SM) +#else +# define machine_is_empos_sm() (0) +#endif + +#ifdef CONFIG_MACH_EGRET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EGRET +# endif +# define machine_is_egret() (machine_arch_type == MACH_TYPE_EGRET) +#else +# define machine_is_egret() (0) +#endif + +#ifdef CONFIG_MACH_OSTRICH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OSTRICH +# endif +# define machine_is_ostrich() (machine_arch_type == MACH_TYPE_OSTRICH) +#else +# define machine_is_ostrich() (0) +#endif + +#ifdef CONFIG_MACH_N50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N50 +# endif +# define machine_is_n50() (machine_arch_type == MACH_TYPE_N50) +#else +# define machine_is_n50() (0) +#endif + +#ifdef CONFIG_MACH_ECBAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECBAT91 +# endif +# define machine_is_ecbat91() (machine_arch_type == MACH_TYPE_ECBAT91) +#else +# define machine_is_ecbat91() (0) +#endif + +#ifdef CONFIG_MACH_STAREAST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAREAST +# endif +# define machine_is_stareast() (machine_arch_type == MACH_TYPE_STAREAST) +#else +# define machine_is_stareast() (0) +#endif + +#ifdef CONFIG_MACH_DSPG_DW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSPG_DW +# endif +# define machine_is_dspg_dw() (machine_arch_type == MACH_TYPE_DSPG_DW) +#else +# define machine_is_dspg_dw() (0) +#endif + +#ifdef CONFIG_MACH_ONEARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ONEARM +# endif +# define machine_is_onearm() (machine_arch_type == MACH_TYPE_ONEARM) +#else +# define machine_is_onearm() (0) +#endif + +#ifdef CONFIG_MACH_MRG110_6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MRG110_6 +# endif +# define machine_is_mrg110_6() (machine_arch_type == MACH_TYPE_MRG110_6) +#else +# define machine_is_mrg110_6() (0) +#endif + +#ifdef CONFIG_MACH_WRT300NV2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WRT300NV2 +# endif +# define machine_is_wrt300nv2() (machine_arch_type == MACH_TYPE_WRT300NV2) +#else +# define machine_is_wrt300nv2() (0) +#endif + +#ifdef CONFIG_MACH_XM_BULVERDE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XM_BULVERDE +# endif +# define machine_is_xm_bulverde() (machine_arch_type == MACH_TYPE_XM_BULVERDE) +#else +# define machine_is_xm_bulverde() (0) +#endif + +#ifdef CONFIG_MACH_MSM6100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM6100 +# endif +# define machine_is_msm6100() (machine_arch_type == MACH_TYPE_MSM6100) +#else +# define machine_is_msm6100() (0) +#endif + +#ifdef CONFIG_MACH_ETI_B1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETI_B1 +# endif +# define machine_is_eti_b1() (machine_arch_type == MACH_TYPE_ETI_B1) +#else +# define machine_is_eti_b1() (0) +#endif + +#ifdef CONFIG_MACH_ZILOG_ZA9L +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZILOG_ZA9L +# endif +# define machine_is_za9l_series() (machine_arch_type == MACH_TYPE_ZILOG_ZA9L) +#else +# define machine_is_za9l_series() (0) +#endif + +#ifdef CONFIG_MACH_BIT2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIT2440 +# endif +# define machine_is_bit2440() (machine_arch_type == MACH_TYPE_BIT2440) +#else +# define machine_is_bit2440() (0) +#endif + +#ifdef CONFIG_MACH_NBI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NBI +# endif +# define machine_is_nbi() (machine_arch_type == MACH_TYPE_NBI) +#else +# define machine_is_nbi() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2443 +# endif +# define machine_is_smdk2443() (machine_arch_type == MACH_TYPE_SMDK2443) +#else +# define machine_is_smdk2443() (0) +#endif + +#ifdef CONFIG_MACH_VDAVINCI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VDAVINCI +# endif +# define machine_is_vdavinci() (machine_arch_type == MACH_TYPE_VDAVINCI) +#else +# define machine_is_vdavinci() (0) +#endif + +#ifdef CONFIG_MACH_ATC6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATC6 +# endif +# define machine_is_atc6() (machine_arch_type == MACH_TYPE_ATC6) +#else +# define machine_is_atc6() (0) +#endif + +#ifdef CONFIG_MACH_MULTMDW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTMDW +# endif +# define machine_is_multmdw() (machine_arch_type == MACH_TYPE_MULTMDW) +#else +# define machine_is_multmdw() (0) +#endif + +#ifdef CONFIG_MACH_MBA2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MBA2440 +# endif +# define machine_is_mba2440() (machine_arch_type == MACH_TYPE_MBA2440) +#else +# define machine_is_mba2440() (0) +#endif + +#ifdef CONFIG_MACH_ECSD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECSD +# endif +# define machine_is_ecsd() (machine_arch_type == MACH_TYPE_ECSD) +#else +# define machine_is_ecsd() (0) +#endif + +#ifdef CONFIG_MACH_PALMZ31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMZ31 +# endif +# define machine_is_palmz31() (machine_arch_type == MACH_TYPE_PALMZ31) +#else +# define machine_is_palmz31() (0) +#endif + +#ifdef CONFIG_MACH_FSG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FSG +# endif +# define machine_is_fsg() (machine_arch_type == MACH_TYPE_FSG) +#else +# define machine_is_fsg() (0) +#endif + +#ifdef CONFIG_MACH_RAZOR101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAZOR101 +# endif +# define machine_is_razor101() (machine_arch_type == MACH_TYPE_RAZOR101) +#else +# define machine_is_razor101() (0) +#endif + +#ifdef CONFIG_MACH_OPERA_TDM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPERA_TDM +# endif +# define machine_is_opera_tdm() (machine_arch_type == MACH_TYPE_OPERA_TDM) +#else +# define machine_is_opera_tdm() (0) +#endif + +#ifdef CONFIG_MACH_COMCERTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMCERTO +# endif +# define machine_is_comcerto() (machine_arch_type == MACH_TYPE_COMCERTO) +#else +# define machine_is_comcerto() (0) +#endif + +#ifdef CONFIG_MACH_TB0319 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TB0319 +# endif +# define machine_is_tb0319() (machine_arch_type == MACH_TYPE_TB0319) +#else +# define machine_is_tb0319() (0) +#endif + +#ifdef CONFIG_MACH_KWS8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KWS8000 +# endif +# define machine_is_kws8000() (machine_arch_type == MACH_TYPE_KWS8000) +#else +# define machine_is_kws8000() (0) +#endif + +#ifdef CONFIG_MACH_B2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_B2 +# endif +# define machine_is_b2() (machine_arch_type == MACH_TYPE_B2) +#else +# define machine_is_b2() (0) +#endif + +#ifdef CONFIG_MACH_LCL54 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LCL54 +# endif +# define machine_is_lcl54() (machine_arch_type == MACH_TYPE_LCL54) +#else +# define machine_is_lcl54() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9260EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9260EK +# endif +# define machine_is_at91sam9260ek() (machine_arch_type == MACH_TYPE_AT91SAM9260EK) +#else +# define machine_is_at91sam9260ek() (0) +#endif + +#ifdef CONFIG_MACH_GLANTANK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLANTANK +# endif +# define machine_is_glantank() (machine_arch_type == MACH_TYPE_GLANTANK) +#else +# define machine_is_glantank() (0) +#endif + +#ifdef CONFIG_MACH_N2100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N2100 +# endif +# define machine_is_n2100() (machine_arch_type == MACH_TYPE_N2100) +#else +# define machine_is_n2100() (0) +#endif + +#ifdef CONFIG_MACH_N4100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N4100 +# endif +# define machine_is_n4100() (machine_arch_type == MACH_TYPE_N4100) +#else +# define machine_is_n4100() (0) +#endif + +#ifdef CONFIG_MACH_VERTICAL_RSC4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VERTICAL_RSC4 +# endif +# define machine_is_rsc4() (machine_arch_type == MACH_TYPE_VERTICAL_RSC4) +#else +# define machine_is_rsc4() (0) +#endif + +#ifdef CONFIG_MACH_SG8100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG8100 +# endif +# define machine_is_sg8100() (machine_arch_type == MACH_TYPE_SG8100) +#else +# define machine_is_sg8100() (0) +#endif + +#ifdef CONFIG_MACH_IM42XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IM42XX +# endif +# define machine_is_im42xx() (machine_arch_type == MACH_TYPE_IM42XX) +#else +# define machine_is_im42xx() (0) +#endif + +#ifdef CONFIG_MACH_FTXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FTXX +# endif +# define machine_is_ftxx() (machine_arch_type == MACH_TYPE_FTXX) +#else +# define machine_is_ftxx() (0) +#endif + +#ifdef CONFIG_MACH_LWFUSION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LWFUSION +# endif +# define machine_is_lwfusion() (machine_arch_type == MACH_TYPE_LWFUSION) +#else +# define machine_is_lwfusion() (0) +#endif + +#ifdef CONFIG_MACH_QT2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QT2410 +# endif +# define machine_is_qt2410() (machine_arch_type == MACH_TYPE_QT2410) +#else +# define machine_is_qt2410() (0) +#endif + +#ifdef CONFIG_MACH_KIXRP435 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIXRP435 +# endif +# define machine_is_kixrp435() (machine_arch_type == MACH_TYPE_KIXRP435) +#else +# define machine_is_kixrp435() (0) +#endif + +#ifdef CONFIG_MACH_CCW9C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9C +# endif +# define machine_is_ccw9c() (machine_arch_type == MACH_TYPE_CCW9C) +#else +# define machine_is_ccw9c() (0) +#endif + +#ifdef CONFIG_MACH_DABHS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DABHS +# endif +# define machine_is_dabhs() (machine_arch_type == MACH_TYPE_DABHS) +#else +# define machine_is_dabhs() (0) +#endif + +#ifdef CONFIG_MACH_GZMX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GZMX +# endif +# define machine_is_gzmx() (machine_arch_type == MACH_TYPE_GZMX) +#else +# define machine_is_gzmx() (0) +#endif + +#ifdef CONFIG_MACH_IPNW100AP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPNW100AP +# endif +# define machine_is_ipnw100ap() (machine_arch_type == MACH_TYPE_IPNW100AP) +#else +# define machine_is_ipnw100ap() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9360DEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9360DEV +# endif +# define machine_is_cc9p9360dev() (machine_arch_type == MACH_TYPE_CC9P9360DEV) +#else +# define machine_is_cc9p9360dev() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9750DEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9750DEV +# endif +# define machine_is_cc9p9750dev() (machine_arch_type == MACH_TYPE_CC9P9750DEV) +#else +# define machine_is_cc9p9750dev() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9360VAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9360VAL +# endif +# define machine_is_cc9p9360val() (machine_arch_type == MACH_TYPE_CC9P9360VAL) +#else +# define machine_is_cc9p9360val() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9750VAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9750VAL +# endif +# define machine_is_cc9p9750val() (machine_arch_type == MACH_TYPE_CC9P9750VAL) +#else +# define machine_is_cc9p9750val() (0) +#endif + +#ifdef CONFIG_MACH_NX70V +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NX70V +# endif +# define machine_is_nx70v() (machine_arch_type == MACH_TYPE_NX70V) +#else +# define machine_is_nx70v() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200DF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200DF +# endif +# define machine_is_at91rm9200df() (machine_arch_type == MACH_TYPE_AT91RM9200DF) +#else +# define machine_is_at91rm9200df() (0) +#endif + +#ifdef CONFIG_MACH_SE_PILOT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SE_PILOT2 +# endif +# define machine_is_se_pilot2() (machine_arch_type == MACH_TYPE_SE_PILOT2) +#else +# define machine_is_se_pilot2() (0) +#endif + +#ifdef CONFIG_MACH_MTCN_T800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MTCN_T800 +# endif +# define machine_is_mtcn_t800() (machine_arch_type == MACH_TYPE_MTCN_T800) +#else +# define machine_is_mtcn_t800() (0) +#endif + +#ifdef CONFIG_MACH_VCMX212 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VCMX212 +# endif +# define machine_is_vcmx212() (machine_arch_type == MACH_TYPE_VCMX212) +#else +# define machine_is_vcmx212() (0) +#endif + +#ifdef CONFIG_MACH_LYNX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LYNX +# endif +# define machine_is_lynx() (machine_arch_type == MACH_TYPE_LYNX) +#else +# define machine_is_lynx() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9260ID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9260ID +# endif +# define machine_is_at91sam9260id() (machine_arch_type == MACH_TYPE_AT91SAM9260ID) +#else +# define machine_is_at91sam9260id() (0) +#endif + +#ifdef CONFIG_MACH_HW86052 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW86052 +# endif +# define machine_is_hw86052() (machine_arch_type == MACH_TYPE_HW86052) +#else +# define machine_is_hw86052() (0) +#endif + +#ifdef CONFIG_MACH_PILZ_PMI3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PILZ_PMI3 +# endif +# define machine_is_pilz_pmi3() (machine_arch_type == MACH_TYPE_PILZ_PMI3) +#else +# define machine_is_pilz_pmi3() (0) +#endif + +#ifdef CONFIG_MACH_EDB9302A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9302A +# endif +# define machine_is_edb9302a() (machine_arch_type == MACH_TYPE_EDB9302A) +#else +# define machine_is_edb9302a() (0) +#endif + +#ifdef CONFIG_MACH_EDB9307A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9307A +# endif +# define machine_is_edb9307a() (machine_arch_type == MACH_TYPE_EDB9307A) +#else +# define machine_is_edb9307a() (0) +#endif + +#ifdef CONFIG_MACH_CT_DFS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CT_DFS +# endif +# define machine_is_ct_dfs() (machine_arch_type == MACH_TYPE_CT_DFS) +#else +# define machine_is_ct_dfs() (0) +#endif + +#ifdef CONFIG_MACH_PILZ_PMI4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PILZ_PMI4 +# endif +# define machine_is_pilz_pmi4() (machine_arch_type == MACH_TYPE_PILZ_PMI4) +#else +# define machine_is_pilz_pmi4() (0) +#endif + +#ifdef CONFIG_MACH_XCEEDNP_IXP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XCEEDNP_IXP +# endif +# define machine_is_xceednp_ixp() (machine_arch_type == MACH_TYPE_XCEEDNP_IXP) +#else +# define machine_is_xceednp_ixp() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2442B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2442B +# endif +# define machine_is_smdk2442b() (machine_arch_type == MACH_TYPE_SMDK2442B) +#else +# define machine_is_smdk2442b() (0) +#endif + +#ifdef CONFIG_MACH_XNODE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XNODE +# endif +# define machine_is_xnode() (machine_arch_type == MACH_TYPE_XNODE) +#else +# define machine_is_xnode() (0) +#endif + +#ifdef CONFIG_MACH_AIDX270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AIDX270 +# endif +# define machine_is_aidx270() (machine_arch_type == MACH_TYPE_AIDX270) +#else +# define machine_is_aidx270() (0) +#endif + +#ifdef CONFIG_MACH_REMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REMA +# endif +# define machine_is_rema() (machine_arch_type == MACH_TYPE_REMA) +#else +# define machine_is_rema() (0) +#endif + +#ifdef CONFIG_MACH_BPS1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BPS1000 +# endif +# define machine_is_bps1000() (machine_arch_type == MACH_TYPE_BPS1000) +#else +# define machine_is_bps1000() (0) +#endif + +#ifdef CONFIG_MACH_HW90350 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90350 +# endif +# define machine_is_hw90350() (machine_arch_type == MACH_TYPE_HW90350) +#else +# define machine_is_hw90350() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_3430SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_3430SDP +# endif +# define machine_is_omap_3430sdp() (machine_arch_type == MACH_TYPE_OMAP_3430SDP) +#else +# define machine_is_omap_3430sdp() (0) +#endif + +#ifdef CONFIG_MACH_BLUETOUCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUETOUCH +# endif +# define machine_is_bluetouch() (machine_arch_type == MACH_TYPE_BLUETOUCH) +#else +# define machine_is_bluetouch() (0) +#endif + +#ifdef CONFIG_MACH_VSTMS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VSTMS +# endif +# define machine_is_vstms() (machine_arch_type == MACH_TYPE_VSTMS) +#else +# define machine_is_vstms() (0) +#endif + +#ifdef CONFIG_MACH_XSBASE270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSBASE270 +# endif +# define machine_is_xsbase270() (machine_arch_type == MACH_TYPE_XSBASE270) +#else +# define machine_is_xsbase270() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9260EK_CN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9260EK_CN +# endif +# define machine_is_at91sam9260ek_cn() (machine_arch_type == MACH_TYPE_AT91SAM9260EK_CN) +#else +# define machine_is_at91sam9260ek_cn() (0) +#endif + +#ifdef CONFIG_MACH_ADSTURBOXB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSTURBOXB +# endif +# define machine_is_adsturboxb() (machine_arch_type == MACH_TYPE_ADSTURBOXB) +#else +# define machine_is_adsturboxb() (0) +#endif + +#ifdef CONFIG_MACH_OTI4110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTI4110 +# endif +# define machine_is_oti4110() (machine_arch_type == MACH_TYPE_OTI4110) +#else +# define machine_is_oti4110() (0) +#endif + +#ifdef CONFIG_MACH_HME_PXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HME_PXA +# endif +# define machine_is_hme_pxa() (machine_arch_type == MACH_TYPE_HME_PXA) +#else +# define machine_is_hme_pxa() (0) +#endif + +#ifdef CONFIG_MACH_DEISTERDCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEISTERDCA +# endif +# define machine_is_deisterdca() (machine_arch_type == MACH_TYPE_DEISTERDCA) +#else +# define machine_is_deisterdca() (0) +#endif + +#ifdef CONFIG_MACH_CES_SSEM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CES_SSEM2 +# endif +# define machine_is_ces_ssem2() (machine_arch_type == MACH_TYPE_CES_SSEM2) +#else +# define machine_is_ces_ssem2() (0) +#endif + +#ifdef CONFIG_MACH_CES_MTR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CES_MTR +# endif +# define machine_is_ces_mtr() (machine_arch_type == MACH_TYPE_CES_MTR) +#else +# define machine_is_ces_mtr() (0) +#endif + +#ifdef CONFIG_MACH_TDS_AVNG_SBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TDS_AVNG_SBC +# endif +# define machine_is_tds_avng_sbc() (machine_arch_type == MACH_TYPE_TDS_AVNG_SBC) +#else +# define machine_is_tds_avng_sbc() (0) +#endif + +#ifdef CONFIG_MACH_EVEREST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EVEREST +# endif +# define machine_is_everest() (machine_arch_type == MACH_TYPE_EVEREST) +#else +# define machine_is_everest() (0) +#endif + +#ifdef CONFIG_MACH_PNX4010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX4010 +# endif +# define machine_is_pnx4010() (machine_arch_type == MACH_TYPE_PNX4010) +#else +# define machine_is_pnx4010() (0) +#endif + +#ifdef CONFIG_MACH_OXNAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OXNAS +# endif +# define machine_is_oxnas() (machine_arch_type == MACH_TYPE_OXNAS) +#else +# define machine_is_oxnas() (0) +#endif + +#ifdef CONFIG_MACH_FIORI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FIORI +# endif +# define machine_is_fiori() (machine_arch_type == MACH_TYPE_FIORI) +#else +# define machine_is_fiori() (0) +#endif + +#ifdef CONFIG_MACH_ML1200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML1200 +# endif +# define machine_is_ml1200() (machine_arch_type == MACH_TYPE_ML1200) +#else +# define machine_is_ml1200() (0) +#endif + +#ifdef CONFIG_MACH_PECOS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PECOS +# endif +# define machine_is_pecos() (machine_arch_type == MACH_TYPE_PECOS) +#else +# define machine_is_pecos() (0) +#endif + +#ifdef CONFIG_MACH_NB2XXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NB2XXX +# endif +# define machine_is_nb2xxx() (machine_arch_type == MACH_TYPE_NB2XXX) +#else +# define machine_is_nb2xxx() (0) +#endif + +#ifdef CONFIG_MACH_HW6900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW6900 +# endif +# define machine_is_hw6900() (machine_arch_type == MACH_TYPE_HW6900) +#else +# define machine_is_hw6900() (0) +#endif + +#ifdef CONFIG_MACH_CDCS_QUOLL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CDCS_QUOLL +# endif +# define machine_is_cdcs_quoll() (machine_arch_type == MACH_TYPE_CDCS_QUOLL) +#else +# define machine_is_cdcs_quoll() (0) +#endif + +#ifdef CONFIG_MACH_QUICKSILVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUICKSILVER +# endif +# define machine_is_quicksilver() (machine_arch_type == MACH_TYPE_QUICKSILVER) +#else +# define machine_is_quicksilver() (0) +#endif + +#ifdef CONFIG_MACH_UPLAT926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UPLAT926 +# endif +# define machine_is_uplat926() (machine_arch_type == MACH_TYPE_UPLAT926) +#else +# define machine_is_uplat926() (0) +#endif + +#ifdef CONFIG_MACH_DEP2410_THOMAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEP2410_THOMAS +# endif +# define machine_is_dep2410_dep2410() (machine_arch_type == MACH_TYPE_DEP2410_THOMAS) +#else +# define machine_is_dep2410_dep2410() (0) +#endif + +#ifdef CONFIG_MACH_DTK2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DTK2410 +# endif +# define machine_is_dtk2410() (machine_arch_type == MACH_TYPE_DTK2410) +#else +# define machine_is_dtk2410() (0) +#endif + +#ifdef CONFIG_MACH_CHILI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHILI +# endif +# define machine_is_chili() (machine_arch_type == MACH_TYPE_CHILI) +#else +# define machine_is_chili() (0) +#endif + +#ifdef CONFIG_MACH_DEMETER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEMETER +# endif +# define machine_is_demeter() (machine_arch_type == MACH_TYPE_DEMETER) +#else +# define machine_is_demeter() (0) +#endif + +#ifdef CONFIG_MACH_DIONYSUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DIONYSUS +# endif +# define machine_is_dionysus() (machine_arch_type == MACH_TYPE_DIONYSUS) +#else +# define machine_is_dionysus() (0) +#endif + +#ifdef CONFIG_MACH_AS352X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS352X +# endif +# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) +#else +# define machine_is_as352x() (0) +#endif + +#ifdef CONFIG_MACH_SERVICE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SERVICE +# endif +# define machine_is_service() (machine_arch_type == MACH_TYPE_SERVICE) +#else +# define machine_is_service() (0) +#endif + +#ifdef CONFIG_MACH_CS_E9301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS_E9301 +# endif +# define machine_is_cs_e9301() (machine_arch_type == MACH_TYPE_CS_E9301) +#else +# define machine_is_cs_e9301() (0) +#endif + +#ifdef CONFIG_MACH_MICRO9M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO9M +# endif +# define machine_is_micro9m() (machine_arch_type == MACH_TYPE_MICRO9M) +#else +# define machine_is_micro9m() (0) +#endif + +#ifdef CONFIG_MACH_IA_MOSPCK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IA_MOSPCK +# endif +# define machine_is_ia_mospck() (machine_arch_type == MACH_TYPE_IA_MOSPCK) +#else +# define machine_is_ia_mospck() (0) +#endif + +#ifdef CONFIG_MACH_QL201B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QL201B +# endif +# define machine_is_ql201b() (machine_arch_type == MACH_TYPE_QL201B) +#else +# define machine_is_ql201b() (0) +#endif + +#ifdef CONFIG_MACH_BBM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BBM +# endif +# define machine_is_bbm() (machine_arch_type == MACH_TYPE_BBM) +#else +# define machine_is_bbm() (0) +#endif + +#ifdef CONFIG_MACH_EXXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXXX +# endif +# define machine_is_exxx() (machine_arch_type == MACH_TYPE_EXXX) +#else +# define machine_is_exxx() (0) +#endif + +#ifdef CONFIG_MACH_WMA11B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WMA11B +# endif +# define machine_is_wma11b() (machine_arch_type == MACH_TYPE_WMA11B) +#else +# define machine_is_wma11b() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_ATLAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_ATLAS +# endif +# define machine_is_pelco_atlas() (machine_arch_type == MACH_TYPE_PELCO_ATLAS) +#else +# define machine_is_pelco_atlas() (0) +#endif + +#ifdef CONFIG_MACH_G500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G500 +# endif +# define machine_is_g500() (machine_arch_type == MACH_TYPE_G500) +#else +# define machine_is_g500() (0) +#endif + +#ifdef CONFIG_MACH_BUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUG +# endif +# define machine_is_bug() (machine_arch_type == MACH_TYPE_BUG) +#else +# define machine_is_bug() (0) +#endif + +#ifdef CONFIG_MACH_MX33ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX33ADS +# endif +# define machine_is_mx33ads() (machine_arch_type == MACH_TYPE_MX33ADS) +#else +# define machine_is_mx33ads() (0) +#endif + +#ifdef CONFIG_MACH_CHUB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHUB +# endif +# define machine_is_chub() (machine_arch_type == MACH_TYPE_CHUB) +#else +# define machine_is_chub() (0) +#endif + +#ifdef CONFIG_MACH_NEO1973_GTA01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEO1973_GTA01 +# endif +# define machine_is_neo1973_gta01() (machine_arch_type == MACH_TYPE_NEO1973_GTA01) +#else +# define machine_is_neo1973_gta01() (0) +#endif + +#ifdef CONFIG_MACH_W90N740 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90N740 +# endif +# define machine_is_w90n740() (machine_arch_type == MACH_TYPE_W90N740) +#else +# define machine_is_w90n740() (0) +#endif + +#ifdef CONFIG_MACH_MEDALLION_SA2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEDALLION_SA2410 +# endif +# define machine_is_medallion_sa2410() (machine_arch_type == MACH_TYPE_MEDALLION_SA2410) +#else +# define machine_is_medallion_sa2410() (0) +#endif + +#ifdef CONFIG_MACH_IA_CPU_9200_2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IA_CPU_9200_2 +# endif +# define machine_is_ia_cpu_9200_2() (machine_arch_type == MACH_TYPE_IA_CPU_9200_2) +#else +# define machine_is_ia_cpu_9200_2() (0) +#endif + +#ifdef CONFIG_MACH_DIMMRM9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DIMMRM9200 +# endif +# define machine_is_dimmrm9200() (machine_arch_type == MACH_TYPE_DIMMRM9200) +#else +# define machine_is_dimmrm9200() (0) +#endif + +#ifdef CONFIG_MACH_PM9261 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PM9261 +# endif +# define machine_is_pm9261() (machine_arch_type == MACH_TYPE_PM9261) +#else +# define machine_is_pm9261() (0) +#endif + +#ifdef CONFIG_MACH_ML7304 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML7304 +# endif +# define machine_is_ml7304() (machine_arch_type == MACH_TYPE_ML7304) +#else +# define machine_is_ml7304() (0) +#endif + +#ifdef CONFIG_MACH_UCP250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UCP250 +# endif +# define machine_is_ucp250() (machine_arch_type == MACH_TYPE_UCP250) +#else +# define machine_is_ucp250() (0) +#endif + +#ifdef CONFIG_MACH_INTBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INTBOARD +# endif +# define machine_is_intboard() (machine_arch_type == MACH_TYPE_INTBOARD) +#else +# define machine_is_intboard() (0) +#endif + +#ifdef CONFIG_MACH_GULFSTREAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GULFSTREAM +# endif +# define machine_is_gulfstream() (machine_arch_type == MACH_TYPE_GULFSTREAM) +#else +# define machine_is_gulfstream() (0) +#endif + +#ifdef CONFIG_MACH_LABQUEST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LABQUEST +# endif +# define machine_is_labquest() (machine_arch_type == MACH_TYPE_LABQUEST) +#else +# define machine_is_labquest() (0) +#endif + +#ifdef CONFIG_MACH_VCMX313 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VCMX313 +# endif +# define machine_is_vcmx313() (machine_arch_type == MACH_TYPE_VCMX313) +#else +# define machine_is_vcmx313() (0) +#endif + +#ifdef CONFIG_MACH_URG200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_URG200 +# endif +# define machine_is_urg200() (machine_arch_type == MACH_TYPE_URG200) +#else +# define machine_is_urg200() (0) +#endif + +#ifdef CONFIG_MACH_CPUX255LCDNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUX255LCDNET +# endif +# define machine_is_cpux255lcdnet() (machine_arch_type == MACH_TYPE_CPUX255LCDNET) +#else +# define machine_is_cpux255lcdnet() (0) +#endif + +#ifdef CONFIG_MACH_NETDCU9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETDCU9 +# endif +# define machine_is_netdcu9() (machine_arch_type == MACH_TYPE_NETDCU9) +#else +# define machine_is_netdcu9() (0) +#endif + +#ifdef CONFIG_MACH_NETDCU10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETDCU10 +# endif +# define machine_is_netdcu10() (machine_arch_type == MACH_TYPE_NETDCU10) +#else +# define machine_is_netdcu10() (0) +#endif + +#ifdef CONFIG_MACH_DSPG_DGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSPG_DGA +# endif +# define machine_is_dspg_dga() (machine_arch_type == MACH_TYPE_DSPG_DGA) +#else +# define machine_is_dspg_dga() (0) +#endif + +#ifdef CONFIG_MACH_DSPG_DVW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSPG_DVW +# endif +# define machine_is_dspg_dvw() (machine_arch_type == MACH_TYPE_DSPG_DVW) +#else +# define machine_is_dspg_dvw() (0) +#endif + +#ifdef CONFIG_MACH_SOLOS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOLOS +# endif +# define machine_is_solos() (machine_arch_type == MACH_TYPE_SOLOS) +#else +# define machine_is_solos() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263EK +# endif +# define machine_is_at91sam9263ek() (machine_arch_type == MACH_TYPE_AT91SAM9263EK) +#else +# define machine_is_at91sam9263ek() (0) +#endif + +#ifdef CONFIG_MACH_OSSTBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OSSTBOX +# endif +# define machine_is_osstbox() (machine_arch_type == MACH_TYPE_OSSTBOX) +#else +# define machine_is_osstbox() (0) +#endif + +#ifdef CONFIG_MACH_KBAT9261 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KBAT9261 +# endif +# define machine_is_kbat9261() (machine_arch_type == MACH_TYPE_KBAT9261) +#else +# define machine_is_kbat9261() (0) +#endif + +#ifdef CONFIG_MACH_CT1100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CT1100 +# endif +# define machine_is_ct1100() (machine_arch_type == MACH_TYPE_CT1100) +#else +# define machine_is_ct1100() (0) +#endif + +#ifdef CONFIG_MACH_AKCPPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AKCPPXA +# endif +# define machine_is_akcppxa() (machine_arch_type == MACH_TYPE_AKCPPXA) +#else +# define machine_is_akcppxa() (0) +#endif + +#ifdef CONFIG_MACH_OCHAYA1020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCHAYA1020 +# endif +# define machine_is_ochaya1020() (machine_arch_type == MACH_TYPE_OCHAYA1020) +#else +# define machine_is_ochaya1020() (0) +#endif + +#ifdef CONFIG_MACH_HITRACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HITRACK +# endif +# define machine_is_hitrack() (machine_arch_type == MACH_TYPE_HITRACK) +#else +# define machine_is_hitrack() (0) +#endif + +#ifdef CONFIG_MACH_SYME1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYME1 +# endif +# define machine_is_syme1() (machine_arch_type == MACH_TYPE_SYME1) +#else +# define machine_is_syme1() (0) +#endif + +#ifdef CONFIG_MACH_SYHL1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYHL1 +# endif +# define machine_is_syhl1() (machine_arch_type == MACH_TYPE_SYHL1) +#else +# define machine_is_syhl1() (0) +#endif + +#ifdef CONFIG_MACH_EMPCA400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMPCA400 +# endif +# define machine_is_empca400() (machine_arch_type == MACH_TYPE_EMPCA400) +#else +# define machine_is_empca400() (0) +#endif + +#ifdef CONFIG_MACH_EM7210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EM7210 +# endif +# define machine_is_em7210() (machine_arch_type == MACH_TYPE_EM7210) +#else +# define machine_is_em7210() (0) +#endif + +#ifdef CONFIG_MACH_HTCHERMES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCHERMES +# endif +# define machine_is_htchermes() (machine_arch_type == MACH_TYPE_HTCHERMES) +#else +# define machine_is_htchermes() (0) +#endif + +#ifdef CONFIG_MACH_ETI_C1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETI_C1 +# endif +# define machine_is_eti_c1() (machine_arch_type == MACH_TYPE_ETI_C1) +#else +# define machine_is_eti_c1() (0) +#endif + +#ifdef CONFIG_MACH_AC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AC100 +# endif +# define machine_is_ac100() (machine_arch_type == MACH_TYPE_AC100) +#else +# define machine_is_ac100() (0) +#endif + +#ifdef CONFIG_MACH_SNEETCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNEETCH +# endif +# define machine_is_sneetch() (machine_arch_type == MACH_TYPE_SNEETCH) +#else +# define machine_is_sneetch() (0) +#endif + +#ifdef CONFIG_MACH_STUDENTMATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STUDENTMATE +# endif +# define machine_is_studentmate() (machine_arch_type == MACH_TYPE_STUDENTMATE) +#else +# define machine_is_studentmate() (0) +#endif + +#ifdef CONFIG_MACH_ZIR2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZIR2410 +# endif +# define machine_is_zir2410() (machine_arch_type == MACH_TYPE_ZIR2410) +#else +# define machine_is_zir2410() (0) +#endif + +#ifdef CONFIG_MACH_ZIR2413 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZIR2413 +# endif +# define machine_is_zir2413() (machine_arch_type == MACH_TYPE_ZIR2413) +#else +# define machine_is_zir2413() (0) +#endif + +#ifdef CONFIG_MACH_DLONIP3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DLONIP3 +# endif +# define machine_is_dlonip3() (machine_arch_type == MACH_TYPE_DLONIP3) +#else +# define machine_is_dlonip3() (0) +#endif + +#ifdef CONFIG_MACH_INSTREAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INSTREAM +# endif +# define machine_is_instream() (machine_arch_type == MACH_TYPE_INSTREAM) +#else +# define machine_is_instream() (0) +#endif + +#ifdef CONFIG_MACH_AMBARELLA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AMBARELLA +# endif +# define machine_is_ambarella() (machine_arch_type == MACH_TYPE_AMBARELLA) +#else +# define machine_is_ambarella() (0) +#endif + +#ifdef CONFIG_MACH_NEVIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEVIS +# endif +# define machine_is_nevis() (machine_arch_type == MACH_TYPE_NEVIS) +#else +# define machine_is_nevis() (0) +#endif + +#ifdef CONFIG_MACH_HTC_TRINITY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_TRINITY +# endif +# define machine_is_htc_trinity() (machine_arch_type == MACH_TYPE_HTC_TRINITY) +#else +# define machine_is_htc_trinity() (0) +#endif + +#ifdef CONFIG_MACH_QL202B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QL202B +# endif +# define machine_is_ql202b() (machine_arch_type == MACH_TYPE_QL202B) +#else +# define machine_is_ql202b() (0) +#endif + +#ifdef CONFIG_MACH_VPAC270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPAC270 +# endif +# define machine_is_vpac270() (machine_arch_type == MACH_TYPE_VPAC270) +#else +# define machine_is_vpac270() (0) +#endif + +#ifdef CONFIG_MACH_RD129 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD129 +# endif +# define machine_is_rd129() (machine_arch_type == MACH_TYPE_RD129) +#else +# define machine_is_rd129() (0) +#endif + +#ifdef CONFIG_MACH_HTCWIZARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCWIZARD +# endif +# define machine_is_htcwizard() (machine_arch_type == MACH_TYPE_HTCWIZARD) +#else +# define machine_is_htcwizard() (0) +#endif + +#ifdef CONFIG_MACH_TREO680 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TREO680 +# endif +# define machine_is_treo680() (machine_arch_type == MACH_TYPE_TREO680) +#else +# define machine_is_treo680() (0) +#endif + +#ifdef CONFIG_MACH_TECON_TMEZON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TECON_TMEZON +# endif +# define machine_is_tecon_tmezon() (machine_arch_type == MACH_TYPE_TECON_TMEZON) +#else +# define machine_is_tecon_tmezon() (0) +#endif + +#ifdef CONFIG_MACH_ZYLONITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZYLONITE +# endif +# define machine_is_zylonite() (machine_arch_type == MACH_TYPE_ZYLONITE) +#else +# define machine_is_zylonite() (0) +#endif + +#ifdef CONFIG_MACH_GENE1270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GENE1270 +# endif +# define machine_is_gene1270() (machine_arch_type == MACH_TYPE_GENE1270) +#else +# define machine_is_gene1270() (0) +#endif + +#ifdef CONFIG_MACH_ZIR2412 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZIR2412 +# endif +# define machine_is_zir2412() (machine_arch_type == MACH_TYPE_ZIR2412) +#else +# define machine_is_zir2412() (0) +#endif + +#ifdef CONFIG_MACH_MX31LITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31LITE +# endif +# define machine_is_mx31lite() (machine_arch_type == MACH_TYPE_MX31LITE) +#else +# define machine_is_mx31lite() (0) +#endif + +#ifdef CONFIG_MACH_T700WX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T700WX +# endif +# define machine_is_t700wx() (machine_arch_type == MACH_TYPE_T700WX) +#else +# define machine_is_t700wx() (0) +#endif + +#ifdef CONFIG_MACH_VF100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VF100 +# endif +# define machine_is_vf100() (machine_arch_type == MACH_TYPE_VF100) +#else +# define machine_is_vf100() (0) +#endif + +#ifdef CONFIG_MACH_NSB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB2 +# endif +# define machine_is_nsb2() (machine_arch_type == MACH_TYPE_NSB2) +#else +# define machine_is_nsb2() (0) +#endif + +#ifdef CONFIG_MACH_NXHMI_BB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXHMI_BB +# endif +# define machine_is_nxhmi_bb() (machine_arch_type == MACH_TYPE_NXHMI_BB) +#else +# define machine_is_nxhmi_bb() (0) +#endif + +#ifdef CONFIG_MACH_NXHMI_RE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXHMI_RE +# endif +# define machine_is_nxhmi_re() (machine_arch_type == MACH_TYPE_NXHMI_RE) +#else +# define machine_is_nxhmi_re() (0) +#endif + +#ifdef CONFIG_MACH_N4100PRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N4100PRO +# endif +# define machine_is_n4100pro() (machine_arch_type == MACH_TYPE_N4100PRO) +#else +# define machine_is_n4100pro() (0) +#endif + +#ifdef CONFIG_MACH_SAM9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAM9260 +# endif +# define machine_is_sam9260() (machine_arch_type == MACH_TYPE_SAM9260) +#else +# define machine_is_sam9260() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_TREO600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_TREO600 +# endif +# define machine_is_omap_treo600() (machine_arch_type == MACH_TYPE_OMAP_TREO600) +#else +# define machine_is_omap_treo600() (0) +#endif + +#ifdef CONFIG_MACH_INDY2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INDY2410 +# endif +# define machine_is_indy2410() (machine_arch_type == MACH_TYPE_INDY2410) +#else +# define machine_is_indy2410() (0) +#endif + +#ifdef CONFIG_MACH_NELT_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NELT_A +# endif +# define machine_is_nelt_a() (machine_arch_type == MACH_TYPE_NELT_A) +#else +# define machine_is_nelt_a() (0) +#endif + +#ifdef CONFIG_MACH_N311 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N311 +# endif +# define machine_is_n311() (machine_arch_type == MACH_TYPE_N311) +#else +# define machine_is_n311() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9260VGK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9260VGK +# endif +# define machine_is_at91sam9260vgk() (machine_arch_type == MACH_TYPE_AT91SAM9260VGK) +#else +# define machine_is_at91sam9260vgk() (0) +#endif + +#ifdef CONFIG_MACH_AT91LEPPE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91LEPPE +# endif +# define machine_is_at91leppe() (machine_arch_type == MACH_TYPE_AT91LEPPE) +#else +# define machine_is_at91leppe() (0) +#endif + +#ifdef CONFIG_MACH_AT91LEPCCN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91LEPCCN +# endif +# define machine_is_at91lepccn() (machine_arch_type == MACH_TYPE_AT91LEPCCN) +#else +# define machine_is_at91lepccn() (0) +#endif + +#ifdef CONFIG_MACH_APC7100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APC7100 +# endif +# define machine_is_apc7100() (machine_arch_type == MACH_TYPE_APC7100) +#else +# define machine_is_apc7100() (0) +#endif + +#ifdef CONFIG_MACH_STARGAZER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STARGAZER +# endif +# define machine_is_stargazer() (machine_arch_type == MACH_TYPE_STARGAZER) +#else +# define machine_is_stargazer() (0) +#endif + +#ifdef CONFIG_MACH_SONATA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONATA +# endif +# define machine_is_sonata() (machine_arch_type == MACH_TYPE_SONATA) +#else +# define machine_is_sonata() (0) +#endif + +#ifdef CONFIG_MACH_SCHMOOGIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCHMOOGIE +# endif +# define machine_is_schmoogie() (machine_arch_type == MACH_TYPE_SCHMOOGIE) +#else +# define machine_is_schmoogie() (0) +#endif + +#ifdef CONFIG_MACH_AZTOOL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AZTOOL +# endif +# define machine_is_aztool() (machine_arch_type == MACH_TYPE_AZTOOL) +#else +# define machine_is_aztool() (0) +#endif + +#ifdef CONFIG_MACH_MIOA701 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOA701 +# endif +# define machine_is_mioa701() (machine_arch_type == MACH_TYPE_MIOA701) +#else +# define machine_is_mioa701() (0) +#endif + +#ifdef CONFIG_MACH_SXNI9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SXNI9260 +# endif +# define machine_is_sxni9260() (machine_arch_type == MACH_TYPE_SXNI9260) +#else +# define machine_is_sxni9260() (0) +#endif + +#ifdef CONFIG_MACH_MXC27520EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC27520EVB +# endif +# define machine_is_mxc27520evb() (machine_arch_type == MACH_TYPE_MXC27520EVB) +#else +# define machine_is_mxc27520evb() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO5X0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO5X0 +# endif +# define machine_is_armadillo5x0() (machine_arch_type == MACH_TYPE_ARMADILLO5X0) +#else +# define machine_is_armadillo5x0() (0) +#endif + +#ifdef CONFIG_MACH_MB9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9260 +# endif +# define machine_is_mb9260() (machine_arch_type == MACH_TYPE_MB9260) +#else +# define machine_is_mb9260() (0) +#endif + +#ifdef CONFIG_MACH_MB9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9263 +# endif +# define machine_is_mb9263() (machine_arch_type == MACH_TYPE_MB9263) +#else +# define machine_is_mb9263() (0) +#endif + +#ifdef CONFIG_MACH_IPAC9302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPAC9302 +# endif +# define machine_is_ipac9302() (machine_arch_type == MACH_TYPE_IPAC9302) +#else +# define machine_is_ipac9302() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9360JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9360JS +# endif +# define machine_is_cc9p9360js() (machine_arch_type == MACH_TYPE_CC9P9360JS) +#else +# define machine_is_cc9p9360js() (0) +#endif + +#ifdef CONFIG_MACH_GALLIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GALLIUM +# endif +# define machine_is_gallium() (machine_arch_type == MACH_TYPE_GALLIUM) +#else +# define machine_is_gallium() (0) +#endif + +#ifdef CONFIG_MACH_MSC2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSC2410 +# endif +# define machine_is_msc2410() (machine_arch_type == MACH_TYPE_MSC2410) +#else +# define machine_is_msc2410() (0) +#endif + +#ifdef CONFIG_MACH_GHI270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GHI270 +# endif +# define machine_is_ghi270() (machine_arch_type == MACH_TYPE_GHI270) +#else +# define machine_is_ghi270() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_LEONARDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_LEONARDO +# endif +# define machine_is_davinci_leonardo() (machine_arch_type == MACH_TYPE_DAVINCI_LEONARDO) +#else +# define machine_is_davinci_leonardo() (0) +#endif + +#ifdef CONFIG_MACH_OIAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OIAB +# endif +# define machine_is_oiab() (machine_arch_type == MACH_TYPE_OIAB) +#else +# define machine_is_oiab() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6400 +# endif +# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400) +#else +# define machine_is_smdk6400() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA_N800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA_N800 +# endif +# define machine_is_nokia_n800() (machine_arch_type == MACH_TYPE_NOKIA_N800) +#else +# define machine_is_nokia_n800() (0) +#endif + +#ifdef CONFIG_MACH_GREENPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GREENPHONE +# endif +# define machine_is_greenphone() (machine_arch_type == MACH_TYPE_GREENPHONE) +#else +# define machine_is_greenphone() (0) +#endif + +#ifdef CONFIG_MACH_COMPEXWP18 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMPEXWP18 +# endif +# define machine_is_compex42x() (machine_arch_type == MACH_TYPE_COMPEXWP18) +#else +# define machine_is_compex42x() (0) +#endif + +#ifdef CONFIG_MACH_XMATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XMATE +# endif +# define machine_is_xmate() (machine_arch_type == MACH_TYPE_XMATE) +#else +# define machine_is_xmate() (0) +#endif + +#ifdef CONFIG_MACH_ENERGIZER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENERGIZER +# endif +# define machine_is_energizer() (machine_arch_type == MACH_TYPE_ENERGIZER) +#else +# define machine_is_energizer() (0) +#endif + +#ifdef CONFIG_MACH_IME1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IME1 +# endif +# define machine_is_ime1() (machine_arch_type == MACH_TYPE_IME1) +#else +# define machine_is_ime1() (0) +#endif + +#ifdef CONFIG_MACH_SWEDATMS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWEDATMS +# endif +# define machine_is_sweda_tms() (machine_arch_type == MACH_TYPE_SWEDATMS) +#else +# define machine_is_sweda_tms() (0) +#endif + +#ifdef CONFIG_MACH_NTNP435C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NTNP435C +# endif +# define machine_is_ntnp435c() (machine_arch_type == MACH_TYPE_NTNP435C) +#else +# define machine_is_ntnp435c() (0) +#endif + +#ifdef CONFIG_MACH_SPECTRO2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPECTRO2 +# endif +# define machine_is_spectro2() (machine_arch_type == MACH_TYPE_SPECTRO2) +#else +# define machine_is_spectro2() (0) +#endif + +#ifdef CONFIG_MACH_H6039 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6039 +# endif +# define machine_is_h6039() (machine_arch_type == MACH_TYPE_H6039) +#else +# define machine_is_h6039() (0) +#endif + +#ifdef CONFIG_MACH_EP80219 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EP80219 +# endif +# define machine_is_ep80219() (machine_arch_type == MACH_TYPE_EP80219) +#else +# define machine_is_ep80219() (0) +#endif + +#ifdef CONFIG_MACH_SAMOA_II +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAMOA_II +# endif +# define machine_is_samoa_ii() (machine_arch_type == MACH_TYPE_SAMOA_II) +#else +# define machine_is_samoa_ii() (0) +#endif + +#ifdef CONFIG_MACH_CWMXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWMXL +# endif +# define machine_is_cwmxl() (machine_arch_type == MACH_TYPE_CWMXL) +#else +# define machine_is_cwmxl() (0) +#endif + +#ifdef CONFIG_MACH_AS9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS9200 +# endif +# define machine_is_as9200() (machine_arch_type == MACH_TYPE_AS9200) +#else +# define machine_is_as9200() (0) +#endif + +#ifdef CONFIG_MACH_SFX1149 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SFX1149 +# endif +# define machine_is_sfx1149() (machine_arch_type == MACH_TYPE_SFX1149) +#else +# define machine_is_sfx1149() (0) +#endif + +#ifdef CONFIG_MACH_NAVI010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAVI010 +# endif +# define machine_is_navi010() (machine_arch_type == MACH_TYPE_NAVI010) +#else +# define machine_is_navi010() (0) +#endif + +#ifdef CONFIG_MACH_MULTMDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTMDP +# endif +# define machine_is_multmdp() (machine_arch_type == MACH_TYPE_MULTMDP) +#else +# define machine_is_multmdp() (0) +#endif + +#ifdef CONFIG_MACH_SCB9520 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCB9520 +# endif +# define machine_is_scb9520() (machine_arch_type == MACH_TYPE_SCB9520) +#else +# define machine_is_scb9520() (0) +#endif + +#ifdef CONFIG_MACH_HTCATHENA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCATHENA +# endif +# define machine_is_htcathena() (machine_arch_type == MACH_TYPE_HTCATHENA) +#else +# define machine_is_htcathena() (0) +#endif + +#ifdef CONFIG_MACH_XP179 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XP179 +# endif +# define machine_is_xp179() (machine_arch_type == MACH_TYPE_XP179) +#else +# define machine_is_xp179() (0) +#endif + +#ifdef CONFIG_MACH_H4300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H4300 +# endif +# define machine_is_h4300() (machine_arch_type == MACH_TYPE_H4300) +#else +# define machine_is_h4300() (0) +#endif + +#ifdef CONFIG_MACH_GORAMO_MLR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GORAMO_MLR +# endif +# define machine_is_goramo_mlr() (machine_arch_type == MACH_TYPE_GORAMO_MLR) +#else +# define machine_is_goramo_mlr() (0) +#endif + +#ifdef CONFIG_MACH_MXC30020EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC30020EVB +# endif +# define machine_is_mxc30020evb() (machine_arch_type == MACH_TYPE_MXC30020EVB) +#else +# define machine_is_mxc30020evb() (0) +#endif + +#ifdef CONFIG_MACH_ADSBITSYG5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSYG5 +# endif +# define machine_is_adsbitsyg5() (machine_arch_type == MACH_TYPE_ADSBITSYG5) +#else +# define machine_is_adsbitsyg5() (0) +#endif + +#ifdef CONFIG_MACH_ADSPORTALPLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSPORTALPLUS +# endif +# define machine_is_adsportalplus() (machine_arch_type == MACH_TYPE_ADSPORTALPLUS) +#else +# define machine_is_adsportalplus() (0) +#endif + +#ifdef CONFIG_MACH_MMSP2PLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMSP2PLUS +# endif +# define machine_is_mmsp2plus() (machine_arch_type == MACH_TYPE_MMSP2PLUS) +#else +# define machine_is_mmsp2plus() (0) +#endif + +#ifdef CONFIG_MACH_EM_X270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EM_X270 +# endif +# define machine_is_em_x270() (machine_arch_type == MACH_TYPE_EM_X270) +#else +# define machine_is_em_x270() (0) +#endif + +#ifdef CONFIG_MACH_TPP302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TPP302 +# endif +# define machine_is_tpp302() (machine_arch_type == MACH_TYPE_TPP302) +#else +# define machine_is_tpp302() (0) +#endif + +#ifdef CONFIG_MACH_TPM104 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TPM104 +# endif +# define machine_is_tpp104() (machine_arch_type == MACH_TYPE_TPM104) +#else +# define machine_is_tpp104() (0) +#endif + +#ifdef CONFIG_MACH_TPM102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TPM102 +# endif +# define machine_is_tpm102() (machine_arch_type == MACH_TYPE_TPM102) +#else +# define machine_is_tpm102() (0) +#endif + +#ifdef CONFIG_MACH_TPM109 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TPM109 +# endif +# define machine_is_tpm109() (machine_arch_type == MACH_TYPE_TPM109) +#else +# define machine_is_tpm109() (0) +#endif + +#ifdef CONFIG_MACH_FBXO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FBXO1 +# endif +# define machine_is_fbxo1() (machine_arch_type == MACH_TYPE_FBXO1) +#else +# define machine_is_fbxo1() (0) +#endif + +#ifdef CONFIG_MACH_HXD8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HXD8 +# endif +# define machine_is_hxd8() (machine_arch_type == MACH_TYPE_HXD8) +#else +# define machine_is_hxd8() (0) +#endif + +#ifdef CONFIG_MACH_NEO1973_GTA02 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEO1973_GTA02 +# endif +# define machine_is_neo1973_gta02() (machine_arch_type == MACH_TYPE_NEO1973_GTA02) +#else +# define machine_is_neo1973_gta02() (0) +#endif + +#ifdef CONFIG_MACH_EMTEST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMTEST +# endif +# define machine_is_emtest() (machine_arch_type == MACH_TYPE_EMTEST) +#else +# define machine_is_emtest() (0) +#endif + +#ifdef CONFIG_MACH_AD6900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AD6900 +# endif +# define machine_is_ad6900() (machine_arch_type == MACH_TYPE_AD6900) +#else +# define machine_is_ad6900() (0) +#endif + +#ifdef CONFIG_MACH_EUROPA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUROPA +# endif +# define machine_is_europa() (machine_arch_type == MACH_TYPE_EUROPA) +#else +# define machine_is_europa() (0) +#endif + +#ifdef CONFIG_MACH_METROCONNECT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_METROCONNECT +# endif +# define machine_is_metroconnect() (machine_arch_type == MACH_TYPE_METROCONNECT) +#else +# define machine_is_metroconnect() (0) +#endif + +#ifdef CONFIG_MACH_EZ_S2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_S2410 +# endif +# define machine_is_ez_s2410() (machine_arch_type == MACH_TYPE_EZ_S2410) +#else +# define machine_is_ez_s2410() (0) +#endif + +#ifdef CONFIG_MACH_EZ_S2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_S2440 +# endif +# define machine_is_ez_s2440() (machine_arch_type == MACH_TYPE_EZ_S2440) +#else +# define machine_is_ez_s2440() (0) +#endif + +#ifdef CONFIG_MACH_EZ_EP9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_EP9312 +# endif +# define machine_is_ez_ep9312() (machine_arch_type == MACH_TYPE_EZ_EP9312) +#else +# define machine_is_ez_ep9312() (0) +#endif + +#ifdef CONFIG_MACH_EZ_EP9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_EP9315 +# endif +# define machine_is_ez_ep9315() (machine_arch_type == MACH_TYPE_EZ_EP9315) +#else +# define machine_is_ez_ep9315() (0) +#endif + +#ifdef CONFIG_MACH_EZ_X7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_X7 +# endif +# define machine_is_ez_x7() (machine_arch_type == MACH_TYPE_EZ_X7) +#else +# define machine_is_ez_x7() (0) +#endif + +#ifdef CONFIG_MACH_GODOTDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GODOTDB +# endif +# define machine_is_godotdb() (machine_arch_type == MACH_TYPE_GODOTDB) +#else +# define machine_is_godotdb() (0) +#endif + +#ifdef CONFIG_MACH_MISTRAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MISTRAL +# endif +# define machine_is_mistral() (machine_arch_type == MACH_TYPE_MISTRAL) +#else +# define machine_is_mistral() (0) +#endif + +#ifdef CONFIG_MACH_MSM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM +# endif +# define machine_is_msm() (machine_arch_type == MACH_TYPE_MSM) +#else +# define machine_is_msm() (0) +#endif + +#ifdef CONFIG_MACH_CT5910 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CT5910 +# endif +# define machine_is_ct5910() (machine_arch_type == MACH_TYPE_CT5910) +#else +# define machine_is_ct5910() (0) +#endif + +#ifdef CONFIG_MACH_CT5912 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CT5912 +# endif +# define machine_is_ct5912() (machine_arch_type == MACH_TYPE_CT5912) +#else +# define machine_is_ct5912() (0) +#endif + +#ifdef CONFIG_MACH_HYNET_INE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HYNET_INE +# endif +# define machine_is_argonst_foundation() (machine_arch_type == MACH_TYPE_HYNET_INE) +#else +# define machine_is_argonst_foundation() (0) +#endif + +#ifdef CONFIG_MACH_HYNET_APP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HYNET_APP +# endif +# define machine_is_hynet_app() (machine_arch_type == MACH_TYPE_HYNET_APP) +#else +# define machine_is_hynet_app() (0) +#endif + +#ifdef CONFIG_MACH_MSM7200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7200 +# endif +# define machine_is_msm7200() (machine_arch_type == MACH_TYPE_MSM7200) +#else +# define machine_is_msm7200() (0) +#endif + +#ifdef CONFIG_MACH_MSM7600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7600 +# endif +# define machine_is_msm7600() (machine_arch_type == MACH_TYPE_MSM7600) +#else +# define machine_is_msm7600() (0) +#endif + +#ifdef CONFIG_MACH_CEB255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEB255 +# endif +# define machine_is_ceb255() (machine_arch_type == MACH_TYPE_CEB255) +#else +# define machine_is_ceb255() (0) +#endif + +#ifdef CONFIG_MACH_CIEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CIEL +# endif +# define machine_is_ciel() (machine_arch_type == MACH_TYPE_CIEL) +#else +# define machine_is_ciel() (0) +#endif + +#ifdef CONFIG_MACH_SLM5650 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SLM5650 +# endif +# define machine_is_slm5650() (machine_arch_type == MACH_TYPE_SLM5650) +#else +# define machine_is_slm5650() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9RLEK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9RLEK +# endif +# define machine_is_at91sam9rlek() (machine_arch_type == MACH_TYPE_AT91SAM9RLEK) +#else +# define machine_is_at91sam9rlek() (0) +#endif + +#ifdef CONFIG_MACH_COMTECH_ROUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMTECH_ROUTER +# endif +# define machine_is_comtech_router() (machine_arch_type == MACH_TYPE_COMTECH_ROUTER) +#else +# define machine_is_comtech_router() (0) +#endif + +#ifdef CONFIG_MACH_SBC2410X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC2410X +# endif +# define machine_is_sbc2410x() (machine_arch_type == MACH_TYPE_SBC2410X) +#else +# define machine_is_sbc2410x() (0) +#endif + +#ifdef CONFIG_MACH_AT4X0BD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT4X0BD +# endif +# define machine_is_at4x0bd() (machine_arch_type == MACH_TYPE_AT4X0BD) +#else +# define machine_is_at4x0bd() (0) +#endif + +#ifdef CONFIG_MACH_CBIFR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CBIFR +# endif +# define machine_is_cbifr() (machine_arch_type == MACH_TYPE_CBIFR) +#else +# define machine_is_cbifr() (0) +#endif + +#ifdef CONFIG_MACH_ARCOM_QUANTUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCOM_QUANTUM +# endif +# define machine_is_arcom_quantum() (machine_arch_type == MACH_TYPE_ARCOM_QUANTUM) +#else +# define machine_is_arcom_quantum() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX520 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX520 +# endif +# define machine_is_matrix520() (machine_arch_type == MACH_TYPE_MATRIX520) +#else +# define machine_is_matrix520() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX510 +# endif +# define machine_is_matrix510() (machine_arch_type == MACH_TYPE_MATRIX510) +#else +# define machine_is_matrix510() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX500 +# endif +# define machine_is_matrix500() (machine_arch_type == MACH_TYPE_MATRIX500) +#else +# define machine_is_matrix500() (0) +#endif + +#ifdef CONFIG_MACH_M501 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M501 +# endif +# define machine_is_m501() (machine_arch_type == MACH_TYPE_M501) +#else +# define machine_is_m501() (0) +#endif + +#ifdef CONFIG_MACH_AAEON1270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AAEON1270 +# endif +# define machine_is_aaeon1270() (machine_arch_type == MACH_TYPE_AAEON1270) +#else +# define machine_is_aaeon1270() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX500EV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX500EV +# endif +# define machine_is_matrix500ev() (machine_arch_type == MACH_TYPE_MATRIX500EV) +#else +# define machine_is_matrix500ev() (0) +#endif + +#ifdef CONFIG_MACH_PAC500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PAC500 +# endif +# define machine_is_pac500() (machine_arch_type == MACH_TYPE_PAC500) +#else +# define machine_is_pac500() (0) +#endif + +#ifdef CONFIG_MACH_PNX8181 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX8181 +# endif +# define machine_is_pnx8181() (machine_arch_type == MACH_TYPE_PNX8181) +#else +# define machine_is_pnx8181() (0) +#endif + +#ifdef CONFIG_MACH_COLIBRI320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI320 +# endif +# define machine_is_colibri320() (machine_arch_type == MACH_TYPE_COLIBRI320) +#else +# define machine_is_colibri320() (0) +#endif + +#ifdef CONFIG_MACH_AZTOOLBB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AZTOOLBB +# endif +# define machine_is_aztoolbb() (machine_arch_type == MACH_TYPE_AZTOOLBB) +#else +# define machine_is_aztoolbb() (0) +#endif + +#ifdef CONFIG_MACH_AZTOOLG2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AZTOOLG2 +# endif +# define machine_is_aztoolg2() (machine_arch_type == MACH_TYPE_AZTOOLG2) +#else +# define machine_is_aztoolg2() (0) +#endif + +#ifdef CONFIG_MACH_DVLHOST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DVLHOST +# endif +# define machine_is_dvlhost() (machine_arch_type == MACH_TYPE_DVLHOST) +#else +# define machine_is_dvlhost() (0) +#endif + +#ifdef CONFIG_MACH_ZIR9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZIR9200 +# endif +# define machine_is_zir9200() (machine_arch_type == MACH_TYPE_ZIR9200) +#else +# define machine_is_zir9200() (0) +#endif + +#ifdef CONFIG_MACH_ZIR9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZIR9260 +# endif +# define machine_is_zir9260() (machine_arch_type == MACH_TYPE_ZIR9260) +#else +# define machine_is_zir9260() (0) +#endif + +#ifdef CONFIG_MACH_COCOPAH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COCOPAH +# endif +# define machine_is_cocopah() (machine_arch_type == MACH_TYPE_COCOPAH) +#else +# define machine_is_cocopah() (0) +#endif + +#ifdef CONFIG_MACH_NDS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NDS +# endif +# define machine_is_nds() (machine_arch_type == MACH_TYPE_NDS) +#else +# define machine_is_nds() (0) +#endif + +#ifdef CONFIG_MACH_ROSENCRANTZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROSENCRANTZ +# endif +# define machine_is_rosencrantz() (machine_arch_type == MACH_TYPE_ROSENCRANTZ) +#else +# define machine_is_rosencrantz() (0) +#endif + +#ifdef CONFIG_MACH_FTTX_ODSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FTTX_ODSC +# endif +# define machine_is_fttx_odsc() (machine_arch_type == MACH_TYPE_FTTX_ODSC) +#else +# define machine_is_fttx_odsc() (0) +#endif + +#ifdef CONFIG_MACH_CLASSE_R6904 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLASSE_R6904 +# endif +# define machine_is_classe_r6904() (machine_arch_type == MACH_TYPE_CLASSE_R6904) +#else +# define machine_is_classe_r6904() (0) +#endif + +#ifdef CONFIG_MACH_CAM60 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAM60 +# endif +# define machine_is_cam60() (machine_arch_type == MACH_TYPE_CAM60) +#else +# define machine_is_cam60() (0) +#endif + +#ifdef CONFIG_MACH_MXC30031ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC30031ADS +# endif +# define machine_is_mxc30031ads() (machine_arch_type == MACH_TYPE_MXC30031ADS) +#else +# define machine_is_mxc30031ads() (0) +#endif + +#ifdef CONFIG_MACH_DATACALL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DATACALL +# endif +# define machine_is_datacall() (machine_arch_type == MACH_TYPE_DATACALL) +#else +# define machine_is_datacall() (0) +#endif + +#ifdef CONFIG_MACH_AT91EB01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91EB01 +# endif +# define machine_is_at91eb01() (machine_arch_type == MACH_TYPE_AT91EB01) +#else +# define machine_is_at91eb01() (0) +#endif + +#ifdef CONFIG_MACH_RTY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTY +# endif +# define machine_is_rty() (machine_arch_type == MACH_TYPE_RTY) +#else +# define machine_is_rty() (0) +#endif + +#ifdef CONFIG_MACH_DWL2100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DWL2100 +# endif +# define machine_is_dwl2100() (machine_arch_type == MACH_TYPE_DWL2100) +#else +# define machine_is_dwl2100() (0) +#endif + +#ifdef CONFIG_MACH_VINSI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VINSI +# endif +# define machine_is_vinsi() (machine_arch_type == MACH_TYPE_VINSI) +#else +# define machine_is_vinsi() (0) +#endif + +#ifdef CONFIG_MACH_DB88F5281 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DB88F5281 +# endif +# define machine_is_db88f5281() (machine_arch_type == MACH_TYPE_DB88F5281) +#else +# define machine_is_db88f5281() (0) +#endif + +#ifdef CONFIG_MACH_CSB726 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB726 +# endif +# define machine_is_csb726() (machine_arch_type == MACH_TYPE_CSB726) +#else +# define machine_is_csb726() (0) +#endif + +#ifdef CONFIG_MACH_TIK27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIK27 +# endif +# define machine_is_tik27() (machine_arch_type == MACH_TYPE_TIK27) +#else +# define machine_is_tik27() (0) +#endif + +#ifdef CONFIG_MACH_MX_UC7420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX_UC7420 +# endif +# define machine_is_mx_uc7420() (machine_arch_type == MACH_TYPE_MX_UC7420) +#else +# define machine_is_mx_uc7420() (0) +#endif + +#ifdef CONFIG_MACH_RIRM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIRM3 +# endif +# define machine_is_rirm3() (machine_arch_type == MACH_TYPE_RIRM3) +#else +# define machine_is_rirm3() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_ODYSSEY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_ODYSSEY +# endif +# define machine_is_pelco_odyssey() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEY) +#else +# define machine_is_pelco_odyssey() (0) +#endif + +#ifdef CONFIG_MACH_ADX_ABOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_ABOX +# endif +# define machine_is_adx_abox() (machine_arch_type == MACH_TYPE_ADX_ABOX) +#else +# define machine_is_adx_abox() (0) +#endif + +#ifdef CONFIG_MACH_ADX_TPID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_TPID +# endif +# define machine_is_adx_tpid() (machine_arch_type == MACH_TYPE_ADX_TPID) +#else +# define machine_is_adx_tpid() (0) +#endif + +#ifdef CONFIG_MACH_MINICHECK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINICHECK +# endif +# define machine_is_minicheck() (machine_arch_type == MACH_TYPE_MINICHECK) +#else +# define machine_is_minicheck() (0) +#endif + +#ifdef CONFIG_MACH_IDAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IDAM +# endif +# define machine_is_idam() (machine_arch_type == MACH_TYPE_IDAM) +#else +# define machine_is_idam() (0) +#endif + +#ifdef CONFIG_MACH_MARIO_MX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARIO_MX +# endif +# define machine_is_mario_mx() (machine_arch_type == MACH_TYPE_MARIO_MX) +#else +# define machine_is_mario_mx() (0) +#endif + +#ifdef CONFIG_MACH_VI1888 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VI1888 +# endif +# define machine_is_vi1888() (machine_arch_type == MACH_TYPE_VI1888) +#else +# define machine_is_vi1888() (0) +#endif + +#ifdef CONFIG_MACH_ZR4230 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZR4230 +# endif +# define machine_is_zr4230() (machine_arch_type == MACH_TYPE_ZR4230) +#else +# define machine_is_zr4230() (0) +#endif + +#ifdef CONFIG_MACH_T1_IX_BLUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T1_IX_BLUE +# endif +# define machine_is_t1_ix_blue() (machine_arch_type == MACH_TYPE_T1_IX_BLUE) +#else +# define machine_is_t1_ix_blue() (0) +#endif + +#ifdef CONFIG_MACH_SYHQ2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYHQ2 +# endif +# define machine_is_syhq2() (machine_arch_type == MACH_TYPE_SYHQ2) +#else +# define machine_is_syhq2() (0) +#endif + +#ifdef CONFIG_MACH_COMPUTIME_R3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMPUTIME_R3 +# endif +# define machine_is_computime_r3() (machine_arch_type == MACH_TYPE_COMPUTIME_R3) +#else +# define machine_is_computime_r3() (0) +#endif + +#ifdef CONFIG_MACH_ORATIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATIS +# endif +# define machine_is_oratis() (machine_arch_type == MACH_TYPE_ORATIS) +#else +# define machine_is_oratis() (0) +#endif + +#ifdef CONFIG_MACH_MIKKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIKKO +# endif +# define machine_is_mikko() (machine_arch_type == MACH_TYPE_MIKKO) +#else +# define machine_is_mikko() (0) +#endif + +#ifdef CONFIG_MACH_HOLON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HOLON +# endif +# define machine_is_holon() (machine_arch_type == MACH_TYPE_HOLON) +#else +# define machine_is_holon() (0) +#endif + +#ifdef CONFIG_MACH_OLIP8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLIP8 +# endif +# define machine_is_olip8() (machine_arch_type == MACH_TYPE_OLIP8) +#else +# define machine_is_olip8() (0) +#endif + +#ifdef CONFIG_MACH_GHI270HG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GHI270HG +# endif +# define machine_is_ghi270hg() (machine_arch_type == MACH_TYPE_GHI270HG) +#else +# define machine_is_ghi270hg() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM6467_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM6467_EVM +# endif +# define machine_is_davinci_dm6467_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467_EVM) +#else +# define machine_is_davinci_dm6467_evm() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM355_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM355_EVM +# endif +# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM) +#else +# define machine_is_davinci_dm355_evm() (0) +#endif + +#ifdef CONFIG_MACH_BLACKRIVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLACKRIVER +# endif +# define machine_is_blackriver() (machine_arch_type == MACH_TYPE_BLACKRIVER) +#else +# define machine_is_blackriver() (0) +#endif + +#ifdef CONFIG_MACH_SANDGATEWP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDGATEWP +# endif +# define machine_is_sandgate_wp() (machine_arch_type == MACH_TYPE_SANDGATEWP) +#else +# define machine_is_sandgate_wp() (0) +#endif + +#ifdef CONFIG_MACH_CDOTBWSG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CDOTBWSG +# endif +# define machine_is_cdotbwsg() (machine_arch_type == MACH_TYPE_CDOTBWSG) +#else +# define machine_is_cdotbwsg() (0) +#endif + +#ifdef CONFIG_MACH_QUARK963 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUARK963 +# endif +# define machine_is_quark963() (machine_arch_type == MACH_TYPE_QUARK963) +#else +# define machine_is_quark963() (0) +#endif + +#ifdef CONFIG_MACH_CSB735 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB735 +# endif +# define machine_is_csb735() (machine_arch_type == MACH_TYPE_CSB735) +#else +# define machine_is_csb735() (0) +#endif + +#ifdef CONFIG_MACH_LITTLETON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LITTLETON +# endif +# define machine_is_littleton() (machine_arch_type == MACH_TYPE_LITTLETON) +#else +# define machine_is_littleton() (0) +#endif + +#ifdef CONFIG_MACH_MIO_P550 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIO_P550 +# endif +# define machine_is_mio_p550() (machine_arch_type == MACH_TYPE_MIO_P550) +#else +# define machine_is_mio_p550() (0) +#endif + +#ifdef CONFIG_MACH_MOTION2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTION2440 +# endif +# define machine_is_motion2440() (machine_arch_type == MACH_TYPE_MOTION2440) +#else +# define machine_is_motion2440() (0) +#endif + +#ifdef CONFIG_MACH_IMM500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMM500 +# endif +# define machine_is_imm500() (machine_arch_type == MACH_TYPE_IMM500) +#else +# define machine_is_imm500() (0) +#endif + +#ifdef CONFIG_MACH_HOMEMATIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HOMEMATIC +# endif +# define machine_is_homematic() (machine_arch_type == MACH_TYPE_HOMEMATIC) +#else +# define machine_is_homematic() (0) +#endif + +#ifdef CONFIG_MACH_ERMINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ERMINE +# endif +# define machine_is_ermine() (machine_arch_type == MACH_TYPE_ERMINE) +#else +# define machine_is_ermine() (0) +#endif + +#ifdef CONFIG_MACH_KB9202B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KB9202B +# endif +# define machine_is_kb9202b() (machine_arch_type == MACH_TYPE_KB9202B) +#else +# define machine_is_kb9202b() (0) +#endif + +#ifdef CONFIG_MACH_HS1XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HS1XX +# endif +# define machine_is_hs1xx() (machine_arch_type == MACH_TYPE_HS1XX) +#else +# define machine_is_hs1xx() (0) +#endif + +#ifdef CONFIG_MACH_STUDENTMATE2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STUDENTMATE2440 +# endif +# define machine_is_studentmate2440() (machine_arch_type == MACH_TYPE_STUDENTMATE2440) +#else +# define machine_is_studentmate2440() (0) +#endif + +#ifdef CONFIG_MACH_ARVOO_L1_Z1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARVOO_L1_Z1 +# endif +# define machine_is_arvoo_l1_z1() (machine_arch_type == MACH_TYPE_ARVOO_L1_Z1) +#else +# define machine_is_arvoo_l1_z1() (0) +#endif + +#ifdef CONFIG_MACH_DEP2410K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEP2410K +# endif +# define machine_is_dep2410k() (machine_arch_type == MACH_TYPE_DEP2410K) +#else +# define machine_is_dep2410k() (0) +#endif + +#ifdef CONFIG_MACH_XXSVIDEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XXSVIDEO +# endif +# define machine_is_xxsvideo() (machine_arch_type == MACH_TYPE_XXSVIDEO) +#else +# define machine_is_xxsvideo() (0) +#endif + +#ifdef CONFIG_MACH_IM4004 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IM4004 +# endif +# define machine_is_im4004() (machine_arch_type == MACH_TYPE_IM4004) +#else +# define machine_is_im4004() (0) +#endif + +#ifdef CONFIG_MACH_OCHAYA1050 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCHAYA1050 +# endif +# define machine_is_ochaya1050() (machine_arch_type == MACH_TYPE_OCHAYA1050) +#else +# define machine_is_ochaya1050() (0) +#endif + +#ifdef CONFIG_MACH_LEP9261 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEP9261 +# endif +# define machine_is_lep9261() (machine_arch_type == MACH_TYPE_LEP9261) +#else +# define machine_is_lep9261() (0) +#endif + +#ifdef CONFIG_MACH_SVENMEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVENMEB +# endif +# define machine_is_svenmeb() (machine_arch_type == MACH_TYPE_SVENMEB) +#else +# define machine_is_svenmeb() (0) +#endif + +#ifdef CONFIG_MACH_FORTUNET2NE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FORTUNET2NE +# endif +# define machine_is_fortunet2ne() (machine_arch_type == MACH_TYPE_FORTUNET2NE) +#else +# define machine_is_fortunet2ne() (0) +#endif + +#ifdef CONFIG_MACH_NXHX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXHX +# endif +# define machine_is_nxhx() (machine_arch_type == MACH_TYPE_NXHX) +#else +# define machine_is_nxhx() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_PB11MP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_PB11MP +# endif +# define machine_is_realview_pb11mp() (machine_arch_type == MACH_TYPE_REALVIEW_PB11MP) +#else +# define machine_is_realview_pb11mp() (0) +#endif + +#ifdef CONFIG_MACH_IDS500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IDS500 +# endif +# define machine_is_ids500() (machine_arch_type == MACH_TYPE_IDS500) +#else +# define machine_is_ids500() (0) +#endif + +#ifdef CONFIG_MACH_ORS_N725 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORS_N725 +# endif +# define machine_is_ors_n725() (machine_arch_type == MACH_TYPE_ORS_N725) +#else +# define machine_is_ors_n725() (0) +#endif + +#ifdef CONFIG_MACH_HSDARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HSDARM +# endif +# define machine_is_hsdarm() (machine_arch_type == MACH_TYPE_HSDARM) +#else +# define machine_is_hsdarm() (0) +#endif + +#ifdef CONFIG_MACH_SHA_PON003 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHA_PON003 +# endif +# define machine_is_sha_pon003() (machine_arch_type == MACH_TYPE_SHA_PON003) +#else +# define machine_is_sha_pon003() (0) +#endif + +#ifdef CONFIG_MACH_SHA_PON004 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHA_PON004 +# endif +# define machine_is_sha_pon004() (machine_arch_type == MACH_TYPE_SHA_PON004) +#else +# define machine_is_sha_pon004() (0) +#endif + +#ifdef CONFIG_MACH_SHA_PON007 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHA_PON007 +# endif +# define machine_is_sha_pon007() (machine_arch_type == MACH_TYPE_SHA_PON007) +#else +# define machine_is_sha_pon007() (0) +#endif + +#ifdef CONFIG_MACH_SHA_PON011 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHA_PON011 +# endif +# define machine_is_sha_pon011() (machine_arch_type == MACH_TYPE_SHA_PON011) +#else +# define machine_is_sha_pon011() (0) +#endif + +#ifdef CONFIG_MACH_H6042 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6042 +# endif +# define machine_is_h6042() (machine_arch_type == MACH_TYPE_H6042) +#else +# define machine_is_h6042() (0) +#endif + +#ifdef CONFIG_MACH_H6043 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6043 +# endif +# define machine_is_h6043() (machine_arch_type == MACH_TYPE_H6043) +#else +# define machine_is_h6043() (0) +#endif + +#ifdef CONFIG_MACH_LOOXC550 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOXC550 +# endif +# define machine_is_looxc550() (machine_arch_type == MACH_TYPE_LOOXC550) +#else +# define machine_is_looxc550() (0) +#endif + +#ifdef CONFIG_MACH_CNTY_TITAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNTY_TITAN +# endif +# define machine_is_cnty_titan() (machine_arch_type == MACH_TYPE_CNTY_TITAN) +#else +# define machine_is_cnty_titan() (0) +#endif + +#ifdef CONFIG_MACH_APP3XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APP3XX +# endif +# define machine_is_app3xx() (machine_arch_type == MACH_TYPE_APP3XX) +#else +# define machine_is_app3xx() (0) +#endif + +#ifdef CONFIG_MACH_SIDEOATSGRAMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIDEOATSGRAMA +# endif +# define machine_is_sideoatsgrama() (machine_arch_type == MACH_TYPE_SIDEOATSGRAMA) +#else +# define machine_is_sideoatsgrama() (0) +#endif + +#ifdef CONFIG_MACH_TREO700P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TREO700P +# endif +# define machine_is_treo700p() (machine_arch_type == MACH_TYPE_TREO700P) +#else +# define machine_is_treo700p() (0) +#endif + +#ifdef CONFIG_MACH_TREO700W +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TREO700W +# endif +# define machine_is_treo700w() (machine_arch_type == MACH_TYPE_TREO700W) +#else +# define machine_is_treo700w() (0) +#endif + +#ifdef CONFIG_MACH_TREO750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TREO750 +# endif +# define machine_is_treo750() (machine_arch_type == MACH_TYPE_TREO750) +#else +# define machine_is_treo750() (0) +#endif + +#ifdef CONFIG_MACH_TREO755P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TREO755P +# endif +# define machine_is_treo755p() (machine_arch_type == MACH_TYPE_TREO755P) +#else +# define machine_is_treo755p() (0) +#endif + +#ifdef CONFIG_MACH_EZREGANUT9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZREGANUT9200 +# endif +# define machine_is_ezreganut9200() (machine_arch_type == MACH_TYPE_EZREGANUT9200) +#else +# define machine_is_ezreganut9200() (0) +#endif + +#ifdef CONFIG_MACH_SARGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SARGE +# endif +# define machine_is_sarge() (machine_arch_type == MACH_TYPE_SARGE) +#else +# define machine_is_sarge() (0) +#endif + +#ifdef CONFIG_MACH_A696 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A696 +# endif +# define machine_is_a696() (machine_arch_type == MACH_TYPE_A696) +#else +# define machine_is_a696() (0) +#endif + +#ifdef CONFIG_MACH_TURTLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TURTLE +# endif +# define machine_is_turtle1916() (machine_arch_type == MACH_TYPE_TURTLE) +#else +# define machine_is_turtle1916() (0) +#endif + +#ifdef CONFIG_MACH_MX27_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27_3DS +# endif +# define machine_is_mx27_3ds() (machine_arch_type == MACH_TYPE_MX27_3DS) +#else +# define machine_is_mx27_3ds() (0) +#endif + +#ifdef CONFIG_MACH_BISHOP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BISHOP +# endif +# define machine_is_bishop() (machine_arch_type == MACH_TYPE_BISHOP) +#else +# define machine_is_bishop() (0) +#endif + +#ifdef CONFIG_MACH_PXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXX +# endif +# define machine_is_pxx() (machine_arch_type == MACH_TYPE_PXX) +#else +# define machine_is_pxx() (0) +#endif + +#ifdef CONFIG_MACH_REDWOOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REDWOOD +# endif +# define machine_is_redwood() (machine_arch_type == MACH_TYPE_REDWOOD) +#else +# define machine_is_redwood() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_2430DLP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_2430DLP +# endif +# define machine_is_omap_2430dlp() (machine_arch_type == MACH_TYPE_OMAP_2430DLP) +#else +# define machine_is_omap_2430dlp() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_2430OSK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_2430OSK +# endif +# define machine_is_omap_2430osk() (machine_arch_type == MACH_TYPE_OMAP_2430OSK) +#else +# define machine_is_omap_2430osk() (0) +#endif + +#ifdef CONFIG_MACH_SARDINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SARDINE +# endif +# define machine_is_sardine() (machine_arch_type == MACH_TYPE_SARDINE) +#else +# define machine_is_sardine() (0) +#endif + +#ifdef CONFIG_MACH_HALIBUT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HALIBUT +# endif +# define machine_is_halibut() (machine_arch_type == MACH_TYPE_HALIBUT) +#else +# define machine_is_halibut() (0) +#endif + +#ifdef CONFIG_MACH_TROUT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TROUT +# endif +# define machine_is_trout() (machine_arch_type == MACH_TYPE_TROUT) +#else +# define machine_is_trout() (0) +#endif + +#ifdef CONFIG_MACH_GOLDFISH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GOLDFISH +# endif +# define machine_is_goldfish() (machine_arch_type == MACH_TYPE_GOLDFISH) +#else +# define machine_is_goldfish() (0) +#endif + +#ifdef CONFIG_MACH_GESBC2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GESBC2440 +# endif +# define machine_is_gesbc2440() (machine_arch_type == MACH_TYPE_GESBC2440) +#else +# define machine_is_gesbc2440() (0) +#endif + +#ifdef CONFIG_MACH_NOMAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOMAD +# endif +# define machine_is_nomad() (machine_arch_type == MACH_TYPE_NOMAD) +#else +# define machine_is_nomad() (0) +#endif + +#ifdef CONFIG_MACH_ROSALIND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROSALIND +# endif +# define machine_is_rosalind() (machine_arch_type == MACH_TYPE_ROSALIND) +#else +# define machine_is_rosalind() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215 +# endif +# define machine_is_cc9p9215() (machine_arch_type == MACH_TYPE_CC9P9215) +#else +# define machine_is_cc9p9215() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9210 +# endif +# define machine_is_cc9p9210() (machine_arch_type == MACH_TYPE_CC9P9210) +#else +# define machine_is_cc9p9210() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215JS +# endif +# define machine_is_cc9p9215js() (machine_arch_type == MACH_TYPE_CC9P9215JS) +#else +# define machine_is_cc9p9215js() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9210JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9210JS +# endif +# define machine_is_cc9p9210js() (machine_arch_type == MACH_TYPE_CC9P9210JS) +#else +# define machine_is_cc9p9210js() (0) +#endif + +#ifdef CONFIG_MACH_NASFFE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NASFFE +# endif +# define machine_is_nasffe() (machine_arch_type == MACH_TYPE_NASFFE) +#else +# define machine_is_nasffe() (0) +#endif + +#ifdef CONFIG_MACH_TN2X0BD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TN2X0BD +# endif +# define machine_is_tn2x0bd() (machine_arch_type == MACH_TYPE_TN2X0BD) +#else +# define machine_is_tn2x0bd() (0) +#endif + +#ifdef CONFIG_MACH_GWMPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GWMPXA +# endif +# define machine_is_gwmpxa() (machine_arch_type == MACH_TYPE_GWMPXA) +#else +# define machine_is_gwmpxa() (0) +#endif + +#ifdef CONFIG_MACH_EXYPLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXYPLUS +# endif +# define machine_is_exyplus() (machine_arch_type == MACH_TYPE_EXYPLUS) +#else +# define machine_is_exyplus() (0) +#endif + +#ifdef CONFIG_MACH_JADOO21 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADOO21 +# endif +# define machine_is_jadoo21() (machine_arch_type == MACH_TYPE_JADOO21) +#else +# define machine_is_jadoo21() (0) +#endif + +#ifdef CONFIG_MACH_LOOXN560 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOXN560 +# endif +# define machine_is_looxn560() (machine_arch_type == MACH_TYPE_LOOXN560) +#else +# define machine_is_looxn560() (0) +#endif + +#ifdef CONFIG_MACH_BONSAI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BONSAI +# endif +# define machine_is_bonsai() (machine_arch_type == MACH_TYPE_BONSAI) +#else +# define machine_is_bonsai() (0) +#endif + +#ifdef CONFIG_MACH_ADSMILGATO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSMILGATO +# endif +# define machine_is_adsmilgato() (machine_arch_type == MACH_TYPE_ADSMILGATO) +#else +# define machine_is_adsmilgato() (0) +#endif + +#ifdef CONFIG_MACH_GBA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GBA +# endif +# define machine_is_gba() (machine_arch_type == MACH_TYPE_GBA) +#else +# define machine_is_gba() (0) +#endif + +#ifdef CONFIG_MACH_H6044 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6044 +# endif +# define machine_is_h6044() (machine_arch_type == MACH_TYPE_H6044) +#else +# define machine_is_h6044() (0) +#endif + +#ifdef CONFIG_MACH_APP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APP +# endif +# define machine_is_app() (machine_arch_type == MACH_TYPE_APP) +#else +# define machine_is_app() (0) +#endif + +#ifdef CONFIG_MACH_TCT_HAMMER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TCT_HAMMER +# endif +# define machine_is_tct_hammer() (machine_arch_type == MACH_TYPE_TCT_HAMMER) +#else +# define machine_is_tct_hammer() (0) +#endif + +#ifdef CONFIG_MACH_HERALD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERALD +# endif +# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD) +#else +# define machine_is_herald() (0) +#endif + +#ifdef CONFIG_MACH_ARTEMIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARTEMIS +# endif +# define machine_is_artemis() (machine_arch_type == MACH_TYPE_ARTEMIS) +#else +# define machine_is_artemis() (0) +#endif + +#ifdef CONFIG_MACH_HTCTITAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTITAN +# endif +# define machine_is_htctitan() (machine_arch_type == MACH_TYPE_HTCTITAN) +#else +# define machine_is_htctitan() (0) +#endif + +#ifdef CONFIG_MACH_QRANIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QRANIUM +# endif +# define machine_is_qranium() (machine_arch_type == MACH_TYPE_QRANIUM) +#else +# define machine_is_qranium() (0) +#endif + +#ifdef CONFIG_MACH_ADX_WSC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_WSC2 +# endif +# define machine_is_adx_wsc2() (machine_arch_type == MACH_TYPE_ADX_WSC2) +#else +# define machine_is_adx_wsc2() (0) +#endif + +#ifdef CONFIG_MACH_ADX_MEDCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_MEDCOM +# endif +# define machine_is_adx_medcom() (machine_arch_type == MACH_TYPE_ADX_MEDCOM) +#else +# define machine_is_adx_medcom() (0) +#endif + +#ifdef CONFIG_MACH_BBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BBOARD +# endif +# define machine_is_bboard() (machine_arch_type == MACH_TYPE_BBOARD) +#else +# define machine_is_bboard() (0) +#endif + +#ifdef CONFIG_MACH_CAMBRIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAMBRIA +# endif +# define machine_is_cambria() (machine_arch_type == MACH_TYPE_CAMBRIA) +#else +# define machine_is_cambria() (0) +#endif + +#ifdef CONFIG_MACH_MT7XXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT7XXX +# endif +# define machine_is_mt7xxx() (machine_arch_type == MACH_TYPE_MT7XXX) +#else +# define machine_is_mt7xxx() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX512 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX512 +# endif +# define machine_is_matrix512() (machine_arch_type == MACH_TYPE_MATRIX512) +#else +# define machine_is_matrix512() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX522 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX522 +# endif +# define machine_is_matrix522() (machine_arch_type == MACH_TYPE_MATRIX522) +#else +# define machine_is_matrix522() (0) +#endif + +#ifdef CONFIG_MACH_IPAC5010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPAC5010 +# endif +# define machine_is_ipac5010() (machine_arch_type == MACH_TYPE_IPAC5010) +#else +# define machine_is_ipac5010() (0) +#endif + +#ifdef CONFIG_MACH_SAKURA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAKURA +# endif +# define machine_is_sakura() (machine_arch_type == MACH_TYPE_SAKURA) +#else +# define machine_is_sakura() (0) +#endif + +#ifdef CONFIG_MACH_GROCX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GROCX +# endif +# define machine_is_grocx() (machine_arch_type == MACH_TYPE_GROCX) +#else +# define machine_is_grocx() (0) +#endif + +#ifdef CONFIG_MACH_PM9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PM9263 +# endif +# define machine_is_pm9263() (machine_arch_type == MACH_TYPE_PM9263) +#else +# define machine_is_pm9263() (0) +#endif + +#ifdef CONFIG_MACH_SIM_ONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIM_ONE +# endif +# define machine_is_sim_one() (machine_arch_type == MACH_TYPE_SIM_ONE) +#else +# define machine_is_sim_one() (0) +#endif + +#ifdef CONFIG_MACH_ACQ132 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACQ132 +# endif +# define machine_is_acq132() (machine_arch_type == MACH_TYPE_ACQ132) +#else +# define machine_is_acq132() (0) +#endif + +#ifdef CONFIG_MACH_DATR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DATR +# endif +# define machine_is_datr() (machine_arch_type == MACH_TYPE_DATR) +#else +# define machine_is_datr() (0) +#endif + +#ifdef CONFIG_MACH_ACTUX1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTUX1 +# endif +# define machine_is_actux1() (machine_arch_type == MACH_TYPE_ACTUX1) +#else +# define machine_is_actux1() (0) +#endif + +#ifdef CONFIG_MACH_ACTUX2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTUX2 +# endif +# define machine_is_actux2() (machine_arch_type == MACH_TYPE_ACTUX2) +#else +# define machine_is_actux2() (0) +#endif + +#ifdef CONFIG_MACH_ACTUX3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTUX3 +# endif +# define machine_is_actux3() (machine_arch_type == MACH_TYPE_ACTUX3) +#else +# define machine_is_actux3() (0) +#endif + +#ifdef CONFIG_MACH_FLEXIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLEXIT +# endif +# define machine_is_flexit() (machine_arch_type == MACH_TYPE_FLEXIT) +#else +# define machine_is_flexit() (0) +#endif + +#ifdef CONFIG_MACH_BH2X0BD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BH2X0BD +# endif +# define machine_is_bh2x0bd() (machine_arch_type == MACH_TYPE_BH2X0BD) +#else +# define machine_is_bh2x0bd() (0) +#endif + +#ifdef CONFIG_MACH_ATB2002 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATB2002 +# endif +# define machine_is_atb2002() (machine_arch_type == MACH_TYPE_ATB2002) +#else +# define machine_is_atb2002() (0) +#endif + +#ifdef CONFIG_MACH_XENON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XENON +# endif +# define machine_is_xenon() (machine_arch_type == MACH_TYPE_XENON) +#else +# define machine_is_xenon() (0) +#endif + +#ifdef CONFIG_MACH_FM607 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FM607 +# endif +# define machine_is_fm607() (machine_arch_type == MACH_TYPE_FM607) +#else +# define machine_is_fm607() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX514 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX514 +# endif +# define machine_is_matrix514() (machine_arch_type == MACH_TYPE_MATRIX514) +#else +# define machine_is_matrix514() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX524 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX524 +# endif +# define machine_is_matrix524() (machine_arch_type == MACH_TYPE_MATRIX524) +#else +# define machine_is_matrix524() (0) +#endif + +#ifdef CONFIG_MACH_INPOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INPOD +# endif +# define machine_is_inpod() (machine_arch_type == MACH_TYPE_INPOD) +#else +# define machine_is_inpod() (0) +#endif + +#ifdef CONFIG_MACH_JIVE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JIVE +# endif +# define machine_is_jive() (machine_arch_type == MACH_TYPE_JIVE) +#else +# define machine_is_jive() (0) +#endif + +#ifdef CONFIG_MACH_TLL_MX21 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TLL_MX21 +# endif +# define machine_is_tll_mx21() (machine_arch_type == MACH_TYPE_TLL_MX21) +#else +# define machine_is_tll_mx21() (0) +#endif + +#ifdef CONFIG_MACH_SBC2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC2800 +# endif +# define machine_is_sbc2800() (machine_arch_type == MACH_TYPE_SBC2800) +#else +# define machine_is_sbc2800() (0) +#endif + +#ifdef CONFIG_MACH_CC7UCAMRY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC7UCAMRY +# endif +# define machine_is_cc7ucamry() (machine_arch_type == MACH_TYPE_CC7UCAMRY) +#else +# define machine_is_cc7ucamry() (0) +#endif + +#ifdef CONFIG_MACH_UBISYS_P9_SC15 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UBISYS_P9_SC15 +# endif +# define machine_is_ubisys_p9_sc15() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC15) +#else +# define machine_is_ubisys_p9_sc15() (0) +#endif + +#ifdef CONFIG_MACH_UBISYS_P9_SSC2D10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UBISYS_P9_SSC2D10 +# endif +# define machine_is_ubisys_p9_ssc2d10() (machine_arch_type == MACH_TYPE_UBISYS_P9_SSC2D10) +#else +# define machine_is_ubisys_p9_ssc2d10() (0) +#endif + +#ifdef CONFIG_MACH_UBISYS_P9_RCU3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UBISYS_P9_RCU3 +# endif +# define machine_is_ubisys_p9_rcu3() (machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3) +#else +# define machine_is_ubisys_p9_rcu3() (0) +#endif + +#ifdef CONFIG_MACH_AML_M8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AML_M8000 +# endif +# define machine_is_aml_m8000() (machine_arch_type == MACH_TYPE_AML_M8000) +#else +# define machine_is_aml_m8000() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER_270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER_270 +# endif +# define machine_is_snapper_270() (machine_arch_type == MACH_TYPE_SNAPPER_270) +#else +# define machine_is_snapper_270() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_BBX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_BBX +# endif +# define machine_is_omap_bbx() (machine_arch_type == MACH_TYPE_OMAP_BBX) +#else +# define machine_is_omap_bbx() (0) +#endif + +#ifdef CONFIG_MACH_UCN2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UCN2410 +# endif +# define machine_is_ucn2410() (machine_arch_type == MACH_TYPE_UCN2410) +#else +# define machine_is_ucn2410() (0) +#endif + +#ifdef CONFIG_MACH_SAM9_L9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAM9_L9260 +# endif +# define machine_is_sam9_l9260() (machine_arch_type == MACH_TYPE_SAM9_L9260) +#else +# define machine_is_sam9_l9260() (0) +#endif + +#ifdef CONFIG_MACH_ETI_C2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETI_C2 +# endif +# define machine_is_eti_c2() (machine_arch_type == MACH_TYPE_ETI_C2) +#else +# define machine_is_eti_c2() (0) +#endif + +#ifdef CONFIG_MACH_AVALANCHE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVALANCHE +# endif +# define machine_is_avalanche() (machine_arch_type == MACH_TYPE_AVALANCHE) +#else +# define machine_is_avalanche() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_PB1176 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_PB1176 +# endif +# define machine_is_realview_pb1176() (machine_arch_type == MACH_TYPE_REALVIEW_PB1176) +#else +# define machine_is_realview_pb1176() (0) +#endif + +#ifdef CONFIG_MACH_DP1500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DP1500 +# endif +# define machine_is_dp1500() (machine_arch_type == MACH_TYPE_DP1500) +#else +# define machine_is_dp1500() (0) +#endif + +#ifdef CONFIG_MACH_APPLE_IPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APPLE_IPHONE +# endif +# define machine_is_apple_iphone() (machine_arch_type == MACH_TYPE_APPLE_IPHONE) +#else +# define machine_is_apple_iphone() (0) +#endif + +#ifdef CONFIG_MACH_YL9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YL9200 +# endif +# define machine_is_yl9200() (machine_arch_type == MACH_TYPE_YL9200) +#else +# define machine_is_yl9200() (0) +#endif + +#ifdef CONFIG_MACH_RD88F5182 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F5182 +# endif +# define machine_is_rd88f5182() (machine_arch_type == MACH_TYPE_RD88F5182) +#else +# define machine_is_rd88f5182() (0) +#endif + +#ifdef CONFIG_MACH_KUROBOX_PRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KUROBOX_PRO +# endif +# define machine_is_kurobox_pro() (machine_arch_type == MACH_TYPE_KUROBOX_PRO) +#else +# define machine_is_kurobox_pro() (0) +#endif + +#ifdef CONFIG_MACH_SE_POET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SE_POET +# endif +# define machine_is_se_poet() (machine_arch_type == MACH_TYPE_SE_POET) +#else +# define machine_is_se_poet() (0) +#endif + +#ifdef CONFIG_MACH_MX31_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31_3DS +# endif +# define machine_is_mx31_3ds() (machine_arch_type == MACH_TYPE_MX31_3DS) +#else +# define machine_is_mx31_3ds() (0) +#endif + +#ifdef CONFIG_MACH_R270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_R270 +# endif +# define machine_is_r270() (machine_arch_type == MACH_TYPE_R270) +#else +# define machine_is_r270() (0) +#endif + +#ifdef CONFIG_MACH_ARMOUR21 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMOUR21 +# endif +# define machine_is_armour21() (machine_arch_type == MACH_TYPE_ARMOUR21) +#else +# define machine_is_armour21() (0) +#endif + +#ifdef CONFIG_MACH_DT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DT2 +# endif +# define machine_is_dt2() (machine_arch_type == MACH_TYPE_DT2) +#else +# define machine_is_dt2() (0) +#endif + +#ifdef CONFIG_MACH_VT4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VT4 +# endif +# define machine_is_vt4() (machine_arch_type == MACH_TYPE_VT4) +#else +# define machine_is_vt4() (0) +#endif + +#ifdef CONFIG_MACH_TYCO320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TYCO320 +# endif +# define machine_is_tyco320() (machine_arch_type == MACH_TYPE_TYCO320) +#else +# define machine_is_tyco320() (0) +#endif + +#ifdef CONFIG_MACH_ADMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADMA +# endif +# define machine_is_adma() (machine_arch_type == MACH_TYPE_ADMA) +#else +# define machine_is_adma() (0) +#endif + +#ifdef CONFIG_MACH_WP188 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WP188 +# endif +# define machine_is_wp188() (machine_arch_type == MACH_TYPE_WP188) +#else +# define machine_is_wp188() (0) +#endif + +#ifdef CONFIG_MACH_CORSICA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORSICA +# endif +# define machine_is_corsica() (machine_arch_type == MACH_TYPE_CORSICA) +#else +# define machine_is_corsica() (0) +#endif + +#ifdef CONFIG_MACH_BIGEYE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIGEYE +# endif +# define machine_is_bigeye() (machine_arch_type == MACH_TYPE_BIGEYE) +#else +# define machine_is_bigeye() (0) +#endif + +#ifdef CONFIG_MACH_TLL5000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TLL5000 +# endif +# define machine_is_tll5000() (machine_arch_type == MACH_TYPE_TLL5000) +#else +# define machine_is_tll5000() (0) +#endif + +#ifdef CONFIG_MACH_BEBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEBOT +# endif +# define machine_is_bebot() (machine_arch_type == MACH_TYPE_BEBOT) +#else +# define machine_is_bebot() (0) +#endif + +#ifdef CONFIG_MACH_QONG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QONG +# endif +# define machine_is_qong() (machine_arch_type == MACH_TYPE_QONG) +#else +# define machine_is_qong() (0) +#endif + +#ifdef CONFIG_MACH_TCOMPACT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TCOMPACT +# endif +# define machine_is_tcompact() (machine_arch_type == MACH_TYPE_TCOMPACT) +#else +# define machine_is_tcompact() (0) +#endif + +#ifdef CONFIG_MACH_PUMA5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PUMA5 +# endif +# define machine_is_puma5() (machine_arch_type == MACH_TYPE_PUMA5) +#else +# define machine_is_puma5() (0) +#endif + +#ifdef CONFIG_MACH_ELARA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELARA +# endif +# define machine_is_elara() (machine_arch_type == MACH_TYPE_ELARA) +#else +# define machine_is_elara() (0) +#endif + +#ifdef CONFIG_MACH_ELLINGTON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELLINGTON +# endif +# define machine_is_ellington() (machine_arch_type == MACH_TYPE_ELLINGTON) +#else +# define machine_is_ellington() (0) +#endif + +#ifdef CONFIG_MACH_XDA_ATOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XDA_ATOM +# endif +# define machine_is_xda_atom() (machine_arch_type == MACH_TYPE_XDA_ATOM) +#else +# define machine_is_xda_atom() (0) +#endif + +#ifdef CONFIG_MACH_ENERGIZER2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENERGIZER2 +# endif +# define machine_is_energizer2() (machine_arch_type == MACH_TYPE_ENERGIZER2) +#else +# define machine_is_energizer2() (0) +#endif + +#ifdef CONFIG_MACH_ODIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ODIN +# endif +# define machine_is_odin() (machine_arch_type == MACH_TYPE_ODIN) +#else +# define machine_is_odin() (0) +#endif + +#ifdef CONFIG_MACH_ACTUX4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTUX4 +# endif +# define machine_is_actux4() (machine_arch_type == MACH_TYPE_ACTUX4) +#else +# define machine_is_actux4() (0) +#endif + +#ifdef CONFIG_MACH_ESL_OMAP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_OMAP +# endif +# define machine_is_esl_omap() (machine_arch_type == MACH_TYPE_ESL_OMAP) +#else +# define machine_is_esl_omap() (0) +#endif + +#ifdef CONFIG_MACH_OMAP2EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP2EVM +# endif +# define machine_is_omap2evm() (machine_arch_type == MACH_TYPE_OMAP2EVM) +#else +# define machine_is_omap2evm() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3EVM +# endif +# define machine_is_omap3evm() (machine_arch_type == MACH_TYPE_OMAP3EVM) +#else +# define machine_is_omap3evm() (0) +#endif + +#ifdef CONFIG_MACH_ADX_PCU57 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_PCU57 +# endif +# define machine_is_adx_pcu57() (machine_arch_type == MACH_TYPE_ADX_PCU57) +#else +# define machine_is_adx_pcu57() (0) +#endif + +#ifdef CONFIG_MACH_MONACO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MONACO +# endif +# define machine_is_monaco() (machine_arch_type == MACH_TYPE_MONACO) +#else +# define machine_is_monaco() (0) +#endif + +#ifdef CONFIG_MACH_LEVANTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEVANTE +# endif +# define machine_is_levante() (machine_arch_type == MACH_TYPE_LEVANTE) +#else +# define machine_is_levante() (0) +#endif + +#ifdef CONFIG_MACH_TMXIPX425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TMXIPX425 +# endif +# define machine_is_tmxipx425() (machine_arch_type == MACH_TYPE_TMXIPX425) +#else +# define machine_is_tmxipx425() (0) +#endif + +#ifdef CONFIG_MACH_LEEP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEEP +# endif +# define machine_is_leep() (machine_arch_type == MACH_TYPE_LEEP) +#else +# define machine_is_leep() (0) +#endif + +#ifdef CONFIG_MACH_RAAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAAD +# endif +# define machine_is_raad() (machine_arch_type == MACH_TYPE_RAAD) +#else +# define machine_is_raad() (0) +#endif + +#ifdef CONFIG_MACH_DNS323 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DNS323 +# endif +# define machine_is_dns323() (machine_arch_type == MACH_TYPE_DNS323) +#else +# define machine_is_dns323() (0) +#endif + +#ifdef CONFIG_MACH_AP1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP1000 +# endif +# define machine_is_ap1000() (machine_arch_type == MACH_TYPE_AP1000) +#else +# define machine_is_ap1000() (0) +#endif + +#ifdef CONFIG_MACH_A9SAM6432 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9SAM6432 +# endif +# define machine_is_a9sam6432() (machine_arch_type == MACH_TYPE_A9SAM6432) +#else +# define machine_is_a9sam6432() (0) +#endif + +#ifdef CONFIG_MACH_SHINY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHINY +# endif +# define machine_is_shiny() (machine_arch_type == MACH_TYPE_SHINY) +#else +# define machine_is_shiny() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BEAGLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BEAGLE +# endif +# define machine_is_omap3_beagle() (machine_arch_type == MACH_TYPE_OMAP3_BEAGLE) +#else +# define machine_is_omap3_beagle() (0) +#endif + +#ifdef CONFIG_MACH_CSR_BDB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSR_BDB2 +# endif +# define machine_is_csr_bdb2() (machine_arch_type == MACH_TYPE_CSR_BDB2) +#else +# define machine_is_csr_bdb2() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA_N810 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA_N810 +# endif +# define machine_is_nokia_n810() (machine_arch_type == MACH_TYPE_NOKIA_N810) +#else +# define machine_is_nokia_n810() (0) +#endif + +#ifdef CONFIG_MACH_C270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C270 +# endif +# define machine_is_c270() (machine_arch_type == MACH_TYPE_C270) +#else +# define machine_is_c270() (0) +#endif + +#ifdef CONFIG_MACH_SENTRY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SENTRY +# endif +# define machine_is_sentry() (machine_arch_type == MACH_TYPE_SENTRY) +#else +# define machine_is_sentry() (0) +#endif + +#ifdef CONFIG_MACH_PCM038 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM038 +# endif +# define machine_is_pcm038() (machine_arch_type == MACH_TYPE_PCM038) +#else +# define machine_is_pcm038() (0) +#endif + +#ifdef CONFIG_MACH_ANC300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANC300 +# endif +# define machine_is_anc300() (machine_arch_type == MACH_TYPE_ANC300) +#else +# define machine_is_anc300() (0) +#endif + +#ifdef CONFIG_MACH_HTCKAISER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCKAISER +# endif +# define machine_is_htckaiser() (machine_arch_type == MACH_TYPE_HTCKAISER) +#else +# define machine_is_htckaiser() (0) +#endif + +#ifdef CONFIG_MACH_SBAT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBAT100 +# endif +# define machine_is_sbat100() (machine_arch_type == MACH_TYPE_SBAT100) +#else +# define machine_is_sbat100() (0) +#endif + +#ifdef CONFIG_MACH_MODUNORM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MODUNORM +# endif +# define machine_is_modunorm() (machine_arch_type == MACH_TYPE_MODUNORM) +#else +# define machine_is_modunorm() (0) +#endif + +#ifdef CONFIG_MACH_PELOS_TWARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELOS_TWARM +# endif +# define machine_is_pelos_twarm() (machine_arch_type == MACH_TYPE_PELOS_TWARM) +#else +# define machine_is_pelos_twarm() (0) +#endif + +#ifdef CONFIG_MACH_FLANK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLANK +# endif +# define machine_is_flank() (machine_arch_type == MACH_TYPE_FLANK) +#else +# define machine_is_flank() (0) +#endif + +#ifdef CONFIG_MACH_SIRLOIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIRLOIN +# endif +# define machine_is_sirloin() (machine_arch_type == MACH_TYPE_SIRLOIN) +#else +# define machine_is_sirloin() (0) +#endif + +#ifdef CONFIG_MACH_BRISKET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRISKET +# endif +# define machine_is_brisket() (machine_arch_type == MACH_TYPE_BRISKET) +#else +# define machine_is_brisket() (0) +#endif + +#ifdef CONFIG_MACH_CHUCK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHUCK +# endif +# define machine_is_chuck() (machine_arch_type == MACH_TYPE_CHUCK) +#else +# define machine_is_chuck() (0) +#endif + +#ifdef CONFIG_MACH_OTTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTTER +# endif +# define machine_is_otter() (machine_arch_type == MACH_TYPE_OTTER) +#else +# define machine_is_otter() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_LDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_LDK +# endif +# define machine_is_davinci_ldk() (machine_arch_type == MACH_TYPE_DAVINCI_LDK) +#else +# define machine_is_davinci_ldk() (0) +#endif + +#ifdef CONFIG_MACH_PHREEDOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHREEDOM +# endif +# define machine_is_phreedom() (machine_arch_type == MACH_TYPE_PHREEDOM) +#else +# define machine_is_phreedom() (0) +#endif + +#ifdef CONFIG_MACH_SG310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG310 +# endif +# define machine_is_sg310() (machine_arch_type == MACH_TYPE_SG310) +#else +# define machine_is_sg310() (0) +#endif + +#ifdef CONFIG_MACH_TS209 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS209 +# endif +# define machine_is_ts_x09() (machine_arch_type == MACH_TYPE_TS209) +#else +# define machine_is_ts_x09() (0) +#endif + +#ifdef CONFIG_MACH_AT91CAP9ADK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91CAP9ADK +# endif +# define machine_is_at91cap9adk() (machine_arch_type == MACH_TYPE_AT91CAP9ADK) +#else +# define machine_is_at91cap9adk() (0) +#endif + +#ifdef CONFIG_MACH_TION9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TION9315 +# endif +# define machine_is_tion9315() (machine_arch_type == MACH_TYPE_TION9315) +#else +# define machine_is_tion9315() (0) +#endif + +#ifdef CONFIG_MACH_MAST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAST +# endif +# define machine_is_mast() (machine_arch_type == MACH_TYPE_MAST) +#else +# define machine_is_mast() (0) +#endif + +#ifdef CONFIG_MACH_PFW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PFW +# endif +# define machine_is_pfw() (machine_arch_type == MACH_TYPE_PFW) +#else +# define machine_is_pfw() (0) +#endif + +#ifdef CONFIG_MACH_YL_P2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YL_P2440 +# endif +# define machine_is_yl_p2440() (machine_arch_type == MACH_TYPE_YL_P2440) +#else +# define machine_is_yl_p2440() (0) +#endif + +#ifdef CONFIG_MACH_ZSBC32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZSBC32 +# endif +# define machine_is_zsbc32() (machine_arch_type == MACH_TYPE_ZSBC32) +#else +# define machine_is_zsbc32() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PACE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PACE2 +# endif +# define machine_is_omap_pace2() (machine_arch_type == MACH_TYPE_OMAP_PACE2) +#else +# define machine_is_omap_pace2() (0) +#endif + +#ifdef CONFIG_MACH_IMX_PACE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX_PACE2 +# endif +# define machine_is_imx_pace2() (machine_arch_type == MACH_TYPE_IMX_PACE2) +#else +# define machine_is_imx_pace2() (0) +#endif + +#ifdef CONFIG_MACH_MX31MOBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31MOBOARD +# endif +# define machine_is_mx31moboard() (machine_arch_type == MACH_TYPE_MX31MOBOARD) +#else +# define machine_is_mx31moboard() (0) +#endif + +#ifdef CONFIG_MACH_MX37_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX37_3DS +# endif +# define machine_is_mx37_3ds() (machine_arch_type == MACH_TYPE_MX37_3DS) +#else +# define machine_is_mx37_3ds() (0) +#endif + +#ifdef CONFIG_MACH_RCC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RCC +# endif +# define machine_is_rcc() (machine_arch_type == MACH_TYPE_RCC) +#else +# define machine_is_rcc() (0) +#endif + +#ifdef CONFIG_MACH_ARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM9 +# endif +# define machine_is_dmp() (machine_arch_type == MACH_TYPE_ARM9) +#else +# define machine_is_dmp() (0) +#endif + +#ifdef CONFIG_MACH_VISION_EP9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VISION_EP9307 +# endif +# define machine_is_vision_ep9307() (machine_arch_type == MACH_TYPE_VISION_EP9307) +#else +# define machine_is_vision_ep9307() (0) +#endif + +#ifdef CONFIG_MACH_SCLY1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCLY1000 +# endif +# define machine_is_scly1000() (machine_arch_type == MACH_TYPE_SCLY1000) +#else +# define machine_is_scly1000() (0) +#endif + +#ifdef CONFIG_MACH_FONTEL_EP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FONTEL_EP +# endif +# define machine_is_fontel_ep() (machine_arch_type == MACH_TYPE_FONTEL_EP) +#else +# define machine_is_fontel_ep() (0) +#endif + +#ifdef CONFIG_MACH_VOICEBLUE3G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOICEBLUE3G +# endif +# define machine_is_voiceblue3g() (machine_arch_type == MACH_TYPE_VOICEBLUE3G) +#else +# define machine_is_voiceblue3g() (0) +#endif + +#ifdef CONFIG_MACH_TT9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT9200 +# endif +# define machine_is_tt9200() (machine_arch_type == MACH_TYPE_TT9200) +#else +# define machine_is_tt9200() (0) +#endif + +#ifdef CONFIG_MACH_DIGI2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DIGI2410 +# endif +# define machine_is_digi2410() (machine_arch_type == MACH_TYPE_DIGI2410) +#else +# define machine_is_digi2410() (0) +#endif + +#ifdef CONFIG_MACH_TERASTATION_PRO2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERASTATION_PRO2 +# endif +# define machine_is_terastation_pro2() (machine_arch_type == MACH_TYPE_TERASTATION_PRO2) +#else +# define machine_is_terastation_pro2() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_PRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_PRO +# endif +# define machine_is_linkstation_pro() (machine_arch_type == MACH_TYPE_LINKSTATION_PRO) +#else +# define machine_is_linkstation_pro() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_A780 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_A780 +# endif +# define machine_is_motorola_a780() (machine_arch_type == MACH_TYPE_MOTOROLA_A780) +#else +# define machine_is_motorola_a780() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_E6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_E6 +# endif +# define machine_is_motorola_e6() (machine_arch_type == MACH_TYPE_MOTOROLA_E6) +#else +# define machine_is_motorola_e6() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_E2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_E2 +# endif +# define machine_is_motorola_e2() (machine_arch_type == MACH_TYPE_MOTOROLA_E2) +#else +# define machine_is_motorola_e2() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_E680 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_E680 +# endif +# define machine_is_motorola_e680() (machine_arch_type == MACH_TYPE_MOTOROLA_E680) +#else +# define machine_is_motorola_e680() (0) +#endif + +#ifdef CONFIG_MACH_UR2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UR2410 +# endif +# define machine_is_ur2410() (machine_arch_type == MACH_TYPE_UR2410) +#else +# define machine_is_ur2410() (0) +#endif + +#ifdef CONFIG_MACH_TAS9261 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAS9261 +# endif +# define machine_is_tas9261() (machine_arch_type == MACH_TYPE_TAS9261) +#else +# define machine_is_tas9261() (0) +#endif + +#ifdef CONFIG_MACH_HERMES_HD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERMES_HD +# endif +# define machine_is_davinci_hermes_hd() (machine_arch_type == MACH_TYPE_HERMES_HD) +#else +# define machine_is_davinci_hermes_hd() (0) +#endif + +#ifdef CONFIG_MACH_PERSEO_HD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PERSEO_HD +# endif +# define machine_is_davinci_perseo_hd() (machine_arch_type == MACH_TYPE_PERSEO_HD) +#else +# define machine_is_davinci_perseo_hd() (0) +#endif + +#ifdef CONFIG_MACH_STARGAZER2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STARGAZER2 +# endif +# define machine_is_stargazer2() (machine_arch_type == MACH_TYPE_STARGAZER2) +#else +# define machine_is_stargazer2() (0) +#endif + +#ifdef CONFIG_MACH_E350 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E350 +# endif +# define machine_is_e350() (machine_arch_type == MACH_TYPE_E350) +#else +# define machine_is_e350() (0) +#endif + +#ifdef CONFIG_MACH_WPCM450 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WPCM450 +# endif +# define machine_is_wpcm450() (machine_arch_type == MACH_TYPE_WPCM450) +#else +# define machine_is_wpcm450() (0) +#endif + +#ifdef CONFIG_MACH_CARTESIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARTESIO +# endif +# define machine_is_cartesio() (machine_arch_type == MACH_TYPE_CARTESIO) +#else +# define machine_is_cartesio() (0) +#endif + +#ifdef CONFIG_MACH_TOYBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOYBOX +# endif +# define machine_is_toybox() (machine_arch_type == MACH_TYPE_TOYBOX) +#else +# define machine_is_toybox() (0) +#endif + +#ifdef CONFIG_MACH_TX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX27 +# endif +# define machine_is_tx27() (machine_arch_type == MACH_TYPE_TX27) +#else +# define machine_is_tx27() (0) +#endif + +#ifdef CONFIG_MACH_TS409 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS409 +# endif +# define machine_is_ts409() (machine_arch_type == MACH_TYPE_TS409) +#else +# define machine_is_ts409() (0) +#endif + +#ifdef CONFIG_MACH_P300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P300 +# endif +# define machine_is_p300() (machine_arch_type == MACH_TYPE_P300) +#else +# define machine_is_p300() (0) +#endif + +#ifdef CONFIG_MACH_XDACOMET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XDACOMET +# endif +# define machine_is_xdacomet() (machine_arch_type == MACH_TYPE_XDACOMET) +#else +# define machine_is_xdacomet() (0) +#endif + +#ifdef CONFIG_MACH_DEXFLEX2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEXFLEX2 +# endif +# define machine_is_dexflex2() (machine_arch_type == MACH_TYPE_DEXFLEX2) +#else +# define machine_is_dexflex2() (0) +#endif + +#ifdef CONFIG_MACH_OW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OW +# endif +# define machine_is_ow() (machine_arch_type == MACH_TYPE_OW) +#else +# define machine_is_ow() (0) +#endif + +#ifdef CONFIG_MACH_ARMEBS3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMEBS3 +# endif +# define machine_is_armebs3() (machine_arch_type == MACH_TYPE_ARMEBS3) +#else +# define machine_is_armebs3() (0) +#endif + +#ifdef CONFIG_MACH_U3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U3 +# endif +# define machine_is_u3() (machine_arch_type == MACH_TYPE_U3) +#else +# define machine_is_u3() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2450 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2450 +# endif +# define machine_is_smdk2450() (machine_arch_type == MACH_TYPE_SMDK2450) +#else +# define machine_is_smdk2450() (0) +#endif + +#ifdef CONFIG_MACH_RSI_EWS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSI_EWS +# endif +# define machine_is_rsi_ews() (machine_arch_type == MACH_TYPE_RSI_EWS) +#else +# define machine_is_rsi_ews() (0) +#endif + +#ifdef CONFIG_MACH_TNB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNB +# endif +# define machine_is_tnb() (machine_arch_type == MACH_TYPE_TNB) +#else +# define machine_is_tnb() (0) +#endif + +#ifdef CONFIG_MACH_TOEPATH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOEPATH +# endif +# define machine_is_toepath() (machine_arch_type == MACH_TYPE_TOEPATH) +#else +# define machine_is_toepath() (0) +#endif + +#ifdef CONFIG_MACH_KB9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KB9263 +# endif +# define machine_is_kb9263() (machine_arch_type == MACH_TYPE_KB9263) +#else +# define machine_is_kb9263() (0) +#endif + +#ifdef CONFIG_MACH_MT7108 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT7108 +# endif +# define machine_is_mt7108() (machine_arch_type == MACH_TYPE_MT7108) +#else +# define machine_is_mt7108() (0) +#endif + +#ifdef CONFIG_MACH_SMTR2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMTR2440 +# endif +# define machine_is_smtr2440() (machine_arch_type == MACH_TYPE_SMTR2440) +#else +# define machine_is_smtr2440() (0) +#endif + +#ifdef CONFIG_MACH_MANAO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MANAO +# endif +# define machine_is_manao() (machine_arch_type == MACH_TYPE_MANAO) +#else +# define machine_is_manao() (0) +#endif + +#ifdef CONFIG_MACH_CM_X300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_X300 +# endif +# define machine_is_cm_x300() (machine_arch_type == MACH_TYPE_CM_X300) +#else +# define machine_is_cm_x300() (0) +#endif + +#ifdef CONFIG_MACH_GULFSTREAM_KP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GULFSTREAM_KP +# endif +# define machine_is_gulfstream_kp() (machine_arch_type == MACH_TYPE_GULFSTREAM_KP) +#else +# define machine_is_gulfstream_kp() (0) +#endif + +#ifdef CONFIG_MACH_LANREADYFN522 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LANREADYFN522 +# endif +# define machine_is_lanreadyfn522() (machine_arch_type == MACH_TYPE_LANREADYFN522) +#else +# define machine_is_lanreadyfn522() (0) +#endif + +#ifdef CONFIG_MACH_ARMA37 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMA37 +# endif +# define machine_is_arma37() (machine_arch_type == MACH_TYPE_ARMA37) +#else +# define machine_is_arma37() (0) +#endif + +#ifdef CONFIG_MACH_MENDEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MENDEL +# endif +# define machine_is_mendel() (machine_arch_type == MACH_TYPE_MENDEL) +#else +# define machine_is_mendel() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_ILIAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_ILIAD +# endif +# define machine_is_pelco_iliad() (machine_arch_type == MACH_TYPE_PELCO_ILIAD) +#else +# define machine_is_pelco_iliad() (0) +#endif + +#ifdef CONFIG_MACH_UNIT2P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIT2P +# endif +# define machine_is_unit2p() (machine_arch_type == MACH_TYPE_UNIT2P) +#else +# define machine_is_unit2p() (0) +#endif + +#ifdef CONFIG_MACH_INC20OTTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INC20OTTER +# endif +# define machine_is_inc20otter() (machine_arch_type == MACH_TYPE_INC20OTTER) +#else +# define machine_is_inc20otter() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20EK +# endif +# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK) +#else +# define machine_is_at91sam9g20ek() (0) +#endif + +#ifdef CONFIG_MACH_STORCENTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STORCENTER +# endif +# define machine_is_sc_ge2() (machine_arch_type == MACH_TYPE_STORCENTER) +#else +# define machine_is_sc_ge2() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6410 +# endif +# define machine_is_smdk6410() (machine_arch_type == MACH_TYPE_SMDK6410) +#else +# define machine_is_smdk6410() (0) +#endif + +#ifdef CONFIG_MACH_U300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U300 +# endif +# define machine_is_u300() (machine_arch_type == MACH_TYPE_U300) +#else +# define machine_is_u300() (0) +#endif + +#ifdef CONFIG_MACH_U500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U500 +# endif +# define machine_is_u500() (machine_arch_type == MACH_TYPE_U500) +#else +# define machine_is_u500() (0) +#endif + +#ifdef CONFIG_MACH_DS9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS9260 +# endif +# define machine_is_ds9260() (machine_arch_type == MACH_TYPE_DS9260) +#else +# define machine_is_ds9260() (0) +#endif + +#ifdef CONFIG_MACH_RIVERROCK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIVERROCK +# endif +# define machine_is_riverrock() (machine_arch_type == MACH_TYPE_RIVERROCK) +#else +# define machine_is_riverrock() (0) +#endif + +#ifdef CONFIG_MACH_SCIBATH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCIBATH +# endif +# define machine_is_scibath() (machine_arch_type == MACH_TYPE_SCIBATH) +#else +# define machine_is_scibath() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM7SE512EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM7SE512EK +# endif +# define machine_is_at91sam7se() (machine_arch_type == MACH_TYPE_AT91SAM7SE512EK) +#else +# define machine_is_at91sam7se() (0) +#endif + +#ifdef CONFIG_MACH_WRT350N_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WRT350N_V2 +# endif +# define machine_is_wrt350n_v2() (machine_arch_type == MACH_TYPE_WRT350N_V2) +#else +# define machine_is_wrt350n_v2() (0) +#endif + +#ifdef CONFIG_MACH_MULTIMEDIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIMEDIA +# endif +# define machine_is_multimedia() (machine_arch_type == MACH_TYPE_MULTIMEDIA) +#else +# define machine_is_multimedia() (0) +#endif + +#ifdef CONFIG_MACH_MARVIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVIN +# endif +# define machine_is_marvin() (machine_arch_type == MACH_TYPE_MARVIN) +#else +# define machine_is_marvin() (0) +#endif + +#ifdef CONFIG_MACH_X500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_X500 +# endif +# define machine_is_x500() (machine_arch_type == MACH_TYPE_X500) +#else +# define machine_is_x500() (0) +#endif + +#ifdef CONFIG_MACH_AWLUG4LCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AWLUG4LCU +# endif +# define machine_is_awlug4lcu() (machine_arch_type == MACH_TYPE_AWLUG4LCU) +#else +# define machine_is_awlug4lcu() (0) +#endif + +#ifdef CONFIG_MACH_PALERMOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALERMOC +# endif +# define machine_is_palermoc() (machine_arch_type == MACH_TYPE_PALERMOC) +#else +# define machine_is_palermoc() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_LDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_LDP +# endif +# define machine_is_omap_ldp() (machine_arch_type == MACH_TYPE_OMAP_LDP) +#else +# define machine_is_omap_ldp() (0) +#endif + +#ifdef CONFIG_MACH_IP500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP500 +# endif +# define machine_is_ip500() (machine_arch_type == MACH_TYPE_IP500) +#else +# define machine_is_ip500() (0) +#endif + +#ifdef CONFIG_MACH_ASE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASE2 +# endif +# define machine_is_ase2() (machine_arch_type == MACH_TYPE_ASE2) +#else +# define machine_is_ase2() (0) +#endif + +#ifdef CONFIG_MACH_MX35EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35EVB +# endif +# define machine_is_mx35evb() (machine_arch_type == MACH_TYPE_MX35EVB) +#else +# define machine_is_mx35evb() (0) +#endif + +#ifdef CONFIG_MACH_AML_M8050 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AML_M8050 +# endif +# define machine_is_aml_m8050() (machine_arch_type == MACH_TYPE_AML_M8050) +#else +# define machine_is_aml_m8050() (0) +#endif + +#ifdef CONFIG_MACH_MX35_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35_3DS +# endif +# define machine_is_mx35_3ds() (machine_arch_type == MACH_TYPE_MX35_3DS) +#else +# define machine_is_mx35_3ds() (0) +#endif + +#ifdef CONFIG_MACH_MARS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARS +# endif +# define machine_is_mars() (machine_arch_type == MACH_TYPE_MARS) +#else +# define machine_is_mars() (0) +#endif + +#ifdef CONFIG_MACH_NEUROS_OSD2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEUROS_OSD2 +# endif +# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2) +#else +# define machine_is_neuros_osd2() (0) +#endif + +#ifdef CONFIG_MACH_BADGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BADGER +# endif +# define machine_is_badger() (machine_arch_type == MACH_TYPE_BADGER) +#else +# define machine_is_badger() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS4WL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS4WL +# endif +# define machine_is_trizeps4wl() (machine_arch_type == MACH_TYPE_TRIZEPS4WL) +#else +# define machine_is_trizeps4wl() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS5 +# endif +# define machine_is_trizeps5() (machine_arch_type == MACH_TYPE_TRIZEPS5) +#else +# define machine_is_trizeps5() (0) +#endif + +#ifdef CONFIG_MACH_MARLIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARLIN +# endif +# define machine_is_marlin() (machine_arch_type == MACH_TYPE_MARLIN) +#else +# define machine_is_marlin() (0) +#endif + +#ifdef CONFIG_MACH_TS78XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS78XX +# endif +# define machine_is_ts78xx() (machine_arch_type == MACH_TYPE_TS78XX) +#else +# define machine_is_ts78xx() (0) +#endif + +#ifdef CONFIG_MACH_HPIPAQ214 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPIPAQ214 +# endif +# define machine_is_hpipaq214() (machine_arch_type == MACH_TYPE_HPIPAQ214) +#else +# define machine_is_hpipaq214() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940DCM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940DCM +# endif +# define machine_is_at572d940dcm() (machine_arch_type == MACH_TYPE_AT572D940DCM) +#else +# define machine_is_at572d940dcm() (0) +#endif + +#ifdef CONFIG_MACH_NE1BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NE1BOARD +# endif +# define machine_is_ne1board() (machine_arch_type == MACH_TYPE_NE1BOARD) +#else +# define machine_is_ne1board() (0) +#endif + +#ifdef CONFIG_MACH_ZANTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZANTE +# endif +# define machine_is_zante() (machine_arch_type == MACH_TYPE_ZANTE) +#else +# define machine_is_zante() (0) +#endif + +#ifdef CONFIG_MACH_SFFSDR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SFFSDR +# endif +# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) +#else +# define machine_is_sffsdr() (0) +#endif + +#ifdef CONFIG_MACH_TW2662 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TW2662 +# endif +# define machine_is_tw2662() (machine_arch_type == MACH_TYPE_TW2662) +#else +# define machine_is_tw2662() (0) +#endif + +#ifdef CONFIG_MACH_VF10XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VF10XX +# endif +# define machine_is_vf10xx() (machine_arch_type == MACH_TYPE_VF10XX) +#else +# define machine_is_vf10xx() (0) +#endif + +#ifdef CONFIG_MACH_ZORAN43XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZORAN43XX +# endif +# define machine_is_zoran43xx() (machine_arch_type == MACH_TYPE_ZORAN43XX) +#else +# define machine_is_zoran43xx() (0) +#endif + +#ifdef CONFIG_MACH_SONIX926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONIX926 +# endif +# define machine_is_sonix926() (machine_arch_type == MACH_TYPE_SONIX926) +#else +# define machine_is_sonix926() (0) +#endif + +#ifdef CONFIG_MACH_CELESTIALSEMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CELESTIALSEMI +# endif +# define machine_is_celestialsemi() (machine_arch_type == MACH_TYPE_CELESTIALSEMI) +#else +# define machine_is_celestialsemi() (0) +#endif + +#ifdef CONFIG_MACH_CC9M2443JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9M2443JS +# endif +# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) +#else +# define machine_is_cc9m2443js() (0) +#endif + +#ifdef CONFIG_MACH_TW5334 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TW5334 +# endif +# define machine_is_tw5334() (machine_arch_type == MACH_TYPE_TW5334) +#else +# define machine_is_tw5334() (0) +#endif + +#ifdef CONFIG_MACH_HTCARTEMIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCARTEMIS +# endif +# define machine_is_omap_htcartemis() (machine_arch_type == MACH_TYPE_HTCARTEMIS) +#else +# define machine_is_omap_htcartemis() (0) +#endif + +#ifdef CONFIG_MACH_NAL_HLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAL_HLITE +# endif +# define machine_is_nal_hlite() (machine_arch_type == MACH_TYPE_NAL_HLITE) +#else +# define machine_is_nal_hlite() (0) +#endif + +#ifdef CONFIG_MACH_HTCVOGUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCVOGUE +# endif +# define machine_is_htcvogue() (machine_arch_type == MACH_TYPE_HTCVOGUE) +#else +# define machine_is_htcvogue() (0) +#endif + +#ifdef CONFIG_MACH_SMARTWEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTWEB +# endif +# define machine_is_smartweb() (machine_arch_type == MACH_TYPE_SMARTWEB) +#else +# define machine_is_smartweb() (0) +#endif + +#ifdef CONFIG_MACH_MV86XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV86XX +# endif +# define machine_is_mv86xx() (machine_arch_type == MACH_TYPE_MV86XX) +#else +# define machine_is_mv86xx() (0) +#endif + +#ifdef CONFIG_MACH_MV87XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV87XX +# endif +# define machine_is_mv87xx() (machine_arch_type == MACH_TYPE_MV87XX) +#else +# define machine_is_mv87xx() (0) +#endif + +#ifdef CONFIG_MACH_SONGYOUNGHO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONGYOUNGHO +# endif +# define machine_is_songyoungho() (machine_arch_type == MACH_TYPE_SONGYOUNGHO) +#else +# define machine_is_songyoungho() (0) +#endif + +#ifdef CONFIG_MACH_YOUNGHOTEMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YOUNGHOTEMA +# endif +# define machine_is_younghotema() (machine_arch_type == MACH_TYPE_YOUNGHOTEMA) +#else +# define machine_is_younghotema() (0) +#endif + +#ifdef CONFIG_MACH_PCM037 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM037 +# endif +# define machine_is_pcm037() (machine_arch_type == MACH_TYPE_PCM037) +#else +# define machine_is_pcm037() (0) +#endif + +#ifdef CONFIG_MACH_MMVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMVP +# endif +# define machine_is_mmvp() (machine_arch_type == MACH_TYPE_MMVP) +#else +# define machine_is_mmvp() (0) +#endif + +#ifdef CONFIG_MACH_MMAP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMAP +# endif +# define machine_is_mmap() (machine_arch_type == MACH_TYPE_MMAP) +#else +# define machine_is_mmap() (0) +#endif + +#ifdef CONFIG_MACH_PTID2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTID2410 +# endif +# define machine_is_ptid2410() (machine_arch_type == MACH_TYPE_PTID2410) +#else +# define machine_is_ptid2410() (0) +#endif + +#ifdef CONFIG_MACH_JAMES_926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JAMES_926 +# endif +# define machine_is_james_926() (machine_arch_type == MACH_TYPE_JAMES_926) +#else +# define machine_is_james_926() (0) +#endif + +#ifdef CONFIG_MACH_FM6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FM6000 +# endif +# define machine_is_fm6000() (machine_arch_type == MACH_TYPE_FM6000) +#else +# define machine_is_fm6000() (0) +#endif + +#ifdef CONFIG_MACH_DB88F6281_BP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DB88F6281_BP +# endif +# define machine_is_db88f6281_bp() (machine_arch_type == MACH_TYPE_DB88F6281_BP) +#else +# define machine_is_db88f6281_bp() (0) +#endif + +#ifdef CONFIG_MACH_RD88F6192_NAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F6192_NAS +# endif +# define machine_is_rd88f6192_nas() (machine_arch_type == MACH_TYPE_RD88F6192_NAS) +#else +# define machine_is_rd88f6192_nas() (0) +#endif + +#ifdef CONFIG_MACH_RD88F6281 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F6281 +# endif +# define machine_is_rd88f6281() (machine_arch_type == MACH_TYPE_RD88F6281) +#else +# define machine_is_rd88f6281() (0) +#endif + +#ifdef CONFIG_MACH_DB78X00_BP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DB78X00_BP +# endif +# define machine_is_db78x00_bp() (machine_arch_type == MACH_TYPE_DB78X00_BP) +#else +# define machine_is_db78x00_bp() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2416 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2416 +# endif +# define machine_is_smdk2416() (machine_arch_type == MACH_TYPE_SMDK2416) +#else +# define machine_is_smdk2416() (0) +#endif + +#ifdef CONFIG_MACH_OCE_SPIDER_SI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCE_SPIDER_SI +# endif +# define machine_is_oce_spider_si() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SI) +#else +# define machine_is_oce_spider_si() (0) +#endif + +#ifdef CONFIG_MACH_OCE_SPIDER_SK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCE_SPIDER_SK +# endif +# define machine_is_oce_spider_sk() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SK) +#else +# define machine_is_oce_spider_sk() (0) +#endif + +#ifdef CONFIG_MACH_ROVERN6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERN6 +# endif +# define machine_is_rovern6() (machine_arch_type == MACH_TYPE_ROVERN6) +#else +# define machine_is_rovern6() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_EVOLUTION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_EVOLUTION +# endif +# define machine_is_pelco_evolution() (machine_arch_type == MACH_TYPE_PELCO_EVOLUTION) +#else +# define machine_is_pelco_evolution() (0) +#endif + +#ifdef CONFIG_MACH_WBD111 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WBD111 +# endif +# define machine_is_wbd111() (machine_arch_type == MACH_TYPE_WBD111) +#else +# define machine_is_wbd111() (0) +#endif + +#ifdef CONFIG_MACH_ELARACPE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELARACPE +# endif +# define machine_is_elaracpe() (machine_arch_type == MACH_TYPE_ELARACPE) +#else +# define machine_is_elaracpe() (0) +#endif + +#ifdef CONFIG_MACH_MABV3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MABV3 +# endif +# define machine_is_mabv3() (machine_arch_type == MACH_TYPE_MABV3) +#else +# define machine_is_mabv3() (0) +#endif + +#ifdef CONFIG_MACH_MV2120 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV2120 +# endif +# define machine_is_mv2120() (machine_arch_type == MACH_TYPE_MV2120) +#else +# define machine_is_mv2120() (0) +#endif + +#ifdef CONFIG_MACH_CSB737 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB737 +# endif +# define machine_is_csb737() (machine_arch_type == MACH_TYPE_CSB737) +#else +# define machine_is_csb737() (0) +#endif + +#ifdef CONFIG_MACH_MX51_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_3DS +# endif +# define machine_is_mx51_3ds() (machine_arch_type == MACH_TYPE_MX51_3DS) +#else +# define machine_is_mx51_3ds() (0) +#endif + +#ifdef CONFIG_MACH_G900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G900 +# endif +# define machine_is_g900() (machine_arch_type == MACH_TYPE_G900) +#else +# define machine_is_g900() (0) +#endif + +#ifdef CONFIG_MACH_APF27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APF27 +# endif +# define machine_is_apf27() (machine_arch_type == MACH_TYPE_APF27) +#else +# define machine_is_apf27() (0) +#endif + +#ifdef CONFIG_MACH_GGUS2000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GGUS2000 +# endif +# define machine_is_ggus2000() (machine_arch_type == MACH_TYPE_GGUS2000) +#else +# define machine_is_ggus2000() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_2430_MIMIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_2430_MIMIC +# endif +# define machine_is_omap_2430_mimic() (machine_arch_type == MACH_TYPE_OMAP_2430_MIMIC) +#else +# define machine_is_omap_2430_mimic() (0) +#endif + +#ifdef CONFIG_MACH_IMX27LITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27LITE +# endif +# define machine_is_imx27lite() (machine_arch_type == MACH_TYPE_IMX27LITE) +#else +# define machine_is_imx27lite() (0) +#endif + +#ifdef CONFIG_MACH_ALMEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALMEX +# endif +# define machine_is_almex() (machine_arch_type == MACH_TYPE_ALMEX) +#else +# define machine_is_almex() (0) +#endif + +#ifdef CONFIG_MACH_CONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CONTROL +# endif +# define machine_is_control() (machine_arch_type == MACH_TYPE_CONTROL) +#else +# define machine_is_control() (0) +#endif + +#ifdef CONFIG_MACH_MBA2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MBA2410 +# endif +# define machine_is_mba2410() (machine_arch_type == MACH_TYPE_MBA2410) +#else +# define machine_is_mba2410() (0) +#endif + +#ifdef CONFIG_MACH_VOLCANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOLCANO +# endif +# define machine_is_volcano() (machine_arch_type == MACH_TYPE_VOLCANO) +#else +# define machine_is_volcano() (0) +#endif + +#ifdef CONFIG_MACH_ZENITH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZENITH +# endif +# define machine_is_zenith() (machine_arch_type == MACH_TYPE_ZENITH) +#else +# define machine_is_zenith() (0) +#endif + +#ifdef CONFIG_MACH_MUCHIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MUCHIP +# endif +# define machine_is_muchip() (machine_arch_type == MACH_TYPE_MUCHIP) +#else +# define machine_is_muchip() (0) +#endif + +#ifdef CONFIG_MACH_MAGELLAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGELLAN +# endif +# define machine_is_magellan() (machine_arch_type == MACH_TYPE_MAGELLAN) +#else +# define machine_is_magellan() (0) +#endif + +#ifdef CONFIG_MACH_USB_A9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_A9260 +# endif +# define machine_is_usb_a9260() (machine_arch_type == MACH_TYPE_USB_A9260) +#else +# define machine_is_usb_a9260() (0) +#endif + +#ifdef CONFIG_MACH_USB_A9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_A9263 +# endif +# define machine_is_usb_a9263() (machine_arch_type == MACH_TYPE_USB_A9263) +#else +# define machine_is_usb_a9263() (0) +#endif + +#ifdef CONFIG_MACH_QIL_A9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QIL_A9260 +# endif +# define machine_is_qil_a9260() (machine_arch_type == MACH_TYPE_QIL_A9260) +#else +# define machine_is_qil_a9260() (0) +#endif + +#ifdef CONFIG_MACH_CME9210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CME9210 +# endif +# define machine_is_cme9210() (machine_arch_type == MACH_TYPE_CME9210) +#else +# define machine_is_cme9210() (0) +#endif + +#ifdef CONFIG_MACH_HCZH4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HCZH4 +# endif +# define machine_is_hczh4() (machine_arch_type == MACH_TYPE_HCZH4) +#else +# define machine_is_hczh4() (0) +#endif + +#ifdef CONFIG_MACH_SPEARBASIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEARBASIC +# endif +# define machine_is_spearbasic() (machine_arch_type == MACH_TYPE_SPEARBASIC) +#else +# define machine_is_spearbasic() (0) +#endif + +#ifdef CONFIG_MACH_DEP2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEP2440 +# endif +# define machine_is_dep2440() (machine_arch_type == MACH_TYPE_DEP2440) +#else +# define machine_is_dep2440() (0) +#endif + +#ifdef CONFIG_MACH_HDL_GXR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDL_GXR +# endif +# define machine_is_hdl_gxr() (machine_arch_type == MACH_TYPE_HDL_GXR) +#else +# define machine_is_hdl_gxr() (0) +#endif + +#ifdef CONFIG_MACH_HDL_GT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDL_GT +# endif +# define machine_is_hdl_gt() (machine_arch_type == MACH_TYPE_HDL_GT) +#else +# define machine_is_hdl_gt() (0) +#endif + +#ifdef CONFIG_MACH_HDL_4G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDL_4G +# endif +# define machine_is_hdl_4g() (machine_arch_type == MACH_TYPE_HDL_4G) +#else +# define machine_is_hdl_4g() (0) +#endif + +#ifdef CONFIG_MACH_S3C6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C6000 +# endif +# define machine_is_s3c6000() (machine_arch_type == MACH_TYPE_S3C6000) +#else +# define machine_is_s3c6000() (0) +#endif + +#ifdef CONFIG_MACH_MMSP2_MDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMSP2_MDK +# endif +# define machine_is_mmsp2_mdk() (machine_arch_type == MACH_TYPE_MMSP2_MDK) +#else +# define machine_is_mmsp2_mdk() (0) +#endif + +#ifdef CONFIG_MACH_MPX220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPX220 +# endif +# define machine_is_mpx220() (machine_arch_type == MACH_TYPE_MPX220) +#else +# define machine_is_mpx220() (0) +#endif + +#ifdef CONFIG_MACH_KZM_ARM11_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KZM_ARM11_01 +# endif +# define machine_is_kzm_arm11_01() (machine_arch_type == MACH_TYPE_KZM_ARM11_01) +#else +# define machine_is_kzm_arm11_01() (0) +#endif + +#ifdef CONFIG_MACH_HTC_POLARIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_POLARIS +# endif +# define machine_is_htc_polaris() (machine_arch_type == MACH_TYPE_HTC_POLARIS) +#else +# define machine_is_htc_polaris() (0) +#endif + +#ifdef CONFIG_MACH_HTC_KAISER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_KAISER +# endif +# define machine_is_htc_kaiser() (machine_arch_type == MACH_TYPE_HTC_KAISER) +#else +# define machine_is_htc_kaiser() (0) +#endif + +#ifdef CONFIG_MACH_LG_KS20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LG_KS20 +# endif +# define machine_is_lg_ks20() (machine_arch_type == MACH_TYPE_LG_KS20) +#else +# define machine_is_lg_ks20() (0) +#endif + +#ifdef CONFIG_MACH_HHGPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HHGPS +# endif +# define machine_is_hhgps() (machine_arch_type == MACH_TYPE_HHGPS) +#else +# define machine_is_hhgps() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA_N810_WIMAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA_N810_WIMAX +# endif +# define machine_is_nokia_n810_wimax() (machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX) +#else +# define machine_is_nokia_n810_wimax() (0) +#endif + +#ifdef CONFIG_MACH_INSIGHT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INSIGHT +# endif +# define machine_is_insight() (machine_arch_type == MACH_TYPE_INSIGHT) +#else +# define machine_is_insight() (0) +#endif + +#ifdef CONFIG_MACH_SAPPHIRE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAPPHIRE +# endif +# define machine_is_sapphire() (machine_arch_type == MACH_TYPE_SAPPHIRE) +#else +# define machine_is_sapphire() (0) +#endif + +#ifdef CONFIG_MACH_CSB637XO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB637XO +# endif +# define machine_is_csb637xo() (machine_arch_type == MACH_TYPE_CSB637XO) +#else +# define machine_is_csb637xo() (0) +#endif + +#ifdef CONFIG_MACH_EVISIONG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EVISIONG +# endif +# define machine_is_evisiong() (machine_arch_type == MACH_TYPE_EVISIONG) +#else +# define machine_is_evisiong() (0) +#endif + +#ifdef CONFIG_MACH_STMP37XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STMP37XX +# endif +# define machine_is_stmp37xx() (machine_arch_type == MACH_TYPE_STMP37XX) +#else +# define machine_is_stmp37xx() (0) +#endif + +#ifdef CONFIG_MACH_STMP378X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STMP378X +# endif +# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP378X) +#else +# define machine_is_stmp378x() (0) +#endif + +#ifdef CONFIG_MACH_TNT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNT +# endif +# define machine_is_tnt() (machine_arch_type == MACH_TYPE_TNT) +#else +# define machine_is_tnt() (0) +#endif + +#ifdef CONFIG_MACH_TBXT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TBXT +# endif +# define machine_is_tbxt() (machine_arch_type == MACH_TYPE_TBXT) +#else +# define machine_is_tbxt() (0) +#endif + +#ifdef CONFIG_MACH_PLAYMATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLAYMATE +# endif +# define machine_is_playmate() (machine_arch_type == MACH_TYPE_PLAYMATE) +#else +# define machine_is_playmate() (0) +#endif + +#ifdef CONFIG_MACH_PNS10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNS10 +# endif +# define machine_is_pns10() (machine_arch_type == MACH_TYPE_PNS10) +#else +# define machine_is_pns10() (0) +#endif + +#ifdef CONFIG_MACH_EZNAVI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZNAVI +# endif +# define machine_is_eznavi() (machine_arch_type == MACH_TYPE_EZNAVI) +#else +# define machine_is_eznavi() (0) +#endif + +#ifdef CONFIG_MACH_PS4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PS4000 +# endif +# define machine_is_ps4000() (machine_arch_type == MACH_TYPE_PS4000) +#else +# define machine_is_ps4000() (0) +#endif + +#ifdef CONFIG_MACH_EZX_A780 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_A780 +# endif +# define machine_is_ezx_a780() (machine_arch_type == MACH_TYPE_EZX_A780) +#else +# define machine_is_ezx_a780() (0) +#endif + +#ifdef CONFIG_MACH_EZX_E680 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_E680 +# endif +# define machine_is_ezx_e680() (machine_arch_type == MACH_TYPE_EZX_E680) +#else +# define machine_is_ezx_e680() (0) +#endif + +#ifdef CONFIG_MACH_EZX_A1200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_A1200 +# endif +# define machine_is_ezx_a1200() (machine_arch_type == MACH_TYPE_EZX_A1200) +#else +# define machine_is_ezx_a1200() (0) +#endif + +#ifdef CONFIG_MACH_EZX_E6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_E6 +# endif +# define machine_is_ezx_e6() (machine_arch_type == MACH_TYPE_EZX_E6) +#else +# define machine_is_ezx_e6() (0) +#endif + +#ifdef CONFIG_MACH_EZX_E2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_E2 +# endif +# define machine_is_ezx_e2() (machine_arch_type == MACH_TYPE_EZX_E2) +#else +# define machine_is_ezx_e2() (0) +#endif + +#ifdef CONFIG_MACH_EZX_A910 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_A910 +# endif +# define machine_is_ezx_a910() (machine_arch_type == MACH_TYPE_EZX_A910) +#else +# define machine_is_ezx_a910() (0) +#endif + +#ifdef CONFIG_MACH_CWMX31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWMX31 +# endif +# define machine_is_cwmx31() (machine_arch_type == MACH_TYPE_CWMX31) +#else +# define machine_is_cwmx31() (0) +#endif + +#ifdef CONFIG_MACH_SL2312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SL2312 +# endif +# define machine_is_sl2312() (machine_arch_type == MACH_TYPE_SL2312) +#else +# define machine_is_sl2312() (0) +#endif + +#ifdef CONFIG_MACH_BLENNY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLENNY +# endif +# define machine_is_blenny() (machine_arch_type == MACH_TYPE_BLENNY) +#else +# define machine_is_blenny() (0) +#endif + +#ifdef CONFIG_MACH_DS107 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS107 +# endif +# define machine_is_ds107() (machine_arch_type == MACH_TYPE_DS107) +#else +# define machine_is_ds107() (0) +#endif + +#ifdef CONFIG_MACH_DSX07 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSX07 +# endif +# define machine_is_dsx07() (machine_arch_type == MACH_TYPE_DSX07) +#else +# define machine_is_dsx07() (0) +#endif + +#ifdef CONFIG_MACH_PICOCOM1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOCOM1 +# endif +# define machine_is_picocom1() (machine_arch_type == MACH_TYPE_PICOCOM1) +#else +# define machine_is_picocom1() (0) +#endif + +#ifdef CONFIG_MACH_LYNX_WOLVERINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LYNX_WOLVERINE +# endif +# define machine_is_lynx_wolverine() (machine_arch_type == MACH_TYPE_LYNX_WOLVERINE) +#else +# define machine_is_lynx_wolverine() (0) +#endif + +#ifdef CONFIG_MACH_UBISYS_P9_SC19 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UBISYS_P9_SC19 +# endif +# define machine_is_ubisys_p9_sc19() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC19) +#else +# define machine_is_ubisys_p9_sc19() (0) +#endif + +#ifdef CONFIG_MACH_KRATOS_LOW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRATOS_LOW +# endif +# define machine_is_kratos_low() (machine_arch_type == MACH_TYPE_KRATOS_LOW) +#else +# define machine_is_kratos_low() (0) +#endif + +#ifdef CONFIG_MACH_M700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M700 +# endif +# define machine_is_m700() (machine_arch_type == MACH_TYPE_M700) +#else +# define machine_is_m700() (0) +#endif + +#ifdef CONFIG_MACH_EDMINI_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDMINI_V2 +# endif +# define machine_is_edmini_v2() (machine_arch_type == MACH_TYPE_EDMINI_V2) +#else +# define machine_is_edmini_v2() (0) +#endif + +#ifdef CONFIG_MACH_ZIPIT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZIPIT2 +# endif +# define machine_is_zipit2() (machine_arch_type == MACH_TYPE_ZIPIT2) +#else +# define machine_is_zipit2() (0) +#endif + +#ifdef CONFIG_MACH_HSLFEMTOCELL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HSLFEMTOCELL +# endif +# define machine_is_hslfemtocell() (machine_arch_type == MACH_TYPE_HSLFEMTOCELL) +#else +# define machine_is_hslfemtocell() (0) +#endif + +#ifdef CONFIG_MACH_DAINTREE_AT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAINTREE_AT91 +# endif +# define machine_is_daintree_at91() (machine_arch_type == MACH_TYPE_DAINTREE_AT91) +#else +# define machine_is_daintree_at91() (0) +#endif + +#ifdef CONFIG_MACH_SG560USB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG560USB +# endif +# define machine_is_sg560usb() (machine_arch_type == MACH_TYPE_SG560USB) +#else +# define machine_is_sg560usb() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PANDORA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PANDORA +# endif +# define machine_is_omap3_pandora() (machine_arch_type == MACH_TYPE_OMAP3_PANDORA) +#else +# define machine_is_omap3_pandora() (0) +#endif + +#ifdef CONFIG_MACH_USR8200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USR8200 +# endif +# define machine_is_usr8200() (machine_arch_type == MACH_TYPE_USR8200) +#else +# define machine_is_usr8200() (0) +#endif + +#ifdef CONFIG_MACH_S1S65K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S1S65K +# endif +# define machine_is_s1s65k() (machine_arch_type == MACH_TYPE_S1S65K) +#else +# define machine_is_s1s65k() (0) +#endif + +#ifdef CONFIG_MACH_S2S65A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S2S65A +# endif +# define machine_is_s2s65a() (machine_arch_type == MACH_TYPE_S2S65A) +#else +# define machine_is_s2s65a() (0) +#endif + +#ifdef CONFIG_MACH_ICORE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICORE +# endif +# define machine_is_icore() (machine_arch_type == MACH_TYPE_ICORE) +#else +# define machine_is_icore() (0) +#endif + +#ifdef CONFIG_MACH_MSS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSS2 +# endif +# define machine_is_mss2() (machine_arch_type == MACH_TYPE_MSS2) +#else +# define machine_is_mss2() (0) +#endif + +#ifdef CONFIG_MACH_BELMONT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BELMONT +# endif +# define machine_is_belmont() (machine_arch_type == MACH_TYPE_BELMONT) +#else +# define machine_is_belmont() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP525 +# endif +# define machine_is_asusp525() (machine_arch_type == MACH_TYPE_ASUSP525) +#else +# define machine_is_asusp525() (0) +#endif + +#ifdef CONFIG_MACH_LB88RC8480 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LB88RC8480 +# endif +# define machine_is_lb88rc8480() (machine_arch_type == MACH_TYPE_LB88RC8480) +#else +# define machine_is_lb88rc8480() (0) +#endif + +#ifdef CONFIG_MACH_HIPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIPXA +# endif +# define machine_is_hipxa() (machine_arch_type == MACH_TYPE_HIPXA) +#else +# define machine_is_hipxa() (0) +#endif + +#ifdef CONFIG_MACH_MX25_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX25_3DS +# endif +# define machine_is_mx25_3ds() (machine_arch_type == MACH_TYPE_MX25_3DS) +#else +# define machine_is_mx25_3ds() (0) +#endif + +#ifdef CONFIG_MACH_M800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M800 +# endif +# define machine_is_m800() (machine_arch_type == MACH_TYPE_M800) +#else +# define machine_is_m800() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3530_LV_SOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3530_LV_SOM +# endif +# define machine_is_omap3530_lv_som() (machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM) +#else +# define machine_is_omap3530_lv_som() (0) +#endif + +#ifdef CONFIG_MACH_PRIMA_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRIMA_EVB +# endif +# define machine_is_prima_evb() (machine_arch_type == MACH_TYPE_PRIMA_EVB) +#else +# define machine_is_prima_evb() (0) +#endif + +#ifdef CONFIG_MACH_MX31BT1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31BT1 +# endif +# define machine_is_mx31bt1() (machine_arch_type == MACH_TYPE_MX31BT1) +#else +# define machine_is_mx31bt1() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS4_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS4_EVB +# endif +# define machine_is_atlas4_evb() (machine_arch_type == MACH_TYPE_ATLAS4_EVB) +#else +# define machine_is_atlas4_evb() (0) +#endif + +#ifdef CONFIG_MACH_MX31CICADA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31CICADA +# endif +# define machine_is_mx31cicada() (machine_arch_type == MACH_TYPE_MX31CICADA) +#else +# define machine_is_mx31cicada() (0) +#endif + +#ifdef CONFIG_MACH_MI424WR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MI424WR +# endif +# define machine_is_mi424wr() (machine_arch_type == MACH_TYPE_MI424WR) +#else +# define machine_is_mi424wr() (0) +#endif + +#ifdef CONFIG_MACH_AXS_ULTRAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXS_ULTRAX +# endif +# define machine_is_axs_ultrax() (machine_arch_type == MACH_TYPE_AXS_ULTRAX) +#else +# define machine_is_axs_ultrax() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940DEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940DEB +# endif +# define machine_is_at572d940deb() (machine_arch_type == MACH_TYPE_AT572D940DEB) +#else +# define machine_is_at572d940deb() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DA830_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM +# endif +# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) +#else +# define machine_is_davinci_da830_evm() (0) +#endif + +#ifdef CONFIG_MACH_EP9302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EP9302 +# endif +# define machine_is_ep9302() (machine_arch_type == MACH_TYPE_EP9302) +#else +# define machine_is_ep9302() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940HFEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940HFEB +# endif +# define machine_is_at572d940hfek() (machine_arch_type == MACH_TYPE_AT572D940HFEB) +#else +# define machine_is_at572d940hfek() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK3 +# endif +# define machine_is_cybook3() (machine_arch_type == MACH_TYPE_CYBOOK3) +#else +# define machine_is_cybook3() (0) +#endif + +#ifdef CONFIG_MACH_WDG002 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WDG002 +# endif +# define machine_is_wdg002() (machine_arch_type == MACH_TYPE_WDG002) +#else +# define machine_is_wdg002() (0) +#endif + +#ifdef CONFIG_MACH_SG560ADSL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG560ADSL +# endif +# define machine_is_sg560adsl() (machine_arch_type == MACH_TYPE_SG560ADSL) +#else +# define machine_is_sg560adsl() (0) +#endif + +#ifdef CONFIG_MACH_NEXTIO_N2800_ICA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXTIO_N2800_ICA +# endif +# define machine_is_nextio_n2800_ica() (machine_arch_type == MACH_TYPE_NEXTIO_N2800_ICA) +#else +# define machine_is_nextio_n2800_ica() (0) +#endif + +#ifdef CONFIG_MACH_DOVE_DB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_DB +# endif +# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB) +#else +# define machine_is_dove_db() (0) +#endif + +#ifdef CONFIG_MACH_MARVELL_NEWDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVELL_NEWDB +# endif +# define machine_is_marvell_newdb() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) +#else +# define machine_is_marvell_newdb() (0) +#endif + +#ifdef CONFIG_MACH_VANDIHUD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VANDIHUD +# endif +# define machine_is_vandihud() (machine_arch_type == MACH_TYPE_VANDIHUD) +#else +# define machine_is_vandihud() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_E8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_E8 +# endif +# define machine_is_magx_e8() (machine_arch_type == MACH_TYPE_MAGX_E8) +#else +# define machine_is_magx_e8() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_Z6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_Z6 +# endif +# define machine_is_magx_z6() (machine_arch_type == MACH_TYPE_MAGX_Z6) +#else +# define machine_is_magx_z6() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_V8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_V8 +# endif +# define machine_is_magx_v8() (machine_arch_type == MACH_TYPE_MAGX_V8) +#else +# define machine_is_magx_v8() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_U9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_U9 +# endif +# define machine_is_magx_u9() (machine_arch_type == MACH_TYPE_MAGX_U9) +#else +# define machine_is_magx_u9() (0) +#endif + +#ifdef CONFIG_MACH_TOUGHCF08 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOUGHCF08 +# endif +# define machine_is_toughcf08() (machine_arch_type == MACH_TYPE_TOUGHCF08) +#else +# define machine_is_toughcf08() (0) +#endif + +#ifdef CONFIG_MACH_ZW4400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZW4400 +# endif +# define machine_is_zw4400() (machine_arch_type == MACH_TYPE_ZW4400) +#else +# define machine_is_zw4400() (0) +#endif + +#ifdef CONFIG_MACH_MARAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARAT91 +# endif +# define machine_is_marat91() (machine_arch_type == MACH_TYPE_MARAT91) +#else +# define machine_is_marat91() (0) +#endif + +#ifdef CONFIG_MACH_OVERO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OVERO +# endif +# define machine_is_overo() (machine_arch_type == MACH_TYPE_OVERO) +#else +# define machine_is_overo() (0) +#endif + +#ifdef CONFIG_MACH_AT2440EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT2440EVB +# endif +# define machine_is_at2440evb() (machine_arch_type == MACH_TYPE_AT2440EVB) +#else +# define machine_is_at2440evb() (0) +#endif + +#ifdef CONFIG_MACH_NEOCORE926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEOCORE926 +# endif +# define machine_is_neocore926() (machine_arch_type == MACH_TYPE_NEOCORE926) +#else +# define machine_is_neocore926() (0) +#endif + +#ifdef CONFIG_MACH_WNR854T +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WNR854T +# endif +# define machine_is_wnr854t() (machine_arch_type == MACH_TYPE_WNR854T) +#else +# define machine_is_wnr854t() (0) +#endif + +#ifdef CONFIG_MACH_IMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27 +# endif +# define machine_is_imx27() (machine_arch_type == MACH_TYPE_IMX27) +#else +# define machine_is_imx27() (0) +#endif + +#ifdef CONFIG_MACH_MOOSE_DB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOOSE_DB +# endif +# define machine_is_moose_db() (machine_arch_type == MACH_TYPE_MOOSE_DB) +#else +# define machine_is_moose_db() (0) +#endif + +#ifdef CONFIG_MACH_FAB4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FAB4 +# endif +# define machine_is_fab4() (machine_arch_type == MACH_TYPE_FAB4) +#else +# define machine_is_fab4() (0) +#endif + +#ifdef CONFIG_MACH_HTCDIAMOND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCDIAMOND +# endif +# define machine_is_htcdiamond() (machine_arch_type == MACH_TYPE_HTCDIAMOND) +#else +# define machine_is_htcdiamond() (0) +#endif + +#ifdef CONFIG_MACH_FIONA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FIONA +# endif +# define machine_is_fiona() (machine_arch_type == MACH_TYPE_FIONA) +#else +# define machine_is_fiona() (0) +#endif + +#ifdef CONFIG_MACH_MXC30030_X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC30030_X +# endif +# define machine_is_mxc30030_x() (machine_arch_type == MACH_TYPE_MXC30030_X) +#else +# define machine_is_mxc30030_x() (0) +#endif + +#ifdef CONFIG_MACH_BMP1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BMP1000 +# endif +# define machine_is_bmp1000() (machine_arch_type == MACH_TYPE_BMP1000) +#else +# define machine_is_bmp1000() (0) +#endif + +#ifdef CONFIG_MACH_LOGI9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOGI9200 +# endif +# define machine_is_logi9200() (machine_arch_type == MACH_TYPE_LOGI9200) +#else +# define machine_is_logi9200() (0) +#endif + +#ifdef CONFIG_MACH_TQMA31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQMA31 +# endif +# define machine_is_tqma31() (machine_arch_type == MACH_TYPE_TQMA31) +#else +# define machine_is_tqma31() (0) +#endif + +#ifdef CONFIG_MACH_CCW9P9215JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9P9215JS +# endif +# define machine_is_ccw9p9215js() (machine_arch_type == MACH_TYPE_CCW9P9215JS) +#else +# define machine_is_ccw9p9215js() (0) +#endif + +#ifdef CONFIG_MACH_RD88F5181L_GE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F5181L_GE +# endif +# define machine_is_rd88f5181l_ge() (machine_arch_type == MACH_TYPE_RD88F5181L_GE) +#else +# define machine_is_rd88f5181l_ge() (0) +#endif + +#ifdef CONFIG_MACH_SIFMAIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIFMAIN +# endif +# define machine_is_sifmain() (machine_arch_type == MACH_TYPE_SIFMAIN) +#else +# define machine_is_sifmain() (0) +#endif + +#ifdef CONFIG_MACH_SAM9_L9261 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAM9_L9261 +# endif +# define machine_is_sam9_l9261() (machine_arch_type == MACH_TYPE_SAM9_L9261) +#else +# define machine_is_sam9_l9261() (0) +#endif + +#ifdef CONFIG_MACH_CC9M2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9M2443 +# endif +# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) +#else +# define machine_is_cc9m2443() (0) +#endif + +#ifdef CONFIG_MACH_XARIA300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XARIA300 +# endif +# define machine_is_xaria300() (machine_arch_type == MACH_TYPE_XARIA300) +#else +# define machine_is_xaria300() (0) +#endif + +#ifdef CONFIG_MACH_IT9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IT9200 +# endif +# define machine_is_it9200() (machine_arch_type == MACH_TYPE_IT9200) +#else +# define machine_is_it9200() (0) +#endif + +#ifdef CONFIG_MACH_RD88F5181L_FXO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F5181L_FXO +# endif +# define machine_is_rd88f5181l_fxo() (machine_arch_type == MACH_TYPE_RD88F5181L_FXO) +#else +# define machine_is_rd88f5181l_fxo() (0) +#endif + +#ifdef CONFIG_MACH_KRISS_SENSOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRISS_SENSOR +# endif +# define machine_is_kriss_sensor() (machine_arch_type == MACH_TYPE_KRISS_SENSOR) +#else +# define machine_is_kriss_sensor() (0) +#endif + +#ifdef CONFIG_MACH_PILZ_PMI5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PILZ_PMI5 +# endif +# define machine_is_pilz_pmi5() (machine_arch_type == MACH_TYPE_PILZ_PMI5) +#else +# define machine_is_pilz_pmi5() (0) +#endif + +#ifdef CONFIG_MACH_JADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADE +# endif +# define machine_is_jade() (machine_arch_type == MACH_TYPE_JADE) +#else +# define machine_is_jade() (0) +#endif + +#ifdef CONFIG_MACH_KS8695_SOFTPLC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KS8695_SOFTPLC +# endif +# define machine_is_ks8695_softplc() (machine_arch_type == MACH_TYPE_KS8695_SOFTPLC) +#else +# define machine_is_ks8695_softplc() (0) +#endif + +#ifdef CONFIG_MACH_GPRISC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GPRISC3 +# endif +# define machine_is_gprisc3() (machine_arch_type == MACH_TYPE_GPRISC3) +#else +# define machine_is_gprisc3() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G20 +# endif +# define machine_is_stamp9g20() (machine_arch_type == MACH_TYPE_STAMP9G20) +#else +# define machine_is_stamp9g20() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6430 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6430 +# endif +# define machine_is_smdk6430() (machine_arch_type == MACH_TYPE_SMDK6430) +#else +# define machine_is_smdk6430() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC100 +# endif +# define machine_is_smdkc100() (machine_arch_type == MACH_TYPE_SMDKC100) +#else +# define machine_is_smdkc100() (0) +#endif + +#ifdef CONFIG_MACH_TAVOREVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAVOREVB +# endif +# define machine_is_tavorevb() (machine_arch_type == MACH_TYPE_TAVOREVB) +#else +# define machine_is_tavorevb() (0) +#endif + +#ifdef CONFIG_MACH_SAAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAAR +# endif +# define machine_is_saar() (machine_arch_type == MACH_TYPE_SAAR) +#else +# define machine_is_saar() (0) +#endif + +#ifdef CONFIG_MACH_DEISTER_EYECAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEISTER_EYECAM +# endif +# define machine_is_deister_eyecam() (machine_arch_type == MACH_TYPE_DEISTER_EYECAM) +#else +# define machine_is_deister_eyecam() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9M10G45EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK +# endif +# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK) +#else +# define machine_is_at91sam9m10g45ek() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_PRODUO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_PRODUO +# endif +# define machine_is_linkstation_produo() (machine_arch_type == MACH_TYPE_LINKSTATION_PRODUO) +#else +# define machine_is_linkstation_produo() (0) +#endif + +#ifdef CONFIG_MACH_HIT_B0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIT_B0 +# endif +# define machine_is_hit_b0() (machine_arch_type == MACH_TYPE_HIT_B0) +#else +# define machine_is_hit_b0() (0) +#endif + +#ifdef CONFIG_MACH_ADX_RMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_RMU +# endif +# define machine_is_adx_rmu() (machine_arch_type == MACH_TYPE_ADX_RMU) +#else +# define machine_is_adx_rmu() (0) +#endif + +#ifdef CONFIG_MACH_XG_CPE_MAIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XG_CPE_MAIN +# endif +# define machine_is_xg_cpe_main() (machine_arch_type == MACH_TYPE_XG_CPE_MAIN) +#else +# define machine_is_xg_cpe_main() (0) +#endif + +#ifdef CONFIG_MACH_EDB9407A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9407A +# endif +# define machine_is_edb9407a() (machine_arch_type == MACH_TYPE_EDB9407A) +#else +# define machine_is_edb9407a() (0) +#endif + +#ifdef CONFIG_MACH_DTB9608 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DTB9608 +# endif +# define machine_is_dtb9608() (machine_arch_type == MACH_TYPE_DTB9608) +#else +# define machine_is_dtb9608() (0) +#endif + +#ifdef CONFIG_MACH_EM104V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EM104V1 +# endif +# define machine_is_em104v1() (machine_arch_type == MACH_TYPE_EM104V1) +#else +# define machine_is_em104v1() (0) +#endif + +#ifdef CONFIG_MACH_DEMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEMO +# endif +# define machine_is_demo() (machine_arch_type == MACH_TYPE_DEMO) +#else +# define machine_is_demo() (0) +#endif + +#ifdef CONFIG_MACH_LOGI9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOGI9260 +# endif +# define machine_is_logi9260() (machine_arch_type == MACH_TYPE_LOGI9260) +#else +# define machine_is_logi9260() (0) +#endif + +#ifdef CONFIG_MACH_MX31_EXM32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31_EXM32 +# endif +# define machine_is_mx31_exm32() (machine_arch_type == MACH_TYPE_MX31_EXM32) +#else +# define machine_is_mx31_exm32() (0) +#endif + +#ifdef CONFIG_MACH_USB_A9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_A9G20 +# endif +# define machine_is_usb_a9g20() (machine_arch_type == MACH_TYPE_USB_A9G20) +#else +# define machine_is_usb_a9g20() (0) +#endif + +#ifdef CONFIG_MACH_PICPROJE2008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICPROJE2008 +# endif +# define machine_is_picproje2008() (machine_arch_type == MACH_TYPE_PICPROJE2008) +#else +# define machine_is_picproje2008() (0) +#endif + +#ifdef CONFIG_MACH_CS_E9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS_E9315 +# endif +# define machine_is_cs_e9315() (machine_arch_type == MACH_TYPE_CS_E9315) +#else +# define machine_is_cs_e9315() (0) +#endif + +#ifdef CONFIG_MACH_QIL_A9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QIL_A9G20 +# endif +# define machine_is_qil_a9g20() (machine_arch_type == MACH_TYPE_QIL_A9G20) +#else +# define machine_is_qil_a9g20() (0) +#endif + +#ifdef CONFIG_MACH_SHA_PON020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHA_PON020 +# endif +# define machine_is_sha_pon020() (machine_arch_type == MACH_TYPE_SHA_PON020) +#else +# define machine_is_sha_pon020() (0) +#endif + +#ifdef CONFIG_MACH_NAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAD +# endif +# define machine_is_nad() (machine_arch_type == MACH_TYPE_NAD) +#else +# define machine_is_nad() (0) +#endif + +#ifdef CONFIG_MACH_SBC35_A9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC35_A9260 +# endif +# define machine_is_sbc35_a9260() (machine_arch_type == MACH_TYPE_SBC35_A9260) +#else +# define machine_is_sbc35_a9260() (0) +#endif + +#ifdef CONFIG_MACH_SBC35_A9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC35_A9G20 +# endif +# define machine_is_sbc35_a9g20() (machine_arch_type == MACH_TYPE_SBC35_A9G20) +#else +# define machine_is_sbc35_a9g20() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_BEGINNING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_BEGINNING +# endif +# define machine_is_davinci_beginning() (machine_arch_type == MACH_TYPE_DAVINCI_BEGINNING) +#else +# define machine_is_davinci_beginning() (0) +#endif + +#ifdef CONFIG_MACH_UWC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UWC +# endif +# define machine_is_uwc() (machine_arch_type == MACH_TYPE_UWC) +#else +# define machine_is_uwc() (0) +#endif + +#ifdef CONFIG_MACH_MXLADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXLADS +# endif +# define machine_is_mxlads() (machine_arch_type == MACH_TYPE_MXLADS) +#else +# define machine_is_mxlads() (0) +#endif + +#ifdef CONFIG_MACH_HTCNIKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCNIKE +# endif +# define machine_is_htcnike() (machine_arch_type == MACH_TYPE_HTCNIKE) +#else +# define machine_is_htcnike() (0) +#endif + +#ifdef CONFIG_MACH_DEISTER_PXA270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEISTER_PXA270 +# endif +# define machine_is_deister_pxa270() (machine_arch_type == MACH_TYPE_DEISTER_PXA270) +#else +# define machine_is_deister_pxa270() (0) +#endif + +#ifdef CONFIG_MACH_CME9210JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CME9210JS +# endif +# define machine_is_cme9210js() (machine_arch_type == MACH_TYPE_CME9210JS) +#else +# define machine_is_cme9210js() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9360 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9360 +# endif +# define machine_is_cc9p9360() (machine_arch_type == MACH_TYPE_CC9P9360) +#else +# define machine_is_cc9p9360() (0) +#endif + +#ifdef CONFIG_MACH_MOCHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOCHA +# endif +# define machine_is_mocha() (machine_arch_type == MACH_TYPE_MOCHA) +#else +# define machine_is_mocha() (0) +#endif + +#ifdef CONFIG_MACH_WAPD170AG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WAPD170AG +# endif +# define machine_is_wapd170ag() (machine_arch_type == MACH_TYPE_WAPD170AG) +#else +# define machine_is_wapd170ag() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_MINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_MINI +# endif +# define machine_is_linkstation_mini() (machine_arch_type == MACH_TYPE_LINKSTATION_MINI) +#else +# define machine_is_linkstation_mini() (0) +#endif + +#ifdef CONFIG_MACH_AFEB9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AFEB9260 +# endif +# define machine_is_afeb9260() (machine_arch_type == MACH_TYPE_AFEB9260) +#else +# define machine_is_afeb9260() (0) +#endif + +#ifdef CONFIG_MACH_W90X900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90X900 +# endif +# define machine_is_w90x900() (machine_arch_type == MACH_TYPE_W90X900) +#else +# define machine_is_w90x900() (0) +#endif + +#ifdef CONFIG_MACH_W90X700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90X700 +# endif +# define machine_is_w90x700() (machine_arch_type == MACH_TYPE_W90X700) +#else +# define machine_is_w90x700() (0) +#endif + +#ifdef CONFIG_MACH_KT300IP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KT300IP +# endif +# define machine_is_kt300ip() (machine_arch_type == MACH_TYPE_KT300IP) +#else +# define machine_is_kt300ip() (0) +#endif + +#ifdef CONFIG_MACH_KT300IP_G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KT300IP_G20 +# endif +# define machine_is_kt300ip_g20() (machine_arch_type == MACH_TYPE_KT300IP_G20) +#else +# define machine_is_kt300ip_g20() (0) +#endif + +#ifdef CONFIG_MACH_SRCM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SRCM +# endif +# define machine_is_srcm() (machine_arch_type == MACH_TYPE_SRCM) +#else +# define machine_is_srcm() (0) +#endif + +#ifdef CONFIG_MACH_WLNX_9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLNX_9260 +# endif +# define machine_is_wlnx_9260() (machine_arch_type == MACH_TYPE_WLNX_9260) +#else +# define machine_is_wlnx_9260() (0) +#endif + +#ifdef CONFIG_MACH_OPENMOKO_GTA03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENMOKO_GTA03 +# endif +# define machine_is_openmoko_gta03() (machine_arch_type == MACH_TYPE_OPENMOKO_GTA03) +#else +# define machine_is_openmoko_gta03() (0) +#endif + +#ifdef CONFIG_MACH_OSPREY2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OSPREY2 +# endif +# define machine_is_osprey2() (machine_arch_type == MACH_TYPE_OSPREY2) +#else +# define machine_is_osprey2() (0) +#endif + +#ifdef CONFIG_MACH_KBIO9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KBIO9260 +# endif +# define machine_is_kbio9260() (machine_arch_type == MACH_TYPE_KBIO9260) +#else +# define machine_is_kbio9260() (0) +#endif + +#ifdef CONFIG_MACH_GINZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GINZA +# endif +# define machine_is_ginza() (machine_arch_type == MACH_TYPE_GINZA) +#else +# define machine_is_ginza() (0) +#endif + +#ifdef CONFIG_MACH_A636N +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A636N +# endif +# define machine_is_a636n() (machine_arch_type == MACH_TYPE_A636N) +#else +# define machine_is_a636n() (0) +#endif + +#ifdef CONFIG_MACH_IMX27IPCAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27IPCAM +# endif +# define machine_is_imx27ipcam() (machine_arch_type == MACH_TYPE_IMX27IPCAM) +#else +# define machine_is_imx27ipcam() (0) +#endif + +#ifdef CONFIG_MACH_NEMOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEMOC +# endif +# define machine_is_nemoc() (machine_arch_type == MACH_TYPE_NEMOC) +#else +# define machine_is_nemoc() (0) +#endif + +#ifdef CONFIG_MACH_GENEVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GENEVA +# endif +# define machine_is_geneva() (machine_arch_type == MACH_TYPE_GENEVA) +#else +# define machine_is_geneva() (0) +#endif + +#ifdef CONFIG_MACH_HTCPHAROS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPHAROS +# endif +# define machine_is_htcpharos() (machine_arch_type == MACH_TYPE_HTCPHAROS) +#else +# define machine_is_htcpharos() (0) +#endif + +#ifdef CONFIG_MACH_NEONC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEONC +# endif +# define machine_is_neonc() (machine_arch_type == MACH_TYPE_NEONC) +#else +# define machine_is_neonc() (0) +#endif + +#ifdef CONFIG_MACH_NAS7100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAS7100 +# endif +# define machine_is_nas7100() (machine_arch_type == MACH_TYPE_NAS7100) +#else +# define machine_is_nas7100() (0) +#endif + +#ifdef CONFIG_MACH_TEUPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEUPHONE +# endif +# define machine_is_teuphone() (machine_arch_type == MACH_TYPE_TEUPHONE) +#else +# define machine_is_teuphone() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_ETH2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_ETH2 +# endif +# define machine_is_annax_eth2() (machine_arch_type == MACH_TYPE_ANNAX_ETH2) +#else +# define machine_is_annax_eth2() (0) +#endif + +#ifdef CONFIG_MACH_CSB733 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB733 +# endif +# define machine_is_csb733() (machine_arch_type == MACH_TYPE_CSB733) +#else +# define machine_is_csb733() (0) +#endif + +#ifdef CONFIG_MACH_BK3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BK3 +# endif +# define machine_is_bk3() (machine_arch_type == MACH_TYPE_BK3) +#else +# define machine_is_bk3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_EM32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_EM32 +# endif +# define machine_is_omap_em32() (machine_arch_type == MACH_TYPE_OMAP_EM32) +#else +# define machine_is_omap_em32() (0) +#endif + +#ifdef CONFIG_MACH_ET9261CP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ET9261CP +# endif +# define machine_is_et9261cp() (machine_arch_type == MACH_TYPE_ET9261CP) +#else +# define machine_is_et9261cp() (0) +#endif + +#ifdef CONFIG_MACH_JASPERC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JASPERC +# endif +# define machine_is_jasperc() (machine_arch_type == MACH_TYPE_JASPERC) +#else +# define machine_is_jasperc() (0) +#endif + +#ifdef CONFIG_MACH_ISSI_ARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ISSI_ARM9 +# endif +# define machine_is_issi_arm9() (machine_arch_type == MACH_TYPE_ISSI_ARM9) +#else +# define machine_is_issi_arm9() (0) +#endif + +#ifdef CONFIG_MACH_UED +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UED +# endif +# define machine_is_ued() (machine_arch_type == MACH_TYPE_UED) +#else +# define machine_is_ued() (0) +#endif + +#ifdef CONFIG_MACH_ESIBLADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESIBLADE +# endif +# define machine_is_esiblade() (machine_arch_type == MACH_TYPE_ESIBLADE) +#else +# define machine_is_esiblade() (0) +#endif + +#ifdef CONFIG_MACH_EYE02 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EYE02 +# endif +# define machine_is_eye02() (machine_arch_type == MACH_TYPE_EYE02) +#else +# define machine_is_eye02() (0) +#endif + +#ifdef CONFIG_MACH_IMX27KBD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27KBD +# endif +# define machine_is_imx27kbd() (machine_arch_type == MACH_TYPE_IMX27KBD) +#else +# define machine_is_imx27kbd() (0) +#endif + +#ifdef CONFIG_MACH_SST61VC010_FPGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SST61VC010_FPGA +# endif +# define machine_is_sst61vc010_fpga() (machine_arch_type == MACH_TYPE_SST61VC010_FPGA) +#else +# define machine_is_sst61vc010_fpga() (0) +#endif + +#ifdef CONFIG_MACH_KIXVP435 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIXVP435 +# endif +# define machine_is_kixvp435() (machine_arch_type == MACH_TYPE_KIXVP435) +#else +# define machine_is_kixvp435() (0) +#endif + +#ifdef CONFIG_MACH_KIXNP435 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIXNP435 +# endif +# define machine_is_kixnp435() (machine_arch_type == MACH_TYPE_KIXNP435) +#else +# define machine_is_kixnp435() (0) +#endif + +#ifdef CONFIG_MACH_AFRICA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AFRICA +# endif +# define machine_is_africa() (machine_arch_type == MACH_TYPE_AFRICA) +#else +# define machine_is_africa() (0) +#endif + +#ifdef CONFIG_MACH_NH233 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NH233 +# endif +# define machine_is_nh233() (machine_arch_type == MACH_TYPE_NH233) +#else +# define machine_is_nh233() (0) +#endif + +#ifdef CONFIG_MACH_RD88F6183AP_GE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F6183AP_GE +# endif +# define machine_is_rd88f6183ap_ge() (machine_arch_type == MACH_TYPE_RD88F6183AP_GE) +#else +# define machine_is_rd88f6183ap_ge() (0) +#endif + +#ifdef CONFIG_MACH_BCM4760 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM4760 +# endif +# define machine_is_bcm4760() (machine_arch_type == MACH_TYPE_BCM4760) +#else +# define machine_is_bcm4760() (0) +#endif + +#ifdef CONFIG_MACH_EDDY_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDDY_V2 +# endif +# define machine_is_eddy_v2() (machine_arch_type == MACH_TYPE_EDDY_V2) +#else +# define machine_is_eddy_v2() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_PBA8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_PBA8 +# endif +# define machine_is_realview_pba8() (machine_arch_type == MACH_TYPE_REALVIEW_PBA8) +#else +# define machine_is_realview_pba8() (0) +#endif + +#ifdef CONFIG_MACH_HID_A7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HID_A7 +# endif +# define machine_is_hid_a7() (machine_arch_type == MACH_TYPE_HID_A7) +#else +# define machine_is_hid_a7() (0) +#endif + +#ifdef CONFIG_MACH_HERO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERO +# endif +# define machine_is_hero() (machine_arch_type == MACH_TYPE_HERO) +#else +# define machine_is_hero() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_POSEIDON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_POSEIDON +# endif +# define machine_is_omap_poseidon() (machine_arch_type == MACH_TYPE_OMAP_POSEIDON) +#else +# define machine_is_omap_poseidon() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_PBX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_PBX +# endif +# define machine_is_realview_pbx() (machine_arch_type == MACH_TYPE_REALVIEW_PBX) +#else +# define machine_is_realview_pbx() (0) +#endif + +#ifdef CONFIG_MACH_MICRO9S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO9S +# endif +# define machine_is_micro9s() (machine_arch_type == MACH_TYPE_MICRO9S) +#else +# define machine_is_micro9s() (0) +#endif + +#ifdef CONFIG_MACH_MAKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAKO +# endif +# define machine_is_mako() (machine_arch_type == MACH_TYPE_MAKO) +#else +# define machine_is_mako() (0) +#endif + +#ifdef CONFIG_MACH_XDAFLAME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XDAFLAME +# endif +# define machine_is_xdaflame() (machine_arch_type == MACH_TYPE_XDAFLAME) +#else +# define machine_is_xdaflame() (0) +#endif + +#ifdef CONFIG_MACH_PHIDGET_SBC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHIDGET_SBC2 +# endif +# define machine_is_phidget_sbc2() (machine_arch_type == MACH_TYPE_PHIDGET_SBC2) +#else +# define machine_is_phidget_sbc2() (0) +#endif + +#ifdef CONFIG_MACH_LIMESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIMESTONE +# endif +# define machine_is_limestone() (machine_arch_type == MACH_TYPE_LIMESTONE) +#else +# define machine_is_limestone() (0) +#endif + +#ifdef CONFIG_MACH_IPROBE_C32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPROBE_C32 +# endif +# define machine_is_iprobe_c32() (machine_arch_type == MACH_TYPE_IPROBE_C32) +#else +# define machine_is_iprobe_c32() (0) +#endif + +#ifdef CONFIG_MACH_RUT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RUT100 +# endif +# define machine_is_rut100() (machine_arch_type == MACH_TYPE_RUT100) +#else +# define machine_is_rut100() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP535 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP535 +# endif +# define machine_is_asusp535() (machine_arch_type == MACH_TYPE_ASUSP535) +#else +# define machine_is_asusp535() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL +# endif +# define machine_is_htcraphael() (machine_arch_type == MACH_TYPE_HTCRAPHAEL) +#else +# define machine_is_htcraphael() (0) +#endif + +#ifdef CONFIG_MACH_SYGDG1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYGDG1 +# endif +# define machine_is_sygdg1() (machine_arch_type == MACH_TYPE_SYGDG1) +#else +# define machine_is_sygdg1() (0) +#endif + +#ifdef CONFIG_MACH_SYGDG2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYGDG2 +# endif +# define machine_is_sygdg2() (machine_arch_type == MACH_TYPE_SYGDG2) +#else +# define machine_is_sygdg2() (0) +#endif + +#ifdef CONFIG_MACH_SEOUL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEOUL +# endif +# define machine_is_seoul() (machine_arch_type == MACH_TYPE_SEOUL) +#else +# define machine_is_seoul() (0) +#endif + +#ifdef CONFIG_MACH_SALERNO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SALERNO +# endif +# define machine_is_salerno() (machine_arch_type == MACH_TYPE_SALERNO) +#else +# define machine_is_salerno() (0) +#endif + +#ifdef CONFIG_MACH_UCN_S3C64XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UCN_S3C64XX +# endif +# define machine_is_ucn_s3c64xx() (machine_arch_type == MACH_TYPE_UCN_S3C64XX) +#else +# define machine_is_ucn_s3c64xx() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A +# endif +# define machine_is_msm7201a() (machine_arch_type == MACH_TYPE_MSM7201A) +#else +# define machine_is_msm7201a() (0) +#endif + +#ifdef CONFIG_MACH_LPR1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPR1 +# endif +# define machine_is_lpr1() (machine_arch_type == MACH_TYPE_LPR1) +#else +# define machine_is_lpr1() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO500FX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO500FX +# endif +# define machine_is_armadillo500fx() (machine_arch_type == MACH_TYPE_ARMADILLO500FX) +#else +# define machine_is_armadillo500fx() (0) +#endif + +#ifdef CONFIG_MACH_G3EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G3EVM +# endif +# define machine_is_g3evm() (machine_arch_type == MACH_TYPE_G3EVM) +#else +# define machine_is_g3evm() (0) +#endif + +#ifdef CONFIG_MACH_Z3_DM355 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z3_DM355 +# endif +# define machine_is_z3_dm355() (machine_arch_type == MACH_TYPE_Z3_DM355) +#else +# define machine_is_z3_dm355() (0) +#endif + +#ifdef CONFIG_MACH_W90P910EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P910EVB +# endif +# define machine_is_w90p910evb() (machine_arch_type == MACH_TYPE_W90P910EVB) +#else +# define machine_is_w90p910evb() (0) +#endif + +#ifdef CONFIG_MACH_W90P920EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P920EVB +# endif +# define machine_is_w90p920evb() (machine_arch_type == MACH_TYPE_W90P920EVB) +#else +# define machine_is_w90p920evb() (0) +#endif + +#ifdef CONFIG_MACH_W90P950EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P950EVB +# endif +# define machine_is_w90p950evb() (machine_arch_type == MACH_TYPE_W90P950EVB) +#else +# define machine_is_w90p950evb() (0) +#endif + +#ifdef CONFIG_MACH_W90N960EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90N960EVB +# endif +# define machine_is_w90n960evb() (machine_arch_type == MACH_TYPE_W90N960EVB) +#else +# define machine_is_w90n960evb() (0) +#endif + +#ifdef CONFIG_MACH_CAMHD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAMHD +# endif +# define machine_is_camhd() (machine_arch_type == MACH_TYPE_CAMHD) +#else +# define machine_is_camhd() (0) +#endif + +#ifdef CONFIG_MACH_MVC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MVC100 +# endif +# define machine_is_mvc100() (machine_arch_type == MACH_TYPE_MVC100) +#else +# define machine_is_mvc100() (0) +#endif + +#ifdef CONFIG_MACH_ELECTRUM_200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELECTRUM_200 +# endif +# define machine_is_electrum_200() (machine_arch_type == MACH_TYPE_ELECTRUM_200) +#else +# define machine_is_electrum_200() (0) +#endif + +#ifdef CONFIG_MACH_HTCJADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCJADE +# endif +# define machine_is_htcjade() (machine_arch_type == MACH_TYPE_HTCJADE) +#else +# define machine_is_htcjade() (0) +#endif + +#ifdef CONFIG_MACH_MEMPHIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEMPHIS +# endif +# define machine_is_memphis() (machine_arch_type == MACH_TYPE_MEMPHIS) +#else +# define machine_is_memphis() (0) +#endif + +#ifdef CONFIG_MACH_IMX27SBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27SBC +# endif +# define machine_is_imx27sbc() (machine_arch_type == MACH_TYPE_IMX27SBC) +#else +# define machine_is_imx27sbc() (0) +#endif + +#ifdef CONFIG_MACH_LEXTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEXTAR +# endif +# define machine_is_lextar() (machine_arch_type == MACH_TYPE_LEXTAR) +#else +# define machine_is_lextar() (0) +#endif + +#ifdef CONFIG_MACH_MV88F6281GTW_GE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV88F6281GTW_GE +# endif +# define machine_is_mv88f6281gtw_ge() (machine_arch_type == MACH_TYPE_MV88F6281GTW_GE) +#else +# define machine_is_mv88f6281gtw_ge() (0) +#endif + +#ifdef CONFIG_MACH_NCP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NCP +# endif +# define machine_is_ncp() (machine_arch_type == MACH_TYPE_NCP) +#else +# define machine_is_ncp() (0) +#endif + +#ifdef CONFIG_MACH_Z32AN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z32AN +# endif +# define machine_is_z32an_series() (machine_arch_type == MACH_TYPE_Z32AN) +#else +# define machine_is_z32an_series() (0) +#endif + +#ifdef CONFIG_MACH_TMQ_CAPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TMQ_CAPD +# endif +# define machine_is_tmq_capd() (machine_arch_type == MACH_TYPE_TMQ_CAPD) +#else +# define machine_is_tmq_capd() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_WL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_WL +# endif +# define machine_is_omap3_wl() (machine_arch_type == MACH_TYPE_OMAP3_WL) +#else +# define machine_is_omap3_wl() (0) +#endif + +#ifdef CONFIG_MACH_CHUMBY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHUMBY +# endif +# define machine_is_chumby() (machine_arch_type == MACH_TYPE_CHUMBY) +#else +# define machine_is_chumby() (0) +#endif + +#ifdef CONFIG_MACH_ATSARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATSARM9 +# endif +# define machine_is_atsarm9() (machine_arch_type == MACH_TYPE_ATSARM9) +#else +# define machine_is_atsarm9() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_EVM +# endif +# define machine_is_davinci_dm365_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM) +#else +# define machine_is_davinci_dm365_evm() (0) +#endif + +#ifdef CONFIG_MACH_BAHAMAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BAHAMAS +# endif +# define machine_is_bahamas() (machine_arch_type == MACH_TYPE_BAHAMAS) +#else +# define machine_is_bahamas() (0) +#endif + +#ifdef CONFIG_MACH_DAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAS +# endif +# define machine_is_das() (machine_arch_type == MACH_TYPE_DAS) +#else +# define machine_is_das() (0) +#endif + +#ifdef CONFIG_MACH_MINIDAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIDAS +# endif +# define machine_is_minidas() (machine_arch_type == MACH_TYPE_MINIDAS) +#else +# define machine_is_minidas() (0) +#endif + +#ifdef CONFIG_MACH_VK1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VK1000 +# endif +# define machine_is_vk1000() (machine_arch_type == MACH_TYPE_VK1000) +#else +# define machine_is_vk1000() (0) +#endif + +#ifdef CONFIG_MACH_CENTRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CENTRO +# endif +# define machine_is_centro() (machine_arch_type == MACH_TYPE_CENTRO) +#else +# define machine_is_centro() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY +# endif +# define machine_is_ctera_2bay() (machine_arch_type == MACH_TYPE_CTERA_2BAY) +#else +# define machine_is_ctera_2bay() (0) +#endif + +#ifdef CONFIG_MACH_EDGECONNECT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDGECONNECT +# endif +# define machine_is_edgeconnect() (machine_arch_type == MACH_TYPE_EDGECONNECT) +#else +# define machine_is_edgeconnect() (0) +#endif + +#ifdef CONFIG_MACH_ND27000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ND27000 +# endif +# define machine_is_nd27000() (machine_arch_type == MACH_TYPE_ND27000) +#else +# define machine_is_nd27000() (0) +#endif + +#ifdef CONFIG_MACH_GEMALTO_COBRA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMALTO_COBRA +# endif +# define machine_is_cobra() (machine_arch_type == MACH_TYPE_GEMALTO_COBRA) +#else +# define machine_is_cobra() (0) +#endif + +#ifdef CONFIG_MACH_INGELABS_COMET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INGELABS_COMET +# endif +# define machine_is_ingelabs_comet() (machine_arch_type == MACH_TYPE_INGELABS_COMET) +#else +# define machine_is_ingelabs_comet() (0) +#endif + +#ifdef CONFIG_MACH_POLLUX_WIZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POLLUX_WIZ +# endif +# define machine_is_pollux_wiz() (machine_arch_type == MACH_TYPE_POLLUX_WIZ) +#else +# define machine_is_pollux_wiz() (0) +#endif + +#ifdef CONFIG_MACH_BLACKSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLACKSTONE +# endif +# define machine_is_blackstone() (machine_arch_type == MACH_TYPE_BLACKSTONE) +#else +# define machine_is_blackstone() (0) +#endif + +#ifdef CONFIG_MACH_TOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPAZ +# endif +# define machine_is_topaz() (machine_arch_type == MACH_TYPE_TOPAZ) +#else +# define machine_is_topaz() (0) +#endif + +#ifdef CONFIG_MACH_AIXLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AIXLE +# endif +# define machine_is_aixle() (machine_arch_type == MACH_TYPE_AIXLE) +#else +# define machine_is_aixle() (0) +#endif + +#ifdef CONFIG_MACH_MW998 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW998 +# endif +# define machine_is_mw998() (machine_arch_type == MACH_TYPE_MW998) +#else +# define machine_is_mw998() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA_RX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA_RX51 +# endif +# define machine_is_nokia_rx51() (machine_arch_type == MACH_TYPE_NOKIA_RX51) +#else +# define machine_is_nokia_rx51() (0) +#endif + +#ifdef CONFIG_MACH_VSC5605EV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VSC5605EV +# endif +# define machine_is_vsc5605ev() (machine_arch_type == MACH_TYPE_VSC5605EV) +#else +# define machine_is_vsc5605ev() (0) +#endif + +#ifdef CONFIG_MACH_NT98700DK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NT98700DK +# endif +# define machine_is_nt98700dk() (machine_arch_type == MACH_TYPE_NT98700DK) +#else +# define machine_is_nt98700dk() (0) +#endif + +#ifdef CONFIG_MACH_ICONTACT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONTACT +# endif +# define machine_is_icontact() (machine_arch_type == MACH_TYPE_ICONTACT) +#else +# define machine_is_icontact() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_FRCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_FRCPU +# endif +# define machine_is_swarco_frcpu() (machine_arch_type == MACH_TYPE_SWARCO_FRCPU) +#else +# define machine_is_swarco_frcpu() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_SCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_SCPU +# endif +# define machine_is_swarco_scpu() (machine_arch_type == MACH_TYPE_SWARCO_SCPU) +#else +# define machine_is_swarco_scpu() (0) +#endif + +#ifdef CONFIG_MACH_BBOX_P16 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BBOX_P16 +# endif +# define machine_is_bbox_p16() (machine_arch_type == MACH_TYPE_BBOX_P16) +#else +# define machine_is_bbox_p16() (0) +#endif + +#ifdef CONFIG_MACH_BSTD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSTD +# endif +# define machine_is_bstd() (machine_arch_type == MACH_TYPE_BSTD) +#else +# define machine_is_bstd() (0) +#endif + +#ifdef CONFIG_MACH_SBC2440II +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC2440II +# endif +# define machine_is_sbc2440ii() (machine_arch_type == MACH_TYPE_SBC2440II) +#else +# define machine_is_sbc2440ii() (0) +#endif + +#ifdef CONFIG_MACH_PCM034 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM034 +# endif +# define machine_is_pcm034() (machine_arch_type == MACH_TYPE_PCM034) +#else +# define machine_is_pcm034() (0) +#endif + +#ifdef CONFIG_MACH_NESO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NESO +# endif +# define machine_is_neso() (machine_arch_type == MACH_TYPE_NESO) +#else +# define machine_is_neso() (0) +#endif + +#ifdef CONFIG_MACH_WLNX_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLNX_9G20 +# endif +# define machine_is_wlnx_9g20() (machine_arch_type == MACH_TYPE_WLNX_9G20) +#else +# define machine_is_wlnx_9g20() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_ZOOM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_ZOOM2 +# endif +# define machine_is_omap_zoom2() (machine_arch_type == MACH_TYPE_OMAP_ZOOM2) +#else +# define machine_is_omap_zoom2() (0) +#endif + +#ifdef CONFIG_MACH_TOTEMNOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOTEMNOVA +# endif +# define machine_is_totemnova() (machine_arch_type == MACH_TYPE_TOTEMNOVA) +#else +# define machine_is_totemnova() (0) +#endif + +#ifdef CONFIG_MACH_C5000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C5000 +# endif +# define machine_is_c5000() (machine_arch_type == MACH_TYPE_C5000) +#else +# define machine_is_c5000() (0) +#endif + +#ifdef CONFIG_MACH_UNIPO_AT91SAM9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIPO_AT91SAM9263 +# endif +# define machine_is_unipo_at91sam9263() (machine_arch_type == MACH_TYPE_UNIPO_AT91SAM9263) +#else +# define machine_is_unipo_at91sam9263() (0) +#endif + +#ifdef CONFIG_MACH_ETHERNUT5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERNUT5 +# endif +# define machine_is_ethernut5() (machine_arch_type == MACH_TYPE_ETHERNUT5) +#else +# define machine_is_ethernut5() (0) +#endif + +#ifdef CONFIG_MACH_ARM11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM11 +# endif +# define machine_is_arm11() (machine_arch_type == MACH_TYPE_ARM11) +#else +# define machine_is_arm11() (0) +#endif + +#ifdef CONFIG_MACH_CPUAT9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUAT9260 +# endif +# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260) +#else +# define machine_is_cpuat9260() (0) +#endif + +#ifdef CONFIG_MACH_CPUPXA255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUPXA255 +# endif +# define machine_is_cpupxa255() (machine_arch_type == MACH_TYPE_CPUPXA255) +#else +# define machine_is_cpupxa255() (0) +#endif + +#ifdef CONFIG_MACH_CPUIMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUIMX27 +# endif +# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) +#else +# define machine_is_eukrea_cpuimx27() (0) +#endif + +#ifdef CONFIG_MACH_CHEFLUX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHEFLUX +# endif +# define machine_is_cheflux() (machine_arch_type == MACH_TYPE_CHEFLUX) +#else +# define machine_is_cheflux() (0) +#endif + +#ifdef CONFIG_MACH_EB_CPUX9K2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EB_CPUX9K2 +# endif +# define machine_is_eb_cpux9k2() (machine_arch_type == MACH_TYPE_EB_CPUX9K2) +#else +# define machine_is_eb_cpux9k2() (0) +#endif + +#ifdef CONFIG_MACH_OPCOTEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPCOTEC +# endif +# define machine_is_opcotec() (machine_arch_type == MACH_TYPE_OPCOTEC) +#else +# define machine_is_opcotec() (0) +#endif + +#ifdef CONFIG_MACH_YT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YT +# endif +# define machine_is_yt() (machine_arch_type == MACH_TYPE_YT) +#else +# define machine_is_yt() (0) +#endif + +#ifdef CONFIG_MACH_MOTOQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOQ +# endif +# define machine_is_motoq() (machine_arch_type == MACH_TYPE_MOTOQ) +#else +# define machine_is_motoq() (0) +#endif + +#ifdef CONFIG_MACH_BSB1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSB1 +# endif +# define machine_is_bsb1() (machine_arch_type == MACH_TYPE_BSB1) +#else +# define machine_is_bsb1() (0) +#endif + +#ifdef CONFIG_MACH_ACS5K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACS5K +# endif +# define machine_is_acs5k() (machine_arch_type == MACH_TYPE_ACS5K) +#else +# define machine_is_acs5k() (0) +#endif + +#ifdef CONFIG_MACH_MILAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILAN +# endif +# define machine_is_milan() (machine_arch_type == MACH_TYPE_MILAN) +#else +# define machine_is_milan() (0) +#endif + +#ifdef CONFIG_MACH_QUARTZV2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUARTZV2 +# endif +# define machine_is_quartzv2() (machine_arch_type == MACH_TYPE_QUARTZV2) +#else +# define machine_is_quartzv2() (0) +#endif + +#ifdef CONFIG_MACH_RSVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSVP +# endif +# define machine_is_rsvp() (machine_arch_type == MACH_TYPE_RSVP) +#else +# define machine_is_rsvp() (0) +#endif + +#ifdef CONFIG_MACH_RMP200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RMP200 +# endif +# define machine_is_rmp200() (machine_arch_type == MACH_TYPE_RMP200) +#else +# define machine_is_rmp200() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER_9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER_9260 +# endif +# define machine_is_snapper_9260() (machine_arch_type == MACH_TYPE_SNAPPER_9260) +#else +# define machine_is_snapper_9260() (0) +#endif + +#ifdef CONFIG_MACH_DSM320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSM320 +# endif +# define machine_is_dsm320() (machine_arch_type == MACH_TYPE_DSM320) +#else +# define machine_is_dsm320() (0) +#endif + +#ifdef CONFIG_MACH_ADSGCM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSGCM +# endif +# define machine_is_adsgcm() (machine_arch_type == MACH_TYPE_ADSGCM) +#else +# define machine_is_adsgcm() (0) +#endif + +#ifdef CONFIG_MACH_ASE2_400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASE2_400 +# endif +# define machine_is_ase2_400() (machine_arch_type == MACH_TYPE_ASE2_400) +#else +# define machine_is_ase2_400() (0) +#endif + +#ifdef CONFIG_MACH_PIZZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PIZZA +# endif +# define machine_is_pizza() (machine_arch_type == MACH_TYPE_PIZZA) +#else +# define machine_is_pizza() (0) +#endif + +#ifdef CONFIG_MACH_SPOT_NGPL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPOT_NGPL +# endif +# define machine_is_spot_ngpl() (machine_arch_type == MACH_TYPE_SPOT_NGPL) +#else +# define machine_is_spot_ngpl() (0) +#endif + +#ifdef CONFIG_MACH_ARMATA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMATA +# endif +# define machine_is_armata() (machine_arch_type == MACH_TYPE_ARMATA) +#else +# define machine_is_armata() (0) +#endif + +#ifdef CONFIG_MACH_EXEDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXEDA +# endif +# define machine_is_exeda() (machine_arch_type == MACH_TYPE_EXEDA) +#else +# define machine_is_exeda() (0) +#endif + +#ifdef CONFIG_MACH_MX31SF005 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31SF005 +# endif +# define machine_is_mx31sf005() (machine_arch_type == MACH_TYPE_MX31SF005) +#else +# define machine_is_mx31sf005() (0) +#endif + +#ifdef CONFIG_MACH_F5D8231_4_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_F5D8231_4_V2 +# endif +# define machine_is_f5d8231_4_v2() (machine_arch_type == MACH_TYPE_F5D8231_4_V2) +#else +# define machine_is_f5d8231_4_v2() (0) +#endif + +#ifdef CONFIG_MACH_Q2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Q2440 +# endif +# define machine_is_q2440() (machine_arch_type == MACH_TYPE_Q2440) +#else +# define machine_is_q2440() (0) +#endif + +#ifdef CONFIG_MACH_QQ2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QQ2440 +# endif +# define machine_is_qq2440() (machine_arch_type == MACH_TYPE_QQ2440) +#else +# define machine_is_qq2440() (0) +#endif + +#ifdef CONFIG_MACH_MINI2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI2440 +# endif +# define machine_is_mini2440() (machine_arch_type == MACH_TYPE_MINI2440) +#else +# define machine_is_mini2440() (0) +#endif + +#ifdef CONFIG_MACH_COLIBRI300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI300 +# endif +# define machine_is_colibri300() (machine_arch_type == MACH_TYPE_COLIBRI300) +#else +# define machine_is_colibri300() (0) +#endif + +#ifdef CONFIG_MACH_JADES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADES +# endif +# define machine_is_jades() (machine_arch_type == MACH_TYPE_JADES) +#else +# define machine_is_jades() (0) +#endif + +#ifdef CONFIG_MACH_SPARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARK +# endif +# define machine_is_spark() (machine_arch_type == MACH_TYPE_SPARK) +#else +# define machine_is_spark() (0) +#endif + +#ifdef CONFIG_MACH_BENZINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZINA +# endif +# define machine_is_benzina() (machine_arch_type == MACH_TYPE_BENZINA) +#else +# define machine_is_benzina() (0) +#endif + +#ifdef CONFIG_MACH_BLAZE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLAZE +# endif +# define machine_is_blaze() (machine_arch_type == MACH_TYPE_BLAZE) +#else +# define machine_is_blaze() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_LS_HGL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_LS_HGL +# endif +# define machine_is_linkstation_ls_hgl() (machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL) +#else +# define machine_is_linkstation_ls_hgl() (0) +#endif + +#ifdef CONFIG_MACH_HTCVENUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCVENUS +# endif +# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCVENUS) +#else +# define machine_is_htckovsky() (0) +#endif + +#ifdef CONFIG_MACH_SONY_PRS505 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONY_PRS505 +# endif +# define machine_is_sony_prs505() (machine_arch_type == MACH_TYPE_SONY_PRS505) +#else +# define machine_is_sony_prs505() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V3 +# endif +# define machine_is_hanlin_v3() (machine_arch_type == MACH_TYPE_HANLIN_V3) +#else +# define machine_is_hanlin_v3() (0) +#endif + +#ifdef CONFIG_MACH_SAPPHIRA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAPPHIRA +# endif +# define machine_is_sapphira() (machine_arch_type == MACH_TYPE_SAPPHIRA) +#else +# define machine_is_sapphira() (0) +#endif + +#ifdef CONFIG_MACH_DACK_SDA_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DACK_SDA_01 +# endif +# define machine_is_dack_sda_01() (machine_arch_type == MACH_TYPE_DACK_SDA_01) +#else +# define machine_is_dack_sda_01() (0) +#endif + +#ifdef CONFIG_MACH_ARMBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMBOX +# endif +# define machine_is_armbox() (machine_arch_type == MACH_TYPE_ARMBOX) +#else +# define machine_is_armbox() (0) +#endif + +#ifdef CONFIG_MACH_HARRIS_RVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HARRIS_RVP +# endif +# define machine_is_harris_rvp() (machine_arch_type == MACH_TYPE_HARRIS_RVP) +#else +# define machine_is_harris_rvp() (0) +#endif + +#ifdef CONFIG_MACH_RIBALDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIBALDO +# endif +# define machine_is_ribaldo() (machine_arch_type == MACH_TYPE_RIBALDO) +#else +# define machine_is_ribaldo() (0) +#endif + +#ifdef CONFIG_MACH_AGORA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AGORA +# endif +# define machine_is_agora() (machine_arch_type == MACH_TYPE_AGORA) +#else +# define machine_is_agora() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_MINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_MINI +# endif +# define machine_is_omap3_mini() (machine_arch_type == MACH_TYPE_OMAP3_MINI) +#else +# define machine_is_omap3_mini() (0) +#endif + +#ifdef CONFIG_MACH_A9SAM6432_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9SAM6432_B +# endif +# define machine_is_a9sam6432_b() (machine_arch_type == MACH_TYPE_A9SAM6432_B) +#else +# define machine_is_a9sam6432_b() (0) +#endif + +#ifdef CONFIG_MACH_USG2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USG2410 +# endif +# define machine_is_usg2410() (machine_arch_type == MACH_TYPE_USG2410) +#else +# define machine_is_usg2410() (0) +#endif + +#ifdef CONFIG_MACH_PC72052_I10_REVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC72052_I10_REVB +# endif +# define machine_is_pc72052_i10_revb() (machine_arch_type == MACH_TYPE_PC72052_I10_REVB) +#else +# define machine_is_pc72052_i10_revb() (0) +#endif + +#ifdef CONFIG_MACH_MX35_EXM32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35_EXM32 +# endif +# define machine_is_mx35_exm32() (machine_arch_type == MACH_TYPE_MX35_EXM32) +#else +# define machine_is_mx35_exm32() (0) +#endif + +#ifdef CONFIG_MACH_TOPAS910 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPAS910 +# endif +# define machine_is_topas910() (machine_arch_type == MACH_TYPE_TOPAS910) +#else +# define machine_is_topas910() (0) +#endif + +#ifdef CONFIG_MACH_HYENA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HYENA +# endif +# define machine_is_hyena() (machine_arch_type == MACH_TYPE_HYENA) +#else +# define machine_is_hyena() (0) +#endif + +#ifdef CONFIG_MACH_POSPAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POSPAX +# endif +# define machine_is_pospax() (machine_arch_type == MACH_TYPE_POSPAX) +#else +# define machine_is_pospax() (0) +#endif + +#ifdef CONFIG_MACH_HDL_GX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDL_GX +# endif +# define machine_is_hdl_gx() (machine_arch_type == MACH_TYPE_HDL_GX) +#else +# define machine_is_hdl_gx() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_4BAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_4BAY +# endif +# define machine_is_ctera_4bay() (machine_arch_type == MACH_TYPE_CTERA_4BAY) +#else +# define machine_is_ctera_4bay() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_PLUG_C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_PLUG_C +# endif +# define machine_is_ctera_plug_c() (machine_arch_type == MACH_TYPE_CTERA_PLUG_C) +#else +# define machine_is_ctera_plug_c() (0) +#endif + +#ifdef CONFIG_MACH_CRWEA_PLUG_I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRWEA_PLUG_I +# endif +# define machine_is_crwea_plug_i() (machine_arch_type == MACH_TYPE_CRWEA_PLUG_I) +#else +# define machine_is_crwea_plug_i() (0) +#endif + +#ifdef CONFIG_MACH_EGAUGE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EGAUGE2 +# endif +# define machine_is_egauge2() (machine_arch_type == MACH_TYPE_EGAUGE2) +#else +# define machine_is_egauge2() (0) +#endif + +#ifdef CONFIG_MACH_DIDJ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DIDJ +# endif +# define machine_is_didj() (machine_arch_type == MACH_TYPE_DIDJ) +#else +# define machine_is_didj() (0) +#endif + +#ifdef CONFIG_MACH_MEISTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEISTER +# endif +# define machine_is_m_s3c2443() (machine_arch_type == MACH_TYPE_MEISTER) +#else +# define machine_is_m_s3c2443() (0) +#endif + +#ifdef CONFIG_MACH_HTCBLACKSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCBLACKSTONE +# endif +# define machine_is_htcblackstone() (machine_arch_type == MACH_TYPE_HTCBLACKSTONE) +#else +# define machine_is_htcblackstone() (0) +#endif + +#ifdef CONFIG_MACH_CPUAT9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUAT9G20 +# endif +# define machine_is_cpuat9g20() (machine_arch_type == MACH_TYPE_CPUAT9G20) +#else +# define machine_is_cpuat9g20() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6440 +# endif +# define machine_is_smdk6440() (machine_arch_type == MACH_TYPE_SMDK6440) +#else +# define machine_is_smdk6440() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_35XX_MVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_35XX_MVP +# endif +# define machine_is_omap_35xx_mvp() (machine_arch_type == MACH_TYPE_OMAP_35XX_MVP) +#else +# define machine_is_omap_35xx_mvp() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_PLUG_I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_PLUG_I +# endif +# define machine_is_ctera_plug_i() (machine_arch_type == MACH_TYPE_CTERA_PLUG_I) +#else +# define machine_is_ctera_plug_i() (0) +#endif + +#ifdef CONFIG_MACH_PVG610 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PVG610 +# endif +# define machine_is_pvg610_100() (machine_arch_type == MACH_TYPE_PVG610) +#else +# define machine_is_pvg610_100() (0) +#endif + +#ifdef CONFIG_MACH_HPRW6815 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPRW6815 +# endif +# define machine_is_hprw6815() (machine_arch_type == MACH_TYPE_HPRW6815) +#else +# define machine_is_hprw6815() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_OSWALD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_OSWALD +# endif +# define machine_is_omap3_oswald() (machine_arch_type == MACH_TYPE_OMAP3_OSWALD) +#else +# define machine_is_omap3_oswald() (0) +#endif + +#ifdef CONFIG_MACH_NAS4220B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAS4220B +# endif +# define machine_is_nas4220b() (machine_arch_type == MACH_TYPE_NAS4220B) +#else +# define machine_is_nas4220b() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA +# endif +# define machine_is_htcraphael_cdma() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA) +#else +# define machine_is_htcraphael_cdma() (0) +#endif + +#ifdef CONFIG_MACH_HTCDIAMOND_CDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCDIAMOND_CDMA +# endif +# define machine_is_htcdiamond_cdma() (machine_arch_type == MACH_TYPE_HTCDIAMOND_CDMA) +#else +# define machine_is_htcdiamond_cdma() (0) +#endif + +#ifdef CONFIG_MACH_SCALER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCALER +# endif +# define machine_is_scaler() (machine_arch_type == MACH_TYPE_SCALER) +#else +# define machine_is_scaler() (0) +#endif + +#ifdef CONFIG_MACH_ZYLONITE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZYLONITE2 +# endif +# define machine_is_zylonite2() (machine_arch_type == MACH_TYPE_ZYLONITE2) +#else +# define machine_is_zylonite2() (0) +#endif + +#ifdef CONFIG_MACH_ASPENITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASPENITE +# endif +# define machine_is_aspenite() (machine_arch_type == MACH_TYPE_ASPENITE) +#else +# define machine_is_aspenite() (0) +#endif + +#ifdef CONFIG_MACH_TETON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TETON +# endif +# define machine_is_teton() (machine_arch_type == MACH_TYPE_TETON) +#else +# define machine_is_teton() (0) +#endif + +#ifdef CONFIG_MACH_TTC_DKB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TTC_DKB +# endif +# define machine_is_ttc_dkb() (machine_arch_type == MACH_TYPE_TTC_DKB) +#else +# define machine_is_ttc_dkb() (0) +#endif + +#ifdef CONFIG_MACH_BISHOP2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BISHOP2 +# endif +# define machine_is_bishop2() (machine_arch_type == MACH_TYPE_BISHOP2) +#else +# define machine_is_bishop2() (0) +#endif + +#ifdef CONFIG_MACH_IPPV5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPPV5 +# endif +# define machine_is_ippv5() (machine_arch_type == MACH_TYPE_IPPV5) +#else +# define machine_is_ippv5() (0) +#endif + +#ifdef CONFIG_MACH_FARM926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FARM926 +# endif +# define machine_is_farm926() (machine_arch_type == MACH_TYPE_FARM926) +#else +# define machine_is_farm926() (0) +#endif + +#ifdef CONFIG_MACH_MMCCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMCCPU +# endif +# define machine_is_mmccpu() (machine_arch_type == MACH_TYPE_MMCCPU) +#else +# define machine_is_mmccpu() (0) +#endif + +#ifdef CONFIG_MACH_SGMSFL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGMSFL +# endif +# define machine_is_sgmsfl() (machine_arch_type == MACH_TYPE_SGMSFL) +#else +# define machine_is_sgmsfl() (0) +#endif + +#ifdef CONFIG_MACH_TT8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT8000 +# endif +# define machine_is_tt8000() (machine_arch_type == MACH_TYPE_TT8000) +#else +# define machine_is_tt8000() (0) +#endif + +#ifdef CONFIG_MACH_ZRN4300LP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZRN4300LP +# endif +# define machine_is_zrn4300lp() (machine_arch_type == MACH_TYPE_ZRN4300LP) +#else +# define machine_is_zrn4300lp() (0) +#endif + +#ifdef CONFIG_MACH_MPTC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPTC +# endif +# define machine_is_mptc() (machine_arch_type == MACH_TYPE_MPTC) +#else +# define machine_is_mptc() (0) +#endif + +#ifdef CONFIG_MACH_H6051 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6051 +# endif +# define machine_is_h6051() (machine_arch_type == MACH_TYPE_H6051) +#else +# define machine_is_h6051() (0) +#endif + +#ifdef CONFIG_MACH_PVG610_101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PVG610_101 +# endif +# define machine_is_pvg610_101() (machine_arch_type == MACH_TYPE_PVG610_101) +#else +# define machine_is_pvg610_101() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9261_PC_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9261_PC_EVB +# endif +# define machine_is_stamp9261_pc_evb() (machine_arch_type == MACH_TYPE_STAMP9261_PC_EVB) +#else +# define machine_is_stamp9261_pc_evb() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_ODYSSEUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_ODYSSEUS +# endif +# define machine_is_pelco_odysseus() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEUS) +#else +# define machine_is_pelco_odysseus() (0) +#endif + +#ifdef CONFIG_MACH_TNY_A9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_A9260 +# endif +# define machine_is_tny_a9260() (machine_arch_type == MACH_TYPE_TNY_A9260) +#else +# define machine_is_tny_a9260() (0) +#endif + +#ifdef CONFIG_MACH_TNY_A9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_A9G20 +# endif +# define machine_is_tny_a9g20() (machine_arch_type == MACH_TYPE_TNY_A9G20) +#else +# define machine_is_tny_a9g20() (0) +#endif + +#ifdef CONFIG_MACH_AESOP_MP2530F +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AESOP_MP2530F +# endif +# define machine_is_aesop_mp2530f() (machine_arch_type == MACH_TYPE_AESOP_MP2530F) +#else +# define machine_is_aesop_mp2530f() (0) +#endif + +#ifdef CONFIG_MACH_DX900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DX900 +# endif +# define machine_is_dx900() (machine_arch_type == MACH_TYPE_DX900) +#else +# define machine_is_dx900() (0) +#endif + +#ifdef CONFIG_MACH_CPODC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPODC2 +# endif +# define machine_is_cpodc2() (machine_arch_type == MACH_TYPE_CPODC2) +#else +# define machine_is_cpodc2() (0) +#endif + +#ifdef CONFIG_MACH_TILT_8925 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TILT_8925 +# endif +# define machine_is_tilt_8925() (machine_arch_type == MACH_TYPE_TILT_8925) +#else +# define machine_is_tilt_8925() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM357_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM357_EVM +# endif +# define machine_is_davinci_dm357_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM357_EVM) +#else +# define machine_is_davinci_dm357_evm() (0) +#endif + +#ifdef CONFIG_MACH_SWORDFISH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWORDFISH +# endif +# define machine_is_swordfish() (machine_arch_type == MACH_TYPE_SWORDFISH) +#else +# define machine_is_swordfish() (0) +#endif + +#ifdef CONFIG_MACH_CORVUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORVUS +# endif +# define machine_is_corvus() (machine_arch_type == MACH_TYPE_CORVUS) +#else +# define machine_is_corvus() (0) +#endif + +#ifdef CONFIG_MACH_TAURUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAURUS +# endif +# define machine_is_taurus() (machine_arch_type == MACH_TYPE_TAURUS) +#else +# define machine_is_taurus() (0) +#endif + +#ifdef CONFIG_MACH_AXM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXM +# endif +# define machine_is_axm() (machine_arch_type == MACH_TYPE_AXM) +#else +# define machine_is_axm() (0) +#endif + +#ifdef CONFIG_MACH_AXC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXC +# endif +# define machine_is_axc() (machine_arch_type == MACH_TYPE_AXC) +#else +# define machine_is_axc() (0) +#endif + +#ifdef CONFIG_MACH_BABY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BABY +# endif +# define machine_is_baby() (machine_arch_type == MACH_TYPE_BABY) +#else +# define machine_is_baby() (0) +#endif + +#ifdef CONFIG_MACH_MP200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP200 +# endif +# define machine_is_mp200() (machine_arch_type == MACH_TYPE_MP200) +#else +# define machine_is_mp200() (0) +#endif + +#ifdef CONFIG_MACH_PCM043 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM043 +# endif +# define machine_is_pcm043() (machine_arch_type == MACH_TYPE_PCM043) +#else +# define machine_is_pcm043() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V3C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V3C +# endif +# define machine_is_hanlin_v3c() (machine_arch_type == MACH_TYPE_HANLIN_V3C) +#else +# define machine_is_hanlin_v3c() (0) +#endif + +#ifdef CONFIG_MACH_KBK9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KBK9G20 +# endif +# define machine_is_kbk9g20() (machine_arch_type == MACH_TYPE_KBK9G20) +#else +# define machine_is_kbk9g20() (0) +#endif + +#ifdef CONFIG_MACH_ADSTURBOG5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSTURBOG5 +# endif +# define machine_is_adsturbog5() (machine_arch_type == MACH_TYPE_ADSTURBOG5) +#else +# define machine_is_adsturbog5() (0) +#endif + +#ifdef CONFIG_MACH_AVENGER_LITE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVENGER_LITE1 +# endif +# define machine_is_avenger_lite1() (machine_arch_type == MACH_TYPE_AVENGER_LITE1) +#else +# define machine_is_avenger_lite1() (0) +#endif + +#ifdef CONFIG_MACH_SUC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUC +# endif +# define machine_is_suc82x() (machine_arch_type == MACH_TYPE_SUC) +#else +# define machine_is_suc82x() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM7S256 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM7S256 +# endif +# define machine_is_at91sam7s256() (machine_arch_type == MACH_TYPE_AT91SAM7S256) +#else +# define machine_is_at91sam7s256() (0) +#endif + +#ifdef CONFIG_MACH_MENDOZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MENDOZA +# endif +# define machine_is_mendoza() (machine_arch_type == MACH_TYPE_MENDOZA) +#else +# define machine_is_mendoza() (0) +#endif + +#ifdef CONFIG_MACH_KIRA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIRA +# endif +# define machine_is_kira() (machine_arch_type == MACH_TYPE_KIRA) +#else +# define machine_is_kira() (0) +#endif + +#ifdef CONFIG_MACH_MX1HBM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX1HBM +# endif +# define machine_is_mx1hbm() (machine_arch_type == MACH_TYPE_MX1HBM) +#else +# define machine_is_mx1hbm() (0) +#endif + +#ifdef CONFIG_MACH_QUATRO43XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUATRO43XX +# endif +# define machine_is_quatro43xx() (machine_arch_type == MACH_TYPE_QUATRO43XX) +#else +# define machine_is_quatro43xx() (0) +#endif + +#ifdef CONFIG_MACH_QUATRO4230 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUATRO4230 +# endif +# define machine_is_quatro4230() (machine_arch_type == MACH_TYPE_QUATRO4230) +#else +# define machine_is_quatro4230() (0) +#endif + +#ifdef CONFIG_MACH_NSB400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB400 +# endif +# define machine_is_nsb400() (machine_arch_type == MACH_TYPE_NSB400) +#else +# define machine_is_nsb400() (0) +#endif + +#ifdef CONFIG_MACH_DRP255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DRP255 +# endif +# define machine_is_drp255() (machine_arch_type == MACH_TYPE_DRP255) +#else +# define machine_is_drp255() (0) +#endif + +#ifdef CONFIG_MACH_THOTH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_THOTH +# endif +# define machine_is_thoth() (machine_arch_type == MACH_TYPE_THOTH) +#else +# define machine_is_thoth() (0) +#endif + +#ifdef CONFIG_MACH_FIRESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FIRESTONE +# endif +# define machine_is_firestone() (machine_arch_type == MACH_TYPE_FIRESTONE) +#else +# define machine_is_firestone() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP750 +# endif +# define machine_is_asusp750() (machine_arch_type == MACH_TYPE_ASUSP750) +#else +# define machine_is_asusp750() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_DL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_DL +# endif +# define machine_is_ctera_dl() (machine_arch_type == MACH_TYPE_CTERA_DL) +#else +# define machine_is_ctera_dl() (0) +#endif + +#ifdef CONFIG_MACH_SOCR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOCR +# endif +# define machine_is_socr() (machine_arch_type == MACH_TYPE_SOCR) +#else +# define machine_is_socr() (0) +#endif + +#ifdef CONFIG_MACH_HTCOXYGEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCOXYGEN +# endif +# define machine_is_htcoxygen() (machine_arch_type == MACH_TYPE_HTCOXYGEN) +#else +# define machine_is_htcoxygen() (0) +#endif + +#ifdef CONFIG_MACH_HEROC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HEROC +# endif +# define machine_is_heroc() (machine_arch_type == MACH_TYPE_HEROC) +#else +# define machine_is_heroc() (0) +#endif + +#ifdef CONFIG_MACH_ZENO6800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZENO6800 +# endif +# define machine_is_zeno6800() (machine_arch_type == MACH_TYPE_ZENO6800) +#else +# define machine_is_zeno6800() (0) +#endif + +#ifdef CONFIG_MACH_SC2MCS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC2MCS +# endif +# define machine_is_sc2mcs() (machine_arch_type == MACH_TYPE_SC2MCS) +#else +# define machine_is_sc2mcs() (0) +#endif + +#ifdef CONFIG_MACH_GENE100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GENE100 +# endif +# define machine_is_gene100() (machine_arch_type == MACH_TYPE_GENE100) +#else +# define machine_is_gene100() (0) +#endif + +#ifdef CONFIG_MACH_AS353X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS353X +# endif +# define machine_is_as353x() (machine_arch_type == MACH_TYPE_AS353X) +#else +# define machine_is_as353x() (0) +#endif + +#ifdef CONFIG_MACH_SHEEVAPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHEEVAPLUG +# endif +# define machine_is_sheevaplug() (machine_arch_type == MACH_TYPE_SHEEVAPLUG) +#else +# define machine_is_sheevaplug() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20 +# endif +# define machine_is_at91sam9g20() (machine_arch_type == MACH_TYPE_AT91SAM9G20) +#else +# define machine_is_at91sam9g20() (0) +#endif + +#ifdef CONFIG_MACH_MV88F6192GTW_FE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV88F6192GTW_FE +# endif +# define machine_is_mv88f6192gtw_fe() (machine_arch_type == MACH_TYPE_MV88F6192GTW_FE) +#else +# define machine_is_mv88f6192gtw_fe() (0) +#endif + +#ifdef CONFIG_MACH_CC9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9200 +# endif +# define machine_is_cc9200() (machine_arch_type == MACH_TYPE_CC9200) +#else +# define machine_is_cc9200() (0) +#endif + +#ifdef CONFIG_MACH_SM9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SM9200 +# endif +# define machine_is_sm9200() (machine_arch_type == MACH_TYPE_SM9200) +#else +# define machine_is_sm9200() (0) +#endif + +#ifdef CONFIG_MACH_TP9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TP9200 +# endif +# define machine_is_tp9200() (machine_arch_type == MACH_TYPE_TP9200) +#else +# define machine_is_tp9200() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPERDV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPERDV +# endif +# define machine_is_snapperdv() (machine_arch_type == MACH_TYPE_SNAPPERDV) +#else +# define machine_is_snapperdv() (0) +#endif + +#ifdef CONFIG_MACH_AVENGERS_LITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVENGERS_LITE +# endif +# define machine_is_avengers_lite() (machine_arch_type == MACH_TYPE_AVENGERS_LITE) +#else +# define machine_is_avengers_lite() (0) +#endif + +#ifdef CONFIG_MACH_AVENGERS_LITE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVENGERS_LITE1 +# endif +# define machine_is_avengers_lite1() (machine_arch_type == MACH_TYPE_AVENGERS_LITE1) +#else +# define machine_is_avengers_lite1() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3AXON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3AXON +# endif +# define machine_is_omap3axon() (machine_arch_type == MACH_TYPE_OMAP3AXON) +#else +# define machine_is_omap3axon() (0) +#endif + +#ifdef CONFIG_MACH_MA8XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MA8XX +# endif +# define machine_is_ma8xx() (machine_arch_type == MACH_TYPE_MA8XX) +#else +# define machine_is_ma8xx() (0) +#endif + +#ifdef CONFIG_MACH_MP201EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP201EK +# endif +# define machine_is_mp201ek() (machine_arch_type == MACH_TYPE_MP201EK) +#else +# define machine_is_mp201ek() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_TUX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_TUX +# endif +# define machine_is_davinci_tux() (machine_arch_type == MACH_TYPE_DAVINCI_TUX) +#else +# define machine_is_davinci_tux() (0) +#endif + +#ifdef CONFIG_MACH_MPA1600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPA1600 +# endif +# define machine_is_mpa1600() (machine_arch_type == MACH_TYPE_MPA1600) +#else +# define machine_is_mpa1600() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_TROY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_TROY +# endif +# define machine_is_pelco_troy() (machine_arch_type == MACH_TYPE_PELCO_TROY) +#else +# define machine_is_pelco_troy() (0) +#endif + +#ifdef CONFIG_MACH_NSB667 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB667 +# endif +# define machine_is_nsb667() (machine_arch_type == MACH_TYPE_NSB667) +#else +# define machine_is_nsb667() (0) +#endif + +#ifdef CONFIG_MACH_ROVERS5_4MPIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERS5_4MPIX +# endif +# define machine_is_rovers5_4mpix() (machine_arch_type == MACH_TYPE_ROVERS5_4MPIX) +#else +# define machine_is_rovers5_4mpix() (0) +#endif + +#ifdef CONFIG_MACH_TWOCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TWOCOM +# endif +# define machine_is_twocom() (machine_arch_type == MACH_TYPE_TWOCOM) +#else +# define machine_is_twocom() (0) +#endif + +#ifdef CONFIG_MACH_UBISYS_P9_RCU3R2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UBISYS_P9_RCU3R2 +# endif +# define machine_is_ubisys_p9_rcu3r2() (machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3R2) +#else +# define machine_is_ubisys_p9_rcu3r2() (0) +#endif + +#ifdef CONFIG_MACH_HERO_ESPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERO_ESPRESSO +# endif +# define machine_is_hero_espresso() (machine_arch_type == MACH_TYPE_HERO_ESPRESSO) +#else +# define machine_is_hero_espresso() (0) +#endif + +#ifdef CONFIG_MACH_AFEUSB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AFEUSB +# endif +# define machine_is_afeusb() (machine_arch_type == MACH_TYPE_AFEUSB) +#else +# define machine_is_afeusb() (0) +#endif + +#ifdef CONFIG_MACH_T830 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T830 +# endif +# define machine_is_t830() (machine_arch_type == MACH_TYPE_T830) +#else +# define machine_is_t830() (0) +#endif + +#ifdef CONFIG_MACH_SPD8020_CC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPD8020_CC +# endif +# define machine_is_spd8020_cc() (machine_arch_type == MACH_TYPE_SPD8020_CC) +#else +# define machine_is_spd8020_cc() (0) +#endif + +#ifdef CONFIG_MACH_OM_3D7K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OM_3D7K +# endif +# define machine_is_om_3d7k() (machine_arch_type == MACH_TYPE_OM_3D7K) +#else +# define machine_is_om_3d7k() (0) +#endif + +#ifdef CONFIG_MACH_PICOCOM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOCOM2 +# endif +# define machine_is_picocom2() (machine_arch_type == MACH_TYPE_PICOCOM2) +#else +# define machine_is_picocom2() (0) +#endif + +#ifdef CONFIG_MACH_UWG4MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UWG4MX27 +# endif +# define machine_is_uwg4mx27() (machine_arch_type == MACH_TYPE_UWG4MX27) +#else +# define machine_is_uwg4mx27() (0) +#endif + +#ifdef CONFIG_MACH_UWG4MX31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UWG4MX31 +# endif +# define machine_is_uwg4mx31() (machine_arch_type == MACH_TYPE_UWG4MX31) +#else +# define machine_is_uwg4mx31() (0) +#endif + +#ifdef CONFIG_MACH_CHERRY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHERRY +# endif +# define machine_is_cherry() (machine_arch_type == MACH_TYPE_CHERRY) +#else +# define machine_is_cherry() (0) +#endif + +#ifdef CONFIG_MACH_MX51_BABBAGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_BABBAGE +# endif +# define machine_is_mx51_babbage() (machine_arch_type == MACH_TYPE_MX51_BABBAGE) +#else +# define machine_is_mx51_babbage() (0) +#endif + +#ifdef CONFIG_MACH_S3C2440TURKIYE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2440TURKIYE +# endif +# define machine_is_s3c2440turkiye() (machine_arch_type == MACH_TYPE_S3C2440TURKIYE) +#else +# define machine_is_s3c2440turkiye() (0) +#endif + +#ifdef CONFIG_MACH_TX37 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX37 +# endif +# define machine_is_tx37() (machine_arch_type == MACH_TYPE_TX37) +#else +# define machine_is_tx37() (0) +#endif + +#ifdef CONFIG_MACH_SBC2800_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC2800_9G20 +# endif +# define machine_is_sbc2800_9g20() (machine_arch_type == MACH_TYPE_SBC2800_9G20) +#else +# define machine_is_sbc2800_9g20() (0) +#endif + +#ifdef CONFIG_MACH_BENZGLB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZGLB +# endif +# define machine_is_benzglb() (machine_arch_type == MACH_TYPE_BENZGLB) +#else +# define machine_is_benzglb() (0) +#endif + +#ifdef CONFIG_MACH_BENZTD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZTD +# endif +# define machine_is_benztd() (machine_arch_type == MACH_TYPE_BENZTD) +#else +# define machine_is_benztd() (0) +#endif + +#ifdef CONFIG_MACH_CARTESIO_PLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARTESIO_PLUS +# endif +# define machine_is_cartesio_plus() (machine_arch_type == MACH_TYPE_CARTESIO_PLUS) +#else +# define machine_is_cartesio_plus() (0) +#endif + +#ifdef CONFIG_MACH_SOLRAD_G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOLRAD_G20 +# endif +# define machine_is_solrad_g20() (machine_arch_type == MACH_TYPE_SOLRAD_G20) +#else +# define machine_is_solrad_g20() (0) +#endif + +#ifdef CONFIG_MACH_MX27WALLACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27WALLACE +# endif +# define machine_is_mx27wallace() (machine_arch_type == MACH_TYPE_MX27WALLACE) +#else +# define machine_is_mx27wallace() (0) +#endif + +#ifdef CONFIG_MACH_FMZWEBMODUL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FMZWEBMODUL +# endif +# define machine_is_fmzwebmodul() (machine_arch_type == MACH_TYPE_FMZWEBMODUL) +#else +# define machine_is_fmzwebmodul() (0) +#endif + +#ifdef CONFIG_MACH_RD78X00_MASA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD78X00_MASA +# endif +# define machine_is_rd78x00_masa() (machine_arch_type == MACH_TYPE_RD78X00_MASA) +#else +# define machine_is_rd78x00_masa() (0) +#endif + +#ifdef CONFIG_MACH_SMALLOGGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMALLOGGER +# endif +# define machine_is_smallogger() (machine_arch_type == MACH_TYPE_SMALLOGGER) +#else +# define machine_is_smallogger() (0) +#endif + +#ifdef CONFIG_MACH_CCW9P9215 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9P9215 +# endif +# define machine_is_ccw9p9215() (machine_arch_type == MACH_TYPE_CCW9P9215) +#else +# define machine_is_ccw9p9215() (0) +#endif + +#ifdef CONFIG_MACH_DM355_LEOPARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM355_LEOPARD +# endif +# define machine_is_dm355_leopard() (machine_arch_type == MACH_TYPE_DM355_LEOPARD) +#else +# define machine_is_dm355_leopard() (0) +#endif + +#ifdef CONFIG_MACH_TS219 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS219 +# endif +# define machine_is_ts219() (machine_arch_type == MACH_TYPE_TS219) +#else +# define machine_is_ts219() (0) +#endif + +#ifdef CONFIG_MACH_TNY_A9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_A9263 +# endif +# define machine_is_tny_a9263() (machine_arch_type == MACH_TYPE_TNY_A9263) +#else +# define machine_is_tny_a9263() (0) +#endif + +#ifdef CONFIG_MACH_APOLLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APOLLO +# endif +# define machine_is_apollo() (machine_arch_type == MACH_TYPE_APOLLO) +#else +# define machine_is_apollo() (0) +#endif + +#ifdef CONFIG_MACH_AT91CAP9STK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91CAP9STK +# endif +# define machine_is_at91cap9stk() (machine_arch_type == MACH_TYPE_AT91CAP9STK) +#else +# define machine_is_at91cap9stk() (0) +#endif + +#ifdef CONFIG_MACH_SPC300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPC300 +# endif +# define machine_is_spc300() (machine_arch_type == MACH_TYPE_SPC300) +#else +# define machine_is_spc300() (0) +#endif + +#ifdef CONFIG_MACH_EKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EKO +# endif +# define machine_is_eko() (machine_arch_type == MACH_TYPE_EKO) +#else +# define machine_is_eko() (0) +#endif + +#ifdef CONFIG_MACH_CCW9M2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9M2443 +# endif +# define machine_is_ccw9m2443() (machine_arch_type == MACH_TYPE_CCW9M2443) +#else +# define machine_is_ccw9m2443() (0) +#endif + +#ifdef CONFIG_MACH_CCW9M2443JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9M2443JS +# endif +# define machine_is_ccw9m2443js() (machine_arch_type == MACH_TYPE_CCW9M2443JS) +#else +# define machine_is_ccw9m2443js() (0) +#endif + +#ifdef CONFIG_MACH_M2M_ROUTER_DEVICE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M2M_ROUTER_DEVICE +# endif +# define machine_is_m2m_router_device() (machine_arch_type == MACH_TYPE_M2M_ROUTER_DEVICE) +#else +# define machine_is_m2m_router_device() (0) +#endif + +#ifdef CONFIG_MACH_STAR9104NAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAR9104NAS +# endif +# define machine_is_str9104nas() (machine_arch_type == MACH_TYPE_STAR9104NAS) +#else +# define machine_is_str9104nas() (0) +#endif + +#ifdef CONFIG_MACH_PCA100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA100 +# endif +# define machine_is_pca100() (machine_arch_type == MACH_TYPE_PCA100) +#else +# define machine_is_pca100() (0) +#endif + +#ifdef CONFIG_MACH_Z3_DM365_MOD_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z3_DM365_MOD_01 +# endif +# define machine_is_z3_dm365_mod_01() (machine_arch_type == MACH_TYPE_Z3_DM365_MOD_01) +#else +# define machine_is_z3_dm365_mod_01() (0) +#endif + +#ifdef CONFIG_MACH_HIPOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIPOX +# endif +# define machine_is_hipox() (machine_arch_type == MACH_TYPE_HIPOX) +#else +# define machine_is_hipox() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PITEDS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PITEDS +# endif +# define machine_is_omap3_piteds() (machine_arch_type == MACH_TYPE_OMAP3_PITEDS) +#else +# define machine_is_omap3_piteds() (0) +#endif + +#ifdef CONFIG_MACH_BM150R +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BM150R +# endif +# define machine_is_bm150r() (machine_arch_type == MACH_TYPE_BM150R) +#else +# define machine_is_bm150r() (0) +#endif + +#ifdef CONFIG_MACH_TBONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TBONE +# endif +# define machine_is_tbone() (machine_arch_type == MACH_TYPE_TBONE) +#else +# define machine_is_tbone() (0) +#endif + +#ifdef CONFIG_MACH_MERLIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MERLIN +# endif +# define machine_is_merlin() (machine_arch_type == MACH_TYPE_MERLIN) +#else +# define machine_is_merlin() (0) +#endif + +#ifdef CONFIG_MACH_FALCON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FALCON +# endif +# define machine_is_falcon() (machine_arch_type == MACH_TYPE_FALCON) +#else +# define machine_is_falcon() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DA850_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DA850_EVM +# endif +# define machine_is_davinci_da850_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) +#else +# define machine_is_davinci_da850_evm() (0) +#endif + +#ifdef CONFIG_MACH_S5P6440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5P6440 +# endif +# define machine_is_s5p6440() (machine_arch_type == MACH_TYPE_S5P6440) +#else +# define machine_is_s5p6440() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G10EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G10EK +# endif +# define machine_is_at91sam9g10ek() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK) +#else +# define machine_is_at91sam9g10ek() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_4430SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_4430SDP +# endif +# define machine_is_omap_4430sdp() (machine_arch_type == MACH_TYPE_OMAP_4430SDP) +#else +# define machine_is_omap_4430sdp() (0) +#endif + +#ifdef CONFIG_MACH_LPC313X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC313X +# endif +# define machine_is_lpc313x() (machine_arch_type == MACH_TYPE_LPC313X) +#else +# define machine_is_lpc313x() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_ZN5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_ZN5 +# endif +# define machine_is_magx_zn5() (machine_arch_type == MACH_TYPE_MAGX_ZN5) +#else +# define machine_is_magx_zn5() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_EM30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_EM30 +# endif +# define machine_is_magx_em30() (machine_arch_type == MACH_TYPE_MAGX_EM30) +#else +# define machine_is_magx_em30() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_VE66 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_VE66 +# endif +# define machine_is_magx_ve66() (machine_arch_type == MACH_TYPE_MAGX_VE66) +#else +# define machine_is_magx_ve66() (0) +#endif + +#ifdef CONFIG_MACH_MEESC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEESC +# endif +# define machine_is_meesc() (machine_arch_type == MACH_TYPE_MEESC) +#else +# define machine_is_meesc() (0) +#endif + +#ifdef CONFIG_MACH_OTC570 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTC570 +# endif +# define machine_is_otc570() (machine_arch_type == MACH_TYPE_OTC570) +#else +# define machine_is_otc570() (0) +#endif + +#ifdef CONFIG_MACH_BCU2412 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCU2412 +# endif +# define machine_is_bcu2412() (machine_arch_type == MACH_TYPE_BCU2412) +#else +# define machine_is_bcu2412() (0) +#endif + +#ifdef CONFIG_MACH_BEACON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEACON +# endif +# define machine_is_beacon() (machine_arch_type == MACH_TYPE_BEACON) +#else +# define machine_is_beacon() (0) +#endif + +#ifdef CONFIG_MACH_ACTIA_TGW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTIA_TGW +# endif +# define machine_is_actia_tgw() (machine_arch_type == MACH_TYPE_ACTIA_TGW) +#else +# define machine_is_actia_tgw() (0) +#endif + +#ifdef CONFIG_MACH_E4430 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E4430 +# endif +# define machine_is_e4430() (machine_arch_type == MACH_TYPE_E4430) +#else +# define machine_is_e4430() (0) +#endif + +#ifdef CONFIG_MACH_QL300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QL300 +# endif +# define machine_is_ql300() (machine_arch_type == MACH_TYPE_QL300) +#else +# define machine_is_ql300() (0) +#endif + +#ifdef CONFIG_MACH_BTMAVB101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMAVB101 +# endif +# define machine_is_btmavb101() (machine_arch_type == MACH_TYPE_BTMAVB101) +#else +# define machine_is_btmavb101() (0) +#endif + +#ifdef CONFIG_MACH_BTMAWB101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMAWB101 +# endif +# define machine_is_btmawb101() (machine_arch_type == MACH_TYPE_BTMAWB101) +#else +# define machine_is_btmawb101() (0) +#endif + +#ifdef CONFIG_MACH_SQ201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SQ201 +# endif +# define machine_is_sq201() (machine_arch_type == MACH_TYPE_SQ201) +#else +# define machine_is_sq201() (0) +#endif + +#ifdef CONFIG_MACH_QUATRO45XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUATRO45XX +# endif +# define machine_is_quatro45xx() (machine_arch_type == MACH_TYPE_QUATRO45XX) +#else +# define machine_is_quatro45xx() (0) +#endif + +#ifdef CONFIG_MACH_OPENPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENPAD +# endif +# define machine_is_openpad() (machine_arch_type == MACH_TYPE_OPENPAD) +#else +# define machine_is_openpad() (0) +#endif + +#ifdef CONFIG_MACH_TX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX25 +# endif +# define machine_is_tx25() (machine_arch_type == MACH_TYPE_TX25) +#else +# define machine_is_tx25() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_TORPEDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_TORPEDO +# endif +# define machine_is_omap3_torpedo() (machine_arch_type == MACH_TYPE_OMAP3_TORPEDO) +#else +# define machine_is_omap3_torpedo() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL_K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL_K +# endif +# define machine_is_htcraphael_k() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_K) +#else +# define machine_is_htcraphael_k() (0) +#endif + +#ifdef CONFIG_MACH_LAL43 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LAL43 +# endif +# define machine_is_lal43() (machine_arch_type == MACH_TYPE_LAL43) +#else +# define machine_is_lal43() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA500 +# endif +# define machine_is_htcraphael_cdma500() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA500) +#else +# define machine_is_htcraphael_cdma500() (0) +#endif + +#ifdef CONFIG_MACH_ANW6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANW6410 +# endif +# define machine_is_anw6410() (machine_arch_type == MACH_TYPE_ANW6410) +#else +# define machine_is_anw6410() (0) +#endif + +#ifdef CONFIG_MACH_HTCPROPHET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPROPHET +# endif +# define machine_is_htcprophet() (machine_arch_type == MACH_TYPE_HTCPROPHET) +#else +# define machine_is_htcprophet() (0) +#endif + +#ifdef CONFIG_MACH_CFA_10022 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CFA_10022 +# endif +# define machine_is_cfa_10022() (machine_arch_type == MACH_TYPE_CFA_10022) +#else +# define machine_is_cfa_10022() (0) +#endif + +#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27_VISSTRIM_M10 +# endif +# define machine_is_imx27_visstrim_m10() (machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10) +#else +# define machine_is_imx27_visstrim_m10() (0) +#endif + +#ifdef CONFIG_MACH_PX2IMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PX2IMX27 +# endif +# define machine_is_px2imx27() (machine_arch_type == MACH_TYPE_PX2IMX27) +#else +# define machine_is_px2imx27() (0) +#endif + +#ifdef CONFIG_MACH_STM3210E_EVAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STM3210E_EVAL +# endif +# define machine_is_stm3210e_eval() (machine_arch_type == MACH_TYPE_STM3210E_EVAL) +#else +# define machine_is_stm3210e_eval() (0) +#endif + +#ifdef CONFIG_MACH_DVS10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DVS10 +# endif +# define machine_is_dvs10() (machine_arch_type == MACH_TYPE_DVS10) +#else +# define machine_is_dvs10() (0) +#endif + +#ifdef CONFIG_MACH_PORTUXG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PORTUXG20 +# endif +# define machine_is_portuxg20() (machine_arch_type == MACH_TYPE_PORTUXG20) +#else +# define machine_is_portuxg20() (0) +#endif + +#ifdef CONFIG_MACH_ARM_SPV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM_SPV +# endif +# define machine_is_arm_spv() (machine_arch_type == MACH_TYPE_ARM_SPV) +#else +# define machine_is_arm_spv() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC110 +# endif +# define machine_is_smdkc110() (machine_arch_type == MACH_TYPE_SMDKC110) +#else +# define machine_is_smdkc110() (0) +#endif + +#ifdef CONFIG_MACH_CABESPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CABESPRESSO +# endif +# define machine_is_cabespresso() (machine_arch_type == MACH_TYPE_CABESPRESSO) +#else +# define machine_is_cabespresso() (0) +#endif + +#ifdef CONFIG_MACH_HMC800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMC800 +# endif +# define machine_is_hmc800() (machine_arch_type == MACH_TYPE_HMC800) +#else +# define machine_is_hmc800() (0) +#endif + +#ifdef CONFIG_MACH_SHOLES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHOLES +# endif +# define machine_is_sholes() (machine_arch_type == MACH_TYPE_SHOLES) +#else +# define machine_is_sholes() (0) +#endif + +#ifdef CONFIG_MACH_BTMXC31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMXC31 +# endif +# define machine_is_btmxc31() (machine_arch_type == MACH_TYPE_BTMXC31) +#else +# define machine_is_btmxc31() (0) +#endif + +#ifdef CONFIG_MACH_DT501 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DT501 +# endif +# define machine_is_dt501() (machine_arch_type == MACH_TYPE_DT501) +#else +# define machine_is_dt501() (0) +#endif + +#ifdef CONFIG_MACH_KTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KTX +# endif +# define machine_is_ktx() (machine_arch_type == MACH_TYPE_KTX) +#else +# define machine_is_ktx() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3517EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3517EVM +# endif +# define machine_is_omap3517evm() (machine_arch_type == MACH_TYPE_OMAP3517EVM) +#else +# define machine_is_omap3517evm() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_V2 +# endif +# define machine_is_netspace_v2() (machine_arch_type == MACH_TYPE_NETSPACE_V2) +#else +# define machine_is_netspace_v2() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_MAX_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_MAX_V2 +# endif +# define machine_is_netspace_max_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2) +#else +# define machine_is_netspace_max_v2() (0) +#endif + +#ifdef CONFIG_MACH_D2NET_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D2NET_V2 +# endif +# define machine_is_d2net_v2() (machine_arch_type == MACH_TYPE_D2NET_V2) +#else +# define machine_is_d2net_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET2BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET2BIG_V2 +# endif +# define machine_is_net2big_v2() (machine_arch_type == MACH_TYPE_NET2BIG_V2) +#else +# define machine_is_net2big_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET4BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET4BIG_V2 +# endif +# define machine_is_net4big_v2() (machine_arch_type == MACH_TYPE_NET4BIG_V2) +#else +# define machine_is_net4big_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET5BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET5BIG_V2 +# endif +# define machine_is_net5big_v2() (machine_arch_type == MACH_TYPE_NET5BIG_V2) +#else +# define machine_is_net5big_v2() (0) +#endif + +#ifdef CONFIG_MACH_ENDB2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENDB2443 +# endif +# define machine_is_endb2443() (machine_arch_type == MACH_TYPE_ENDB2443) +#else +# define machine_is_endb2443() (0) +#endif + +#ifdef CONFIG_MACH_INETSPACE_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INETSPACE_V2 +# endif +# define machine_is_inetspace_v2() (machine_arch_type == MACH_TYPE_INETSPACE_V2) +#else +# define machine_is_inetspace_v2() (0) +#endif + +#ifdef CONFIG_MACH_TROS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TROS +# endif +# define machine_is_tros() (machine_arch_type == MACH_TYPE_TROS) +#else +# define machine_is_tros() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_HOMER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_HOMER +# endif +# define machine_is_pelco_homer() (machine_arch_type == MACH_TYPE_PELCO_HOMER) +#else +# define machine_is_pelco_homer() (0) +#endif + +#ifdef CONFIG_MACH_OFSP8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OFSP8 +# endif +# define machine_is_ofsp8() (machine_arch_type == MACH_TYPE_OFSP8) +#else +# define machine_is_ofsp8() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G45EKES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G45EKES +# endif +# define machine_is_at91sam9g45ekes() (machine_arch_type == MACH_TYPE_AT91SAM9G45EKES) +#else +# define machine_is_at91sam9g45ekes() (0) +#endif + +#ifdef CONFIG_MACH_GUF_CUPID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUF_CUPID +# endif +# define machine_is_guf_cupid() (machine_arch_type == MACH_TYPE_GUF_CUPID) +#else +# define machine_is_guf_cupid() (0) +#endif + +#ifdef CONFIG_MACH_EAB1R +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EAB1R +# endif +# define machine_is_eab1r() (machine_arch_type == MACH_TYPE_EAB1R) +#else +# define machine_is_eab1r() (0) +#endif + +#ifdef CONFIG_MACH_DESIREC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DESIREC +# endif +# define machine_is_desirec() (machine_arch_type == MACH_TYPE_DESIREC) +#else +# define machine_is_desirec() (0) +#endif + +#ifdef CONFIG_MACH_CORDOBA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORDOBA +# endif +# define machine_is_cordoba() (machine_arch_type == MACH_TYPE_CORDOBA) +#else +# define machine_is_cordoba() (0) +#endif + +#ifdef CONFIG_MACH_IRVINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IRVINE +# endif +# define machine_is_irvine() (machine_arch_type == MACH_TYPE_IRVINE) +#else +# define machine_is_irvine() (0) +#endif + +#ifdef CONFIG_MACH_SFF772 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SFF772 +# endif +# define machine_is_sff772() (machine_arch_type == MACH_TYPE_SFF772) +#else +# define machine_is_sff772() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_MILANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_MILANO +# endif +# define machine_is_pelco_milano() (machine_arch_type == MACH_TYPE_PELCO_MILANO) +#else +# define machine_is_pelco_milano() (0) +#endif + +#ifdef CONFIG_MACH_PC7302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7302 +# endif +# define machine_is_pc7302() (machine_arch_type == MACH_TYPE_PC7302) +#else +# define machine_is_pc7302() (0) +#endif + +#ifdef CONFIG_MACH_BIP6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIP6000 +# endif +# define machine_is_bip6000() (machine_arch_type == MACH_TYPE_BIP6000) +#else +# define machine_is_bip6000() (0) +#endif + +#ifdef CONFIG_MACH_SILVERMOON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SILVERMOON +# endif +# define machine_is_silvermoon() (machine_arch_type == MACH_TYPE_SILVERMOON) +#else +# define machine_is_silvermoon() (0) +#endif + +#ifdef CONFIG_MACH_VC0830 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC0830 +# endif +# define machine_is_vc0830() (machine_arch_type == MACH_TYPE_VC0830) +#else +# define machine_is_vc0830() (0) +#endif + +#ifdef CONFIG_MACH_DT430 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DT430 +# endif +# define machine_is_dt430() (machine_arch_type == MACH_TYPE_DT430) +#else +# define machine_is_dt430() (0) +#endif + +#ifdef CONFIG_MACH_JI42PF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JI42PF +# endif +# define machine_is_ji42pf() (machine_arch_type == MACH_TYPE_JI42PF) +#else +# define machine_is_ji42pf() (0) +#endif + +#ifdef CONFIG_MACH_GNET_KSM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_KSM +# endif +# define machine_is_gnet_ksm() (machine_arch_type == MACH_TYPE_GNET_KSM) +#else +# define machine_is_gnet_ksm() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGM +# endif +# define machine_is_gnet_sgm() (machine_arch_type == MACH_TYPE_GNET_SGM) +#else +# define machine_is_gnet_sgm() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGR +# endif +# define machine_is_gnet_sgr() (machine_arch_type == MACH_TYPE_GNET_SGR) +#else +# define machine_is_gnet_sgr() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_ICETEKEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_ICETEKEVM +# endif +# define machine_is_omap3_icetekevm() (machine_arch_type == MACH_TYPE_OMAP3_ICETEKEVM) +#else +# define machine_is_omap3_icetekevm() (0) +#endif + +#ifdef CONFIG_MACH_PNP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNP +# endif +# define machine_is_pnp() (machine_arch_type == MACH_TYPE_PNP) +#else +# define machine_is_pnp() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_K +# endif +# define machine_is_ctera_2bay_k() (machine_arch_type == MACH_TYPE_CTERA_2BAY_K) +#else +# define machine_is_ctera_2bay_k() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_U +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_U +# endif +# define machine_is_ctera_2bay_u() (machine_arch_type == MACH_TYPE_CTERA_2BAY_U) +#else +# define machine_is_ctera_2bay_u() (0) +#endif + +#ifdef CONFIG_MACH_SAS_C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAS_C +# endif +# define machine_is_sas_c() (machine_arch_type == MACH_TYPE_SAS_C) +#else +# define machine_is_sas_c() (0) +#endif + +#ifdef CONFIG_MACH_VMA2315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMA2315 +# endif +# define machine_is_vma2315() (machine_arch_type == MACH_TYPE_VMA2315) +#else +# define machine_is_vma2315() (0) +#endif + +#ifdef CONFIG_MACH_VCS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VCS +# endif +# define machine_is_vcs() (machine_arch_type == MACH_TYPE_VCS) +#else +# define machine_is_vcs() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR600 +# endif +# define machine_is_spear600() (machine_arch_type == MACH_TYPE_SPEAR600) +#else +# define machine_is_spear600() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR300 +# endif +# define machine_is_spear300() (machine_arch_type == MACH_TYPE_SPEAR300) +#else +# define machine_is_spear300() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR1300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR1300 +# endif +# define machine_is_spear1300() (machine_arch_type == MACH_TYPE_SPEAR1300) +#else +# define machine_is_spear1300() (0) +#endif + +#ifdef CONFIG_MACH_LILLY1131 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LILLY1131 +# endif +# define machine_is_lilly1131() (machine_arch_type == MACH_TYPE_LILLY1131) +#else +# define machine_is_lilly1131() (0) +#endif + +#ifdef CONFIG_MACH_ARVOO_AX301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARVOO_AX301 +# endif +# define machine_is_arvoo_ax301() (machine_arch_type == MACH_TYPE_ARVOO_AX301) +#else +# define machine_is_arvoo_ax301() (0) +#endif + +#ifdef CONFIG_MACH_MAPPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAPPHONE +# endif +# define machine_is_mapphone() (machine_arch_type == MACH_TYPE_MAPPHONE) +#else +# define machine_is_mapphone() (0) +#endif + +#ifdef CONFIG_MACH_LEGEND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEGEND +# endif +# define machine_is_legend() (machine_arch_type == MACH_TYPE_LEGEND) +#else +# define machine_is_legend() (0) +#endif + +#ifdef CONFIG_MACH_SALSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SALSA +# endif +# define machine_is_salsa() (machine_arch_type == MACH_TYPE_SALSA) +#else +# define machine_is_salsa() (0) +#endif + +#ifdef CONFIG_MACH_LOUNGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOUNGE +# endif +# define machine_is_lounge() (machine_arch_type == MACH_TYPE_LOUNGE) +#else +# define machine_is_lounge() (0) +#endif + +#ifdef CONFIG_MACH_VISION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VISION +# endif +# define machine_is_vision() (machine_arch_type == MACH_TYPE_VISION) +#else +# define machine_is_vision() (0) +#endif + +#ifdef CONFIG_MACH_VMB20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMB20 +# endif +# define machine_is_vmb20() (machine_arch_type == MACH_TYPE_VMB20) +#else +# define machine_is_vmb20() (0) +#endif + +#ifdef CONFIG_MACH_HY2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY2410 +# endif +# define machine_is_hy2410() (machine_arch_type == MACH_TYPE_HY2410) +#else +# define machine_is_hy2410() (0) +#endif + +#ifdef CONFIG_MACH_HY9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9315 +# endif +# define machine_is_hy9315() (machine_arch_type == MACH_TYPE_HY9315) +#else +# define machine_is_hy9315() (0) +#endif + +#ifdef CONFIG_MACH_BULLWINKLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BULLWINKLE +# endif +# define machine_is_bullwinkle() (machine_arch_type == MACH_TYPE_BULLWINKLE) +#else +# define machine_is_bullwinkle() (0) +#endif + +#ifdef CONFIG_MACH_ARM_ULTIMATOR2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM_ULTIMATOR2 +# endif +# define machine_is_arm_ultimator2() (machine_arch_type == MACH_TYPE_ARM_ULTIMATOR2) +#else +# define machine_is_arm_ultimator2() (0) +#endif + +#ifdef CONFIG_MACH_VS_V210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VS_V210 +# endif +# define machine_is_vs_v210() (machine_arch_type == MACH_TYPE_VS_V210) +#else +# define machine_is_vs_v210() (0) +#endif + +#ifdef CONFIG_MACH_VS_V212 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VS_V212 +# endif +# define machine_is_vs_v212() (machine_arch_type == MACH_TYPE_VS_V212) +#else +# define machine_is_vs_v212() (0) +#endif + +#ifdef CONFIG_MACH_HMT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMT +# endif +# define machine_is_hmt() (machine_arch_type == MACH_TYPE_HMT) +#else +# define machine_is_hmt() (0) +#endif + +#ifdef CONFIG_MACH_SUEN3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUEN3 +# endif +# define machine_is_suen3() (machine_arch_type == MACH_TYPE_SUEN3) +#else +# define machine_is_suen3() (0) +#endif + +#ifdef CONFIG_MACH_VESPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VESPER +# endif +# define machine_is_vesper() (machine_arch_type == MACH_TYPE_VESPER) +#else +# define machine_is_vesper() (0) +#endif + +#ifdef CONFIG_MACH_STR9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR9 +# endif +# define machine_is_str9() (machine_arch_type == MACH_TYPE_STR9) +#else +# define machine_is_str9() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_WL_FF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_WL_FF +# endif +# define machine_is_omap3_wl_ff() (machine_arch_type == MACH_TYPE_OMAP3_WL_FF) +#else +# define machine_is_omap3_wl_ff() (0) +#endif + +#ifdef CONFIG_MACH_SIMCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMCOM +# endif +# define machine_is_simcom() (machine_arch_type == MACH_TYPE_SIMCOM) +#else +# define machine_is_simcom() (0) +#endif + +#ifdef CONFIG_MACH_MCWEBIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCWEBIO +# endif +# define machine_is_mcwebio() (machine_arch_type == MACH_TYPE_MCWEBIO) +#else +# define machine_is_mcwebio() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PHRAZER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PHRAZER +# endif +# define machine_is_omap3_phrazer() (machine_arch_type == MACH_TYPE_OMAP3_PHRAZER) +#else +# define machine_is_omap3_phrazer() (0) +#endif + +#ifdef CONFIG_MACH_DARWIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DARWIN +# endif +# define machine_is_darwin() (machine_arch_type == MACH_TYPE_DARWIN) +#else +# define machine_is_darwin() (0) +#endif + +#ifdef CONFIG_MACH_ORATISCOMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISCOMU +# endif +# define machine_is_oratiscomu() (machine_arch_type == MACH_TYPE_ORATISCOMU) +#else +# define machine_is_oratiscomu() (0) +#endif + +#ifdef CONFIG_MACH_RTSBC20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTSBC20 +# endif +# define machine_is_rtsbc20() (machine_arch_type == MACH_TYPE_RTSBC20) +#else +# define machine_is_rtsbc20() (0) +#endif + +#ifdef CONFIG_MACH_I780 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I780 +# endif +# define machine_is_sgh_i780() (machine_arch_type == MACH_TYPE_I780) +#else +# define machine_is_sgh_i780() (0) +#endif + +#ifdef CONFIG_MACH_GEMINI324 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMINI324 +# endif +# define machine_is_gemini324() (machine_arch_type == MACH_TYPE_GEMINI324) +#else +# define machine_is_gemini324() (0) +#endif + +#ifdef CONFIG_MACH_ORATISLAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISLAN +# endif +# define machine_is_oratislan() (machine_arch_type == MACH_TYPE_ORATISLAN) +#else +# define machine_is_oratislan() (0) +#endif + +#ifdef CONFIG_MACH_ORATISALOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISALOG +# endif +# define machine_is_oratisalog() (machine_arch_type == MACH_TYPE_ORATISALOG) +#else +# define machine_is_oratisalog() (0) +#endif + +#ifdef CONFIG_MACH_ORATISMADI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISMADI +# endif +# define machine_is_oratismadi() (machine_arch_type == MACH_TYPE_ORATISMADI) +#else +# define machine_is_oratismadi() (0) +#endif + +#ifdef CONFIG_MACH_ORATISOT16 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISOT16 +# endif +# define machine_is_oratisot16() (machine_arch_type == MACH_TYPE_ORATISOT16) +#else +# define machine_is_oratisot16() (0) +#endif + +#ifdef CONFIG_MACH_ORATISDESK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISDESK +# endif +# define machine_is_oratisdesk() (machine_arch_type == MACH_TYPE_ORATISDESK) +#else +# define machine_is_oratisdesk() (0) +#endif + +#ifdef CONFIG_MACH_VEXPRESS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VEXPRESS +# endif +# define machine_is_vexpress() (machine_arch_type == MACH_TYPE_VEXPRESS) +#else +# define machine_is_vexpress() (0) +#endif + +#ifdef CONFIG_MACH_SINTEXO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SINTEXO +# endif +# define machine_is_sintexo() (machine_arch_type == MACH_TYPE_SINTEXO) +#else +# define machine_is_sintexo() (0) +#endif + +#ifdef CONFIG_MACH_CM3389 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM3389 +# endif +# define machine_is_cm3389() (machine_arch_type == MACH_TYPE_CM3389) +#else +# define machine_is_cm3389() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CIO +# endif +# define machine_is_omap3_cio() (machine_arch_type == MACH_TYPE_OMAP3_CIO) +#else +# define machine_is_omap3_cio() (0) +#endif + +#ifdef CONFIG_MACH_SGH_I900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGH_I900 +# endif +# define machine_is_sgh_i900() (machine_arch_type == MACH_TYPE_SGH_I900) +#else +# define machine_is_sgh_i900() (0) +#endif + +#ifdef CONFIG_MACH_BST100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BST100 +# endif +# define machine_is_bst100() (machine_arch_type == MACH_TYPE_BST100) +#else +# define machine_is_bst100() (0) +#endif + +#ifdef CONFIG_MACH_PASSION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSION +# endif +# define machine_is_passion() (machine_arch_type == MACH_TYPE_PASSION) +#else +# define machine_is_passion() (0) +#endif + +#ifdef CONFIG_MACH_INDESIGN_AT91SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INDESIGN_AT91SAM +# endif +# define machine_is_indesign_at91sam() (machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM) +#else +# define machine_is_indesign_at91sam() (0) +#endif + +#ifdef CONFIG_MACH_C4_BADGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_BADGER +# endif +# define machine_is_c4_badger() (machine_arch_type == MACH_TYPE_C4_BADGER) +#else +# define machine_is_c4_badger() (0) +#endif + +#ifdef CONFIG_MACH_C4_VIPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_VIPER +# endif +# define machine_is_c4_viper() (machine_arch_type == MACH_TYPE_C4_VIPER) +#else +# define machine_is_c4_viper() (0) +#endif + +#ifdef CONFIG_MACH_D2NET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D2NET +# endif +# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET) +#else +# define machine_is_d2net() (0) +#endif + +#ifdef CONFIG_MACH_BIGDISK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIGDISK +# endif +# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK) +#else +# define machine_is_bigdisk() (0) +#endif + +#ifdef CONFIG_MACH_NOTALVISION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOTALVISION +# endif +# define machine_is_notalvision() (machine_arch_type == MACH_TYPE_NOTALVISION) +#else +# define machine_is_notalvision() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_KBOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_KBOC +# endif +# define machine_is_omap3_kboc() (machine_arch_type == MACH_TYPE_OMAP3_KBOC) +#else +# define machine_is_omap3_kboc() (0) +#endif + +#ifdef CONFIG_MACH_CYCLONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYCLONE +# endif +# define machine_is_cyclone() (machine_arch_type == MACH_TYPE_CYCLONE) +#else +# define machine_is_cyclone() (0) +#endif + +#ifdef CONFIG_MACH_NINJA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NINJA +# endif +# define machine_is_ninja() (machine_arch_type == MACH_TYPE_NINJA) +#else +# define machine_is_ninja() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC +# endif +# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC) +#else +# define machine_is_at91sam9g20ek_2mmc() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING +# endif +# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING) +#else +# define machine_is_bcmring() (0) +#endif + +#ifdef CONFIG_MACH_RESOL_DL2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RESOL_DL2 +# endif +# define machine_is_resol_dl2() (machine_arch_type == MACH_TYPE_RESOL_DL2) +#else +# define machine_is_resol_dl2() (0) +#endif + +#ifdef CONFIG_MACH_IFOSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IFOSW +# endif +# define machine_is_ifosw() (machine_arch_type == MACH_TYPE_IFOSW) +#else +# define machine_is_ifosw() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUM +# endif +# define machine_is_htcrhodium() (machine_arch_type == MACH_TYPE_HTCRHODIUM) +#else +# define machine_is_htcrhodium() (0) +#endif + +#ifdef CONFIG_MACH_HTCTOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTOPAZ +# endif +# define machine_is_htctopaz() (machine_arch_type == MACH_TYPE_HTCTOPAZ) +#else +# define machine_is_htctopaz() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX504 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX504 +# endif +# define machine_is_matrix504() (machine_arch_type == MACH_TYPE_MATRIX504) +#else +# define machine_is_matrix504() (0) +#endif + +#ifdef CONFIG_MACH_MRFSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MRFSA +# endif +# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA) +#else +# define machine_is_mrfsa() (0) +#endif + +#ifdef CONFIG_MACH_SC_P270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC_P270 +# endif +# define machine_is_sc_p270() (machine_arch_type == MACH_TYPE_SC_P270) +#else +# define machine_is_sc_p270() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS5_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS5_EVB +# endif +# define machine_is_atlas5_evb() (machine_arch_type == MACH_TYPE_ATLAS5_EVB) +#else +# define machine_is_atlas5_evb() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LOBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LOBOX +# endif +# define machine_is_pelco_lobox() (machine_arch_type == MACH_TYPE_PELCO_LOBOX) +#else +# define machine_is_pelco_lobox() (0) +#endif + +#ifdef CONFIG_MACH_DILAX_PCU200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DILAX_PCU200 +# endif +# define machine_is_dilax_pcu200() (machine_arch_type == MACH_TYPE_DILAX_PCU200) +#else +# define machine_is_dilax_pcu200() (0) +#endif + +#ifdef CONFIG_MACH_LEONARDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEONARDO +# endif +# define machine_is_leonardo() (machine_arch_type == MACH_TYPE_LEONARDO) +#else +# define machine_is_leonardo() (0) +#endif + +#ifdef CONFIG_MACH_ZORAN_APPROACH7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZORAN_APPROACH7 +# endif +# define machine_is_zoran_approach7() (machine_arch_type == MACH_TYPE_ZORAN_APPROACH7) +#else +# define machine_is_zoran_approach7() (0) +#endif + +#ifdef CONFIG_MACH_DP6XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DP6XX +# endif +# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX) +#else +# define machine_is_dp6xx() (0) +#endif + +#ifdef CONFIG_MACH_BCM2153_VESPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM2153_VESPER +# endif +# define machine_is_bcm2153_vesper() (machine_arch_type == MACH_TYPE_BCM2153_VESPER) +#else +# define machine_is_bcm2153_vesper() (0) +#endif + +#ifdef CONFIG_MACH_MAHIMAHI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAHIMAHI +# endif +# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI) +#else +# define machine_is_mahimahi() (0) +#endif + +#ifdef CONFIG_MACH_CLICKC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLICKC +# endif +# define machine_is_clickc() (machine_arch_type == MACH_TYPE_CLICKC) +#else +# define machine_is_clickc() (0) +#endif + +#ifdef CONFIG_MACH_ZB_GATEWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZB_GATEWAY +# endif +# define machine_is_zb_gateway() (machine_arch_type == MACH_TYPE_ZB_GATEWAY) +#else +# define machine_is_zb_gateway() (0) +#endif + +#ifdef CONFIG_MACH_TAZCARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZCARD +# endif +# define machine_is_tazcard() (machine_arch_type == MACH_TYPE_TAZCARD) +#else +# define machine_is_tazcard() (0) +#endif + +#ifdef CONFIG_MACH_TAZDEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZDEV +# endif +# define machine_is_tazdev() (machine_arch_type == MACH_TYPE_TAZDEV) +#else +# define machine_is_tazdev() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_CB_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_CB_ARM +# endif +# define machine_is_annax_cb_arm() (machine_arch_type == MACH_TYPE_ANNAX_CB_ARM) +#else +# define machine_is_annax_cb_arm() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_DM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_DM3 +# endif +# define machine_is_annax_dm3() (machine_arch_type == MACH_TYPE_ANNAX_DM3) +#else +# define machine_is_annax_dm3() (0) +#endif + +#ifdef CONFIG_MACH_CEREBRIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEREBRIC +# endif +# define machine_is_cerebric() (machine_arch_type == MACH_TYPE_CEREBRIC) +#else +# define machine_is_cerebric() (0) +#endif + +#ifdef CONFIG_MACH_ORCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORCA +# endif +# define machine_is_orca() (machine_arch_type == MACH_TYPE_ORCA) +#else +# define machine_is_orca() (0) +#endif + +#ifdef CONFIG_MACH_PC9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC9260 +# endif +# define machine_is_pc9260() (machine_arch_type == MACH_TYPE_PC9260) +#else +# define machine_is_pc9260() (0) +#endif + +#ifdef CONFIG_MACH_EMS285A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMS285A +# endif +# define machine_is_ems285a() (machine_arch_type == MACH_TYPE_EMS285A) +#else +# define machine_is_ems285a() (0) +#endif + +#ifdef CONFIG_MACH_GEC2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2410 +# endif +# define machine_is_gec2410() (machine_arch_type == MACH_TYPE_GEC2410) +#else +# define machine_is_gec2410() (0) +#endif + +#ifdef CONFIG_MACH_GEC2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2440 +# endif +# define machine_is_gec2440() (machine_arch_type == MACH_TYPE_GEC2440) +#else +# define machine_is_gec2440() (0) +#endif + +#ifdef CONFIG_MACH_ARCH_MW903 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCH_MW903 +# endif +# define machine_is_mw903() (machine_arch_type == MACH_TYPE_ARCH_MW903) +#else +# define machine_is_mw903() (0) +#endif + +#ifdef CONFIG_MACH_MW2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW2440 +# endif +# define machine_is_mw2440() (machine_arch_type == MACH_TYPE_MW2440) +#else +# define machine_is_mw2440() (0) +#endif + +#ifdef CONFIG_MACH_ECAC2378 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECAC2378 +# endif +# define machine_is_ecac2378() (machine_arch_type == MACH_TYPE_ECAC2378) +#else +# define machine_is_ecac2378() (0) +#endif + +#ifdef CONFIG_MACH_TAZKIOSK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZKIOSK +# endif +# define machine_is_tazkiosk() (machine_arch_type == MACH_TYPE_TAZKIOSK) +#else +# define machine_is_tazkiosk() (0) +#endif + +#ifdef CONFIG_MACH_WHITERABBIT_MCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITERABBIT_MCH +# endif +# define machine_is_whiterabbit_mch() (machine_arch_type == MACH_TYPE_WHITERABBIT_MCH) +#else +# define machine_is_whiterabbit_mch() (0) +#endif + +#ifdef CONFIG_MACH_SBOX9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBOX9263 +# endif +# define machine_is_sbox9263() (machine_arch_type == MACH_TYPE_SBOX9263) +#else +# define machine_is_sbox9263() (0) +#endif + +#ifdef CONFIG_MACH_OREO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO +# endif +# define machine_is_oreo_camera() (machine_arch_type == MACH_TYPE_OREO) +#else +# define machine_is_oreo_camera() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6442 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6442 +# endif +# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442) +#else +# define machine_is_smdk6442() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_BASE +# endif +# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) +#else +# define machine_is_openrd_base() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLE +# endif +# define machine_is_incredible() (machine_arch_type == MACH_TYPE_INCREDIBLE) +#else +# define machine_is_incredible() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLEC +# endif +# define machine_is_incrediblec() (machine_arch_type == MACH_TYPE_INCREDIBLEC) +#else +# define machine_is_incrediblec() (0) +#endif + +#ifdef CONFIG_MACH_HEROCT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HEROCT +# endif +# define machine_is_heroct() (machine_arch_type == MACH_TYPE_HEROCT) +#else +# define machine_is_heroct() (0) +#endif + +#ifdef CONFIG_MACH_MMNET1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMNET1000 +# endif +# define machine_is_mmnet1000() (machine_arch_type == MACH_TYPE_MMNET1000) +#else +# define machine_is_mmnet1000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT8000 +# endif +# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000) +#else +# define machine_is_devkit8000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT9000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT9000 +# endif +# define machine_is_devkit9000() (machine_arch_type == MACH_TYPE_DEVKIT9000) +#else +# define machine_is_devkit9000() (0) +#endif + +#ifdef CONFIG_MACH_MX31TXTR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31TXTR +# endif +# define machine_is_mx31txtr() (machine_arch_type == MACH_TYPE_MX31TXTR) +#else +# define machine_is_mx31txtr() (0) +#endif + +#ifdef CONFIG_MACH_U380 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U380 +# endif +# define machine_is_u380() (machine_arch_type == MACH_TYPE_U380) +#else +# define machine_is_u380() (0) +#endif + +#ifdef CONFIG_MACH_HUALU_BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUALU_BOARD +# endif +# define machine_is_oamp3_hualu() (machine_arch_type == MACH_TYPE_HUALU_BOARD) +#else +# define machine_is_oamp3_hualu() (0) +#endif + +#ifdef CONFIG_MACH_NPCMX50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NPCMX50 +# endif +# define machine_is_npcmx50() (machine_arch_type == MACH_TYPE_NPCMX50) +#else +# define machine_is_npcmx50() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE51 +# endif +# define machine_is_mx51_lange51() (machine_arch_type == MACH_TYPE_MX51_LANGE51) +#else +# define machine_is_mx51_lange51() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE52 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE52 +# endif +# define machine_is_mx51_lange52() (machine_arch_type == MACH_TYPE_MX51_LANGE52) +#else +# define machine_is_mx51_lange52() (0) +#endif + +#ifdef CONFIG_MACH_RIOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOM +# endif +# define machine_is_riom() (machine_arch_type == MACH_TYPE_RIOM) +#else +# define machine_is_riom() (0) +#endif + +#ifdef CONFIG_MACH_COMCAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMCAS +# endif +# define machine_is_comcas() (machine_arch_type == MACH_TYPE_COMCAS) +#else +# define machine_is_comcas() (0) +#endif + +#ifdef CONFIG_MACH_WSI_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WSI_MX27 +# endif +# define machine_is_wsi_mx27() (machine_arch_type == MACH_TYPE_WSI_MX27) +#else +# define machine_is_wsi_mx27() (0) +#endif + +#ifdef CONFIG_MACH_CM_T35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T35 +# endif +# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35) +#else +# define machine_is_cm_t35() (0) +#endif + +#ifdef CONFIG_MACH_NET2BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET2BIG +# endif +# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG) +#else +# define machine_is_net2big() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_A1600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_A1600 +# endif +# define machine_is_motorola_a1600() (machine_arch_type == MACH_TYPE_MOTOROLA_A1600) +#else +# define machine_is_motorola_a1600() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0020 +# endif +# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020) +#else +# define machine_is_igep0020() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0010 +# endif +# define machine_is_igep0010() (machine_arch_type == MACH_TYPE_IGEP0010) +#else +# define machine_is_igep0010() (0) +#endif + +#ifdef CONFIG_MACH_MV6281GTWGE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV6281GTWGE2 +# endif +# define machine_is_mv6281gtwge2() (machine_arch_type == MACH_TYPE_MV6281GTWGE2) +#else +# define machine_is_mv6281gtwge2() (0) +#endif + +#ifdef CONFIG_MACH_SCAT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT100 +# endif +# define machine_is_scat100() (machine_arch_type == MACH_TYPE_SCAT100) +#else +# define machine_is_scat100() (0) +#endif + +#ifdef CONFIG_MACH_SANMINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANMINA +# endif +# define machine_is_sanmina() (machine_arch_type == MACH_TYPE_SANMINA) +#else +# define machine_is_sanmina() (0) +#endif + +#ifdef CONFIG_MACH_MOMENTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOMENTO +# endif +# define machine_is_momento() (machine_arch_type == MACH_TYPE_MOMENTO) +#else +# define machine_is_momento() (0) +#endif + +#ifdef CONFIG_MACH_NUC9XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC9XX +# endif +# define machine_is_nuc9xx() (machine_arch_type == MACH_TYPE_NUC9XX) +#else +# define machine_is_nuc9xx() (0) +#endif + +#ifdef CONFIG_MACH_NUC910EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC910EVB +# endif +# define machine_is_nuc910evb() (machine_arch_type == MACH_TYPE_NUC910EVB) +#else +# define machine_is_nuc910evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC920EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC920EVB +# endif +# define machine_is_nuc920evb() (machine_arch_type == MACH_TYPE_NUC920EVB) +#else +# define machine_is_nuc920evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC950EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC950EVB +# endif +# define machine_is_nuc950evb() (machine_arch_type == MACH_TYPE_NUC950EVB) +#else +# define machine_is_nuc950evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC945EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC945EVB +# endif +# define machine_is_nuc945evb() (machine_arch_type == MACH_TYPE_NUC945EVB) +#else +# define machine_is_nuc945evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC960EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC960EVB +# endif +# define machine_is_nuc960evb() (machine_arch_type == MACH_TYPE_NUC960EVB) +#else +# define machine_is_nuc960evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC932EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC932EVB +# endif +# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB) +#else +# define machine_is_nuc932evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC900 +# endif +# define machine_is_nuc900() (machine_arch_type == MACH_TYPE_NUC900) +#else +# define machine_is_nuc900() (0) +#endif + +#ifdef CONFIG_MACH_SD1SOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SD1SOC +# endif +# define machine_is_sd1soc() (machine_arch_type == MACH_TYPE_SD1SOC) +#else +# define machine_is_sd1soc() (0) +#endif + +#ifdef CONFIG_MACH_LN2440BC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LN2440BC +# endif +# define machine_is_ln2440bc() (machine_arch_type == MACH_TYPE_LN2440BC) +#else +# define machine_is_ln2440bc() (0) +#endif + +#ifdef CONFIG_MACH_RSBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSBC +# endif +# define machine_is_rsbc() (machine_arch_type == MACH_TYPE_RSBC) +#else +# define machine_is_rsbc() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_CLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_CLIENT +# endif +# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT) +#else +# define machine_is_openrd_client() (0) +#endif + +#ifdef CONFIG_MACH_HPIPAQ11X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPIPAQ11X +# endif +# define machine_is_hpipaq11x() (machine_arch_type == MACH_TYPE_HPIPAQ11X) +#else +# define machine_is_hpipaq11x() (0) +#endif + +#ifdef CONFIG_MACH_WAYLAND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WAYLAND +# endif +# define machine_is_wayland() (machine_arch_type == MACH_TYPE_WAYLAND) +#else +# define machine_is_wayland() (0) +#endif + +#ifdef CONFIG_MACH_ACNBSX102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACNBSX102 +# endif +# define machine_is_acnbsx102() (machine_arch_type == MACH_TYPE_ACNBSX102) +#else +# define machine_is_acnbsx102() (0) +#endif + +#ifdef CONFIG_MACH_HWAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HWAT91 +# endif +# define machine_is_hwat91() (machine_arch_type == MACH_TYPE_HWAT91) +#else +# define machine_is_hwat91() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263CS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263CS +# endif +# define machine_is_at91sam9263cs() (machine_arch_type == MACH_TYPE_AT91SAM9263CS) +#else +# define machine_is_at91sam9263cs() (0) +#endif + +#ifdef CONFIG_MACH_CSB732 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB732 +# endif +# define machine_is_csb732() (machine_arch_type == MACH_TYPE_CSB732) +#else +# define machine_is_csb732() (0) +#endif + +#ifdef CONFIG_MACH_U8500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U8500 +# endif +# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) +#else +# define machine_is_u8500() (0) +#endif + +#ifdef CONFIG_MACH_HUQIU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUQIU +# endif +# define machine_is_huqiu() (machine_arch_type == MACH_TYPE_HUQIU) +#else +# define machine_is_huqiu() (0) +#endif + +#ifdef CONFIG_MACH_MX51_KUNLUN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_KUNLUN +# endif +# define machine_is_mx51_kunlun() (machine_arch_type == MACH_TYPE_MX51_KUNLUN) +#else +# define machine_is_mx51_kunlun() (0) +#endif + +#ifdef CONFIG_MACH_PMT1G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMT1G +# endif +# define machine_is_pmt1g() (machine_arch_type == MACH_TYPE_PMT1G) +#else +# define machine_is_pmt1g() (0) +#endif + +#ifdef CONFIG_MACH_HTCELF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCELF +# endif +# define machine_is_htcelf() (machine_arch_type == MACH_TYPE_HTCELF) +#else +# define machine_is_htcelf() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO420 +# endif +# define machine_is_armadillo420() (machine_arch_type == MACH_TYPE_ARMADILLO420) +#else +# define machine_is_armadillo420() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO440 +# endif +# define machine_is_armadillo440() (machine_arch_type == MACH_TYPE_ARMADILLO440) +#else +# define machine_is_armadillo440() (0) +#endif + +#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U_CHIP_DUAL_ARM +# endif +# define machine_is_u_chip_dual_arm() (machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM) +#else +# define machine_is_u_chip_dual_arm() (0) +#endif + +#ifdef CONFIG_MACH_CSR_BDB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSR_BDB3 +# endif +# define machine_is_csr_bdb3() (machine_arch_type == MACH_TYPE_CSR_BDB3) +#else +# define machine_is_csr_bdb3() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1018 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1018 +# endif +# define machine_is_dolby_cat1018() (machine_arch_type == MACH_TYPE_DOLBY_CAT1018) +#else +# define machine_is_dolby_cat1018() (0) +#endif + +#ifdef CONFIG_MACH_HY9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9307 +# endif +# define machine_is_hy9307() (machine_arch_type == MACH_TYPE_HY9307) +#else +# define machine_is_hy9307() (0) +#endif + +#ifdef CONFIG_MACH_A_ES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A_ES +# endif +# define machine_is_aspire_easystore() (machine_arch_type == MACH_TYPE_A_ES) +#else +# define machine_is_aspire_easystore() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_IRIF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_IRIF +# endif +# define machine_is_davinci_irif() (machine_arch_type == MACH_TYPE_DAVINCI_IRIF) +#else +# define machine_is_davinci_irif() (0) +#endif + +#ifdef CONFIG_MACH_AGAMA9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AGAMA9263 +# endif +# define machine_is_agama9263() (machine_arch_type == MACH_TYPE_AGAMA9263) +#else +# define machine_is_agama9263() (0) +#endif + +#ifdef CONFIG_MACH_MARVELL_JASPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVELL_JASPER +# endif +# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER) +#else +# define machine_is_marvell_jasper() (0) +#endif + +#ifdef CONFIG_MACH_FLINT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLINT +# endif +# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT) +#else +# define machine_is_flint() (0) +#endif + +#ifdef CONFIG_MACH_TAVOREVB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAVOREVB3 +# endif +# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3) +#else +# define machine_is_tavorevb3() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M490 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M490 +# endif +# define machine_is_sch_m490() (machine_arch_type == MACH_TYPE_SCH_M490) +#else +# define machine_is_sch_m490() (0) +#endif + +#ifdef CONFIG_MACH_RBL01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RBL01 +# endif +# define machine_is_rbl01() (machine_arch_type == MACH_TYPE_RBL01) +#else +# define machine_is_rbl01() (0) +#endif + +#ifdef CONFIG_MACH_OMNIFI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMNIFI +# endif +# define machine_is_omnifi() (machine_arch_type == MACH_TYPE_OMNIFI) +#else +# define machine_is_omnifi() (0) +#endif + +#ifdef CONFIG_MACH_OTAVALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTAVALO +# endif +# define machine_is_otavalo() (machine_arch_type == MACH_TYPE_OTAVALO) +#else +# define machine_is_otavalo() (0) +#endif + +#ifdef CONFIG_MACH_SIENNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIENNA +# endif +# define machine_is_siena() (machine_arch_type == MACH_TYPE_SIENNA) +#else +# define machine_is_siena() (0) +#endif + +#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_EXCALIBUR_S620 +# endif +# define machine_is_htc_excalibur_s620() (machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620) +#else +# define machine_is_htc_excalibur_s620() (0) +#endif + +#ifdef CONFIG_MACH_HTC_OPAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_OPAL +# endif +# define machine_is_htc_opal() (machine_arch_type == MACH_TYPE_HTC_OPAL) +#else +# define machine_is_htc_opal() (0) +#endif + +#ifdef CONFIG_MACH_TOUCHBOOK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOUCHBOOK +# endif +# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK) +#else +# define machine_is_touchbook() (0) +#endif + +#ifdef CONFIG_MACH_LATTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LATTE +# endif +# define machine_is_latte() (machine_arch_type == MACH_TYPE_LATTE) +#else +# define machine_is_latte() (0) +#endif + +#ifdef CONFIG_MACH_XA200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XA200 +# endif +# define machine_is_xa200() (machine_arch_type == MACH_TYPE_XA200) +#else +# define machine_is_xa200() (0) +#endif + +#ifdef CONFIG_MACH_NIMROD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMROD +# endif +# define machine_is_nimrod() (machine_arch_type == MACH_TYPE_NIMROD) +#else +# define machine_is_nimrod() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3G +# endif +# define machine_is_cc9p9215_3g() (machine_arch_type == MACH_TYPE_CC9P9215_3G) +#else +# define machine_is_cc9p9215_3g() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3GJS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3GJS +# endif +# define machine_is_cc9p9215_3gjs() (machine_arch_type == MACH_TYPE_CC9P9215_3GJS) +#else +# define machine_is_cc9p9215_3gjs() (0) +#endif + +#ifdef CONFIG_MACH_TK71 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TK71 +# endif +# define machine_is_tk71() (machine_arch_type == MACH_TYPE_TK71) +#else +# define machine_is_tk71() (0) +#endif + +#ifdef CONFIG_MACH_COMHAM3525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMHAM3525 +# endif +# define machine_is_comham3525() (machine_arch_type == MACH_TYPE_COMHAM3525) +#else +# define machine_is_comham3525() (0) +#endif + +#ifdef CONFIG_MACH_MX31EREBUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31EREBUS +# endif +# define machine_is_mx31erebus() (machine_arch_type == MACH_TYPE_MX31EREBUS) +#else +# define machine_is_mx31erebus() (0) +#endif + +#ifdef CONFIG_MACH_MCARDMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCARDMX27 +# endif +# define machine_is_mcardmx27() (machine_arch_type == MACH_TYPE_MCARDMX27) +#else +# define machine_is_mcardmx27() (0) +#endif + +#ifdef CONFIG_MACH_PARADISE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PARADISE +# endif +# define machine_is_paradise() (machine_arch_type == MACH_TYPE_PARADISE) +#else +# define machine_is_paradise() (0) +#endif + +#ifdef CONFIG_MACH_TIDE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIDE +# endif +# define machine_is_tide() (machine_arch_type == MACH_TYPE_TIDE) +#else +# define machine_is_tide() (0) +#endif + +#ifdef CONFIG_MACH_WZL2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL2440 +# endif +# define machine_is_wzl2440() (machine_arch_type == MACH_TYPE_WZL2440) +#else +# define machine_is_wzl2440() (0) +#endif + +#ifdef CONFIG_MACH_SDRDEMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SDRDEMO +# endif +# define machine_is_sdrdemo() (machine_arch_type == MACH_TYPE_SDRDEMO) +#else +# define machine_is_sdrdemo() (0) +#endif + +#ifdef CONFIG_MACH_ETHERCAN2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERCAN2 +# endif +# define machine_is_ethercan2() (machine_arch_type == MACH_TYPE_ETHERCAN2) +#else +# define machine_is_ethercan2() (0) +#endif + +#ifdef CONFIG_MACH_ECMIMG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECMIMG20 +# endif +# define machine_is_ecmimg20() (machine_arch_type == MACH_TYPE_ECMIMG20) +#else +# define machine_is_ecmimg20() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_DRAGON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_DRAGON +# endif +# define machine_is_omap_dragon() (machine_arch_type == MACH_TYPE_OMAP_DRAGON) +#else +# define machine_is_omap_dragon() (0) +#endif + +#ifdef CONFIG_MACH_HALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HALO +# endif +# define machine_is_halo() (machine_arch_type == MACH_TYPE_HALO) +#else +# define machine_is_halo() (0) +#endif + +#ifdef CONFIG_MACH_HUANGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUANGSHAN +# endif +# define machine_is_huangshan() (machine_arch_type == MACH_TYPE_HUANGSHAN) +#else +# define machine_is_huangshan() (0) +#endif + +#ifdef CONFIG_MACH_VL_MA2SC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VL_MA2SC +# endif +# define machine_is_vl_ma2sc() (machine_arch_type == MACH_TYPE_VL_MA2SC) +#else +# define machine_is_vl_ma2sc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_RC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_RC +# endif +# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC) +#else +# define machine_is_raumfeld_rc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR +# endif +# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR) +#else +# define machine_is_raumfeld_connector() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_SPEAKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER +# endif +# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER) +#else +# define machine_is_raumfeld_speaker() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_MASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_MASTER +# endif +# define machine_is_multibus_master() (machine_arch_type == MACH_TYPE_MULTIBUS_MASTER) +#else +# define machine_is_multibus_master() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_PBK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_PBK +# endif +# define machine_is_multibus_pbk() (machine_arch_type == MACH_TYPE_MULTIBUS_PBK) +#else +# define machine_is_multibus_pbk() (0) +#endif + +#ifdef CONFIG_MACH_TNETV107X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNETV107X +# endif +# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X) +#else +# define machine_is_tnetv107x() (0) +#endif + +#ifdef CONFIG_MACH_SNAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAKE +# endif +# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE) +#else +# define machine_is_snake() (0) +#endif + +#ifdef CONFIG_MACH_CWMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWMX27 +# endif +# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27) +#else +# define machine_is_cwmx27() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M480 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M480 +# endif +# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480) +#else +# define machine_is_sch_m480() (0) +#endif + +#ifdef CONFIG_MACH_PLATYPUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLATYPUS +# endif +# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS) +#else +# define machine_is_platypus() (0) +#endif + +#ifdef CONFIG_MACH_PSS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PSS2 +# endif +# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2) +#else +# define machine_is_pss2() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_APM150 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_APM150 +# endif +# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150) +#else +# define machine_is_davinci_apm150() (0) +#endif + +#ifdef CONFIG_MACH_STR9100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR9100 +# endif +# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100) +#else +# define machine_is_str9100() (0) +#endif + +#ifdef CONFIG_MACH_NET5BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET5BIG +# endif +# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG) +#else +# define machine_is_net5big() (0) +#endif + +#ifdef CONFIG_MACH_SEABED9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEABED9263 +# endif +# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263) +#else +# define machine_is_seabed9263() (0) +#endif + +#ifdef CONFIG_MACH_MX51_M2ID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_M2ID +# endif +# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID) +#else +# define machine_is_mx51_m2id() (0) +#endif + +#ifdef CONFIG_MACH_OCTVOCPLUS_EB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB +# endif +# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB) +#else +# define machine_is_octvocplus_eb() (0) +#endif + +#ifdef CONFIG_MACH_KLK_FIREFOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_FIREFOX +# endif +# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX) +#else +# define machine_is_klk_firefox() (0) +#endif + +#ifdef CONFIG_MACH_KLK_WIRMA_MODULE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE +# endif +# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE) +#else +# define machine_is_klk_wirma_module() (0) +#endif + +#ifdef CONFIG_MACH_KLK_WIRMA_MMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI +# endif +# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI) +#else +# define machine_is_klk_wirma_mmi() (0) +#endif + +#ifdef CONFIG_MACH_SUPERSONIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUPERSONIC +# endif +# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC) +#else +# define machine_is_supersonic() (0) +#endif + +#ifdef CONFIG_MACH_LIBERTY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIBERTY +# endif +# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY) +#else +# define machine_is_liberty() (0) +#endif + +#ifdef CONFIG_MACH_MH355 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MH355 +# endif +# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355) +#else +# define machine_is_mh355() (0) +#endif + +#ifdef CONFIG_MACH_PC7802 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7802 +# endif +# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802) +#else +# define machine_is_pc7802() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGC +# endif +# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC) +#else +# define machine_is_gnet_sgc() (0) +#endif + +#ifdef CONFIG_MACH_EINSTEIN15 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EINSTEIN15 +# endif +# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15) +#else +# define machine_is_einstein15() (0) +#endif + +#ifdef CONFIG_MACH_CMPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMPD +# endif +# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD) +#else +# define machine_is_cmpd() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_HASE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_HASE1 +# endif +# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1) +#else +# define machine_is_davinci_hase1() (0) +#endif + +#ifdef CONFIG_MACH_LGEINCITEPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LGEINCITEPHONE +# endif +# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE) +#else +# define machine_is_lgeincitephone() (0) +#endif + +#ifdef CONFIG_MACH_EA313X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA313X +# endif +# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X) +#else +# define machine_is_ea313x() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_39064 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_39064 +# endif +# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064) +#else +# define machine_is_fwbd_39064() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_390128 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_390128 +# endif +# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128) +#else +# define machine_is_fwbd_390128() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_MOE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_MOE +# endif +# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE) +#else +# define machine_is_pelco_moe() (0) +#endif + +#ifdef CONFIG_MACH_MINIMIX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIMIX27 +# endif +# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27) +#else +# define machine_is_minimix27() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_THUNDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_THUNDER +# endif +# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER) +#else +# define machine_is_omap3_thunder() (0) +#endif + +#ifdef CONFIG_MACH_PASSIONC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSIONC +# endif +# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC) +#else +# define machine_is_passionc() (0) +#endif + +#ifdef CONFIG_MACH_MX27AMATA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27AMATA +# endif +# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA) +#else +# define machine_is_mx27amata() (0) +#endif + +#ifdef CONFIG_MACH_BGAT1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BGAT1 +# endif +# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1) +#else +# define machine_is_bgat1() (0) +#endif + +#ifdef CONFIG_MACH_BUZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUZZ +# endif +# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ) +#else +# define machine_is_buzz() (0) +#endif + +#ifdef CONFIG_MACH_MB9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9G20 +# endif +# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20) +#else +# define machine_is_mb9g20() (0) +#endif + +#ifdef CONFIG_MACH_YUSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YUSHAN +# endif +# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN) +#else +# define machine_is_yushan() (0) +#endif + +#ifdef CONFIG_MACH_LIZARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIZARD +# endif +# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD) +#else +# define machine_is_lizard() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3POLYCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3POLYCOM +# endif +# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM) +#else +# define machine_is_omap3polycom() (0) +#endif + +#ifdef CONFIG_MACH_SMDKV210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKV210 +# endif +# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210) +#else +# define machine_is_smdkv210() (0) +#endif + +#ifdef CONFIG_MACH_BRAVO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRAVO +# endif +# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO) +#else +# define machine_is_bravo() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO1 +# endif +# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1) +#else +# define machine_is_siogentoo1() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO2 +# endif +# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2) +#else +# define machine_is_siogentoo2() (0) +#endif + +#ifdef CONFIG_MACH_SM3K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SM3K +# endif +# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K) +#else +# define machine_is_sm3k() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_F900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900 +# endif +# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900) +#else +# define machine_is_acer_tempo_f900() (0) +#endif + +#ifdef CONFIG_MACH_SST61VC010_DEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SST61VC010_DEV +# endif +# define machine_is_sst61vc010_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV) +#else +# define machine_is_sst61vc010_dev() (0) +#endif + +#ifdef CONFIG_MACH_GLITTERTIND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLITTERTIND +# endif +# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND) +#else +# define machine_is_glittertind() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_ZOOM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_ZOOM3 +# endif +# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3) +#else +# define machine_is_omap_zoom3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_3630SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_3630SDP +# endif +# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP) +#else +# define machine_is_omap_3630sdp() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK2440 +# endif +# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440) +#else +# define machine_is_cybook2440() (0) +#endif + +#ifdef CONFIG_MACH_TORINO_S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TORINO_S +# endif +# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S) +#else +# define machine_is_torino_s() (0) +#endif + +#ifdef CONFIG_MACH_HAVANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAVANA +# endif +# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA) +#else +# define machine_is_havana() (0) +#endif + +#ifdef CONFIG_MACH_BEAUMONT_11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEAUMONT_11 +# endif +# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11) +#else +# define machine_is_beaumont_11() (0) +#endif + +#ifdef CONFIG_MACH_VANGUARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VANGUARD +# endif +# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD) +#else +# define machine_is_vanguard() (0) +#endif + +#ifdef CONFIG_MACH_S5PC110_DRACO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC110_DRACO +# endif +# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO) +#else +# define machine_is_s5pc110_draco() (0) +#endif + +#ifdef CONFIG_MACH_CARTESIO_TWO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARTESIO_TWO +# endif +# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO) +#else +# define machine_is_cartesio_two() (0) +#endif + +#ifdef CONFIG_MACH_ASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASTER +# endif +# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER) +#else +# define machine_is_aster() (0) +#endif + +#ifdef CONFIG_MACH_VOGUESV210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOGUESV210 +# endif +# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210) +#else +# define machine_is_voguesv210() (0) +#endif + +#ifdef CONFIG_MACH_ACM500X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACM500X +# endif +# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X) +#else +# define machine_is_acm500x() (0) +#endif + +#ifdef CONFIG_MACH_KM9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KM9260 +# endif +# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260) +#else +# define machine_is_km9260() (0) +#endif + +#ifdef CONFIG_MACH_NIDEFLEXG1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIDEFLEXG1 +# endif +# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1) +#else +# define machine_is_nideflexg1() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_PLUG_IO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO +# endif +# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO) +#else +# define machine_is_ctera_plug_io() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQ7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQ7 +# endif +# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7) +#else +# define machine_is_smartq7() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G10EK2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2 +# endif +# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2) +#else +# define machine_is_at91sam9g10ek2() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP527 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP527 +# endif +# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527) +#else +# define machine_is_asusp527() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20MPM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2 +# endif +# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2) +#else +# define machine_is_at91sam9g20mpm2() (0) +#endif + +#ifdef CONFIG_MACH_TOPASA900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPASA900 +# endif +# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900) +#else +# define machine_is_topasa900() (0) +#endif + +#ifdef CONFIG_MACH_ELECTRUM_100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELECTRUM_100 +# endif +# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100) +#else +# define machine_is_electrum_100() (0) +#endif + +#ifdef CONFIG_MACH_MX51GRB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51GRB +# endif +# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB) +#else +# define machine_is_mx51grb() (0) +#endif + +#ifdef CONFIG_MACH_XEA300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XEA300 +# endif +# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300) +#else +# define machine_is_xea300() (0) +#endif + +#ifdef CONFIG_MACH_HTCSTARTREK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCSTARTREK +# endif +# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK) +#else +# define machine_is_htcstartrek() (0) +#endif + +#ifdef CONFIG_MACH_LIMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIMA +# endif +# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA) +#else +# define machine_is_lima() (0) +#endif + +#ifdef CONFIG_MACH_CSB740 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB740 +# endif +# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740) +#else +# define machine_is_csb740() (0) +#endif + +#ifdef CONFIG_MACH_USB_S8815 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_S8815 +# endif +# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815) +#else +# define machine_is_usb_s8815() (0) +#endif + +#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN +# endif +# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN) +#else +# define machine_is_watson_efm_plugin() (0) +#endif + +#ifdef CONFIG_MACH_MILKYWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILKYWAY +# endif +# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY) +#else +# define machine_is_milkyway() (0) +#endif + +#ifdef CONFIG_MACH_G4EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G4EVM +# endif +# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM) +#else +# define machine_is_g4evm() (0) +#endif + +#ifdef CONFIG_MACH_PICOMOD6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOMOD6 +# endif +# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6) +#else +# define machine_is_picomod6() (0) +#endif + +#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD +# endif +# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD) +#else +# define machine_is_omapl138_hawkboard() (0) +#endif + +#ifdef CONFIG_MACH_IP6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP6000 +# endif +# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000) +#else +# define machine_is_ip6000() (0) +#endif + +#ifdef CONFIG_MACH_IP6010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP6010 +# endif +# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010) +#else +# define machine_is_ip6010() (0) +#endif + +#ifdef CONFIG_MACH_UTM400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UTM400 +# endif +# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400) +#else +# define machine_is_utm400() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_ZYBEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX +# endif +# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX) +#else +# define machine_is_omap3_zybex() (0) +#endif + +#ifdef CONFIG_MACH_WIRELESS_SPACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WIRELESS_SPACE +# endif +# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE) +#else +# define machine_is_wireless_space() (0) +#endif + +#ifdef CONFIG_MACH_SX560 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SX560 +# endif +# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560) +#else +# define machine_is_sx560() (0) +#endif + +#ifdef CONFIG_MACH_TS41X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS41X +# endif +# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X) +#else +# define machine_is_ts41x() (0) +#endif + +#ifdef CONFIG_MACH_ELPHEL10373 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELPHEL10373 +# endif +# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373) +#else +# define machine_is_elphel10373() (0) +#endif + +#ifdef CONFIG_MACH_RHOBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RHOBOT +# endif +# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT) +#else +# define machine_is_rhobot() (0) +#endif + +#ifdef CONFIG_MACH_MX51_REFRESH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_REFRESH +# endif +# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH) +#else +# define machine_is_mx51_refresh() (0) +#endif + +#ifdef CONFIG_MACH_LS9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LS9260 +# endif +# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260) +#else +# define machine_is_ls9260() (0) +#endif + +#ifdef CONFIG_MACH_SHANK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHANK +# endif +# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK) +#else +# define machine_is_shank() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_ST1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_ST1 +# endif +# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1) +#else +# define machine_is_qsd8x50_st1() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9M10EKES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES +# endif +# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES) +#else +# define machine_is_at91sam9m10ekes() (0) +#endif + +#ifdef CONFIG_MACH_HIRAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIRAM +# endif +# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM) +#else +# define machine_is_hiram() (0) +#endif + +#ifdef CONFIG_MACH_PHY3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHY3250 +# endif +# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250) +#else +# define machine_is_phy3250() (0) +#endif + +#ifdef CONFIG_MACH_EA3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA3250 +# endif +# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250) +#else +# define machine_is_ea3250() (0) +#endif + +#ifdef CONFIG_MACH_FDI3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FDI3250 +# endif +# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250) +#else +# define machine_is_fdi3250() (0) +#endif + +#ifdef CONFIG_MACH_WHITESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITESTONE +# endif +# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) +#else +# define machine_is_whitestone() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263NIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263NIT +# endif +# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT) +#else +# define machine_is_at91sam9263nit() (0) +#endif + +#ifdef CONFIG_MACH_CCMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCMX51 +# endif +# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51) +#else +# define machine_is_ccmx51() (0) +#endif + +#ifdef CONFIG_MACH_CCMX51JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCMX51JS +# endif +# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS) +#else +# define machine_is_ccmx51js() (0) +#endif + +#ifdef CONFIG_MACH_CCWMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCWMX51 +# endif +# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51) +#else +# define machine_is_ccwmx51() (0) +#endif + +#ifdef CONFIG_MACH_CCWMX51JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCWMX51JS +# endif +# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS) +#else +# define machine_is_ccwmx51js() (0) +#endif + +#ifdef CONFIG_MACH_MINI6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI6410 +# endif +# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410) +#else +# define machine_is_mini6410() (0) +#endif + +#ifdef CONFIG_MACH_TINY6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINY6410 +# endif +# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410) +#else +# define machine_is_tiny6410() (0) +#endif + +#ifdef CONFIG_MACH_NANO6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANO6410 +# endif +# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410) +#else +# define machine_is_nano6410() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940HFNLDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940HFNLDB +# endif +# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB) +#else +# define machine_is_at572d940hfnldb() (0) +#endif + +#ifdef CONFIG_MACH_HTCLEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCLEO +# endif +# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO) +#else +# define machine_is_htcleo() (0) +#endif + +#ifdef CONFIG_MACH_AVP13 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVP13 +# endif +# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13) +#else +# define machine_is_avp13() (0) +#endif + +#ifdef CONFIG_MACH_XXSVIDEOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XXSVIDEOD +# endif +# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD) +#else +# define machine_is_xxsvideod() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT +# endif +# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT) +#else +# define machine_is_vpnext() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_ITC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_ITC3 +# endif +# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3) +#else +# define machine_is_swarco_itc3() (0) +#endif + +#ifdef CONFIG_MACH_TX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX51 +# endif +# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51) +#else +# define machine_is_tx51() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1021 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1021 +# endif +# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021) +#else +# define machine_is_dolby_cat1021() (0) +#endif + +#ifdef CONFIG_MACH_MX28EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX28EVK +# endif +# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK) +#else +# define machine_is_mx28evk() (0) +#endif + +#ifdef CONFIG_MACH_PHOENIX260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHOENIX260 +# endif +# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260) +#else +# define machine_is_phoenix260() (0) +#endif + +#ifdef CONFIG_MACH_UVACA_STORK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UVACA_STORK +# endif +# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK) +#else +# define machine_is_uvaca_stork() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQ5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQ5 +# endif +# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5) +#else +# define machine_is_smartq5() (0) +#endif + +#ifdef CONFIG_MACH_ALL3078 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALL3078 +# endif +# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078) +#else +# define machine_is_all3078() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS +# endif +# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS) +#else +# define machine_is_ctera_2bay_ds() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO3 +# endif +# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3) +#else +# define machine_is_siogentoo3() (0) +#endif + +#ifdef CONFIG_MACH_EPB5000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPB5000 +# endif +# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000) +#else +# define machine_is_epb5000() (0) +#endif + +#ifdef CONFIG_MACH_HY9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9263 +# endif +# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263) +#else +# define machine_is_hy9263() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_M900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900 +# endif +# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900) +#else +# define machine_is_acer_tempo_m900() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_DX900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900 +# endif +# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900) +#else +# define machine_is_acer_tempo_dx650() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_X960 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960 +# endif +# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960) +#else +# define machine_is_acer_tempo_x960() (0) +#endif + +#ifdef CONFIG_MACH_ACER_ETEN_V900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_ETEN_V900 +# endif +# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900) +#else +# define machine_is_acer_eten_v900() (0) +#endif + +#ifdef CONFIG_MACH_ACER_ETEN_X900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_ETEN_X900 +# endif +# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900) +#else +# define machine_is_acer_eten_x900() (0) +#endif + +#ifdef CONFIG_MACH_BONNELL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BONNELL +# endif +# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL) +#else +# define machine_is_bonnell() (0) +#endif + +#ifdef CONFIG_MACH_OHT_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OHT_MX27 +# endif +# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27) +#else +# define machine_is_oht_mx27() (0) +#endif + +#ifdef CONFIG_MACH_HTCQUARTZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCQUARTZ +# endif +# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ) +#else +# define machine_is_htcquartz() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM +# endif +# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM) +#else +# define machine_is_davinci_dm6467tevm() (0) +#endif + +#ifdef CONFIG_MACH_C3AX03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C3AX03 +# endif +# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03) +#else +# define machine_is_c3ax03() (0) +#endif + +#ifdef CONFIG_MACH_MXT_TD60 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXT_TD60 +# endif +# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60) +#else +# define machine_is_mxt_td60() (0) +#endif + +#ifdef CONFIG_MACH_ESYX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESYX +# endif +# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX) +#else +# define machine_is_esyx() (0) +#endif + +#ifdef CONFIG_MACH_DOVE_DB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_DB2 +# endif +# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB2) +#else +# define machine_is_dove_db2() (0) +#endif + +#ifdef CONFIG_MACH_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BULLDOG +# endif +# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG) +#else +# define machine_is_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_DERELL_ME2000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DERELL_ME2000 +# endif +# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000) +#else +# define machine_is_derell_me2000() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_BASE +# endif +# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE) +#else +# define machine_is_bcmring_base() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM +# endif +# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM) +#else +# define machine_is_bcmring_evm() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ +# endif +# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ) +#else +# define machine_is_bcmring_evm_jazz() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SP +# endif +# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP) +#else +# define machine_is_bcmring_sp() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SV +# endif +# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV) +#else +# define machine_is_bcmring_sv() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SV_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ +# endif +# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ) +#else +# define machine_is_bcmring_sv_jazz() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_TABLET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_TABLET +# endif +# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET) +#else +# define machine_is_bcmring_tablet() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_VP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_VP +# endif +# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP) +#else +# define machine_is_bcmring_vp() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR +# endif +# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR) +#else +# define machine_is_bcmring_evm_seikor() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SP_WQVGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA +# endif +# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA) +#else +# define machine_is_bcmring_sp_wqvga() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_CUSTOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM +# endif +# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM) +#else +# define machine_is_bcmring_custom() (0) +#endif + +#ifdef CONFIG_MACH_ACER_S200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_S200 +# endif +# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200) +#else +# define machine_is_acer_s200() (0) +#endif + +#ifdef CONFIG_MACH_BT270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BT270 +# endif +# define machine_is_bt270() (machine_arch_type == MACH_TYPE_BT270) +#else +# define machine_is_bt270() (0) +#endif + +#ifdef CONFIG_MACH_ISEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ISEO +# endif +# define machine_is_iseo() (machine_arch_type == MACH_TYPE_ISEO) +#else +# define machine_is_iseo() (0) +#endif + +#ifdef CONFIG_MACH_CEZANNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEZANNE +# endif +# define machine_is_cezanne() (machine_arch_type == MACH_TYPE_CEZANNE) +#else +# define machine_is_cezanne() (0) +#endif + +#ifdef CONFIG_MACH_LUCCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUCCA +# endif +# define machine_is_lucca() (machine_arch_type == MACH_TYPE_LUCCA) +#else +# define machine_is_lucca() (0) +#endif + +#ifdef CONFIG_MACH_SUPERSMART +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUPERSMART +# endif +# define machine_is_supersmart() (machine_arch_type == MACH_TYPE_SUPERSMART) +#else +# define machine_is_supersmart() (0) +#endif + +#ifdef CONFIG_MACH_CS_MISANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS_MISANO +# endif +# define machine_is_arm11_board() (machine_arch_type == MACH_TYPE_CS_MISANO) +#else +# define machine_is_arm11_board() (0) +#endif + +#ifdef CONFIG_MACH_MAGNOLIA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGNOLIA2 +# endif +# define machine_is_magnolia2() (machine_arch_type == MACH_TYPE_MAGNOLIA2) +#else +# define machine_is_magnolia2() (0) +#endif + +#ifdef CONFIG_MACH_EMXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMXX +# endif +# define machine_is_emxx() (machine_arch_type == MACH_TYPE_EMXX) +#else +# define machine_is_emxx() (0) +#endif + +#ifdef CONFIG_MACH_OUTLAW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OUTLAW +# endif +# define machine_is_outlaw() (machine_arch_type == MACH_TYPE_OUTLAW) +#else +# define machine_is_outlaw() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_BEI2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_BEI2 +# endif +# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2) +#else +# define machine_is_riot_bei2() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_VOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_VOX +# endif +# define machine_is_riot_vox() (machine_arch_type == MACH_TYPE_RIOT_VOX) +#else +# define machine_is_riot_vox() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_X37 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_X37 +# endif +# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37) +#else +# define machine_is_riot_x37() (0) +#endif + +#ifdef CONFIG_MACH_MEGA25MX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEGA25MX +# endif +# define machine_is_mega25mx() (machine_arch_type == MACH_TYPE_MEGA25MX) +#else +# define machine_is_mega25mx() (0) +#endif + +#ifdef CONFIG_MACH_BENZINA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZINA2 +# endif +# define machine_is_benzina2() (machine_arch_type == MACH_TYPE_BENZINA2) +#else +# define machine_is_benzina2() (0) +#endif + +#ifdef CONFIG_MACH_IGNITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGNITE +# endif +# define machine_is_ignite() (machine_arch_type == MACH_TYPE_IGNITE) +#else +# define machine_is_ignite() (0) +#endif + +#ifdef CONFIG_MACH_FOGGIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FOGGIA +# endif +# define machine_is_foggia() (machine_arch_type == MACH_TYPE_FOGGIA) +#else +# define machine_is_foggia() (0) +#endif + +#ifdef CONFIG_MACH_AREZZO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AREZZO +# endif +# define machine_is_arezzo() (machine_arch_type == MACH_TYPE_AREZZO) +#else +# define machine_is_arezzo() (0) +#endif + +#ifdef CONFIG_MACH_LEICA_SKYWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEICA_SKYWALKER +# endif +# define machine_is_leica_skywalker() (machine_arch_type == MACH_TYPE_LEICA_SKYWALKER) +#else +# define machine_is_leica_skywalker() (0) +#endif + +#ifdef CONFIG_MACH_JACINTO2_JAMR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JACINTO2_JAMR +# endif +# define machine_is_jacinto2_jamr() (machine_arch_type == MACH_TYPE_JACINTO2_JAMR) +#else +# define machine_is_jacinto2_jamr() (0) +#endif + +#ifdef CONFIG_MACH_GTS_NOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTS_NOVA +# endif +# define machine_is_gts_nova() (machine_arch_type == MACH_TYPE_GTS_NOVA) +#else +# define machine_is_gts_nova() (0) +#endif + +#ifdef CONFIG_MACH_P3600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P3600 +# endif +# define machine_is_p3600() (machine_arch_type == MACH_TYPE_P3600) +#else +# define machine_is_p3600() (0) +#endif + +#ifdef CONFIG_MACH_DLT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DLT2 +# endif +# define machine_is_dlt2() (machine_arch_type == MACH_TYPE_DLT2) +#else +# define machine_is_dlt2() (0) +#endif + +#ifdef CONFIG_MACH_DF3120 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DF3120 +# endif +# define machine_is_df3120() (machine_arch_type == MACH_TYPE_DF3120) +#else +# define machine_is_df3120() (0) +#endif + +#ifdef CONFIG_MACH_ECUCORE_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECUCORE_9G20 +# endif +# define machine_is_ecucore_9g20() (machine_arch_type == MACH_TYPE_ECUCORE_9G20) +#else +# define machine_is_ecucore_9g20() (0) +#endif + +#ifdef CONFIG_MACH_NAUTEL_LPC3240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAUTEL_LPC3240 +# endif +# define machine_is_nautel_lpc3240() (machine_arch_type == MACH_TYPE_NAUTEL_LPC3240) +#else +# define machine_is_nautel_lpc3240() (0) +#endif + +#ifdef CONFIG_MACH_GLACIER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLACIER +# endif +# define machine_is_glacier() (machine_arch_type == MACH_TYPE_GLACIER) +#else +# define machine_is_glacier() (0) +#endif + +#ifdef CONFIG_MACH_PHRAZER_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHRAZER_BULLDOG +# endif +# define machine_is_phrazer_bulldog() (machine_arch_type == MACH_TYPE_PHRAZER_BULLDOG) +#else +# define machine_is_phrazer_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BULLDOG +# endif +# define machine_is_omap3_bulldog() (machine_arch_type == MACH_TYPE_OMAP3_BULLDOG) +#else +# define machine_is_omap3_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_PCA101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA101 +# endif +# define machine_is_pca101() (machine_arch_type == MACH_TYPE_PCA101) +#else +# define machine_is_pca101() (0) +#endif + +#ifdef CONFIG_MACH_BUZZC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUZZC +# endif +# define machine_is_buzzc() (machine_arch_type == MACH_TYPE_BUZZC) +#else +# define machine_is_buzzc() (0) +#endif + +#ifdef CONFIG_MACH_SASIE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SASIE2 +# endif +# define machine_is_sasie2() (machine_arch_type == MACH_TYPE_SASIE2) +#else +# define machine_is_sasie2() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_CIO +# endif +# define machine_is_davinci_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO) +#else +# define machine_is_davinci_cio() (0) +#endif + +#ifdef CONFIG_MACH_SMARTMETER_DL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTMETER_DL +# endif +# define machine_is_smartmeter_dl() (machine_arch_type == MACH_TYPE_SMARTMETER_DL) +#else +# define machine_is_smartmeter_dl() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410 +# endif +# define machine_is_wzl6410() (machine_arch_type == MACH_TYPE_WZL6410) +#else +# define machine_is_wzl6410() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410M +# endif +# define machine_is_wzl6410m() (machine_arch_type == MACH_TYPE_WZL6410M) +#else +# define machine_is_wzl6410m() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410F +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410F +# endif +# define machine_is_wzl6410f() (machine_arch_type == MACH_TYPE_WZL6410F) +#else +# define machine_is_wzl6410f() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410I +# endif +# define machine_is_wzl6410i() (machine_arch_type == MACH_TYPE_WZL6410I) +#else +# define machine_is_wzl6410i() (0) +#endif + +#ifdef CONFIG_MACH_SPACECOM1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPACECOM1 +# endif +# define machine_is_spacecom1() (machine_arch_type == MACH_TYPE_SPACECOM1) +#else +# define machine_is_spacecom1() (0) +#endif + +#ifdef CONFIG_MACH_PINGU920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PINGU920 +# endif +# define machine_is_pingu920() (machine_arch_type == MACH_TYPE_PINGU920) +#else +# define machine_is_pingu920() (0) +#endif + +#ifdef CONFIG_MACH_BRAVOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRAVOC +# endif +# define machine_is_bravoc() (machine_arch_type == MACH_TYPE_BRAVOC) +#else +# define machine_is_bravoc() (0) +#endif + +#ifdef CONFIG_MACH_CYBO2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBO2440 +# endif +# define machine_is_cybo2440() (machine_arch_type == MACH_TYPE_CYBO2440) +#else +# define machine_is_cybo2440() (0) +#endif + +#ifdef CONFIG_MACH_VDSSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VDSSW +# endif +# define machine_is_vdssw() (machine_arch_type == MACH_TYPE_VDSSW) +#else +# define machine_is_vdssw() (0) +#endif + +#ifdef CONFIG_MACH_ROMULUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROMULUS +# endif +# define machine_is_romulus() (machine_arch_type == MACH_TYPE_ROMULUS) +#else +# define machine_is_romulus() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_MAGIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_MAGIC +# endif +# define machine_is_omap_magic() (machine_arch_type == MACH_TYPE_OMAP_MAGIC) +#else +# define machine_is_omap_magic() (0) +#endif + +#ifdef CONFIG_MACH_ELTD100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELTD100 +# endif +# define machine_is_eltd100() (machine_arch_type == MACH_TYPE_ELTD100) +#else +# define machine_is_eltd100() (0) +#endif + +#ifdef CONFIG_MACH_CAPC7117 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAPC7117 +# endif +# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117) +#else +# define machine_is_capc7117() (0) +#endif + +#ifdef CONFIG_MACH_SWAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWAN +# endif +# define machine_is_swan() (machine_arch_type == MACH_TYPE_SWAN) +#else +# define machine_is_swan() (0) +#endif + +#ifdef CONFIG_MACH_VEU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VEU +# endif +# define machine_is_veu() (machine_arch_type == MACH_TYPE_VEU) +#else +# define machine_is_veu() (0) +#endif + +#ifdef CONFIG_MACH_RM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RM2 +# endif +# define machine_is_rm2() (machine_arch_type == MACH_TYPE_RM2) +#else +# define machine_is_rm2() (0) +#endif + +#ifdef CONFIG_MACH_TT2100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT2100 +# endif +# define machine_is_tt2100() (machine_arch_type == MACH_TYPE_TT2100) +#else +# define machine_is_tt2100() (0) +#endif + +#ifdef CONFIG_MACH_VENICE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENICE +# endif +# define machine_is_venice() (machine_arch_type == MACH_TYPE_VENICE) +#else +# define machine_is_venice() (0) +#endif + +#ifdef CONFIG_MACH_PC7323 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7323 +# endif +# define machine_is_pc7323() (machine_arch_type == MACH_TYPE_PC7323) +#else +# define machine_is_pc7323() (0) +#endif + +#ifdef CONFIG_MACH_MASP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MASP +# endif +# define machine_is_masp() (machine_arch_type == MACH_TYPE_MASP) +#else +# define machine_is_masp() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC +# endif +# define machine_is_fujitsu_tvstbsoc0() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC) +#else +# define machine_is_fujitsu_tvstbsoc0() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC1 +# endif +# define machine_is_fujitsu_tvstbsoc1() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC1) +#else +# define machine_is_fujitsu_tvstbsoc1() (0) +#endif + +#ifdef CONFIG_MACH_LEXIKON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEXIKON +# endif +# define machine_is_lexikon() (machine_arch_type == MACH_TYPE_LEXIKON) +#else +# define machine_is_lexikon() (0) +#endif + +#ifdef CONFIG_MACH_MINI2440V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI2440V2 +# endif +# define machine_is_mini2440v2() (machine_arch_type == MACH_TYPE_MINI2440V2) +#else +# define machine_is_mini2440v2() (0) +#endif + +#ifdef CONFIG_MACH_ICONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONTROL +# endif +# define machine_is_icontrol() (machine_arch_type == MACH_TYPE_ICONTROL) +#else +# define machine_is_icontrol() (0) +#endif + +#ifdef CONFIG_MACH_SHEEVAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHEEVAD +# endif +# define machine_is_sheevad() (machine_arch_type == MACH_TYPE_SHEEVAD) +#else +# define machine_is_sheevad() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_ST1_1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_1 +# endif +# define machine_is_qsd8x50a_st1_1() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_1) +#else +# define machine_is_qsd8x50a_st1_1() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_ST1_5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_5 +# endif +# define machine_is_qsd8x50a_st1_5() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5) +#else +# define machine_is_qsd8x50a_st1_5() (0) +#endif + +#ifdef CONFIG_MACH_BEE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEE +# endif +# define machine_is_bee() (machine_arch_type == MACH_TYPE_BEE) +#else +# define machine_is_bee() (0) +#endif + +#ifdef CONFIG_MACH_MX23EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX23EVK +# endif +# define machine_is_mx23evk() (machine_arch_type == MACH_TYPE_MX23EVK) +#else +# define machine_is_mx23evk() (0) +#endif + +#ifdef CONFIG_MACH_AP4EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP4EVB +# endif +# define machine_is_ap4evb() (machine_arch_type == MACH_TYPE_AP4EVB) +#else +# define machine_is_ap4evb() (0) +#endif + +#ifdef CONFIG_MACH_STOCKHOLM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STOCKHOLM +# endif +# define machine_is_stockholm() (machine_arch_type == MACH_TYPE_STOCKHOLM) +#else +# define machine_is_stockholm() (0) +#endif + +#ifdef CONFIG_MACH_LPC_H3131 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC_H3131 +# endif +# define machine_is_lpc_h3131() (machine_arch_type == MACH_TYPE_LPC_H3131) +#else +# define machine_is_lpc_h3131() (0) +#endif + +#ifdef CONFIG_MACH_STINGRAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STINGRAY +# endif +# define machine_is_stingray() (machine_arch_type == MACH_TYPE_STINGRAY) +#else +# define machine_is_stingray() (0) +#endif + +#ifdef CONFIG_MACH_KRAKEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRAKEN +# endif +# define machine_is_kraken() (machine_arch_type == MACH_TYPE_KRAKEN) +#else +# define machine_is_kraken() (0) +#endif + +#ifdef CONFIG_MACH_GW2388 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GW2388 +# endif +# define machine_is_gw2388() (machine_arch_type == MACH_TYPE_GW2388) +#else +# define machine_is_gw2388() (0) +#endif + +#ifdef CONFIG_MACH_JADECPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADECPU +# endif +# define machine_is_jadecpu() (machine_arch_type == MACH_TYPE_JADECPU) +#else +# define machine_is_jadecpu() (0) +#endif + +#ifdef CONFIG_MACH_CARLISLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARLISLE +# endif +# define machine_is_carlisle() (machine_arch_type == MACH_TYPE_CARLISLE) +#else +# define machine_is_carlisle() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SFT9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SFT9 +# endif +# define machine_is_lux_sf9() (machine_arch_type == MACH_TYPE_LUX_SFT9) +#else +# define machine_is_lux_sf9() (0) +#endif + +#ifdef CONFIG_MACH_NEMID_TB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEMID_TB +# endif +# define machine_is_nemid_tb() (machine_arch_type == MACH_TYPE_NEMID_TB) +#else +# define machine_is_nemid_tb() (0) +#endif + +#ifdef CONFIG_MACH_TERRIER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERRIER +# endif +# define machine_is_terrier() (machine_arch_type == MACH_TYPE_TERRIER) +#else +# define machine_is_terrier() (0) +#endif + +#ifdef CONFIG_MACH_TURBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TURBOT +# endif +# define machine_is_turbot() (machine_arch_type == MACH_TYPE_TURBOT) +#else +# define machine_is_turbot() (0) +#endif + +#ifdef CONFIG_MACH_SANDDAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDDAB +# endif +# define machine_is_sanddab() (machine_arch_type == MACH_TYPE_SANDDAB) +#else +# define machine_is_sanddab() (0) +#endif + +#ifdef CONFIG_MACH_MX35_CICADA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35_CICADA +# endif +# define machine_is_mx35_cicada() (machine_arch_type == MACH_TYPE_MX35_CICADA) +#else +# define machine_is_mx35_cicada() (0) +#endif + +#ifdef CONFIG_MACH_GHI2703D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GHI2703D +# endif +# define machine_is_ghi2703d() (machine_arch_type == MACH_TYPE_GHI2703D) +#else +# define machine_is_ghi2703d() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SFX9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SFX9 +# endif +# define machine_is_lux_sfx9() (machine_arch_type == MACH_TYPE_LUX_SFX9) +#else +# define machine_is_lux_sfx9() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SF9G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SF9G +# endif +# define machine_is_lux_sf9g() (machine_arch_type == MACH_TYPE_LUX_SF9G) +#else +# define machine_is_lux_sf9g() (0) +#endif + +#ifdef CONFIG_MACH_LUX_EDK9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_EDK9 +# endif +# define machine_is_lux_edk9() (machine_arch_type == MACH_TYPE_LUX_EDK9) +#else +# define machine_is_lux_edk9() (0) +#endif + +#ifdef CONFIG_MACH_HW90240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90240 +# endif +# define machine_is_hw90240() (machine_arch_type == MACH_TYPE_HW90240) +#else +# define machine_is_hw90240() (0) +#endif + +#ifdef CONFIG_MACH_DM365_LEOPARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM365_LEOPARD +# endif +# define machine_is_dm365_leopard() (machine_arch_type == MACH_TYPE_DM365_LEOPARD) +#else +# define machine_is_dm365_leopard() (0) +#endif + +#ifdef CONFIG_MACH_MITYOMAPL138 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MITYOMAPL138 +# endif +# define machine_is_mityomapl138() (machine_arch_type == MACH_TYPE_MITYOMAPL138) +#else +# define machine_is_mityomapl138() (0) +#endif + +#ifdef CONFIG_MACH_SCAT110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT110 +# endif +# define machine_is_scat110() (machine_arch_type == MACH_TYPE_SCAT110) +#else +# define machine_is_scat110() (0) +#endif + +#ifdef CONFIG_MACH_ACER_A1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_A1 +# endif +# define machine_is_acer_a1() (machine_arch_type == MACH_TYPE_ACER_A1) +#else +# define machine_is_acer_a1() (0) +#endif + +#ifdef CONFIG_MACH_CMCONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMCONTROL +# endif +# define machine_is_cmcontrol() (machine_arch_type == MACH_TYPE_CMCONTROL) +#else +# define machine_is_cmcontrol() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LAMAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LAMAR +# endif +# define machine_is_pelco_lamar() (machine_arch_type == MACH_TYPE_PELCO_LAMAR) +#else +# define machine_is_pelco_lamar() (0) +#endif + +#ifdef CONFIG_MACH_RFP43 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RFP43 +# endif +# define machine_is_rfp43() (machine_arch_type == MACH_TYPE_RFP43) +#else +# define machine_is_rfp43() (0) +#endif + +#ifdef CONFIG_MACH_SK86R0301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SK86R0301 +# endif +# define machine_is_sk86r0301() (machine_arch_type == MACH_TYPE_SK86R0301) +#else +# define machine_is_sk86r0301() (0) +#endif + +#ifdef CONFIG_MACH_CTPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTPXA +# endif +# define machine_is_ctpxa() (machine_arch_type == MACH_TYPE_CTPXA) +#else +# define machine_is_ctpxa() (0) +#endif + +#ifdef CONFIG_MACH_EPB_ARM9_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPB_ARM9_A +# endif +# define machine_is_epb_arm9_a() (machine_arch_type == MACH_TYPE_EPB_ARM9_A) +#else +# define machine_is_epb_arm9_a() (0) +#endif + +#ifdef CONFIG_MACH_GURUPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GURUPLUG +# endif +# define machine_is_guruplug() (machine_arch_type == MACH_TYPE_GURUPLUG) +#else +# define machine_is_guruplug() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR310 +# endif +# define machine_is_spear310() (machine_arch_type == MACH_TYPE_SPEAR310) +#else +# define machine_is_spear310() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR320 +# endif +# define machine_is_spear320() (machine_arch_type == MACH_TYPE_SPEAR320) +#else +# define machine_is_spear320() (0) +#endif + +#ifdef CONFIG_MACH_ROBOTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROBOTX +# endif +# define machine_is_robotx() (machine_arch_type == MACH_TYPE_ROBOTX) +#else +# define machine_is_robotx() (0) +#endif + +#ifdef CONFIG_MACH_LSXHL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSXHL +# endif +# define machine_is_lsxhl() (machine_arch_type == MACH_TYPE_LSXHL) +#else +# define machine_is_lsxhl() (0) +#endif + +#ifdef CONFIG_MACH_SMARTLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTLITE +# endif +# define machine_is_smartlite() (machine_arch_type == MACH_TYPE_SMARTLITE) +#else +# define machine_is_smartlite() (0) +#endif + +#ifdef CONFIG_MACH_CWS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWS2 +# endif +# define machine_is_cws2() (machine_arch_type == MACH_TYPE_CWS2) +#else +# define machine_is_cws2() (0) +#endif + +#ifdef CONFIG_MACH_M619 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M619 +# endif +# define machine_is_m619() (machine_arch_type == MACH_TYPE_M619) +#else +# define machine_is_m619() (0) +#endif + +#ifdef CONFIG_MACH_SMARTVIEW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTVIEW +# endif +# define machine_is_smartview() (machine_arch_type == MACH_TYPE_SMARTVIEW) +#else +# define machine_is_smartview() (0) +#endif + +#ifdef CONFIG_MACH_LSA_SALSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSA_SALSA +# endif +# define machine_is_lsa_salsa() (machine_arch_type == MACH_TYPE_LSA_SALSA) +#else +# define machine_is_lsa_salsa() (0) +#endif + +#ifdef CONFIG_MACH_KIZBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIZBOX +# endif +# define machine_is_kizbox() (machine_arch_type == MACH_TYPE_KIZBOX) +#else +# define machine_is_kizbox() (0) +#endif + +#ifdef CONFIG_MACH_HTCCHARMER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCCHARMER +# endif +# define machine_is_htccharmer() (machine_arch_type == MACH_TYPE_HTCCHARMER) +#else +# define machine_is_htccharmer() (0) +#endif + +#ifdef CONFIG_MACH_GUF_NESO_LT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUF_NESO_LT +# endif +# define machine_is_guf_neso_lt() (machine_arch_type == MACH_TYPE_GUF_NESO_LT) +#else +# define machine_is_guf_neso_lt() (0) +#endif + +#ifdef CONFIG_MACH_PM9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PM9G45 +# endif +# define machine_is_pm9g45() (machine_arch_type == MACH_TYPE_PM9G45) +#else +# define machine_is_pm9g45() (0) +#endif + +#ifdef CONFIG_MACH_HTCPANTHER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPANTHER +# endif +# define machine_is_htcpanther() (machine_arch_type == MACH_TYPE_HTCPANTHER) +#else +# define machine_is_htcpanther() (0) +#endif + +#ifdef CONFIG_MACH_HTCPANTHER_CDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPANTHER_CDMA +# endif +# define machine_is_htcpanther_cdma() (machine_arch_type == MACH_TYPE_HTCPANTHER_CDMA) +#else +# define machine_is_htcpanther_cdma() (0) +#endif + +#ifdef CONFIG_MACH_REB01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REB01 +# endif +# define machine_is_reb01() (machine_arch_type == MACH_TYPE_REB01) +#else +# define machine_is_reb01() (0) +#endif + +#ifdef CONFIG_MACH_AQUILA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AQUILA +# endif +# define machine_is_aquila() (machine_arch_type == MACH_TYPE_AQUILA) +#else +# define machine_is_aquila() (0) +#endif + +#ifdef CONFIG_MACH_SPARK_SLS_HW2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARK_SLS_HW2 +# endif +# define machine_is_spark_sls_hw2() (machine_arch_type == MACH_TYPE_SPARK_SLS_HW2) +#else +# define machine_is_spark_sls_hw2() (0) +#endif + +#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESATA_SHEEVAPLUG +# endif +# define machine_is_sheeva_esata() (machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG) +#else +# define machine_is_sheeva_esata() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_SURF +# endif +# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_MSM7X30_SURF) +#else +# define machine_is_msm7x30_surf() (0) +#endif + +#ifdef CONFIG_MACH_MICRO2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO2440 +# endif +# define machine_is_micro2440() (machine_arch_type == MACH_TYPE_MICRO2440) +#else +# define machine_is_micro2440() (0) +#endif + +#ifdef CONFIG_MACH_AM2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AM2440 +# endif +# define machine_is_am2440() (machine_arch_type == MACH_TYPE_AM2440) +#else +# define machine_is_am2440() (0) +#endif + +#ifdef CONFIG_MACH_TQ2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQ2440 +# endif +# define machine_is_tq2440() (machine_arch_type == MACH_TYPE_TQ2440) +#else +# define machine_is_tq2440() (0) +#endif + +#ifdef CONFIG_MACH_LPC2478OEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2478OEM +# endif +# define machine_is_lpc2478oem() (machine_arch_type == MACH_TYPE_LPC2478OEM) +#else +# define machine_is_lpc2478oem() (0) +#endif + +#ifdef CONFIG_MACH_AK880X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK880X +# endif +# define machine_is_ak880x() (machine_arch_type == MACH_TYPE_AK880X) +#else +# define machine_is_ak880x() (0) +#endif + +#ifdef CONFIG_MACH_COBRA3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COBRA3530 +# endif +# define machine_is_cobra3530() (machine_arch_type == MACH_TYPE_COBRA3530) +#else +# define machine_is_cobra3530() (0) +#endif + +#ifdef CONFIG_MACH_PMPPB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMPPB +# endif +# define machine_is_pmppb() (machine_arch_type == MACH_TYPE_PMPPB) +#else +# define machine_is_pmppb() (0) +#endif + +#ifdef CONFIG_MACH_U6715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U6715 +# endif +# define machine_is_u6715() (machine_arch_type == MACH_TYPE_U6715) +#else +# define machine_is_u6715() (0) +#endif + +#ifdef CONFIG_MACH_AXAR1500_SENDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXAR1500_SENDER +# endif +# define machine_is_axar1500_sender() (machine_arch_type == MACH_TYPE_AXAR1500_SENDER) +#else +# define machine_is_axar1500_sender() (0) +#endif + +#ifdef CONFIG_MACH_G30_DVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G30_DVB +# endif +# define machine_is_g30_dvb() (machine_arch_type == MACH_TYPE_G30_DVB) +#else +# define machine_is_g30_dvb() (0) +#endif + +#ifdef CONFIG_MACH_VC088X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC088X +# endif +# define machine_is_vc088x() (machine_arch_type == MACH_TYPE_VC088X) +#else +# define machine_is_vc088x() (0) +#endif + +#ifdef CONFIG_MACH_MIOA702 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOA702 +# endif +# define machine_is_mioa702() (machine_arch_type == MACH_TYPE_MIOA702) +#else +# define machine_is_mioa702() (0) +#endif + +#ifdef CONFIG_MACH_HPMIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPMIN +# endif +# define machine_is_hpmin() (machine_arch_type == MACH_TYPE_HPMIN) +#else +# define machine_is_hpmin() (0) +#endif + +#ifdef CONFIG_MACH_AK880XAK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK880XAK +# endif +# define machine_is_ak880xak() (machine_arch_type == MACH_TYPE_AK880XAK) +#else +# define machine_is_ak880xak() (0) +#endif + +#ifdef CONFIG_MACH_ARM926TOMAP850 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM926TOMAP850 +# endif +# define machine_is_arm926tomap850() (machine_arch_type == MACH_TYPE_ARM926TOMAP850) +#else +# define machine_is_arm926tomap850() (0) +#endif + +#ifdef CONFIG_MACH_LKEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LKEVM +# endif +# define machine_is_lkevm() (machine_arch_type == MACH_TYPE_LKEVM) +#else +# define machine_is_lkevm() (0) +#endif + +#ifdef CONFIG_MACH_MW6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW6410 +# endif +# define machine_is_mw6410() (machine_arch_type == MACH_TYPE_MW6410) +#else +# define machine_is_mw6410() (0) +#endif + +#ifdef CONFIG_MACH_TERASTATION_WXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERASTATION_WXL +# endif +# define machine_is_terastation_wxl() (machine_arch_type == MACH_TYPE_TERASTATION_WXL) +#else +# define machine_is_terastation_wxl() (0) +#endif + +#ifdef CONFIG_MACH_CPU8000E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPU8000E +# endif +# define machine_is_cpu8000e() (machine_arch_type == MACH_TYPE_CPU8000E) +#else +# define machine_is_cpu8000e() (0) +#endif + +#ifdef CONFIG_MACH_CATANIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATANIA +# endif +# define machine_is_catania() (machine_arch_type == MACH_TYPE_CATANIA) +#else +# define machine_is_catania() (0) +#endif + +#ifdef CONFIG_MACH_TOKYO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOKYO +# endif +# define machine_is_tokyo() (machine_arch_type == MACH_TYPE_TOKYO) +#else +# define machine_is_tokyo() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A_SURF +# endif +# define machine_is_msm7201a_surf() (machine_arch_type == MACH_TYPE_MSM7201A_SURF) +#else +# define machine_is_msm7201a_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A_FFA +# endif +# define machine_is_msm7201a_ffa() (machine_arch_type == MACH_TYPE_MSM7201A_FFA) +#else +# define machine_is_msm7201a_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X25_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X25_SURF +# endif +# define machine_is_msm7x25_surf() (machine_arch_type == MACH_TYPE_MSM7X25_SURF) +#else +# define machine_is_msm7x25_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X25_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X25_FFA +# endif +# define machine_is_msm7x25_ffa() (machine_arch_type == MACH_TYPE_MSM7X25_FFA) +#else +# define machine_is_msm7x25_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X27_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X27_SURF +# endif +# define machine_is_msm7x27_surf() (machine_arch_type == MACH_TYPE_MSM7X27_SURF) +#else +# define machine_is_msm7x27_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X27_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X27_FFA +# endif +# define machine_is_msm7x27_ffa() (machine_arch_type == MACH_TYPE_MSM7X27_FFA) +#else +# define machine_is_msm7x27_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_FFA +# endif +# define machine_is_msm7x30_ffa() (machine_arch_type == MACH_TYPE_MSM7X30_FFA) +#else +# define machine_is_msm7x30_ffa() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_SURF +# endif +# define machine_is_qsd8x50_surf() (machine_arch_type == MACH_TYPE_QSD8X50_SURF) +#else +# define machine_is_qsd8x50_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_COMET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_COMET +# endif +# define machine_is_qsd8x50_comet() (machine_arch_type == MACH_TYPE_QSD8X50_COMET) +#else +# define machine_is_qsd8x50_comet() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_FFA +# endif +# define machine_is_qsd8x50_ffa() (machine_arch_type == MACH_TYPE_QSD8X50_FFA) +#else +# define machine_is_qsd8x50_ffa() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_SURF +# endif +# define machine_is_qsd8x50a_surf() (machine_arch_type == MACH_TYPE_QSD8X50A_SURF) +#else +# define machine_is_qsd8x50a_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_FFA +# endif +# define machine_is_qsd8x50a_ffa() (machine_arch_type == MACH_TYPE_QSD8X50A_FFA) +#else +# define machine_is_qsd8x50a_ffa() (0) +#endif + +#ifdef CONFIG_MACH_ADX_XGCP10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_XGCP10 +# endif +# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_ADX_XGCP10) +#else +# define machine_is_adx_xgcp10() (0) +#endif + +#ifdef CONFIG_MACH_MCGWUMTS2A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCGWUMTS2A +# endif +# define machine_is_mcgwumts2a() (machine_arch_type == MACH_TYPE_MCGWUMTS2A) +#else +# define machine_is_mcgwumts2a() (0) +#endif + +#ifdef CONFIG_MACH_MOBIKT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOBIKT +# endif +# define machine_is_mobikt() (machine_arch_type == MACH_TYPE_MOBIKT) +#else +# define machine_is_mobikt() (0) +#endif + +#ifdef CONFIG_MACH_MX53_EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX53_EVK +# endif +# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK) +#else +# define machine_is_mx53_evk() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0030 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0030 +# endif +# define machine_is_igep0030() (machine_arch_type == MACH_TYPE_IGEP0030) +#else +# define machine_is_igep0030() (0) +#endif + +#ifdef CONFIG_MACH_AXELL_H40_H50_CTRL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXELL_H40_H50_CTRL +# endif +# define machine_is_axell_h40_h50_ctrl() (machine_arch_type == MACH_TYPE_AXELL_H40_H50_CTRL) +#else +# define machine_is_axell_h40_h50_ctrl() (0) +#endif + +#ifdef CONFIG_MACH_DTCOMMOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DTCOMMOD +# endif +# define machine_is_dtcommod() (machine_arch_type == MACH_TYPE_DTCOMMOD) +#else +# define machine_is_dtcommod() (0) +#endif + +#ifdef CONFIG_MACH_GOULD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GOULD +# endif +# define machine_is_gould() (machine_arch_type == MACH_TYPE_GOULD) +#else +# define machine_is_gould() (0) +#endif + +#ifdef CONFIG_MACH_SIBERIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIBERIA +# endif +# define machine_is_siberia() (machine_arch_type == MACH_TYPE_SIBERIA) +#else +# define machine_is_siberia() (0) +#endif + +#ifdef CONFIG_MACH_SBC3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC3530 +# endif +# define machine_is_sbc3530() (machine_arch_type == MACH_TYPE_SBC3530) +#else +# define machine_is_sbc3530() (0) +#endif + +#ifdef CONFIG_MACH_QARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QARM +# endif +# define machine_is_qarm() (machine_arch_type == MACH_TYPE_QARM) +#else +# define machine_is_qarm() (0) +#endif + +#ifdef CONFIG_MACH_MIPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIPS +# endif +# define machine_is_mips() (machine_arch_type == MACH_TYPE_MIPS) +#else +# define machine_is_mips() (0) +#endif + +#ifdef CONFIG_MACH_MX27GRB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27GRB +# endif +# define machine_is_mx27grb() (machine_arch_type == MACH_TYPE_MX27GRB) +#else +# define machine_is_mx27grb() (0) +#endif + +#ifdef CONFIG_MACH_SBC8100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC8100 +# endif +# define machine_is_sbc8100() (machine_arch_type == MACH_TYPE_SBC8100) +#else +# define machine_is_sbc8100() (0) +#endif + +#ifdef CONFIG_MACH_SAARB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAARB +# endif +# define machine_is_saarb() (machine_arch_type == MACH_TYPE_SAARB) +#else +# define machine_is_saarb() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3MINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3MINI +# endif +# define machine_is_omap3mini() (machine_arch_type == MACH_TYPE_OMAP3MINI) +#else +# define machine_is_omap3mini() (0) +#endif + +#ifdef CONFIG_MACH_CNMBOOK7SE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNMBOOK7SE +# endif +# define machine_is_cnmbook7se() (machine_arch_type == MACH_TYPE_CNMBOOK7SE) +#else +# define machine_is_cnmbook7se() (0) +#endif + +#ifdef CONFIG_MACH_CATAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATAN +# endif +# define machine_is_catan() (machine_arch_type == MACH_TYPE_CATAN) +#else +# define machine_is_catan() (0) +#endif + +#ifdef CONFIG_MACH_HARMONY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HARMONY +# endif +# define machine_is_harmony() (machine_arch_type == MACH_TYPE_HARMONY) +#else +# define machine_is_harmony() (0) +#endif + +#ifdef CONFIG_MACH_TONGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TONGA +# endif +# define machine_is_tonga() (machine_arch_type == MACH_TYPE_TONGA) +#else +# define machine_is_tonga() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK_ORIZON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK_ORIZON +# endif +# define machine_is_cybook_orizon() (machine_arch_type == MACH_TYPE_CYBOOK_ORIZON) +#else +# define machine_is_cybook_orizon() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUMCDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUMCDMA +# endif +# define machine_is_htcrhodiumcdma() (machine_arch_type == MACH_TYPE_HTCRHODIUMCDMA) +#else +# define machine_is_htcrhodiumcdma() (0) +#endif + +#ifdef CONFIG_MACH_EPC_G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPC_G45 +# endif +# define machine_is_epc_g45() (machine_arch_type == MACH_TYPE_EPC_G45) +#else +# define machine_is_epc_g45() (0) +#endif + +#ifdef CONFIG_MACH_EPC_LPC3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPC_LPC3250 +# endif +# define machine_is_epc_lpc3250() (machine_arch_type == MACH_TYPE_EPC_LPC3250) +#else +# define machine_is_epc_lpc3250() (0) +#endif + +#ifdef CONFIG_MACH_MXC91341EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC91341EVB +# endif +# define machine_is_mxc91341evb() (machine_arch_type == MACH_TYPE_MXC91341EVB) +#else +# define machine_is_mxc91341evb() (0) +#endif + +#ifdef CONFIG_MACH_RTW1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTW1000 +# endif +# define machine_is_rtw1000() (machine_arch_type == MACH_TYPE_RTW1000) +#else +# define machine_is_rtw1000() (0) +#endif + +#ifdef CONFIG_MACH_BOBCAT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BOBCAT +# endif +# define machine_is_bobcat() (machine_arch_type == MACH_TYPE_BOBCAT) +#else +# define machine_is_bobcat() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS6 +# endif +# define machine_is_trizeps6() (machine_arch_type == MACH_TYPE_TRIZEPS6) +#else +# define machine_is_trizeps6() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_FLUID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_FLUID +# endif +# define machine_is_msm7x30_fluid() (machine_arch_type == MACH_TYPE_MSM7X30_FLUID) +#else +# define machine_is_msm7x30_fluid() (0) +#endif + +#ifdef CONFIG_MACH_NEDAP9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEDAP9263 +# endif +# define machine_is_nedap9263() (machine_arch_type == MACH_TYPE_NEDAP9263) +#else +# define machine_is_nedap9263() (0) +#endif + +#ifdef CONFIG_MACH_NETGEAR_MS2110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETGEAR_MS2110 +# endif +# define machine_is_netgear_ms2110() (machine_arch_type == MACH_TYPE_NETGEAR_MS2110) +#else +# define machine_is_netgear_ms2110() (0) +#endif + +#ifdef CONFIG_MACH_BMX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BMX +# endif +# define machine_is_bmx() (machine_arch_type == MACH_TYPE_BMX) +#else +# define machine_is_bmx() (0) +#endif + +#ifdef CONFIG_MACH_NETSTREAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSTREAM +# endif +# define machine_is_netstream() (machine_arch_type == MACH_TYPE_NETSTREAM) +#else +# define machine_is_netstream() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT_RCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT_RCU +# endif +# define machine_is_vpnext_rcu() (machine_arch_type == MACH_TYPE_VPNEXT_RCU) +#else +# define machine_is_vpnext_rcu() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT_MPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT_MPU +# endif +# define machine_is_vpnext_mpu() (machine_arch_type == MACH_TYPE_VPNEXT_MPU) +#else +# define machine_is_vpnext_mpu() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_TABLET_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_TABLET_V1 +# endif +# define machine_is_bcmring_tablet_v1() (machine_arch_type == MACH_TYPE_BCMRING_TABLET_V1) +#else +# define machine_is_bcmring_tablet_v1() (0) +#endif + +#ifdef CONFIG_MACH_SGARM10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGARM10 +# endif +# define machine_is_sgarm10() (machine_arch_type == MACH_TYPE_SGARM10) +#else +# define machine_is_sgarm10() (0) +#endif + +#ifdef CONFIG_MACH_CM_T3517 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T3517 +# endif +# define machine_is_cm_t3517() (machine_arch_type == MACH_TYPE_CM_T3517) +#else +# define machine_is_cm_t3517() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CPS +# endif +# define machine_is_omap3_cps() (machine_arch_type == MACH_TYPE_OMAP3_CPS) +#else +# define machine_is_omap3_cps() (0) +#endif + +#ifdef CONFIG_MACH_AXAR1500_RECEIVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXAR1500_RECEIVER +# endif +# define machine_is_axar1500_receiver() (machine_arch_type == MACH_TYPE_AXAR1500_RECEIVER) +#else +# define machine_is_axar1500_receiver() (0) +#endif + +#ifdef CONFIG_MACH_WBD222 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WBD222 +# endif +# define machine_is_wbd222() (machine_arch_type == MACH_TYPE_WBD222) +#else +# define machine_is_wbd222() (0) +#endif + +#ifdef CONFIG_MACH_MT65XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT65XX +# endif +# define machine_is_mt65xx() (machine_arch_type == MACH_TYPE_MT65XX) +#else +# define machine_is_mt65xx() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_SURF +# endif +# define machine_is_msm8x60_surf() (machine_arch_type == MACH_TYPE_MSM8X60_SURF) +#else +# define machine_is_msm8x60_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_SIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_SIM +# endif +# define machine_is_msm8x60_sim() (machine_arch_type == MACH_TYPE_MSM8X60_SIM) +#else +# define machine_is_msm8x60_sim() (0) +#endif + +#ifdef CONFIG_MACH_VMC300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMC300 +# endif +# define machine_is_vmc300() (machine_arch_type == MACH_TYPE_VMC300) +#else +# define machine_is_vmc300() (0) +#endif + +#ifdef CONFIG_MACH_TCC8000_SDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TCC8000_SDK +# endif +# define machine_is_tcc8000_sdk() (machine_arch_type == MACH_TYPE_TCC8000_SDK) +#else +# define machine_is_tcc8000_sdk() (0) +#endif + +#ifdef CONFIG_MACH_NANOS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANOS +# endif +# define machine_is_nanos() (machine_arch_type == MACH_TYPE_NANOS) +#else +# define machine_is_nanos() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G10 +# endif +# define machine_is_stamp9g10() (machine_arch_type == MACH_TYPE_STAMP9G10) +#else +# define machine_is_stamp9g10() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G45 +# endif +# define machine_is_stamp9g45() (machine_arch_type == MACH_TYPE_STAMP9G45) +#else +# define machine_is_stamp9g45() (0) +#endif + +#ifdef CONFIG_MACH_H6053 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6053 +# endif +# define machine_is_h6053() (machine_arch_type == MACH_TYPE_H6053) +#else +# define machine_is_h6053() (0) +#endif + +#ifdef CONFIG_MACH_SMINT01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMINT01 +# endif +# define machine_is_smint01() (machine_arch_type == MACH_TYPE_SMINT01) +#else +# define machine_is_smint01() (0) +#endif + +#ifdef CONFIG_MACH_PRTLVT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRTLVT2 +# endif +# define machine_is_prtlvt2() (machine_arch_type == MACH_TYPE_PRTLVT2) +#else +# define machine_is_prtlvt2() (0) +#endif + +#ifdef CONFIG_MACH_AP420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP420 +# endif +# define machine_is_ap420() (machine_arch_type == MACH_TYPE_AP420) +#else +# define machine_is_ap420() (0) +#endif + +#ifdef CONFIG_MACH_HTCSHIFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCSHIFT +# endif +# define machine_is_htcclio() (machine_arch_type == MACH_TYPE_HTCSHIFT) +#else +# define machine_is_htcclio() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_FC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_FC +# endif +# define machine_is_davinci_dm365_fc() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_FC) +#else +# define machine_is_davinci_dm365_fc() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SURF +# endif +# define machine_is_msm8x55_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SURF) +#else +# define machine_is_msm8x55_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_FFA +# endif +# define machine_is_msm8x55_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_FFA) +#else +# define machine_is_msm8x55_ffa() (0) +#endif + +#ifdef CONFIG_MACH_ESL_VAMANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_VAMANA +# endif +# define machine_is_esl_vamana() (machine_arch_type == MACH_TYPE_ESL_VAMANA) +#else +# define machine_is_esl_vamana() (0) +#endif + +#ifdef CONFIG_MACH_SBC35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC35 +# endif +# define machine_is_sbc35() (machine_arch_type == MACH_TYPE_SBC35) +#else +# define machine_is_sbc35() (0) +#endif + +#ifdef CONFIG_MACH_MPX6446 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPX6446 +# endif +# define machine_is_mpx6446() (machine_arch_type == MACH_TYPE_MPX6446) +#else +# define machine_is_mpx6446() (0) +#endif + +#ifdef CONFIG_MACH_OREO_CONTROLLER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO_CONTROLLER +# endif +# define machine_is_oreo_controller() (machine_arch_type == MACH_TYPE_OREO_CONTROLLER) +#else +# define machine_is_oreo_controller() (0) +#endif + +#ifdef CONFIG_MACH_KOPIN_MODELS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOPIN_MODELS +# endif +# define machine_is_kopin_models() (machine_arch_type == MACH_TYPE_KOPIN_MODELS) +#else +# define machine_is_kopin_models() (0) +#endif + +#ifdef CONFIG_MACH_TTC_VISION2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TTC_VISION2 +# endif +# define machine_is_ttc_vision2() (machine_arch_type == MACH_TYPE_TTC_VISION2) +#else +# define machine_is_ttc_vision2() (0) +#endif + +#ifdef CONFIG_MACH_CNS3420VB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNS3420VB +# endif +# define machine_is_cns3420vb() (machine_arch_type == MACH_TYPE_CNS3420VB) +#else +# define machine_is_cns3420vb() (0) +#endif + +#ifdef CONFIG_MACH_LPC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2 +# endif +# define machine_is_lpc2() (machine_arch_type == MACH_TYPE_LPC2) +#else +# define machine_is_lpc2() (0) +#endif + +#ifdef CONFIG_MACH_OLYMPUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLYMPUS +# endif +# define machine_is_olympus() (machine_arch_type == MACH_TYPE_OLYMPUS) +#else +# define machine_is_olympus() (0) +#endif + +#ifdef CONFIG_MACH_VORTEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VORTEX +# endif +# define machine_is_vortex() (machine_arch_type == MACH_TYPE_VORTEX) +#else +# define machine_is_vortex() (0) +#endif + +#ifdef CONFIG_MACH_S5PC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC200 +# endif +# define machine_is_s5pc200() (machine_arch_type == MACH_TYPE_S5PC200) +#else +# define machine_is_s5pc200() (0) +#endif + +#ifdef CONFIG_MACH_ECUCORE_9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECUCORE_9263 +# endif +# define machine_is_ecucore_9263() (machine_arch_type == MACH_TYPE_ECUCORE_9263) +#else +# define machine_is_ecucore_9263() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC200 +# endif +# define machine_is_smdkc200() (machine_arch_type == MACH_TYPE_SMDKC200) +#else +# define machine_is_smdkc200() (0) +#endif + +#ifdef CONFIG_MACH_EMSISO_SX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMSISO_SX27 +# endif +# define machine_is_emsiso_sx27() (machine_arch_type == MACH_TYPE_EMSISO_SX27) +#else +# define machine_is_emsiso_sx27() (0) +#endif + +#ifdef CONFIG_MACH_APX_SOM9G45_EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APX_SOM9G45_EK +# endif +# define machine_is_apx_som9g45_ek() (machine_arch_type == MACH_TYPE_APX_SOM9G45_EK) +#else +# define machine_is_apx_som9g45_ek() (0) +#endif + +#ifdef CONFIG_MACH_SONGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONGSHAN +# endif +# define machine_is_songshan() (machine_arch_type == MACH_TYPE_SONGSHAN) +#else +# define machine_is_songshan() (0) +#endif + +#ifdef CONFIG_MACH_TIANSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIANSHAN +# endif +# define machine_is_tianshan() (machine_arch_type == MACH_TYPE_TIANSHAN) +#else +# define machine_is_tianshan() (0) +#endif + +#ifdef CONFIG_MACH_VPX500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPX500 +# endif +# define machine_is_vpx500() (machine_arch_type == MACH_TYPE_VPX500) +#else +# define machine_is_vpx500() (0) +#endif + +#ifdef CONFIG_MACH_AM3517SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AM3517SAM +# endif +# define machine_is_am3517sam() (machine_arch_type == MACH_TYPE_AM3517SAM) +#else +# define machine_is_am3517sam() (0) +#endif + +#ifdef CONFIG_MACH_SKAT91_SIM508 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKAT91_SIM508 +# endif +# define machine_is_skat91_sim508() (machine_arch_type == MACH_TYPE_SKAT91_SIM508) +#else +# define machine_is_skat91_sim508() (0) +#endif + +#ifdef CONFIG_MACH_SKAT91_S3E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKAT91_S3E +# endif +# define machine_is_skat91_s3e() (machine_arch_type == MACH_TYPE_SKAT91_S3E) +#else +# define machine_is_skat91_s3e() (0) +#endif + +#ifdef CONFIG_MACH_OMAP4_PANDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP4_PANDA +# endif +# define machine_is_omap4_panda() (machine_arch_type == MACH_TYPE_OMAP4_PANDA) +#else +# define machine_is_omap4_panda() (0) +#endif + +#ifdef CONFIG_MACH_DF7220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DF7220 +# endif +# define machine_is_df7220() (machine_arch_type == MACH_TYPE_DF7220) +#else +# define machine_is_df7220() (0) +#endif + +/* + * These have not yet been registered + */ + +#ifndef machine_arch_type +#define machine_arch_type __machine_arch_type +#endif + +#endif diff --git a/include/asm-arm/macro.h b/arch/arm/include/asm/macro.h similarity index 100% rename from include/asm-arm/macro.h rename to arch/arm/include/asm/macro.h diff --git a/include/asm-arm/memory.h b/arch/arm/include/asm/memory.h similarity index 100% rename from include/asm-arm/memory.h rename to arch/arm/include/asm/memory.h diff --git a/include/asm-arm/posix_types.h b/arch/arm/include/asm/posix_types.h similarity index 100% rename from include/asm-arm/posix_types.h rename to arch/arm/include/asm/posix_types.h diff --git a/include/asm-arm/proc-armv/domain.h b/arch/arm/include/asm/proc-armv/domain.h similarity index 100% rename from include/asm-arm/proc-armv/domain.h rename to arch/arm/include/asm/proc-armv/domain.h diff --git a/include/asm-arm/proc-armv/processor.h b/arch/arm/include/asm/proc-armv/processor.h similarity index 100% rename from include/asm-arm/proc-armv/processor.h rename to arch/arm/include/asm/proc-armv/processor.h diff --git a/include/asm-arm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h similarity index 100% rename from include/asm-arm/proc-armv/ptrace.h rename to arch/arm/include/asm/proc-armv/ptrace.h diff --git a/include/asm-arm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h similarity index 100% rename from include/asm-arm/proc-armv/system.h rename to arch/arm/include/asm/proc-armv/system.h diff --git a/include/asm-arm/processor.h b/arch/arm/include/asm/processor.h similarity index 100% rename from include/asm-arm/processor.h rename to arch/arm/include/asm/processor.h diff --git a/include/asm-arm/ptrace.h b/arch/arm/include/asm/ptrace.h similarity index 100% rename from include/asm-arm/ptrace.h rename to arch/arm/include/asm/ptrace.h diff --git a/include/asm-arm/setup.h b/arch/arm/include/asm/setup.h similarity index 100% rename from include/asm-arm/setup.h rename to arch/arm/include/asm/setup.h diff --git a/include/asm-arm/sizes.h b/arch/arm/include/asm/sizes.h similarity index 100% rename from include/asm-arm/sizes.h rename to arch/arm/include/asm/sizes.h diff --git a/include/asm-arm/string.h b/arch/arm/include/asm/string.h similarity index 100% rename from include/asm-arm/string.h rename to arch/arm/include/asm/string.h diff --git a/include/asm-arm/system.h b/arch/arm/include/asm/system.h similarity index 100% rename from include/asm-arm/system.h rename to arch/arm/include/asm/system.h diff --git a/include/asm-arm/types.h b/arch/arm/include/asm/types.h similarity index 100% rename from include/asm-arm/types.h rename to arch/arm/include/asm/types.h diff --git a/include/asm-arm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h similarity index 100% rename from include/asm-arm/u-boot-arm.h rename to arch/arm/include/asm/u-boot-arm.h diff --git a/include/asm-arm/u-boot.h b/arch/arm/include/asm/u-boot.h similarity index 100% rename from include/asm-arm/u-boot.h rename to arch/arm/include/asm/u-boot.h diff --git a/include/asm-arm/unaligned.h b/arch/arm/include/asm/unaligned.h similarity index 100% rename from include/asm-arm/unaligned.h rename to arch/arm/include/asm/unaligned.h diff --git a/lib_arm/Makefile b/arch/arm/lib/Makefile similarity index 100% rename from lib_arm/Makefile rename to arch/arm/lib/Makefile diff --git a/lib_arm/_ashldi3.S b/arch/arm/lib/_ashldi3.S similarity index 100% rename from lib_arm/_ashldi3.S rename to arch/arm/lib/_ashldi3.S diff --git a/lib_arm/_ashrdi3.S b/arch/arm/lib/_ashrdi3.S similarity index 100% rename from lib_arm/_ashrdi3.S rename to arch/arm/lib/_ashrdi3.S diff --git a/lib_arm/_divsi3.S b/arch/arm/lib/_divsi3.S similarity index 100% rename from lib_arm/_divsi3.S rename to arch/arm/lib/_divsi3.S diff --git a/lib_arm/_lshrdi3.S b/arch/arm/lib/_lshrdi3.S similarity index 100% rename from lib_arm/_lshrdi3.S rename to arch/arm/lib/_lshrdi3.S diff --git a/lib_arm/_modsi3.S b/arch/arm/lib/_modsi3.S similarity index 100% rename from lib_arm/_modsi3.S rename to arch/arm/lib/_modsi3.S diff --git a/lib_arm/_udivsi3.S b/arch/arm/lib/_udivsi3.S similarity index 100% rename from lib_arm/_udivsi3.S rename to arch/arm/lib/_udivsi3.S diff --git a/lib_arm/_umodsi3.S b/arch/arm/lib/_umodsi3.S similarity index 100% rename from lib_arm/_umodsi3.S rename to arch/arm/lib/_umodsi3.S diff --git a/lib_arm/board.c b/arch/arm/lib/board.c similarity index 100% rename from lib_arm/board.c rename to arch/arm/lib/board.c diff --git a/lib_arm/bootm.c b/arch/arm/lib/bootm.c similarity index 100% rename from lib_arm/bootm.c rename to arch/arm/lib/bootm.c diff --git a/lib_arm/cache-cp15.c b/arch/arm/lib/cache-cp15.c similarity index 100% rename from lib_arm/cache-cp15.c rename to arch/arm/lib/cache-cp15.c diff --git a/lib_arm/cache.c b/arch/arm/lib/cache.c similarity index 100% rename from lib_arm/cache.c rename to arch/arm/lib/cache.c diff --git a/lib_arm/div0.c b/arch/arm/lib/div0.c similarity index 100% rename from lib_arm/div0.c rename to arch/arm/lib/div0.c diff --git a/lib_arm/eabi_compat.c b/arch/arm/lib/eabi_compat.c similarity index 100% rename from lib_arm/eabi_compat.c rename to arch/arm/lib/eabi_compat.c diff --git a/lib_arm/interrupts.c b/arch/arm/lib/interrupts.c similarity index 100% rename from lib_arm/interrupts.c rename to arch/arm/lib/interrupts.c diff --git a/lib_arm/reset.c b/arch/arm/lib/reset.c similarity index 100% rename from lib_arm/reset.c rename to arch/arm/lib/reset.c diff --git a/lib_avr32/config.mk b/arch/avr32/config.mk similarity index 100% rename from lib_avr32/config.mk rename to arch/avr32/config.mk diff --git a/cpu/at32ap/Makefile b/arch/avr32/cpu/Makefile similarity index 100% rename from cpu/at32ap/Makefile rename to arch/avr32/cpu/Makefile diff --git a/cpu/at32ap/at32ap700x/Makefile b/arch/avr32/cpu/at32ap700x/Makefile similarity index 100% rename from cpu/at32ap/at32ap700x/Makefile rename to arch/avr32/cpu/at32ap700x/Makefile diff --git a/cpu/at32ap/at32ap700x/clk.c b/arch/avr32/cpu/at32ap700x/clk.c similarity index 100% rename from cpu/at32ap/at32ap700x/clk.c rename to arch/avr32/cpu/at32ap700x/clk.c diff --git a/cpu/at32ap/at32ap700x/portmux.c b/arch/avr32/cpu/at32ap700x/portmux.c similarity index 100% rename from cpu/at32ap/at32ap700x/portmux.c rename to arch/avr32/cpu/at32ap700x/portmux.c diff --git a/cpu/at32ap/at32ap700x/sm.h b/arch/avr32/cpu/at32ap700x/sm.h similarity index 100% rename from cpu/at32ap/at32ap700x/sm.h rename to arch/avr32/cpu/at32ap700x/sm.h diff --git a/cpu/at32ap/cache.c b/arch/avr32/cpu/cache.c similarity index 100% rename from cpu/at32ap/cache.c rename to arch/avr32/cpu/cache.c diff --git a/cpu/at32ap/config.mk b/arch/avr32/cpu/config.mk similarity index 100% rename from cpu/at32ap/config.mk rename to arch/avr32/cpu/config.mk diff --git a/cpu/at32ap/cpu.c b/arch/avr32/cpu/cpu.c similarity index 100% rename from cpu/at32ap/cpu.c rename to arch/avr32/cpu/cpu.c diff --git a/cpu/at32ap/exception.c b/arch/avr32/cpu/exception.c similarity index 100% rename from cpu/at32ap/exception.c rename to arch/avr32/cpu/exception.c diff --git a/cpu/at32ap/hsdramc.c b/arch/avr32/cpu/hsdramc.c similarity index 100% rename from cpu/at32ap/hsdramc.c rename to arch/avr32/cpu/hsdramc.c diff --git a/cpu/at32ap/hsdramc1.h b/arch/avr32/cpu/hsdramc1.h similarity index 100% rename from cpu/at32ap/hsdramc1.h rename to arch/avr32/cpu/hsdramc1.h diff --git a/cpu/at32ap/hsmc3.h b/arch/avr32/cpu/hsmc3.h similarity index 100% rename from cpu/at32ap/hsmc3.h rename to arch/avr32/cpu/hsmc3.h diff --git a/cpu/at32ap/interrupts.c b/arch/avr32/cpu/interrupts.c similarity index 100% rename from cpu/at32ap/interrupts.c rename to arch/avr32/cpu/interrupts.c diff --git a/cpu/at32ap/pio2.h b/arch/avr32/cpu/pio2.h similarity index 100% rename from cpu/at32ap/pio2.h rename to arch/avr32/cpu/pio2.h diff --git a/cpu/at32ap/portmux-gpio.c b/arch/avr32/cpu/portmux-gpio.c similarity index 100% rename from cpu/at32ap/portmux-gpio.c rename to arch/avr32/cpu/portmux-gpio.c diff --git a/cpu/at32ap/portmux-pio.c b/arch/avr32/cpu/portmux-pio.c similarity index 100% rename from cpu/at32ap/portmux-pio.c rename to arch/avr32/cpu/portmux-pio.c diff --git a/cpu/at32ap/start.S b/arch/avr32/cpu/start.S similarity index 100% rename from cpu/at32ap/start.S rename to arch/avr32/cpu/start.S diff --git a/include/asm-avr32/arch-at32ap700x/addrspace.h b/arch/avr32/include/asm/arch-at32ap700x/addrspace.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/addrspace.h rename to arch/avr32/include/asm/arch-at32ap700x/addrspace.h diff --git a/include/asm-avr32/arch-at32ap700x/cacheflush.h b/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/cacheflush.h rename to arch/avr32/include/asm/arch-at32ap700x/cacheflush.h diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/arch/avr32/include/asm/arch-at32ap700x/chip-features.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/chip-features.h rename to arch/avr32/include/asm/arch-at32ap700x/chip-features.h diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/arch/avr32/include/asm/arch-at32ap700x/clk.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/clk.h rename to arch/avr32/include/asm/arch-at32ap700x/clk.h diff --git a/include/asm-avr32/arch-at32ap700x/gpio-impl.h b/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/gpio-impl.h rename to arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/arch/avr32/include/asm/arch-at32ap700x/gpio.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/gpio.h rename to arch/avr32/include/asm/arch-at32ap700x/gpio.h diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix.h b/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/hmatrix.h rename to arch/avr32/include/asm/arch-at32ap700x/hmatrix.h diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/arch/avr32/include/asm/arch-at32ap700x/memory-map.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/memory-map.h rename to arch/avr32/include/asm/arch-at32ap700x/memory-map.h diff --git a/include/asm-avr32/arch-at32ap700x/portmux.h b/arch/avr32/include/asm/arch-at32ap700x/portmux.h similarity index 100% rename from include/asm-avr32/arch-at32ap700x/portmux.h rename to arch/avr32/include/asm/arch-at32ap700x/portmux.h diff --git a/include/asm-avr32/arch-common/portmux-gpio.h b/arch/avr32/include/asm/arch-common/portmux-gpio.h similarity index 100% rename from include/asm-avr32/arch-common/portmux-gpio.h rename to arch/avr32/include/asm/arch-common/portmux-gpio.h diff --git a/include/asm-avr32/arch-common/portmux-pio.h b/arch/avr32/include/asm/arch-common/portmux-pio.h similarity index 100% rename from include/asm-avr32/arch-common/portmux-pio.h rename to arch/avr32/include/asm/arch-common/portmux-pio.h diff --git a/include/asm-avr32/bitops.h b/arch/avr32/include/asm/bitops.h similarity index 100% rename from include/asm-avr32/bitops.h rename to arch/avr32/include/asm/bitops.h diff --git a/include/asm-avr32/byteorder.h b/arch/avr32/include/asm/byteorder.h similarity index 100% rename from include/asm-avr32/byteorder.h rename to arch/avr32/include/asm/byteorder.h diff --git a/include/asm-avr32/config.h b/arch/avr32/include/asm/config.h similarity index 100% rename from include/asm-avr32/config.h rename to arch/avr32/include/asm/config.h diff --git a/include/asm-avr32/dma-mapping.h b/arch/avr32/include/asm/dma-mapping.h similarity index 100% rename from include/asm-avr32/dma-mapping.h rename to arch/avr32/include/asm/dma-mapping.h diff --git a/include/asm-avr32/errno.h b/arch/avr32/include/asm/errno.h similarity index 100% rename from include/asm-avr32/errno.h rename to arch/avr32/include/asm/errno.h diff --git a/include/asm-avr32/global_data.h b/arch/avr32/include/asm/global_data.h similarity index 100% rename from include/asm-avr32/global_data.h rename to arch/avr32/include/asm/global_data.h diff --git a/include/asm-avr32/hmatrix-common.h b/arch/avr32/include/asm/hmatrix-common.h similarity index 100% rename from include/asm-avr32/hmatrix-common.h rename to arch/avr32/include/asm/hmatrix-common.h diff --git a/include/asm-avr32/initcalls.h b/arch/avr32/include/asm/initcalls.h similarity index 100% rename from include/asm-avr32/initcalls.h rename to arch/avr32/include/asm/initcalls.h diff --git a/include/asm-avr32/io.h b/arch/avr32/include/asm/io.h similarity index 100% rename from include/asm-avr32/io.h rename to arch/avr32/include/asm/io.h diff --git a/include/asm-avr32/posix_types.h b/arch/avr32/include/asm/posix_types.h similarity index 100% rename from include/asm-avr32/posix_types.h rename to arch/avr32/include/asm/posix_types.h diff --git a/include/asm-avr32/processor.h b/arch/avr32/include/asm/processor.h similarity index 100% rename from include/asm-avr32/processor.h rename to arch/avr32/include/asm/processor.h diff --git a/include/asm-avr32/ptrace.h b/arch/avr32/include/asm/ptrace.h similarity index 100% rename from include/asm-avr32/ptrace.h rename to arch/avr32/include/asm/ptrace.h diff --git a/include/asm-avr32/sdram.h b/arch/avr32/include/asm/sdram.h similarity index 100% rename from include/asm-avr32/sdram.h rename to arch/avr32/include/asm/sdram.h diff --git a/include/asm-avr32/sections.h b/arch/avr32/include/asm/sections.h similarity index 100% rename from include/asm-avr32/sections.h rename to arch/avr32/include/asm/sections.h diff --git a/include/asm-avr32/setup.h b/arch/avr32/include/asm/setup.h similarity index 100% rename from include/asm-avr32/setup.h rename to arch/avr32/include/asm/setup.h diff --git a/include/asm-avr32/string.h b/arch/avr32/include/asm/string.h similarity index 100% rename from include/asm-avr32/string.h rename to arch/avr32/include/asm/string.h diff --git a/include/asm-avr32/sysreg.h b/arch/avr32/include/asm/sysreg.h similarity index 100% rename from include/asm-avr32/sysreg.h rename to arch/avr32/include/asm/sysreg.h diff --git a/include/asm-avr32/types.h b/arch/avr32/include/asm/types.h similarity index 100% rename from include/asm-avr32/types.h rename to arch/avr32/include/asm/types.h diff --git a/include/asm-avr32/u-boot.h b/arch/avr32/include/asm/u-boot.h similarity index 100% rename from include/asm-avr32/u-boot.h rename to arch/avr32/include/asm/u-boot.h diff --git a/lib_avr32/Makefile b/arch/avr32/lib/Makefile similarity index 100% rename from lib_avr32/Makefile rename to arch/avr32/lib/Makefile diff --git a/lib_avr32/board.c b/arch/avr32/lib/board.c similarity index 100% rename from lib_avr32/board.c rename to arch/avr32/lib/board.c diff --git a/lib_avr32/bootm.c b/arch/avr32/lib/bootm.c similarity index 100% rename from lib_avr32/bootm.c rename to arch/avr32/lib/bootm.c diff --git a/lib_avr32/interrupts.c b/arch/avr32/lib/interrupts.c similarity index 100% rename from lib_avr32/interrupts.c rename to arch/avr32/lib/interrupts.c diff --git a/lib_avr32/memset.S b/arch/avr32/lib/memset.S similarity index 100% rename from lib_avr32/memset.S rename to arch/avr32/lib/memset.S diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk new file mode 100644 index 0000000000..137834e7ee --- /dev/null +++ b/arch/blackfin/config.mk @@ -0,0 +1,72 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CROSS_COMPILE ?= bfin-uclinux- + +STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin + +CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) +CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) +CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET))) +CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE))) + +PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic +PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN + +LDFLAGS += --gc-sections -m elf32bfin +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections + +ifneq (,$(CONFIG_BFIN_CPU)) +PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) +endif + +ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) +ALL += $(obj)u-boot.ldr +endif +ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) +CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o +else +CREATE_LDR_ENV = +endif + +SYM_PREFIX = _ + +LDR_FLAGS-y := +LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J + +LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE)) +LDR_FLAGS += --use-vmas +LDR_FLAGS += --initcode $(obj)$(CPUDIR)/initcode.o +ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART) +LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \ + --punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o +endif +ifneq (,$(findstring s,$(MAKEFLAGS))) +LDR_FLAGS += --quiet +endif + +LDR_FLAGS += $(LDR_FLAGS-y) + +ifeq ($(wildcard $(TOPDIR)/board/$(BOARD)/u-boot.lds*),) +LDSCRIPT = $(obj)arch/$(ARCH)/lib/u-boot.lds.S +endif diff --git a/cpu/blackfin/.gitignore b/arch/blackfin/cpu/.gitignore similarity index 100% rename from cpu/blackfin/.gitignore rename to arch/blackfin/cpu/.gitignore diff --git a/cpu/blackfin/Makefile b/arch/blackfin/cpu/Makefile similarity index 100% rename from cpu/blackfin/Makefile rename to arch/blackfin/cpu/Makefile diff --git a/cpu/blackfin/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk similarity index 100% rename from cpu/blackfin/bootrom-asm-offsets.awk rename to arch/blackfin/cpu/bootrom-asm-offsets.awk diff --git a/cpu/blackfin/bootrom-asm-offsets.c.in b/arch/blackfin/cpu/bootrom-asm-offsets.c.in similarity index 100% rename from cpu/blackfin/bootrom-asm-offsets.c.in rename to arch/blackfin/cpu/bootrom-asm-offsets.c.in diff --git a/cpu/blackfin/cache.S b/arch/blackfin/cpu/cache.S similarity index 100% rename from cpu/blackfin/cache.S rename to arch/blackfin/cpu/cache.S diff --git a/cpu/blackfin/cpu.c b/arch/blackfin/cpu/cpu.c similarity index 100% rename from cpu/blackfin/cpu.c rename to arch/blackfin/cpu/cpu.c diff --git a/cpu/blackfin/cpu.h b/arch/blackfin/cpu/cpu.h similarity index 100% rename from cpu/blackfin/cpu.h rename to arch/blackfin/cpu/cpu.h diff --git a/cpu/blackfin/initcode.c b/arch/blackfin/cpu/initcode.c similarity index 100% rename from cpu/blackfin/initcode.c rename to arch/blackfin/cpu/initcode.c diff --git a/cpu/blackfin/interrupt.S b/arch/blackfin/cpu/interrupt.S similarity index 100% rename from cpu/blackfin/interrupt.S rename to arch/blackfin/cpu/interrupt.S diff --git a/cpu/blackfin/interrupts.c b/arch/blackfin/cpu/interrupts.c similarity index 100% rename from cpu/blackfin/interrupts.c rename to arch/blackfin/cpu/interrupts.c diff --git a/cpu/blackfin/jtag-console.c b/arch/blackfin/cpu/jtag-console.c similarity index 100% rename from cpu/blackfin/jtag-console.c rename to arch/blackfin/cpu/jtag-console.c diff --git a/cpu/blackfin/os_log.c b/arch/blackfin/cpu/os_log.c similarity index 100% rename from cpu/blackfin/os_log.c rename to arch/blackfin/cpu/os_log.c diff --git a/cpu/blackfin/reset.c b/arch/blackfin/cpu/reset.c similarity index 100% rename from cpu/blackfin/reset.c rename to arch/blackfin/cpu/reset.c diff --git a/cpu/blackfin/serial.c b/arch/blackfin/cpu/serial.c similarity index 100% rename from cpu/blackfin/serial.c rename to arch/blackfin/cpu/serial.c diff --git a/cpu/blackfin/serial.h b/arch/blackfin/cpu/serial.h similarity index 100% rename from cpu/blackfin/serial.h rename to arch/blackfin/cpu/serial.h diff --git a/cpu/blackfin/start.S b/arch/blackfin/cpu/start.S similarity index 100% rename from cpu/blackfin/start.S rename to arch/blackfin/cpu/start.S diff --git a/cpu/blackfin/traps.c b/arch/blackfin/cpu/traps.c similarity index 100% rename from cpu/blackfin/traps.c rename to arch/blackfin/cpu/traps.c diff --git a/cpu/blackfin/watchdog.c b/arch/blackfin/cpu/watchdog.c similarity index 100% rename from cpu/blackfin/watchdog.c rename to arch/blackfin/cpu/watchdog.c diff --git a/include/asm-blackfin/bfin_logo_230x230.h b/arch/blackfin/include/asm/bfin_logo_230x230.h similarity index 100% rename from include/asm-blackfin/bfin_logo_230x230.h rename to arch/blackfin/include/asm/bfin_logo_230x230.h diff --git a/include/asm-blackfin/bfin_logo_rgb565_230x230.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h similarity index 100% rename from include/asm-blackfin/bfin_logo_rgb565_230x230.h rename to arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h diff --git a/include/asm-blackfin/bitops.h b/arch/blackfin/include/asm/bitops.h similarity index 100% rename from include/asm-blackfin/bitops.h rename to arch/blackfin/include/asm/bitops.h diff --git a/include/asm-blackfin/blackfin.h b/arch/blackfin/include/asm/blackfin.h similarity index 100% rename from include/asm-blackfin/blackfin.h rename to arch/blackfin/include/asm/blackfin.h diff --git a/include/asm-blackfin/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h similarity index 100% rename from include/asm-blackfin/blackfin_cdef.h rename to arch/blackfin/include/asm/blackfin_cdef.h diff --git a/include/asm-blackfin/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h similarity index 100% rename from include/asm-blackfin/blackfin_def.h rename to arch/blackfin/include/asm/blackfin_def.h diff --git a/include/asm-blackfin/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h similarity index 100% rename from include/asm-blackfin/blackfin_local.h rename to arch/blackfin/include/asm/blackfin_local.h diff --git a/include/asm-blackfin/byteorder.h b/arch/blackfin/include/asm/byteorder.h similarity index 100% rename from include/asm-blackfin/byteorder.h rename to arch/blackfin/include/asm/byteorder.h diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h new file mode 100644 index 0000000000..4531519d91 --- /dev/null +++ b/arch/blackfin/include/asm/config-pre.h @@ -0,0 +1,80 @@ +/* + * config-pre.h - common defines for Blackfin boards in config.h + * + * Copyright (c) 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__ +#define __ASM_BLACKFIN_CONFIG_PRE_H__ + +/* Misc helper functions */ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE. + * Depending on your cpu, some of these may not be valid, check your HRM. + * The actual values here are meaningless as long as they're unique. + */ +#define BFIN_BOOT_BYPASS 1 /* bypass bootrom */ +#define BFIN_BOOT_PARA 2 /* boot ldr out of parallel flash */ +#define BFIN_BOOT_SPI_MASTER 3 /* boot ldr out of serial flash */ +#define BFIN_BOOT_SPI_SLAVE 4 /* boot ldr as spi slave */ +#define BFIN_BOOT_TWI_MASTER 5 /* boot ldr over twi device */ +#define BFIN_BOOT_TWI_SLAVE 6 /* boot ldr over twi slave */ +#define BFIN_BOOT_UART 7 /* boot ldr over uart */ +#define BFIN_BOOT_IDLE 8 /* do nothing, just idle */ +#define BFIN_BOOT_FIFO 9 /* boot ldr out of FIFO */ +#define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */ +#define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */ +#define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */ +#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */ + +#ifndef __ASSEMBLY__ +static inline const char *get_bfin_boot_mode(int bfin_boot) +{ + switch (bfin_boot) { + case BFIN_BOOT_BYPASS: return "bypass"; + case BFIN_BOOT_PARA: return "parallel flash"; + case BFIN_BOOT_SPI_MASTER: return "spi flash"; + case BFIN_BOOT_SPI_SLAVE: return "spi slave"; + case BFIN_BOOT_TWI_MASTER: return "i2c flash"; + case BFIN_BOOT_TWI_SLAVE: return "i2c slave"; + case BFIN_BOOT_UART: return "uart"; + case BFIN_BOOT_IDLE: return "idle"; + case BFIN_BOOT_FIFO: return "fifo"; + case BFIN_BOOT_MEM: return "memory"; + case BFIN_BOOT_16HOST_DMA: return "16bit dma"; + case BFIN_BOOT_8HOST_DMA: return "8bit dma"; + case BFIN_BOOT_NAND: return "nand flash"; + default: return "INVALID"; + } +} +#endif + +/* Most bootroms allow for EVT1 redirection */ +#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \ + && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__) +# undef CONFIG_BFIN_BOOTROM_USES_EVT1 +#else +# define CONFIG_BFIN_BOOTROM_USES_EVT1 +#endif + +/* Define the default SPI CS used when booting out of SPI */ +#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \ + defined(__ADSPBF51x__) +# define BFIN_BOOT_SPI_SSEL 2 +#else +# define BFIN_BOOT_SPI_SSEL 1 +#endif + +/* There is no Blackfin/NetBSD port */ +#undef CONFIG_BOOTM_NETBSD + +/* We rarely use interrupts, so favor throughput over latency */ +#define CONFIG_BFIN_INS_LOWOVERHEAD + +#endif diff --git a/include/asm-blackfin/config.h b/arch/blackfin/include/asm/config.h similarity index 100% rename from include/asm-blackfin/config.h rename to arch/blackfin/include/asm/config.h diff --git a/include/asm-blackfin/cplb.h b/arch/blackfin/include/asm/cplb.h similarity index 100% rename from include/asm-blackfin/cplb.h rename to arch/blackfin/include/asm/cplb.h diff --git a/include/asm-blackfin/deferred.h b/arch/blackfin/include/asm/deferred.h similarity index 100% rename from include/asm-blackfin/deferred.h rename to arch/blackfin/include/asm/deferred.h diff --git a/include/asm-blackfin/delay.h b/arch/blackfin/include/asm/delay.h similarity index 100% rename from include/asm-blackfin/delay.h rename to arch/blackfin/include/asm/delay.h diff --git a/include/asm-blackfin/entry.h b/arch/blackfin/include/asm/entry.h similarity index 100% rename from include/asm-blackfin/entry.h rename to arch/blackfin/include/asm/entry.h diff --git a/include/asm-blackfin/errno.h b/arch/blackfin/include/asm/errno.h similarity index 100% rename from include/asm-blackfin/errno.h rename to arch/blackfin/include/asm/errno.h diff --git a/include/asm-blackfin/global_data.h b/arch/blackfin/include/asm/global_data.h similarity index 100% rename from include/asm-blackfin/global_data.h rename to arch/blackfin/include/asm/global_data.h diff --git a/include/asm-blackfin/io.h b/arch/blackfin/include/asm/io.h similarity index 100% rename from include/asm-blackfin/io.h rename to arch/blackfin/include/asm/io.h diff --git a/include/asm-blackfin/linkage.h b/arch/blackfin/include/asm/linkage.h similarity index 100% rename from include/asm-blackfin/linkage.h rename to arch/blackfin/include/asm/linkage.h diff --git a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h rename to arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h diff --git a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_def.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_def.h rename to arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h diff --git a/include/asm-blackfin/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf527/BF522_cdef.h rename to arch/blackfin/include/asm/mach-bf527/BF522_cdef.h diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h similarity index 100% rename from include/asm-blackfin/mach-bf527/BF522_def.h rename to arch/blackfin/include/asm/mach-bf527/BF522_def.h diff --git a/include/asm-blackfin/mach-bf527/BF523_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf527/BF523_cdef.h rename to arch/blackfin/include/asm/mach-bf527/BF523_cdef.h diff --git a/include/asm-blackfin/mach-bf527/BF523_def.h b/arch/blackfin/include/asm/mach-bf527/BF523_def.h similarity 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include/asm-blackfin/mach-bf527/BF527_def.h rename to arch/blackfin/include/asm/mach-bf527/BF527_def.h diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h similarity index 100% rename from include/asm-blackfin/mach-bf527/anomaly.h rename to arch/blackfin/include/asm/mach-bf527/anomaly.h diff --git a/include/asm-blackfin/mach-bf527/def_local.h b/arch/blackfin/include/asm/mach-bf527/def_local.h similarity index 100% rename from include/asm-blackfin/mach-bf527/def_local.h rename to arch/blackfin/include/asm/mach-bf527/def_local.h diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/arch/blackfin/include/asm/mach-bf527/mem_map.h similarity index 100% rename from include/asm-blackfin/mach-bf527/mem_map.h rename to arch/blackfin/include/asm/mach-bf527/mem_map.h diff --git a/include/asm-blackfin/mach-bf527/ports.h b/arch/blackfin/include/asm/mach-bf527/ports.h similarity index 100% rename from include/asm-blackfin/mach-bf527/ports.h rename to arch/blackfin/include/asm/mach-bf527/ports.h diff --git a/include/asm-blackfin/mach-bf533/BF531_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf533/BF531_cdef.h rename to arch/blackfin/include/asm/mach-bf533/BF531_cdef.h diff --git a/include/asm-blackfin/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h similarity index 100% rename from include/asm-blackfin/mach-bf533/BF531_def.h rename to arch/blackfin/include/asm/mach-bf533/BF531_def.h diff --git a/include/asm-blackfin/mach-bf533/BF532_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf533/BF532_cdef.h rename to arch/blackfin/include/asm/mach-bf533/BF532_cdef.h diff --git a/include/asm-blackfin/mach-bf533/BF532_def.h b/arch/blackfin/include/asm/mach-bf533/BF532_def.h similarity index 100% rename from include/asm-blackfin/mach-bf533/BF532_def.h rename to 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arch/blackfin/include/asm/mach-bf533/def_local.h diff --git a/include/asm-blackfin/mach-bf533/ports.h b/arch/blackfin/include/asm/mach-bf533/ports.h similarity index 100% rename from include/asm-blackfin/mach-bf533/ports.h rename to arch/blackfin/include/asm/mach-bf533/ports.h diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h rename to arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h rename to arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h diff --git a/include/asm-blackfin/mach-bf537/BF534_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf537/BF534_cdef.h rename to arch/blackfin/include/asm/mach-bf537/BF534_cdef.h diff --git a/include/asm-blackfin/mach-bf537/BF534_def.h b/arch/blackfin/include/asm/mach-bf537/BF534_def.h similarity index 100% rename from include/asm-blackfin/mach-bf537/BF534_def.h rename to arch/blackfin/include/asm/mach-bf537/BF534_def.h diff --git a/include/asm-blackfin/mach-bf537/BF536_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf537/BF536_cdef.h rename to arch/blackfin/include/asm/mach-bf537/BF536_cdef.h diff --git a/include/asm-blackfin/mach-bf537/BF536_def.h b/arch/blackfin/include/asm/mach-bf537/BF536_def.h similarity index 100% rename from include/asm-blackfin/mach-bf537/BF536_def.h rename to arch/blackfin/include/asm/mach-bf537/BF536_def.h diff --git a/include/asm-blackfin/mach-bf537/BF537_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf537/BF537_cdef.h rename to arch/blackfin/include/asm/mach-bf537/BF537_cdef.h diff --git a/include/asm-blackfin/mach-bf537/BF537_def.h b/arch/blackfin/include/asm/mach-bf537/BF537_def.h similarity index 100% rename from include/asm-blackfin/mach-bf537/BF537_def.h rename to arch/blackfin/include/asm/mach-bf537/BF537_def.h diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h similarity index 100% rename from include/asm-blackfin/mach-bf537/anomaly.h rename to arch/blackfin/include/asm/mach-bf537/anomaly.h diff --git a/include/asm-blackfin/mach-bf537/def_local.h b/arch/blackfin/include/asm/mach-bf537/def_local.h similarity index 100% rename from include/asm-blackfin/mach-bf537/def_local.h rename to arch/blackfin/include/asm/mach-bf537/def_local.h diff --git a/include/asm-blackfin/mach-bf537/ports.h b/arch/blackfin/include/asm/mach-bf537/ports.h similarity index 100% rename from include/asm-blackfin/mach-bf537/ports.h rename to arch/blackfin/include/asm/mach-bf537/ports.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_def.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_def.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_def.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_def.h rename to arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h diff --git a/include/asm-blackfin/mach-bf548/BF541_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF541_cdef.h rename to arch/blackfin/include/asm/mach-bf548/BF541_cdef.h diff --git a/include/asm-blackfin/mach-bf548/BF541_def.h b/arch/blackfin/include/asm/mach-bf548/BF541_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF541_def.h rename to arch/blackfin/include/asm/mach-bf548/BF541_def.h diff --git a/include/asm-blackfin/mach-bf548/BF542_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF542_cdef.h rename to arch/blackfin/include/asm/mach-bf548/BF542_cdef.h diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/arch/blackfin/include/asm/mach-bf548/BF542_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF542_def.h rename to arch/blackfin/include/asm/mach-bf548/BF542_def.h diff --git a/include/asm-blackfin/mach-bf548/BF544_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF544_cdef.h rename to arch/blackfin/include/asm/mach-bf548/BF544_cdef.h diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/arch/blackfin/include/asm/mach-bf548/BF544_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF544_def.h rename to arch/blackfin/include/asm/mach-bf548/BF544_def.h diff --git a/include/asm-blackfin/mach-bf548/BF547_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF547_cdef.h rename to arch/blackfin/include/asm/mach-bf548/BF547_cdef.h diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/arch/blackfin/include/asm/mach-bf548/BF547_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF547_def.h rename to arch/blackfin/include/asm/mach-bf548/BF547_def.h diff --git a/include/asm-blackfin/mach-bf548/BF548_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF548_cdef.h rename to arch/blackfin/include/asm/mach-bf548/BF548_cdef.h diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/arch/blackfin/include/asm/mach-bf548/BF548_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF548_def.h rename to arch/blackfin/include/asm/mach-bf548/BF548_def.h diff --git a/include/asm-blackfin/mach-bf548/BF549_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF549_cdef.h rename to arch/blackfin/include/asm/mach-bf548/BF549_cdef.h diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/arch/blackfin/include/asm/mach-bf548/BF549_def.h similarity index 100% rename from include/asm-blackfin/mach-bf548/BF549_def.h rename to arch/blackfin/include/asm/mach-bf548/BF549_def.h diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h similarity index 100% rename from include/asm-blackfin/mach-bf548/anomaly.h rename to arch/blackfin/include/asm/mach-bf548/anomaly.h diff --git a/include/asm-blackfin/mach-bf548/def_local.h b/arch/blackfin/include/asm/mach-bf548/def_local.h similarity index 100% rename from include/asm-blackfin/mach-bf548/def_local.h rename to arch/blackfin/include/asm/mach-bf548/def_local.h diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/arch/blackfin/include/asm/mach-bf548/mem_map.h similarity index 100% rename from include/asm-blackfin/mach-bf548/mem_map.h rename to arch/blackfin/include/asm/mach-bf548/mem_map.h diff --git a/include/asm-blackfin/mach-bf548/ports.h b/arch/blackfin/include/asm/mach-bf548/ports.h similarity index 100% rename from include/asm-blackfin/mach-bf548/ports.h rename to arch/blackfin/include/asm/mach-bf548/ports.h diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h similarity index 100% rename from include/asm-blackfin/mach-bf561/BF561_cdef.h rename to arch/blackfin/include/asm/mach-bf561/BF561_cdef.h diff --git a/include/asm-blackfin/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h similarity index 100% rename from include/asm-blackfin/mach-bf561/BF561_def.h rename to arch/blackfin/include/asm/mach-bf561/BF561_def.h diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h similarity index 100% rename from include/asm-blackfin/mach-bf561/anomaly.h rename to arch/blackfin/include/asm/mach-bf561/anomaly.h diff --git a/include/asm-blackfin/mach-bf561/def_local.h b/arch/blackfin/include/asm/mach-bf561/def_local.h similarity index 100% rename from include/asm-blackfin/mach-bf561/def_local.h rename to arch/blackfin/include/asm/mach-bf561/def_local.h diff --git a/include/asm-blackfin/mach-bf561/ports.h b/arch/blackfin/include/asm/mach-bf561/ports.h similarity index 100% rename from include/asm-blackfin/mach-bf561/ports.h rename to arch/blackfin/include/asm/mach-bf561/ports.h diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h rename to arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h rename to arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h similarity index 100% rename from include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h rename to arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h similarity index 100% rename from include/asm-blackfin/mach-common/ADSP-EDN-core_def.h rename to arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h similarity index 100% rename from include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h rename to arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_def.h similarity index 100% rename from include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h rename to arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_def.h diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/arch/blackfin/include/asm/mach-common/bits/bootrom.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/bootrom.h rename to arch/blackfin/include/asm/mach-common/bits/bootrom.h diff --git a/include/asm-blackfin/mach-common/bits/core.h b/arch/blackfin/include/asm/mach-common/bits/core.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/core.h rename to arch/blackfin/include/asm/mach-common/bits/core.h diff --git a/include/asm-blackfin/mach-common/bits/dma.h b/arch/blackfin/include/asm/mach-common/bits/dma.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/dma.h rename to arch/blackfin/include/asm/mach-common/bits/dma.h diff --git a/include/asm-blackfin/mach-common/bits/ebiu.h b/arch/blackfin/include/asm/mach-common/bits/ebiu.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ebiu.h rename to arch/blackfin/include/asm/mach-common/bits/ebiu.h diff --git a/include/asm-blackfin/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/emac.h rename to arch/blackfin/include/asm/mach-common/bits/emac.h diff --git a/include/asm-blackfin/mach-common/bits/eppi.h b/arch/blackfin/include/asm/mach-common/bits/eppi.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/eppi.h rename to arch/blackfin/include/asm/mach-common/bits/eppi.h diff --git a/include/asm-blackfin/mach-common/bits/lockbox.h b/arch/blackfin/include/asm/mach-common/bits/lockbox.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/lockbox.h rename to arch/blackfin/include/asm/mach-common/bits/lockbox.h diff --git a/include/asm-blackfin/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/mpu.h rename to arch/blackfin/include/asm/mach-common/bits/mpu.h diff --git a/include/asm-blackfin/mach-common/bits/otp.h b/arch/blackfin/include/asm/mach-common/bits/otp.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/otp.h rename to arch/blackfin/include/asm/mach-common/bits/otp.h diff --git a/include/asm-blackfin/mach-common/bits/pata.h b/arch/blackfin/include/asm/mach-common/bits/pata.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/pata.h rename to arch/blackfin/include/asm/mach-common/bits/pata.h diff --git a/include/asm-blackfin/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/pll.h rename to arch/blackfin/include/asm/mach-common/bits/pll.h diff --git a/include/asm-blackfin/mach-common/bits/ports-a.h b/arch/blackfin/include/asm/mach-common/bits/ports-a.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-a.h rename to arch/blackfin/include/asm/mach-common/bits/ports-a.h diff --git a/include/asm-blackfin/mach-common/bits/ports-b.h b/arch/blackfin/include/asm/mach-common/bits/ports-b.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-b.h rename to arch/blackfin/include/asm/mach-common/bits/ports-b.h diff --git a/include/asm-blackfin/mach-common/bits/ports-c.h b/arch/blackfin/include/asm/mach-common/bits/ports-c.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-c.h rename to arch/blackfin/include/asm/mach-common/bits/ports-c.h diff --git a/include/asm-blackfin/mach-common/bits/ports-d.h b/arch/blackfin/include/asm/mach-common/bits/ports-d.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-d.h rename to arch/blackfin/include/asm/mach-common/bits/ports-d.h diff --git a/include/asm-blackfin/mach-common/bits/ports-e.h b/arch/blackfin/include/asm/mach-common/bits/ports-e.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-e.h rename to arch/blackfin/include/asm/mach-common/bits/ports-e.h diff --git a/include/asm-blackfin/mach-common/bits/ports-f.h b/arch/blackfin/include/asm/mach-common/bits/ports-f.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-f.h rename to arch/blackfin/include/asm/mach-common/bits/ports-f.h diff --git a/include/asm-blackfin/mach-common/bits/ports-g.h b/arch/blackfin/include/asm/mach-common/bits/ports-g.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-g.h rename to arch/blackfin/include/asm/mach-common/bits/ports-g.h diff --git a/include/asm-blackfin/mach-common/bits/ports-h.h b/arch/blackfin/include/asm/mach-common/bits/ports-h.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-h.h rename to arch/blackfin/include/asm/mach-common/bits/ports-h.h diff --git a/include/asm-blackfin/mach-common/bits/ports-i.h b/arch/blackfin/include/asm/mach-common/bits/ports-i.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-i.h rename to arch/blackfin/include/asm/mach-common/bits/ports-i.h diff --git a/include/asm-blackfin/mach-common/bits/ports-j.h b/arch/blackfin/include/asm/mach-common/bits/ports-j.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ports-j.h rename to arch/blackfin/include/asm/mach-common/bits/ports-j.h diff --git a/include/asm-blackfin/mach-common/bits/ppi.h b/arch/blackfin/include/asm/mach-common/bits/ppi.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/ppi.h rename to arch/blackfin/include/asm/mach-common/bits/ppi.h diff --git a/include/asm-blackfin/mach-common/bits/rtc.h b/arch/blackfin/include/asm/mach-common/bits/rtc.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/rtc.h rename to arch/blackfin/include/asm/mach-common/bits/rtc.h diff --git a/include/asm-blackfin/mach-common/bits/sdh.h b/arch/blackfin/include/asm/mach-common/bits/sdh.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/sdh.h rename to arch/blackfin/include/asm/mach-common/bits/sdh.h diff --git a/include/asm-blackfin/mach-common/bits/spi.h b/arch/blackfin/include/asm/mach-common/bits/spi.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/spi.h rename to arch/blackfin/include/asm/mach-common/bits/spi.h diff --git a/include/asm-blackfin/mach-common/bits/sport.h b/arch/blackfin/include/asm/mach-common/bits/sport.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/sport.h rename to arch/blackfin/include/asm/mach-common/bits/sport.h diff --git a/include/asm-blackfin/mach-common/bits/timer.h b/arch/blackfin/include/asm/mach-common/bits/timer.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/timer.h rename to arch/blackfin/include/asm/mach-common/bits/timer.h diff --git a/include/asm-blackfin/mach-common/bits/trace.h b/arch/blackfin/include/asm/mach-common/bits/trace.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/trace.h rename to arch/blackfin/include/asm/mach-common/bits/trace.h diff --git a/include/asm-blackfin/mach-common/bits/twi.h b/arch/blackfin/include/asm/mach-common/bits/twi.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/twi.h rename to arch/blackfin/include/asm/mach-common/bits/twi.h diff --git a/include/asm-blackfin/mach-common/bits/uart.h b/arch/blackfin/include/asm/mach-common/bits/uart.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/uart.h rename to arch/blackfin/include/asm/mach-common/bits/uart.h diff --git a/include/asm-blackfin/mach-common/bits/usb.h b/arch/blackfin/include/asm/mach-common/bits/usb.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/usb.h rename to arch/blackfin/include/asm/mach-common/bits/usb.h diff --git a/include/asm-blackfin/mach-common/bits/watchdog.h b/arch/blackfin/include/asm/mach-common/bits/watchdog.h similarity index 100% rename from include/asm-blackfin/mach-common/bits/watchdog.h rename to arch/blackfin/include/asm/mach-common/bits/watchdog.h diff --git a/include/asm-blackfin/mem_map.h b/arch/blackfin/include/asm/mem_map.h similarity index 100% rename from include/asm-blackfin/mem_map.h rename to arch/blackfin/include/asm/mem_map.h diff --git a/include/asm-blackfin/net.h b/arch/blackfin/include/asm/net.h similarity index 100% rename from include/asm-blackfin/net.h rename to arch/blackfin/include/asm/net.h diff --git a/include/asm-blackfin/posix_types.h b/arch/blackfin/include/asm/posix_types.h similarity index 100% rename from include/asm-blackfin/posix_types.h rename to arch/blackfin/include/asm/posix_types.h diff --git a/include/asm-blackfin/processor.h b/arch/blackfin/include/asm/processor.h similarity index 100% rename from include/asm-blackfin/processor.h rename to arch/blackfin/include/asm/processor.h diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h new file mode 100644 index 0000000000..251d5e60c8 --- /dev/null +++ b/arch/blackfin/include/asm/ptrace.h @@ -0,0 +1,198 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_PTRACE_H +#define _BFIN_PTRACE_H + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 7 are data registers R0-R7 + * 8 - 15 are address registers P0-P7 + * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 + * 32 - 33 A registers A0 & A1 + * 34 - status register + * ----------------------------- + * + * We follows above, except: + * 32-33 --- Low 32-bit of A0&1 + * 34-35 --- High 8-bit of A0&1 + */ + +#ifndef __ASSEMBLY__ + +struct task_struct; + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long orig_pc; + long ipend; + long seqstat; + long rete; + long retn; + long retx; + long pc; /* PC == RETI */ + long rets; + long reserved; /* Used as scratch during system calls */ + long astat; + long lb1; + long lb0; + long lt1; + long lt0; + long lc1; + long lc0; + long a1w; + long a1x; + long a0w; + long a0x; + long b3; + long b2; + long b1; + long b0; + long l3; + long l2; + long l1; + long l0; + long m3; + long m2; + long m1; + long m0; + long i3; + long i2; + long i1; + long i0; + long usp; + long fp; + long p5; + long p4; + long p3; + long p2; + long p1; + long p0; + long r7; + long r6; + long r5; + long r4; + long r3; + long r2; + long r1; + long r0; + long orig_r0; + long orig_p0; + long syscfg; +}; + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 /* ptrace signal */ + +#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ +#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ +#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ + +#define PS_S (0x0002) + +#ifdef __KERNEL__ + +/* user_mode returns true if only one bit is set in IPEND, other than the + master interrupt enable. */ +#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1))) +#define instruction_pointer(regs) ((regs)->pc) +#define user_stack_pointer(regs) ((regs)->usp) +#define profile_pc(regs) instruction_pointer(regs) +extern void show_regs(struct pt_regs *); + +#define arch_has_single_step() (1) +extern void user_enable_single_step(struct task_struct *); +/* see arch/blackfin/kernel/ptrace.c about this redirect */ +#define user_disable_single_step(child) ptrace_disable(child) + +/* + * Get the address of the live pt_regs for the specified task. + * These are saved onto the top kernel stack when the process + * is not running. + * + * Note: if a user thread is execve'd from kernel space, the + * kernel stack will not be empty on entry to the kernel, so + * ptracing these tasks will fail. + */ +#define task_pt_regs(task) \ + (struct pt_regs *) \ + ((unsigned long)task_stack_page(task) + \ + (THREAD_SIZE - sizeof(struct pt_regs))) + +#endif /* __KERNEL__ */ + +#endif /* __ASSEMBLY__ */ + +/* + * Offsets used by 'ptrace' system call interface. + */ + +#define PT_R0 204 +#define PT_R1 200 +#define PT_R2 196 +#define PT_R3 192 +#define PT_R4 188 +#define PT_R5 184 +#define PT_R6 180 +#define PT_R7 176 +#define PT_P0 172 +#define PT_P1 168 +#define PT_P2 164 +#define PT_P3 160 +#define PT_P4 156 +#define PT_P5 152 +#define PT_FP 148 +#define PT_USP 144 +#define PT_I0 140 +#define PT_I1 136 +#define PT_I2 132 +#define PT_I3 128 +#define PT_M0 124 +#define PT_M1 120 +#define PT_M2 116 +#define PT_M3 112 +#define PT_L0 108 +#define PT_L1 104 +#define PT_L2 100 +#define PT_L3 96 +#define PT_B0 92 +#define PT_B1 88 +#define PT_B2 84 +#define PT_B3 80 +#define PT_A0X 76 +#define PT_A0W 72 +#define PT_A1X 68 +#define PT_A1W 64 +#define PT_LC0 60 +#define PT_LC1 56 +#define PT_LT0 52 +#define PT_LT1 48 +#define PT_LB0 44 +#define PT_LB1 40 +#define PT_ASTAT 36 +#define PT_RESERVED 32 +#define PT_RETS 28 +#define PT_PC 24 +#define PT_RETX 20 +#define PT_RETN 16 +#define PT_RETE 12 +#define PT_SEQSTAT 8 +#define PT_IPEND 4 + +#define PT_ORIG_R0 208 +#define PT_ORIG_P0 212 +#define PT_SYSCFG 216 +#define PT_TEXT_ADDR 220 +#define PT_TEXT_END_ADDR 224 +#define PT_DATA_ADDR 228 +#define PT_FDPIC_EXEC 232 +#define PT_FDPIC_INTERP 236 + +#endif /* _BFIN_PTRACE_H */ diff --git a/include/asm-blackfin/sdh.h b/arch/blackfin/include/asm/sdh.h similarity index 100% rename from include/asm-blackfin/sdh.h rename to arch/blackfin/include/asm/sdh.h diff --git a/include/asm-blackfin/shared_resources.h b/arch/blackfin/include/asm/shared_resources.h similarity index 100% rename from include/asm-blackfin/shared_resources.h rename to arch/blackfin/include/asm/shared_resources.h diff --git a/include/asm-blackfin/signal.h b/arch/blackfin/include/asm/signal.h similarity index 100% rename from include/asm-blackfin/signal.h rename to arch/blackfin/include/asm/signal.h diff --git a/include/asm-blackfin/string.h b/arch/blackfin/include/asm/string.h similarity index 100% rename from include/asm-blackfin/string.h rename to arch/blackfin/include/asm/string.h diff --git a/include/asm-blackfin/system.h b/arch/blackfin/include/asm/system.h similarity index 100% rename from include/asm-blackfin/system.h rename to arch/blackfin/include/asm/system.h diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h new file mode 100644 index 0000000000..7422d3d1be --- /dev/null +++ b/arch/blackfin/include/asm/traps.h @@ -0,0 +1,50 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * 2001 Lineo, Inc + * Tony Kou + * 1993 Hamish Macdonald + * + * Licensed under the GPL-2 + */ + +#ifndef _BFIN_TRAPS_H +#define _BFIN_TRAPS_H + +#define VEC_SYS (0) +#define VEC_EXCPT01 (1) +#define VEC_EXCPT02 (2) +#define VEC_EXCPT03 (3) +#define VEC_EXCPT04 (4) +#define VEC_EXCPT05 (5) +#define VEC_EXCPT06 (6) +#define VEC_EXCPT07 (7) +#define VEC_EXCPT08 (8) +#define VEC_EXCPT09 (9) +#define VEC_EXCPT10 (10) +#define VEC_EXCPT11 (11) +#define VEC_EXCPT12 (12) +#define VEC_EXCPT13 (13) +#define VEC_EXCPT14 (14) +#define VEC_EXCPT15 (15) +#define VEC_STEP (16) +#define VEC_OVFLOW (17) +#define VEC_UNDEF_I (33) +#define VEC_ILGAL_I (34) +#define VEC_CPLB_VL (35) +#define VEC_MISALI_D (36) +#define VEC_UNCOV (37) +#define VEC_CPLB_M (38) +#define VEC_CPLB_MHIT (39) +#define VEC_WATCH (40) +#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */ +#define VEC_MISALI_I (42) +#define VEC_CPLB_I_VL (43) +#define VEC_CPLB_I_M (44) +#define VEC_CPLB_I_MHIT (45) +#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ +/* The hardware reserves (63) for future use - we use it to tell our + * normal exception handling code we have a hardware error + */ +#define VEC_HWERR (63) + +#endif /* _BFIN_TRAPS_H */ diff --git a/include/asm-blackfin/types.h b/arch/blackfin/include/asm/types.h similarity index 100% rename from include/asm-blackfin/types.h rename to arch/blackfin/include/asm/types.h diff --git a/include/asm-blackfin/u-boot.h b/arch/blackfin/include/asm/u-boot.h similarity index 100% rename from include/asm-blackfin/u-boot.h rename to arch/blackfin/include/asm/u-boot.h diff --git a/include/asm-blackfin/unaligned.h b/arch/blackfin/include/asm/unaligned.h similarity index 100% rename from include/asm-blackfin/unaligned.h rename to arch/blackfin/include/asm/unaligned.h diff --git a/lib_blackfin/.gitignore b/arch/blackfin/lib/.gitignore similarity index 100% rename from lib_blackfin/.gitignore rename to arch/blackfin/lib/.gitignore diff --git a/lib_blackfin/Makefile b/arch/blackfin/lib/Makefile similarity index 100% rename from lib_blackfin/Makefile rename to arch/blackfin/lib/Makefile diff --git a/lib_blackfin/__kgdb.S b/arch/blackfin/lib/__kgdb.S similarity index 100% rename from lib_blackfin/__kgdb.S rename to arch/blackfin/lib/__kgdb.S diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c new file mode 100644 index 0000000000..4e9bb19226 --- /dev/null +++ b/arch/blackfin/lib/board.c @@ -0,0 +1,419 @@ +/* + * U-boot - board.c First C file to be called contains init routines + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_CMD_NAND +#include /* cannot even include nand.h if it isnt configured */ +#endif + +#ifdef CONFIG_BITBANGMII +#include +#endif + +#if defined(CONFIG_POST) +#include +int post_flag; +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")"; + +__attribute__((always_inline)) +static inline void serial_early_puts(const char *s) +{ +#ifdef CONFIG_DEBUG_EARLY_SERIAL + serial_puts("Early: "); + serial_puts(s); +#endif +} + +static int display_banner(void) +{ + printf("\n\n%s\n\n", version_string); + printf("CPU: ADSP " MK_STR(CONFIG_BFIN_CPU) " " + "(Detected Rev: 0.%d) " + "(%s boot)\n", + bfin_revid(), + get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE)); + return 0; +} + +static int init_baudrate(void) +{ + char baudrate[15]; + int i = getenv_r("baudrate", baudrate, sizeof(baudrate)); + gd->bd->bi_baudrate = gd->baudrate = (i > 0) + ? simple_strtoul(baudrate, NULL, 10) + : CONFIG_BAUDRATE; + return 0; +} + +static void display_global_data(void) +{ + bd_t *bd; + +#ifndef CONFIG_DEBUG_EARLY_SERIAL + return; +#endif + + bd = gd->bd; + printf(" gd: %p\n", gd); + printf(" |-flags: %lx\n", gd->flags); + printf(" |-board_type: %lx\n", gd->board_type); + printf(" |-baudrate: %lu\n", gd->baudrate); + printf(" |-have_console: %lx\n", gd->have_console); + printf(" |-ram_size: %lx\n", gd->ram_size); + printf(" |-env_addr: %lx\n", gd->env_addr); + printf(" |-env_valid: %lx\n", gd->env_valid); + printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt)); + printf(" \\-bd: %p\n", gd->bd); + printf(" |-bi_baudrate: %x\n", bd->bi_baudrate); + printf(" |-bi_ip_addr: %lx\n", bd->bi_ip_addr); + printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); + printf(" |-bi_memstart: %lx\n", bd->bi_memstart); + printf(" |-bi_memsize: %lx\n", bd->bi_memsize); + printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart); + printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize); + printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset); +} + +#define CPLB_PAGE_SIZE (4 * 1024 * 1024) +#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) +void init_cplbtables(void) +{ + volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; + volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA; + uint32_t extern_memory; + size_t i; + + void icplb_add(uint32_t addr, uint32_t data) + { + *(ICPLB_ADDR + i) = addr; + *(ICPLB_DATA + i) = data; + } + void dcplb_add(uint32_t addr, uint32_t data) + { + *(DCPLB_ADDR + i) = addr; + *(DCPLB_DATA + i) = data; + } + + /* populate a few common entries ... we'll let + * the memory map and cplb exception handler do + * the rest of the work. + */ + i = 0; + ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0; + ICPLB_DATA = (uint32_t *)ICPLB_DATA0; + DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0; + DCPLB_DATA = (uint32_t *)DCPLB_DATA0; + + icplb_add(0xFFA00000, L1_IMEMORY); + dcplb_add(0xFF800000, L1_DMEMORY); + ++i; + + if (CONFIG_MEM_SIZE) { + uint32_t mbase = CONFIG_SYS_MONITOR_BASE; + uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN; + mbase &= CPLB_PAGE_MASK; + mend &= CPLB_PAGE_MASK; + + icplb_add(mbase, SDRAM_IKERNEL); + dcplb_add(mbase, SDRAM_DKERNEL); + ++i; + + /* + * If the monitor crosses a 4 meg boundary, we'll need + * to lock two entries for it. We assume it doesn't + * cross two 4 meg boundaries ... + */ + if (mbase != mend) { + icplb_add(mend, SDRAM_IKERNEL); + dcplb_add(mend, SDRAM_DKERNEL); + ++i; + } + } + + icplb_add(0x20000000, SDRAM_INON_CHBL); + dcplb_add(0x20000000, SDRAM_EBIU); + ++i; + + /* Add entries for the rest of external RAM up to the bootrom */ + extern_memory = 0; + +#ifdef CONFIG_DEBUG_NULL_PTR + icplb_add(extern_memory, (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB); + dcplb_add(extern_memory, (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB); + ++i; + icplb_add(extern_memory, SDRAM_IKERNEL); + dcplb_add(extern_memory, SDRAM_DKERNEL); + extern_memory += CPLB_PAGE_SIZE; + ++i; +#endif + + while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) { + icplb_add(extern_memory, SDRAM_IGENERIC); + dcplb_add(extern_memory, SDRAM_DGENERIC); + extern_memory += CPLB_PAGE_SIZE; + ++i; + } + while (i < 16) { + icplb_add(0, 0); + dcplb_add(0, 0); + ++i; + } +} + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ + +extern int watchdog_init(void); +extern int exception_init(void); +extern int irq_init(void); +extern int timer_init(void); + +void board_init_f(ulong bootflag) +{ + ulong addr; + bd_t *bd; + char buf[32]; + +#ifdef CONFIG_BOARD_EARLY_INIT_F + serial_early_puts("Board early init flash\n"); + board_early_init_f(); +#endif + + serial_early_puts("Init CPLB tables\n"); + init_cplbtables(); + + serial_early_puts("Exceptions setup\n"); + exception_init(); + +#ifndef CONFIG_ICACHE_OFF + serial_early_puts("Turn on ICACHE\n"); + icache_enable(); +#endif +#ifndef CONFIG_DCACHE_OFF + serial_early_puts("Turn on DCACHE\n"); + dcache_enable(); +#endif + +#ifdef CONFIG_WATCHDOG + serial_early_puts("Setting up external watchdog\n"); + watchdog_init(); +#endif + +#ifdef DEBUG + if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd)) + hang(); +#endif + serial_early_puts("Init global data\n"); + gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR); + memset((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE); + + /* Board data initialization */ + addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t)); + + /* Align to 4 byte boundary */ + addr &= ~(4 - 1); + bd = (bd_t *) addr; + gd->bd = bd; + memset((void *)bd, 0, sizeof(bd_t)); + + bd->bi_r_version = version_string; + bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU); + bd->bi_board_name = BFIN_BOARD_NAME; + bd->bi_vco = get_vco(); + bd->bi_cclk = get_cclk(); + bd->bi_sclk = get_sclk(); + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + + /* Initialize */ + serial_early_puts("IRQ init\n"); + irq_init(); + serial_early_puts("Environment init\n"); + env_init(); + serial_early_puts("Baudrate init\n"); + init_baudrate(); + serial_early_puts("Serial init\n"); + serial_init(); + serial_early_puts("Console init flash\n"); + console_init_f(); + serial_early_puts("End of early debugging\n"); + display_banner(); + + checkboard(); + timer_init(); + + printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco())); + printf("Core: %s MHz, ", strmhz(buf, get_cclk())); + printf("System: %s MHz\n", strmhz(buf, get_sclk())); + + printf("RAM: "); + print_size(bd->bi_memsize, "\n"); +#if defined(CONFIG_POST) + post_init_f(); + post_bootmode_init(); + post_run(NULL, POST_ROM | post_bootmode_get(0)); +#endif + + board_init_r((gd_t *) gd, 0x20000010); +} + +static void board_net_init_r(bd_t *bd) +{ +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif +#ifdef CONFIG_CMD_NET + char *s; + + if ((s = getenv("bootfile")) != NULL) + copy_filename(BootFile, s, sizeof(BootFile)); + + bd->bi_ip_addr = getenv_IPaddr("ipaddr"); + + printf("Net: "); + eth_initialize(gd->bd); +#endif +} + +void board_init_r(gd_t * id, ulong dest_addr) +{ + char *s; + bd_t *bd; + gd = id; + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + bd = gd->bd; + +#if defined(CONFIG_POST) + post_output_backlog(); + post_reloc(); +#endif + + /* initialize malloc() area */ + mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); + +#if !defined(CONFIG_SYS_NO_FLASH) + /* Initialize the flash and protect u-boot by default */ + extern flash_info_t flash_info[]; + puts("Flash: "); + ulong size = flash_init(); + print_size(size, "\n"); + flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - 1, + &flash_info[0]); + bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; + bd->bi_flashsize = size; + bd->bi_flashoffset = 0; +#else + bd->bi_flashstart = 0; + bd->bi_flashsize = 0; + bd->bi_flashoffset = 0; +#endif + +#ifdef CONFIG_CMD_NAND + puts("NAND: "); + nand_init(); /* go init the NAND */ +#endif + +#ifdef CONFIG_GENERIC_MMC + puts("MMC: "); + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ + env_relocate(); + + /* Initialize stdio devices */ + stdio_init(); + jumptable_init(); + + /* Initialize the console (after the relocation and devices init) */ + console_init_r(); + +#ifdef CONFIG_CMD_KGDB + puts("KGDB: "); + kgdb_init(); +#endif + +#ifdef CONFIG_STATUS_LED + status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); + status_led_set(STATUS_LED_CRASH, STATUS_LED_OFF); +#endif + + /* Initialize from environment */ + if ((s = getenv("loadaddr")) != NULL) + load_addr = simple_strtoul(s, NULL, 16); + +#if defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r(); +#endif + + board_net_init_r(bd); + + display_global_data(); + +#if defined(CONFIG_POST) + if (post_flag) + post_run(NULL, POST_RAM | post_bootmode_get(0)); +#endif + + if (bfin_os_log_check()) { + puts("\nLog buffer from operating system:\n"); + bfin_os_log_dump(); + puts("\n"); + } + + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) + main_loop(); +} + +void hang(void) +{ +#ifdef CONFIG_STATUS_LED + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + status_led_set(STATUS_LED_CRASH, STATUS_LED_BLINKING); +#endif + puts("### ERROR ### Please RESET the board ###\n"); + while (1) + /* If a JTAG emulator is hooked up, we'll automatically trigger + * a breakpoint in it. If one isn't, this is just a NOP. + */ + asm("emuexcpt;"); +} diff --git a/lib_blackfin/boot.c b/arch/blackfin/lib/boot.c similarity index 100% rename from lib_blackfin/boot.c rename to arch/blackfin/lib/boot.c diff --git a/lib_blackfin/cache.c b/arch/blackfin/lib/cache.c similarity index 100% rename from lib_blackfin/cache.c rename to arch/blackfin/lib/cache.c diff --git a/lib_blackfin/clocks.c b/arch/blackfin/lib/clocks.c similarity index 100% rename from lib_blackfin/clocks.c rename to arch/blackfin/lib/clocks.c diff --git a/lib_blackfin/cmd_cache_dump.c b/arch/blackfin/lib/cmd_cache_dump.c similarity index 100% rename from lib_blackfin/cmd_cache_dump.c rename to arch/blackfin/lib/cmd_cache_dump.c diff --git a/lib_blackfin/ins.S b/arch/blackfin/lib/ins.S similarity index 100% rename from lib_blackfin/ins.S rename to arch/blackfin/lib/ins.S diff --git a/lib_blackfin/kgdb.c b/arch/blackfin/lib/kgdb.c similarity index 100% rename from lib_blackfin/kgdb.c rename to arch/blackfin/lib/kgdb.c diff --git a/lib_blackfin/kgdb.h b/arch/blackfin/lib/kgdb.h similarity index 100% rename from lib_blackfin/kgdb.h rename to arch/blackfin/lib/kgdb.h diff --git a/lib_blackfin/memcmp.S b/arch/blackfin/lib/memcmp.S similarity index 100% rename from lib_blackfin/memcmp.S rename to arch/blackfin/lib/memcmp.S diff --git a/lib_blackfin/memcpy.S b/arch/blackfin/lib/memcpy.S similarity index 100% rename from lib_blackfin/memcpy.S rename to arch/blackfin/lib/memcpy.S diff --git a/lib_blackfin/memmove.S b/arch/blackfin/lib/memmove.S similarity index 100% rename from lib_blackfin/memmove.S rename to arch/blackfin/lib/memmove.S diff --git a/lib_blackfin/memset.S b/arch/blackfin/lib/memset.S similarity index 100% rename from lib_blackfin/memset.S rename to arch/blackfin/lib/memset.S diff --git a/lib_blackfin/muldi3.c b/arch/blackfin/lib/muldi3.c similarity index 100% rename from lib_blackfin/muldi3.c rename to arch/blackfin/lib/muldi3.c diff --git a/lib_blackfin/outs.S b/arch/blackfin/lib/outs.S similarity index 100% rename from lib_blackfin/outs.S rename to arch/blackfin/lib/outs.S diff --git a/lib_blackfin/post.c b/arch/blackfin/lib/post.c similarity index 100% rename from lib_blackfin/post.c rename to arch/blackfin/lib/post.c diff --git a/lib_blackfin/string.c b/arch/blackfin/lib/string.c similarity index 100% rename from lib_blackfin/string.c rename to arch/blackfin/lib/string.c diff --git a/lib_blackfin/tests.c b/arch/blackfin/lib/tests.c similarity index 100% rename from lib_blackfin/tests.c rename to arch/blackfin/lib/tests.c diff --git a/arch/blackfin/lib/u-boot.lds.S b/arch/blackfin/lib/u-boot.lds.S new file mode 100644 index 0000000000..9163d20c29 --- /dev/null +++ b/arch/blackfin/lib/u-boot.lds.S @@ -0,0 +1,153 @@ +/* + * U-boot - u-boot.lds.S + * + * Copyright (c) 2005-2010 Analog Device Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#undef ALIGN +#undef ENTRY + +#ifndef LDS_BOARD_TEXT +# define LDS_BOARD_TEXT +#endif + +/* If we don't actually load anything into L1 data, this will avoid + * a syntax error. If we do actually load something into L1 data, + * we'll get a linker memory load error (which is what we'd want). + * This is here in the first place so we can quickly test building + * for different CPU's which may lack non-cache L1 data. + */ +#ifndef L1_DATA_B_SRAM +# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE +# define L1_DATA_B_SRAM_SIZE 0 +#endif + +/* The 0xC offset is so we don't clobber the tiny LDR jump block. */ +#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 +# define L1_CODE_ORIGIN L1_INST_SRAM +#else +# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC +#endif + +OUTPUT_ARCH(bfin) + +MEMORY +{ +#if CONFIG_MEM_SIZE + ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN +# define ram_code ram +# define ram_data ram +#else +# define ram_code l1_code +# define ram_data l1_data +#endif + l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE + l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE +} + +ENTRY(_start) +SECTIONS +{ + .text.pre : + { + arch/blackfin/cpu/start.o (.text .text.*) + + LDS_BOARD_TEXT + } >ram_code + + .text.init : + { + arch/blackfin/cpu/initcode.o (.text .text.*) + } >ram_code + __initcode_lma = LOADADDR(.text.init); + __initcode_len = SIZEOF(.text.init); + + .text : + { + *(.text .text.*) + } >ram_code + + .rodata : + { + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } >ram_data + + .data : + { + . = ALIGN(4); + *(.data .data.*) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } >ram_data + + .u_boot_cmd : + { + ___u_boot_cmd_start = .; + *(.u_boot_cmd) + ___u_boot_cmd_end = .; + } >ram_data + + .text_l1 : + { + . = ALIGN(4); + __stext_l1 = .; + *(.l1.text) + . = ALIGN(4); + __etext_l1 = .; + } >l1_code AT>ram_code + __text_l1_lma = LOADADDR(.text_l1); + __text_l1_len = SIZEOF(.text_l1); + ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!") + + .data_l1 : + { + . = ALIGN(4); + __sdata_l1 = .; + *(.l1.data) + *(.l1.bss) + . = ALIGN(4); + __edata_l1 = .; + } >l1_data AT>ram_data + __data_l1_lma = LOADADDR(.data_l1); + __data_l1_len = SIZEOF(.data_l1); + ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!") + + .bss : + { + . = ALIGN(4); + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss .bss.*) + *(COMMON) + } >ram_data + __bss_vma = ADDR(.bss); + __bss_len = SIZEOF(.bss); +} diff --git a/lib_i386/config.mk b/arch/i386/config.mk similarity index 100% rename from lib_i386/config.mk rename to arch/i386/config.mk diff --git a/cpu/i386/Makefile b/arch/i386/cpu/Makefile similarity index 100% rename from cpu/i386/Makefile rename to arch/i386/cpu/Makefile diff --git a/cpu/i386/config.mk b/arch/i386/cpu/config.mk similarity index 100% rename from cpu/i386/config.mk rename to arch/i386/cpu/config.mk diff --git a/cpu/i386/cpu.c b/arch/i386/cpu/cpu.c similarity index 100% rename from cpu/i386/cpu.c rename to arch/i386/cpu/cpu.c diff --git a/cpu/i386/interrupts.c b/arch/i386/cpu/interrupts.c similarity index 100% rename from cpu/i386/interrupts.c rename to arch/i386/cpu/interrupts.c diff --git a/cpu/i386/resetvec.S b/arch/i386/cpu/resetvec.S similarity index 100% rename from cpu/i386/resetvec.S rename to arch/i386/cpu/resetvec.S diff --git a/cpu/i386/sc520/Makefile b/arch/i386/cpu/sc520/Makefile similarity index 100% rename from cpu/i386/sc520/Makefile rename to arch/i386/cpu/sc520/Makefile diff --git a/cpu/i386/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c similarity index 100% rename from cpu/i386/sc520/sc520.c rename to arch/i386/cpu/sc520/sc520.c diff --git a/cpu/i386/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S similarity index 100% rename from cpu/i386/sc520/sc520_asm.S rename to arch/i386/cpu/sc520/sc520_asm.S diff --git a/cpu/i386/sc520/sc520_pci.c b/arch/i386/cpu/sc520/sc520_pci.c similarity index 100% rename from cpu/i386/sc520/sc520_pci.c rename to arch/i386/cpu/sc520/sc520_pci.c diff --git a/cpu/i386/sc520/sc520_ssi.c b/arch/i386/cpu/sc520/sc520_ssi.c similarity index 100% rename from cpu/i386/sc520/sc520_ssi.c rename to arch/i386/cpu/sc520/sc520_ssi.c diff --git a/cpu/i386/sc520/sc520_timer.c b/arch/i386/cpu/sc520/sc520_timer.c similarity index 100% rename from cpu/i386/sc520/sc520_timer.c rename to arch/i386/cpu/sc520/sc520_timer.c diff --git a/cpu/i386/serial.c b/arch/i386/cpu/serial.c similarity index 100% rename from cpu/i386/serial.c rename to arch/i386/cpu/serial.c diff --git a/cpu/i386/start.S b/arch/i386/cpu/start.S similarity index 100% rename from cpu/i386/start.S rename to arch/i386/cpu/start.S diff --git a/cpu/i386/start16.S b/arch/i386/cpu/start16.S similarity index 100% rename from cpu/i386/start16.S rename to arch/i386/cpu/start16.S diff --git a/include/asm-i386/bitops.h b/arch/i386/include/asm/bitops.h similarity index 100% rename from include/asm-i386/bitops.h rename to arch/i386/include/asm/bitops.h diff --git a/include/asm-i386/byteorder.h b/arch/i386/include/asm/byteorder.h similarity index 100% rename from include/asm-i386/byteorder.h rename to arch/i386/include/asm/byteorder.h diff --git a/include/asm-i386/config.h b/arch/i386/include/asm/config.h similarity index 100% rename from include/asm-i386/config.h rename to arch/i386/include/asm/config.h diff --git a/include/asm-i386/errno.h b/arch/i386/include/asm/errno.h similarity index 100% rename from include/asm-i386/errno.h rename to arch/i386/include/asm/errno.h diff --git a/include/asm-i386/global_data.h b/arch/i386/include/asm/global_data.h similarity index 100% rename from include/asm-i386/global_data.h rename to arch/i386/include/asm/global_data.h diff --git a/include/asm-i386/i8254.h b/arch/i386/include/asm/i8254.h similarity index 100% rename from include/asm-i386/i8254.h rename to arch/i386/include/asm/i8254.h diff --git a/include/asm-i386/i8259.h b/arch/i386/include/asm/i8259.h similarity index 100% rename from include/asm-i386/i8259.h rename to arch/i386/include/asm/i8259.h diff --git a/include/asm-i386/ibmpc.h b/arch/i386/include/asm/ibmpc.h similarity index 100% rename from include/asm-i386/ibmpc.h rename to arch/i386/include/asm/ibmpc.h diff --git a/include/asm-i386/ic/pci.h b/arch/i386/include/asm/ic/pci.h similarity index 100% rename from include/asm-i386/ic/pci.h rename to arch/i386/include/asm/ic/pci.h diff --git a/include/asm-i386/ic/sc520.h b/arch/i386/include/asm/ic/sc520.h similarity index 100% rename from include/asm-i386/ic/sc520.h rename to arch/i386/include/asm/ic/sc520.h diff --git a/include/asm-i386/ic/ssi.h b/arch/i386/include/asm/ic/ssi.h similarity index 100% rename from include/asm-i386/ic/ssi.h rename to arch/i386/include/asm/ic/ssi.h diff --git a/arch/i386/include/asm/interrupt.h b/arch/i386/include/asm/interrupt.h new file mode 100644 index 0000000000..07426fe6a7 --- /dev/null +++ b/arch/i386/include/asm/interrupt.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2009 + * Graeme Russ, graeme.russ@gmail.com + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_INTERRUPT_H_ +#define __ASM_INTERRUPT_H_ 1 + +/* arch/i386/cpu/interrupts.c */ +void set_vector(u8 intnum, void *routine); + +/* arch/i386/lib/interupts.c */ +void disable_irq(int irq); +void enable_irq(int irq); + +/* Architecture specific functions */ +void mask_irq(int irq); +void unmask_irq(int irq); +void specific_eoi(int irq); + +extern char exception_stack[]; + +#define __isr__ void __attribute__ ((regparm(0))) + +#endif diff --git a/include/asm-i386/io.h b/arch/i386/include/asm/io.h similarity index 100% rename from include/asm-i386/io.h rename to arch/i386/include/asm/io.h diff --git a/include/asm-i386/pci.h b/arch/i386/include/asm/pci.h similarity index 100% rename from include/asm-i386/pci.h rename to arch/i386/include/asm/pci.h diff --git a/include/asm-i386/posix_types.h b/arch/i386/include/asm/posix_types.h similarity index 100% rename from include/asm-i386/posix_types.h rename to arch/i386/include/asm/posix_types.h diff --git a/include/asm-i386/processor.h b/arch/i386/include/asm/processor.h similarity index 100% rename from include/asm-i386/processor.h rename to arch/i386/include/asm/processor.h diff --git a/include/asm-i386/ptrace.h b/arch/i386/include/asm/ptrace.h similarity index 100% rename from include/asm-i386/ptrace.h rename to arch/i386/include/asm/ptrace.h diff --git a/include/asm-i386/realmode.h b/arch/i386/include/asm/realmode.h similarity index 100% rename from include/asm-i386/realmode.h rename to arch/i386/include/asm/realmode.h diff --git a/include/asm-i386/string.h b/arch/i386/include/asm/string.h similarity index 100% rename from include/asm-i386/string.h rename to arch/i386/include/asm/string.h diff --git a/include/asm-i386/types.h b/arch/i386/include/asm/types.h similarity index 100% rename from include/asm-i386/types.h rename to arch/i386/include/asm/types.h diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h new file mode 100644 index 0000000000..521fd352bb --- /dev/null +++ b/arch/i386/include/asm/u-boot-i386.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_I386_H_ +#define _U_BOOT_I386_H_ 1 + +/* cpu/.../cpu.c */ +int cpu_init_r(void); +int cpu_init_f(void); + +/* cpu/.../timer.c */ +void timer_isr(void *); +typedef void (timer_fnc_t) (void); +int register_timer_isr (timer_fnc_t *isr_func); + +/* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */ +int timer_init(void); + +/* cpu/.../interrupts.c */ +int cpu_init_interrupts(void); + +/* board/.../... */ +int board_init(void); +int dram_init(void); + +void isa_unmap_rom(u32 addr); +u32 isa_map_rom(u32 bus_addr, int size); + +/* arch/i386/lib/... */ +int video_bios_init(void); +int video_init(void); + + +#endif /* _U_BOOT_I386_H_ */ diff --git a/include/asm-i386/u-boot.h b/arch/i386/include/asm/u-boot.h similarity index 100% rename from include/asm-i386/u-boot.h rename to arch/i386/include/asm/u-boot.h diff --git a/include/asm-i386/zimage.h b/arch/i386/include/asm/zimage.h similarity index 100% rename from include/asm-i386/zimage.h rename to arch/i386/include/asm/zimage.h diff --git a/lib_i386/Makefile b/arch/i386/lib/Makefile similarity index 100% rename from lib_i386/Makefile rename to arch/i386/lib/Makefile diff --git a/lib_i386/bios.S b/arch/i386/lib/bios.S similarity index 100% rename from lib_i386/bios.S rename to arch/i386/lib/bios.S diff --git a/lib_i386/bios.h b/arch/i386/lib/bios.h similarity index 100% rename from lib_i386/bios.h rename to arch/i386/lib/bios.h diff --git a/lib_i386/bios_pci.S b/arch/i386/lib/bios_pci.S similarity index 100% rename from lib_i386/bios_pci.S rename to arch/i386/lib/bios_pci.S diff --git a/lib_i386/bios_setup.c b/arch/i386/lib/bios_setup.c similarity index 100% rename from lib_i386/bios_setup.c rename to arch/i386/lib/bios_setup.c diff --git a/lib_i386/board.c b/arch/i386/lib/board.c similarity index 100% rename from lib_i386/board.c rename to arch/i386/lib/board.c diff --git a/lib_i386/bootm.c b/arch/i386/lib/bootm.c similarity index 100% rename from lib_i386/bootm.c rename to arch/i386/lib/bootm.c diff --git a/lib_i386/interrupts.c b/arch/i386/lib/interrupts.c similarity index 100% rename from lib_i386/interrupts.c rename to arch/i386/lib/interrupts.c diff --git a/lib_i386/pcat_interrupts.c b/arch/i386/lib/pcat_interrupts.c similarity index 100% rename from lib_i386/pcat_interrupts.c rename to arch/i386/lib/pcat_interrupts.c diff --git a/lib_i386/pcat_timer.c b/arch/i386/lib/pcat_timer.c similarity index 100% rename from lib_i386/pcat_timer.c rename to arch/i386/lib/pcat_timer.c diff --git a/lib_i386/pci.c b/arch/i386/lib/pci.c similarity index 100% rename from lib_i386/pci.c rename to arch/i386/lib/pci.c diff --git a/lib_i386/pci_type1.c b/arch/i386/lib/pci_type1.c similarity index 100% rename from lib_i386/pci_type1.c rename to arch/i386/lib/pci_type1.c diff --git a/lib_i386/realmode.c b/arch/i386/lib/realmode.c similarity index 100% rename from lib_i386/realmode.c rename to arch/i386/lib/realmode.c diff --git a/lib_i386/realmode_switch.S b/arch/i386/lib/realmode_switch.S similarity index 100% rename from lib_i386/realmode_switch.S rename to arch/i386/lib/realmode_switch.S diff --git a/lib_i386/timer.c b/arch/i386/lib/timer.c similarity index 100% rename from lib_i386/timer.c rename to arch/i386/lib/timer.c diff --git a/lib_i386/video.c b/arch/i386/lib/video.c similarity index 100% rename from lib_i386/video.c rename to arch/i386/lib/video.c diff --git a/lib_i386/video_bios.c b/arch/i386/lib/video_bios.c similarity index 100% rename from lib_i386/video_bios.c rename to arch/i386/lib/video_bios.c diff --git a/lib_i386/zimage.c b/arch/i386/lib/zimage.c similarity index 100% rename from lib_i386/zimage.c rename to arch/i386/lib/zimage.c diff --git a/lib_m68k/config.mk b/arch/m68k/config.mk similarity index 100% rename from lib_m68k/config.mk rename to arch/m68k/config.mk diff --git a/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile similarity index 100% rename from cpu/mcf5227x/Makefile rename to arch/m68k/cpu/mcf5227x/Makefile diff --git a/cpu/mcf5227x/config.mk b/arch/m68k/cpu/mcf5227x/config.mk similarity index 100% rename from cpu/mcf5227x/config.mk rename to arch/m68k/cpu/mcf5227x/config.mk diff --git a/cpu/mcf5227x/cpu.c b/arch/m68k/cpu/mcf5227x/cpu.c similarity index 100% rename from cpu/mcf5227x/cpu.c rename to arch/m68k/cpu/mcf5227x/cpu.c diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c new file mode 100644 index 0000000000..beb78f5839 --- /dev/null +++ b/arch/m68k/cpu/mcf5227x/cpu_init.c @@ -0,0 +1,206 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + +#if !defined(CONFIG_CF_SBF) + /* Workaround, must place before fbcs */ + pll->psr = 0x12; + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + scm1->pacri = 0; + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ + && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; +#endif +#endif /* CONFIG_CF_SBF */ + +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ + && defined(CONFIG_SYS_CS1_CTRL)) + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; +#endif + +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ + && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; +#endif + +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ + && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; +#endif + +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ + && defined(CONFIG_SYS_CS4_CTRL)) + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; +#endif + +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ + && defined(CONFIG_SYS_CS5_CTRL)) + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFRTC + volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); + volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + + rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; +#endif + + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->par_uart &= + (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK); + gpio->par_uart |= + (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + break; + case 1: + gpio->par_uart &= + (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK); + gpio->par_uart |= + (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + break; + case 2: + gpio->par_dspi &= + (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK); + gpio->par_dspi = + (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); + break; + } +} + +#ifdef CONFIG_CF_DSPI +void cfspi_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_dspi = + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK; +} + +int cfspi_claim_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + return -1; + + /* Clear FIFO and resume transfer */ + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 2: + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; + gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; + break; + } + + return 0; +} + +void cfspi_release_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 2: + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; + break; + } +} +#endif diff --git a/cpu/mcf5227x/interrupts.c b/arch/m68k/cpu/mcf5227x/interrupts.c similarity index 100% rename from cpu/mcf5227x/interrupts.c rename to arch/m68k/cpu/mcf5227x/interrupts.c diff --git a/cpu/mcf5227x/speed.c b/arch/m68k/cpu/mcf5227x/speed.c similarity index 100% rename from cpu/mcf5227x/speed.c rename to arch/m68k/cpu/mcf5227x/speed.c diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S new file mode 100644 index 0000000000..30428f15d8 --- /dev/null +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -0,0 +1,513 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "version.h" +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +#if defined(CONFIG_CF_SBF) +#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#endif + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +#if defined(CONFIG_CF_SBF) +INITSP: .long 0 /* Initial SP */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ +#else +INITSP: .long 0 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +#endif + +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +#if !defined(CONFIG_CF_SBF) +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +#endif + +#if defined(CONFIG_CF_SBF) + /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ +asm_sbf_img_hdr: + .long 0x00000000 /* checksum, not yet implemented */ + .long 0x00020000 /* image length */ + .long TEXT_BASE /* image to be relocated at */ + +asm_dram_init: + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 /* init Rambar */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + /* Must disable global address */ + move.l #0xFC008000, %a1 + move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #0xFC008008, %a1 + move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #0xFC008004, %a1 + move.l #(CONFIG_SYS_CS0_MASK), (%a1) + + /* + * Dram Initialization + * a1, a2, and d0 + */ + /* mscr sdram */ + move.l #0xFC0A4074, %a1 + move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) + nop + + /* SDRAM Chip 0 and 1 */ + move.l #0xFC0B8110, %a1 + move.l #0xFC0B8114, %a2 + + /* calculate the size */ + move.l #0x13, %d1 + move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 +#ifdef CONFIG_SYS_SDRAM_BASE1 + lsr.l #1, %d2 +#endif + +dramsz_loop: + lsr.l #1, %d2 + add.l #1, %d1 + cmp.l #1, %d2 + bne dramsz_loop + + /* SDRAM Chip 0 and 1 */ + move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) + or.l %d1, (%a1) +#ifdef CONFIG_SYS_SDRAM_BASE1 + move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) + or.l %d1, (%a2) +#endif + nop + + /* dram cfg1 and cfg2 */ + move.l #0xFC0B8008, %a1 + move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) + nop + move.l #0xFC0B800C, %a2 + move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) + nop + + move.l #0xFC0B8000, %a1 /* Mode */ + move.l #0xFC0B8004, %a2 /* Ctrl */ + + /* Issue PALL */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) + nop + + /* Issue LEMR */ + move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) + nop + move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) + nop + + move.l #1000, %d0 +wait1000: + nop + subq.l #1, %d0 + bne wait1000 + + /* Issue PALL */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) + nop + + /* Perform two refresh cycles */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 + nop + move.l %d0, (%a2) + move.l %d0, (%a2) + nop + + move.l #(CONFIG_SYS_SDRAM_CTRL), %d0 + and.l #0x7FFFFFFF, %d0 + or.l #0x10000c00, %d0 + move.l %d0, (%a2) + nop + + /* + * DSPI Initialization + * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h + * a1 - dspi status + * a2 - dtfr + * a3 - drfr + * a4 - Dst addr + */ + + /* Enable pins for DSPI mode - chip-selects are enabled later */ + move.l #0xFC0A4036, %a0 + move.b #0x3F, %d0 + move.b %d0, (%a0) + + /* DSPI CS */ +#ifdef CONFIG_SYS_DSPI_CS0 + move.b (%a0), %d0 + or.l #0xC0, %d0 + move.b %d0, (%a0) +#endif +#ifdef CONFIG_SYS_DSPI_CS2 + move.l #0xFC0A4037, %a0 + move.b (%a0), %d0 + or.l #0x10, %d0 + move.b %d0, (%a0) +#endif + nop + + /* Configure DSPI module */ + move.l #0xFC05C000, %a0 + move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ + + move.l #0xFC05C00C, %a0 + move.l #0x3E000011, (%a0) + + move.l #0xFC05C034, %a2 /* dtfr */ + move.l #0xFC05C03B, %a3 /* drfr */ + + move.l #(ASM_SBF_IMG_HDR + 4), %a1 + move.l (%a1)+, %d5 + move.l (%a1), %a4 + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 + move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 + + move.l #0xFC05C02C, %a1 /* dspi status */ + + /* Issue commands and address */ + move.l #0x8004000B, %d2 /* Fast Read Cmd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80040000, %d2 /* Address byte 2 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80040000, %d2 /* Address byte 1 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80040000, %d2 /* Address byte 0 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80040000, %d2 /* Dummy Wr and Rd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* Transfer serial boot header to sram */ +asm_dspi_rd_loop1: + move.l #0x80040000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a0) /* read, copy to dst */ + + add.l #1, %a0 /* inc dst by 1 */ + sub.l #1, %d4 /* dec cnt by 1 */ + bne asm_dspi_rd_loop1 + + /* Transfer u-boot from serial flash to memory */ +asm_dspi_rd_loop2: + move.l #0x80040000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a4) /* read, copy to dst */ + + add.l #1, %a4 /* inc dst by 1 */ + sub.l #1, %d5 /* dec cnt by 1 */ + bne asm_dspi_rd_loop2 + + move.l #0x00040000, %d2 /* Terminate */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* jump to memory and execute */ + move.l #(TEXT_BASE + 0x400), %a0 + move.l %a0, (%a1) + jmp (%a0) + +asm_dspi_wr_status: + move.l (%a1), %d0 /* status */ + and.l #0x0000F000, %d0 + cmp.l #0x00003000, %d0 + bgt asm_dspi_wr_status + + move.l %d2, (%a2) + rts + +asm_dspi_rd_status: + move.l (%a1), %d0 /* status */ + and.l #0x000000F0, %d0 + lsr.l #4, %d0 + cmp.l #0, %d0 + beq asm_dspi_rd_status + + move.b (%a3), %d1 + rts +#endif /* CONFIG_CF_SBF */ + + .text + . = 0x400 + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ +#if defined(CONFIG_CF_SBF) + move.l #TEXT_BASE, %d0 + movec %d0, %VBR +#else + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 +#endif + + /* invalidate and disable cache */ + move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for + the first c-code */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf523x/Makefile b/arch/m68k/cpu/mcf523x/Makefile similarity index 100% rename from cpu/mcf523x/Makefile rename to arch/m68k/cpu/mcf523x/Makefile diff --git a/cpu/mcf523x/config.mk b/arch/m68k/cpu/mcf523x/config.mk similarity index 100% rename from cpu/mcf523x/config.mk rename to arch/m68k/cpu/mcf523x/config.mk diff --git a/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c similarity index 100% rename from cpu/mcf523x/cpu.c rename to arch/m68k/cpu/mcf523x/cpu.c diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c new file mode 100644 index 0000000000..0f299f0c3c --- /dev/null +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -0,0 +1,179 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + volatile scm_t *scm = (scm_t *) MMAP_SCM; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + wdog->cr = 0; +#endif + + scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + + /* Port configuration */ + gpio->par_cs = 0; + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; +#endif + +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS1; + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; +#endif + +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS2; + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; +#endif + +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS3; + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; +#endif + +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS4; + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; +#endif + +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS5; + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; +#endif + +#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS6; + fbcs->csar6 = CONFIG_SYS_CS6_BASE; + fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; + fbcs->csmr6 = CONFIG_SYS_CS6_MASK; +#endif + +#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) + gpio->par_cs |= GPIO_PAR_CS_CS7; + fbcs->csar7 = CONFIG_SYS_CS7_BASE; + fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; + fbcs->csmr7 = CONFIG_SYS_CS7_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; + CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + break; + case 1: + gpio->par_uart &= + ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK); + gpio->par_uart |= + (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + break; + case 2: +#ifdef CONFIG_SYS_UART2_PRI_GPIO + gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); +#elif defined(CONFIG_SYS_UART2_ALT1_GPIO) + gpio->feci2c &= + ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + gpio->feci2c |= + (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD); +#endif + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_EMDC_FECEMDC | + GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + } + + return 0; +} +#endif diff --git a/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c similarity index 100% rename from cpu/mcf523x/interrupts.c rename to arch/m68k/cpu/mcf523x/interrupts.c diff --git a/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c similarity index 100% rename from cpu/mcf523x/speed.c rename to arch/m68k/cpu/mcf523x/speed.c diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S new file mode 100644 index 0000000000..20b50e7579 --- /dev/null +++ b/arch/m68k/cpu/mcf523x/start.S @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "version.h" +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + /* invalidate and disable cache */ + move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + nop + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the + first c-code */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf52x2/Makefile b/arch/m68k/cpu/mcf52x2/Makefile similarity index 100% rename from cpu/mcf52x2/Makefile rename to arch/m68k/cpu/mcf52x2/Makefile diff --git a/cpu/mcf52x2/config.mk b/arch/m68k/cpu/mcf52x2/config.mk similarity index 100% rename from cpu/mcf52x2/config.mk rename to arch/m68k/cpu/mcf52x2/config.mk diff --git a/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c similarity index 100% rename from cpu/mcf52x2/cpu.c rename to arch/m68k/cpu/mcf52x2/cpu.c diff --git a/cpu/mcf52x2/cpu.h b/arch/m68k/cpu/mcf52x2/cpu.h similarity index 100% rename from cpu/mcf52x2/cpu.h rename to arch/m68k/cpu/mcf52x2/cpu.h diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c new file mode 100644 index 0000000000..170bbfc356 --- /dev/null +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -0,0 +1,747 @@ +/* + * (C) Copyright 2003 + * Josef Baumgartner + * + * MCF5282 additionals + * (C) Copyright 2005 + * BuS Elektronik GmbH & Co. KG + * (c) Copyright 2010 + * Arcturus Networks Inc. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * Hayden Fraser (Hayden.Fraser@freescale.com) + * + * MCF5275 additions + * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + +#ifndef CONFIG_M5272 +/* Only 5272 Flexbus chipselect is different from the rest */ +void init_fbcs(void) +{ + volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ + && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; +#else +#warning "Chip Select 0 are not initialized/used" +#endif +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ + && defined(CONFIG_SYS_CS1_CTRL)) + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; +#endif +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ + && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; +#endif +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ + && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; +#endif +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ + && defined(CONFIG_SYS_CS4_CTRL)) + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; +#endif +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ + && defined(CONFIG_SYS_CS5_CTRL)) + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; +#endif +#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ + && defined(CONFIG_SYS_CS6_CTRL)) + fbcs->csar6 = CONFIG_SYS_CS6_BASE; + fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; + fbcs->csmr6 = CONFIG_SYS_CS6_MASK; +#endif +#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ + && defined(CONFIG_SYS_CS7_CTRL)) + fbcs->csar7 = CONFIG_SYS_CS7_BASE; + fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; + fbcs->csmr7 = CONFIG_SYS_CS7_MASK; +#endif +} +#endif + +#if defined(CONFIG_M5208) +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + +#ifndef CONFIG_WATCHDOG + volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG; + + /* Disable the watchdog if we aren't using it */ + wdg->cr = 0; +#endif + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + + /* FlexBus Chipselect */ + init_fbcs(); + + icache_enable(); +} + +/* initialize higher level parts of CPU like timers */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->par_uart &= GPIO_PAR_UART0_UNMASK; + gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + break; + case 1: + gpio->par_uart &= GPIO_PAR_UART0_UNMASK; + gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); + break; + case 2: +#ifdef CONFIG_SYS_UART2_PRI_GPIO + gpio->par_timer &= + (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK); + gpio->par_timer |= + (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); +#endif +#ifdef CONFIG_SYS_UART2_ALT1_GPIO + gpio->par_feci2c &= + (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK); + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); +#endif +#ifdef CONFIG_SYS_UART2_ALT1_GPIO + gpio->par_feci2c &= + (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); +#endif + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO; + } else { + gpio->par_fec &= + (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK); + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK; + } + return 0; +} +#endif /* CONFIG_CMD_NET */ +#endif /* CONFIG_M5208 */ + +#if defined(CONFIG_M5253) +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_SYPCR, 0x00); + mbar_writeByte(MCFSIM_SWIVR, 0x0f); + mbar_writeByte(MCFSIM_SWSR, 0x00); + mbar_writeByte(MCFSIM_SWDICR, 0x00); + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); + mbar_writeByte(MCFSIM_I2CICR, 0x00); + mbar_writeByte(MCFSIM_UART1ICR, 0x00); + mbar_writeByte(MCFSIM_UART2ICR, 0x00); + mbar_writeByte(MCFSIM_ICR6, 0x00); + mbar_writeByte(MCFSIM_ICR7, 0x00); + mbar_writeByte(MCFSIM_ICR8, 0x00); + mbar_writeByte(MCFSIM_ICR9, 0x00); + mbar_writeByte(MCFSIM_QSPIICR, 0x00); + + mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); + mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ + mbar2_writeByte(MCFSIM_SPURVEC, 0x00); + + /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ + + /* FlexBus Chipselect */ + init_fbcs(); + +#ifdef CONFIG_FSL_I2C + CONFIG_SYS_I2C_PINMUX_REG = + CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; + CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; +#ifdef CONFIG_SYS_I2C2_OFFSET + CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; + CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; +#endif +#endif + + /* enable instruction cache now */ + icache_enable(); +} + +/*initialize higher level parts of CPU like timers */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ + volatile u32 *par = (u32 *) MMAP_PAR; + + /* Setup Ports: */ + switch (port) { + case 1: + *par &= 0xFFE7FFFF; + *par |= 0x00180000; + break; + case 2: + *par &= 0xFFFFFFFC; + *par &= 0x00000003; + break; + } +} +#endif /* #if defined(CONFIG_M5253) */ + +#if defined(CONFIG_M5271) +void cpu_init_f(void) +{ +#ifndef CONFIG_WATCHDOG + /* Disable the watchdog if we aren't using it */ + mbar_writeShort(MCF_WTM_WCR, 0); +#endif + + /* FlexBus Chipselect */ + init_fbcs(); + +#ifdef CONFIG_SYS_MCF_SYNCR + /* Set clockspeed according to board header file */ + mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); +#else + /* Set clockspeed to 100MHz */ + mbar_writeLong(MCF_FMPLL_SYNCR, + MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); +#endif + while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ + u16 temp; + + /* Setup Ports: */ + switch (port) { + case 0: + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3; + temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); + break; + case 1: + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF; + temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); + break; + case 2: + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF; + temp |= (0x3000); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, + (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0)); + } else { + } + + return 0; +} +#endif /* CONFIG_CMD_NET */ +#endif + +#if defined(CONFIG_M5272) +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + /* if we come from RAM we assume the CPU is + * already initialized. + */ +#ifndef CONFIG_MONITOR_IS_IN_RAM + volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); + volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); + volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); + + sysctrl->sc_scr = CONFIG_SYS_SCR; + sysctrl->sc_spr = CONFIG_SYS_SPR; + + /* Setup Ports: */ + gpio->gpio_pacnt = CONFIG_SYS_PACNT; + gpio->gpio_paddr = CONFIG_SYS_PADDR; + gpio->gpio_padat = CONFIG_SYS_PADAT; + gpio->gpio_pbcnt = CONFIG_SYS_PBCNT; + gpio->gpio_pbddr = CONFIG_SYS_PBDDR; + gpio->gpio_pbdat = CONFIG_SYS_PBDAT; + gpio->gpio_pdcnt = CONFIG_SYS_PDCNT; + + /* Memory Controller: */ + csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM; + csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM; + +#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) + csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM; + csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) + csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM; + csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) + csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM; + csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) + csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM; + csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) + csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM; + csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) + csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM; + csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM; +#endif + +#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) + csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM; + csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM; +#endif + +#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ + + /* enable instruction cache now */ + icache_enable(); + +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); + gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); + break; + case 1: + gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); + gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | + GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | + GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | + GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} +#endif /* CONFIG_CMD_NET */ +#endif /* #if defined(CONFIG_M5272) */ + +#if defined(CONFIG_M5275) + +/* + * Breathe some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + /* + * if we come from RAM we assume the CPU is + * already initialized. + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM + volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); + volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); + + /* Kill watchdog so we can initialize the PLL */ + wdog_reg->wcr = 0; + + /* FlexBus Chipselect */ + init_fbcs(); +#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ + +#ifdef CONFIG_FSL_I2C + CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; + CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; +#endif + + /* enable instruction cache now */ + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->par_uart &= ~UART0_ENABLE_MASK; + gpio->par_uart |= UART0_ENABLE_MASK; + break; + case 1: + gpio->par_uart &= ~UART1_ENABLE_MASK; + gpio->par_uart |= UART1_ENABLE_MASK; + break; + case 2: + gpio->par_uart &= ~UART2_ENABLE_MASK; + gpio->par_uart |= UART2_ENABLE_MASK; + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + struct fec_info_s *info = (struct fec_info_s *) dev->priv; + volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; + + if (setclear) { + /* Enable Ethernet pins */ + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + gpio->par_feci2c |= 0x0F00; + gpio->par_fec0hl |= 0xC0; + } else { + gpio->par_feci2c |= 0x00A0; + gpio->par_fec1hl |= 0xC0; + } + } else { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + gpio->par_feci2c &= ~0x0F00; + gpio->par_fec0hl &= ~0xC0; + } else { + gpio->par_feci2c &= ~0x00A0; + gpio->par_fec1hl &= ~0xC0; + } + } + + return 0; +} +#endif /* CONFIG_CMD_NET */ +#endif /* #if defined(CONFIG_M5275) */ + +#if defined(CONFIG_M5282) +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ +#ifndef CONFIG_WATCHDOG + /* disable watchdog if we aren't using it */ + MCFWTM_WCR = 0; +#endif + +#ifndef CONFIG_MONITOR_IS_IN_RAM + /* Set speed /PLL */ + MCFCLOCK_SYNCR = + MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | + MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); + while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; + + MCFGPIO_PBCDPAR = 0xc0; + + /* Set up the GPIO ports */ +#ifdef CONFIG_SYS_PEPAR + MCFGPIO_PEPAR = CONFIG_SYS_PEPAR; +#endif +#ifdef CONFIG_SYS_PFPAR + MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; +#endif +#ifdef CONFIG_SYS_PJPAR + MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; +#endif +#ifdef CONFIG_SYS_PSDPAR + MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; +#endif +#ifdef CONFIG_SYS_PASPAR + MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; +#endif +#ifdef CONFIG_SYS_PEHLPAR + MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; +#endif +#ifdef CONFIG_SYS_PQSPAR + MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; +#endif +#ifdef CONFIG_SYS_PTCPAR + MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; +#endif +#if defined(CONFIG_SYS_PORTTC) + MCFGPIO_PORTTC = CONFIG_SYS_PORTTC; +#endif +#if defined(CONFIG_SYS_DDRTC) + MCFGPIO_DDRTC = CONFIG_SYS_DDRTC; +#endif +#ifdef CONFIG_SYS_PTDPAR + MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; +#endif +#ifdef CONFIG_SYS_PUAPAR + MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; +#endif + +#if defined(CONFIG_SYS_DDRD) + MCFGPIO_DDRD = CONFIG_SYS_DDRD; +#endif +#ifdef CONFIG_SYS_DDRUA + MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; +#endif + + /* FlexBus Chipselect */ + init_fbcs(); + +#endif /* CONFIG_MONITOR_IS_IN_RAM */ + + /* defer enabling cache until boot (see do_go) */ + /* icache_enable(); */ +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ + /* Setup Ports: */ + switch (port) { + case 0: + MCFGPIO_PUAPAR &= 0xFc; + MCFGPIO_PUAPAR |= 0x03; + break; + case 1: + MCFGPIO_PUAPAR &= 0xF3; + MCFGPIO_PUAPAR |= 0x0C; + break; + case 2: + MCFGPIO_PASPAR &= 0xFF0F; + MCFGPIO_PASPAR |= 0x00A0; + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; + } + return 0; +} +#endif /* CONFIG_CMD_NET */ +#endif + +#if defined(CONFIG_M5249) +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + /* + * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins + * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins + * which is their primary function. + * ~Jeremy + */ + mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); + mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); + mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); + mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); + mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); + mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); + + /* + * dBug Compliance: + * You can verify these values by using dBug's 'ird' + * (Internal Register Display) command + * ~Jeremy + * + */ + mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_SYPCR, 0x00); + mbar_writeByte(MCFSIM_SWIVR, 0x0f); + mbar_writeByte(MCFSIM_SWSR, 0x00); + mbar_writeLong(MCFSIM_IMR, 0xfffffbff); + mbar_writeByte(MCFSIM_SWDICR, 0x00); + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); + mbar_writeByte(MCFSIM_I2CICR, 0x00); + mbar_writeByte(MCFSIM_UART1ICR, 0x00); + mbar_writeByte(MCFSIM_UART2ICR, 0x00); + mbar_writeByte(MCFSIM_ICR6, 0x00); + mbar_writeByte(MCFSIM_ICR7, 0x00); + mbar_writeByte(MCFSIM_ICR8, 0x00); + mbar_writeByte(MCFSIM_ICR9, 0x00); + mbar_writeByte(MCFSIM_QSPIICR, 0x00); + + mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); + mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ + mbar2_writeByte(MCFSIM_SPURVEC, 0x00); + mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ + + /* Setup interrupt priorities for gpio7 */ + /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ + + /* IDE Config registers */ + mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); + mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); + + /* FlexBus Chipselect */ + init_fbcs(); + + /* enable instruction cache now */ + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ +} +#endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c similarity index 100% rename from cpu/mcf52x2/interrupts.c rename to arch/m68k/cpu/mcf52x2/interrupts.c diff --git a/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c similarity index 100% rename from cpu/mcf52x2/speed.c rename to arch/m68k/cpu/mcf52x2/speed.c diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S new file mode 100644 index 0000000000..9ef206aa0f --- /dev/null +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "version.h" +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; \ + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte + +/* If we come from a pre-loader we don't need an initial exception + * table. + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ +#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +.long _start - TEXT_BASE +#else +.long _START +#endif + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +#endif + + .text + + +#if defined(CONFIG_SYS_INT_FLASH_BASE) && \ + (defined(CONFIG_M5282) || defined(CONFIG_M5281)) + #if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) + .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ + .long 0xFFFFFFFF /* all sectors protected */ + .long 0x00000000 /* supervisor/User restriction */ + .long 0x00000000 /* programm/data space restriction */ + .long 0x00000000 /* Flash security */ + #endif +#endif + .globl _start +_start: + nop + nop + move.w #0x2700,%sr + +#if defined(CONFIG_M5208) + /* Initialize RAMBAR: locate SRAM and validate it */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 +#endif + +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) + move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */ + move.c %d0, %MBAR + + /*** The 5249 has MBAR2 as well ***/ +#ifdef CONFIG_SYS_MBAR2 + move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */ + movec %d0, #0xc0e /* Set MBAR2 */ +#endif + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + movec %d0, %RAMBAR0 +#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ + +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) + /* Initialize IPSBAR */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + move.l %d0, 0x40000000 + + /* Initialize RAMBAR1: locate SRAM and validate it */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + movec %d0, %RAMBAR1 + +#if defined(CONFIG_M5282) +#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) + /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */ + + move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 +_copy_flash: + move.l (%a0)+, (%a2)+ + cmp.l %a0, %a1 + bgt.s _copy_flash + jmp CONFIG_SYS_INIT_RAM_ADDR + +_flashbar_setup: + /* Initialize FLASHBAR: locate internal Flash and validate it */ + move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + movec %d0, %FLASHBAR + jmp _after_flashbar_copy.L /* Force jump to absolute address */ +_flashbar_setup_end: + nop +_after_flashbar_copy: +#else + /* Setup code to initialize FLASHBAR, if start from external Memory */ + move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + movec %d0, %FLASHBAR +#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */ + +#endif +#endif + /* if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) +#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) + move.l #CONFIG_SYS_INT_FLASH_BASE, %d0 +#else + move.l #CONFIG_SYS_FLASH_BASE, %d0 +#endif + movec %d0, %VBR +#endif + +#ifdef CONFIG_M5275 + /* Initialize IPSBAR */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + move.l %d0, 0x40000000 +/* movec %d0, %MBAR */ + + /* Initialize RAMBAR: locate SRAM and validate it */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + movec %d0, %RAMBAR1 +#endif + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ +#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \ + defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) + halt +#endif + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + + .globl _exc_handler +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf532x/Makefile b/arch/m68k/cpu/mcf532x/Makefile similarity index 100% rename from cpu/mcf532x/Makefile rename to arch/m68k/cpu/mcf532x/Makefile diff --git a/arch/m68k/cpu/mcf532x/config.mk b/arch/m68k/cpu/mcf532x/config.mk new file mode 100644 index 0000000000..b783444ae8 --- /dev/null +++ b/arch/m68k/cpu/mcf532x/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data + +cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg)) +is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg)) + +ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) + +ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) +PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC +endif +ifneq (,$(findstring CONFIG_MCF532x,$(is532x))) +PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC +endif + +else +PLATFORM_CPPFLAGS += -m5307 -fPIC +endif diff --git a/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c similarity index 100% rename from cpu/mcf532x/cpu.c rename to arch/m68k/cpu/mcf532x/cpu.c diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c new file mode 100644 index 0000000000..6f551b60c9 --- /dev/null +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -0,0 +1,350 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + +#ifdef CONFIG_MCF5301x +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + /*wdog->cr = 0; */ +#endif + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ + && defined(CONFIG_SYS_CS0_CTRL)) + gpio->par_cs |= GPIO_PAR_CS0_CS0; + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; +#endif + +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ + && defined(CONFIG_SYS_CS1_CTRL)) + gpio->par_cs |= GPIO_PAR_CS1_CS1; + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; +#endif + +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ + && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; +#endif + +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ + && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; +#endif + +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ + && defined(CONFIG_SYS_CS4_CTRL)) + gpio->par_cs |= GPIO_PAR_CS4; + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; +#endif + +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ + && defined(CONFIG_SYS_CS5_CTRL)) + gpio->par_cs |= GPIO_PAR_CS5; + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL; +#endif + + icache_enable(); +} + +/* initialize higher level parts of CPU like timers */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFFEC + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; +#endif +#ifdef CONFIG_MCFRTC + volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); + volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended; + + rtcex->gocu = CONFIG_SYS_RTC_CNT; + rtcex->gocl = CONFIG_SYS_RTC_SETUP; + +#endif +#ifdef CONFIG_MCFFEC + if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) + ccm->misccr |= CCM_MISCCR_FECM; + else + ccm->misccr &= ~CCM_MISCCR_FECM; +#endif + + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + break; + case 1: +#ifdef CONFIG_SYS_UART1_ALT1_GPIO + gpio->par_simp1h &= + ~(GPIO_PAR_SIMP1H_DATA1_UNMASK | + GPIO_PAR_SIMP1H_VEN1_UNMASK); + gpio->par_simp1h |= + (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); +#elif defined(CONFIG_SYS_UART1_ALT2_GPIO) + gpio->par_ssih &= + ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK); + gpio->par_ssih |= + (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); +#endif + break; + case 2: +#ifdef CONFIG_SYS_UART2_PRI_GPIO + gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); +#elif defined(CONFIG_SYS_UART2_ALT1_GPIO) + gpio->par_dspih &= + ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK); + gpio->par_dspih |= + (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); +#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); +#endif + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + gpio->par_fec |= + GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0; + } else { + gpio->par_fec |= + GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1; + } + } else { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { + gpio->par_fec &= + ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK; + } else { + gpio->par_fec &= + ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK; + } + } + return 0; +} +#endif /* CONFIG_CMD_NET */ +#endif /* CONFIG_MCF5301x */ + +#ifdef CONFIG_MCF532x +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + wdog->cr = 0; +#endif + + scm1->mpr0 = 0x77777777; + scm2->pacra = 0; + scm2->pacrb = 0; + scm2->pacrc = 0; + scm2->pacrd = 0; + scm2->pacre = 0; + scm2->pacrf = 0; + scm2->pacrg = 0; + scm1->pacrh = 0; + + /* Port configuration */ + gpio->par_cs = 0; + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ + && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; +#endif + +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ + && defined(CONFIG_SYS_CS1_CTRL)) + /* Latch chipselect */ + gpio->par_cs |= GPIO_PAR_CS1; + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; +#endif + +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ + && defined(CONFIG_SYS_CS2_CTRL)) + gpio->par_cs |= GPIO_PAR_CS2; + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; +#endif + +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ + && defined(CONFIG_SYS_CS3_CTRL)) + gpio->par_cs |= GPIO_PAR_CS3; + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; +#endif + +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ + && defined(CONFIG_SYS_CS4_CTRL)) + gpio->par_cs |= GPIO_PAR_CS4; + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; +#endif + +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ + && defined(CONFIG_SYS_CS5_CTRL)) + gpio->par_cs |= GPIO_PAR_CS5; + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + break; + case 1: + gpio->par_uart &= + ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + gpio->par_uart |= + (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + break; + case 2: +#ifdef CONFIG_SYS_UART2_ALT1_GPIO + gpio->par_timer &= 0x0F; + gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); +#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) + gpio->par_feci2c &= 0xFF00; + gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); +#elif defined(CONFIG_SYS_UART2_ALT3_GPIO) + gpio->par_ssi &= 0xF0FF; + gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); +#endif + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + } else { + gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + } + return 0; +} +#endif +#endif /* CONFIG_MCF532x */ diff --git a/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c similarity index 100% rename from cpu/mcf532x/interrupts.c rename to arch/m68k/cpu/mcf532x/interrupts.c diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c new file mode 100644 index 0000000000..5a29e2567a --- /dev/null +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -0,0 +1,275 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* PLL min/max specifications */ +#define MAX_FVCO 500000 /* KHz */ +#define MAX_FSYS 80000 /* KHz */ +#define MIN_FSYS 58333 /* KHz */ + +#ifdef CONFIG_MCF5301x +#define FREF 20000 /* KHz */ +#define MAX_MFD 63 /* Multiplier */ +#define MIN_MFD 0 /* Multiplier */ +#define USBDIV 8 + +/* Low Power Divider specifications */ +#define MIN_LPD (0) /* Divider (not encoded) */ +#define MAX_LPD (15) /* Divider (not encoded) */ +#define DEFAULT_LPD (0) /* Divider (not encoded) */ +#endif + +#ifdef CONFIG_MCF532x +#define FREF 16000 /* KHz */ +#define MAX_MFD 135 /* Multiplier */ +#define MIN_MFD 88 /* Multiplier */ + +/* Low Power Divider specifications */ +#define MIN_LPD (1 << 0) /* Divider (not encoded) */ +#define MAX_LPD (1 << 15) /* Divider (not encoded) */ +#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ +#endif + +#define BUSDIV 6 /* Divider */ + +/* Get the value of the current system clock */ +int get_sys_clock(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + int divider; + + /* Test to see if device is in LIMP mode */ + if (ccm->misccr & CCM_MISCCR_LIMP) { + divider = ccm->cdr & CCM_CDR_LPDIV(0xF); +#ifdef CONFIG_MCF5301x + return (FREF / (3 * (1 << divider))); +#endif +#ifdef CONFIG_MCF532x + return (FREF / (2 << divider)); +#endif + } else { +#ifdef CONFIG_MCF5301x + u32 pfdr = (pll->pcr & 0x3F) + 1; + u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8)); + u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1; + + return (((FREF * pfdr) / refdiv) / busdiv); +#endif +#ifdef CONFIG_MCF532x + return ((FREF * pll->pfdr) / (BUSDIV * 4)); +#endif + } +} + +/* + * Initialize the Low Power Divider circuit + * + * Parameters: + * div Desired system frequency divider + * + * Return Value: + * The resulting output system frequency + */ +int clock_limp(int div) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + u32 temp; + + /* Check bounds of divider */ + if (div < MIN_LPD) + div = MIN_LPD; + if (div > MAX_LPD) + div = MAX_LPD; + + /* Save of the current value of the SSIDIV so we don't overwrite the value */ + temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF)); + + /* Apply the divider to the system clock */ + ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); + + ccm->misccr |= CCM_MISCCR_LIMP; + + return (FREF / (3 * (1 << div))); +} + +/* Exit low power LIMP mode */ +int clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + int fout; + + /* Exit LIMP mode */ + ccm->misccr &= (~CCM_MISCCR_LIMP); + + /* Wait for PLL to lock */ + while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ; + + fout = get_sys_clock(); + + return fout; +} + +/* Initialize the PLL + * + * Parameters: + * fref PLL reference clock frequency in KHz + * fsys Desired PLL output frequency in KHz + * flags Operating parameters + * + * Return Value: + * The resulting output system frequency + */ +int clock_pll(int fsys, int flags) +{ +#ifdef CONFIG_MCF532x + volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); +#endif + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + int fref, temp, fout, mfd; + u32 i; + + fref = FREF; + + if (fsys == 0) { + /* Return current PLL output */ +#ifdef CONFIG_MCF5301x + u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1; + mfd = (pll->pcr & 0x3F) + 1; + + return (fref * mfd) / busdiv; +#endif +#ifdef CONFIG_MCF532x + mfd = pll->pfdr; + + return (fref * mfd / (BUSDIV * 4)); +#endif + } + + /* Check bounds of requested system clock */ + if (fsys > MAX_FSYS) + fsys = MAX_FSYS; + + if (fsys < MIN_FSYS) + fsys = MIN_FSYS; + + /* + * Multiplying by 100 when calculating the temp value, + * and then dividing by 100 to calculate the mfd allows + * for exact values without needing to include floating + * point libraries. + */ + temp = (100 * fsys) / fref; +#ifdef CONFIG_MCF5301x + mfd = (BUSDIV * temp) / 100; + + /* Determine the output frequency for selected values */ + fout = ((fref * mfd) / BUSDIV); +#endif +#ifdef CONFIG_MCF532x + mfd = (4 * BUSDIV * temp) / 100; + + /* Determine the output frequency for selected values */ + fout = ((fref * mfd) / (BUSDIV * 4)); +#endif + +/* must not tamper with SDRAMC if running from SDRAM */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + /* + * Check to see if the SDRAM has already been initialized. + * If it has then the SDRAM needs to be put into self refresh + * mode before reprogramming the PLL. + */ + if (sdram->ctrl & SDRAMC_SDCR_REF) + sdram->ctrl &= ~SDRAMC_SDCR_CKE; + + /* + * Initialize the PLL to generate the new system clock frequency. + * The device must be put into LIMP mode to reprogram the PLL. + */ + + /* Enter LIMP mode */ + clock_limp(DEFAULT_LPD); + +#ifdef CONFIG_MCF5301x + pll->pdr = + PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | + PLL_PDR_OUTDIV2(BUSDIV - 1) | + PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | + PLL_PDR_OUTDIV4(USBDIV - 1); + + pll->pcr &= PLL_PCR_FBDIV_UNMASK; + pll->pcr |= PLL_PCR_FBDIV(mfd - 1); +#endif +#ifdef CONFIG_MCF532x + /* Reprogram PLL for desired fsys */ + pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); + + pll->pfdr = mfd; +#endif + + /* Exit LIMP mode */ + clock_exit_limp(); + + /* Return the SDRAM to normal operation if it is in use. */ + if (sdram->ctrl & SDRAMC_SDCR_REF) + sdram->ctrl |= SDRAMC_SDCR_CKE; + +#ifdef CONFIG_MCF532x + /* + * software workaround for SDRAM opeartion after exiting LIMP + * mode errata + */ + *sdram_workaround = CONFIG_SYS_SDRAM_BASE; +#endif + + /* wait for DQS logic to relock */ + for (i = 0; i < 0x200; i++) ; +#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ + + return fout; +} + +/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ +int get_clocks(void) +{ + gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; + gd->cpu_clk = (gd->bus_clk * 3); + +#ifdef CONFIG_FSL_I2C + gd->i2c1_clk = gd->bus_clk; +#endif + + return (0); +} diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S new file mode 100644 index 0000000000..a80b0a9946 --- /dev/null +++ b/arch/m68k/cpu/mcf532x/start.S @@ -0,0 +1,288 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "version.h" +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +#if !defined(CONFIG_MONITOR_IS_IN_RAM) +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + /* Set vector base register at the beginning of the Flash */ + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR +#endif + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + /* invalidate and disable cache */ + move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + +#ifdef CONFIG_MCF5301x + move.l #(0xFC0a0010), %a0 + move.w (%a0), %d0 + and.l %d0, 0xEFFF + + move.w %d0, (%a0) +#endif + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the + first c-code */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile similarity index 100% rename from cpu/mcf5445x/Makefile rename to arch/m68k/cpu/mcf5445x/Makefile diff --git a/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk similarity index 100% rename from cpu/mcf5445x/config.mk rename to arch/m68k/cpu/mcf5445x/config.mk diff --git a/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c similarity index 100% rename from cpu/mcf5445x/cpu.c rename to arch/m68k/cpu/mcf5445x/cpu.c diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c new file mode 100644 index 0000000000..8d51d35d68 --- /dev/null +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -0,0 +1,272 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + + /* FlexBus */ + gpio->par_be = + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | + GPIO_PAR_BE_BE0_BE0; + gpio->par_fbctl = + GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | + GPIO_PAR_FBCTL_TS_TS; + +#if !defined(CONFIG_CF_SBF) +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; +#endif +#endif + +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) + /* Latch chipselect */ + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; +#endif + +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; +#endif + +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; +#endif + +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; +#endif + +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; +#endif + + /* + * now the flash base address is no longer at 0 (Newer ColdFire family + * boot at address 0 instead of 0xFFnn_nnnn). The vector table must + * also move to the new location. + */ + if (CONFIG_SYS_CS0_BASE != 0) + setvbr(CONFIG_SYS_CS0_BASE); + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFRTC + volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); + volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + + rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; +#endif + + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->par_uart &= + ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + gpio->par_uart |= + (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + break; + case 1: +#ifdef CONFIG_SYS_UART1_PRI_GPIO + gpio->par_uart &= + ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + gpio->par_uart |= + (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); +#elif defined(CONFIG_SYS_UART1_ALT1_GPIO) + gpio->par_ssi &= + (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK); + gpio->par_ssi |= + (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); +#endif + break; + case 2: +#if defined(CONFIG_SYS_UART2_ALT1_GPIO) + gpio->par_timer &= + (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK); + gpio->par_timer |= + (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); +#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) + gpio->par_timer &= + (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK); + gpio->par_timer |= + (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); +#endif + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + else + gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK; + else + gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK; + } + return 0; +} +#endif + +#ifdef CONFIG_CF_DSPI +void cfspi_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK; +} + +int cfspi_claim_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + return -1; + + /* Clear FIFO and resume transfer */ + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 1: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1; + break; + case 2: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; + break; + case 5: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; + break; + } + + return 0; +} + +void cfspi_release_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 1: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; + break; + case 2: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; + break; + case 5: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; + break; + } +} +#endif diff --git a/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c similarity index 100% rename from cpu/mcf5445x/interrupts.c rename to arch/m68k/cpu/mcf5445x/interrupts.c diff --git a/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c similarity index 100% rename from cpu/mcf5445x/pci.c rename to arch/m68k/cpu/mcf5445x/pci.c diff --git a/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c similarity index 100% rename from cpu/mcf5445x/speed.c rename to arch/m68k/cpu/mcf5445x/speed.c diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S new file mode 100644 index 0000000000..738e4a7110 --- /dev/null +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -0,0 +1,545 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "version.h" +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +#if defined(CONFIG_CF_SBF) +#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#endif + +.text + +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: +#if defined(CONFIG_CF_SBF) + +INITSP: .long 0 /* Initial SP */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ + +#else + +INITSP: .long 0 /* Initial SP */ +INITPC: .long _START /* Initial PC */ + +#endif + +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +#if !defined(CONFIG_CF_SBF) + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +#endif + +#if defined(CONFIG_CF_SBF) + /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ +asm_sbf_img_hdr: + .long 0x00000000 /* checksum, not yet implemented */ + .long 0x00030000 /* image length */ + .long TEXT_BASE /* image to be relocated at */ + +asm_dram_init: + move.w #0x2700,%sr /* Mask off Interrupt */ + + move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 + movec %d0, %VBR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* invalidate and disable cache */ + move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + /* Must disable global address */ + move.l #0xFC008000, %a1 + move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #0xFC008008, %a1 + move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #0xFC008004, %a1 + move.l #(CONFIG_SYS_CS0_MASK), (%a1) + + /* Dram Initialization a1, a2, and d0 */ + /* mscr sdram */ + move.l #0xFC0A4074, %a1 + move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) + nop + + /* SDRAM Chip 0 and 1 */ + move.l #0xFC0B8110, %a1 + move.l #0xFC0B8114, %a2 + + /* calculate the size */ + move.l #0x13, %d1 + move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 +#ifdef CONFIG_SYS_SDRAM_BASE1 + lsr.l #1, %d2 +#endif + +dramsz_loop: + lsr.l #1, %d2 + add.l #1, %d1 + cmp.l #1, %d2 + bne dramsz_loop + + /* SDRAM Chip 0 and 1 */ + move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) + or.l %d1, (%a1) +#ifdef CONFIG_SYS_SDRAM_BASE1 + move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) + or.l %d1, (%a2) +#endif + nop + + /* dram cfg1 and cfg2 */ + move.l #0xFC0B8008, %a1 + move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) + nop + move.l #0xFC0B800C, %a2 + move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) + nop + + move.l #0xFC0B8000, %a1 /* Mode */ + move.l #0xFC0B8004, %a2 /* Ctrl */ + + /* Issue PALL */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) + nop + +#ifdef CONFIG_M54455EVB + /* Issue LEMR */ + move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) + nop + move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) + nop +#endif + + move.l #1000, %d1 + jsr asm_delay + + /* Issue PALL */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) + nop + + /* Perform two refresh cycles */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 + nop + move.l %d0, (%a2) + move.l %d0, (%a2) + nop + +#ifdef CONFIG_M54455EVB + move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1) + nop +#elif defined(CONFIG_M54451EVB) + /* Issue LEMR */ + move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) + nop + move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) +#endif + + move.l #500, %d1 + jsr asm_delay + + move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 + and.l #0x7FFFFFFF, %d1 +#ifdef CONFIG_M54455EVB + or.l #0x10000C00, %d1 +#elif defined(CONFIG_M54451EVB) + or.l #0x10000C00, %d1 +#endif + move.l %d1, (%a2) + nop + + move.l #2000, %d1 + jsr asm_delay + + /* + * DSPI Initialization + * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h + * a1 - dspi status + * a2 - dtfr + * a3 - drfr + * a4 - Dst addr + */ + /* Enable pins for DSPI mode - chip-selects are enabled later */ +asm_dspi_init: + move.l #0xFC0A4063, %a0 + move.b #0x7F, (%a0) + + /* Configure DSPI module */ + move.l #0xFC05C000, %a0 + move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ + + move.l #0xFC05C00C, %a0 + move.l #0x3E000011, (%a0) + + move.l #0xFC05C034, %a2 /* dtfr */ + move.l #0xFC05C03B, %a3 /* drfr */ + + move.l #(ASM_SBF_IMG_HDR + 4), %a1 + move.l (%a1)+, %d5 + move.l (%a1), %a4 + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 + move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 + + move.l #0xFC05C02C, %a1 /* dspi status */ + + /* Issue commands and address */ + move.l #0x8002000B, %d2 /* Fast Read Cmd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 2 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 1 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 0 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Dummy Wr and Rd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* Transfer serial boot header to sram */ +asm_dspi_rd_loop1: + move.l #0x80020000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a0) /* read, copy to dst */ + + add.l #1, %a0 /* inc dst by 1 */ + sub.l #1, %d4 /* dec cnt by 1 */ + bne asm_dspi_rd_loop1 + + /* Transfer u-boot from serial flash to memory */ +asm_dspi_rd_loop2: + move.l #0x80020000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a4) /* read, copy to dst */ + + add.l #1, %a4 /* inc dst by 1 */ + sub.l #1, %d5 /* dec cnt by 1 */ + bne asm_dspi_rd_loop2 + + move.l #0x00020000, %d2 /* Terminate */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* jump to memory and execute */ + move.l #(TEXT_BASE + 0x400), %a0 + jmp (%a0) + +asm_dspi_wr_status: + move.l (%a1), %d0 /* status */ + and.l #0x0000F000, %d0 + cmp.l #0x00003000, %d0 + bgt asm_dspi_wr_status + + move.l %d2, (%a2) + rts + +asm_dspi_rd_status: + move.l (%a1), %d0 /* status */ + and.l #0x000000F0, %d0 + lsr.l #4, %d0 + cmp.l #0, %d0 + beq asm_dspi_rd_status + + move.b (%a3), %d1 + rts + +asm_delay: + nop + subq.l #1, %d1 + bne asm_delay + rts +#endif /* CONFIG_CF_SBF */ + + .text + . = 0x400 + .globl _start +_start: +#if !defined(CONFIG_CF_SBF) + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* invalidate and disable cache */ + move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + + /* set stackpointer to end of internal ram to get some stackspace for + the first c-code */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- +#endif + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + bra _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf547x_8x/Makefile b/arch/m68k/cpu/mcf547x_8x/Makefile similarity index 100% rename from cpu/mcf547x_8x/Makefile rename to arch/m68k/cpu/mcf547x_8x/Makefile diff --git a/cpu/mcf547x_8x/config.mk b/arch/m68k/cpu/mcf547x_8x/config.mk similarity index 100% rename from cpu/mcf547x_8x/config.mk rename to arch/m68k/cpu/mcf547x_8x/config.mk diff --git a/cpu/mcf547x_8x/cpu.c b/arch/m68k/cpu/mcf547x_8x/cpu.c similarity index 100% rename from cpu/mcf547x_8x/cpu.c rename to arch/m68k/cpu/mcf547x_8x/cpu.c diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c b/arch/m68k/cpu/mcf547x_8x/cpu_init.c new file mode 100644 index 0000000000..60c91267a7 --- /dev/null +++ b/arch/m68k/cpu/mcf547x_8x/cpu_init.c @@ -0,0 +1,159 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_CMD_NET) +#include +#include +#include +#endif + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; + + xlbarb->adrto = 0x2000; + xlbarb->datto = 0x2500; + xlbarb->busto = 0x3000; + + xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT; + + /* Master Priority Enable */ + xlbarb->prien = 0xff; + xlbarb->pri = 0; + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; +#endif + +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; +#endif + +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; +#endif + +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; +#endif + +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; +#endif + +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC) + MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512), + MCD_RELOC_TASKS); +#endif + return (0); +} + +void uart_port_conf(int port) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); + + /* Setup Ports: */ + switch (port) { + case 0: + gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); + break; + case 1: + gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); + break; + case 2: + gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); + break; + case 3: + gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); + break; + } + + *pscsicr &= 0xF8; +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; + + if (setclear) { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + gpio->par_feci2cirq |= 0xF000; + else + gpio->par_feci2cirq |= 0x0FC0; + } else { + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) + gpio->par_feci2cirq &= 0x0FFF; + else + gpio->par_feci2cirq &= 0xF03F; + } + return 0; +} +#endif diff --git a/cpu/mcf547x_8x/interrupts.c b/arch/m68k/cpu/mcf547x_8x/interrupts.c similarity index 100% rename from cpu/mcf547x_8x/interrupts.c rename to arch/m68k/cpu/mcf547x_8x/interrupts.c diff --git a/cpu/mcf547x_8x/pci.c b/arch/m68k/cpu/mcf547x_8x/pci.c similarity index 100% rename from cpu/mcf547x_8x/pci.c rename to arch/m68k/cpu/mcf547x_8x/pci.c diff --git a/cpu/mcf547x_8x/slicetimer.c b/arch/m68k/cpu/mcf547x_8x/slicetimer.c similarity index 100% rename from cpu/mcf547x_8x/slicetimer.c rename to arch/m68k/cpu/mcf547x_8x/slicetimer.c diff --git a/cpu/mcf547x_8x/speed.c b/arch/m68k/cpu/mcf547x_8x/speed.c similarity index 100% rename from cpu/mcf547x_8x/speed.c rename to arch/m68k/cpu/mcf547x_8x/speed.c diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S new file mode 100644 index 0000000000..84118629e2 --- /dev/null +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "version.h" +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR0 + + move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0 + movec %d0, %RAMBAR1 + + move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */ + move.c %d0, %MBAR + + /* invalidate and disable cache */ + move.l #0x01040100, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the + first c-code */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + bra _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/include/asm-m68k/bitops.h b/arch/m68k/include/asm/bitops.h similarity index 100% rename from include/asm-m68k/bitops.h rename to arch/m68k/include/asm/bitops.h diff --git a/include/asm-m68k/byteorder.h b/arch/m68k/include/asm/byteorder.h similarity index 100% rename from include/asm-m68k/byteorder.h rename to arch/m68k/include/asm/byteorder.h diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h new file mode 100644 index 0000000000..7c84e48471 --- /dev/null +++ b/arch/m68k/include/asm/cache.h @@ -0,0 +1,210 @@ +/* + * ColdFire cache + * + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CACHE_H +#define __CACHE_H + +#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ + defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) +#define CONFIG_CF_V2 +#endif + +#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) +#define CONFIG_CF_V3 +#endif + +#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) +#define CONFIG_CF_V4 +#if defined(CONFIG_MCF5441x) +#define CONFIG_CF_V4E /* Four Extra ACRn */ +#endif +#endif + +/* ***** CACR ***** */ +/* V2 Core */ +#ifdef CONFIG_CF_V2 + +#define CF_CACR_CENB (1 << 31) +#define CF_CACR_CPD (1 << 28) +#define CF_CACR_CFRZ (1 << 27) +#define CF_CACR_CEIB (1 << 10) +#define CF_CACR_DCM (1 << 9) +#define CF_CACR_DBWE (1 << 8) + +#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) +#define CF_CACR_DWP (1 << 6) +#else +#define CF_CACR_CINV (1 << 24) +#define CF_CACR_DISI (1 << 23) +#define CF_CACR_DISD (1 << 22) +#define CF_CACR_INVI (1 << 21) +#define CF_CACR_INVD (1 << 20) +#define CF_CACR_DWP (1 << 5) +#define CF_CACR_EUSP (1 << 4) +#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ + +#endif /* CONFIG_CF_V2 */ + +/* V3 Core */ +#ifdef CONFIG_CF_V3 + +#define CF_CACR_EC (1 << 31) +#define CF_CACR_ESB (1 << 29) +#define CF_CACR_DPI (1 << 28) +#define CF_CACR_HLCK (1 << 27) +#define CF_CACR_CINVA (1 << 24) +#define CF_CACR_DNFB (1 << 10) +#define CF_CACR_DCM_UNMASK 0xFFFFFCFF +#define CF_CACR_DCM_WT (0 << 8) +#define CF_CACR_DCM_CB (1 << 8) +#define CF_CACR_DCM_P (2 << 8) +#define CF_CACR_DCM_IP (3 << 8) +#define CF_CACR_DW (1 << 5) +#define CF_CACR_EUSP (1 << 4) + +#endif /* CONFIG_CF_V3 */ + +/* V4 Core */ +#ifdef CONFIG_CF_V4 + +#define CF_CACR_DEC (1 << 31) +#define CF_CACR_DW (1 << 30) +#define CF_CACR_DESB (1 << 29) +#define CF_CACR_DDPI (1 << 28) +#define CF_CACR_DHLCK (1 << 27) +#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) +#define CF_CACR_DDCM_WT (0 << 25) +#define CF_CACR_DDCM_CB (1 << 25) +#define CF_CACR_DDCM_P (2 << 25) +#define CF_CACR_DDCM_IP (3 << 25) +#define CF_CACR_DCINVA (1 << 24) + +#define CF_CACR_DDSP (1 << 23) +#define CF_CACR_BEC (1 << 19) +#define CF_CACR_BCINVA (1 << 18) +#define CF_CACR_IEC (1 << 15) +#define CF_CACR_DNFB (1 << 13) +#define CF_CACR_IDPI (1 << 12) +#define CF_CACR_IHLCK (1 << 11) +#define CF_CACR_IDCM (1 << 10) +#define CF_CACR_ICINVA (1 << 8) +#define CF_CACR_IDSP (1 << 7) +#define CF_CACR_EUSP (1 << 5) + +#ifdef CONFIG_MCF5445x +#define CF_CACR_IVO (1 << 20) +#define CF_CACR_SPA (1 << 14) +#else +#define CF_CACR_DF (1 << 4) +#endif + +#endif /* CONFIG_CF_V4 */ + +/* ***** ACR ***** */ +#define CF_ACR_ADR_UNMASK (0x00FFFFFF) +#define CF_ACR_ADR(x) ((x & 0xFF) << 24) +#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) +#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) +#define CF_ACR_EN (1 << 15) +#define CF_ACR_SM_UNMASK (0xFFFF9FFF) +#define CF_ACR_SM_UM (0 << 13) +#define CF_ACR_SM_SM (1 << 13) +#define CF_ACR_SM_ALL (3 << 13) +#define CF_ACR_WP (1 << 2) + +/* V2 Core */ +#ifdef CONFIG_CF_V2 +#define CF_ACR_CM (1 << 6) +#define CF_ACR_BWE (1 << 5) +#else +/* V3 & V4 */ +#define CF_ACR_CM_UNMASK (0xFFFFFF9F) +#define CF_ACR_CM_WT (0 << 5) +#define CF_ACR_CM_CB (1 << 5) +#define CF_ACR_CM_P (2 << 5) +#define CF_ACR_CM_IP (3 << 5) +#endif /* CONFIG_CF_V2 */ + +/* V4 Core */ +#ifdef CONFIG_CF_V4 +#define CF_ACR_AMM (1 << 10) +#define CF_ACR_SP (1 << 3) +#endif /* CONFIG_CF_V4 */ + + +#ifndef CONFIG_SYS_CACHE_ICACR +#define CONFIG_SYS_CACHE_ICACR 0 +#endif + +#ifndef CONFIG_SYS_CACHE_DCACR +#ifdef CONFIG_SYS_CACHE_ICACR +#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR +#else +#define CONFIG_SYS_CACHE_DCACR 0 +#endif +#endif + +#ifndef CONFIG_SYS_CACHE_ACR0 +#define CONFIG_SYS_CACHE_ACR0 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR1 +#define CONFIG_SYS_CACHE_ACR1 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR2 +#define CONFIG_SYS_CACHE_ACR2 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR3 +#define CONFIG_SYS_CACHE_ACR3 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR4 +#define CONFIG_SYS_CACHE_ACR4 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR5 +#define CONFIG_SYS_CACHE_ACR5 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR6 +#define CONFIG_SYS_CACHE_ACR6 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR7 +#define CONFIG_SYS_CACHE_ACR7 0 +#endif + +#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ + +void icache_invalid(void); +void dcache_invalid(void); + +#endif + +#endif /* __CACHE_H */ diff --git a/include/asm-m68k/coldfire/ata.h b/arch/m68k/include/asm/coldfire/ata.h similarity index 100% rename from include/asm-m68k/coldfire/ata.h rename to arch/m68k/include/asm/coldfire/ata.h diff --git a/include/asm-m68k/coldfire/crossbar.h b/arch/m68k/include/asm/coldfire/crossbar.h similarity index 100% rename from include/asm-m68k/coldfire/crossbar.h rename to arch/m68k/include/asm/coldfire/crossbar.h diff --git a/include/asm-m68k/coldfire/dspi.h b/arch/m68k/include/asm/coldfire/dspi.h similarity index 100% rename from include/asm-m68k/coldfire/dspi.h rename to arch/m68k/include/asm/coldfire/dspi.h diff --git a/include/asm-m68k/coldfire/edma.h b/arch/m68k/include/asm/coldfire/edma.h similarity index 100% rename from include/asm-m68k/coldfire/edma.h rename to arch/m68k/include/asm/coldfire/edma.h diff --git a/include/asm-m68k/coldfire/eport.h b/arch/m68k/include/asm/coldfire/eport.h similarity index 100% rename from include/asm-m68k/coldfire/eport.h rename to arch/m68k/include/asm/coldfire/eport.h diff --git a/include/asm-m68k/coldfire/flexbus.h b/arch/m68k/include/asm/coldfire/flexbus.h similarity index 100% rename from include/asm-m68k/coldfire/flexbus.h rename to arch/m68k/include/asm/coldfire/flexbus.h diff --git a/include/asm-m68k/coldfire/flexcan.h b/arch/m68k/include/asm/coldfire/flexcan.h similarity index 100% rename from include/asm-m68k/coldfire/flexcan.h rename to arch/m68k/include/asm/coldfire/flexcan.h diff --git a/include/asm-m68k/coldfire/intctrl.h b/arch/m68k/include/asm/coldfire/intctrl.h similarity index 100% rename from include/asm-m68k/coldfire/intctrl.h rename to arch/m68k/include/asm/coldfire/intctrl.h diff --git a/include/asm-m68k/coldfire/lcd.h b/arch/m68k/include/asm/coldfire/lcd.h similarity index 100% rename from include/asm-m68k/coldfire/lcd.h rename to arch/m68k/include/asm/coldfire/lcd.h diff --git a/include/asm-m68k/coldfire/mdha.h b/arch/m68k/include/asm/coldfire/mdha.h similarity index 100% rename from include/asm-m68k/coldfire/mdha.h rename to arch/m68k/include/asm/coldfire/mdha.h diff --git a/include/asm-m68k/coldfire/pwm.h b/arch/m68k/include/asm/coldfire/pwm.h similarity index 100% rename from include/asm-m68k/coldfire/pwm.h rename to arch/m68k/include/asm/coldfire/pwm.h diff --git a/include/asm-m68k/coldfire/qspi.h b/arch/m68k/include/asm/coldfire/qspi.h similarity index 100% rename from include/asm-m68k/coldfire/qspi.h rename to arch/m68k/include/asm/coldfire/qspi.h diff --git a/include/asm-m68k/coldfire/rng.h b/arch/m68k/include/asm/coldfire/rng.h similarity index 100% rename from include/asm-m68k/coldfire/rng.h rename to arch/m68k/include/asm/coldfire/rng.h diff --git a/include/asm-m68k/coldfire/skha.h b/arch/m68k/include/asm/coldfire/skha.h similarity index 100% rename from include/asm-m68k/coldfire/skha.h rename to arch/m68k/include/asm/coldfire/skha.h diff --git a/include/asm-m68k/coldfire/ssi.h b/arch/m68k/include/asm/coldfire/ssi.h similarity index 100% rename from include/asm-m68k/coldfire/ssi.h rename to arch/m68k/include/asm/coldfire/ssi.h diff --git a/include/asm-m68k/config.h b/arch/m68k/include/asm/config.h similarity index 100% rename from include/asm-m68k/config.h rename to arch/m68k/include/asm/config.h diff --git a/include/asm-m68k/errno.h b/arch/m68k/include/asm/errno.h similarity index 100% rename from include/asm-m68k/errno.h rename to arch/m68k/include/asm/errno.h diff --git a/include/asm-m68k/fec.h b/arch/m68k/include/asm/fec.h similarity index 100% rename from include/asm-m68k/fec.h rename to arch/m68k/include/asm/fec.h diff --git a/include/asm-m68k/fsl_i2c.h b/arch/m68k/include/asm/fsl_i2c.h similarity index 100% rename from include/asm-m68k/fsl_i2c.h rename to arch/m68k/include/asm/fsl_i2c.h diff --git a/include/asm-m68k/fsl_mcdmafec.h b/arch/m68k/include/asm/fsl_mcdmafec.h similarity index 100% rename from include/asm-m68k/fsl_mcdmafec.h rename to arch/m68k/include/asm/fsl_mcdmafec.h diff --git a/include/asm-m68k/global_data.h b/arch/m68k/include/asm/global_data.h similarity index 100% rename from include/asm-m68k/global_data.h rename to arch/m68k/include/asm/global_data.h diff --git a/include/asm-m68k/immap.h b/arch/m68k/include/asm/immap.h similarity index 100% rename from include/asm-m68k/immap.h rename to arch/m68k/include/asm/immap.h diff --git a/include/asm-m68k/immap_520x.h b/arch/m68k/include/asm/immap_520x.h similarity index 100% rename from include/asm-m68k/immap_520x.h rename to arch/m68k/include/asm/immap_520x.h diff --git a/include/asm-m68k/immap_5227x.h b/arch/m68k/include/asm/immap_5227x.h similarity index 100% rename from include/asm-m68k/immap_5227x.h rename to arch/m68k/include/asm/immap_5227x.h diff --git a/include/asm-m68k/immap_5235.h b/arch/m68k/include/asm/immap_5235.h similarity index 100% rename from include/asm-m68k/immap_5235.h rename to arch/m68k/include/asm/immap_5235.h diff --git a/include/asm-m68k/immap_5249.h b/arch/m68k/include/asm/immap_5249.h similarity index 100% rename from include/asm-m68k/immap_5249.h rename to arch/m68k/include/asm/immap_5249.h diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h new file mode 100644 index 0000000000..28cd107a82 --- /dev/null +++ b/arch/m68k/include/asm/immap_5253.h @@ -0,0 +1,53 @@ +/* + * MCF5253 Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5253__ +#define __IMMAP_5253__ + +#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) +#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) + +#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) +#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) +#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) + +#include +#include +#include +#include + +typedef struct canex_ctrl { + can_msg_t msg[32]; /* 0x80 Message Buffer 0-31 */ +} canex_t; + +#endif /* __IMMAP_5253__ */ diff --git a/include/asm-m68k/immap_5271.h b/arch/m68k/include/asm/immap_5271.h similarity index 100% rename from include/asm-m68k/immap_5271.h rename to arch/m68k/include/asm/immap_5271.h diff --git a/include/asm-m68k/immap_5272.h b/arch/m68k/include/asm/immap_5272.h similarity index 100% rename from include/asm-m68k/immap_5272.h rename to arch/m68k/include/asm/immap_5272.h diff --git a/include/asm-m68k/immap_5275.h b/arch/m68k/include/asm/immap_5275.h similarity index 100% rename from include/asm-m68k/immap_5275.h rename to arch/m68k/include/asm/immap_5275.h diff --git a/include/asm-m68k/immap_5282.h b/arch/m68k/include/asm/immap_5282.h similarity index 100% rename from include/asm-m68k/immap_5282.h rename to arch/m68k/include/asm/immap_5282.h diff --git a/include/asm-m68k/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h similarity index 100% rename from include/asm-m68k/immap_5301x.h rename to arch/m68k/include/asm/immap_5301x.h diff --git a/include/asm-m68k/immap_5329.h b/arch/m68k/include/asm/immap_5329.h similarity index 100% rename from include/asm-m68k/immap_5329.h rename to arch/m68k/include/asm/immap_5329.h diff --git a/include/asm-m68k/immap_5445x.h b/arch/m68k/include/asm/immap_5445x.h similarity index 100% rename from include/asm-m68k/immap_5445x.h rename to arch/m68k/include/asm/immap_5445x.h diff --git a/include/asm-m68k/immap_547x_8x.h b/arch/m68k/include/asm/immap_547x_8x.h similarity index 100% rename from include/asm-m68k/immap_547x_8x.h rename to arch/m68k/include/asm/immap_547x_8x.h diff --git a/include/asm-m68k/io.h b/arch/m68k/include/asm/io.h similarity index 100% rename from include/asm-m68k/io.h rename to arch/m68k/include/asm/io.h diff --git a/arch/m68k/include/asm/m520x.h b/arch/m68k/include/asm/m520x.h new file mode 100644 index 0000000000..71f147e751 --- /dev/null +++ b/arch/m68k/include/asm/m520x.h @@ -0,0 +1,357 @@ +/* + * m520x.h -- Definitions for Freescale Coldfire 520x + * + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __M520X__ +#define __M520X__ + +/* *** System Control Module (SCM) *** */ +#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) +#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) +#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) +#define MPROT_MTR 4 +#define MPROT_MTW 2 +#define MPROT_MPL 1 + +#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) +#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) +#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) + +#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) + +#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) +#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) +#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) +#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) +#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) +#define SCM_PACRC_PACR23(x) ((x) & 0x0F) + +#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) +#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) +#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) +#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) +#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) +#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) +#define SCM_PACRD_PACR31(x) ((x) & 0x0F) + +#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) +#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) +#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) +#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) +#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) + +#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) +#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) +#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) + +#define PACR_SP 4 +#define PACR_WP 2 +#define PACR_TP 1 + +#define SCM_BMT_BME (0x00000008) +#define SCM_BMT_BMT(x) ((x) & 0x07) +#define SCM_BMT_BMT1024 (0x0000) +#define SCM_BMT_BMT512 (0x0001) +#define SCM_BMT_BMT256 (0x0002) +#define SCM_BMT_BMT128 (0x0003) +#define SCM_BMT_BMT64 (0x0004) +#define SCM_BMT_BMT32 (0x0005) +#define SCM_BMT_BMT16 (0x0006) +#define SCM_BMT_BMT8 (0x0007) + +#define SCM_CWCR_RO (0x8000) +#define SCM_CWCR_CWR_WH (0x0100) +#define SCM_CWCR_CWE (0x0080) +#define SCM_CWRI_WINDOW (0x0060) +#define SCM_CWRI_RESET (0x0040) +#define SCM_CWRI_INT_RESET (0x0020) +#define SCM_CWRI_INT (0x0000) +#define SCM_CWCR_CWT(x) (((x) & 0x001F)) + +#define SCM_ISR_CFEI (0x02) +#define SCM_ISR_CWIC (0x01) + +#define SCM_CFIER_ECFEI (0x01) + +#define SCM_CFLOC_LOC (0x80) + +#define SCM_CFATR_WRITE (0x80) +#define SCM_CFATR_SZ32 (0x20) +#define SCM_CFATR_SZ16 (0x10) +#define SCM_CFATR_SZ08 (0x00) +#define SCM_CFATR_CACHE (0x08) +#define SCM_CFATR_MODE (0x02) +#define SCM_CFATR_TYPE (0x01) + +/* *** Interrupt Controller (INTC) *** */ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT_F1 (1) +#define INT0_LO_EPORT_F4 (2) +#define INT0_LO_EPORT_F7 (3) +#define INT1_LO_PIT0 (4) +#define INT1_LO_PIT1 (5) +/* 6 - 7 rsvd */ +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM_CWIC (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +/* 29 rsvd */ +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) + +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC0_TXF (36) +#define INT0_HI_FEC0_TXB (37) +#define INT0_HI_FEC0_UN (38) +#define INT0_HI_FEC0_RL (39) +#define INT0_HI_FEC0_RXF (40) +#define INT0_HI_FEC0_RXB (41) +#define INT0_HI_FEC0_MII (42) +#define INT0_HI_FEC0_LC (43) +#define INT0_HI_FEC0_HBERR (44) +#define INT0_HI_FEC0_GRA (45) +#define INT0_HI_FEC0_EBERR (46) +#define INT0_HI_FEC0_BABT (47) +#define INT0_HI_FEC0_BABR (48) +/* 49 - 61 rsvd */ +#define INT0_HI_SCMISR_CFEI (62) + +/* *** Reset Controller Module (RCM) *** */ +#define RCM_RCR_SOFTRST (0x80) +#define RCM_RCR_FRCRSTOUT (0x40) + +#define RCM_RSR_SOFT (0x20) +#define RCM_RSR_WDOG (0x10) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_LOL (0x01) + +/* *** Chip Configuration Module (CCM) *** */ +#define CCM_CCR_CSC (0x0200) +#define CCM_CCR_OSCFREQ (0x0080) +#define CCM_CCR_LIMP (0x0040) +#define CCM_CCR_LOAD (0x0020) +#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3) +#define CCM_CCR_OSC_MODE (0x0004) +#define CCM_CCR_PLL_MODE (0x0002) +#define CCM_CCR_RESERVED (0x0001) + +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) + +/* *** General Purpose I/O (GPIO) *** */ +#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F) +#define GPIO_PDR_BE(x) ((x) & 0x0F) +#define GPIO_PDR_CS(x) (((x) & 0x07) << 1) +#define GPIO_PDR_FECI2C(x) ((x) & 0x0F) +#define GPIO_PDR_QSPI(x) ((x) & 0x0F) +#define GPIO_PDR_TIMER(x) ((x) & 0x0F) +#define GPIO_PDR_UART(x) ((x) & 0xFF) +#define GPIO_PDR_FECH(x) ((x) & 0xFF) +#define GPIO_PDR_FECL(x) ((x) & 0xFF) + +#define GPIO_PAR_FBCTL_OE (0x10) +#define GPIO_PAR_FBCTL_TA (0x08) +#define GPIO_PAR_FBCTL_RWB (0x04) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC) +#define GPIO_PAR_FBCTL_TS_TS (0x03) +#define GPIO_PAR_FBCTL_TS_DMA (0x02) + +#define GPIO_PAR_BE3 (0x08) +#define GPIO_PAR_BE2 (0x04) +#define GPIO_PAR_BE1 (0x02) +#define GPIO_PAR_BE0 (0x01) + +#define GPIO_PAR_CS3 (0x08) +#define GPIO_PAR_CS2 (0x04) +#define GPIO_PAR_CS1_UNMASK (0xFC) +#define GPIO_PAR_CS1_CS1 (0x03) +#define GPIO_PAR_CS1_SDCS1 (0x02) + +#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F) +#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F) +#define GPIO_PAR_FECI2C_MDC_MDC (0xC0) +#define GPIO_PAR_FECI2C_MDC_SCL (0x80) +#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40) +#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF) +#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30) +#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) +#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10) +#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3) +#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) +#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC) +#define GPIO_PAR_FECI2C_SDA_SDA (0x03) +#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01) + +#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F) +#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0) +#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80) +#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40) +#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF) +#define GPIO_PAR_QSPI_DIN_DIN (0x30) +#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20) +#define GPIO_PAR_QSPI_DIN_U2CTS (0x10) +#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3) +#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C) +#define GPIO_PAR_QSPI_DOUT_SDA (0x08) +#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC) +#define GPIO_PAR_QSPI_SCK_SCK (0x03) +#define GPIO_PAR_QSPI_SCK_SCL (0x02) + +#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6) +#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4) +#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2) +#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03) +#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F) +#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0) +#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80) +#define GPIO_PAR_TMR_TIN3_U2CTS (0x40) +#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF) +#define GPIO_PAR_TMR_TIN2_TIN2 (0x30) +#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20) +#define GPIO_PAR_TMR_TIN2_U2RTS (0x10) +#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3) +#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C) +#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08) +#define GPIO_PAR_TMR_TIN1_U2RXD (0x04) +#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC) +#define GPIO_PAR_TMR_TIN0_TIN0 (0x03) +#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02) +#define GPIO_PAR_TMR_TIN0_U2TXD (0x01) + +#define GPIO_PAR_UART1_UNMASK (0xF03F) +#define GPIO_PAR_UART0_UNMASK (0xFFC0) +#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00) +#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800) +#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400) +#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300) +#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200) +#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100) +#define GPIO_PAR_UART_U1TXD (0x0080) +#define GPIO_PAR_UART_U1RXD (0x0040) +#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF) +#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030) +#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020) +#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010) +#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3) +#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C) +#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008) +#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004) +#define GPIO_PAR_UART_U0TXD (0x0002) +#define GPIO_PAR_UART_U0RXD (0x0001) + +#define GPIO_PAR_FEC_7W_UNMASK (0xF3) +#define GPIO_PAR_FEC_7W_FEC (0x0C) +#define GPIO_PAR_FEC_7W_U1RTS (0x04) +#define GPIO_PAR_FEC_MII_UNMASK (0xFC) +#define GPIO_PAR_FEC_MII_FEC (0x03) +#define GPIO_PAR_FEC_MII_UnCTS (0x01) + +#define GPIO_PAR_IRQ_IRQ4 (0x01) + +#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6) +#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4) +#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2) +#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03) +#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F) +#define GPIO_MSCR_FB_DUP_UNMASK (0xCF) +#define GPIO_MSCR_FB_DLO_UNMASK (0xF3) +#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC) + +#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4) +#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2) +#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03) +#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF) +#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3) +#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC) + +#define MSCR_25VDDR (0x03) +#define MSCR_18VDDR_FULL (0x02) +#define MSCR_OPENDRAIN (0x01) +#define MSCR_18VDDR_HALF (0x00) + +#define GPIO_DSCR_I2C(x) ((x) & 0x03) +#define GPIO_DSCR_I2C_UNMASK (0xFC) + +#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4) +#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF) +#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2) +#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3) +#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03) +#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC) + +#define GPIO_DSCR_FEC(x) ((x) & 0x03) +#define GPIO_DSCR_FEC_UNMASK (0xFC) + +#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4) +#define GPIO_DSCR_UART_UART1_UNMASK (0xCF) +#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2) +#define GPIO_DSCR_UART_UART0_UNMASK (0xF3) +#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03) +#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC) + +#define GPIO_DSCR_QSPI(x) ((x) & 0x03) +#define GPIO_DSCR_QSPI_UNMASK (0xFC) + +#define DSCR_50PF (0x03) +#define DSCR_30PF (0x02) +#define DSCR_20PF (0x01) +#define DSCR_10PF (0x00) + +/* *** Phase Locked Loop (PLL) *** */ +#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4) +#define PLL_PODR_CPUDIV_UNMASK (0x0F) +#define PLL_PODR_BUSDIV(x) ((x) & 0x0F) +#define PLL_PODR_BUSDIV_UNMASK (0xF0) + +#define PLL_PCR_DITHEN (0x80) +#define PLL_PCR_DITHDEV(x) ((x) & 0x07) +#define PLL_PCR_DITHDEV_UNMASK (0xF8) + +#endif /* __M520X__ */ diff --git a/arch/m68k/include/asm/m5227x.h b/arch/m68k/include/asm/m5227x.h new file mode 100644 index 0000000000..c77d5dd657 --- /dev/null +++ b/arch/m68k/include/asm/m5227x.h @@ -0,0 +1,563 @@ +/* + * MCF5227x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCF5227X__ +#define __MCF5227X__ + +/* Interrupt Controller (INTC) */ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM_CWIC (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_I2C (30) +#define INT0_LO_DSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_SCMIR (62) +#define INT0_HI_RTC_ISR (63) + +#define INT1_HI_CAN_BOFFINT (1) +#define INT1_HI_CAN_ERRINT (3) +#define INT1_HI_CAN_BUF0I (4) +#define INT1_HI_CAN_BUF1I (5) +#define INT1_HI_CAN_BUF2I (6) +#define INT1_HI_CAN_BUF3I (7) +#define INT1_HI_CAN_BUF4I (8) +#define INT1_HI_CAN_BUF5I (9) +#define INT1_HI_CAN_BUF6I (10) +#define INT1_HI_CAN_BUF7I (11) +#define INT1_HI_CAN_BUF8I (12) +#define INT1_HI_CAN_BUF9I (13) +#define INT1_HI_CAN_BUF10I (14) +#define INT1_HI_CAN_BUF11I (15) +#define INT1_HI_CAN_BUF12I (16) +#define INT1_HI_CAN_BUF13I (17) +#define INT1_HI_CAN_BUF14I (18) +#define INT1_HI_CAN_BUF15I (19) +#define INT1_HI_PIT0_PIF (43) +#define INT1_HI_PIT1_PIF (44) +#define INT1_HI_USBOTG_STS (47) +#define INT1_HI_SSI_ISR (49) +#define INT1_HI_PWM_INT (50) +#define INT1_HI_LCDC_ISR (51) +#define INT1_HI_CCM_UOCSR (53) +#define INT1_HI_DSPI_EOQF (54) +#define INT1_HI_DSPI_TFFF (55) +#define INT1_HI_DSPI_TCF (56) +#define INT1_HI_DSPI_TFUF (57) +#define INT1_HI_DSPI_RFDF (58) +#define INT1_HI_DSPI_RFOF (59) +#define INT1_HI_DSPI_RFOF_TFUF (60) +#define INT1_HI_TOUCH_ADC (61) +#define INT1_HI_PLL_LOCKS (62) + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +/* Bit definitions and macros for RCR */ +#define RCM_RCR_FRCRSTOUT (0x40) +#define RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for RSR */ +#define RCM_RSR_LOL (0x01) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_SOFT (0x20) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +/* Bit definitions and macros for CCR */ +#define CCM_CCR_DRAMSEL (0x0100) +#define CCM_CCR_CSC_UNMASK (0xFF3F) +#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) +#define CCM_CCR_CSC_FBCS5_A22 (0x0080) +#define CCM_CCR_CSC_FB_A23_A22 (0x0040) +#define CCM_CCR_LIMP (0x0020) +#define CCM_CCR_LOAD (0x0010) +#define CCM_CCR_BOOTPS_UNMASK (0xFFF3) +#define CCM_CCR_BOOTPS_PS16 (0x0008) +#define CCM_CCR_BOOTPS_PS8 (0x0004) +#define CCM_CCR_BOOTPS_PS32 (0x0000) +#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) + +/* Bit definitions and macros for RCON */ +#define CCM_RCON_CSC_UNMASK (0xFF3F) +#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) +#define CCM_RCON_CSC_FBCS5_A22 (0x0080) +#define CCM_RCON_CSC_FB_A23_A22 (0x0040) +#define CCM_RCON_LIMP (0x0020) +#define CCM_RCON_LOAD (0x0010) +#define CCM_RCON_BOOTPS_UNMASK (0xFFF3) +#define CCM_RCON_BOOTPS_PS16 (0x0008) +#define CCM_RCON_BOOTPS_PS8 (0x0004) +#define CCM_RCON_BOOTPS_PS32 (0x0000) +#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) + +/* Bit definitions and macros for CIR */ +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) +#define CCM_CIR_PIN_MCF52277 (0x0000) + +/* Bit definitions and macros for MISCCR */ +#define CCM_MISCCR_RTCSRC (0x4000) +#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */ +#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ + +#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */ +#define CCM_MISCCR_BMT_65536 (0) +#define CCM_MISCCR_BMT_32768 (1) +#define CCM_MISCCR_BMT_16384 (2) +#define CCM_MISCCR_BMT_8192 (3) +#define CCM_MISCCR_BMT_4096 (4) +#define CCM_MISCCR_BMT_2048 (5) +#define CCM_MISCCR_BMT_1024 (6) +#define CCM_MISCCR_BMT_512 (7) + +#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ +#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ +#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ +#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ +#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */ +#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */ +#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ + +/* Bit definitions and macros for CDR */ +#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12) +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */ +#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */ + +/* Bit definitions and macros for UOCSR */ +#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */ +#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */ +#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */ +#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */ +#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */ +#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ +#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ +#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ +#define CCM_UOCSR_SEND (0x0010) /* Session end */ +#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ +#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */ +#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */ + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ +/* Bit definitions and macros for PAR_BE */ +#define GPIO_PAR_BE_UNMASK (0x0F) +#define GPIO_PAR_BE_BE3_BE3 (0x08) +#define GPIO_PAR_BE_BE3_GPIO (0x00) +#define GPIO_PAR_BE_BE2_BE2 (0x04) +#define GPIO_PAR_BE_BE2_GPIO (0x00) +#define GPIO_PAR_BE_BE1_BE1 (0x02) +#define GPIO_PAR_BE_BE1_GPIO (0x00) +#define GPIO_PAR_BE_BE0_BE0 (0x01) +#define GPIO_PAR_BE_BE0_GPIO (0x00) + +/* Bit definitions and macros for PAR_CS */ +#define GPIO_PAR_CS_CS3 (0x10) +#define GPIO_PAR_CS_CS2 (0x08) +#define GPIO_PAR_CS_CS1_FBCS1 (0x06) +#define GPIO_PAR_CS_CS1_SDCS1 (0x04) +#define GPIO_PAR_CS_CS1_GPIO (0x00) +#define GPIO_PAR_CS_CS0 (0x01) + +/* Bit definitions and macros for PAR_FBCTL */ +#define GPIO_PAR_FBCTL_OE (0x80) +#define GPIO_PAR_FBCTL_TA (0x40) +#define GPIO_PAR_FBCTL_RW (0x20) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) +#define GPIO_PAR_FBCTL_TS_FBTS (0x18) +#define GPIO_PAR_FBCTL_TS_DMAACK (0x10) +#define GPIO_PAR_FBCTL_TS_GPIO (0x00) + +/* Bit definitions and macros for PAR_FECI2C */ +#define GPIO_PAR_I2C_SCL_UNMASK (0xF3) +#define GPIO_PAR_I2C_SCL_SCL (0x0C) +#define GPIO_PAR_I2C_SCL_CANTXD (0x08) +#define GPIO_PAR_I2C_SCL_U2TXD (0x04) +#define GPIO_PAR_I2C_SCL_GPIO (0x00) + +#define GPIO_PAR_I2C_SDA_UNMASK (0xFC) +#define GPIO_PAR_I2C_SDA_SDA (0x03) +#define GPIO_PAR_I2C_SDA_CANRXD (0x02) +#define GPIO_PAR_I2C_SDA_U2RXD (0x01) +#define GPIO_PAR_I2C_SDA_GPIO (0x00) + +/* Bit definitions and macros for PAR_UART */ +#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF) +#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) +#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) +#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) +#define GPIO_PAR_UART_U1CTS_GPIO (0x0000) + +#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) +#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) +#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) +#define GPIO_PAR_UART_U1RTS_GPIO (0x0000) + +#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) +#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) +#define GPIO_PAR_UART_U1RXD_GPIO (0x0000) + +#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) +#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) +#define GPIO_PAR_UART_U1TXD_GPIO (0x0000) + +#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F) +#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) +#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) +#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) +#define GPIO_PAR_UART_U0CTS_GPIO (0x0000) + +#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF) +#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) +#define GPIO_PAR_UART_U0RTS_T1IN (0x0020) +#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) +#define GPIO_PAR_UART_U0RTS_GPIO (0x0000) + +#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3) +#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) +#define GPIO_PAR_UART_U0RXD_CANRX (0x0008) +#define GPIO_PAR_UART_U0RXD_GPIO (0x0000) + +#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC) +#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) +#define GPIO_PAR_UART_U0TXD_CANTX (0x0002) +#define GPIO_PAR_UART_U0TXD_GPIO (0x0000) + +/* Bit definitions and macros for PAR_DSPI */ +#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F) +#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) +#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) +#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) +#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF) +#define GPIO_PAR_DSPI_SIN_SIN (0x30) +#define GPIO_PAR_DSPI_SIN_U2RXD (0x20) +#define GPIO_PAR_DSPI_SIN_GPIO (0x00) +#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3) +#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) +#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) +#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) +#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC) +#define GPIO_PAR_DSPI_SCK_SCK (0x03) +#define GPIO_PAR_DSPI_SCK_U2CTS (0x02) +#define GPIO_PAR_DSPI_SCK_GPIO (0x00) + +/* Bit definitions and macros for PAR_TIMER */ +#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) +#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) +#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) +#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) +#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) +#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) +#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) +#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) +#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) +#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) +#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) +#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) +#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) + +/* Bit definitions and macros for GPIO_PAR_LCDCTL */ +#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7) +#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) +#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) +#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) +#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04) +#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02) +#define GPIO_PAR_LCDCTL_LSCLK (0x01) + +/* Bit definitions and macros for PAR_IRQ */ +#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3) +#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) +#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) +#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) +#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC) +#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) +#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) +#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) +#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) + +/* Bit definitions and macros for GPIO_PAR_LCDH */ +#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF) +#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) +#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) +#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF) +#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) +#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) +#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F) +#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) +#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) +#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF) +#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) +#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) +#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3) +#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) +#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) +#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC) +#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) +#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) +#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) + +/* Bit definitions and macros for GPIO_PAR_LCDL */ +#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF) +#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) +#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) +#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF) +#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) +#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) +#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF) +#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) +#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) +#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF) +#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) +#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) +#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF) +#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) +#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) +#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF) +#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) +#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) +#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF) +#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) +#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) +#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF) +#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) +#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) +#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF) +#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) +#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) +#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF) +#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) +#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) +#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF) +#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) +#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) +#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF) +#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) +#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) +#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) + +/* Bit definitions and macros for MSCR_FB */ +#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF) +#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) +#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) +#define GPIO_MSCR_FB_DUPPER_OD (0x10) +#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) + +#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3) +#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) +#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) +#define GPIO_MSCR_FB_DLOWER_OD (0x04) +#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) + +#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC) +#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) +#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) +#define GPIO_MSCR_FB_ADDRCTL_OD (0x01) +#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) + +/* Bit definitions and macros for MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF) +#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) +#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) +#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) +#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) + +#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) +#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) +#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) +#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) + +#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) +#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) +#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) +#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00) + +/* Bit definitions and macros for Drive Strength Control */ +#define DSCR_LOAD_50PF (0x03) +#define DSCR_LOAD_30PF (0x02) +#define DSCR_LOAD_20PF (0x01) +#define DSCR_LOAD_10PF (0x00) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +/* Bit definitions and macros for SDMR */ +#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ +#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ +#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ +#define SDRAMC_SDMR_BK_LMR (0x00000000) +#define SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for SDCR */ +#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ +#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ +#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ +#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ +#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ +#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ +#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ +#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ +#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ +#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ +#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ +#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) + +/* Bit definitions and macros for SDCFG1 */ +#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ +#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ +#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ +#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ + +/* Bit definitions and macros for SDCFG2 */ +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ +#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ +#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ +#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ + +/* Bit definitions and macros for SDCS group */ +#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ +#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +/* Bit definitions and macros for PCR */ +#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ +#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */ +#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */ +#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ +#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ +#define PLL_PCR_PFDR_MASK (0x000F0000) +#define PLL_PCR_OUTDIV5_MASK (0x000F0000) +#define PLL_PCR_OUTDIV3_MASK (0x00000F00) +#define PLL_PCR_OUTDIV2_MASK (0x000000F0) +#define PLL_PCR_OUTDIV1_MASK (0x0000000F) + +/* Bit definitions and macros for PSR */ +#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ +#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ +#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ +#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ + +/********************************************************************/ + +#endif /* __MCF5227X__ */ diff --git a/arch/m68k/include/asm/m5235.h b/arch/m68k/include/asm/m5235.h new file mode 100644 index 0000000000..71a40d33d2 --- /dev/null +++ b/arch/m68k/include/asm/m5235.h @@ -0,0 +1,602 @@ +/* + * mcf5329.h -- Definitions for Freescale Coldfire 5329 + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef mcf5235_h +#define mcf5235_h +/****************************************************************************/ + +/********************************************************************* +* System Control Module (SCM) +*********************************************************************/ + +/* Bit definition and macros for SCM_IPSBAR */ +#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) +#define SCM_IPSBAR_V (0x00000001) + +/* Bit definition and macros for SCM_RAMBAR */ +#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) +#define SCM_RAMBAR_BDE (0x00000200) + +/* Bit definition and macros for SCM_CRSR */ +#define SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for SCM_CWCR */ +#define SCM_CWCR_CWE (0x80) +#define SCM_CWCR_CWRI (0x40) +#define SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define SCM_CWCR_CWTA (0x04) +#define SCM_CWCR_CWTAVAL (0x02) +#define SCM_CWCR_CWTIC (0x01) + +/* Bit definitions and macros for SCM_LPICR */ +#define SCM_LPICR_ENBSTOP (0x80) +#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) +#define SCM_LPICR_XLPM_IPL_ANY (0x00) +#define SCM_LPICR_XLPM_IPL_L2_7 (0x10) +#define SCM_LPICR_XLPM_IPL_L3_7 (0x20) +#define SCM_LPICR_XLPM_IPL_L4_7 (0x30) +#define SCM_LPICR_XLPM_IPL_L5_7 (0x40) +#define SCM_LPICR_XLPM_IPL_L6_7 (0x50) +#define SCM_LPICR_XLPM_IPL_L7 (0x70) + +/* Bit definitions and macros for SCM_DMAREQC */ +#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) +#define SCM_DMAREQC_EXT_ETPU (0x00080000) +#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000) +#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000) +#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000) +#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) +#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) +#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) +#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) +#define SCM_DMAREQC_DMACn_DTMR0 (0x04) +#define SCM_DMAREQC_DMACn_DTMR1 (0x05) +#define SCM_DMAREQC_DMACn_DTMR2 (0x06) +#define SCM_DMAREQC_DMACn_DTMR3 (0x07) +#define SCM_DMAREQC_DMACn_UART0RX (0x08) +#define SCM_DMAREQC_DMACn_UART1RX (0x09) +#define SCM_DMAREQC_DMACn_UART2RX (0x0A) +#define SCM_DMAREQC_DMACn_UART0TX (0x0C) +#define SCM_DMAREQC_DMACn_UART1TX (0x0D) +#define SCM_DMAREQC_DMACn_UART3TX (0x0E) + +/* Bit definitions and macros for SCM_MPARK */ +#define SCM_MPARK_M2_P_EN (0x02000000) +#define SCM_MPARK_M3_PRTY_MSK (0x00C00000) +#define SCM_MPARK_M3_PRTY_4TH (0x00000000) +#define SCM_MPARK_M3_PRTY_3RD (0x00400000) +#define SCM_MPARK_M3_PRTY_2ND (0x00800000) +#define SCM_MPARK_M3_PRTY_1ST (0x00C00000) +#define SCM_MPARK_M2_PRTY_MSK (0x00300000) +#define SCM_MPARK_M2_PRTY_4TH (0x00000000) +#define SCM_MPARK_M2_PRTY_3RD (0x00100000) +#define SCM_MPARK_M2_PRTY_2ND (0x00200000) +#define SCM_MPARK_M2_PRTY_1ST (0x00300000) +#define SCM_MPARK_M0_PRTY_MSK (0x000C0000) +#define SCM_MPARK_M0_PRTY_4TH (0x00000000) +#define SCM_MPARK_M0_PRTY_3RD (0x00040000) +#define SCM_MPARK_M0_PRTY_2ND (0x00080000) +#define SCM_MPARK_M0_PRTY_1ST (0x000C0000) +#define SCM_MPARK_FIXED (0x00004000) +#define SCM_MPARK_TIMEOUT (0x00002000) +#define SCM_MPARK_PRKLAST (0x00001000) +#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) + +/* Bit definitions and macros for SCM_MPR */ +#define SCM_MPR_MPR3 (0x08) +#define SCM_MPR_MPR2 (0x04) +#define SCM_MPR_MPR1 (0x02) +#define SCM_MPR_MPR0 (0x01) + +/* Bit definitions and macros for SCM_PACRn */ +#define SCM_PACRn_LOCK1 (0x80) +#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4) +#define SCM_PACRn_LOCK0 (0x08) +#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) + +/* Bit definitions and macros for SCM_GPACR */ +#define SCM_PACRn_LOCK (0x80) +#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ +/* Bit definitions and macros for SDRAMC_DCR */ +#define SDRAMC_DCR_NAM (0x2000) +#define SDRAMC_DCR_COC (0x1000) +#define SDRAMC_DCR_IS (0x0800) +#define SDRAMC_DCR_RTIM_MASK (0x0C00) +#define SDRAMC_DCR_RTIM_3CLKS (0x0000) +#define SDRAMC_DCR_RTIM_6CLKS (0x0200) +#define SDRAMC_DCR_RTIM_9CLKS (0x0400) +#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8) + +/* Bit definitions and macros for SDRAMC_DARCn */ +#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18) +#define SDRAMC_DARCn_RE (0x00008000) +#define SDRAMC_DARCn_CASL_MASK (0x00003000) +#define SDRAMC_DARCn_CASL_C0 (0x00000000) +#define SDRAMC_DARCn_CASL_C1 (0x00001000) +#define SDRAMC_DARCn_CASL_C2 (0x00002000) +#define SDRAMC_DARCn_CASL_C3 (0x00003000) +#define SDRAMC_DARCn_CBM_MASK (0x00000700) +#define SDRAMC_DARCn_CBM_CMD17 (0x00000000) +#define SDRAMC_DARCn_CBM_CMD18 (0x00000100) +#define SDRAMC_DARCn_CBM_CMD19 (0x00000200) +#define SDRAMC_DARCn_CBM_CMD20 (0x00000300) +#define SDRAMC_DARCn_CBM_CMD21 (0x00000400) +#define SDRAMC_DARCn_CBM_CMD22 (0x00000500) +#define SDRAMC_DARCn_CBM_CMD23 (0x00000600) +#define SDRAMC_DARCn_CBM_CMD24 (0x00000700) +#define SDRAMC_DARCn_IMRS (0x00000040) +#define SDRAMC_DARCn_PS_MASK (0x00000030) +#define SDRAMC_DARCn_PS_32 (0x00000000) +#define SDRAMC_DARCn_PS_16 (0x00000010) +#define SDRAMC_DARCn_PS_8 (0x00000020) +#define SDRAMC_DARCn_IP (0x00000008) + +/* Bit definitions and macros for SDRAMC_DMRn */ +#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18) +#define SDRAMC_DMRn_WP (0x00000100) +#define SDRAMC_DMRn_V (0x00000001) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_SCM (8) +#define INT0_LO_DMA0 (9) +#define INT0_LO_DMA1 (10) +#define INT0_LO_DMA2 (11) +#define INT0_LO_DMA3 (12) +#define INT0_LO_UART0 (13) +#define INT0_LO_UART1 (14) +#define INT0_LO_UART2 (15) +#define INT0_LO_RSVD1 (16) +#define INT0_LO_I2C (17) +#define INT0_LO_QSPI (18) +#define INT0_LO_DTMR0 (19) +#define INT0_LO_DTMR1 (20) +#define INT0_LO_DTMR2 (21) +#define INT0_LO_DTMR3 (22) +#define INT0_LO_FEC_TXF (23) +#define INT0_LO_FEC_TXB (24) +#define INT0_LO_FEC_UN (25) +#define INT0_LO_FEC_RL (26) +#define INT0_LO_FEC_RXF (27) +#define INT0_LO_FEC_RXB (28) +#define INT0_LO_FEC_MII (29) +#define INT0_LO_FEC_LC (30) +#define INT0_LO_FEC_HBERR (31) +#define INT0_HI_FEC_GRA (32) +#define INT0_HI_FEC_EBERR (33) +#define INT0_HI_FEC_BABT (34) +#define INT0_HI_FEC_BABR (35) +#define INT0_HI_PIT0 (36) +#define INT0_HI_PIT1 (37) +#define INT0_HI_PIT2 (38) +#define INT0_HI_PIT3 (39) +#define INT0_HI_RNG (40) +#define INT0_HI_SKHA (41) +#define INT0_HI_MDHA (42) +#define INT0_HI_CAN1_BUF0I (43) +#define INT0_HI_CAN1_BUF1I (44) +#define INT0_HI_CAN1_BUF2I (45) +#define INT0_HI_CAN1_BUF3I (46) +#define INT0_HI_CAN1_BUF4I (47) +#define INT0_HI_CAN1_BUF5I (48) +#define INT0_HI_CAN1_BUF6I (49) +#define INT0_HI_CAN1_BUF7I (50) +#define INT0_HI_CAN1_BUF8I (51) +#define INT0_HI_CAN1_BUF9I (52) +#define INT0_HI_CAN1_BUF10I (53) +#define INT0_HI_CAN1_BUF11I (54) +#define INT0_HI_CAN1_BUF12I (55) +#define INT0_HI_CAN1_BUF13I (56) +#define INT0_HI_CAN1_BUF14I (57) +#define INT0_HI_CAN1_BUF15I (58) +#define INT0_HI_CAN1_ERRINT (59) +#define INT0_HI_CAN1_BOFFINT (60) +/* 60-63 Reserved */ + +/* 0 - 7 Reserved */ +#define INT1_LO_CAN1_BUF0I (8) +#define INT1_LO_CAN1_BUF1I (9) +#define INT1_LO_CAN1_BUF2I (10) +#define INT1_LO_CAN1_BUF3I (11) +#define INT1_LO_CAN1_BUF4I (12) +#define INT1_LO_CAN1_BUF5I (13) +#define INT1_LO_CAN1_BUF6I (14) +#define INT1_LO_CAN1_BUF7I (15) +#define INT1_LO_CAN1_BUF8I (16) +#define INT1_LO_CAN1_BUF9I (17) +#define INT1_LO_CAN1_BUF10I (18) +#define INT1_LO_CAN1_BUF11I (19) +#define INT1_LO_CAN1_BUF12I (20) +#define INT1_LO_CAN1_BUF13I (21) +#define INT1_LO_CAN1_BUF14I (22) +#define INT1_LO_CAN1_BUF15I (23) +#define INT1_LO_CAN1_ERRINT (24) +#define INT1_LO_CAN1_BOFFINT (25) +/* 26 Reserved */ +#define INT1_LO_ETPU_TC0F (27) +#define INT1_LO_ETPU_TC1F (28) +#define INT1_LO_ETPU_TC2F (29) +#define INT1_LO_ETPU_TC3F (30) +#define INT1_LO_ETPU_TC4F (31) +#define INT1_HI_ETPU_TC5F (32) +#define INT1_HI_ETPU_TC6F (33) +#define INT1_HI_ETPU_TC7F (34) +#define INT1_HI_ETPU_TC8F (35) +#define INT1_HI_ETPU_TC9F (36) +#define INT1_HI_ETPU_TC10F (37) +#define INT1_HI_ETPU_TC11F (38) +#define INT1_HI_ETPU_TC12F (39) +#define INT1_HI_ETPU_TC13F (40) +#define INT1_HI_ETPU_TC14F (41) +#define INT1_HI_ETPU_TC15F (42) +#define INT1_HI_ETPU_TC16F (43) +#define INT1_HI_ETPU_TC17F (44) +#define INT1_HI_ETPU_TC18F (45) +#define INT1_HI_ETPU_TC19F (46) +#define INT1_HI_ETPU_TC20F (47) +#define INT1_HI_ETPU_TC21F (48) +#define INT1_HI_ETPU_TC22F (49) +#define INT1_HI_ETPU_TC23F (50) +#define INT1_HI_ETPU_TC24F (51) +#define INT1_HI_ETPU_TC25F (52) +#define INT1_HI_ETPU_TC26F (53) +#define INT1_HI_ETPU_TC27F (54) +#define INT1_HI_ETPU_TC28F (55) +#define INT1_HI_ETPU_TC29F (56) +#define INT1_HI_ETPU_TC30F (57) +#define INT1_HI_ETPU_TC31F (58) +#define INT1_HI_ETPU_TGIF (59) + +/********************************************************************* +* General Purpose I/O (GPIO) +*********************************************************************/ +/* Bit definitions and macros for GPIO_PODR */ +#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5) +#define GPIO_PODR_ADDR_MASK (0xE0) +#define GPIO_PODR_BS(x) ((x)&0x0F) +#define GPIO_PODR_BS_MASK (0x0F) +#define GPIO_PODR_CS(x) (((x)&0x7F)<<1) +#define GPIO_PODR_CS_MASK (0xFE) +#define GPIO_PODR_SDRAM(X) ((x)&0x3F) +#define GPIO_PODR_SDRAM_MASK (0x3F) +#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x) +#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK +#define GPIO_PODR_UARTH(x) ((x)&0x03) +#define GPIO_PODR_UARTH_MASK (0x03) +#define GPIO_PODR_QSPI(x) ((x)&0x1F) +#define GPIO_PODR_QSPI_MASK (0x1F) +#define GPIO_PODR_ETPU(x) ((x)&0x07) +#define GPIO_PODR_ETPU_MASK (0x07) + +/* Bit definitions and macros for GPIO_PDDR */ +#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x) +#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK +#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PPDSDR */ +#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x) +#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK +#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PCLRR */ +#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x) +#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK +#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x) +#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK +#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x) +#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK +#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X) +#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK +#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x) +#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK +#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x) +#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK +#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x) +#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK +#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x) +#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK + +/* Bit definitions and macros for GPIO_PAR */ +#define GPIO_PAR_AD_ADDR23 (0x80) +#define GPIO_PAR_AD_ADDR22 (0x40) +#define GPIO_PAR_AD_ADDR21 (0x20) +#define GPIO_PAR_AD_DATAL (0x01) +#define GPIO_PAR_BUSCTL_OE (0x4000) +#define GPIO_PAR_BUSCTL_TA (0x1000) +#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10) +#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00) +#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400) +#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800) +#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00) +#define GPIO_PAR_BUSCTL_RWB (0x0100) +#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040) +#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010) +#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2) +#define GPIO_PAR_BUSCTL_TS_MASK (0x0C) +#define GPIO_PAR_BUSCTL_TS_GPIO (0x04) +#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08) +#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C) +#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03) +#define GPIO_PAR_BUSCTL_TIP_MASK (0x03) +#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01) +#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02) +#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03) +#define GPIO_PAR_BS(x) ((x)&0x0F) +#define GPIO_PAR_BS_MASK (0x0F) +#define GPIO_PAR_CS(x) (((x)&0x7F)<<1) +#define GPIO_PAR_CS_MASK (0xFE) +#define GPIO_PAR_CS_CS7 (0x80) +#define GPIO_PAR_CS_CS6 (0x40) +#define GPIO_PAR_CS_CS5 (0x20) +#define GPIO_PAR_CS_CS4 (0x10) +#define GPIO_PAR_CS_CS3 (0x08) +#define GPIO_PAR_CS_CS2 (0x04) +#define GPIO_PAR_CS_CS1 (0x02) +#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3 +#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2 +#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6) +#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0) +#define GPIO_PAR_SDRAM_SDWE (0x20) +#define GPIO_PAR_SDRAM_SCAS (0x10) +#define GPIO_PAR_SDRAM_SRAS (0x08) +#define GPIO_PAR_SDRAM_SCKE (0x04) +#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03) +#define GPIO_PAR_SDRAM_SDCS_MASK (0x03) +#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6) +#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0) +#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40) +#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80) +#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0) +#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4) +#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30) +#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10) +#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20) +#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) +#define GPIO_PAR_FECI2C_SCL_MASK (0x0C) +#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08) +#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C) +#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03) +#define GPIO_PAR_FECI2C_SDA_MASK (0x03) +#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02) +#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03) +#define GPIO_PAR_UART_DREQ2 (0x8000) +#define GPIO_PAR_UART_CAN1EN (0x4000) +#define GPIO_PAR_UART_U2RXD (0x2000) +#define GPIO_PAR_UART_U2TXD (0x1000) +#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10) +#define GPIO_PAR_UART_U1RXD_MASK (0x0C00) +#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) +#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8) +#define GPIO_PAR_UART_U1TXD_MASK (0x0300) +#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) +#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6) +#define GPIO_PAR_UART_U1CTS_MASK (0x00C0) +#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0) +#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4) +#define GPIO_PAR_UART_U1RTS_MASK (0x0030) +#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030) +#define GPIO_PAR_UART_U0RXD (0x0008) +#define GPIO_PAR_UART_U0TXD (0x0004) +#define GPIO_PAR_UART_U0CTS (0x0002) +#define GPIO_PAR_UART_U0RTS (0x0001) +#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6) +#define GPIO_PAR_QSPI_CS1_MASK (0xC0) +#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80) +#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0) +#define GPIO_PAR_QSPI_CS0 (0x20) +#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3) +#define GPIO_PAR_QSPI_DIN_MASK (0x18) +#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10) +#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18) +#define GPIO_PAR_QSPI_DOUT (0x04) +#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03) +#define GPIO_PAR_QSPI_SCK_MASK (0x03) +#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02) +#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03) +#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14) +#define GPIO_PAR_DT3IN_MASK (0xC000) +#define GPIO_PAR_DT3IN_QSPICS2 (0x4000) +#define GPIO_PAR_DT3IN_U2CTS (0x8000) +#define GPIO_PAR_DT3IN_DT3IN (0xC000) +#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12) +#define GPIO_PAR_DT2IN_MASK (0x3000) +#define GPIO_PAR_DT2IN_DT2OUT (0x1000) +#define GPIO_PAR_DT2IN_DREQ2 (0x2000) +#define GPIO_PAR_DT2IN_DT2IN (0x3000) +#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10) +#define GPIO_PAR_DT1IN_MASK (0x0C00) +#define GPIO_PAR_DT1IN_DT1OUT (0x0400) +#define GPIO_PAR_DT1IN_DREQ1 (0x0800) +#define GPIO_PAR_DT1IN_DT1IN (0x0C00) +#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8) +#define GPIO_PAR_DT0IN_MASK (0x0300) +#define GPIO_PAR_DT0IN_DREQ0 (0x0200) +#define GPIO_PAR_DT0IN_DT0IN (0x0300) +#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6) +#define GPIO_PAR_DT3OUT_MASK (0x00C0) +#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040) +#define GPIO_PAR_DT3OUT_U2RTS (0x0080) +#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0) +#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4) +#define GPIO_PAR_DT2OUT_MASK (0x0030) +#define GPIO_PAR_DT2OUT_DACK2 (0x0020) +#define GPIO_PAR_DT2OUT_DT2OUT (0x0030) +#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2) +#define GPIO_PAR_DT1OUT_MASK (0x000C) +#define GPIO_PAR_DT1OUT_DACK1 (0x0008) +#define GPIO_PAR_DT1OUT_DT1OUT (0x000C) +#define GPIO_PAR_DT0OUT(x) ((x)&0x03) +#define GPIO_PAR_DT0OUT_MASK (0x0003) +#define GPIO_PAR_DT0OUT_DACK0 (0x0002) +#define GPIO_PAR_DT0OUT_DT0OUT (0x0003) +#define GPIO_PAR_ETPU_TCRCLK (0x04) +#define GPIO_PAR_ETPU_UTPU_ODIS (0x02) +#define GPIO_PAR_ETPU_LTPU_ODIS (0x01) + +/* Bit definitions and macros for GPIO_DSCR */ +#define GPIO_DSCR_EIM_EIM1 (0x10) +#define GPIO_DSCR_EIM_EIM0 (0x01) +#define GPIO_DSCR_ETPU_ETPU31_24 (0x40) +#define GPIO_DSCR_ETPU_ETPU23_16 (0x10) +#define GPIO_DSCR_ETPU_ETPU15_8 (0x04) +#define GPIO_DSCR_ETPU_ETPU7_0 (0x01) +#define GPIO_DSCR_FECI2C_FEC (0x10) +#define GPIO_DSCR_FECI2C_I2C (0x01) +#define GPIO_DSCR_UART_IRQ (0x40) +#define GPIO_DSCR_UART_UART2 (0x10) +#define GPIO_DSCR_UART_UART1 (0x04) +#define GPIO_DSCR_UART_UART0 (0x01) +#define GPIO_DSCR_QSPI_QSPI (0x01) +#define GPIO_DSCR_TIMER (0x01) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ +/* Bit definitions and macros for CCM_RCR */ +#define CCM_RCR_SOFTRST (0x80) +#define CCM_RCR_FRCRSTOUT (0x40) + +/* Bit definitions and macros for CCM_RSR */ +#define CCM_RSR_SOFT (0x20) +#define CCM_RSR_WDR (0x10) +#define CCM_RSR_POR (0x08) +#define CCM_RSR_EXT (0x04) +#define CCM_RSR_LOC (0x02) +#define CCM_RSR_LOL (0x01) + +/* Bit definitions and macros for CCM_CCR */ +#define CCM_CCR_LOAD (0x8000) +#define CCM_CCR_SZEN (0x0040) +#define CCM_CCR_PSTEN (0x0020) +#define CCM_CCR_BME (0x0008) +#define CCM_CCR_BMT(x) ((x)&0x07) +#define CCM_CCR_BMT_MASK (0x0007) +#define CCM_CCR_BMT_64K (0x0000) +#define CCM_CCR_BMT_32K (0x0001) +#define CCM_CCR_BMT_16K (0x0002) +#define CCM_CCR_BMT_8K (0x0003) +#define CCM_CCR_BMT_4K (0x0004) +#define CCM_CCR_BMT_2K (0x0005) +#define CCM_CCR_BMT_1K (0x0006) +#define CCM_CCR_BMT_512 (0x0007) + +/* Bit definitions and macros for CCM_RCON */ +#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8) +#define CCM_RCON_RLOAD (0x0020) +#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) +#define CCM_RCON_BOOTPS_MASK (0x0018) +#define CCM_RCON_BOOTPS_32 (0x0018) +#define CCM_RCON_BOOTPS_16 (0x0008) +#define CCM_RCON_BOOTPS_8 (0x0010) +#define CCM_RCON_MODE (0x0001) + +/* Bit definitions and macros for CCM_CIR */ +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) + +/********************************************************************* +* PLL Clock Module +*********************************************************************/ +/* Bit definitions and macros for PLL_SYNCR */ +#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24) +#define PLL_SYNCR_MFD_MASK (0x07000000) +#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19) +#define PLL_SYNCR_RFC_MASK (0x00380000) +#define PLL_SYNCR_LOCEN (0x00040000) +#define PLL_SYNCR_LOLRE (0x00020000) +#define PLL_SYNCR_LOCRE (0x00010000) +#define PLL_SYNCR_DISCLK (0x00008000) +#define PLL_SYNCR_LOLIRQ (0x00004000) +#define PLL_SYNCR_LOCIRQ (0x00002000) +#define PLL_SYNCR_RATE (0x00001000) +#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10) +#define PLL_SYNCR_EXP(x) ((x)&0x03FF) + +/* Bit definitions and macros for PLL_SYNSR */ +#define PLL_SYNSR_LOLF (0x00000200) +#define PLL_SYNSR_LOC (0x00000100) +#define PLL_SYNSR_MODE (0x00000080) +#define PLL_SYNSR_PLLSEL (0x00000040) +#define PLL_SYNSR_PLLREF (0x00000020) +#define PLL_SYNSR_LOCKS (0x00000010) +#define PLL_SYNSR_LOCK (0x00000008) +#define PLL_SYNSR_LOCF (0x00000004) +#define PLL_SYNSR_CALDONE (0x00000002) +#define PLL_SYNSR_CALPASS (0x00000001) + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ +/* Bit definitions and macros for WTM_WCR */ +#define WTM_WCR_WAIT (0x0008) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_EN (0x0001) + +#endif /* mcf5235_h */ diff --git a/include/asm-m68k/m5249.h b/arch/m68k/include/asm/m5249.h similarity index 100% rename from include/asm-m68k/m5249.h rename to arch/m68k/include/asm/m5249.h diff --git a/include/asm-m68k/m5253.h b/arch/m68k/include/asm/m5253.h similarity index 100% rename from include/asm-m68k/m5253.h rename to arch/m68k/include/asm/m5253.h diff --git a/include/asm-m68k/m5271.h b/arch/m68k/include/asm/m5271.h similarity index 100% rename from include/asm-m68k/m5271.h rename to arch/m68k/include/asm/m5271.h diff --git a/include/asm-m68k/m5272.h b/arch/m68k/include/asm/m5272.h similarity index 100% rename from include/asm-m68k/m5272.h rename to arch/m68k/include/asm/m5272.h diff --git a/include/asm-m68k/m5275.h b/arch/m68k/include/asm/m5275.h similarity index 100% rename from include/asm-m68k/m5275.h rename to arch/m68k/include/asm/m5275.h diff --git a/include/asm-m68k/m5282.h b/arch/m68k/include/asm/m5282.h similarity index 100% rename from include/asm-m68k/m5282.h rename to arch/m68k/include/asm/m5282.h diff --git a/arch/m68k/include/asm/m5301x.h b/arch/m68k/include/asm/m5301x.h new file mode 100644 index 0000000000..0920a0dc2a --- /dev/null +++ b/arch/m68k/include/asm/m5301x.h @@ -0,0 +1,608 @@ +/* + * m5301x.h -- Definitions for Freescale Coldfire 5301x + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef m5301x_h +#define m5301x_h + +/* *** System Control Module (SCM) *** */ +#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) +#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) +#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) +#define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12) +#define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8) +#define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4) +#define MPROT_MTR 4 +#define MPROT_MTW 2 +#define MPROT_MPL 1 + +#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) +#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) +#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) +#define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8) + +#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) +#define SCM_PACRB_PACR13(x) (((x) & 0x0F) << 8) + +#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) +#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) +#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) +#define SCM_PACRC_PACR19(x) (((x) & 0x0F) << 16) +#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) +#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) +#define SCM_PACRC_PACR23(x) ((x) & 0x0F) + +#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) +#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) +#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) +#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) +#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) +#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) +#define SCM_PACRD_PACR31(x) ((x) & 0x0F) + +#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) +#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) +#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) +#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) +#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) +#define SCM_PACRE_PACR37(x) (((x) & 0x0F) << 8) +#define SCM_PACRE_PACR39(x) ((x) & 0x0F) + +#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) +#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) +#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) +#define SCM_PACRF_PACR43(x) (((x) & 0x0F) << 16) +#define SCM_PACRF_PACR44(x) (((x) & 0x0F) << 12) +#define SCM_PACRF_PACR45(x) (((x) & 0x0F) << 8) +#define SCM_PACRF_PACR46(x) (((x) & 0x0F) << 4) +#define SCM_PACRF_PACR47(x) ((x) & 0x0F) + +#define SCM_PACRG_PACR48(x) (((x) & 0x0F) << 28) +#define SCM_PACRG_PACR49(x) (((x) & 0x0F) << 24) +#define SCM_PACRG_PACR50(x) (((x) & 0x0F) << 20) +#define SCM_PACRG_PACR51(x) (((x) & 0x0F) << 16) + +#define PACR_SP 4 +#define PACR_WP 2 +#define PACR_TP 1 + +#define SCM_CWCR_RO (0x8000) +#define SCM_CWCR_CWR_WH (0x0100) +#define SCM_CWCR_CWE (0x0080) +#define SCM_CWCR_CWRI_WINDOW (0x0060) +#define SCM_CWCR_CWRI_RESET (0x0040) +#define SCM_CWCR_CWRI_INT_RESET (0x0020) +#define SCM_CWCR_CWRI_INT (0x0000) +#define SCM_CWCR_CWT(x) (((x) & 0x001F)) + +#define SCM_ISR_CFEI (0x02) +#define SCM_ISR_CWIC (0x01) + +#define BCR_GBR (0x00000200) +#define BCR_GBW (0x00000100) +#define BCR_S7 (0x00000080) +#define BCR_S6 (0x00000040) +#define BCR_S4 (0x00000010) +#define BCR_S1 (0x00000002) + +#define SCM_CFIER_ECFEI (0x01) + +#define SCM_CFLOC_LOC (0x80) + +#define SCM_CFATR_WRITE (0x80) +#define SCM_CFATR_SZ32 (0x20) +#define SCM_CFATR_SZ16 (0x10) +#define SCM_CFATR_SZ08 (0x00) +#define SCM_CFATR_CACHE (0x08) +#define SCM_CFATR_MODE (0x02) +#define SCM_CFATR_TYPE (0x01) + +/* *** Interrupt Controller (INTC) *** */ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM_CWIC (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_DSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC0_TXF (36) +#define INT0_HI_FEC0_TXB (37) +#define INT0_HI_FEC0_UN (38) +#define INT0_HI_FEC0_RL (39) +#define INT0_HI_FEC0_RXF (40) +#define INT0_HI_FEC0_RXB (41) +#define INT0_HI_FEC0_MII (42) +#define INT0_HI_FEC0_LC (43) +#define INT0_HI_FEC0_HBERR (44) +#define INT0_HI_FEC0_GRA (45) +#define INT0_HI_FEC0_EBERR (46) +#define INT0_HI_FEC0_BABT (47) +#define INT0_HI_FEC0_BABR (48) +#define INT0_HI_FEC1_TXF (49) +#define INT0_HI_FEC1_TXB (50) +#define INT0_HI_FEC1_UN (51) +#define INT0_HI_FEC1_RL (52) +#define INT0_HI_FEC1_RXF (53) +#define INT0_HI_FEC1_RXB (54) +#define INT0_HI_FEC1_MII (55) +#define INT0_HI_FEC1_LC (56) +#define INT0_HI_FEC1_HBERR (57) +#define INT0_HI_FEC1_GRA (58) +#define INT0_HI_FEC1_EBERR (59) +#define INT0_HI_FEC1_BABT (60) +#define INT0_HI_FEC1_BABR (61) +#define INT0_HI_SCM_CFEI (62) + +/* 0 - 24 reserved */ +#define INT1_LO_EPORT1_FLAG0 (25) +#define INT1_LO_EPORT1_FLAG1 (26) +#define INT1_LO_EPORT1_FLAG2 (27) +#define INT1_LO_EPORT1_FLAG3 (28) +#define INT1_LO_EPORT1_FLAG4 (29) +#define INT1_LO_EPORT1_FLAG5 (30) +#define INT1_LO_EPORT1_FLAG6 (31) +#define INT1_LO_EPORT1_FLAG7 (32) +#define INT1_HI_DSPI_EOQF (33) +#define INT1_HI_DSPI_TFFF (34) +#define INT1_HI_DSPI_TCF (35) +#define INT1_HI_DSPI_TFUF (36) +#define INT1_HI_DSPI_RFDF (37) +#define INT1_HI_DSPI_RFOF (38) +#define INT1_HI_DSPI_RFOF_TFUF (39) +#define INT1_HI_RNG_EI (40) +#define INT1_HI_PLL_LOCF (41) +#define INT1_HI_PLL_LOLF (42) +#define INT1_HI_PIT0 (43) +#define INT1_HI_PIT1 (44) +#define INT1_HI_PIT2 (45) +#define INT1_HI_PIT3 (46) +#define INT1_HI_USBOTG_STS (47) +#define INT1_HI_USBHOST_STS (48) +#define INT1_HI_SSI (49) +/* 50 - 51 reserved */ +#define INT1_HI_RTC (52) +#define INT1_HI_CCM_USBSTAT (53) +#define INT1_HI_CODEC_OR (54) +#define INT1_HI_CODEC_RF_TE (55) +#define INT1_HI_CODEC_ROE (56) +#define INT1_HI_CODEC_TUE (57) +/* 58 reserved */ +#define INT1_HI_SIM1_DATA (59) +#define INT1_HI_SIM1_GENERAL (60) +/* 61 - 62 reserved */ +#define INT1_HI_SDHC (63) + +/* *** Reset Controller Module (RCM) *** */ +#define RCM_RCR_SOFTRST (0x80) +#define RCM_RCR_FRCRSTOUT (0x40) + +#define RCM_RSR_SOFT (0x20) +#define RCM_RSR_LOC (0x10) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_LOL (0x01) + +/* *** Chip Configuration Module (CCM) *** */ +#define CCM_CCR_CSC (0x0020) +#define CCM_CCR_BOOTPS (0x0010) +#define CCM_CCR_LOAD (0x0008) +#define CCM_CCR_OSC_MODE (0x0004) +#define CCM_CCR_SDR_MODE (0x0002) +#define CCM_CCR_RESERVED (0x0001) + +#define CCM_RCON_SDR_32BIT_UNIFIED (0x0012) +#define CCM_RCON_DDR_8BIT_SPLIT (0x0010) +#define CCM_RCON_SDR_16BIT_UNIFIED (0x0002) +#define CCM_RCON_DDR_16BIT_SPLIT (0x0000) + +#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) + +#define CCM_MISCCR_FECM (0x8000) +#define CCM_MISCCR_CDCSRC (0x4000) +#define CCM_MISCCR_PLL_LOCK (0x2000) +#define CCM_MISCCR_LIMP (0x1000) +#define CCM_MISCCR_BME (0x8000) +#define CCM_MISCCR_BMT_UNMASK (0xF8FF) +#define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) +#define CCM_MISCCR_BMT_512 (0x0700) +#define CCM_MISCCR_BMT_1024 (0x0600) +#define CCM_MISCCR_BMT_2048 (0x0500) +#define CCM_MISCCR_BMT_4096 (0x0400) +#define CCM_MISCCR_BMT_8192 (0x0300) +#define CCM_MISCCR_BMT_16384 (0x0200) +#define CCM_MISCCR_BMT_32768 (0x0100) +#define CCM_MISCCR_BMT_65536 (0x0000) +#define CCM_MISCCR_TIM_DMA (0x0020) +#define CCM_MISCCR_SSI_SRC (0x0010) +#define CCM_MISCCR_USBH_OC (0x0008) +#define CCM_MISCCR_USBO_OC (0x0004) +#define CCM_MISCCR_USB_PUE (0x0002) +#define CCM_MISCCR_USB_SRC (0x0001) + +#define CCM_CDR_LPDIV(x) (((x) & 0x0F) << 8) +#define CCM_CDR_SSIDIV(x) ((x) & 0xFF) + +#define CCM_UOCSR_DPPD (0x2000) +#define CCM_UOCSR_DMPD (0x1000) +#define CCM_UOCSR_DRV_VBUS (0x0800) +#define CCM_UOCSR_CRG_VBUS (0x0400) +#define CCM_UOCSR_DCR_VBUS (0x0200) +#define CCM_UOCSR_DPPU (0x0100) +#define CCM_UOCSR_AVLD (0x0080) +#define CCM_UOCSR_BVLD (0x0040) +#define CCM_UOCSR_VVLD (0x0020) +#define CCM_UOCSR_SEND (0x0010) +#define CCM_UOCSR_PWRFLT (0x0008) +#define CCM_UOCSR_WKUP (0x0004) +#define CCM_UOCSR_UOMIE (0x0002) +#define CCM_UOCSR_XPDE (0x0001) + +#define CCM_UHCSR_PORTIND(x) (((x) & 0x0003) << 14) +#define CCM_UHCSR_DRV_VBUS (0x0010) +#define CCM_UHCSR_PWRFLT (0x0008) +#define CCM_UHCSR_WKUP (0x0004) +#define CCM_UHCSR_UHMIE (0x0002) +#define CCM_UHCSR_XPDE (0x0001) + +#define CCM_CODCR_BGREN (0x8000) +#define CCM_CODCR_REGEN (0x0080) + +#define CCM_MISC2_IGNLL (0x0008) +#define CCM_MISC2_DPS (0x0001) + +/* *** General Purpose I/O (GPIO) *** */ +#define GPIO_PDR_FBCTL ((x) & 0x0F) +#define GPIO_PDR_BE ((x) & 0x0F) +#define GPIO_PDR_CS32 (((x) & 0x03) << 4) +#define GPIO_PDR_CS10 (((x) & 0x03) << 4) +#define GPIO_PDR_DSPI ((x) & 0x7F) +#define GPIO_PDR_FEC0 ((x) & 0x7F) +#define GPIO_PDR_FECI2C ((x) & 0x3F) +#define GPIO_PDR_SIMP1 ((x) & 0x1F) +#define GPIO_PDR_SIMP0 ((x) & 0x1F) +#define GPIO_PDR_TIMER ((x) & 0x0F) +#define GPIO_PDR_UART ((x) & 0x3F) +#define GPIO_PDR_DEBUG (0x01) +#define GPIO_PDR_SDHC ((x) & 0x3F) +#define GPIO_PDR_SSI ((x) & 0x1F) + +#define GPIO_PAR_FBCTL_OE (0x80) +#define GPIO_PAR_FBCTL_TA (0x40) +#define GPIO_PAR_FBCTL_RWB (0x20) +#define GPIO_PAR_FBCTL_TS (0x18) + +#define GPIO_PAR_BE3 (0x40) +#define GPIO_PAR_BE2 (0x10) +#define GPIO_PAR_BE1 (0x04) +#define GPIO_PAR_BE0 (0x01) + +#define GPIO_PAR_CS5 (0x40) +#define GPIO_PAR_CS4 (0x10) +#define GPIO_PAR_CS1_UNMASK (0xF3) +#define GPIO_PAR_CS1_CS1 (0x0C) +#define GPIO_PAR_CS1_SDCS1 (0x08) +#define GPIO_PAR_CS0_UNMASK (0xFC) +#define GPIO_PAR_CS0_CS0 (0x03) +#define GPIO_PAR_CS0_CS4 (0x02) + +#define GPIO_PAR_DSPIH_SIN_UNMASK (0x3F) +#define GPIO_PAR_DSPIH_SIN (0xC0) +#define GPIO_PAR_DSPIH_SIN_U2RXD (0x80) +#define GPIO_PAR_DSPIH_SOUT_UNMASK (0xCF) +#define GPIO_PAR_DSPIH_SOUT (0x30) +#define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20) +#define GPIO_PAR_DSPIH_SCK_UNMASK (0xF3) +#define GPIO_PAR_DSPIH_SCK (0x0C) +#define GPIO_PAR_DSPIH_SCK_U2CTS (0x08) +#define GPIO_PAR_DSPIH_PCS0_UNMASK (0xFC) +#define GPIO_PAR_DSPIH_PCS0 (0x03) +#define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02) + +#define GPIO_PAR_DSPIL_PCS1_UNMASK (0x3F) +#define GPIO_PAR_DSPIL_PCS1 (0xC0) +#define GPIO_PAR_DSPIL_PCS2_UNMASK (0xCF) +#define GPIO_PAR_DSPIL_PCS2 (0x30) +#define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20) +#define GPIO_PAR_DSPIL_PCS3_UNMASK (0xF3) +#define GPIO_PAR_DSPIL_PCS3 (0x0C) +#define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08) + +#define GPIO_PAR_FEC1_7W_FEC (0x40) +#define GPIO_PAR_FEC1_RMII_FEC (0x10) +#define GPIO_PAR_FEC0_7W_FEC (0x04) +#define GPIO_PAR_FEC0_RMII_FEC (0x01) + +/* GPIO_PAR_FECI2C */ +#define GPIO_PAR_FECI2C_RMII0_UNMASK (0x3F) +#define GPIO_PAR_FECI2C_MDC0 (0x80) +#define GPIO_PAR_FECI2C_MDIO0 (0x40) +#define GPIO_PAR_FECI2C_RMII1_UNMASK (0xCF) +#define GPIO_PAR_FECI2C_MDC1 (0x20) +#define GPIO_PAR_FECI2C_MDIO1 (0x10) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xF3) +#define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2) +#define GPIO_PAR_FECI2C_SDA_SDA (0x0C) +#define GPIO_PAR_FECI2C_SDA_U2TXD (0x08) +#define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFC) +#define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03) +#define GPIO_PAR_FECI2C_SCL_SCL (0x03) +#define GPIO_PAR_FECI2C_SCL_U2RXD (0x02) +#define GPIO_PAR_FECI2C_SCL_MDC1 (0x01) + +#define GPIO_PAR_IRQ0H_IRQ07_UNMASK (0x3F) +#define GPIO_PAR_IRQ0H_IRQ06_UNMASK (0xCF) +#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10) +#define GPIO_PAR_IRQ0H_IRQ04_UNMASK (0xFC) +#define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02) + +#define GPIO_PAR_IRQ0L_IRQ01_UNMASK (0xF3) +#define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08) + +#define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40) +#define GPIO_PAR_IRQ1H_IRQ16_DDATA2 (0x10) +#define GPIO_PAR_IRQ1H_IRQ15_DDATA1 (0x04) +#define GPIO_PAR_IRQ1H_IRQ14_DDATA0 (0x01) + +#define GPIO_PAR_IRQ1L_IRQ13_PST3 (0x40) +#define GPIO_PAR_IRQ1L_IRQ12_PST2 (0x10) +#define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04) +#define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01) + +#define GPIO_PAR_SIMP1H_DATA1_UNMASK (0x3F) +#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0) +#define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80) +#define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40) +#define GPIO_PAR_SIMP1H_VEN1_UNMASK (0xCF) +#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30) +#define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20) +#define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10) +#define GPIO_PAR_SIMP1H_RST1_UNMASK (0xF3) +#define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C) +#define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08) +#define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04) +#define GPIO_PAR_SIMP1H_PD1_UNMASK (0xFC) +#define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03) +#define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02) +#define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01) + +#define GPIO_PAR_SIMP1L_CLK_UNMASK (0x3F) +#define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0) +#define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80) + +#define GPIO_PAR_SIMP0_DATA0 (0x10) +#define GPIO_PAR_SIMP0_VEN0 (0x08) +#define GPIO_PAR_SIMP0_RST0 (0x04) +#define GPIO_PAR_SIMP0_PD0 (0x02) +#define GPIO_PAR_SIMP0_CLK0 (0x01) + +#define GPIO_PAR_TIN3(x) (((x) & 0x03) << 6) +#define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4) +#define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2) +#define GPIO_PAR_TIN0(x) ((x) & 0x03) +#define GPIO_PAR_TIN3_UNMASK (0x3F) +#define GPIO_PAR_TIN3_TIN3 (0xC0) +#define GPIO_PAR_TIN3_TOUT3 (0x80) +#define GPIO_PAR_TIN3_IRQ03 (0x40) +#define GPIO_PAR_TIN2_UNMASK (0xCF) +#define GPIO_PAR_TIN2_TIN2 (0x30) +#define GPIO_PAR_TIN2_TOUT2 (0x20) +#define GPIO_PAR_TIN2_IRQ02 (0x10) +#define GPIO_PAR_TIN1_UNMASK (0xF3) +#define GPIO_PAR_TIN1_TIN1 (0x0C) +#define GPIO_PAR_TIN1_TOUT1 (0x08) +#define GPIO_PAR_TIN1_DACK1 (0x04) +#define GPIO_PAR_TIN0_UNMASK (0xFC) +#define GPIO_PAR_TIN0_TIN0 (0x03) +#define GPIO_PAR_TIN0_TOUT0 (0x02) +#define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01) + +#define GPIO_PAR_UART_U2TXD (0x80) +#define GPIO_PAR_UART_U2RXD (0x40) +#define GPIO_PAR_UART_U0TXD (0x20) +#define GPIO_PAR_UART_U0RXD (0x10) +#define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2) +#define GPIO_PAR_UART_CTS0(x) ((x) & 0x03) +#define GPIO_PAR_UART_RTS0_UNMASK (0xF3) +#define GPIO_PAR_UART_RTS0_U0RTS (0x0C) +#define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08) +#define GPIO_PAR_UART_CTS0_UNMASK (0xFC) +#define GPIO_PAR_UART_CTS0_U0CTS (0x03) +#define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02) +#define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01) + +#define GPIO_PAR_DEBUG_ALLPST (0x80) + +#define GPIO_PAR_SDHC_DATA3 (0x20) +#define GPIO_PAR_SDHC_DATA2 (0x10) +#define GPIO_PAR_SDHC_DATA1 (0x08) +#define GPIO_PAR_SDHC_DATA0 (0x04) +#define GPIO_PAR_SDHC_CMD (0x02) +#define GPIO_PAR_SDHC_CLK (0x01) + +#define GPIO_PAR_SSIH_RXD(x) (((x) & 0x03) << 6) +#define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4) +#define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2) +#define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03) +#define GPIO_PAR_SSIH_RXD_UNMASK (0x3F) +#define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0) +#define GPIO_PAR_SSIH_RXD_U1RXD (0x40) +#define GPIO_PAR_SSIH_TXD_UNMASK (0xCF) +#define GPIO_PAR_SSIH_TXD_SSIRXD (0x30) +#define GPIO_PAR_SSIH_TXD_U1TXD (0x10) +#define GPIO_PAR_SSIH_FS_UNMASK (0xF3) +#define GPIO_PAR_SSIH_FS_SSIFS (0x0C) +#define GPIO_PAR_SSIH_FS_U1RTS (0x04) +#define GPIO_PAR_SSIH_MCLK_UNMASK (0xFC) +#define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03) +#define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01) + +#define GPIO_PAR_SSIL_UNMASK (0x3F) +#define GPIO_PAR_SSIL_BCLK (0xC0) +#define GPIO_PAR_SSIL_U1CTS (0x40) + +#define GPIO_MSCR_MSCR1(x) (((x) & 0x07) << 5) +#define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5) +#define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5) +#define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5) +#define GPIO_MSCR_MSCRn_UNMASK (0x1F) +#define GPIO_MSCR_MSCRn_SDR (0xE0) +#define GPIO_MSCR_MSCRn_25VDDR (0x60) +#define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20) +#define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00) + +#define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2) +#define GPIO_MSCR_MSCR5_UNMASK (0xE3) +#define GPIO_MSCR_MSCR5_SDR (0x1C) +#define GPIO_MSCR_MSCR5_25VDDR (0x0C) +#define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04) +#define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00) + +#define GPIO_SRCR_DSPI_UNMASK (0xFC) +#define GPIO_SRCR_DSPI(x) ((x) & 0x03) +#define GPIO_SRCR_I2C_UNMASK (0xFC) +#define GPIO_SRCR_I2C(x) ((x) & 0x03) +#define GPIO_SRCR_IRQ_IRQ0_UNMASK (0xF3) +#define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2) +#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK (0xFC) +#define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03) +#define GPIO_SRCR_SIM_SIMP0_UNMASK (0xF3) +#define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2) +#define GPIO_SRCR_SIM_SIMP1_UNMASK (0xFC) +#define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03) +#define GPIO_SRCR_TIMER_UNMASK (0xFC) +#define GPIO_SRCR_TIMER(x) ((x) & 0x03) +#define GPIO_SRCR_UART2_UNMASK (0xF3) +#define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2) +#define GPIO_SRCR_UART0_UNMASK (0xFC) +#define GPIO_SRCR_UART0(x) ((x) & 0x03) +#define GPIO_SRCR_SDHC_UNMASK (0xFC) +#define GPIO_SRCR_SDHC(x) ((x) & 0x03) +#define GPIO_SRCR_SSI_UNMASK (0xFC) +#define GPIO_SRCR_SSI(x) ((x) & 0x03) + +#define SRCR_HIGHEST (0x03) +#define SRCR_HIGH (0x02) +#define SRCR_LOW (0x01) +#define SRCR_LOWEST (0x00) + +#define GPIO_DSCR_FEC_RMIICLK_UNMASK (0xCF) +#define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4) +#define GPIO_DSCR_FEC_RMII0_UNMASK (0xF3) +#define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2) +#define GPIO_DSCR_FEC_RMII1_UNMASK (0xFC) +#define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03) + +#define DSCR_50PF (0x03) +#define DSCR_30PF (0x02) +#define DSCR_20PF (0x01) +#define DSCR_10PF (0x00) + +#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN (0x80) +#define GPIO_PCRH_SIM_VEN1_PULLUP_EN (0x40) +#define GPIO_PCRH_SIM_VEN1_PULLUP (0x20) +#define GPIO_PCRH_SIM_DATA1_PULLUP_EN (0x10) +#define GPIO_PCRH_SIM_DATA1_PULLUP (0x08) +#define GPIO_PCRH_SSI_PULLUP_EN (0x02) +#define GPIO_PCRH_SSI_PULLUP (0x01) + +#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN (0x80) +#define GPIO_PCRL_SDHC_DATA3_PULLUP (0x40) +#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN (0x20) +#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN (0x10) +#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN (0x08) +#define GPIO_PCRL_SDHC_CMD_PULLUP_EN (0x04) + +/* *** Phase Locked Loop (PLL) *** */ +#define PLL_PCR_LOC_IRQ (0x00040000) +#define PLL_PCR_LOC_RE (0x00020000) +#define PLL_PCR_LOC_EN (0x00010000) +#define PLL_PCR_LOL_IRQ (0x00004000) +#define PLL_PCR_LOL_RE (0x00002000) +#define PLL_PCR_LOL_EN (0x00001000) +#define PLL_PCR_REFDIV_UNMASK (0xFFFFF8FF) +#define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8) +#define PLL_PCR_FBDIV_UNMASK (0xFFFFFFC0) +#define PLL_PCR_FBDIV(x) ((x) & 0x3F) + +#define PLL_PDR_OUTDIV4_UNMASK (0x0FFF) +#define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12) +#define PLL_PDR_OUTDIV3_UNMASK (0xF0FF) +#define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8) +#define PLL_PDR_OUTDIV2_UNMASK (0xFF0F) +#define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4) +#define PLL_PDR_OUTDIV1_UNMASK (0xFFF0) +#define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F) +#define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x) +#define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x) +#define PLL_PDR_FB(x) PLL_PDR_OUTDIV2(x) +#define PLL_PDR_CPU(x) PLL_PDR_OUTDIV1(x) + +#define PLL_PSR_LOCF (0x00000200) +#define PLL_PSR_LOC (0x00000100) +#define PLL_PSR_LOLF (0x00000040) +#define PLL_PSR_LOCKS (0x00000020) +#define PLL_PSR_LOCK (0x00000010) +#define PLL_PSR_MODE(x) ((x) & 0x07) + +/* *** Real Time Clock *** */ +#define RTC_OCEN_OSCBYP (0x00000010) +#define RTC_OCEN_CLKEN (0x00000008) + +/* SDRAM */ +#define SDRAMC_SDCR_CKE (0x40000000) +#define SDRAMC_SDCR_REF (0x10000000) + +#endif /* m5301x_h */ diff --git a/include/asm-m68k/m5329.h b/arch/m68k/include/asm/m5329.h similarity index 100% rename from include/asm-m68k/m5329.h rename to arch/m68k/include/asm/m5329.h diff --git a/arch/m68k/include/asm/m5445x.h b/arch/m68k/include/asm/m5445x.h new file mode 100644 index 0000000000..dfddde62ad --- /dev/null +++ b/arch/m68k/include/asm/m5445x.h @@ -0,0 +1,904 @@ +/* + * MCF5445x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCF5445X__ +#define __MCF5445X__ + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC0_TXF (36) +#define INT0_HI_FEC0_TXB (37) +#define INT0_HI_FEC0_UN (38) +#define INT0_HI_FEC0_RL (39) +#define INT0_HI_FEC0_RXF (40) +#define INT0_HI_FEC0_RXB (41) +#define INT0_HI_FEC0_MII (42) +#define INT0_HI_FEC0_LC (43) +#define INT0_HI_FEC0_HBERR (44) +#define INT0_HI_FEC0_GRA (45) +#define INT0_HI_FEC0_EBERR (46) +#define INT0_HI_FEC0_BABT (47) +#define INT0_HI_FEC0_BABR (48) +#define INT0_HI_FEC1_TXF (49) +#define INT0_HI_FEC1_TXB (50) +#define INT0_HI_FEC1_UN (51) +#define INT0_HI_FEC1_RL (52) +#define INT0_HI_FEC1_RXF (53) +#define INT0_HI_FEC1_RXB (54) +#define INT0_HI_FEC1_MII (55) +#define INT0_HI_FEC1_LC (56) +#define INT0_HI_FEC1_HBERR (57) +#define INT0_HI_FEC1_GRA (58) +#define INT0_HI_FEC1_EBERR (59) +#define INT0_HI_FEC1_BABT (60) +#define INT0_HI_FEC1_BABR (61) +#define INT0_HI_SCMIR (62) +#define INT0_HI_RTC_ISR (63) + +#define INT1_HI_DSPI_EOQF (33) +#define INT1_HI_DSPI_TFFF (34) +#define INT1_HI_DSPI_TCF (35) +#define INT1_HI_DSPI_TFUF (36) +#define INT1_HI_DSPI_RFDF (37) +#define INT1_HI_DSPI_RFOF (38) +#define INT1_HI_DSPI_RFOF_TFUF (39) +#define INT1_HI_RNG_EI (40) +#define INT1_HI_PIT0_PIF (43) +#define INT1_HI_PIT1_PIF (44) +#define INT1_HI_PIT2_PIF (45) +#define INT1_HI_PIT3_PIF (46) +#define INT1_HI_USBOTG_USBSTS (47) +#define INT1_HI_SSI_ISR (49) +#define INT1_HI_CCM_UOCSR (53) +#define INT1_HI_ATA_ISR (54) +#define INT1_HI_PCI_SCR (55) +#define INT1_HI_PCI_ASR (56) +#define INT1_HI_PLL_LOCKS (57) + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ + +/* Bit definitions and macros for WCR */ +#define WTM_WCR_EN (0x0001) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_WAIT (0x0008) + +/********************************************************************* +* Serial Boot Facility (SBF) +*********************************************************************/ + +/* Bit definitions and macros for SBFCR */ +#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ +#define SBF_SBFCR_FR (0x0010) /* Fast read */ + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +/* Bit definitions and macros for RCR */ +#define RCM_RCR_FRCRSTOUT (0x40) +#define RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for RSR */ +#define RCM_RSR_LOL (0x01) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_SOFT (0x20) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +/* Bit definitions and macros for CCR_360 */ +#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ +#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ +#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ +#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ +#define CCM_CCR_360_FBCONFIG_MASK (0x00E0) +#define CCM_CCR_360_PLLMULT2_MASK (0x0003) +#define CCM_CCR_360_PLLMULT3_MASK (0x0007) +#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) +#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) +#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) +#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) +#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) +#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) +#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) +#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) +#define CCM_CCR_360_PLLMULT2_12X (0x0000) +#define CCM_CCR_360_PLLMULT2_6X (0x0001) +#define CCM_CCR_360_PLLMULT2_16X (0x0002) +#define CCM_CCR_360_PLLMULT2_8X (0x0003) +#define CCM_CCR_360_PLLMULT3_20X (0x0000) +#define CCM_CCR_360_PLLMULT3_10X (0x0001) +#define CCM_CCR_360_PLLMULT3_24X (0x0002) +#define CCM_CCR_360_PLLMULT3_18X (0x0003) +#define CCM_CCR_360_PLLMULT3_12X (0x0004) +#define CCM_CCR_360_PLLMULT3_6X (0x0005) +#define CCM_CCR_360_PLLMULT3_16X (0x0006) +#define CCM_CCR_360_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for CCR_256 */ +#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ +#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ +#define CCM_CCR_256_FBCONFIG_MASK (0x00E0) +#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) +#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) +#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) +#define CCM_CCR_256_FBCONFIG_M_32 (0x0080) +#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) +#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) +#define CCM_CCR_256_PLLMULT3_MASK (0x0007) +#define CCM_CCR_256_PLLMULT3_20X (0x0000) +#define CCM_CCR_256_PLLMULT3_10X (0x0001) +#define CCM_CCR_256_PLLMULT3_24X (0x0002) +#define CCM_CCR_256_PLLMULT3_18X (0x0003) +#define CCM_CCR_256_PLLMULT3_12X (0x0004) +#define CCM_CCR_256_PLLMULT3_6X (0x0005) +#define CCM_CCR_256_PLLMULT3_16X (0x0006) +#define CCM_CCR_256_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for RCON_360 */ +#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ +#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for RCON_256 */ +#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ +#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for CIR */ +#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ +#define CCM_CIR_PIN_MASK (0xFFC0) +#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN_MCF54450 (0x4F<<6) +#define CCM_CIR_PIN_MCF54451 (0x4D<<6) +#define CCM_CIR_PIN_MCF54452 (0x4B<<6) +#define CCM_CIR_PIN_MCF54453 (0x49<<6) +#define CCM_CIR_PIN_MCF54454 (0x4A<<6) +#define CCM_CIR_PIN_MCF54455 (0x48<<6) + +/* Bit definitions and macros for MISCCR */ +#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ +#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ +#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ +#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ +#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ +#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ +#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ +#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ +#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ +#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ +#define CCM_MISCCR_BMT_65536 (0) +#define CCM_MISCCR_BMT_32768 (1) +#define CCM_MISCCR_BMT_16384 (2) +#define CCM_MISCCR_BMT_8192 (3) +#define CCM_MISCCR_BMT_4096 (4) +#define CCM_MISCCR_BMT_2048 (5) +#define CCM_MISCCR_BMT_1024 (6) +#define CCM_MISCCR_BMT_512 (7) +#define CCM_MISCCR_SSIPUS_UP (1) +#define CCM_MISCCR_SSIPUS_DOWN (0) +#define CCM_MISCCR_TIMDMA_TIM (1) +#define CCM_MISCCR_TIMDMA_SSI (0) +#define CCM_MISCCR_SSISRC_CLKIN (0) +#define CCM_MISCCR_SSISRC_PLL (1) +#define CCM_MISCCR_USBOC_ACTHI (0) +#define CCM_MISCCR_USBOV_ACTLO (1) +#define CCM_MISCCR_USBSRC_CLKIN (0) +#define CCM_MISCCR_USBSRC_PLL (1) + +/* Bit definitions and macros for CDR */ +#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ + +/* Bit definitions and macros for UOCSR */ +#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ +#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ +#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ +#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ +#define CCM_UOCSR_SEND (0x0010) /* Session end */ +#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ +#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ +#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ +#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ +#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ +#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ +#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ +#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ + +/* Bit definitions and macros for PAR_FEC */ +#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) +#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) +#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F) +#define GPIO_PAR_FEC_FEC1_MII (0x70) +#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) +#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) +#define GPIO_PAR_FEC_FEC1_ATA (0x10) +#define GPIO_PAR_FEC_FEC1_GPIO (0x00) +#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8) +#define GPIO_PAR_FEC_FEC0_MII (0x07) +#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) +#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) +#define GPIO_PAR_FEC_FEC0_ULPI (0x01) +#define GPIO_PAR_FEC_FEC0_GPIO (0x00) + +/* Bit definitions and macros for PAR_DMA */ +#define GPIO_PAR_DMA_DREQ0 (0x01) +#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) +#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) +#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) +#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F) +#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) +#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) +#define GPIO_PAR_DMA_DACK1_GPIO (0x00) +#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF) +#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) +#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) +#define GPIO_PAR_DMA_DREQ1_GPIO (0x00) +#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) +#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) +#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) +#define GPIO_PAR_DMA_DACK0_GPIO (0x00) +#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) +#define GPIO_PAR_DMA_DREQ0_GPIO (0x00) + +/* Bit definitions and macros for PAR_FBCTL */ +#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) +#define GPIO_PAR_FBCTL_RW (0x20) +#define GPIO_PAR_FBCTL_TA (0x40) +#define GPIO_PAR_FBCTL_OE (0x80) +#define GPIO_PAR_FBCTL_OE_OE (0x80) +#define GPIO_PAR_FBCTL_OE_GPIO (0x00) +#define GPIO_PAR_FBCTL_TA_TA (0x40) +#define GPIO_PAR_FBCTL_TA_GPIO (0x00) +#define GPIO_PAR_FBCTL_RW_RW (0x20) +#define GPIO_PAR_FBCTL_RW_GPIO (0x00) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) +#define GPIO_PAR_FBCTL_TS_TS (0x18) +#define GPIO_PAR_FBCTL_TS_ALE (0x10) +#define GPIO_PAR_FBCTL_TS_TBST (0x08) +#define GPIO_PAR_FBCTL_TS_GPIO (0x80) + +/* Bit definitions and macros for PAR_DSPI */ +#define GPIO_PAR_DSPI_SCK (0x01) +#define GPIO_PAR_DSPI_SOUT (0x02) +#define GPIO_PAR_DSPI_SIN (0x04) +#define GPIO_PAR_DSPI_PCS0 (0x08) +#define GPIO_PAR_DSPI_PCS1 (0x10) +#define GPIO_PAR_DSPI_PCS2 (0x20) +#define GPIO_PAR_DSPI_PCS5 (0x40) +#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) +#define GPIO_PAR_DSPI_PCS5_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) +#define GPIO_PAR_DSPI_PCS2_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) +#define GPIO_PAR_DSPI_PCS1_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) +#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) +#define GPIO_PAR_DSPI_SIN_SIN (0x04) +#define GPIO_PAR_DSPI_SIN_GPIO (0x00) +#define GPIO_PAR_DSPI_SOUT_SOUT (0x02) +#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) +#define GPIO_PAR_DSPI_SCK_SCK (0x01) +#define GPIO_PAR_DSPI_SCK_GPIO (0x00) + +/* Bit definitions and macros for PAR_BE */ +#define GPIO_PAR_BE_BS0 (0x01) +#define GPIO_PAR_BE_BS1 (0x04) +#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) +#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) +#define GPIO_PAR_BE_BE3_UNMASK (0x3F) +#define GPIO_PAR_BE_BE3_BE3 (0xC0) +#define GPIO_PAR_BE_BE3_TSIZ1 (0x80) +#define GPIO_PAR_BE_BE3_GPIO (0x00) +#define GPIO_PAR_BE_BE2_UNMASK (0xCF) +#define GPIO_PAR_BE_BE2_BE2 (0x30) +#define GPIO_PAR_BE_BE2_TSIZ0 (0x20) +#define GPIO_PAR_BE_BE2_GPIO (0x00) +#define GPIO_PAR_BE_BE1_BE1 (0x04) +#define GPIO_PAR_BE_BE1_GPIO (0x00) +#define GPIO_PAR_BE_BE0_BE0 (0x01) +#define GPIO_PAR_BE_BE0_GPIO (0x00) + +/* Bit definitions and macros for PAR_CS */ +#define GPIO_PAR_CS_CS1 (0x02) +#define GPIO_PAR_CS_CS2 (0x04) +#define GPIO_PAR_CS_CS3 (0x08) +#define GPIO_PAR_CS_CS3_CS3 (0x08) +#define GPIO_PAR_CS_CS3_GPIO (0x00) +#define GPIO_PAR_CS_CS2_CS2 (0x04) +#define GPIO_PAR_CS_CS2_GPIO (0x00) +#define GPIO_PAR_CS_CS1_CS1 (0x02) +#define GPIO_PAR_CS_CS1_GPIO (0x00) + +/* Bit definitions and macros for PAR_TIMER */ +#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) +#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) +#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) +#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) +#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) +#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) +#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) +#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) +#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) +#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) +#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) +#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) +#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) +#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) + +/* Bit definitions and macros for PAR_USB */ +#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) +#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) +#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3) +#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) +#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) +#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) +#define GPIO_PAR_USB_VBUSEN_GPIO (0x00) +#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC) +#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) +#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) +#define GPIO_PAR_USB_VBUSOC_GPIO (0x00) + +/* Bit definitions and macros for PAR_UART */ +#define GPIO_PAR_UART_U0TXD (0x01) +#define GPIO_PAR_UART_U0RXD (0x02) +#define GPIO_PAR_UART_U0RTS (0x04) +#define GPIO_PAR_UART_U0CTS (0x08) +#define GPIO_PAR_UART_U1TXD (0x10) +#define GPIO_PAR_UART_U1RXD (0x20) +#define GPIO_PAR_UART_U1RTS (0x40) +#define GPIO_PAR_UART_U1CTS (0x80) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x80) +#define GPIO_PAR_UART_U1CTS_GPIO (0x00) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x40) +#define GPIO_PAR_UART_U1RTS_GPIO (0x00) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x20) +#define GPIO_PAR_UART_U1RXD_GPIO (0x00) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x10) +#define GPIO_PAR_UART_U1TXD_GPIO (0x00) +#define GPIO_PAR_UART_U0CTS_U0CTS (0x08) +#define GPIO_PAR_UART_U0CTS_GPIO (0x00) +#define GPIO_PAR_UART_U0RTS_U0RTS (0x04) +#define GPIO_PAR_UART_U0RTS_GPIO (0x00) +#define GPIO_PAR_UART_U0RXD_U0RXD (0x02) +#define GPIO_PAR_UART_U0RXD_GPIO (0x00) +#define GPIO_PAR_UART_U0TXD_U0TXD (0x01) +#define GPIO_PAR_UART_U0TXD_GPIO (0x00) + +/* Bit definitions and macros for PAR_FECI2C */ +#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) +#define GPIO_PAR_FECI2C_MDIO0 (0x0010) +#define GPIO_PAR_FECI2C_MDC0 (0x0040) +#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) +#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) +#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF) +#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) +#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) +#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF) +#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) +#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) +#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) +#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) +#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3) +#define GPIO_PAR_FECI2C_SCL_SCL (0x000C) +#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) +#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC) +#define GPIO_PAR_FECI2C_SDA_SDA (0x0003) +#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) +#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) + +/* Bit definitions and macros for PAR_SSI */ +#define GPIO_PAR_SSI_MCLK (0x0001) +#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) +#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) +#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) +#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) +#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF) +#define GPIO_PAR_SSI_BCLK_BCLK (0x0300) +#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) +#define GPIO_PAR_SSI_BCLK_GPIO (0x0000) +#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F) +#define GPIO_PAR_SSI_FS_FS (0x00C0) +#define GPIO_PAR_SSI_FS_U1RTS (0x0080) +#define GPIO_PAR_SSI_FS_GPIO (0x0000) +#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF) +#define GPIO_PAR_SSI_SRXD_SRXD (0x0030) +#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) +#define GPIO_PAR_SSI_SRXD_GPIO (0x0000) +#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3) +#define GPIO_PAR_SSI_STXD_STXD (0x000C) +#define GPIO_PAR_SSI_STXD_U1TXD (0x0008) +#define GPIO_PAR_SSI_STXD_GPIO (0x0000) +#define GPIO_PAR_SSI_MCLK_MCLK (0x0001) +#define GPIO_PAR_SSI_MCLK_GPIO (0x0000) + +/* Bit definitions and macros for PAR_ATA */ +#define GPIO_PAR_ATA_IORDY (0x0001) +#define GPIO_PAR_ATA_DMARQ (0x0002) +#define GPIO_PAR_ATA_RESET (0x0004) +#define GPIO_PAR_ATA_DA0 (0x0020) +#define GPIO_PAR_ATA_DA1 (0x0040) +#define GPIO_PAR_ATA_DA2 (0x0080) +#define GPIO_PAR_ATA_CS0 (0x0100) +#define GPIO_PAR_ATA_CS1 (0x0200) +#define GPIO_PAR_ATA_BUFEN (0x0400) +#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) +#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) +#define GPIO_PAR_ATA_CS1_CS1 (0x0200) +#define GPIO_PAR_ATA_CS1_GPIO (0x0000) +#define GPIO_PAR_ATA_CS0_CS0 (0x0100) +#define GPIO_PAR_ATA_CS0_GPIO (0x0000) +#define GPIO_PAR_ATA_DA2_DA2 (0x0080) +#define GPIO_PAR_ATA_DA2_GPIO (0x0000) +#define GPIO_PAR_ATA_DA1_DA1 (0x0040) +#define GPIO_PAR_ATA_DA1_GPIO (0x0000) +#define GPIO_PAR_ATA_DA0_DA0 (0x0020) +#define GPIO_PAR_ATA_DA0_GPIO (0x0000) +#define GPIO_PAR_ATA_RESET_RESET (0x0004) +#define GPIO_PAR_ATA_RESET_GPIO (0x0000) +#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) +#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) +#define GPIO_PAR_ATA_IORDY_IORDY (0x0001) +#define GPIO_PAR_ATA_IORDY_GPIO (0x0000) + +/* Bit definitions and macros for PAR_IRQ */ +#define GPIO_PAR_IRQ_IRQ1 (0x02) +#define GPIO_PAR_IRQ_IRQ4 (0x10) +#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) +#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) +#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) +#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) + +/* Bit definitions and macros for PAR_PCI */ +#define GPIO_PAR_PCI_REQ0 (0x0001) +#define GPIO_PAR_PCI_REQ1 (0x0004) +#define GPIO_PAR_PCI_REQ2 (0x0010) +#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) +#define GPIO_PAR_PCI_GNT0 (0x0100) +#define GPIO_PAR_PCI_GNT1 (0x0400) +#define GPIO_PAR_PCI_GNT2 (0x1000) +#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) +#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF) +#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) +#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) +#define GPIO_PAR_PCI_GNT3_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) +#define GPIO_PAR_PCI_GNT2_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) +#define GPIO_PAR_PCI_GNT1_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) +#define GPIO_PAR_PCI_GNT0_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F) +#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) +#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) +#define GPIO_PAR_PCI_REQ3_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) +#define GPIO_PAR_PCI_REQ2_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) +#define GPIO_PAR_PCI_REQ1_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) +#define GPIO_PAR_PCI_REQ0_GPIO (0x0000) + +/* Bit definitions and macros for MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) +#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) +#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) +#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F) +#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) +#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) +#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) +#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF) +#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) +#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) +#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) +#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) +#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) +#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) +#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) +#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) +#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) +#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) + +/* Bit definitions and macros for MSCR_PCI */ +#define GPIO_MSCR_PCI_PCI (0x01) +#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) +#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) + +/* Bit definitions and macros for DSCR_I2C */ +#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) +#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) +#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) +#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) +#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FLEXBUS */ +#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) +#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) +#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) +#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FEC */ +#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) +#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) +#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) +#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) +#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) +#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) +#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) +#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) +#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) +#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_UART */ +#define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) +#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) +#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) +#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) +#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) +#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) +#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) +#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) +#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) +#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DSPI */ +#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) +#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) +#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) +#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) +#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_TIMER */ +#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) +#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) +#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) +#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) +#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_SSI */ +#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) +#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) +#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) +#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) +#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DMA */ +#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) +#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) +#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) +#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) +#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DEBUG */ +#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_RESET */ +#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) +#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) +#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) +#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) +#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_IRQ */ +#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) +#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) +#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) +#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) +#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_USB */ +#define GPIO_DSCR_USB_USB(x) (((x)&0x03)) +#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) +#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) +#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) +#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_ATA */ +#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) +#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) +#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) +#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) +#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +/* Bit definitions and macros for SDMR */ +#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ +#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ +#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ +#define SDRAMC_SDMR_BK_LMR (0x00000000) +#define SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for SDCR */ +#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ +#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ +#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ +#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ +#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ +#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ +#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ +#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ +#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ +#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ +#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ +#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) + +/* Bit definitions and macros for SDCFG1 */ +#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ +#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ +#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ +#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ + +/* Bit definitions and macros for SDCFG2 */ +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ +#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ +#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ +#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ + +/* Bit definitions and macros for SDCS group */ +#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ +#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +/* Bit definitions and macros for PCR */ +#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ +#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ +#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ +#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ +#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ +#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ +#define PLL_PCR_PFDR_MASK (0x000F0000) +#define PLL_PCR_OUTDIV5_MASK (0x000F0000) +#define PLL_PCR_OUTDIV4_MASK (0x0000F000) +#define PLL_PCR_OUTDIV3_MASK (0x00000F00) +#define PLL_PCR_OUTDIV2_MASK (0x000000F0) +#define PLL_PCR_OUTDIV1_MASK (0x0000000F) + +/* Bit definitions and macros for PSR */ +#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ +#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ +#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ +#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ + +/********************************************************************* +* PCI +*********************************************************************/ + +/* Bit definitions and macros for SCR */ +#define PCI_SCR_PE (0x80000000) /* Parity Error detected */ +#define PCI_SCR_SE (0x40000000) /* System error signalled */ +#define PCI_SCR_MA (0x20000000) /* Master aboart received */ +#define PCI_SCR_TR (0x10000000) /* Target abort received */ +#define PCI_SCR_TS (0x08000000) /* Target abort signalled */ +#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ +#define PCI_SCR_DP (0x01000000) /* Master data parity err */ +#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ +#define PCI_SCR_R (0x00400000) /* Reserved */ +#define PCI_SCR_66M (0x00200000) /* 66Mhz */ +#define PCI_SCR_C (0x00100000) /* Capabilities list */ +#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ +#define PCI_SCR_S (0x00000100) /* SERR enable */ +#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ +#define PCI_SCR_PER (0x00000040) /* Parity error response */ +#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ +#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ +#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ +#define PCI_SCR_B (0x00000004) /* Bus master enable */ +#define PCI_SCR_M (0x00000002) /* Memory access control */ +#define PCI_SCR_IO (0x00000001) /* I/O access control */ + +#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ +#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ +#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ +#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ + +#define PCI_BAR_BAR0(x) (x & 0xFFFC0000) +#define PCI_BAR_BAR1(x) (x & 0xFFF00000) +#define PCI_BAR_BAR2(x) (x & 0xFFC00000) +#define PCI_BAR_BAR3(x) (x & 0xFF000000) +#define PCI_BAR_BAR4(x) (x & 0xF8000000) +#define PCI_BAR_BAR5(x) (x & 0xE0000000) +#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ +#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ +#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ + +#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ +#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ +#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ +#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ + +#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ +#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ +#define PCI_GSCR_SE (0x10000000) /* SERR detected */ +#define PCI_GSCR_ER (0x08000000) /* Error response detected */ +#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ +#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ +#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ +#define PCI_GSCR_PR (0x00000001) /* PCI reset */ + +#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ +#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ +#define PCI_TCR1_P (0x00010000) /* Prefetch reads */ +#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ + +#define PCI_TCR2_B5E (0x00002000) /* */ +#define PCI_TCR2_B4E (0x00001000) /* */ +#define PCI_TCR2_B3E (0x00000800) /* */ +#define PCI_TCR2_B2E (0x00000400) /* */ +#define PCI_TCR2_B1E (0x00000200) /* */ +#define PCI_TCR2_B0E (0x00000100) /* */ +#define PCI_TCR2_CR (0x00000001) /* */ + +#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) +#define PCI_TBATR_EN (0x00000001) /* Enable */ + +#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ +#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ +#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ +#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ +#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ +#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ +#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ +#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ +#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ + +#define PCI_ICR_REE (0x04000000) /* Retry error enable */ +#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ +#define PCI_ICR_TAE (0x01000000) /* Target abort enable */ +#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) + +/********************************************************************/ + +#endif /* __MCF5445X__ */ diff --git a/include/asm-m68k/m547x_8x.h b/arch/m68k/include/asm/m547x_8x.h similarity index 100% rename from include/asm-m68k/m547x_8x.h rename to arch/m68k/include/asm/m547x_8x.h diff --git a/include/asm-m68k/posix_types.h b/arch/m68k/include/asm/posix_types.h similarity index 100% rename from include/asm-m68k/posix_types.h rename to arch/m68k/include/asm/posix_types.h diff --git a/include/asm-m68k/processor.h b/arch/m68k/include/asm/processor.h similarity index 100% rename from include/asm-m68k/processor.h rename to arch/m68k/include/asm/processor.h diff --git a/include/asm-m68k/ptrace.h b/arch/m68k/include/asm/ptrace.h similarity index 100% rename from include/asm-m68k/ptrace.h rename to arch/m68k/include/asm/ptrace.h diff --git a/include/asm-m68k/rtc.h b/arch/m68k/include/asm/rtc.h similarity index 100% rename from include/asm-m68k/rtc.h rename to arch/m68k/include/asm/rtc.h diff --git a/include/asm-m68k/string.h b/arch/m68k/include/asm/string.h similarity index 100% rename from include/asm-m68k/string.h rename to arch/m68k/include/asm/string.h diff --git a/include/asm-m68k/timer.h b/arch/m68k/include/asm/timer.h similarity index 100% rename from include/asm-m68k/timer.h rename to arch/m68k/include/asm/timer.h diff --git a/include/asm-m68k/types.h b/arch/m68k/include/asm/types.h similarity index 100% rename from include/asm-m68k/types.h rename to arch/m68k/include/asm/types.h diff --git a/include/asm-m68k/u-boot.h b/arch/m68k/include/asm/u-boot.h similarity index 100% rename from include/asm-m68k/u-boot.h rename to arch/m68k/include/asm/u-boot.h diff --git a/include/asm-m68k/uart.h b/arch/m68k/include/asm/uart.h similarity index 100% rename from include/asm-m68k/uart.h rename to arch/m68k/include/asm/uart.h diff --git a/include/asm-m68k/unaligned.h b/arch/m68k/include/asm/unaligned.h similarity index 100% rename from include/asm-m68k/unaligned.h rename to arch/m68k/include/asm/unaligned.h diff --git a/lib_m68k/Makefile b/arch/m68k/lib/Makefile similarity index 100% rename from lib_m68k/Makefile rename to arch/m68k/lib/Makefile diff --git a/lib_m68k/board.c b/arch/m68k/lib/board.c similarity index 100% rename from lib_m68k/board.c rename to arch/m68k/lib/board.c diff --git a/lib_m68k/bootm.c b/arch/m68k/lib/bootm.c similarity index 100% rename from lib_m68k/bootm.c rename to arch/m68k/lib/bootm.c diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c new file mode 100644 index 0000000000..ed881783f1 --- /dev/null +++ b/arch/m68k/lib/cache.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +volatile int *cf_icache_status = (int *)ICACHE_STATUS; +volatile int *cf_dcache_status = (int *)DCACHE_STATUS; + +void flush_cache(ulong start_addr, ulong size) +{ + /* Must be implemented for all M68k processors with copy-back data cache */ +} + +int icache_status(void) +{ + return *cf_icache_status; +} + +int dcache_status(void) +{ + return *cf_dcache_status; +} + +void icache_enable(void) +{ + icache_invalid(); + + *cf_icache_status = 1; + +#ifdef CONFIG_CF_V4 + __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2)); + __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3)); +#elif defined(CONFIG_CF_V4e) + __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6)); + __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7)); +#else + __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); +#endif + + __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR)); +} + +void icache_disable(void) +{ + u32 temp = 0; + + *cf_icache_status = 0; + icache_invalid(); + +#ifdef CONFIG_CF_V4 + __asm__ __volatile__("movec %0, %%acr2"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr3"::"r"(temp)); +#elif defined(CONFIG_CF_V4e) + __asm__ __volatile__("movec %0, %%acr6"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr7"::"r"(temp)); +#else + __asm__ __volatile__("movec %0, %%acr0"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(temp)); + +#endif +} + +void icache_invalid(void) +{ + u32 temp; + + temp = CONFIG_SYS_ICACHE_INV; + if (*cf_icache_status) + temp |= CONFIG_SYS_CACHE_ICACR; + + __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); +} + +/* + * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x + * the dcache will be dummy in ColdFire V2 and V3 + */ +void dcache_enable(void) +{ + dcache_invalid(); + *cf_dcache_status = 1; + +#ifdef CONFIG_CF_V4 + __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); +#elif defined(CONFIG_CF_V4e) + __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4)); + __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5)); + +#endif + + __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR)); +} + +void dcache_disable(void) +{ + u32 temp = 0; + + *cf_dcache_status = 0; + dcache_invalid(); + + __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); + +#ifdef CONFIG_CF_V4 + __asm__ __volatile__("movec %0, %%acr0"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(temp)); +#elif defined(CONFIG_CF_V4e) + __asm__ __volatile__("movec %0, %%acr4"::"r"(temp)); + __asm__ __volatile__("movec %0, %%acr5"::"r"(temp)); + +#endif +} + +void dcache_invalid(void) +{ +#ifdef CONFIG_CF_V4 + u32 temp; + + temp = CONFIG_SYS_DCACHE_INV; + if (*cf_dcache_status) + temp |= CONFIG_SYS_CACHE_DCACR; + if (*cf_icache_status) + temp |= CONFIG_SYS_CACHE_ICACR; + + __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); +#endif +} diff --git a/lib_m68k/interrupts.c b/arch/m68k/lib/interrupts.c similarity index 100% rename from lib_m68k/interrupts.c rename to arch/m68k/lib/interrupts.c diff --git a/lib_m68k/time.c b/arch/m68k/lib/time.c similarity index 100% rename from lib_m68k/time.c rename to arch/m68k/lib/time.c diff --git a/lib_m68k/traps.c b/arch/m68k/lib/traps.c similarity index 100% rename from lib_m68k/traps.c rename to arch/m68k/lib/traps.c diff --git a/lib_microblaze/config.mk b/arch/microblaze/config.mk similarity index 100% rename from lib_microblaze/config.mk rename to arch/microblaze/config.mk diff --git a/cpu/microblaze/Makefile b/arch/microblaze/cpu/Makefile similarity index 100% rename from cpu/microblaze/Makefile rename to arch/microblaze/cpu/Makefile diff --git a/cpu/microblaze/cache.c b/arch/microblaze/cpu/cache.c similarity index 100% rename from cpu/microblaze/cache.c rename to arch/microblaze/cpu/cache.c diff --git a/cpu/microblaze/cpu.c b/arch/microblaze/cpu/cpu.c similarity index 100% rename from cpu/microblaze/cpu.c rename to arch/microblaze/cpu/cpu.c diff --git a/cpu/microblaze/exception.c b/arch/microblaze/cpu/exception.c similarity index 100% rename from cpu/microblaze/exception.c rename to arch/microblaze/cpu/exception.c diff --git a/cpu/microblaze/interrupts.c b/arch/microblaze/cpu/interrupts.c similarity index 100% rename from cpu/microblaze/interrupts.c rename to arch/microblaze/cpu/interrupts.c diff --git a/cpu/microblaze/irq.S b/arch/microblaze/cpu/irq.S similarity index 100% rename from cpu/microblaze/irq.S rename to arch/microblaze/cpu/irq.S diff --git a/cpu/microblaze/start.S b/arch/microblaze/cpu/start.S similarity index 100% rename from cpu/microblaze/start.S rename to arch/microblaze/cpu/start.S diff --git a/cpu/microblaze/timer.c b/arch/microblaze/cpu/timer.c similarity index 100% rename from cpu/microblaze/timer.c rename to arch/microblaze/cpu/timer.c diff --git a/include/asm-microblaze/asm.h b/arch/microblaze/include/asm/asm.h similarity index 100% rename from include/asm-microblaze/asm.h rename to arch/microblaze/include/asm/asm.h diff --git a/include/asm-microblaze/bitops.h b/arch/microblaze/include/asm/bitops.h similarity index 100% rename from include/asm-microblaze/bitops.h rename to arch/microblaze/include/asm/bitops.h diff --git a/include/asm-microblaze/byteorder.h b/arch/microblaze/include/asm/byteorder.h similarity index 100% rename from include/asm-microblaze/byteorder.h rename to arch/microblaze/include/asm/byteorder.h diff --git a/include/asm-microblaze/config.h b/arch/microblaze/include/asm/config.h similarity index 100% rename from include/asm-microblaze/config.h rename to arch/microblaze/include/asm/config.h diff --git a/include/asm-microblaze/errno.h b/arch/microblaze/include/asm/errno.h similarity index 100% rename from include/asm-microblaze/errno.h rename to arch/microblaze/include/asm/errno.h diff --git a/include/asm-microblaze/global_data.h b/arch/microblaze/include/asm/global_data.h similarity index 100% rename from include/asm-microblaze/global_data.h rename to arch/microblaze/include/asm/global_data.h diff --git a/include/asm-microblaze/io.h b/arch/microblaze/include/asm/io.h similarity index 100% rename from include/asm-microblaze/io.h rename to arch/microblaze/include/asm/io.h diff --git a/include/asm-microblaze/microblaze_intc.h b/arch/microblaze/include/asm/microblaze_intc.h similarity index 100% rename from include/asm-microblaze/microblaze_intc.h rename to arch/microblaze/include/asm/microblaze_intc.h diff --git a/include/asm-microblaze/microblaze_timer.h b/arch/microblaze/include/asm/microblaze_timer.h similarity index 100% rename from include/asm-microblaze/microblaze_timer.h rename to arch/microblaze/include/asm/microblaze_timer.h diff --git a/include/asm-microblaze/posix_types.h b/arch/microblaze/include/asm/posix_types.h similarity index 100% rename from include/asm-microblaze/posix_types.h rename to arch/microblaze/include/asm/posix_types.h diff --git a/include/asm-microblaze/processor.h b/arch/microblaze/include/asm/processor.h similarity index 100% rename from include/asm-microblaze/processor.h rename to arch/microblaze/include/asm/processor.h diff --git a/include/asm-microblaze/ptrace.h b/arch/microblaze/include/asm/ptrace.h similarity index 100% rename from include/asm-microblaze/ptrace.h rename to arch/microblaze/include/asm/ptrace.h diff --git a/include/asm-microblaze/string.h b/arch/microblaze/include/asm/string.h similarity index 100% rename from include/asm-microblaze/string.h rename to arch/microblaze/include/asm/string.h diff --git a/include/asm-microblaze/system.h b/arch/microblaze/include/asm/system.h similarity index 100% rename from include/asm-microblaze/system.h rename to arch/microblaze/include/asm/system.h diff --git a/include/asm-microblaze/types.h b/arch/microblaze/include/asm/types.h similarity index 100% rename from include/asm-microblaze/types.h rename to arch/microblaze/include/asm/types.h diff --git a/include/asm-microblaze/u-boot.h b/arch/microblaze/include/asm/u-boot.h similarity index 100% rename from include/asm-microblaze/u-boot.h rename to arch/microblaze/include/asm/u-boot.h diff --git a/include/asm-microblaze/unaligned.h b/arch/microblaze/include/asm/unaligned.h similarity index 100% rename from include/asm-microblaze/unaligned.h rename to arch/microblaze/include/asm/unaligned.h diff --git a/lib_microblaze/Makefile b/arch/microblaze/lib/Makefile similarity index 100% rename from lib_microblaze/Makefile rename to arch/microblaze/lib/Makefile diff --git a/lib_microblaze/board.c b/arch/microblaze/lib/board.c similarity index 100% rename from lib_microblaze/board.c rename to arch/microblaze/lib/board.c diff --git a/lib_microblaze/bootm.c b/arch/microblaze/lib/bootm.c similarity index 100% rename from lib_microblaze/bootm.c rename to arch/microblaze/lib/bootm.c diff --git a/lib_microblaze/cache.c b/arch/microblaze/lib/cache.c similarity index 100% rename from lib_microblaze/cache.c rename to arch/microblaze/lib/cache.c diff --git a/lib_microblaze/time.c b/arch/microblaze/lib/time.c similarity index 100% rename from lib_microblaze/time.c rename to arch/microblaze/lib/time.c diff --git a/lib_mips/config.mk b/arch/mips/config.mk similarity index 100% rename from lib_mips/config.mk rename to arch/mips/config.mk diff --git a/cpu/mips/Makefile b/arch/mips/cpu/Makefile similarity index 100% rename from cpu/mips/Makefile rename to arch/mips/cpu/Makefile diff --git a/cpu/mips/asc_serial.c b/arch/mips/cpu/asc_serial.c similarity index 100% rename from cpu/mips/asc_serial.c rename to arch/mips/cpu/asc_serial.c diff --git a/cpu/mips/asc_serial.h b/arch/mips/cpu/asc_serial.h similarity index 100% rename from cpu/mips/asc_serial.h rename to arch/mips/cpu/asc_serial.h diff --git a/cpu/mips/au1x00_eth.c b/arch/mips/cpu/au1x00_eth.c similarity index 100% rename from cpu/mips/au1x00_eth.c rename to arch/mips/cpu/au1x00_eth.c diff --git a/cpu/mips/au1x00_serial.c b/arch/mips/cpu/au1x00_serial.c similarity index 100% rename from cpu/mips/au1x00_serial.c rename to arch/mips/cpu/au1x00_serial.c diff --git a/cpu/mips/au1x00_usb_ohci.c b/arch/mips/cpu/au1x00_usb_ohci.c similarity index 100% rename from cpu/mips/au1x00_usb_ohci.c rename to arch/mips/cpu/au1x00_usb_ohci.c diff --git a/cpu/mips/au1x00_usb_ohci.h b/arch/mips/cpu/au1x00_usb_ohci.h similarity index 100% rename from cpu/mips/au1x00_usb_ohci.h rename to arch/mips/cpu/au1x00_usb_ohci.h diff --git a/cpu/mips/cache.S b/arch/mips/cpu/cache.S similarity index 100% rename from cpu/mips/cache.S rename to arch/mips/cpu/cache.S diff --git a/cpu/mips/config.mk b/arch/mips/cpu/config.mk similarity index 100% rename from cpu/mips/config.mk rename to arch/mips/cpu/config.mk diff --git a/cpu/mips/cpu.c b/arch/mips/cpu/cpu.c similarity index 100% rename from cpu/mips/cpu.c rename to arch/mips/cpu/cpu.c diff --git a/cpu/mips/incaip_clock.c b/arch/mips/cpu/incaip_clock.c similarity index 100% rename from cpu/mips/incaip_clock.c rename to arch/mips/cpu/incaip_clock.c diff --git a/cpu/mips/incaip_wdt.S b/arch/mips/cpu/incaip_wdt.S similarity index 100% rename from cpu/mips/incaip_wdt.S rename to arch/mips/cpu/incaip_wdt.S diff --git a/cpu/mips/interrupts.c b/arch/mips/cpu/interrupts.c similarity index 100% rename from cpu/mips/interrupts.c rename to arch/mips/cpu/interrupts.c diff --git a/cpu/mips/start.S b/arch/mips/cpu/start.S similarity index 100% rename from cpu/mips/start.S rename to arch/mips/cpu/start.S diff --git a/include/asm-mips/addrspace.h b/arch/mips/include/asm/addrspace.h similarity index 100% rename from include/asm-mips/addrspace.h rename to arch/mips/include/asm/addrspace.h diff --git a/include/asm-mips/asm.h b/arch/mips/include/asm/asm.h similarity index 100% rename from include/asm-mips/asm.h rename to arch/mips/include/asm/asm.h diff --git a/include/asm-mips/au1x00.h b/arch/mips/include/asm/au1x00.h similarity index 100% rename from include/asm-mips/au1x00.h rename to arch/mips/include/asm/au1x00.h diff --git a/include/asm-mips/bitops.h b/arch/mips/include/asm/bitops.h similarity index 100% rename from include/asm-mips/bitops.h rename to arch/mips/include/asm/bitops.h diff --git a/include/asm-mips/byteorder.h b/arch/mips/include/asm/byteorder.h similarity index 100% rename from include/asm-mips/byteorder.h rename to arch/mips/include/asm/byteorder.h diff --git a/include/asm-mips/cachectl.h b/arch/mips/include/asm/cachectl.h similarity index 100% rename from include/asm-mips/cachectl.h rename to arch/mips/include/asm/cachectl.h diff --git a/include/asm-mips/cacheops.h b/arch/mips/include/asm/cacheops.h similarity index 100% rename from include/asm-mips/cacheops.h rename to arch/mips/include/asm/cacheops.h diff --git a/include/asm-mips/config.h b/arch/mips/include/asm/config.h similarity index 100% rename from include/asm-mips/config.h rename to arch/mips/include/asm/config.h diff --git a/include/asm-mips/errno.h b/arch/mips/include/asm/errno.h similarity index 100% rename from include/asm-mips/errno.h rename to arch/mips/include/asm/errno.h diff --git a/include/asm-mips/global_data.h b/arch/mips/include/asm/global_data.h similarity index 100% rename from include/asm-mips/global_data.h rename to arch/mips/include/asm/global_data.h diff --git a/include/asm-mips/inca-ip.h b/arch/mips/include/asm/inca-ip.h similarity index 100% rename from include/asm-mips/inca-ip.h rename to arch/mips/include/asm/inca-ip.h diff --git a/include/asm-mips/io.h b/arch/mips/include/asm/io.h similarity index 100% rename from include/asm-mips/io.h rename to arch/mips/include/asm/io.h diff --git a/include/asm-mips/isadep.h b/arch/mips/include/asm/isadep.h similarity index 100% rename from include/asm-mips/isadep.h rename to arch/mips/include/asm/isadep.h diff --git a/include/asm-mips/mipsregs.h b/arch/mips/include/asm/mipsregs.h similarity index 100% rename from include/asm-mips/mipsregs.h rename to arch/mips/include/asm/mipsregs.h diff --git a/include/asm-mips/posix_types.h b/arch/mips/include/asm/posix_types.h similarity index 100% rename from include/asm-mips/posix_types.h rename to arch/mips/include/asm/posix_types.h diff --git a/include/asm-mips/processor.h b/arch/mips/include/asm/processor.h similarity index 100% rename from include/asm-mips/processor.h rename to arch/mips/include/asm/processor.h diff --git a/include/asm-mips/ptrace.h b/arch/mips/include/asm/ptrace.h similarity index 100% rename from include/asm-mips/ptrace.h rename to arch/mips/include/asm/ptrace.h diff --git a/include/asm-mips/reboot.h b/arch/mips/include/asm/reboot.h similarity index 100% rename from include/asm-mips/reboot.h rename to arch/mips/include/asm/reboot.h diff --git a/include/asm-mips/reg.h b/arch/mips/include/asm/reg.h similarity index 100% rename from include/asm-mips/reg.h rename to arch/mips/include/asm/reg.h diff --git a/include/asm-mips/regdef.h b/arch/mips/include/asm/regdef.h similarity index 100% rename from include/asm-mips/regdef.h rename to arch/mips/include/asm/regdef.h diff --git a/include/asm-mips/sgidefs.h b/arch/mips/include/asm/sgidefs.h similarity index 100% rename from include/asm-mips/sgidefs.h rename to arch/mips/include/asm/sgidefs.h diff --git a/include/asm-mips/string.h b/arch/mips/include/asm/string.h similarity index 100% rename from include/asm-mips/string.h rename to arch/mips/include/asm/string.h diff --git a/include/asm-mips/system.h b/arch/mips/include/asm/system.h similarity index 100% rename from include/asm-mips/system.h rename to arch/mips/include/asm/system.h diff --git a/include/asm-mips/types.h b/arch/mips/include/asm/types.h similarity index 100% rename from include/asm-mips/types.h rename to arch/mips/include/asm/types.h diff --git a/include/asm-mips/u-boot.h b/arch/mips/include/asm/u-boot.h similarity index 100% rename from include/asm-mips/u-boot.h rename to arch/mips/include/asm/u-boot.h diff --git a/include/asm-mips/unaligned.h b/arch/mips/include/asm/unaligned.h similarity index 100% rename from include/asm-mips/unaligned.h rename to arch/mips/include/asm/unaligned.h diff --git a/lib_mips/Makefile b/arch/mips/lib/Makefile similarity index 100% rename from lib_mips/Makefile rename to arch/mips/lib/Makefile diff --git a/lib_mips/board.c b/arch/mips/lib/board.c similarity index 100% rename from lib_mips/board.c rename to arch/mips/lib/board.c diff --git a/lib_mips/bootm.c b/arch/mips/lib/bootm.c similarity index 100% rename from lib_mips/bootm.c rename to arch/mips/lib/bootm.c diff --git a/lib_mips/bootm_qemu_mips.c b/arch/mips/lib/bootm_qemu_mips.c similarity index 100% rename from lib_mips/bootm_qemu_mips.c rename to arch/mips/lib/bootm_qemu_mips.c diff --git a/lib_mips/time.c b/arch/mips/lib/time.c similarity index 100% rename from lib_mips/time.c rename to arch/mips/lib/time.c diff --git a/lib_nios/config.mk b/arch/nios/config.mk similarity index 100% rename from lib_nios/config.mk rename to arch/nios/config.mk diff --git a/cpu/nios/Makefile b/arch/nios/cpu/Makefile similarity index 100% rename from cpu/nios/Makefile rename to arch/nios/cpu/Makefile diff --git a/cpu/nios/asmi.c b/arch/nios/cpu/asmi.c similarity index 100% rename from cpu/nios/asmi.c rename to arch/nios/cpu/asmi.c diff --git a/cpu/nios/config.mk b/arch/nios/cpu/config.mk similarity index 100% rename from cpu/nios/config.mk rename to arch/nios/cpu/config.mk diff --git a/cpu/nios/cpu.c b/arch/nios/cpu/cpu.c similarity index 100% rename from cpu/nios/cpu.c rename to arch/nios/cpu/cpu.c diff --git a/cpu/nios/interrupts.c b/arch/nios/cpu/interrupts.c similarity index 100% rename from cpu/nios/interrupts.c rename to arch/nios/cpu/interrupts.c diff --git a/cpu/nios/serial.c b/arch/nios/cpu/serial.c similarity index 100% rename from cpu/nios/serial.c rename to arch/nios/cpu/serial.c diff --git a/cpu/nios/spi.c b/arch/nios/cpu/spi.c similarity index 100% rename from cpu/nios/spi.c rename to arch/nios/cpu/spi.c diff --git a/cpu/nios/start.S b/arch/nios/cpu/start.S similarity index 100% rename from cpu/nios/start.S rename to arch/nios/cpu/start.S diff --git a/cpu/nios/traps.S b/arch/nios/cpu/traps.S similarity index 100% rename from cpu/nios/traps.S rename to arch/nios/cpu/traps.S diff --git a/include/asm-nios/bitops.h b/arch/nios/include/asm/bitops.h similarity index 100% rename from include/asm-nios/bitops.h rename to arch/nios/include/asm/bitops.h diff --git a/include/asm-nios/byteorder.h b/arch/nios/include/asm/byteorder.h similarity index 100% rename from include/asm-nios/byteorder.h rename to arch/nios/include/asm/byteorder.h diff --git a/include/asm-nios/cache.h b/arch/nios/include/asm/cache.h similarity index 100% rename from include/asm-nios/cache.h rename to arch/nios/include/asm/cache.h diff --git a/include/asm-nios/config.h b/arch/nios/include/asm/config.h similarity index 100% rename from include/asm-nios/config.h rename to arch/nios/include/asm/config.h diff --git a/include/asm-nios/global_data.h b/arch/nios/include/asm/global_data.h similarity index 100% rename from include/asm-nios/global_data.h rename to arch/nios/include/asm/global_data.h diff --git a/include/asm-nios/io.h b/arch/nios/include/asm/io.h similarity index 100% rename from include/asm-nios/io.h rename to arch/nios/include/asm/io.h diff --git a/include/asm-nios/posix_types.h b/arch/nios/include/asm/posix_types.h similarity index 100% rename from include/asm-nios/posix_types.h rename to arch/nios/include/asm/posix_types.h diff --git a/include/asm-nios/processor.h b/arch/nios/include/asm/processor.h similarity index 100% rename from include/asm-nios/processor.h rename to arch/nios/include/asm/processor.h diff --git a/include/asm-nios/psr.h b/arch/nios/include/asm/psr.h similarity index 100% rename from include/asm-nios/psr.h rename to arch/nios/include/asm/psr.h diff --git a/include/asm-nios/ptrace.h b/arch/nios/include/asm/ptrace.h similarity index 100% rename from include/asm-nios/ptrace.h rename to arch/nios/include/asm/ptrace.h diff --git a/include/asm-nios/status_led.h b/arch/nios/include/asm/status_led.h similarity index 100% rename from include/asm-nios/status_led.h rename to arch/nios/include/asm/status_led.h diff --git a/include/asm-nios/string.h b/arch/nios/include/asm/string.h similarity index 100% rename from include/asm-nios/string.h rename to arch/nios/include/asm/string.h diff --git a/include/asm-nios/system.h b/arch/nios/include/asm/system.h similarity index 100% rename from include/asm-nios/system.h rename to arch/nios/include/asm/system.h diff --git a/include/asm-nios/types.h b/arch/nios/include/asm/types.h similarity index 100% rename from include/asm-nios/types.h rename to arch/nios/include/asm/types.h diff --git a/include/asm-nios/u-boot.h b/arch/nios/include/asm/u-boot.h similarity index 100% rename from include/asm-nios/u-boot.h rename to arch/nios/include/asm/u-boot.h diff --git a/lib_nios/Makefile b/arch/nios/lib/Makefile similarity index 100% rename from lib_nios/Makefile rename to arch/nios/lib/Makefile diff --git a/lib_nios/board.c b/arch/nios/lib/board.c similarity index 100% rename from lib_nios/board.c rename to arch/nios/lib/board.c diff --git a/lib_nios/bootm.c b/arch/nios/lib/bootm.c similarity index 100% rename from lib_nios/bootm.c rename to arch/nios/lib/bootm.c diff --git a/lib_nios/cache.c b/arch/nios/lib/cache.c similarity index 100% rename from lib_nios/cache.c rename to arch/nios/lib/cache.c diff --git a/lib_nios/divmod.c b/arch/nios/lib/divmod.c similarity index 100% rename from lib_nios/divmod.c rename to arch/nios/lib/divmod.c diff --git a/lib_nios/math.h b/arch/nios/lib/math.h similarity index 100% rename from lib_nios/math.h rename to arch/nios/lib/math.h diff --git a/lib_nios/mult.c b/arch/nios/lib/mult.c similarity index 100% rename from lib_nios/mult.c rename to arch/nios/lib/mult.c diff --git a/lib_nios/time.c b/arch/nios/lib/time.c similarity index 100% rename from lib_nios/time.c rename to arch/nios/lib/time.c diff --git a/lib_nios2/config.mk b/arch/nios2/config.mk similarity index 100% rename from lib_nios2/config.mk rename to arch/nios2/config.mk diff --git a/arch/nios2/cpu/Makefile b/arch/nios2/cpu/Makefile new file mode 100644 index 0000000000..3dfaa833c0 --- /dev/null +++ b/arch/nios2/cpu/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +SOBJS = exceptions.o +COBJS = cpu.o interrupts.o sysid.o traps.o epcs.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/nios2/config.mk b/arch/nios2/cpu/config.mk similarity index 100% rename from cpu/nios2/config.mk rename to arch/nios2/cpu/config.mk diff --git a/cpu/nios2/cpu.c b/arch/nios2/cpu/cpu.c similarity index 100% rename from cpu/nios2/cpu.c rename to arch/nios2/cpu/cpu.c diff --git a/arch/nios2/cpu/epcs.c b/arch/nios2/cpu/epcs.c new file mode 100644 index 0000000000..ab7d746b5f --- /dev/null +++ b/arch/nios2/cpu/epcs.c @@ -0,0 +1,733 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_SYS_NIOS_EPCSBASE) +#include +#include +#include +#include + + +/*-----------------------------------------------------------------------*/ +#define SHORT_HELP\ + "epcs - read/write Cyclone EPCS configuration device.\n" + +#define LONG_HELP\ + "\n"\ + "epcs erase start [end]\n"\ + " - erase sector start or sectors start through end.\n"\ + "epcs info\n"\ + " - display EPCS device information.\n"\ + "epcs protect on | off\n"\ + " - turn device protection on or off.\n"\ + "epcs read addr offset count\n"\ + " - read count bytes from offset to addr.\n"\ + "epcs write addr offset count\n"\ + " - write count bytes to offset from addr.\n"\ + "epcs verify addr offset count\n"\ + " - verify count bytes at offset from addr." + + +/*-----------------------------------------------------------------------*/ +/* Operation codes for serial configuration devices + */ +#define EPCS_WRITE_ENA 0x06 /* Write enable */ +#define EPCS_WRITE_DIS 0x04 /* Write disable */ +#define EPCS_READ_STAT 0x05 /* Read status */ +#define EPCS_READ_BYTES 0x03 /* Read bytes */ +#define EPCS_READ_ID 0xab /* Read silicon id */ +#define EPCS_WRITE_STAT 0x01 /* Write status */ +#define EPCS_WRITE_BYTES 0x02 /* Write bytes */ +#define EPCS_ERASE_BULK 0xc7 /* Erase entire device */ +#define EPCS_ERASE_SECT 0xd8 /* Erase sector */ + +/* Device status register bits + */ +#define EPCS_STATUS_WIP (1<<0) /* Write in progress */ +#define EPCS_STATUS_WEL (1<<1) /* Write enable latch */ + +/* Misc + */ +#define EPCS_TIMEOUT 100 /* 100 msec timeout */ + +static nios_spi_t *epcs = (nios_spi_t *)CONFIG_SYS_NIOS_EPCSBASE; + +/*********************************************************************** + * Device access + ***********************************************************************/ +static int epcs_cs (int assert) +{ + ulong start; + unsigned tmp; + + + if (assert) { + tmp = readl (&epcs->control); + writel (tmp | NIOS_SPI_SSO, &epcs->control); + } else { + /* Let all bits shift out */ + start = get_timer (0); + while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + tmp = readl (&epcs->control); + writel (tmp & ~NIOS_SPI_SSO, &epcs->control); + } + return (0); +} + +static int epcs_tx (unsigned char c) +{ + ulong start; + + start = get_timer (0); + while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + writel (c, &epcs->txdata); + return (0); +} + +static int epcs_rx (void) +{ + ulong start; + + start = get_timer (0); + while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + return (readl (&epcs->rxdata)); +} + +static unsigned char bitrev[] = { + 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, + 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f +}; + +static unsigned char epcs_bitrev (unsigned char c) +{ + unsigned char val; + + val = bitrev[c>>4]; + val |= bitrev[c & 0x0f]<<4; + return (val); +} + +static void epcs_rcv (unsigned char *dst, int len) +{ + while (len--) { + epcs_tx (0); + *dst++ = epcs_rx (); + } +} + +static void epcs_rrcv (unsigned char *dst, int len) +{ + while (len--) { + epcs_tx (0); + *dst++ = epcs_bitrev (epcs_rx ()); + } +} + +static void epcs_snd (unsigned char *src, int len) +{ + while (len--) { + epcs_tx (*src++); + epcs_rx (); + } +} + +static void epcs_rsnd (unsigned char *src, int len) +{ + while (len--) { + epcs_tx (epcs_bitrev (*src++)); + epcs_rx (); + } +} + +static void epcs_wr_enable (void) +{ + epcs_cs (1); + epcs_tx (EPCS_WRITE_ENA); + epcs_rx (); + epcs_cs (0); +} + +static unsigned char epcs_status_rd (void) +{ + unsigned char status; + + epcs_cs (1); + epcs_tx (EPCS_READ_STAT); + epcs_rx (); + epcs_tx (0); + status = epcs_rx (); + epcs_cs (0); + return (status); +} + +static void epcs_status_wr (unsigned char status) +{ + epcs_wr_enable (); + epcs_cs (1); + epcs_tx (EPCS_WRITE_STAT); + epcs_rx (); + epcs_tx (status); + epcs_rx (); + epcs_cs (0); + return; +} + +/*********************************************************************** + * Device information + ***********************************************************************/ + +static struct epcs_devinfo_t devinfo[] = { + { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, + { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, + { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c }, + { "EPCS64", 0x16, 23,128, 16, 8, 0x1c }, + { 0, 0, 0, 0, 0, 0 } +}; + +int epcs_reset (void) +{ + /* When booting from an epcs controller, the epcs bootrom + * code may leave the slave select in an asserted state. + * This causes two problems: (1) The initial epcs access + * will fail -- not a big deal, and (2) a software reset + * will cause the bootrom code to hang since it does not + * ensure the select is negated prior to first access -- a + * big deal. Here we just negate chip select and everything + * gets better :-) + */ + epcs_cs (0); /* Negate chip select */ + return (0); +} + +epcs_devinfo_t *epcs_dev_find (void) +{ + unsigned char buf[4]; + unsigned char id; + int i; + struct epcs_devinfo_t *dev = NULL; + + /* Read silicon id requires 3 "dummy bytes" before it's put + * on the wire. + */ + buf[0] = EPCS_READ_ID; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rcv (buf,1); + if (epcs_cs (0) == -1) + return (NULL); + id = buf[0]; + + /* Find the info struct */ + i = 0; + while (devinfo[i].name) { + if (id == devinfo[i].id) { + dev = &devinfo[i]; + break; + } + i++; + } + + return (dev); +} + +/*********************************************************************** + * Misc Utilities + ***********************************************************************/ +int epcs_cfgsz (void) +{ + int sz = 0; + unsigned char buf[128]; + unsigned char *p; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + /* Read in the first 128 bytes of the device */ + buf[0] = EPCS_READ_BYTES; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rrcv (buf, sizeof(buf)); + epcs_cs (0); + + /* Search for the starting 0x6a which is followed by the + * 4-byte 'register' and 4-byte bit-count. + */ + p = buf; + while (p < buf + sizeof(buf)-8) { + if ( *p == 0x6a ) { + /* Point to bit count and extract */ + p += 5; + sz = *p++; + sz |= *p++ << 8; + sz |= *p++ << 16; + sz |= *p++ << 24; + /* Convert to byte count */ + sz += 7; + sz >>= 3; + } else if (*p == 0xff) { + /* 0xff is ok ... just skip */ + p++; + continue; + } else { + /* Not 0xff or 0x6a ... something's not + * right ... report 'unknown' (sz=0). + */ + break; + } + } + return (sz); +} + +int epcs_erase (unsigned start, unsigned end) +{ + unsigned off, sectsz; + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev || (start>end)) + return (-1); + + /* Erase the requested sectors. An address is required + * that lies within the requested sector -- we'll just + * use the first address in the sector. + */ + printf ("epcs erasing sector %d ", start); + if (start != end) + printf ("to %d ", end); + sectsz = (1 << dev->sz_sect); + while (start <= end) { + off = start * sectsz; + start++; + + buf[0] = EPCS_ERASE_SECT; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_wr_enable (); + epcs_cs (1); + epcs_snd (buf,4); + epcs_cs (0); + + printf ("."); /* Some user feedback */ + + /* Wait for erase to complete */ + while (epcs_status_rd() & EPCS_STATUS_WIP) + ; + } + printf (" done.\n"); + return (0); +} + +int epcs_read (ulong addr, ulong off, ulong cnt) +{ + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + buf[0] = EPCS_READ_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rrcv ((unsigned char *)addr, cnt); + epcs_cs (0); + + return (0); +} + +int epcs_write (ulong addr, ulong off, ulong cnt) +{ + ulong wrcnt; + unsigned pgsz; + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + pgsz = (1<sz_page); + while (cnt) { + if (off % pgsz) + wrcnt = pgsz - (off % pgsz); + else + wrcnt = pgsz; + wrcnt = (wrcnt > cnt) ? cnt : wrcnt; + + buf[0] = EPCS_WRITE_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_wr_enable (); + epcs_cs (1); + epcs_snd (buf,4); + epcs_rsnd ((unsigned char *)addr, wrcnt); + epcs_cs (0); + + /* Wait for write to complete */ + while (epcs_status_rd() & EPCS_STATUS_WIP) + ; + + cnt -= wrcnt; + off += wrcnt; + addr += wrcnt; + } + + return (0); +} + +int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err) +{ + ulong rdcnt; + unsigned char buf[256]; + unsigned char *start,*end; + int i; + + start = end = (unsigned char *)addr; + while (cnt) { + rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; + epcs_read ((ulong)buf, off, rdcnt); + for (i=0; isz_sect); + off = sectsz * sect; + end = off + sectsz; + + while (off < end) { + epcs_read ((ulong)buf, off, sizeof(buf)); + for (i=0; i < sizeof(buf); i++) { + if (buf[i] != 0xff) { + *offset = off + i; + return (0); + } + } + off += sizeof(buf); + } + return (1); +} + + +/*********************************************************************** + * Commands + ***********************************************************************/ +static +void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + int i; + unsigned char stat; + unsigned tmp; + int erased; + + /* Basic device info */ + printf ("%s: %d kbytes (%d sectors x %d kbytes," + " %d bytes/page)\n", + dev->name, 1 << (dev->size-10), + dev->num_sects, 1 << (dev->sz_sect-10), + 1 << dev->sz_page ); + + /* Status -- for now protection is all-or-nothing */ + stat = epcs_status_rd(); + printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", + stat, + (stat & EPCS_STATUS_WIP) ? 1 : 0, + (stat & EPCS_STATUS_WEL) ? 1 : 0, + (stat & dev->prot_mask) ? "on" : "off" ); + + /* Configuration */ + tmp = epcs_cfgsz (); + if (tmp) { + printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); + } else { + printf ("config: unknown\n" ); + } + + /* Sector info */ + for (i=0; (i < dev->num_sects) && (argc > 1); i++) { + erased = epcs_sect_erased (i, &tmp, dev); + if ((i & 0x03) == 0) printf ("\n"); + printf ("%4d: %07x ", + i, i*(1<sz_sect) ); + if (erased) + printf ("E "); + else + printf (" "); + } + printf ("\n"); + + return; +} + +static +void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned start,end; + + if ((argc < 3) || (argc > 4)) { + printf ("USAGE: epcs erase sect [end]\n"); + return; + } + if ((epcs_status_rd() & dev->prot_mask) != 0) { + printf ( "epcs: device protected.\n"); + return; + } + + start = simple_strtoul (argv[2], NULL, 10); + if (argc > 3) + end = simple_strtoul (argv[3], NULL, 10); + else + end = start; + if ((start >= dev->num_sects) || (start > end)) { + printf ("epcs: invalid sector range: [%d:%d]\n", + start, end ); + return; + } + + epcs_erase (start, end); + + return; +} + +static +void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned char stat; + + /* For now protection is all-or-nothing to keep things + * simple. The protection bits don't map in a linear + * fashion ... and we would rather protect the bottom + * of the device since it contains the config data and + * leave the top unprotected for app use. But unfortunately + * protection works from top-to-bottom so it does + * really help very much from a software app point-of-view. + */ + if (argc < 3) { + printf ("USAGE: epcs protect on | off\n"); + return; + } + if (!dev) + return; + + /* Protection on/off is just a matter of setting/clearing + * all protection bits in the status register. + */ + stat = epcs_status_rd (); + if (strcmp ("on", argv[2]) == 0) { + stat |= dev->prot_mask; + } else if (strcmp ("off", argv[2]) == 0 ) { + stat &= ~dev->prot_mask; + } else { + printf ("epcs: unknown protection: %s\n", argv[2]); + return; + } + epcs_status_wr (stat); + return; +} + +static +void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + + if (argc < 5) { + printf ("USAGE: epcs read addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n", + addr, off, cnt); + epcs_read (addr, off, cnt); + + return; +} + +static +void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: epcs write addr offset count\n"); + return; + } + if ((epcs_status_rd() & dev->prot_mask) != 0) { + printf ( "epcs: device protected.\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + epcs_write (addr, off, cnt); + if (epcs_verify (addr, off, cnt, &err) != 0) + printf ("epcs: write error at offset %06lx\n", err); + + return; +} + +static +void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: epcs verify addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + if (epcs_verify (addr, off, cnt, &err) != 0) + printf ("epcs: verify error at offset %06lx\n", err); + + return; +} + +/*-----------------------------------------------------------------------*/ +int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int len; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) { + printf ("epcs: device not found.\n"); + return (-1); + } + + if (argc < 2) { + do_epcs_info (dev, argc, argv); + return (0); + } + + len = strlen (argv[1]); + if (strncmp ("info", argv[1], len) == 0) { + do_epcs_info (dev, argc, argv); + } else if (strncmp ("erase", argv[1], len) == 0) { + do_epcs_erase (dev, argc, argv); + } else if (strncmp ("protect", argv[1], len) == 0) { + do_epcs_protect (dev, argc, argv); + } else if (strncmp ("read", argv[1], len) == 0) { + do_epcs_read (dev, argc, argv); + } else if (strncmp ("write", argv[1], len) == 0) { + do_epcs_write (dev, argc, argv); + } else if (strncmp ("verify", argv[1], len) == 0) { + do_epcs_verify (dev, argc, argv); + } else { + printf ("epcs: unknown operation: %s\n", argv[1]); + } + + return (0); +} + +/*-----------------------------------------------------------------------*/ + + +U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP ); + +#endif /* CONFIG_NIOS_EPCS */ diff --git a/cpu/nios2/exceptions.S b/arch/nios2/cpu/exceptions.S similarity index 100% rename from cpu/nios2/exceptions.S rename to arch/nios2/cpu/exceptions.S diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c new file mode 100644 index 0000000000..b552db4eba --- /dev/null +++ b/arch/nios2/cpu/interrupts.c @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_STATUS_LED +#include +#endif + +#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ) +#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation) +#endif + +/****************************************************************************/ + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + int count; +}; + +static struct irq_action vecs[32]; + +/*************************************************************************/ +volatile ulong timestamp = 0; + +void reset_timer (void) +{ + nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; + + /* From Embedded Peripherals Handbook: + * + * "When the hardware is configured with Writeable period + * disabled, writing to one of the period_n registers causes + * the counter to reset to the fixed Timeout Period specified + * at system generation time." + * + * Here we force a reload to prevent early timeouts from + * get_timer() when the interrupt period is greater than + * than 1 msec. + * + * Simply write to periodl with its own value to force an + * internal counter reload, THEN reset the timestamp. + */ + writel (readl (&tmr->periodl), &tmr->periodl); + timestamp = 0; + + /* From Embedded Peripherals Handbook: + * + * "Writing to one of the period_n registers stops the internal + * counter, except when the hardware is configured with Start/Stop + * control bits off. If Start/Stop control bits is off, writing + * either register does not stop the counter." + * + * In order to accomodate either configuration, the control + * register is re-written. If the counter is stopped, it will + * be restarted. If it is running, the write is essentially + * a nop. + */ + writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START, + &tmr->control); + +} + +ulong get_timer (ulong base) +{ + WATCHDOG_RESET (); + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} + + +/* The board must handle this interrupt if a timer is not + * provided. + */ +#if defined(CONFIG_SYS_NIOS_TMRBASE) +void tmr_isr (void *arg) +{ + nios_timer_t *tmr = (nios_timer_t *)arg; + /* Interrupt is cleared by writing anything to the + * status register. + */ + writel (0, &tmr->status); + timestamp += CONFIG_SYS_NIOS_TMRMS; +#ifdef CONFIG_STATUS_LED + status_led_tick(timestamp); +#endif +} + +static void tmr_init (void) +{ + nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; + + writel (0, &tmr->status); + writel (0, &tmr->control); + writel (NIOS_TIMER_STOP, &tmr->control); + +#if defined(CONFIG_SYS_NIOS_TMRCNT) + writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl); + writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh); +#endif + writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START, + &tmr->control); + irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr); +} + +#endif /* CONFIG_SYS_NIOS_TMRBASE */ + +/*************************************************************************/ +int disable_interrupts (void) +{ + int val = rdctl (CTL_STATUS); + wrctl (CTL_STATUS, val & ~STATUS_IE); + return (val & STATUS_IE); +} + +void enable_interrupts( void ) +{ + int val = rdctl (CTL_STATUS); + wrctl (CTL_STATUS, val | STATUS_IE); +} + +void external_interrupt (struct pt_regs *regs) +{ + unsigned irqs; + struct irq_action *act; + + /* Evaluate only irqs that are both enabled AND pending */ + irqs = rdctl (CTL_IENABLE) & rdctl (CTL_IPENDING); + act = vecs; + + /* Assume (as does the Nios2 HAL) that bit 0 is highest + * priority. NOTE: There is ALWAYS a handler assigned + * (the default if no other). + */ + while (irqs) { + if (irqs & 1) { + act->handler (act->arg); + act->count++; + } + irqs >>=1; + act++; + } +} + +static void def_hdlr (void *arg) +{ + unsigned irqs = rdctl (CTL_IENABLE); + + /* Disable the individual interrupt -- with gratuitous + * warning. + */ + irqs &= ~(1 << (int)arg); + wrctl (CTL_IENABLE, irqs); + printf ("WARNING: Disabling unhandled interrupt: %d\n", + (int)arg); +} + +/*************************************************************************/ +void irq_install_handler (int irq, interrupt_handler_t *hdlr, void *arg) +{ + + int flag; + struct irq_action *act; + unsigned ena = rdctl (CTL_IENABLE); + + if ((irq < 0) || (irq > 31)) + return; + act = &vecs[irq]; + + flag = disable_interrupts (); + if (hdlr) { + act->handler = hdlr; + act->arg = arg; + ena |= (1 << irq); /* enable */ + } else { + act->handler = def_hdlr; + act->arg = (void *)irq; + ena &= ~(1 << irq); /* disable */ + } + wrctl (CTL_IENABLE, ena); + if (flag) enable_interrupts (); +} + + +int interrupt_init (void) +{ + int i; + + /* Assign the default handler to all */ + for (i = 0; i < 32; i++) { + vecs[i].handler = def_hdlr; + vecs[i].arg = (void *)i; + vecs[i].count = 0; + } + +#if defined(CONFIG_SYS_NIOS_TMRBASE) + tmr_init (); +#endif + + enable_interrupts (); + return (0); +} + + +/*************************************************************************/ +#if defined(CONFIG_CMD_IRQ) +int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + struct irq_action *act = vecs; + + printf ("\nInterrupt-Information:\n\n"); + printf ("Nr Routine Arg Count\n"); + printf ("-----------------------------\n"); + + for (i=0; i<32; i++) { + if (act->handler != def_hdlr) { + printf ("%02d %08lx %08lx %d\n", + i, + (ulong)act->handler, + (ulong)act->arg, + act->count); + } + act++; + } + printf ("\n"); + + return (0); +} +#endif diff --git a/cpu/nios2/start.S b/arch/nios2/cpu/start.S similarity index 100% rename from cpu/nios2/start.S rename to arch/nios2/cpu/start.S diff --git a/cpu/nios2/sysid.c b/arch/nios2/cpu/sysid.c similarity index 100% rename from cpu/nios2/sysid.c rename to arch/nios2/cpu/sysid.c diff --git a/cpu/nios2/traps.c b/arch/nios2/cpu/traps.c similarity index 100% rename from cpu/nios2/traps.c rename to arch/nios2/cpu/traps.c diff --git a/arch/nios2/include/asm/bitops.h b/arch/nios2/include/asm/bitops.h new file mode 100644 index 0000000000..cf48ff7a1a --- /dev/null +++ b/arch/nios2/include/asm/bitops.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_BITOPS_H_ +#define __ASM_NIOS2_BITOPS_H_ + +/* copied from linux-2.6/include/asm-generic/bitops */ +#include +#include +#include + +#endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/arch/nios2/include/asm/bitops/atomic.h b/arch/nios2/include/asm/bitops/atomic.h new file mode 100644 index 0000000000..c8946465e6 --- /dev/null +++ b/arch/nios2/include/asm/bitops/atomic.h @@ -0,0 +1,189 @@ +#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_ATOMIC_H_ + +#include +#include + +#ifdef CONFIG_SMP +#include +#include /* we use L1_CACHE_BYTES */ + +/* Use an array of spinlocks for our atomic_ts. + * Hash function to index into a different SPINLOCK. + * Since "a" is usually an address, use one spinlock per cacheline. + */ +# define ATOMIC_HASH_SIZE 4 +# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) + +extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; + +/* Can't use raw_spin_lock_irq because of #include problems, so + * this is the substitute */ +#define _atomic_spin_lock_irqsave(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + local_irq_save(f); \ + __raw_spin_lock(s); \ +} while(0) + +#define _atomic_spin_unlock_irqrestore(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + __raw_spin_unlock(s); \ + local_irq_restore(f); \ +} while(0) + + +#else +# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) +# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) +#endif + +/* + * NMI events can occur at any time, including when interrupts have been + * disabled by *_irqsave(). So you can get NMI events occurring while a + * *_bit function is holding a spin lock. If the NMI handler also wants + * to do bit manipulation (and they do) then you can get a deadlock + * between the original caller of *_bit() and the NMI handler. + * + * by Keith Owens + */ + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p |= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +static inline void clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p &= ~mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * change_bit - Toggle a bit in memory + * @nr: Bit to change + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. It may be + * reordered on other architectures than x86. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p ^= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It may be reordered on other architectures than x86. + * It also implies a memory barrier. + */ +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old | mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It can be reorderdered on other architectures other than x86. + * It also implies a memory barrier. + */ +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old & ~mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old ^ mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ diff --git a/arch/nios2/include/asm/bitops/ffs.h b/arch/nios2/include/asm/bitops/ffs.h new file mode 100644 index 0000000000..fbbb43af7d --- /dev/null +++ b/arch/nios2/include/asm/bitops/ffs.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/arch/nios2/include/asm/bitops/non-atomic.h b/arch/nios2/include/asm/bitops/non-atomic.h new file mode 100644 index 0000000000..697cc2b7e0 --- /dev/null +++ b/arch/nios2/include/asm/bitops/non-atomic.h @@ -0,0 +1,108 @@ +#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ + +#include + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void __clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to change + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +/* WARNING: non atomic and it can be reordered! */ +static inline int __test_and_change_bit(int nr, + volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile unsigned long *addr) +{ + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); +} + +#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */ diff --git a/include/asm-nios2/byteorder.h b/arch/nios2/include/asm/byteorder.h similarity index 100% rename from include/asm-nios2/byteorder.h rename to arch/nios2/include/asm/byteorder.h diff --git a/include/asm-nios2/cache.h b/arch/nios2/include/asm/cache.h similarity index 100% rename from include/asm-nios2/cache.h rename to arch/nios2/include/asm/cache.h diff --git a/include/asm-nios2/config.h b/arch/nios2/include/asm/config.h similarity index 100% rename from include/asm-nios2/config.h rename to arch/nios2/include/asm/config.h diff --git a/include/asm-ppc/errno.h b/arch/nios2/include/asm/errno.h similarity index 100% rename from include/asm-ppc/errno.h rename to arch/nios2/include/asm/errno.h diff --git a/include/asm-nios2/global_data.h b/arch/nios2/include/asm/global_data.h similarity index 100% rename from include/asm-nios2/global_data.h rename to arch/nios2/include/asm/global_data.h diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h new file mode 100644 index 0000000000..121405cd60 --- /dev/null +++ b/arch/nios2/include/asm/io.h @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_IO_H_ +#define __ASM_NIOS2_IO_H_ + +static inline void sync(void) +{ + __asm__ __volatile__ ("sync" : : : "memory"); +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + +extern unsigned char inb (unsigned char *port); +extern unsigned short inw (unsigned short *port); +extern unsigned inl (unsigned port); + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +#define readb(addr)\ + ({unsigned char val;\ + asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readw(addr)\ + ({unsigned short val;\ + asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readl(addr)\ + ({unsigned long val;\ + asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) + +#define writeb(val,addr)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writew(val,addr)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writel(val,addr)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr)) + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(val, addr) writeb(val,addr) +#define outw(val, addr) writew(val,addr) +#define outl(val, addr) writel(val,addr) + +static inline void insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) *p++ = inb (port); +} +static inline void insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) *p++ = inw (port); +} +static inline void insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) *p++ = inl (port); +} + +static inline void outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) outb (*p++, port); +} + +static inline void outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) outw (*p++, port); +} +static inline void outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) outl (*p++, port); +} + +#endif /* __ASM_NIOS2_IO_H_ */ diff --git a/include/asm-nios2/opcodes.h b/arch/nios2/include/asm/opcodes.h similarity index 100% rename from include/asm-nios2/opcodes.h rename to arch/nios2/include/asm/opcodes.h diff --git a/include/asm-nios2/posix_types.h b/arch/nios2/include/asm/posix_types.h similarity index 100% rename from include/asm-nios2/posix_types.h rename to arch/nios2/include/asm/posix_types.h diff --git a/include/asm-nios2/processor.h b/arch/nios2/include/asm/processor.h similarity index 100% rename from include/asm-nios2/processor.h rename to arch/nios2/include/asm/processor.h diff --git a/include/asm-nios2/psr.h b/arch/nios2/include/asm/psr.h similarity index 100% rename from include/asm-nios2/psr.h rename to arch/nios2/include/asm/psr.h diff --git a/include/asm-nios2/ptrace.h b/arch/nios2/include/asm/ptrace.h similarity index 100% rename from include/asm-nios2/ptrace.h rename to arch/nios2/include/asm/ptrace.h diff --git a/include/asm-nios2/status_led.h b/arch/nios2/include/asm/status_led.h similarity index 100% rename from include/asm-nios2/status_led.h rename to arch/nios2/include/asm/status_led.h diff --git a/include/asm-nios2/string.h b/arch/nios2/include/asm/string.h similarity index 100% rename from include/asm-nios2/string.h rename to arch/nios2/include/asm/string.h diff --git a/arch/nios2/include/asm/system.h b/arch/nios2/include/asm/system.h new file mode 100644 index 0000000000..bb03ca5316 --- /dev/null +++ b/arch/nios2/include/asm/system.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_NIOS2_SYSTEM_H_ +#define __ASM_NIOS2_SYSTEM_H_ + +#define local_irq_enable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "ori r8, r8, 1\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_irq_disable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "andi r8, r8, 0xfffe\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_save_flags(x) __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "mov %0, r8\n" \ + : "=r" (x) : : "r8", "memory") + +#define local_irq_restore(x) __asm__ __volatile__ ( \ + "mov r8, %0\n" \ + "wrctl status, r8\n" \ + : : "r" (x) : "r8", "memory") + +/* For spinlocks etc */ +#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \ + while (0) + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ +}) + +#endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/include/asm-nios2/types.h b/arch/nios2/include/asm/types.h similarity index 100% rename from include/asm-nios2/types.h rename to arch/nios2/include/asm/types.h diff --git a/include/asm-nios2/u-boot.h b/arch/nios2/include/asm/u-boot.h similarity index 100% rename from include/asm-nios2/u-boot.h rename to arch/nios2/include/asm/u-boot.h diff --git a/include/asm-nios2/unaligned.h b/arch/nios2/include/asm/unaligned.h similarity index 100% rename from include/asm-nios2/unaligned.h rename to arch/nios2/include/asm/unaligned.h diff --git a/lib_nios2/Makefile b/arch/nios2/lib/Makefile similarity index 100% rename from lib_nios2/Makefile rename to arch/nios2/lib/Makefile diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c new file mode 100644 index 0000000000..8ec66a3540 --- /dev/null +++ b/arch/nios2/lib/board.c @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_STATUS_LED +#include +#endif +#if defined(CONFIG_SYS_NIOS_EPCSBASE) +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ + + +typedef int (init_fnc_t) (void); + + +/************************************************************************ + * Initialization sequence * + ***********************************************************************/ + +init_fnc_t *init_sequence[] = { + +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, /* Call board-specific init code early.*/ +#endif +#if defined(CONFIG_SYS_NIOS_EPCSBASE) + epcs_reset, +#endif + + env_init, + serial_init, + console_init_f, + display_options, + checkcpu, + checkboard, + NULL, /* Terminate this list */ +}; + + +/***********************************************************************/ +void board_init (void) +{ + bd_t *bd; + init_fnc_t **init_fnc_ptr; + + /* Pointer is writable since we allocated a register for it. + * Nios treats CONFIG_SYS_GBL_DATA_OFFSET as an address. + */ + gd = (gd_t *)CONFIG_SYS_GBL_DATA_OFFSET; + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset( gd, 0, CONFIG_SYS_GBL_DATA_SIZE ); + + gd->bd = (bd_t *)(gd+1); /* At end of global data */ + gd->baudrate = CONFIG_BAUDRATE; + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + + bd = gd->bd; + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) + bd->bi_sramstart= CONFIG_SYS_SRAM_BASE; + bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; +#endif + bd->bi_baudrate = CONFIG_BAUDRATE; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + WATCHDOG_RESET (); + if ((*init_fnc_ptr) () != 0) { + hang (); + } + } + + WATCHDOG_RESET (); + + /* The Malloc area is immediately below the monitor copy in RAM */ + mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); + + WATCHDOG_RESET (); + bd->bi_flashsize = flash_init(); + + WATCHDOG_RESET (); + env_relocate(); + + bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + + WATCHDOG_RESET (); + stdio_init(); + jumptable_init(); + console_init_r(); + + WATCHDOG_RESET (); + interrupt_init (); + +#if defined(CONFIG_BOARD_LATE_INIT) + board_late_init (); +#endif + +#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); +#endif + eth_initialize (bd); +#endif + + /* main_loop */ + for (;;) { + WATCHDOG_RESET (); + main_loop (); + } +} + + +/***********************************************************************/ + +void hang (void) +{ + disable_interrupts (); + puts("### ERROR ### Please reset board ###\n"); + for (;;); +} diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c new file mode 100644 index 0000000000..5d25edf80d --- /dev/null +++ b/arch/nios2/lib/bootm.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ + +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + void (*kernel)(int, int, int, char *) = (void *)images->ep; + char *commandline = getenv("bootargs"); + ulong initrd_start = images->rd_start; + ulong initrd_end = images->rd_end; + + if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) + return 1; + + /* flushes data and instruction caches before calling the kernel */ + disable_interrupts(); + flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE); + flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE); + + debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline); + debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end); + kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline); + /* does not return */ + + return 1; +} diff --git a/lib_nios2/cache.S b/arch/nios2/lib/cache.S similarity index 100% rename from lib_nios2/cache.S rename to arch/nios2/lib/cache.S diff --git a/lib_nios2/divmod.c b/arch/nios2/lib/divmod.c similarity index 100% rename from lib_nios2/divmod.c rename to arch/nios2/lib/divmod.c diff --git a/lib_nios2/math.h b/arch/nios2/lib/math.h similarity index 100% rename from lib_nios2/math.h rename to arch/nios2/lib/math.h diff --git a/lib_nios2/mult.c b/arch/nios2/lib/mult.c similarity index 100% rename from lib_nios2/mult.c rename to arch/nios2/lib/mult.c diff --git a/lib_nios2/time.c b/arch/nios2/lib/time.c similarity index 100% rename from lib_nios2/time.c rename to arch/nios2/lib/time.c diff --git a/lib_ppc/config.mk b/arch/ppc/config.mk similarity index 100% rename from lib_ppc/config.mk rename to arch/ppc/config.mk diff --git a/cpu/74xx_7xx/Makefile b/arch/ppc/cpu/74xx_7xx/Makefile similarity index 100% rename from cpu/74xx_7xx/Makefile rename to arch/ppc/cpu/74xx_7xx/Makefile diff --git a/cpu/74xx_7xx/cache.S b/arch/ppc/cpu/74xx_7xx/cache.S similarity index 100% rename from cpu/74xx_7xx/cache.S rename to arch/ppc/cpu/74xx_7xx/cache.S diff --git a/cpu/74xx_7xx/config.mk b/arch/ppc/cpu/74xx_7xx/config.mk similarity index 100% rename from cpu/74xx_7xx/config.mk rename to arch/ppc/cpu/74xx_7xx/config.mk diff --git a/cpu/74xx_7xx/cpu.c b/arch/ppc/cpu/74xx_7xx/cpu.c similarity index 100% rename from cpu/74xx_7xx/cpu.c rename to arch/ppc/cpu/74xx_7xx/cpu.c diff --git a/cpu/74xx_7xx/cpu_init.c b/arch/ppc/cpu/74xx_7xx/cpu_init.c similarity index 100% rename from cpu/74xx_7xx/cpu_init.c rename to arch/ppc/cpu/74xx_7xx/cpu_init.c diff --git a/cpu/74xx_7xx/interrupts.c b/arch/ppc/cpu/74xx_7xx/interrupts.c similarity index 100% rename from cpu/74xx_7xx/interrupts.c rename to arch/ppc/cpu/74xx_7xx/interrupts.c diff --git a/cpu/74xx_7xx/io.S b/arch/ppc/cpu/74xx_7xx/io.S similarity index 100% rename from cpu/74xx_7xx/io.S rename to arch/ppc/cpu/74xx_7xx/io.S diff --git a/cpu/74xx_7xx/kgdb.S b/arch/ppc/cpu/74xx_7xx/kgdb.S similarity index 100% rename from cpu/74xx_7xx/kgdb.S rename to arch/ppc/cpu/74xx_7xx/kgdb.S diff --git a/cpu/74xx_7xx/speed.c b/arch/ppc/cpu/74xx_7xx/speed.c similarity index 100% rename from cpu/74xx_7xx/speed.c rename to arch/ppc/cpu/74xx_7xx/speed.c diff --git a/cpu/74xx_7xx/start.S b/arch/ppc/cpu/74xx_7xx/start.S similarity index 100% rename from cpu/74xx_7xx/start.S rename to arch/ppc/cpu/74xx_7xx/start.S diff --git a/cpu/74xx_7xx/traps.c b/arch/ppc/cpu/74xx_7xx/traps.c similarity index 100% rename from cpu/74xx_7xx/traps.c rename to arch/ppc/cpu/74xx_7xx/traps.c diff --git a/arch/ppc/cpu/mpc512x/Makefile b/arch/ppc/cpu/mpc512x/Makefile new file mode 100644 index 0000000000..1719c66e8d --- /dev/null +++ b/arch/ppc/cpu/mpc512x/Makefile @@ -0,0 +1,63 @@ +# +# (C) Copyright 2007-2009 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +$(shell mkdir -p $(OBJTREE)/board/freescale/common) + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS-y := cpu.o +COBJS-y += traps.o +COBJS-y += cpu_init.o +COBJS-y += fixed_sdram.o +COBJS-y += i2c.o +COBJS-y += interrupts.o +COBJS-y += iopin.o +COBJS-y += serial.o +COBJS-y += speed.o +COBJS-${CONFIG_FSL_DIU_FB} += diu.o +COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_diu_fb.o +COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_logo_bmp.o +COBJS-${CONFIG_CMD_IDE} += ide.o +COBJS-${CONFIG_IIM} += iim.o +COBJS-$(CONFIG_PCI) += pci.o + +COBJS := $(COBJS-y) +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/ppc/cpu/mpc512x/asm-offsets.h b/arch/ppc/cpu/mpc512x/asm-offsets.h new file mode 100644 index 0000000000..5873fe05ec --- /dev/null +++ b/arch/ppc/cpu/mpc512x/asm-offsets.h @@ -0,0 +1,15 @@ +/* + * needed for arch/ppc/cpu/mpc512x/start.S + * + * These should be auto-generated + */ +#define LPCS0AW 0x0024 +#define SRAMBAR 0x00C4 +#define SWCRR 0x0904 +#define LPC_OFFSET 0x10000 +#define CS0_CONFIG 0x00000 +#define CS_CTRL 0x00020 +#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ + +#define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET diff --git a/arch/ppc/cpu/mpc512x/config.mk b/arch/ppc/cpu/mpc512x/config.mk new file mode 100644 index 0000000000..b6727dcd21 --- /dev/null +++ b/arch/ppc/cpu/mpc512x/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2007-2009 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fPIC -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ + -ffixed-r2 -msoft-float -mcpu=603e + +# Use default linker script. +# A board port can override this setting in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc512x/u-boot.lds diff --git a/cpu/mpc512x/cpu.c b/arch/ppc/cpu/mpc512x/cpu.c similarity index 100% rename from cpu/mpc512x/cpu.c rename to arch/ppc/cpu/mpc512x/cpu.c diff --git a/cpu/mpc512x/cpu_init.c b/arch/ppc/cpu/mpc512x/cpu_init.c similarity index 100% rename from cpu/mpc512x/cpu_init.c rename to arch/ppc/cpu/mpc512x/cpu_init.c diff --git a/arch/ppc/cpu/mpc512x/diu.c b/arch/ppc/cpu/mpc512x/diu.c new file mode 100644 index 0000000000..93611615f1 --- /dev/null +++ b/arch/ppc/cpu/mpc512x/diu.c @@ -0,0 +1,188 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * York Sun + * + * FSL DIU Framebuffer driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "../../../../board/freescale/common/fsl_diu_fb.h" + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +#include +#include +#endif + +#ifdef CONFIG_FSL_DIU_LOGO_BMP +extern unsigned int FSL_Logo_BMP[]; +#else +#define FSL_Logo_BMP NULL +#endif + +static int xres, yres; + +void diu_set_pixel_clock(unsigned int pixclock) +{ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile clk512x_t *clk = &immap->clk; + volatile unsigned int *clkdvdr = &clk->scfr[0]; + unsigned long speed_ccb, temp, pixval; + + speed_ccb = get_bus_freq(0) * 4; + temp = 1000000000/pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + debug("DIU: Current value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); + temp = in_be32(clkdvdr) & 0xFFFFFF00; + out_be32(clkdvdr, temp | (pixval & 0xFF)); + debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); +} + +char *valid_bmp(char *addr) +{ + unsigned long h_addr; + + h_addr = simple_strtoul(addr, NULL, 16); + if (h_addr < CONFIG_SYS_FLASH_BASE || + h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) { + printf("bmp addr %lx is not a valid flash address\n", h_addr); + return 0; + } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) { + printf("bmp addr is not a bmp\n"); + return 0; + } else + return (char *)h_addr; +} + +int mpc5121_diu_init(void) +{ + unsigned int pixel_format; + char *bmp = NULL; + char *bmp_env; + + xres = 1024; + yres = 768; + pixel_format = 0x88883316; + + debug("mpc5121_diu_init\n"); + bmp_env = getenv("diu_bmp_addr"); + if (bmp_env) { + bmp = valid_bmp(bmp_env); + } + if (!bmp) + bmp = (char *)FSL_Logo_BMP; + return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp); +} + +int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]) +{ + unsigned int addr; + + if (argc < 2) { + cmd_usage(cmdtp); + return 1; + } + + if (!strncmp(argv[1], "init", 4)) { +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + fsl_diu_clear_screen(); + drv_video_init(); +#else + return mpc5121_diu_init(); +#endif + } else { + addr = simple_strtoul(argv[1], NULL, 16); + fsl_diu_clear_screen(); + fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); + } + + return 0; +} + +U_BOOT_CMD( + diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp, + "Init or Display BMP file", + "init\n - initialize DIU\n" + "addr\n - display bmp at address 'addr'" + ); + + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + +/* + * The Graphic Device + */ +GraphicDevice ctfb; +void *video_hw_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *) &ctfb; + struct fb_info *info; + + if (mpc5121_diu_init() < 0) + return NULL; + + /* fill in Graphic device struct */ + sprintf(pGD->modeIdent, "%dx%dx%d %dkHz %dHz", + xres, yres, 32, 64, 60); + + pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); + pGD->winSizeX = xres; + pGD->winSizeY = yres - info->logo_height; + pGD->plnSizeX = pGD->winSizeX; + pGD->plnSizeY = pGD->winSizeY; + + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + + pGD->isaBase = 0; + pGD->pciBase = 0; + pGD->memSize = info->screen_size - info->logo_size; + + /* Cursor Start Address */ + pGD->dprBase = 0; + pGD->vprBase = 0; + pGD->cprBase = 0; + + return (void *)pGD; +} + +/** + * Set the LUT + * + * @index: color number + * @r: red + * @b: blue + * @g: green + */ +void video_set_lut + (unsigned int index, unsigned char r, unsigned char g, unsigned char b) +{ + return; +} + +#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/cpu/mpc512x/fixed_sdram.c b/arch/ppc/cpu/mpc512x/fixed_sdram.c similarity index 100% rename from cpu/mpc512x/fixed_sdram.c rename to arch/ppc/cpu/mpc512x/fixed_sdram.c diff --git a/cpu/mpc512x/i2c.c b/arch/ppc/cpu/mpc512x/i2c.c similarity index 100% rename from cpu/mpc512x/i2c.c rename to arch/ppc/cpu/mpc512x/i2c.c diff --git a/cpu/mpc512x/ide.c b/arch/ppc/cpu/mpc512x/ide.c similarity index 100% rename from cpu/mpc512x/ide.c rename to arch/ppc/cpu/mpc512x/ide.c diff --git a/cpu/mpc512x/iim.c b/arch/ppc/cpu/mpc512x/iim.c similarity index 100% rename from cpu/mpc512x/iim.c rename to arch/ppc/cpu/mpc512x/iim.c diff --git a/cpu/mpc512x/interrupts.c b/arch/ppc/cpu/mpc512x/interrupts.c similarity index 100% rename from cpu/mpc512x/interrupts.c rename to arch/ppc/cpu/mpc512x/interrupts.c diff --git a/cpu/mpc512x/iopin.c b/arch/ppc/cpu/mpc512x/iopin.c similarity index 100% rename from cpu/mpc512x/iopin.c rename to arch/ppc/cpu/mpc512x/iopin.c diff --git a/cpu/mpc512x/pci.c b/arch/ppc/cpu/mpc512x/pci.c similarity index 100% rename from cpu/mpc512x/pci.c rename to arch/ppc/cpu/mpc512x/pci.c diff --git a/cpu/mpc512x/serial.c b/arch/ppc/cpu/mpc512x/serial.c similarity index 100% rename from cpu/mpc512x/serial.c rename to arch/ppc/cpu/mpc512x/serial.c diff --git a/cpu/mpc512x/speed.c b/arch/ppc/cpu/mpc512x/speed.c similarity index 100% rename from cpu/mpc512x/speed.c rename to arch/ppc/cpu/mpc512x/speed.c diff --git a/cpu/mpc512x/start.S b/arch/ppc/cpu/mpc512x/start.S similarity index 100% rename from cpu/mpc512x/start.S rename to arch/ppc/cpu/mpc512x/start.S diff --git a/cpu/mpc512x/traps.c b/arch/ppc/cpu/mpc512x/traps.c similarity index 100% rename from cpu/mpc512x/traps.c rename to arch/ppc/cpu/mpc512x/traps.c diff --git a/arch/ppc/cpu/mpc512x/u-boot.lds b/arch/ppc/cpu/mpc512x/u-boot.lds new file mode 100644 index 0000000000..fbc2026d53 --- /dev/null +++ b/arch/ppc/cpu/mpc512x/u-boot.lds @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2007 DENX Software Engineering. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + arch/ppc/cpu/mpc512x/start.o (.text) + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/arch/ppc/cpu/mpc5xx/Makefile b/arch/ppc/cpu/mpc5xx/Makefile new file mode 100644 index 0000000000..f2ebb9a123 --- /dev/null +++ b/arch/ppc/cpu/mpc5xx/Makefile @@ -0,0 +1,59 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2003 +# Martin Winistoerfer, martinwinistoerfer@gmx.ch. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# File: arch/ppc/cpu/mpc5xx/Makefile +# +# Discription: Makefile to build mpc5xx cpu configuration. +# Will include top config.mk which itselfs +# uses the definitions made in arch/ppc/cpu/mpc5xx/config.mk +# + + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/ppc/cpu/mpc5xx/config.mk b/arch/ppc/cpu/mpc5xx/config.mk new file mode 100644 index 0000000000..e0b0ce1fd5 --- /dev/null +++ b/arch/ppc/cpu/mpc5xx/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2003 +# Martin Winistoerfer, martinwinistoerfer@gmx.ch. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# File: config.mk +# +# Discription: compiler flags and make definitions +# + + +PLATFORM_RELFLAGS += -fPIC -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xx/u-boot.lds diff --git a/cpu/mpc5xx/cpu.c b/arch/ppc/cpu/mpc5xx/cpu.c similarity index 100% rename from cpu/mpc5xx/cpu.c rename to arch/ppc/cpu/mpc5xx/cpu.c diff --git a/cpu/mpc5xx/cpu_init.c b/arch/ppc/cpu/mpc5xx/cpu_init.c similarity index 100% rename from cpu/mpc5xx/cpu_init.c rename to arch/ppc/cpu/mpc5xx/cpu_init.c diff --git a/cpu/mpc5xx/interrupts.c b/arch/ppc/cpu/mpc5xx/interrupts.c similarity index 100% rename from cpu/mpc5xx/interrupts.c rename to arch/ppc/cpu/mpc5xx/interrupts.c diff --git a/cpu/mpc5xx/serial.c b/arch/ppc/cpu/mpc5xx/serial.c similarity index 100% rename from cpu/mpc5xx/serial.c rename to arch/ppc/cpu/mpc5xx/serial.c diff --git a/cpu/mpc5xx/speed.c b/arch/ppc/cpu/mpc5xx/speed.c similarity index 100% rename from cpu/mpc5xx/speed.c rename to arch/ppc/cpu/mpc5xx/speed.c diff --git a/cpu/mpc5xx/spi.c b/arch/ppc/cpu/mpc5xx/spi.c similarity index 100% rename from cpu/mpc5xx/spi.c rename to arch/ppc/cpu/mpc5xx/spi.c diff --git a/cpu/mpc5xx/start.S b/arch/ppc/cpu/mpc5xx/start.S similarity index 100% rename from cpu/mpc5xx/start.S rename to arch/ppc/cpu/mpc5xx/start.S diff --git a/cpu/mpc5xx/traps.c b/arch/ppc/cpu/mpc5xx/traps.c similarity index 100% rename from cpu/mpc5xx/traps.c rename to arch/ppc/cpu/mpc5xx/traps.c diff --git a/arch/ppc/cpu/mpc5xx/u-boot.lds b/arch/ppc/cpu/mpc5xx/u-boot.lds new file mode 100644 index 0000000000..55190c72d9 --- /dev/null +++ b/arch/ppc/cpu/mpc5xx/u-boot.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + arch/ppc/cpu/mpc5xx/start.o (.text) + + *(.text) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + + _end = . ; + PROVIDE (end = .); +/* . = env_start; + .ppcenv : + { + common/env_embedded.o (.ppcenv) + } +*/ +} diff --git a/arch/ppc/cpu/mpc5xxx/Makefile b/arch/ppc/cpu/mpc5xxx/Makefile new file mode 100644 index 0000000000..0ee0611550 --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +SOBJS = io.o firmware_sc_task_bestcomm.impl.o +COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \ + loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/ppc/cpu/mpc5xxx/config.mk b/arch/ppc/cpu/mpc5xxx/config.mk new file mode 100644 index 0000000000..9a64cb623d --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ + -mstring -mcpu=603e -mmultiple + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds diff --git a/arch/ppc/cpu/mpc5xxx/cpu.c b/arch/ppc/cpu/mpc5xxx/cpu.c new file mode 100644 index 0000000000..b20234d32e --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/cpu.c @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2000-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code for the MPC5xxx CPUs + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_LIBFDT) +#include +#include +#include +#endif + +#if defined(CONFIG_OF_IDE_FIXUP) +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int checkcpu (void) +{ + ulong clock = gd->cpu_clk; + char buf[32]; + uint svr, pvr; + + puts ("CPU: "); + + svr = get_svr(); + pvr = get_pvr(); + + switch (pvr) { + case PVR_5200: + printf("MPC5200"); + break; + case PVR_5200B: + printf("MPC5200B"); + break; + default: + printf("Unknown MPC5xxx"); + break; + } + + printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), + PVR_MAJ(pvr), PVR_MIN(pvr)); + printf (" at %s MHz\n", strmhz (buf, clock)); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +int +do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr; + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* Charge the watchdog timer */ + *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f; + *(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */ + while(1); + + return 1; + +} + +/* ------------------------------------------------------------------------- */ + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + * + */ +unsigned long get_tbclk (void) +{ + ulong tbclk; + + tbclk = (gd->bus_clk + 3L) / 4L; + + return (tbclk); +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) +void ft_cpu_setup(void *blob, bd_t *bd) +{ + int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4; + char * cpu_path = "/cpus/" OF_CPU; +#ifdef CONFIG_MPC5xxx_FEC + uchar enetaddr[6]; + char * eth_path = "/" OF_SOC "/ethernet@3000"; +#endif + + do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); + do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1); + do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency", + bd->bi_busfreq*div, 1); +#ifdef CONFIG_MPC5xxx_FEC + eth_getenv_enetaddr("ethaddr", enetaddr); + do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0); + do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0); +#endif +#if defined(CONFIG_OF_IDE_FIXUP) + if (!ide_device_present(0)) { + /* NO CF card detected -> delete ata node in DTS */ + int nodeoffset = 0; + char nodename[] = "/soc5200@f0000000/ata@3a00"; + + nodeoffset = fdt_path_offset(blob, nodename); + if (nodeoffset >= 0) { + fdt_del_node(blob, nodeoffset); + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror(nodeoffset)); + } + } + +#endif + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} +#endif + +#ifdef CONFIG_BOOTCOUNT_LIMIT + +void bootcount_store (ulong a) +{ + volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB); + + *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a; +} + +ulong bootcount_load (void) +{ + volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB); + + if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) + return 0; + else + return (*save_addr & 0x0000ffff); +} +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + +#ifdef CONFIG_MPC5xxx_FEC +/* Default initializations for FEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +int cpu_eth_init(bd_t *bis) +{ + return mpc5xxx_fec_initialize(bis); +} +#endif + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset(void) +{ + int re_enable = disable_interrupts(); + reset_5xxx_watchdog(); + if (re_enable) enable_interrupts(); +} + +void reset_5xxx_watchdog(void) +{ + volatile struct mpc5xxx_gpt *gpt0 = + (struct mpc5xxx_gpt *) MPC5XXX_GPT; + + /* Trigger TIMER_0 by writing A5 to OCPW */ + clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000); +} +#endif /* CONFIG_WATCHDOG */ diff --git a/arch/ppc/cpu/mpc5xxx/cpu_init.c b/arch/ppc/cpu/mpc5xxx/cpu_init.c new file mode 100644 index 0000000000..9daf3755ac --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/cpu_init.c @@ -0,0 +1,233 @@ +/* + * (C) Copyright 2000-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers. + */ +void cpu_init_f (void) +{ + volatile struct mpc5xxx_mmap_ctl *mm = + (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; + volatile struct mpc5xxx_lpb *lpb = + (struct mpc5xxx_lpb *) MPC5XXX_LPB; + volatile struct mpc5xxx_gpio *gpio = + (struct mpc5xxx_gpio *) MPC5XXX_GPIO; + volatile struct mpc5xxx_xlb *xlb = + (struct mpc5xxx_xlb *) MPC5XXX_XLBARB; +#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) + volatile struct mpc5xxx_cdm *cdm = + (struct mpc5xxx_cdm *) MPC5XXX_CDM; +#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ +#if defined(CONFIG_WATCHDOG) + volatile struct mpc5xxx_gpt *gpt0 = + (struct mpc5xxx_gpt *) MPC5XXX_GPT; +#endif /* CONFIG_WATCHDOG */ + unsigned long addecr = (1 << 25); /* Boot_CS */ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* + * Memory Controller: configure chip selects and enable them + */ +#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE) + out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START)); + out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START, + CONFIG_SYS_BOOTCS_SIZE)); +#endif +#if defined(CONFIG_SYS_BOOTCS_CFG) + out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG); +#endif + +#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) + out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START)); + out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START, + CONFIG_SYS_CS0_SIZE)); + /* CS0 and BOOT_CS cannot be enabled at once. */ + /* addecr |= (1 << 16); */ +#endif +#if defined(CONFIG_SYS_CS0_CFG) + out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG); +#endif + +#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) + out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START)); + out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START, + CONFIG_SYS_CS1_SIZE)); + addecr |= (1 << 17); +#endif +#if defined(CONFIG_SYS_CS1_CFG) + out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG); +#endif + +#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE) + out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START)); + out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START, + CONFIG_SYS_CS2_SIZE)); + addecr |= (1 << 18); +#endif +#if defined(CONFIG_SYS_CS2_CFG) + out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG); +#endif + +#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) + out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START)); + out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START, + CONFIG_SYS_CS3_SIZE)); + addecr |= (1 << 19); +#endif +#if defined(CONFIG_SYS_CS3_CFG) + out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG); +#endif + +#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) + out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START)); + out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START, + CONFIG_SYS_CS4_SIZE)); + addecr |= (1 << 20); +#endif +#if defined(CONFIG_SYS_CS4_CFG) + out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG); +#endif + +#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) + out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START)); + out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START, + CONFIG_SYS_CS5_SIZE)); + addecr |= (1 << 21); +#endif +#if defined(CONFIG_SYS_CS5_CFG) + out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG); +#endif + + addecr |= 1; +#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) + out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START)); + out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START, + CONFIG_SYS_CS6_SIZE)); + addecr |= (1 << 26); +#endif +#if defined(CONFIG_SYS_CS6_CFG) + out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG); +#endif + +#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) + out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START)); + out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START, + CONFIG_SYS_CS7_SIZE)); + addecr |= (1 << 27); +#endif +#if defined(CONFIG_SYS_CS7_CFG) + out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG); +#endif + +#if defined(CONFIG_SYS_CS_BURST) + out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST); +#endif +#if defined(CONFIG_SYS_CS_DEADCYCLE) + out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE); +#endif + + /* Enable chip selects */ + out_be32(&mm->ipbi_ws_ctrl, addecr); + out_be32(&lpb->cs_ctrl, (1 << 24)); + + /* Setup pin multiplexing */ +#if defined(CONFIG_SYS_GPS_PORT_CONFIG) + out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG); +#endif + + /* enable timebase */ + setbits_be32(&xlb->config, (1 << 13)); + + /* Enable snooping for RAM */ + setbits_be32(&xlb->config, (1 << 15)); + out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d); + +#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) + /* Motorola reports IPB should better run at 133 MHz. */ + setbits_be32(&mm->ipbi_ws_ctrl, 1); + /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ + addecr = in_be32(&cdm->cfg); + addecr &= ~0x103; +# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) + /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ + addecr |= 0x01; +# else + /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ + addecr |= 0x02; +# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ + out_be32(&cdm->cfg, addecr); +#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ + /* Configure the XLB Arbiter */ + out_be32(&xlb->master_pri_enable, 0xff); + out_be32(&xlb->master_priority, 0x11111111); + +#if defined(CONFIG_SYS_XLB_PIPELINING) + /* Enable piplining */ + clrbits_be32(&xlb->config, (1 << 31)); +#endif + +#if defined(CONFIG_WATCHDOG) + /* Charge the watchdog timer - prescaler = 64k, count = 64k*/ + out_be32(&gpt0->cir, 0x0000ffff); + out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */ + + reset_5xxx_watchdog(); +#endif /* CONFIG_WATCHDOG */ +} + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r (void) +{ + volatile struct mpc5xxx_intr *intr = + (struct mpc5xxx_intr *) MPC5XXX_ICTL; + + /* mask all interrupts */ + out_be32(&intr->per_mask, 0xffffff00); + setbits_be32(&intr->main_mask, 0x0001ffff); + clrbits_be32(&intr->ctrl, 0x00000f00); + /* route critical ints to normal ints */ + setbits_be32(&intr->ctrl, 0x00000001); + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) + /* load FEC microcode */ + loadtask(0, 2); +#endif + + return (0); +} diff --git a/arch/ppc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/arch/ppc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S new file mode 100644 index 0000000000..00c23121ac --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S @@ -0,0 +1,359 @@ +/* + * Copyright (C) 2001, Software Center, Motorola China. + * + * This file contains microcode for the FEC controller of the MPC5200 CPU. + */ + +#include + +/* sas/sccg, gas target */ +.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ +.section smartdmaTaskTable,"aw",@progbits /* Task tables */ +.align 9 +.globl taskTable +taskTable: +.globl scEthernetRecv_Entry +scEthernetRecv_Entry: /* Task 0 */ +.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ +.long scEthernetRecv_TDT - taskTable + 0x000000a4 +.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ +.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ +.long 0x00000000 +.long 0x00000000 +.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ +.long CONFIG_SYS_MBAR +.globl scEthernetXmit_Entry +scEthernetXmit_Entry: /* Task 1 */ +.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ +.long scEthernetXmit_TDT - taskTable + 0x000000d0 +.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ +.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ +.long 0x00000000 +.long 0x00000000 +.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ +.long CONFIG_SYS_MBAR + + +.globl scEthernetRecv_TDT +scEthernetRecv_TDT: /* Task 0 Descriptor Table */ +.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ +.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ +.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ +.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x010cf04c /* 0020: DRD2B1: var4 = EU3(); EU3(var1,var12) */ +.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ +.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ +.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x018cf04e /* 0030: DRD2B1: var6 = EU3(); EU3(var1,var14) */ +.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x020cf04f /* 0038: DRD2B1: var8 = EU3(); EU3(var1,var15) */ +.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ +.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ +.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ +.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ +.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ +.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ +.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ +.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ +.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ +.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ +.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ +.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ +.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ +.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ +.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x080cf04c /* 00A0: DRD2B1: idx0 = EU3(); EU3(var1,var12) */ +.long 0x000001f8 /* 00A4(:0): NOP */ + + +.globl scEthernetXmit_TDT +scEthernetXmit_TDT: /* Task 1 Descriptor Table */ +.long 0x80024800 /* 0000: LCDEXT: idx0 = 0xf0008800; ; */ +.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ +.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ +.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ +.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x024cf04d /* 0020: DRD2B1: var9 = EU3(); EU3(var1,var13) */ +.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ +.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ +.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ +.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x010cf04e /* 0034: DRD2B1: var4 = EU3(); EU3(var1,var14) */ +.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x014cf04f /* 003C: DRD2B1: var5 = EU3(); EU3(var1,var15) */ +.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x028cf050 /* 0044: DRD2B1: var10 = EU3(); EU3(var1,var16) */ +.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x018cf051 /* 004C: DRD2B1: var6 = EU3(); EU3(var1,var17) */ +.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x01ccf0a1 /* 0058: DRD2B1: var7 = EU3(); EU3(var2,idx1) */ +.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ +.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ +.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ +.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ +.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ +.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ +.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ +.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ +.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ +.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ +.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x60000001 /* 0088: DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */ +.long 0x0c4cfc4d /* 008C: DRD2B1: *idx1 = EU3(); EU3(*idx1,var13) */ +.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ +.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ +.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ +.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ +.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ +.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ +.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ +.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x080cf04d /* 00CC: DRD2B1: idx0 = EU3(); EU3(var1,var13) */ +.long 0x000001f8 /* 00D0(:0): NOP */ + +.align 8 + +.globl scEthernetRecv_VarTab +scEthernetRecv_VarTab: /* Task 0 Variable Table */ +.long 0x00000000 /* var[0] */ +.long 0x00000000 /* var[1] */ +.long 0x00000000 /* var[2] */ +.long 0x00000000 /* var[3] */ +.long 0x00000000 /* var[4] */ +.long 0x00000000 /* var[5] */ +.long 0x00000000 /* var[6] */ +.long 0x00000000 /* var[7] */ +.long 0x00000000 /* var[8] */ +.long (CONFIG_SYS_MBAR + 0x8800) /* var[9] */ +.long 0x00000008 /* var[10] */ +.long 0x0000000c /* var[11] */ +.long 0x80000000 /* var[12] */ +.long 0x00000000 /* var[13] */ +.long 0x10000000 /* var[14] */ +.long 0x20000000 /* var[15] */ +.long 0x000005e4 /* var[16] */ +.long 0x0000000e /* var[17] */ +.long 0x000005e0 /* var[18] */ +.long 0x00000004 /* var[19] */ +.long 0x00000000 /* var[20] */ +.long 0x00000000 /* var[21] */ +.long 0x00000000 /* var[22] */ +.long 0x00000000 /* var[23] */ +.long 0x00000000 /* inc[0] */ +.long 0x60000000 /* inc[1] */ +.long 0x20000001 /* inc[2] */ +.long 0x80000000 /* inc[3] */ +.long 0x40000000 /* inc[4] */ +.long 0x00000000 /* inc[5] */ +.long 0x00000000 /* inc[6] */ +.long 0x00000000 /* inc[7] */ + +.align 8 + +.globl scEthernetXmit_VarTab +scEthernetXmit_VarTab: /* Task 1 Variable Table */ +.long 0x00000000 /* var[0] */ +.long 0x00000000 /* var[1] */ +.long 0x00000000 /* var[2] */ +.long 0x00000000 /* var[3] */ +.long 0x00000000 /* var[4] */ +.long 0x00000000 /* var[5] */ +.long 0x00000000 /* var[6] */ +.long 0x00000000 /* var[7] */ +.long 0x00000000 /* var[8] */ +.long 0x00000000 /* var[9] */ +.long 0x00000000 /* var[10] */ +.long (CONFIG_SYS_MBAR + 0x8800) /* var[11] */ +.long 0x00000000 /* var[12] */ +.long 0x80000000 /* var[13] */ +.long 0x10000000 /* var[14] */ +.long 0x08000000 /* var[15] */ +.long 0x20000000 /* var[16] */ +.long 0x0000ffff /* var[17] */ +.long 0xffffffff /* var[18] */ +.long 0x00000008 /* var[19] */ +.long 0x00000000 /* var[20] */ +.long 0x00000000 /* var[21] */ +.long 0x00000000 /* var[22] */ +.long 0x00000000 /* var[23] */ +.long 0x00000000 /* inc[0] */ +.long 0x60000000 /* inc[1] */ +.long 0x40000000 /* inc[2] */ +.long 0x4000ffff /* inc[3] */ +.long 0xe0000001 /* inc[4] */ +.long 0x80000000 /* inc[5] */ +.long 0x00000000 /* inc[6] */ +.long 0x00000000 /* inc[7] */ + +.align 8 + +.globl scEthernetRecv_FDT +scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x21800000 /* and(), EU# 3 */ +.long 0x21400000 /* andn(), EU# 3 */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 + +.align 8 + +.globl scEthernetXmit_FDT +scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x21800000 /* and(), EU# 3 */ +.long 0x21400000 /* andn(), EU# 3 */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 + + +.globl scEthernetRecv_CSave +scEthernetRecv_CSave: /* Task 0 context save space */ +.space 128, 0x0 + + +.globl scEthernetXmit_CSave +scEthernetXmit_CSave: /* Task 1 context save space */ +.space 128, 0x0 diff --git a/cpu/mpc5xxx/i2c.c b/arch/ppc/cpu/mpc5xxx/i2c.c similarity index 100% rename from cpu/mpc5xxx/i2c.c rename to arch/ppc/cpu/mpc5xxx/i2c.c diff --git a/cpu/mpc5xxx/ide.c b/arch/ppc/cpu/mpc5xxx/ide.c similarity index 100% rename from cpu/mpc5xxx/ide.c rename to arch/ppc/cpu/mpc5xxx/ide.c diff --git a/cpu/mpc5xxx/interrupts.c b/arch/ppc/cpu/mpc5xxx/interrupts.c similarity index 100% rename from cpu/mpc5xxx/interrupts.c rename to arch/ppc/cpu/mpc5xxx/interrupts.c diff --git a/cpu/mpc5xxx/io.S b/arch/ppc/cpu/mpc5xxx/io.S similarity index 100% rename from cpu/mpc5xxx/io.S rename to arch/ppc/cpu/mpc5xxx/io.S diff --git a/cpu/mpc5xxx/loadtask.c b/arch/ppc/cpu/mpc5xxx/loadtask.c similarity index 100% rename from cpu/mpc5xxx/loadtask.c rename to arch/ppc/cpu/mpc5xxx/loadtask.c diff --git a/arch/ppc/cpu/mpc5xxx/pci_mpc5200.c b/arch/ppc/cpu/mpc5xxx/pci_mpc5200.c new file mode 100644 index 0000000000..8268f8afe1 --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/pci_mpc5200.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_PCI) + +#include +#include +#include +#include + +/* System RAM mapped over PCI */ +#define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024) + +/* PCIIWCR bit fields */ +#define IWCR_MEM (0 << 3) +#define IWCR_IO (1 << 3) +#define IWCR_READ (0 << 1) +#define IWCR_READLINE (1 << 1) +#define IWCR_READMULT (2 << 1) +#define IWCR_EN (1 << 0) + +static int mpc5200_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32* value) +{ + *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; + eieio(); + udelay(10); +#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200) + if (dev & 0x00ff0000) { + u32 val; + val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2)); + udelay(10); + val = val << 16; + val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0)); + *value = val; + } else { + *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); + } + udelay(10); +#else + *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); +#endif + eieio(); + *(volatile u32 *)MPC5XXX_PCI_CAR = 0; + udelay(10); + return 0; +} + +static int mpc5200_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; + eieio(); + udelay(10); + out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value); + eieio(); + *(volatile u32 *)MPC5XXX_PCI_CAR = 0; + udelay(10); + return 0; +} + +void pci_mpc5xxx_init (struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEMORY_BUS, + CONFIG_PCI_MEMORY_PHYS, + CONFIG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + pci_register_hose(hose); + + /* GPIO Multiplexing - enable PCI */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15); + + /* Set host bridge as pci master and enable memory decoding */ + *(vu_long *)MPC5XXX_PCI_CMD |= + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + + /* Set maximum latency timer */ + *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800); + + /* Set cache line size */ + *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) | + (CONFIG_SYS_CACHELINE_SIZE / 4); + + /* Map MBAR to PCI space */ + *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR; + *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1; + + /* Map RAM to PCI space */ + *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); + *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1; + + /* Park XLB on PCI */ + *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5)); + *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5); + + /* Disable interrupts from PCI controller */ + *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12); + *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24); + + /* Set PCI retry counter to 0 = infinite retry. */ + /* The default of 255 is too short for slow devices. */ + *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00; + + /* Disable initiator windows */ + *(vu_long *)MPC5XXX_PCI_IWCR = 0; + + /* Map PCI memory to physical space */ + *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS | + (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) | + (CONFIG_PCI_MEM_BUS >> 16); + *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24; + + /* Map PCI I/O to physical space */ + *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS | + (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) | + (CONFIG_PCI_IO_BUS >> 16); + *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16; + + /* Reset the PCI bus */ + *(vu_long *)MPC5XXX_PCI_GSCR |= 1; + udelay(1000); + *(vu_long *)MPC5XXX_PCI_GSCR &= ~1; + udelay(1000); + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + mpc5200_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + mpc5200_write_config_dword); + + udelay(1000); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCI */ diff --git a/arch/ppc/cpu/mpc5xxx/serial.c b/arch/ppc/cpu/mpc5xxx/serial.c new file mode 100644 index 0000000000..66759887c6 --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/serial.c @@ -0,0 +1,363 @@ +/* + * (C) Copyright 2000 - 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with + * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the + * Linux/PPC sources (m8260_tty.c had no copyright info in it). + * + * Martin Krause, 8 Jun 2006 + * Added CONFIG_SERIAL_MULTI support + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include +#include + +#if defined (CONFIG_SERIAL_MULTI) +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PSC_CONSOLE) + +#if CONFIG_PSC_CONSOLE == 1 +#define PSC_BASE MPC5XXX_PSC1 +#elif CONFIG_PSC_CONSOLE == 2 +#define PSC_BASE MPC5XXX_PSC2 +#elif CONFIG_PSC_CONSOLE == 3 +#define PSC_BASE MPC5XXX_PSC3 +#elif CONFIG_PSC_CONSOLE == 4 +#define PSC_BASE MPC5XXX_PSC4 +#elif CONFIG_PSC_CONSOLE == 5 +#define PSC_BASE MPC5XXX_PSC5 +#elif CONFIG_PSC_CONSOLE == 6 +#define PSC_BASE MPC5XXX_PSC6 +#else +#error CONFIG_PSC_CONSOLE must be in 1 ... 6 +#endif + +#if defined(CONFIG_SERIAL_MULTI) && !defined(CONFIG_PSC_CONSOLE2) +#error you must define CONFIG_PSC_CONSOLE2 if CONFIG_SERIAL_MULTI is set +#endif + +#if defined(CONFIG_SERIAL_MULTI) +#if CONFIG_PSC_CONSOLE2 == 1 +#define PSC_BASE2 MPC5XXX_PSC1 +#elif CONFIG_PSC_CONSOLE2 == 2 +#define PSC_BASE2 MPC5XXX_PSC2 +#elif CONFIG_PSC_CONSOLE2 == 3 +#define PSC_BASE2 MPC5XXX_PSC3 +#elif CONFIG_PSC_CONSOLE2 == 4 +#define PSC_BASE2 MPC5XXX_PSC4 +#elif CONFIG_PSC_CONSOLE2 == 5 +#define PSC_BASE2 MPC5XXX_PSC5 +#elif CONFIG_PSC_CONSOLE2 == 6 +#define PSC_BASE2 MPC5XXX_PSC6 +#else +#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6 +#endif +#endif /* CONFIG_SERIAL_MULTI */ + +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init (void) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + unsigned long baseclk; + int div; + + /* reset PSC */ + psc->command = PSC_SEL_MODE_REG_1; + + /* select clock sources */ + psc->psc_clock_select = 0; + baseclk = (gd->ipb_clk + 16) / 32; + + /* switch to UART mode */ + psc->sicr = 0; + + /* configure parity, bit length and so on */ + psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; + psc->mode = PSC_MODE_ONE_STOP; + + /* set up UART divisor */ + div = (baseclk + (gd->baudrate/2)) / gd->baudrate; + psc->ctur = (div >> 8) & 0xff; + psc->ctlr = div & 0xff; + + /* disable all interrupts */ + psc->psc_imr = 0; + + /* reset and enable Rx/Tx */ + psc->command = PSC_RST_RX; + psc->command = PSC_RST_TX; + psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; + + return (0); +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_dev (unsigned long dev_base, const char c) +#else +void serial_putc(const char c) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + if (c == '\n') +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, '\r'); +#else + serial_putc('\r'); +#endif + + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->psc_buffer_8 = c; +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_raw_dev(unsigned long dev_base, const char c) +#else +void serial_putc_raw(const char c) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->psc_buffer_8 = c; +} + + +#if defined(CONFIG_SERIAL_MULTI) +void serial_puts_dev (unsigned long dev_base, const char *s) +#else +void serial_puts (const char *s) +#endif +{ + while (*s) { +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, *s++); +#else + serial_putc (*s++); +#endif + } +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_getc_dev (unsigned long dev_base) +#else +int serial_getc(void) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + /* Wait for a character to arrive. */ + while (!(psc->psc_status & PSC_SR_RXRDY)) + ; + + return psc->psc_buffer_8; +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_tstc_dev (unsigned long dev_base) +#else +int serial_tstc(void) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + return (psc->psc_status & PSC_SR_RXRDY); +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_setbrg_dev (unsigned long dev_base) +#else +void serial_setbrg(void) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + unsigned long baseclk, div; + + baseclk = (gd->ipb_clk + 16) / 32; + + /* set up UART divisor */ + div = (baseclk + (gd->baudrate/2)) / gd->baudrate; + psc->ctur = (div >> 8) & 0xFF; + psc->ctlr = div & 0xff; +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_setrts_dev (unsigned long dev_base, int s) +#else +void serial_setrts(int s) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + if (s) { + /* Assert RTS (become LOW) */ + psc->op1 = 0x1; + } + else { + /* Negate RTS (become HIGH) */ + psc->op0 = 0x1; + } +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_getcts_dev (unsigned long dev_base) +#else +int serial_getcts(void) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + return (psc->ip & 0x1) ? 0 : 1; +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial0_init(void) +{ + return (serial_init_dev(PSC_BASE)); +} + +int serial1_init(void) +{ + return (serial_init_dev(PSC_BASE2)); +} +void serial0_setbrg (void) +{ + serial_setbrg_dev(PSC_BASE); +} +void serial1_setbrg (void) +{ + serial_setbrg_dev(PSC_BASE2); +} + +void serial0_putc(const char c) +{ + serial_putc_dev(PSC_BASE,c); +} + +void serial1_putc(const char c) +{ + serial_putc_dev(PSC_BASE2, c); +} +void serial0_puts(const char *s) +{ + serial_puts_dev(PSC_BASE, s); +} + +void serial1_puts(const char *s) +{ + serial_puts_dev(PSC_BASE2, s); +} + +int serial0_getc(void) +{ + return(serial_getc_dev(PSC_BASE)); +} + +int serial1_getc(void) +{ + return(serial_getc_dev(PSC_BASE2)); +} +int serial0_tstc(void) +{ + return (serial_tstc_dev(PSC_BASE)); +} + +int serial1_tstc(void) +{ + return (serial_tstc_dev(PSC_BASE2)); +} + +struct serial_device serial0_device = +{ + "serial0", + "UART0", + serial0_init, + serial0_setbrg, + serial0_getc, + serial0_tstc, + serial0_putc, + serial0_puts, +}; + +struct serial_device serial1_device = +{ + "serial1", + "UART1", + serial1_init, + serial1_setbrg, + serial1_getc, + serial1_tstc, + serial1_putc, + serial1_puts, +}; +#endif /* CONFIG_SERIAL_MULTI */ + +#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc5xxx/speed.c b/arch/ppc/cpu/mpc5xxx/speed.c similarity index 100% rename from cpu/mpc5xxx/speed.c rename to arch/ppc/cpu/mpc5xxx/speed.c diff --git a/arch/ppc/cpu/mpc5xxx/start.S b/arch/ppc/cpu/mpc5xxx/start.S new file mode 100644 index 0000000000..ba49944210 --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/start.S @@ -0,0 +1,777 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000 - 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot - Startup Code for MPC5xxx CPUs + */ +#include +#include +#include +#include + +#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +/* Floating Point enable, Machine Check and Recoverable Interr. */ +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* + * Set up GOT: Global Offset Table + * + * Use r12 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * Version string + */ + .data + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + +/* + * Exception vectors + */ + .text + . = EXC_OFF_SYS_RESET + .globl _start +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On */ + nop + b boot_cold + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + +boot_cold: +boot_warm: + mfmsr r5 /* save msr contents */ + + /* Move CSBoot and adjust instruction pointer */ + /*--------------------------------------------------------------*/ + +#if defined(CONFIG_SYS_LOWBOOT) +# if defined(CONFIG_SYS_RAMBOOT) +# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT +# endif /* CONFIG_SYS_RAMBOOT */ + lis r4, CONFIG_SYS_DEFAULT_MBAR@h + lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h + ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l + stw r3, 0x4(r4) /* CS0 start */ + lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h + ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l + stw r3, 0x8(r4) /* CS0 stop */ + lis r3, 0x02010000@h + ori r3, r3, 0x02010000@l + stw r3, 0x54(r4) /* CS0 and Boot enable */ + + lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */ + ori r3, r3, lowboot_reentry@l /* to the address space the linker used */ + mtlr r3 + blr + +lowboot_reentry: + lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h + ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l + stw r3, 0x4c(r4) /* Boot start */ + lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h + ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l + stw r3, 0x50(r4) /* Boot stop */ + lis r3, 0x02000001@h + ori r3, r3, 0x02000001@l + stw r3, 0x54(r4) /* Boot enable, CS0 disable */ +#endif /* CONFIG_SYS_LOWBOOT */ + +#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT) + lis r3, CONFIG_SYS_MBAR@h + ori r3, r3, CONFIG_SYS_MBAR@l + /* MBAR is mirrored into the MBAR SPR */ + mtspr MBAR,r3 + rlwinm r3, r3, 16, 16, 31 + lis r4, CONFIG_SYS_DEFAULT_MBAR@h + stw r3, 0(r4) +#endif /* CONFIG_SYS_DEFAULT_MBAR */ + + /* Initialise the MPC5xxx processor core */ + /*--------------------------------------------------------------*/ + + bl init_5xxx_core + + /* initialize some things that are hard to access from C */ + /*--------------------------------------------------------------*/ + + /* set up stack in on-chip SRAM */ + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l + ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*--------------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + bl cpu_init_f /* run low-level CPU init code (in Flash)*/ + + mr r3, r21 + /* r3: BOOTFLAG */ + bl board_init_f /* run 1st part of board init code (in Flash)*/ + +/* + * Vector Table + */ + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) + + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) +#ifdef DEBUG + . = 0x1300 + /* + * This exception occurs when the program counter matches the + * Instruction Address Breakpoint Register (IABR). + * + * I want the cpu to halt if this occurs so I can hunt around + * with the debugger and look at things. + * + * When DEBUG is defined, both machine check enable (in the MSR) + * and checkstop reset enable (in the reset mode register) are + * turned off and so a checkstop condition will result in the cpu + * halting. + * + * I force the cpu into a checkstop condition by putting an illegal + * instruction here (at least this is the theory). + * + * well - that didnt work, so just do an infinite loop! + */ +1: b 1b +#else + STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) +#endif + STD_EXCEPTION(0x1400, SMI, UnknownException) + + STD_EXCEPTION(0x1500, Trap_15, UnknownException) + STD_EXCEPTION(0x1600, Trap_16, UnknownException) + STD_EXCEPTION(0x1700, Trap_17, UnknownException) + STD_EXCEPTION(0x1800, Trap_18, UnknownException) + STD_EXCEPTION(0x1900, Trap_19, UnknownException) + STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) + STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) + STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) + STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) + STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) + STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) + STD_EXCEPTION(0x2000, Trap_20, UnknownException) + STD_EXCEPTION(0x2100, Trap_21, UnknownException) + STD_EXCEPTION(0x2200, Trap_22, UnknownException) + STD_EXCEPTION(0x2300, Trap_23, UnknownException) + STD_EXCEPTION(0x2400, Trap_24, UnknownException) + STD_EXCEPTION(0x2500, Trap_25, UnknownException) + STD_EXCEPTION(0x2600, Trap_26, UnknownException) + STD_EXCEPTION(0x2700, Trap_27, UnknownException) + STD_EXCEPTION(0x2800, Trap_28, UnknownException) + STD_EXCEPTION(0x2900, Trap_29, UnknownException) + STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) + STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) + STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) + STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) + STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) + STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) + + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x3000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* + * This code initialises the MPC5xxx processor core + * (conforms to PowerPC 603e spec) + * Note: expects original MSR contents to be in r5. + */ + + .globl init_5xx_core +init_5xxx_core: + + /* Initialize machine status; enable machine check interrupt */ + /*--------------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ +#endif + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*--------------------------------------------------------------*/ + + lis r3, CONFIG_SYS_HID0_INIT@h + ori r3, r3, CONFIG_SYS_HID0_INIT@l + SYNC + mtspr HID0, r3 + + lis r3, CONFIG_SYS_HID0_FINAL@h + ori r3, r3, CONFIG_SYS_HID0_FINAL@l + SYNC + mtspr HID0, r3 + + /* clear all BAT's */ + /*--------------------------------------------------------------*/ + + li r0, 0 + mtspr DBAT0U, r0 + mtspr DBAT0L, r0 + mtspr DBAT1U, r0 + mtspr DBAT1L, r0 + mtspr DBAT2U, r0 + mtspr DBAT2L, r0 + mtspr DBAT3U, r0 + mtspr DBAT3L, r0 + mtspr DBAT4U, r0 + mtspr DBAT4L, r0 + mtspr DBAT5U, r0 + mtspr DBAT5L, r0 + mtspr DBAT6U, r0 + mtspr DBAT6L, r0 + mtspr DBAT7U, r0 + mtspr DBAT7L, r0 + mtspr IBAT0U, r0 + mtspr IBAT0L, r0 + mtspr IBAT1U, r0 + mtspr IBAT1L, r0 + mtspr IBAT2U, r0 + mtspr IBAT2L, r0 + mtspr IBAT3U, r0 + mtspr IBAT3L, r0 + mtspr IBAT4U, r0 + mtspr IBAT4L, r0 + mtspr IBAT5U, r0 + mtspr IBAT5L, r0 + mtspr IBAT6U, r0 + mtspr IBAT6L, r0 + mtspr IBAT7U, r0 + mtspr IBAT7L, r0 + SYNC + + /* invalidate all tlb's */ + /* */ + /* From the 603e User Manual: "The 603e provides the ability to */ + /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ + /* instruction invalidates the TLB entry indexed by the EA, and */ + /* operates on both the instruction and data TLBs simultaneously*/ + /* invalidating four TLB entries (both sets in each TLB). The */ + /* index corresponds to bits 15-19 of the EA. To invalidate all */ + /* entries within both TLBs, 32 tlbie instructions should be */ + /* issued, incrementing this field by one each time." */ + /* */ + /* "Note that the tlbia instruction is not implemented on the */ + /* 603e." */ + /* */ + /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ + /* incrementing by 0x1000 each time. The code below is sort of */ + /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ + /* */ + /*--------------------------------------------------------------*/ + + li r3, 32 + mtctr r3 + li r3, 0 +1: tlbie r3 + addi r3, r3, 0x1000 + bdnz 1b + SYNC + + /* Done! */ + /*--------------------------------------------------------------*/ + + blr + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ICE + lis r4, 0 + ori r4, r4, HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_disable +icache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_ICE|HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 + blr + + .globl dcache_enable +dcache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_DCE + lis r4, 0 + ori r4, r4, HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_disable +dcache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_DCE|HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 + blr + + .globl get_svr +get_svr: + mfspr r3, SVR + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + GET_GOT + mr r3, r5 /* Destination Address */ + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r12, r12, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ + rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 + cmpwi r7,0 + beq 9f + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ +9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ + rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 + cmpwi r7,0 + beq 7f + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r12 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f + add r0,r0,r11 + stw r0,0(r3) +2: bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ + li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + mflr r4 /* save link register */ + GET_GOT + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mfmsr r3 /* now that the vectors have */ + lis r7, MSR_IP@h /* relocated into low memory */ + ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ + andc r3, r3, r7 /* (if it was on) */ + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + + mtlr r4 /* restore link register */ + blr diff --git a/cpu/mpc5xxx/traps.c b/arch/ppc/cpu/mpc5xxx/traps.c similarity index 100% rename from cpu/mpc5xxx/traps.c rename to arch/ppc/cpu/mpc5xxx/traps.c diff --git a/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds new file mode 100644 index 0000000000..81ebde987f --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + arch/ppc/cpu/mpc5xxx/start.o (.text) + arch/ppc/cpu/mpc5xxx/traps.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.ppcenv) + + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/arch/ppc/cpu/mpc5xxx/u-boot.lds b/arch/ppc/cpu/mpc5xxx/u-boot.lds new file mode 100644 index 0000000000..64ef481297 --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + arch/ppc/cpu/mpc5xxx/start.o (.text) + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc5xxx/usb.c b/arch/ppc/cpu/mpc5xxx/usb.c similarity index 100% rename from cpu/mpc5xxx/usb.c rename to arch/ppc/cpu/mpc5xxx/usb.c diff --git a/arch/ppc/cpu/mpc5xxx/usb_ohci.c b/arch/ppc/cpu/mpc5xxx/usb_ohci.c new file mode 100644 index 0000000000..7976e4df7d --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/usb_ohci.c @@ -0,0 +1,1646 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200. + * + * (C) Copyright 2003-2004 + * Gary Jennejohn, DENX Software Engineering + * + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTES + * 1 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include + +#ifdef CONFIG_USB_OHCI + +#include +#include +#include "usb_ohci.h" + +#include + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ +#undef DEBUG +#undef SHOW_INFO +#undef OHCI_FILL_TRACE + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#define readl(a) (*((volatile u32 *)(a))) +#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +#define ohci_cpu_to_le16(x) (x) +#define ohci_cpu_to_le32(x) (x) + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; +/* flag guarding URB transation */ +int urb_finished = 0; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a (struct ohci *hc) + { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_b (struct ohci *hc) + { return readl (&hc->regs->roothub.b); } +static inline u32 roothub_status (struct ohci *hc) + { return readl (&hc->regs->roothub.status); } +static u32 roothub_portstatus (struct ohci *hc, int i) + { return read_roothub (hc, portstatus [i], 0xffe0fce0); } + + +/* forward declaration */ +static int hc_interrupt (void); +static void +td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv (urb_priv_t * urb) +{ + int i; + int last; + struct td * td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number (struct usb_device * dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, char * str, int small) +{ + urb_priv_t * purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number (dev), + usb_pipedevice (pipe), + usb_pipeendpoint (pipe), + usb_pipeout (pipe)? 'O': 'I', + usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): + (usb_pipecontrol (pipe)? "CTRL": "BULK"), + purb->actual_length, + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol (pipe)) { + printf (__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + printf (" %02x", ((__u8 *) setup) [i]); + printf ("\n"); + } + if (transfer_len > 0 && buffer) { + printf (__FILE__ ": data(%d/%d):", + purb->actual_length, + transfer_len); + len = usb_pipeout (pipe)? + transfer_len: purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf (" %02x", ((__u8 *) buffer) [i]); + printf ("%s\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds (ohci_t *ohci, char * str) { + int i, j; + __u32 * ed_p; + for (i= 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table [i]); + if (*ed_p == 0) + continue; + printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); + printf (" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf ("\n"); + } +} + +static void ohci_dump_intr_mask (char *label, __u32 mask) +{ + dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds (char *label, __u32 value) +{ + ed_t *edp = (ed_t *)value; + + if (value) { + dbg ("%s %08x", label, value); + dbg ("%08x", edp->hwINFO); + dbg ("%08x", edp->hwTailP); + dbg ("%08x", edp->hwHeadP); + dbg ("%08x", edp->hwNextED); + } +} + +static char * hcfs2string (int state) +{ + switch (state) { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status (ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl (®s->revision) & 0xff; + if (temp != 0x10) + dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl (®s->control); + dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string (temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl (®s->cmdstatus); + dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + + ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); + ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); + + maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); + + maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); + maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); + + maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); + maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); + + maybe_print_eds ("donehead", readl (®s->donehead)); +} + +static void ohci_dump_roothub (ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + + if (verbose) { + dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b (controller); + dbg ("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status (controller); + dbg ("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump (ohci_t *controller, int verbose) +{ + dbg ("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status (controller); + if (verbose) + ep_print_int_eds (controller, "hcca"); + dbg ("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub (controller, 1); +} + + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t * ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* if we have an unfinished URB from previous transaction let's + * fail and scream as quickly as possible so as not to corrupt + * further communication */ + if (!urb_finished) { + err("sohci_submit_job: URB NOT FINISHED"); + return -1; + } + /* we're about to begin a new transaction here so mark the URB unfinished */ + urb_finished = 0; + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed (dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype (pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0)? 2: + (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc (dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv (purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv (purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link (ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number (struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return ohci_cpu_to_le16 (ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel (ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel (ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | + (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc (usb_dev); + ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype (pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) + | usb_pipeendpoint (pipe) << 7 + | (usb_pipeisoc (pipe)? 0x8000: 0) + | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) + | usb_pipeslow (pipe) << 13 + | usb_maxpacket (usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill (ohci_t *ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td [index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = ohci_cpu_to_le32 (info); + td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); + if (data) + td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); + else + td->hwBE = 0; + td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ +static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype (pipe)) { + case PIPE_BULK: + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) { + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill (ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout (pipe)? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill (ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t * td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = &urb_priv; + + tdINFO = ohci_cpu_to_le32 (td->hwINFO); + tdBE = ohci_cpu_to_le32 (td->hwBE); + tdCBP = ohci_cpu_to_le32 (td->hwCBP); + + + if (!(usb_pipecontrol(lurb_priv->pipe) && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static td_t * dl_reverse_done_list (ohci_t *ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + urb_priv_t *lurb_priv = NULL; + + td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (td_t *)td_list_hc; + + if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); + if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { + if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { + td_list->ed->hwHeadP = + (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | + (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); + lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; + } else + td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); + } + td_list->hwNextTD = 0; + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; + } + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list (ohci_t *ohci, td_t *td_list) +{ + td_t *td_list_next = NULL; + ed_t *ed; + int cc = 0; + int stat = 0; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET (tdINFO); + if (++(lurb_priv->td_cnt) == lurb_priv->length) { + if ((ed->state & (ED_OPER | ED_UNLINK)) + && (lurb_priv->state != URB_DEL)) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + urb_finished = 1; + } + } + + if (ed->state != ED_NEW) { + edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; + edTailP = ohci_cpu_to_le32 (ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink (ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && + ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void * data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *)datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG +urb_priv.actual_length = 0; +pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#endif + if (usb_pipeint(pipe)) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap (cmd->value); + wIndex = m16_swap (cmd->index); + wLength = m16_swap (cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(__u16 *) data_buf = m16_swap (1); OK (2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *) data_buf = m32_swap ( + RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK (4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_POCI); OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_PESC); OK (0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PRS); + OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PES ); + OK (0); + } + break; + + case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; OK(len); + case (0x03): /* string descriptors */ + if(wValue==0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if(wValue==0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a (&gohci); + + data_buf [0] = 9; /* min length; */ + data_buf [1] = 0x29; + data_buf [2] = temp & RH_A_NDP; + data_buf [3] = 0; + if (temp & RH_A_PSM) /* per-port power switching? */ + data_buf [3] |= 0x1; + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf [3] |= 0x10; + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf [3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab [1] = 0; + data_buf [5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b (&gohci); + data_buf [7] = temp & RH_B_DR; + if (data_buf [2] < 7) { + data_buf [8] = 0xff; + } else { + data_buf [0] += 2; + data_buf [8] = (temp & RH_B_DR) >> 8; + data_buf [10] = data_buf [9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf [0], wLength)); + OK (len); + } + + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + + default: + dbg ("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + + len = min_t(int, len, leni); + if (data != data_buf) + memcpy (data, data_buf, len); + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { + err("sohci_submit_job failed"); + return -1; + } + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipebulk(pipe)) + timeout = BULK_TO; + else + timeout = 100; + + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + + /* NOTE: since we are not interrupt driven in U-Boot and always + * handle only one URB at a time, we cannot assume the + * transaction finished on the first successful return from + * hc_interrupt().. unless the flag for current URB is set, + * meaning that all TD's to/from device got actually + * transferred and processed. If the current URB is not + * finished we need to re-iterate this loop so as + * hc_interrupt() gets called again as there needs to be some + * more TD's to process still */ + if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { + /* 0xff is returned for an SF-interrupt */ + break; + } + + if (--timeout) { + wait_ms(1); + if (!urb_finished) + dbg("\%"); + + } else { + err("CTL:TIMEOUT "); + dbg("submit_common_msg: TO status %x\n", stat); + stat = USB_ST_CRC_ERR; + urb_finished = 1; + break; + } + } +#if 0 + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { +#if 0 /* this does nothing useful, but leave it here in case that changes */ + /* the called routine adds 1 to the passed value */ + usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); +#endif + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } +#endif + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#endif + + /* free TDs in urb_priv */ + urb_free_priv (&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset (ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ + writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + info("USB HC TakeOver from SMM"); + while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { + wait_ms (10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", + ohci->slot_name, + readl (&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + ohci->hc_control = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel (OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay (1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start (ohci_t * ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel (0, &ohci->regs->ed_controlhead); + writel (0, &ohci->regs->ed_bulkhead); + + writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel (fminterval, &ohci->regs->fminterval); + writel (0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel (mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel (mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel (mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel (RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay ((roothub_a (ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int +hc_interrupt (void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) && + !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { + + ints = OHCI_INTR_WDH; + + } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { + ohci->disabled++; + err ("%s device removed!", ohci->slot_name); + return -1; + + } else if ((ints &= readl (®s->intrenable)) == 0) { + dbg("hc_interrupt: returning..\n"); + return 0xff; + } + + /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ + + if (ints & OHCI_INTR_RHSC) { + got_rhsc = 1; + stat = 0xff; + } + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err ("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump (ohci, 1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset (ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + writel (OHCI_INTR_WDH, ®s->intrdisable); + stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); + writel (OHCI_INTR_WDH, ®s->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel (OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; + wait_ms(1); + writel (OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + writel (OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + + writel (ints, ®s->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci (ohci_t *ohci) +{ + dbg ("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset (ohci); +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(void) +{ + + /* Set the USB Clock */ + *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; + +#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */ + /* remove all PSC3 USB bits first before ORing in ours */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00; +#else + /* remove all USB bits first before ORing in ours */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000; +#endif + /* Activate USB port */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG; + + memset (&gohci, 0, sizeof (ohci_t)); + memset (&urb_priv, 0, sizeof (urb_priv_t)); + + /* align the storage */ + if ((__u32)&ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + if ((__u32)&ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); + if ((__u32)gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset (phcca, 0, sizeof (struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)MPC5XXX_USB; + + gohci.flags = 0; + gohci.slot_name = "mpc5200"; + + if (hc_reset (&gohci) < 0) { + hc_release_ohci (&gohci); + return -1; + } + + if (hc_start (&gohci) < 0) { + err ("can't start usb-%s", gohci.slot_name); + hc_release_ohci (&gohci); + return -1; + } + +#ifdef DEBUG + ohci_dump (&gohci, 1); +#endif + ohci_inited = 1; + urb_finished = 1; + + return 0; +} + +int usb_lowlevel_stop(void) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset (&gohci); + return 0; +} + +#endif /* CONFIG_USB_OHCI */ diff --git a/arch/ppc/cpu/mpc5xxx/usb_ohci.h b/arch/ppc/cpu/mpc5xxx/usb_ohci.h new file mode 100644 index 0000000000..629b529a69 --- /dev/null +++ b/arch/ppc/cpu/mpc5xxx/usb_ohci.h @@ -0,0 +1,418 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute__((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute__((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ + __u16 pad1; /* set to 0 on each frame_no change */ + __u16 frame_no; /* current frame number */ + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute__((aligned(256))); + + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute__((aligned(32))); + + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma;*/ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD+1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td * +td_alloc (struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) + { + if (ptd[i].usb_dev == NULL) + { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void +ed_free (struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/cpu/mpc8220/Makefile b/arch/ppc/cpu/mpc8220/Makefile similarity index 100% rename from cpu/mpc8220/Makefile rename to arch/ppc/cpu/mpc8220/Makefile diff --git a/arch/ppc/cpu/mpc8220/config.mk b/arch/ppc/cpu/mpc8220/config.mk new file mode 100644 index 0000000000..e2ebf38bd5 --- /dev/null +++ b/arch/ppc/cpu/mpc8220/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \ + -mstring -mcpu=603e -mmultiple + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8220/u-boot.lds diff --git a/cpu/mpc8220/cpu.c b/arch/ppc/cpu/mpc8220/cpu.c similarity index 100% rename from cpu/mpc8220/cpu.c rename to arch/ppc/cpu/mpc8220/cpu.c diff --git a/cpu/mpc8220/cpu_init.c b/arch/ppc/cpu/mpc8220/cpu_init.c similarity index 100% rename from cpu/mpc8220/cpu_init.c rename to arch/ppc/cpu/mpc8220/cpu_init.c diff --git a/cpu/mpc8220/dma.h b/arch/ppc/cpu/mpc8220/dma.h similarity index 100% rename from cpu/mpc8220/dma.h rename to arch/ppc/cpu/mpc8220/dma.h diff --git a/cpu/mpc8220/dramSetup.c b/arch/ppc/cpu/mpc8220/dramSetup.c similarity index 100% rename from cpu/mpc8220/dramSetup.c rename to arch/ppc/cpu/mpc8220/dramSetup.c diff --git a/cpu/mpc8220/dramSetup.h b/arch/ppc/cpu/mpc8220/dramSetup.h similarity index 100% rename from cpu/mpc8220/dramSetup.h rename to arch/ppc/cpu/mpc8220/dramSetup.h diff --git a/cpu/mpc8220/fec.c b/arch/ppc/cpu/mpc8220/fec.c similarity index 100% rename from cpu/mpc8220/fec.c rename to arch/ppc/cpu/mpc8220/fec.c diff --git a/cpu/mpc8220/fec.h b/arch/ppc/cpu/mpc8220/fec.h similarity index 100% rename from cpu/mpc8220/fec.h rename to arch/ppc/cpu/mpc8220/fec.h diff --git a/cpu/mpc8220/fec_dma_tasks.S b/arch/ppc/cpu/mpc8220/fec_dma_tasks.S similarity index 100% rename from cpu/mpc8220/fec_dma_tasks.S rename to arch/ppc/cpu/mpc8220/fec_dma_tasks.S diff --git a/cpu/mpc8220/i2c.c b/arch/ppc/cpu/mpc8220/i2c.c similarity index 100% rename from cpu/mpc8220/i2c.c rename to arch/ppc/cpu/mpc8220/i2c.c diff --git a/cpu/mpc8220/i2cCore.c b/arch/ppc/cpu/mpc8220/i2cCore.c similarity index 100% rename from cpu/mpc8220/i2cCore.c rename to arch/ppc/cpu/mpc8220/i2cCore.c diff --git a/cpu/mpc8220/i2cCore.h b/arch/ppc/cpu/mpc8220/i2cCore.h similarity index 100% rename from cpu/mpc8220/i2cCore.h rename to arch/ppc/cpu/mpc8220/i2cCore.h diff --git a/cpu/mpc8220/interrupts.c b/arch/ppc/cpu/mpc8220/interrupts.c similarity index 100% rename from cpu/mpc8220/interrupts.c rename to arch/ppc/cpu/mpc8220/interrupts.c diff --git a/cpu/mpc8220/io.S b/arch/ppc/cpu/mpc8220/io.S similarity index 100% rename from cpu/mpc8220/io.S rename to arch/ppc/cpu/mpc8220/io.S diff --git a/cpu/mpc8220/loadtask.c b/arch/ppc/cpu/mpc8220/loadtask.c similarity index 100% rename from cpu/mpc8220/loadtask.c rename to arch/ppc/cpu/mpc8220/loadtask.c diff --git a/cpu/mpc8220/pci.c b/arch/ppc/cpu/mpc8220/pci.c similarity index 100% rename from cpu/mpc8220/pci.c rename to arch/ppc/cpu/mpc8220/pci.c diff --git a/cpu/mpc8220/speed.c b/arch/ppc/cpu/mpc8220/speed.c similarity index 100% rename from cpu/mpc8220/speed.c rename to arch/ppc/cpu/mpc8220/speed.c diff --git a/cpu/mpc8220/start.S b/arch/ppc/cpu/mpc8220/start.S similarity index 100% rename from cpu/mpc8220/start.S rename to arch/ppc/cpu/mpc8220/start.S diff --git a/cpu/mpc8220/traps.c b/arch/ppc/cpu/mpc8220/traps.c similarity index 100% rename from cpu/mpc8220/traps.c rename to arch/ppc/cpu/mpc8220/traps.c diff --git a/arch/ppc/cpu/mpc8220/u-boot.lds b/arch/ppc/cpu/mpc8220/u-boot.lds new file mode 100644 index 0000000000..8c5d3071f9 --- /dev/null +++ b/arch/ppc/cpu/mpc8220/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + arch/ppc/cpu/mpc8220/start.o (.text) + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc8220/uart.c b/arch/ppc/cpu/mpc8220/uart.c similarity index 100% rename from cpu/mpc8220/uart.c rename to arch/ppc/cpu/mpc8220/uart.c diff --git a/cpu/mpc824x/.gitignore b/arch/ppc/cpu/mpc824x/.gitignore similarity index 100% rename from cpu/mpc824x/.gitignore rename to arch/ppc/cpu/mpc824x/.gitignore diff --git a/cpu/mpc824x/Makefile b/arch/ppc/cpu/mpc824x/Makefile similarity index 100% rename from cpu/mpc824x/Makefile rename to arch/ppc/cpu/mpc824x/Makefile diff --git a/arch/ppc/cpu/mpc824x/config.mk b/arch/ppc/cpu/mpc824x/config.mk new file mode 100644 index 0000000000..31ecd20d9f --- /dev/null +++ b/arch/ppc/cpu/mpc824x/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc824x/u-boot.lds diff --git a/cpu/mpc824x/cpu.c b/arch/ppc/cpu/mpc824x/cpu.c similarity index 100% rename from cpu/mpc824x/cpu.c rename to arch/ppc/cpu/mpc824x/cpu.c diff --git a/cpu/mpc824x/cpu_init.c b/arch/ppc/cpu/mpc824x/cpu_init.c similarity index 100% rename from cpu/mpc824x/cpu_init.c rename to arch/ppc/cpu/mpc824x/cpu_init.c diff --git a/cpu/mpc824x/drivers/epic.h b/arch/ppc/cpu/mpc824x/drivers/epic.h similarity index 100% rename from cpu/mpc824x/drivers/epic.h rename to arch/ppc/cpu/mpc824x/drivers/epic.h diff --git a/cpu/mpc824x/drivers/epic/README b/arch/ppc/cpu/mpc824x/drivers/epic/README similarity index 100% rename from cpu/mpc824x/drivers/epic/README rename to arch/ppc/cpu/mpc824x/drivers/epic/README diff --git a/cpu/mpc824x/drivers/epic/epic.h b/arch/ppc/cpu/mpc824x/drivers/epic/epic.h similarity index 100% rename from cpu/mpc824x/drivers/epic/epic.h rename to arch/ppc/cpu/mpc824x/drivers/epic/epic.h diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/arch/ppc/cpu/mpc824x/drivers/epic/epic1.c similarity index 100% rename from cpu/mpc824x/drivers/epic/epic1.c rename to arch/ppc/cpu/mpc824x/drivers/epic/epic1.c diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/arch/ppc/cpu/mpc824x/drivers/epic/epic2.S similarity index 100% rename from cpu/mpc824x/drivers/epic/epic2.S rename to arch/ppc/cpu/mpc824x/drivers/epic/epic2.S diff --git a/cpu/mpc824x/drivers/epic/epicutil.S b/arch/ppc/cpu/mpc824x/drivers/epic/epicutil.S similarity index 100% rename from cpu/mpc824x/drivers/epic/epicutil.S rename to arch/ppc/cpu/mpc824x/drivers/epic/epicutil.S diff --git a/cpu/mpc824x/drivers/errors.h b/arch/ppc/cpu/mpc824x/drivers/errors.h similarity index 100% rename from cpu/mpc824x/drivers/errors.h rename to arch/ppc/cpu/mpc824x/drivers/errors.h diff --git a/cpu/mpc824x/drivers/i2c/i2c.c b/arch/ppc/cpu/mpc824x/drivers/i2c/i2c.c similarity index 100% rename from cpu/mpc824x/drivers/i2c/i2c.c rename to arch/ppc/cpu/mpc824x/drivers/i2c/i2c.c diff --git a/cpu/mpc824x/drivers/i2c_export.h b/arch/ppc/cpu/mpc824x/drivers/i2c_export.h similarity index 100% rename from cpu/mpc824x/drivers/i2c_export.h rename to arch/ppc/cpu/mpc824x/drivers/i2c_export.h diff --git a/cpu/mpc824x/interrupts.c b/arch/ppc/cpu/mpc824x/interrupts.c similarity index 100% rename from cpu/mpc824x/interrupts.c rename to arch/ppc/cpu/mpc824x/interrupts.c diff --git a/cpu/mpc824x/pci.c b/arch/ppc/cpu/mpc824x/pci.c similarity index 100% rename from cpu/mpc824x/pci.c rename to arch/ppc/cpu/mpc824x/pci.c diff --git a/cpu/mpc824x/speed.c b/arch/ppc/cpu/mpc824x/speed.c similarity index 100% rename from cpu/mpc824x/speed.c rename to arch/ppc/cpu/mpc824x/speed.c diff --git a/cpu/mpc824x/start.S b/arch/ppc/cpu/mpc824x/start.S similarity index 100% rename from cpu/mpc824x/start.S rename to arch/ppc/cpu/mpc824x/start.S diff --git a/cpu/mpc824x/traps.c b/arch/ppc/cpu/mpc824x/traps.c similarity index 100% rename from cpu/mpc824x/traps.c rename to arch/ppc/cpu/mpc824x/traps.c diff --git a/arch/ppc/cpu/mpc824x/u-boot.lds b/arch/ppc/cpu/mpc824x/u-boot.lds new file mode 100644 index 0000000000..8a6d5084ec --- /dev/null +++ b/arch/ppc/cpu/mpc824x/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2001-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + arch/ppc/cpu/mpc824x/start.o (.text) + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc8260/Makefile b/arch/ppc/cpu/mpc8260/Makefile similarity index 100% rename from cpu/mpc8260/Makefile rename to arch/ppc/cpu/mpc8260/Makefile diff --git a/cpu/mpc8260/bedbug_603e.c b/arch/ppc/cpu/mpc8260/bedbug_603e.c similarity index 100% rename from cpu/mpc8260/bedbug_603e.c rename to arch/ppc/cpu/mpc8260/bedbug_603e.c diff --git a/cpu/mpc8260/commproc.c b/arch/ppc/cpu/mpc8260/commproc.c similarity index 100% rename from cpu/mpc8260/commproc.c rename to arch/ppc/cpu/mpc8260/commproc.c diff --git a/arch/ppc/cpu/mpc8260/config.mk b/arch/ppc/cpu/mpc8260/config.mk new file mode 100644 index 0000000000..51bb9faf25 --- /dev/null +++ b/arch/ppc/cpu/mpc8260/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ + -mstring -mcpu=603e -mmultiple + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8260/u-boot.lds diff --git a/cpu/mpc8260/cpu.c b/arch/ppc/cpu/mpc8260/cpu.c similarity index 100% rename from cpu/mpc8260/cpu.c rename to arch/ppc/cpu/mpc8260/cpu.c diff --git a/cpu/mpc8260/cpu_init.c b/arch/ppc/cpu/mpc8260/cpu_init.c similarity index 100% rename from cpu/mpc8260/cpu_init.c rename to arch/ppc/cpu/mpc8260/cpu_init.c diff --git a/cpu/mpc8260/ether_fcc.c b/arch/ppc/cpu/mpc8260/ether_fcc.c similarity index 100% rename from cpu/mpc8260/ether_fcc.c rename to arch/ppc/cpu/mpc8260/ether_fcc.c diff --git a/cpu/mpc8260/ether_scc.c b/arch/ppc/cpu/mpc8260/ether_scc.c similarity index 100% rename from cpu/mpc8260/ether_scc.c rename to arch/ppc/cpu/mpc8260/ether_scc.c diff --git a/cpu/mpc8260/i2c.c b/arch/ppc/cpu/mpc8260/i2c.c similarity index 100% rename from cpu/mpc8260/i2c.c rename to arch/ppc/cpu/mpc8260/i2c.c diff --git a/cpu/mpc8260/interrupts.c b/arch/ppc/cpu/mpc8260/interrupts.c similarity index 100% rename from cpu/mpc8260/interrupts.c rename to arch/ppc/cpu/mpc8260/interrupts.c diff --git a/cpu/mpc8260/kgdb.S b/arch/ppc/cpu/mpc8260/kgdb.S similarity index 100% rename from cpu/mpc8260/kgdb.S rename to arch/ppc/cpu/mpc8260/kgdb.S diff --git a/cpu/mpc8260/pci.c b/arch/ppc/cpu/mpc8260/pci.c similarity index 100% rename from cpu/mpc8260/pci.c rename to arch/ppc/cpu/mpc8260/pci.c diff --git a/cpu/mpc8260/serial_scc.c b/arch/ppc/cpu/mpc8260/serial_scc.c similarity index 100% rename from cpu/mpc8260/serial_scc.c rename to arch/ppc/cpu/mpc8260/serial_scc.c diff --git a/cpu/mpc8260/serial_smc.c b/arch/ppc/cpu/mpc8260/serial_smc.c similarity index 100% rename from cpu/mpc8260/serial_smc.c rename to arch/ppc/cpu/mpc8260/serial_smc.c diff --git a/cpu/mpc8260/speed.c b/arch/ppc/cpu/mpc8260/speed.c similarity index 100% rename from cpu/mpc8260/speed.c rename to arch/ppc/cpu/mpc8260/speed.c diff --git a/cpu/mpc8260/speed.h b/arch/ppc/cpu/mpc8260/speed.h similarity index 100% rename from cpu/mpc8260/speed.h rename to arch/ppc/cpu/mpc8260/speed.h diff --git a/cpu/mpc8260/spi.c b/arch/ppc/cpu/mpc8260/spi.c similarity index 100% rename from cpu/mpc8260/spi.c rename to arch/ppc/cpu/mpc8260/spi.c diff --git a/cpu/mpc8260/start.S b/arch/ppc/cpu/mpc8260/start.S similarity index 100% rename from cpu/mpc8260/start.S rename to arch/ppc/cpu/mpc8260/start.S diff --git a/cpu/mpc8260/traps.c b/arch/ppc/cpu/mpc8260/traps.c similarity index 100% rename from cpu/mpc8260/traps.c rename to arch/ppc/cpu/mpc8260/traps.c diff --git a/arch/ppc/cpu/mpc8260/u-boot.lds b/arch/ppc/cpu/mpc8260/u-boot.lds new file mode 100644 index 0000000000..988784416f --- /dev/null +++ b/arch/ppc/cpu/mpc8260/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2001-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + arch/ppc/cpu/mpc8260/start.o (.text) + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc83xx/Makefile b/arch/ppc/cpu/mpc83xx/Makefile similarity index 100% rename from cpu/mpc83xx/Makefile rename to arch/ppc/cpu/mpc83xx/Makefile diff --git a/arch/ppc/cpu/mpc83xx/config.mk b/arch/ppc/cpu/mpc83xx/config.mk new file mode 100644 index 0000000000..8596f6a5e7 --- /dev/null +++ b/arch/ppc/cpu/mpc83xx/config.mk @@ -0,0 +1,29 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \ + -ffixed-r2 -msoft-float + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc83xx/u-boot.lds diff --git a/cpu/mpc83xx/cpu.c b/arch/ppc/cpu/mpc83xx/cpu.c similarity index 100% rename from cpu/mpc83xx/cpu.c rename to arch/ppc/cpu/mpc83xx/cpu.c diff --git a/cpu/mpc83xx/cpu_init.c b/arch/ppc/cpu/mpc83xx/cpu_init.c similarity index 100% rename from cpu/mpc83xx/cpu_init.c rename to arch/ppc/cpu/mpc83xx/cpu_init.c diff --git a/cpu/mpc83xx/ecc.c b/arch/ppc/cpu/mpc83xx/ecc.c similarity index 100% rename from cpu/mpc83xx/ecc.c rename to arch/ppc/cpu/mpc83xx/ecc.c diff --git a/cpu/mpc83xx/fdt.c b/arch/ppc/cpu/mpc83xx/fdt.c similarity index 100% rename from cpu/mpc83xx/fdt.c rename to arch/ppc/cpu/mpc83xx/fdt.c diff --git a/cpu/mpc83xx/interrupts.c b/arch/ppc/cpu/mpc83xx/interrupts.c similarity index 100% rename from cpu/mpc83xx/interrupts.c rename to arch/ppc/cpu/mpc83xx/interrupts.c diff --git a/cpu/mpc83xx/nand_init.c b/arch/ppc/cpu/mpc83xx/nand_init.c similarity index 100% rename from cpu/mpc83xx/nand_init.c rename to arch/ppc/cpu/mpc83xx/nand_init.c diff --git a/cpu/mpc83xx/pci.c b/arch/ppc/cpu/mpc83xx/pci.c similarity index 100% rename from cpu/mpc83xx/pci.c rename to arch/ppc/cpu/mpc83xx/pci.c diff --git a/cpu/mpc83xx/pcie.c b/arch/ppc/cpu/mpc83xx/pcie.c similarity index 100% rename from cpu/mpc83xx/pcie.c rename to arch/ppc/cpu/mpc83xx/pcie.c diff --git a/cpu/mpc83xx/qe_io.c b/arch/ppc/cpu/mpc83xx/qe_io.c similarity index 100% rename from cpu/mpc83xx/qe_io.c rename to arch/ppc/cpu/mpc83xx/qe_io.c diff --git a/cpu/mpc83xx/serdes.c b/arch/ppc/cpu/mpc83xx/serdes.c similarity index 100% rename from cpu/mpc83xx/serdes.c rename to arch/ppc/cpu/mpc83xx/serdes.c diff --git a/cpu/mpc83xx/spd_sdram.c b/arch/ppc/cpu/mpc83xx/spd_sdram.c similarity index 100% rename from cpu/mpc83xx/spd_sdram.c rename to arch/ppc/cpu/mpc83xx/spd_sdram.c diff --git a/cpu/mpc83xx/speed.c b/arch/ppc/cpu/mpc83xx/speed.c similarity index 100% rename from cpu/mpc83xx/speed.c rename to arch/ppc/cpu/mpc83xx/speed.c diff --git a/cpu/mpc83xx/start.S b/arch/ppc/cpu/mpc83xx/start.S similarity index 100% rename from cpu/mpc83xx/start.S rename to arch/ppc/cpu/mpc83xx/start.S diff --git a/cpu/mpc83xx/traps.c b/arch/ppc/cpu/mpc83xx/traps.c similarity index 100% rename from cpu/mpc83xx/traps.c rename to arch/ppc/cpu/mpc83xx/traps.c diff --git a/arch/ppc/cpu/mpc83xx/u-boot.lds b/arch/ppc/cpu/mpc83xx/u-boot.lds new file mode 100644 index 0000000000..157cef676e --- /dev/null +++ b/arch/ppc/cpu/mpc83xx/u-boot.lds @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + arch/ppc/cpu/mpc83xx/start.o (.text) + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/arch/ppc/cpu/mpc85xx/Makefile b/arch/ppc/cpu/mpc85xx/Makefile new file mode 100644 index 0000000000..f064fee26b --- /dev/null +++ b/arch/ppc/cpu/mpc85xx/Makefile @@ -0,0 +1,95 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002,2003 Motorola Inc. +# Xianghua Xiao,X.Xiao@motorola.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o resetvec.o +SOBJS-$(CONFIG_MP) += release.o +SOBJS = $(SOBJS-y) + +COBJS-$(CONFIG_CPM2) += commproc.o + +# supports ddr1 +COBJS-$(CONFIG_MPC8540) += ddr-gen1.o +COBJS-$(CONFIG_MPC8560) += ddr-gen1.o +COBJS-$(CONFIG_MPC8541) += ddr-gen1.o +COBJS-$(CONFIG_MPC8555) += ddr-gen1.o + +# supports ddr1/2 +COBJS-$(CONFIG_MPC8548) += ddr-gen2.o +COBJS-$(CONFIG_MPC8568) += ddr-gen2.o +COBJS-$(CONFIG_MPC8544) += ddr-gen2.o + +# supports ddr1/2/3 +COBJS-$(CONFIG_MPC8572) += ddr-gen3.o +COBJS-$(CONFIG_MPC8536) += ddr-gen3.o +COBJS-$(CONFIG_MPC8569) += ddr-gen3.o +COBJS-$(CONFIG_P1011) += ddr-gen3.o +COBJS-$(CONFIG_P1012) += ddr-gen3.o +COBJS-$(CONFIG_P1013) += ddr-gen3.o +COBJS-$(CONFIG_P1020) += ddr-gen3.o +COBJS-$(CONFIG_P1021) += ddr-gen3.o +COBJS-$(CONFIG_P1022) += ddr-gen3.o +COBJS-$(CONFIG_P2010) += ddr-gen3.o +COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o + +COBJS-$(CONFIG_CPM2) += ether_fcc.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_MP) += mp.o +COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_QE) += qe_io.o +COBJS-$(CONFIG_CPM2) += serial_scc.o + +COBJS = $(COBJS-y) +COBJS += cpu.o +COBJS += cpu_init.o +COBJS += cpu_init_early.o +COBJS += interrupts.o +COBJS += speed.o +COBJS += tlb.o +COBJS += traps.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mpc85xx/commproc.c b/arch/ppc/cpu/mpc85xx/commproc.c similarity index 100% rename from cpu/mpc85xx/commproc.c rename to arch/ppc/cpu/mpc85xx/commproc.c diff --git a/arch/ppc/cpu/mpc85xx/config.mk b/arch/ppc/cpu/mpc85xx/config.mk new file mode 100644 index 0000000000..ffb813dc39 --- /dev/null +++ b/arch/ppc/cpu/mpc85xx/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2002,2003 Motorola Inc. +# Xianghua Xiao, X.Xiao@motorola.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -meabi + +PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string + +# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; +# see "[PATCH,rs6000] make -mno-spe work as expected" on +# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html +PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=yes) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe) + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc85xx/u-boot.lds diff --git a/cpu/mpc85xx/cpu.c b/arch/ppc/cpu/mpc85xx/cpu.c similarity index 100% rename from cpu/mpc85xx/cpu.c rename to arch/ppc/cpu/mpc85xx/cpu.c diff --git a/cpu/mpc85xx/cpu_init.c b/arch/ppc/cpu/mpc85xx/cpu_init.c similarity index 100% rename from cpu/mpc85xx/cpu_init.c rename to arch/ppc/cpu/mpc85xx/cpu_init.c diff --git a/cpu/mpc85xx/cpu_init_early.c b/arch/ppc/cpu/mpc85xx/cpu_init_early.c similarity index 100% rename from cpu/mpc85xx/cpu_init_early.c rename to arch/ppc/cpu/mpc85xx/cpu_init_early.c diff --git a/cpu/mpc85xx/cpu_init_nand.c b/arch/ppc/cpu/mpc85xx/cpu_init_nand.c similarity index 100% rename from cpu/mpc85xx/cpu_init_nand.c rename to arch/ppc/cpu/mpc85xx/cpu_init_nand.c diff --git a/cpu/mpc85xx/ddr-gen1.c b/arch/ppc/cpu/mpc85xx/ddr-gen1.c similarity index 100% rename from cpu/mpc85xx/ddr-gen1.c rename to arch/ppc/cpu/mpc85xx/ddr-gen1.c diff --git a/cpu/mpc85xx/ddr-gen2.c b/arch/ppc/cpu/mpc85xx/ddr-gen2.c similarity index 100% rename from cpu/mpc85xx/ddr-gen2.c rename to arch/ppc/cpu/mpc85xx/ddr-gen2.c diff --git a/cpu/mpc85xx/ddr-gen3.c b/arch/ppc/cpu/mpc85xx/ddr-gen3.c similarity index 100% rename from cpu/mpc85xx/ddr-gen3.c rename to arch/ppc/cpu/mpc85xx/ddr-gen3.c diff --git a/cpu/mpc85xx/ether_fcc.c b/arch/ppc/cpu/mpc85xx/ether_fcc.c similarity index 100% rename from cpu/mpc85xx/ether_fcc.c rename to arch/ppc/cpu/mpc85xx/ether_fcc.c diff --git a/cpu/mpc85xx/fdt.c b/arch/ppc/cpu/mpc85xx/fdt.c similarity index 100% rename from cpu/mpc85xx/fdt.c rename to arch/ppc/cpu/mpc85xx/fdt.c diff --git a/cpu/mpc85xx/fixed_ivor.S b/arch/ppc/cpu/mpc85xx/fixed_ivor.S similarity index 100% rename from cpu/mpc85xx/fixed_ivor.S rename to arch/ppc/cpu/mpc85xx/fixed_ivor.S diff --git a/cpu/mpc85xx/interrupts.c b/arch/ppc/cpu/mpc85xx/interrupts.c similarity index 100% rename from cpu/mpc85xx/interrupts.c rename to arch/ppc/cpu/mpc85xx/interrupts.c diff --git a/cpu/mpc85xx/mp.c b/arch/ppc/cpu/mpc85xx/mp.c similarity index 100% rename from cpu/mpc85xx/mp.c rename to arch/ppc/cpu/mpc85xx/mp.c diff --git a/cpu/mpc85xx/mp.h b/arch/ppc/cpu/mpc85xx/mp.h similarity index 100% rename from cpu/mpc85xx/mp.h rename to arch/ppc/cpu/mpc85xx/mp.h diff --git a/cpu/mpc85xx/mpc8536_serdes.c b/arch/ppc/cpu/mpc85xx/mpc8536_serdes.c similarity index 100% rename from cpu/mpc85xx/mpc8536_serdes.c rename to arch/ppc/cpu/mpc85xx/mpc8536_serdes.c diff --git a/cpu/mpc85xx/pci.c b/arch/ppc/cpu/mpc85xx/pci.c similarity index 100% rename from cpu/mpc85xx/pci.c rename to arch/ppc/cpu/mpc85xx/pci.c diff --git a/cpu/mpc85xx/qe_io.c b/arch/ppc/cpu/mpc85xx/qe_io.c similarity index 100% rename from cpu/mpc85xx/qe_io.c rename to arch/ppc/cpu/mpc85xx/qe_io.c diff --git a/arch/ppc/cpu/mpc85xx/release.S b/arch/ppc/cpu/mpc85xx/release.S new file mode 100644 index 0000000000..0b5b9da032 --- /dev/null +++ b/arch/ppc/cpu/mpc85xx/release.S @@ -0,0 +1,311 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Kumar Gala + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +/* To boot secondary cpus, we need a place for them to start up. + * Normally, they start at 0xfffffffc, but that's usually the + * firmware, and we don't want to have to run the firmware again. + * Instead, the primary cpu will set the BPTR to point here to + * this page. We then set up the core, and head to + * start_secondary. Note that this means that the code below + * must never exceed 1023 instructions (the branch at the end + * would then be the 1024th). + */ + .globl __secondary_start_page + .align 12 +__secondary_start_page: +/* First do some preliminary setup */ + lis r3, HID0_EMCP@h /* enable machine check */ +#ifndef CONFIG_E500MC + ori r3,r3,HID0_TBEN@l /* enable Timebase */ +#endif +#ifdef CONFIG_PHYS_64BIT + ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ +#endif + mtspr SPRN_HID0,r3 + +#ifndef CONFIG_E500MC + li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r0,PVR + andi. r0,r0,0xff + cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r3, r3, HID1_MBDD@l +1: + mtspr SPRN_HID1,r3 +#endif + + /* Enable branch prediction */ + lis r3,BUCSR_ENABLE@h + ori r3,r3,BUCSR_ENABLE@l + mtspr SPRN_BUCSR,r3 + + /* Ensure TB is 0 */ + li r3,0 + mttbl r3 + mttbu r3 + + /* Enable/invalidate the I-Cache */ + lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h + ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l + mtspr SPRN_L1CSR1,r2 +1: + mfspr r3,SPRN_L1CSR1 + and. r1,r3,r2 + bne 1b + + lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h + ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l + mtspr SPRN_L1CSR1,r3 + isync +2: + mfspr r3,SPRN_L1CSR1 + andi. r1,r3,L1CSR1_ICE@l + beq 2b + + /* Enable/invalidate the D-Cache */ + lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h + ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l + mtspr SPRN_L1CSR0,r2 +1: + mfspr r3,SPRN_L1CSR0 + and. r1,r3,r2 + bne 1b + + lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h + ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l + mtspr SPRN_L1CSR0,r3 + isync +2: + mfspr r3,SPRN_L1CSR0 + andi. r1,r3,L1CSR0_DCE@l + beq 2b + +#define toreset(x) (x - __secondary_start_page + 0xfffff000) + + /* get our PIR to figure out our table entry */ + lis r3,toreset(__spin_table)@h + ori r3,r3,toreset(__spin_table)@l + + /* r10 has the base address for the entry */ + mfspr r0,SPRN_PIR +#ifdef CONFIG_E500MC + rlwinm r4,r0,27,27,31 +#else + mr r4,r0 +#endif + slwi r8,r4,5 + add r10,r3,r8 + +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + +#ifdef CONFIG_BACKSIDE_L2_CACHE + /* Enable/invalidate the L2 cache */ + msync + lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l + mtspr SPRN_L2CSR0,r2 +1: + mfspr r3,SPRN_L2CSR0 + and. r1,r3,r2 + bne 1b + +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + addi r3,r8,1 + mtspr SPRN_L2CSR1,r3 +#endif + + lis r3,CONFIG_SYS_INIT_L2CSR0@h + ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l + mtspr SPRN_L2CSR0,r3 + isync +2: + mfspr r3,SPRN_L2CSR0 + andis. r1,r3,L2CSR0_L2E@h + beq 2b +#endif + +#define EPAPR_MAGIC (0x45504150) +#define ENTRY_ADDR_UPPER 0 +#define ENTRY_ADDR_LOWER 4 +#define ENTRY_R3_UPPER 8 +#define ENTRY_R3_LOWER 12 +#define ENTRY_RESV 16 +#define ENTRY_PIR 20 +#define ENTRY_R6_UPPER 24 +#define ENTRY_R6_LOWER 28 +#define ENTRY_SIZE 32 + + /* setup the entry */ + li r3,0 + li r8,1 + stw r0,ENTRY_PIR(r10) + stw r3,ENTRY_ADDR_UPPER(r10) + stw r8,ENTRY_ADDR_LOWER(r10) + stw r3,ENTRY_R3_UPPER(r10) + stw r4,ENTRY_R3_LOWER(r10) + stw r3,ENTRY_R6_UPPER(r10) + stw r3,ENTRY_R6_LOWER(r10) + + /* load r13 with the address of the 'bootpg' in SDRAM */ + lis r13,toreset(__bootpg_addr)@h + ori r13,r13,toreset(__bootpg_addr)@l + lwz r13,0(r13) + + /* setup mapping for AS = 1, and jump there */ + lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h + mtspr SPRN_MAS0,r11 + lis r11,(MAS1_VALID|MAS1_IPROT)@h + ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l + mtspr SPRN_MAS1,r11 + oris r11,r13,(MAS2_I|MAS2_G)@h + ori r11,r13,(MAS2_I|MAS2_G)@l + mtspr SPRN_MAS2,r11 + oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h + ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l + mtspr SPRN_MAS3,r11 + tlbwe + + bl 1f +1: mflr r11 + /* + * OR in 0xfff to create a mask of the bootpg SDRAM address. We use + * this mask to fixup the cpu spin table and the address that we want + * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the + * bootpg is at 0x7ffff000 in SDRAM. + */ + ori r13,r13,0xfff + and r11, r11, r13 + and r10, r10, r13 + + addi r11,r11,(2f-1b) + mfmsr r13 + ori r12,r13,MSR_IS|MSR_DS@l + + mtspr SPRN_SRR0,r11 + mtspr SPRN_SRR1,r12 + rfi + + /* spin waiting for addr */ +2: + lwz r4,ENTRY_ADDR_LOWER(r10) + andi. r11,r4,1 + bne 2b + isync + + /* setup IVORs to match fixed offsets */ +#include "fixed_ivor.S" + + /* get the upper bits of the addr */ + lwz r11,ENTRY_ADDR_UPPER(r10) + + /* setup branch addr */ + mtspr SPRN_SRR0,r4 + + /* mark the entry as released */ + li r8,3 + stw r8,ENTRY_ADDR_LOWER(r10) + + /* mask by ~64M to setup our tlb we will jump to */ + rlwinm r12,r4,0,0,5 + + /* setup r3, r4, r5, r6, r7, r8, r9 */ + lwz r3,ENTRY_R3_LOWER(r10) + li r4,0 + li r5,0 + lwz r6,ENTRY_R6_LOWER(r10) + lis r7,(64*1024*1024)@h + li r8,0 + li r9,0 + + /* load up the pir */ + lwz r0,ENTRY_PIR(r10) + mtspr SPRN_PIR,r0 + mfspr r0,SPRN_PIR + stw r0,ENTRY_PIR(r10) + + mtspr IVPR,r12 +/* + * Coming here, we know the cpu has one TLB mapping in TLB1[0] + * which maps 0xfffff000-0xffffffff one-to-one. We set up a + * second mapping that maps addr 1:1 for 64M, and then we jump to + * addr + */ + lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h + mtspr SPRN_MAS0,r10 + lis r10,(MAS1_VALID|MAS1_IPROT)@h + ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l + mtspr SPRN_MAS1,r10 + /* WIMGE = 0b00000 for now */ + mtspr SPRN_MAS2,r12 + ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) + mtspr SPRN_MAS3,r12 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr SPRN_MAS7,r11 +#endif + tlbwe + +/* Now we have another mapping for this page, so we jump to that + * mapping + */ + mtspr SPRN_SRR1,r13 + rfi + + /* + * Allocate some space for the SDRAM address of the bootpg. + * This variable has to be in the boot page so that it can + * be accessed by secondary cores when they come out of reset. + */ + .globl __bootpg_addr +__bootpg_addr: + .long 0 + + .align L1_CACHE_SHIFT + .globl __spin_table +__spin_table: + .space CONFIG_MAX_CPUS*ENTRY_SIZE + + /* Fill in the empty space. The actual reset vector is + * the last word of the page */ +__secondary_start_code_end: + .space 4092 - (__secondary_start_code_end - __secondary_start_page) +__secondary_reset_vector: + b __secondary_start_page diff --git a/cpu/mpc85xx/resetvec.S b/arch/ppc/cpu/mpc85xx/resetvec.S similarity index 100% rename from cpu/mpc85xx/resetvec.S rename to arch/ppc/cpu/mpc85xx/resetvec.S diff --git a/cpu/mpc85xx/serial_scc.c b/arch/ppc/cpu/mpc85xx/serial_scc.c similarity index 100% rename from cpu/mpc85xx/serial_scc.c rename to arch/ppc/cpu/mpc85xx/serial_scc.c diff --git a/cpu/mpc85xx/speed.c b/arch/ppc/cpu/mpc85xx/speed.c similarity index 100% rename from cpu/mpc85xx/speed.c rename to arch/ppc/cpu/mpc85xx/speed.c diff --git a/arch/ppc/cpu/mpc85xx/start.S b/arch/ppc/cpu/mpc85xx/start.S new file mode 100644 index 0000000000..b3cb56a5b0 --- /dev/null +++ b/arch/ppc/cpu/mpc85xx/start.S @@ -0,0 +1,1195 @@ +/* + * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. + * Copyright (C) 2003 Motorola,Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards + * + * The processor starts at 0xfffffffc and the code is first executed in the + * last 4K page(0xfffff000-0xffffffff) in flash/rom. + * + */ + +#include +#include +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#undef MSR_KERNEL +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ + +/* + * Set up GOT: Global Offset Table + * + * Use r12 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + +#ifndef CONFIG_NAND_SPL + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) +#endif + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * e500 Startup -- after reset only the last 4KB of the effective + * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg + * section is located at THIS LAST page and basically does three + * things: clear some registers, set up exception tables and + * add more TLB entries for 'larger spaces'(e.g. the boot rom) to + * continue the boot procedure. + + * Once the boot rom is mapped by TLB entries we can proceed + * with normal startup. + * + */ + + .section .bootpg,"ax" + .globl _start_e500 + +_start_e500: + +/* clear registers/arrays not reset by hardware */ + + /* L1 */ + li r0,2 + mtspr L1CSR0,r0 /* invalidate d-cache */ + mtspr L1CSR1,r0 /* invalidate i-cache */ + + mfspr r1,DBSR + mtspr DBSR,r1 /* Clear all valid bits */ + + /* + * Enable L1 Caches early + * + */ + +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + li r2,(32 + 0) + mtspr L1CSR2,r2 +#endif + + /* Enable/invalidate the I-Cache */ + lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h + ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l + mtspr SPRN_L1CSR1,r2 +1: + mfspr r3,SPRN_L1CSR1 + and. r1,r3,r2 + bne 1b + + lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h + ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l + mtspr SPRN_L1CSR1,r3 + isync +2: + mfspr r3,SPRN_L1CSR1 + andi. r1,r3,L1CSR1_ICE@l + beq 2b + + /* Enable/invalidate the D-Cache */ + lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h + ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l + mtspr SPRN_L1CSR0,r2 +1: + mfspr r3,SPRN_L1CSR0 + and. r1,r3,r2 + bne 1b + + lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h + ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l + mtspr SPRN_L1CSR0,r3 + isync +2: + mfspr r3,SPRN_L1CSR0 + andi. r1,r3,L1CSR0_DCE@l + beq 2b + + /* Setup interrupt vectors */ + lis r1,TEXT_BASE@h + mtspr IVPR,r1 + + li r1,0x0100 + mtspr IVOR0,r1 /* 0: Critical input */ + li r1,0x0200 + mtspr IVOR1,r1 /* 1: Machine check */ + li r1,0x0300 + mtspr IVOR2,r1 /* 2: Data storage */ + li r1,0x0400 + mtspr IVOR3,r1 /* 3: Instruction storage */ + li r1,0x0500 + mtspr IVOR4,r1 /* 4: External interrupt */ + li r1,0x0600 + mtspr IVOR5,r1 /* 5: Alignment */ + li r1,0x0700 + mtspr IVOR6,r1 /* 6: Program check */ + li r1,0x0800 + mtspr IVOR7,r1 /* 7: floating point unavailable */ + li r1,0x0900 + mtspr IVOR8,r1 /* 8: System call */ + /* 9: Auxiliary processor unavailable(unsupported) */ + li r1,0x0a00 + mtspr IVOR10,r1 /* 10: Decrementer */ + li r1,0x0b00 + mtspr IVOR11,r1 /* 11: Interval timer */ + li r1,0x0c00 + mtspr IVOR12,r1 /* 12: Watchdog timer */ + li r1,0x0d00 + mtspr IVOR13,r1 /* 13: Data TLB error */ + li r1,0x0e00 + mtspr IVOR14,r1 /* 14: Instruction TLB error */ + li r1,0x0f00 + mtspr IVOR15,r1 /* 15: Debug */ + + /* Clear and set up some registers. */ + li r0,0x0000 + lis r1,0xffff + mtspr DEC,r0 /* prevent dec exceptions */ + mttbl r0 /* prevent fit & wdt exceptions */ + mttbu r0 + mtspr TSR,r1 /* clear all timer exception status */ + mtspr TCR,r0 /* disable all */ + mtspr ESR,r0 /* clear exception syndrome register */ + mtspr MCSR,r0 /* machine check syndrome register */ + mtxer r0 /* clear integer exception register */ + +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r0 /* make sure MAS8 is clear */ +#endif + + /* Enable Time Base and Select Time Base Clock */ + lis r0,HID0_EMCP@h /* Enable machine check */ +#if defined(CONFIG_ENABLE_36BIT_PHYS) + ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ +#endif +#ifndef CONFIG_E500MC + ori r0,r0,HID0_TBEN@l /* Enable Timebase */ +#endif + mtspr HID0,r0 + +#ifndef CONFIG_E500MC + li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r3,PVR + andi. r3,r3, 0xff + cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r0, r0, HID1_MBDD@l +1: + mtspr HID1,r0 +#endif + + /* Enable Branch Prediction */ +#if defined(CONFIG_BTB) + lis r0,BUCSR_ENABLE@h + ori r0,r0,BUCSR_ENABLE@l + mtspr SPRN_BUCSR,r0 +#endif + +#if defined(CONFIG_SYS_INIT_DBCR) + lis r1,0xffff + ori r1,r1,0xffff + mtspr DBSR,r1 /* Clear all status bits */ + lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CONFIG_SYS_INIT_DBCR@l + mtspr DBCR0,r0 +#endif + +#ifdef CONFIG_MPC8569 +#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) +#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) + + /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to + * use address space which is more than 12bits, and it must be done in + * the 4K boot page. So we set this bit here. + */ + + /* create a temp mapping TLB0[0] for LBCR */ + lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + /* Set LBCR register */ + lis r4,CONFIG_SYS_LBCR_ADDR@h + ori r4,r4,CONFIG_SYS_LBCR_ADDR@l + + lis r5,CONFIG_SYS_LBC_LBCR@h + ori r5,r5,CONFIG_SYS_LBC_LBCR@l + stw r5,0(r4) + isync + + /* invalidate this temp TLB */ + lis r4,CONFIG_SYS_LBC_ADDR@h + ori r4,r4,CONFIG_SYS_LBC_ADDR@l + tlbivax 0,r4 + isync + +#endif /* CONFIG_MPC8569 */ + + lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l + +#ifndef CONFIG_SYS_RAMBOOT + /* create a temp mapping in AS=1 to the 4M boot window */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l + + lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l + + /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ + lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else + /* + * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main + * image has been relocated to TEXT_BASE on the second stage. + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l + + lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + /* create a temp mapping in AS=1 to the stack */ + lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + lis r6,MSR_IS|MSR_DS@h + ori r6,r6,MSR_IS|MSR_DS@l + lis r7,switch_as@h + ori r7,r7,switch_as@l + + mtspr SPRN_SRR0,r7 + mtspr SPRN_SRR1,r6 + rfi + +switch_as: +/* L1 DCache is used for initial RAM */ + + /* Allocate Initial RAM in data cache. + */ + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + mfspr r2, L1CFG0 + andi. r2, r2, 0x1ff + /* cache size * 1024 / (2 * L1 line size) */ + slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) + mtctr r2 + li r0,0 +1: + dcbz r0,r3 + dcbtls 0,r0,r3 + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE + bdnz 1b + + /* Jump out the last 4K page and continue to 'normal' start */ +#ifdef CONFIG_SYS_RAMBOOT + b _start_cont +#else + /* Calculate absolute address in FLASH and jump there */ + /*--------------------------------------------------------------*/ + lis r3,CONFIG_SYS_MONITOR_BASE@h + ori r3,r3,CONFIG_SYS_MONITOR_BASE@l + addi r3,r3,_start_cont - _start + _START_OFFSET + mtlr r3 + blr +#endif + + .text + .globl _start +_start: + .long 0x27051956 /* U-BOOT Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + .align 4 + .globl _start_cont +_start_cont: + /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ + lis r1,CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l + + li r0,0 + stwu r0,-4(r1) + stwu r0,-4(r1) /* Terminate call chain */ + + stwu r1,-8(r1) /* Save back chain and move SP */ + lis r0,RESET_VECTOR@h /* Address of reset vector */ + ori r0,r0,RESET_VECTOR@l + stwu r1,-8(r1) /* Save back chain and move SP */ + stw r0,+12(r1) /* Save return addr (underflow vect) */ + + GET_GOT + bl cpu_init_early_f + + /* switch back to AS = 0 */ + lis r3,(MSR_CE|MSR_ME|MSR_DE)@h + ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l + mtmsr r3 + isync + + bl cpu_init_f + bl board_init_f + isync + +#ifndef CONFIG_NAND_SPL + . = EXC_OFF_SYS_RESET + .globl _start_of_vectors +_start_of_vectors: + +/* Critical input. */ + CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) + +/* Machine check */ + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x0300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x0400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) + +/* Alignment exception. */ + . = 0x0600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) + +/* Program check exception */ + . = 0x0700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) + + /* No FPU on MPC85xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) + + . = 0x0900 +/* + * r0 - SYSCALL number + * r3-... arguments + */ +SystemCall: + addis r11,r0,0 /* get functions table addr */ + ori r11,r11,0 /* Note: this code is patched in trap_init */ + addis r12,r0,0 /* get number of functions */ + ori r12,r12,0 + + cmplw 0,r0,r12 + bge 1f + + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ + add r11,r11,r0 + lwz r11,0(r11) + + li r20,0xd00-4 /* Get stack pointer */ + lwz r12,0(r20) + subi r12,r12,12 /* Adjust stack pointer */ + li r0,0xc00+_end_back-SystemCall + cmplw 0,r0,r12 /* Check stack overflow */ + bgt 1f + stw r12,0(r20) + + mflr r0 + stw r0,0(r12) + mfspr r0,SRR0 + stw r0,4(r12) + mfspr r0,SRR1 + stw r0,8(r12) + + li r12,0xc00+_back-SystemCall + mtlr r12 + mtspr SRR0,r11 + +1: SYNC + rfi +_back: + + mfmsr r11 /* Disable interrupts */ + li r12,0 + ori r12,r12,MSR_EE + andc r11,r11,r12 + SYNC /* Some chip revs need this... */ + mtmsr r11 + SYNC + + li r12,0xd00-4 /* restore regs */ + lwz r12,0(r12) + + lwz r11,0(r12) + mtlr r11 + lwz r11,4(r12) + mtspr SRR0,r11 + lwz r11,8(r12) + mtspr SRR1,r11 + + addi r12,r12,12 /* Adjust stack pointer */ + li r20,0xd00-4 + stw r12,0(r20) + + SYNC + rfi +_end_back: + + STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) + STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) + STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) + + STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) + STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) + + CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) + + .globl _end_of_vectors +_end_of_vectors: + + + . = . + (0x100 - ( . & 0xff )) /* align for debug */ + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +crit_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SPRN_CSRR0,r2 + mtspr SPRN_CSRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfci + +mck_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SPRN_MCSRR0,r2 + mtspr SPRN_MCSRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfmci + +/* Cache functions. +*/ +.globl invalidate_icache +invalidate_icache: + mfspr r0,L1CSR1 + ori r0,r0,L1CSR1_ICFI + msync + isync + mtspr L1CSR1,r0 + isync + blr /* entire I cache */ + +.globl invalidate_dcache +invalidate_dcache: + mfspr r0,L1CSR0 + ori r0,r0,L1CSR0_DCFI + msync + isync + mtspr L1CSR0,r0 + isync + blr + + .globl icache_enable +icache_enable: + mflr r8 + bl invalidate_icache + mtlr r8 + isync + mfspr r4,L1CSR1 + ori r4,r4,0x0001 + oris r4,r4,0x0001 + mtspr L1CSR1,r4 + isync + blr + + .globl icache_disable +icache_disable: + mfspr r0,L1CSR1 + lis r3,0 + ori r3,r3,L1CSR1_ICE + andc r0,r0,r3 + mtspr L1CSR1,r0 + isync + blr + + .globl icache_status +icache_status: + mfspr r3,L1CSR1 + andi. r3,r3,L1CSR1_ICE + blr + + .globl dcache_enable +dcache_enable: + mflr r8 + bl invalidate_dcache + mtlr r8 + isync + mfspr r0,L1CSR0 + ori r0,r0,0x0001 + oris r0,r0,0x0001 + msync + isync + mtspr L1CSR0,r0 + isync + blr + + .globl dcache_disable +dcache_disable: + mfspr r3,L1CSR0 + lis r4,0 + ori r4,r4,L1CSR0_DCE + andc r3,r3,r4 + mtspr L1CSR0,r0 + isync + blr + + .globl dcache_status +dcache_status: + mfspr r3,L1CSR0 + andi. r3,r3,L1CSR0_DCE + blr + + .globl get_pir +get_pir: + mfspr r3,PIR + blr + + .globl get_pvr +get_pvr: + mfspr r3,PVR + blr + + .globl get_svr +get_svr: + mfspr r3,SVR + blr + + .globl wr_tcr +wr_tcr: + mtspr TCR,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0x0000(r3) + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0x0000(r3) + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,r0,r3 + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0x0000(r3) + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,r0,r3 + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,r0,r3 + blr +#endif /* !CONFIG_NAND_SPL */ + +/*------------------------------------------------------------------------------*/ + +/* + * void write_tlb(mas0, mas1, mas2, mas3, mas7) + */ + .globl write_tlb +write_tlb: + mtspr MAS0,r3 + mtspr MAS1,r4 + mtspr MAS2,r5 + mtspr MAS3,r6 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr MAS7,r7 +#endif + li r3,0 +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r3 +#endif + isync + tlbwe + msync + isync + blr + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1,r3 /* Set new stack pointer */ + mr r9,r4 /* Save copy of Init Data pointer */ + mr r10,r5 /* Save copy of Destination Address */ + + GET_GOT + mr r3,r5 /* Destination Address */ + lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4,r4,CONFIG_SYS_MONITOR_BASE@l + lwz r5,GOT(__init_end) + sub r5,r5,r4 + li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15,r10,r4 + + /* First our own GOT */ + add r12,r12,r15 + /* the the one used by the C code */ + add r30,r30,r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0,r10,in_ram - _start + _START_OFFSET + mtlr r0 + blr /* NEVER RETURNS! */ + .globl in_ram +in_ram: + + /* + * Relocation Function, r12 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f + add r0,r0,r11 + stw r0,0(r3) +2: bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ + li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0,r3,r4 + beq 6f + + li r0,0 +5: + stw r0,0(r3) + addi r3,r3,4 + cmplw 0,r3,r4 + bne 5b +6: + + mr r3,r9 /* Init Data pointer */ + mr r4,r10 /* Destination Address */ + bl board_init_r + +#ifndef CONFIG_NAND_SPL + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + mflr r4 /* save link register */ + GET_GOT + lwz r7,GOT(_start_of_vectors) + lwz r8,GOT(_end_of_vectors) + + li r9,0x100 /* reset vector always at 0x100 */ + + cmplw 0,r7,r8 + bgelr /* return if r7>=r8 - just in case */ +1: + lwz r0,0(r7) + stw r0,0(r9) + addi r7,r7,4 + addi r9,r9,4 + cmplw 0,r7,r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7,.L_CriticalInput - _start + _START_OFFSET + bl trap_reloc + li r7,.L_MachineCheck - _start + _START_OFFSET + bl trap_reloc + li r7,.L_DataStorage - _start + _START_OFFSET + bl trap_reloc + li r7,.L_InstStorage - _start + _START_OFFSET + bl trap_reloc + li r7,.L_ExtInterrupt - _start + _START_OFFSET + bl trap_reloc + li r7,.L_Alignment - _start + _START_OFFSET + bl trap_reloc + li r7,.L_ProgramCheck - _start + _START_OFFSET + bl trap_reloc + li r7,.L_FPUnavailable - _start + _START_OFFSET + bl trap_reloc + li r7,.L_Decrementer - _start + _START_OFFSET + bl trap_reloc + li r7,.L_IntervalTimer - _start + _START_OFFSET + li r8,_end_of_vectors - _start + _START_OFFSET +2: + bl trap_reloc + addi r7,r7,0x100 /* next exception vector */ + cmplw 0,r7,r8 + blt 2b + + lis r7,0x0 + mtspr IVPR,r7 + + mtlr r4 /* restore link register */ + blr + +.globl unlock_ram_in_cache +unlock_ram_in_cache: + /* invalidate the INIT_RAM section */ + lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h + ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l + mfspr r4,L1CFG0 + andi. r4,r4,0x1ff + slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) + mtctr r4 +1: dcbi r0,r3 + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE + bdnz 1b + sync + + /* Invalidate the TLB entries for the cache */ + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + isync + blr + +.globl flush_dcache +flush_dcache: + mfspr r3,SPRN_L1CFG0 + + rlwinm r5,r3,9,3 /* Extract cache block size */ + twlgti r5,1 /* Only 32 and 64 byte cache blocks + * are currently defined. + */ + li r4,32 + subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - + * log2(number of ways) + */ + slw r5,r4,r5 /* r5 = cache block size */ + + rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ + mulli r7,r7,13 /* An 8-way cache will require 13 + * loads per set. + */ + slw r7,r7,r6 + + /* save off HID0 and set DCFA */ + mfspr r8,SPRN_HID0 + ori r9,r8,HID0_DCFA@l + mtspr SPRN_HID0,r9 + isync + + lis r4,0 + mtctr r7 + +1: lwz r3,0(r4) /* Load... */ + add r4,r4,r5 + bdnz 1b + + msync + lis r4,0 + mtctr r7 + +1: dcbf 0,r4 /* ...and flush. */ + add r4,r4,r5 + bdnz 1b + + /* restore HID0 */ + mtspr SPRN_HID0,r8 + isync + + blr + +.globl setup_ivors +setup_ivors: + +#include "fixed_ivor.S" + blr +#endif /* !CONFIG_NAND_SPL */ diff --git a/cpu/mpc85xx/tlb.c b/arch/ppc/cpu/mpc85xx/tlb.c similarity index 100% rename from cpu/mpc85xx/tlb.c rename to arch/ppc/cpu/mpc85xx/tlb.c diff --git a/cpu/mpc85xx/traps.c b/arch/ppc/cpu/mpc85xx/traps.c similarity index 100% rename from cpu/mpc85xx/traps.c rename to arch/ppc/cpu/mpc85xx/traps.c diff --git a/arch/ppc/cpu/mpc85xx/u-boot-nand.lds b/arch/ppc/cpu/mpc85xx/u-boot-nand.lds new file mode 100644 index 0000000000..b9240f22a7 --- /dev/null +++ b/arch/ppc/cpu/mpc85xx/u-boot-nand.lds @@ -0,0 +1,137 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) - 0x1000 : + { + arch/ppc/cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/ppc/cpu/mpc85xx/u-boot-nand_spl.lds similarity index 100% rename from cpu/mpc85xx/u-boot-nand_spl.lds rename to arch/ppc/cpu/mpc85xx/u-boot-nand_spl.lds diff --git a/arch/ppc/cpu/mpc85xx/u-boot.lds b/arch/ppc/cpu/mpc85xx/u-boot.lds new file mode 100644 index 0000000000..9698bf405a --- /dev/null +++ b/arch/ppc/cpu/mpc85xx/u-boot.lds @@ -0,0 +1,157 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg RESET_VECTOR_ADDRESS - 0xffc : + { + arch/ppc/cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec RESET_VECTOR_ADDRESS : + { + *(.resetvec) + } :text = 0xffff + + . = RESET_VECTOR_ADDRESS + 0x4; + + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. Note that + * this is a temporary fix. Code to dynamically the fixup the bss + * location will be added in the future. When the bss relocation + * fixup code is present this workaround should be removed. + */ +#if (RESET_VECTOR_ADDRESS == 0xfffffffc) + . |= 0x10; +#endif + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc86xx/Makefile b/arch/ppc/cpu/mpc86xx/Makefile similarity index 100% rename from cpu/mpc86xx/Makefile rename to arch/ppc/cpu/mpc86xx/Makefile diff --git a/cpu/mpc86xx/cache.S b/arch/ppc/cpu/mpc86xx/cache.S similarity index 100% rename from cpu/mpc86xx/cache.S rename to arch/ppc/cpu/mpc86xx/cache.S diff --git a/cpu/mpc86xx/config.mk b/arch/ppc/cpu/mpc86xx/config.mk similarity index 100% rename from cpu/mpc86xx/config.mk rename to arch/ppc/cpu/mpc86xx/config.mk diff --git a/arch/ppc/cpu/mpc86xx/cpu.c b/arch/ppc/cpu/mpc86xx/cpu.c new file mode 100644 index 0000000000..188757587f --- /dev/null +++ b/arch/ppc/cpu/mpc86xx/cpu.c @@ -0,0 +1,233 @@ +/* + * Copyright 2006,2009-2010 Freescale Semiconductor, Inc. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Default board reset function + */ +static void +__board_reset(void) +{ + /* Do nothing */ +} +void board_reset(void) __attribute__((weak, alias("__board_reset"))); + + +int +checkcpu(void) +{ + sys_info_t sysinfo; + uint pvr, svr; + uint ver; + uint major, minor; + char buf1[32], buf2[32]; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + struct cpu_type *cpu; + uint msscr0 = mfspr(MSSCR0); + + svr = get_svr(); + ver = SVR_SOC_VER(svr); + major = SVR_MAJ(svr); + minor = SVR_MIN(svr); + + if (cpu_numcores() > 1) { +#ifndef CONFIG_MP + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); +#endif + } + puts("CPU: "); + + cpu = gd->cpu; + + puts(cpu->name); + + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); + puts("Core: "); + + pvr = get_pvr(); + ver = PVR_E600_VER(pvr); + major = PVR_E600_MAJ(pvr); + minor = PVR_E600_MIN(pvr); + + printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); + if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) + puts("\n Core1Translation Enabled"); + debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); + + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + + get_sys_info(&sysinfo); + + puts("Clock Configuration:\n"); + printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); + printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); + printf(" DDR:%-4s MHz (%s MT/s data rate), ", + strmhz(buf1, sysinfo.freqSystemBus / 2), + strmhz(buf2, sysinfo.freqSystemBus)); + + if (sysinfo.freqLocalBus > LCRR_CLKDIV) { + printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); + } else { + printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", + sysinfo.freqLocalBus); + } + + puts("L1: D-cache 32 KB enabled\n"); + puts(" I-cache 32 KB enabled\n"); + + puts("L2: "); + if (get_l2cr() & 0x80000000) { +#if defined(CONFIG_MPC8610) + puts("256"); +#elif defined(CONFIG_MPC8641) + puts("512"); +#endif + puts(" KB enabled\n"); + } else { + puts("Disabled\n"); + } + + return 0; +} + + +void +do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + /* Attempt board-specific reset */ + board_reset(); + + /* Next try asserting HRESET_REQ */ + out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ); + + while (1) + ; +} + + +/* + * Get timebase clock frequency + */ +unsigned long +get_tbclk(void) +{ + sys_info_t sys_info; + + get_sys_info(&sys_info); + return (sys_info.freqSystemBus + 3L) / 4L; +} + + +#if defined(CONFIG_WATCHDOG) +void +watchdog_reset(void) +{ +#if defined(CONFIG_MPC8610) + /* + * This actually feed the hard enabled watchdog. + */ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile ccsr_wdt_t *wdt = &immap->im_wdt; + volatile ccsr_gur_t *gur = &immap->im_gur; + u32 tmp = gur->pordevsr; + + if (tmp & 0x4000) { + wdt->swsrr = 0x556c; + wdt->swsrr = 0xaa39; + } +#endif +} +#endif /* CONFIG_WATCHDOG */ + +/* + * Print out the state of various machine registers. + * Currently prints out LAWs, BR0/OR0, and BATs + */ +void mpc86xx_reginfo(void) +{ + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + ccsr_lbc_t *lbc = &immap->im_lbc; + + print_bats(); + print_laws(); + + printf ("Local Bus Controller Registers\n" + "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0)); + printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1)); + printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2)); + printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3)); + printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4)); + printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5)); + printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6)); + printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); + +} + +/* + * Set the DDR BATs to reflect the actual size of DDR. + * + * dram_size is the actual size of DDR, in bytes + * + * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only + * are using a single BAT to cover DDR. + * + * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN + * is not defined) then we might have a situation where U-Boot will attempt + * to relocated itself outside of the region mapped by DBAT0. + * This will cause a machine check. + * + * Currently we are limited to power of two sized DDR since we only use a + * single bat. If a non-power of two size is used that is less than + * CONFIG_MAX_MEM_MAPPED u-boot will crash. + * + */ +void setup_ddr_bat(phys_addr_t dram_size) +{ + unsigned long batu, bl; + + bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED)); + + if (BATU_SIZE(bl) != dram_size) { + u64 sz = (u64)dram_size - BATU_SIZE(bl); + print_size(sz, " left unmapped\n"); + } + + batu = bl | BATU_VS | BATU_VP; + write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L); + write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L); +} diff --git a/arch/ppc/cpu/mpc86xx/cpu_init.c b/arch/ppc/cpu/mpc86xx/cpu_init.c new file mode 100644 index 0000000000..b4f047d85d --- /dev/null +++ b/arch/ppc/cpu/mpc86xx/cpu_init.c @@ -0,0 +1,190 @@ +/* + * Copyright 2004,2009 Freescale Semiconductor, Inc. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * cpu_init.c - low level cpu init + */ + +#include +#include +#include +#include +#include +#include + +void setup_bats(void); + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Breathe some life into the CPU... + * + * Set up the memory map + * initialize a bunch of registers + */ + +void cpu_init_f(void) +{ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile ccsr_lbc_t *memctl = &immap->im_lbc; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + +#ifdef CONFIG_FSL_LAW + init_laws(); +#endif + + setup_bats(); + + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary + * addresses - these have to be modified later when FLASH size + * has been determined + */ + +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->or0 = CONFIG_SYS_OR0_REMAP; +#endif +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->or1 = CONFIG_SYS_OR1_REMAP; +#endif + + /* now restrict to preliminary range */ +#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) + memctl->br0 = CONFIG_SYS_BR0_PRELIM; + memctl->or0 = CONFIG_SYS_OR0_PRELIM; +#endif + +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + memctl->or1 = CONFIG_SYS_OR1_PRELIM; + memctl->br1 = CONFIG_SYS_BR1_PRELIM; +#endif + +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + memctl->or2 = CONFIG_SYS_OR2_PRELIM; + memctl->br2 = CONFIG_SYS_BR2_PRELIM; +#endif + +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + memctl->or3 = CONFIG_SYS_OR3_PRELIM; + memctl->br3 = CONFIG_SYS_BR3_PRELIM; +#endif + +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + memctl->or4 = CONFIG_SYS_OR4_PRELIM; + memctl->br4 = CONFIG_SYS_BR4_PRELIM; +#endif + +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + memctl->or5 = CONFIG_SYS_OR5_PRELIM; + memctl->br5 = CONFIG_SYS_BR5_PRELIM; +#endif + +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + memctl->or6 = CONFIG_SYS_OR6_PRELIM; + memctl->br6 = CONFIG_SYS_BR6_PRELIM; +#endif + +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + memctl->or7 = CONFIG_SYS_OR7_PRELIM; + memctl->br7 = CONFIG_SYS_BR7_PRELIM; +#endif +#if defined(CONFIG_FSL_DMA) + dma_init(); +#endif + + /* enable the timebase bit in HID0 */ + set_hid0(get_hid0() | 0x4000000); + + /* enable EMCP, SYNCBE | ABE bits in HID1 */ + set_hid1(get_hid1() | 0x80000C00); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#if defined(CONFIG_MP) + setup_mp(); +#endif + return 0; +} + +/* Set up BAT registers */ +void setup_bats(void) +{ +#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) + write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); +#endif +#if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) + write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); +#endif + write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); + write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); + write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); + write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); + write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); + write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); + write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); + write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); + write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); + write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); + write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); + write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); + + return; +} + +#ifdef CONFIG_ADDR_MAP +/* Initialize address mapping array */ +void init_addr_map(void) +{ + int i; + ppc_bat_t bat = DBAT0; + phys_size_t size; + unsigned long upper, lower; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { + if (read_bat(bat, &upper, &lower) != -1) { + if (!BATU_VALID(upper)) + size = 0; + else + size = BATU_SIZE(upper); + addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), + size, i); + } +#ifdef CONFIG_HIGH_BATS + /* High bats are not contiguous with low BAT numbers */ + if (bat == DBAT3) + bat = DBAT4 - 1; +#endif + } +} +#endif diff --git a/cpu/mpc86xx/ddr-8641.c b/arch/ppc/cpu/mpc86xx/ddr-8641.c similarity index 100% rename from cpu/mpc86xx/ddr-8641.c rename to arch/ppc/cpu/mpc86xx/ddr-8641.c diff --git a/cpu/mpc86xx/fdt.c b/arch/ppc/cpu/mpc86xx/fdt.c similarity index 100% rename from cpu/mpc86xx/fdt.c rename to arch/ppc/cpu/mpc86xx/fdt.c diff --git a/cpu/mpc86xx/interrupts.c b/arch/ppc/cpu/mpc86xx/interrupts.c similarity index 100% rename from cpu/mpc86xx/interrupts.c rename to arch/ppc/cpu/mpc86xx/interrupts.c diff --git a/cpu/mpc86xx/mp.c b/arch/ppc/cpu/mpc86xx/mp.c similarity index 100% rename from cpu/mpc86xx/mp.c rename to arch/ppc/cpu/mpc86xx/mp.c diff --git a/cpu/mpc86xx/release.S b/arch/ppc/cpu/mpc86xx/release.S similarity index 100% rename from cpu/mpc86xx/release.S rename to arch/ppc/cpu/mpc86xx/release.S diff --git a/cpu/mpc86xx/speed.c b/arch/ppc/cpu/mpc86xx/speed.c similarity index 100% rename from cpu/mpc86xx/speed.c rename to arch/ppc/cpu/mpc86xx/speed.c diff --git a/cpu/mpc86xx/start.S b/arch/ppc/cpu/mpc86xx/start.S similarity index 100% rename from cpu/mpc86xx/start.S rename to arch/ppc/cpu/mpc86xx/start.S diff --git a/cpu/mpc86xx/traps.c b/arch/ppc/cpu/mpc86xx/traps.c similarity index 100% rename from cpu/mpc86xx/traps.c rename to arch/ppc/cpu/mpc86xx/traps.c diff --git a/cpu/mpc8xx/Makefile b/arch/ppc/cpu/mpc8xx/Makefile similarity index 100% rename from cpu/mpc8xx/Makefile rename to arch/ppc/cpu/mpc8xx/Makefile diff --git a/cpu/mpc8xx/bedbug_860.c b/arch/ppc/cpu/mpc8xx/bedbug_860.c similarity index 100% rename from cpu/mpc8xx/bedbug_860.c rename to arch/ppc/cpu/mpc8xx/bedbug_860.c diff --git a/cpu/mpc8xx/commproc.c b/arch/ppc/cpu/mpc8xx/commproc.c similarity index 100% rename from cpu/mpc8xx/commproc.c rename to arch/ppc/cpu/mpc8xx/commproc.c diff --git a/cpu/mpc8xx/config.mk b/arch/ppc/cpu/mpc8xx/config.mk similarity index 100% rename from cpu/mpc8xx/config.mk rename to arch/ppc/cpu/mpc8xx/config.mk diff --git a/cpu/mpc8xx/cpu.c b/arch/ppc/cpu/mpc8xx/cpu.c similarity index 100% rename from cpu/mpc8xx/cpu.c rename to arch/ppc/cpu/mpc8xx/cpu.c diff --git a/cpu/mpc8xx/cpu_init.c b/arch/ppc/cpu/mpc8xx/cpu_init.c similarity index 100% rename from cpu/mpc8xx/cpu_init.c rename to arch/ppc/cpu/mpc8xx/cpu_init.c diff --git a/cpu/mpc8xx/fdt.c b/arch/ppc/cpu/mpc8xx/fdt.c similarity index 100% rename from cpu/mpc8xx/fdt.c rename to arch/ppc/cpu/mpc8xx/fdt.c diff --git a/cpu/mpc8xx/fec.c b/arch/ppc/cpu/mpc8xx/fec.c similarity index 100% rename from cpu/mpc8xx/fec.c rename to arch/ppc/cpu/mpc8xx/fec.c diff --git a/cpu/mpc8xx/fec.h b/arch/ppc/cpu/mpc8xx/fec.h similarity index 100% rename from cpu/mpc8xx/fec.h rename to arch/ppc/cpu/mpc8xx/fec.h diff --git a/cpu/mpc8xx/i2c.c b/arch/ppc/cpu/mpc8xx/i2c.c similarity index 100% rename from cpu/mpc8xx/i2c.c rename to arch/ppc/cpu/mpc8xx/i2c.c diff --git a/cpu/mpc8xx/interrupts.c b/arch/ppc/cpu/mpc8xx/interrupts.c similarity index 100% rename from cpu/mpc8xx/interrupts.c rename to arch/ppc/cpu/mpc8xx/interrupts.c diff --git a/cpu/mpc8xx/kgdb.S b/arch/ppc/cpu/mpc8xx/kgdb.S similarity index 100% rename from cpu/mpc8xx/kgdb.S rename to arch/ppc/cpu/mpc8xx/kgdb.S diff --git a/cpu/mpc8xx/lcd.c b/arch/ppc/cpu/mpc8xx/lcd.c similarity index 100% rename from cpu/mpc8xx/lcd.c rename to arch/ppc/cpu/mpc8xx/lcd.c diff --git a/cpu/mpc8xx/plprcr_write.S b/arch/ppc/cpu/mpc8xx/plprcr_write.S similarity index 100% rename from cpu/mpc8xx/plprcr_write.S rename to arch/ppc/cpu/mpc8xx/plprcr_write.S diff --git a/cpu/mpc8xx/scc.c b/arch/ppc/cpu/mpc8xx/scc.c similarity index 100% rename from cpu/mpc8xx/scc.c rename to arch/ppc/cpu/mpc8xx/scc.c diff --git a/cpu/mpc8xx/serial.c b/arch/ppc/cpu/mpc8xx/serial.c similarity index 100% rename from cpu/mpc8xx/serial.c rename to arch/ppc/cpu/mpc8xx/serial.c diff --git a/cpu/mpc8xx/speed.c b/arch/ppc/cpu/mpc8xx/speed.c similarity index 100% rename from cpu/mpc8xx/speed.c rename to arch/ppc/cpu/mpc8xx/speed.c diff --git a/cpu/mpc8xx/spi.c b/arch/ppc/cpu/mpc8xx/spi.c similarity index 100% rename from cpu/mpc8xx/spi.c rename to arch/ppc/cpu/mpc8xx/spi.c diff --git a/cpu/mpc8xx/start.S b/arch/ppc/cpu/mpc8xx/start.S similarity index 100% rename from cpu/mpc8xx/start.S rename to arch/ppc/cpu/mpc8xx/start.S diff --git a/cpu/mpc8xx/traps.c b/arch/ppc/cpu/mpc8xx/traps.c similarity index 100% rename from cpu/mpc8xx/traps.c rename to arch/ppc/cpu/mpc8xx/traps.c diff --git a/cpu/mpc8xx/upatch.c b/arch/ppc/cpu/mpc8xx/upatch.c similarity index 100% rename from cpu/mpc8xx/upatch.c rename to arch/ppc/cpu/mpc8xx/upatch.c diff --git a/cpu/mpc8xx/video.c b/arch/ppc/cpu/mpc8xx/video.c similarity index 100% rename from cpu/mpc8xx/video.c rename to arch/ppc/cpu/mpc8xx/video.c diff --git a/cpu/mpc8xx/wlkbd.c b/arch/ppc/cpu/mpc8xx/wlkbd.c similarity index 100% rename from cpu/mpc8xx/wlkbd.c rename to arch/ppc/cpu/mpc8xx/wlkbd.c diff --git a/cpu/mpc8xxx/Makefile b/arch/ppc/cpu/mpc8xxx/Makefile similarity index 100% rename from cpu/mpc8xxx/Makefile rename to arch/ppc/cpu/mpc8xxx/Makefile diff --git a/arch/ppc/cpu/mpc8xxx/cpu.c b/arch/ppc/cpu/mpc8xxx/cpu.c new file mode 100644 index 0000000000..fef062b224 --- /dev/null +++ b/arch/ppc/cpu/mpc8xxx/cpu.c @@ -0,0 +1,144 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This file is derived from arch/ppc/cpu/mpc85xx/cpu.c and + * arch/ppc/cpu/mpc86xx/cpu.c. Basically this file contains + * cpu specific common code for 85xx/86xx processors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct cpu_type cpu_type_list [] = { +#if defined(CONFIG_MPC85xx) + CPU_TYPE_ENTRY(8533, 8533, 1), + CPU_TYPE_ENTRY(8533, 8533_E, 1), + CPU_TYPE_ENTRY(8535, 8535, 1), + CPU_TYPE_ENTRY(8535, 8535_E, 1), + CPU_TYPE_ENTRY(8536, 8536, 1), + CPU_TYPE_ENTRY(8536, 8536_E, 1), + CPU_TYPE_ENTRY(8540, 8540, 1), + CPU_TYPE_ENTRY(8541, 8541, 1), + CPU_TYPE_ENTRY(8541, 8541_E, 1), + CPU_TYPE_ENTRY(8543, 8543, 1), + CPU_TYPE_ENTRY(8543, 8543_E, 1), + CPU_TYPE_ENTRY(8544, 8544, 1), + CPU_TYPE_ENTRY(8544, 8544_E, 1), + CPU_TYPE_ENTRY(8545, 8545, 1), + CPU_TYPE_ENTRY(8545, 8545_E, 1), + CPU_TYPE_ENTRY(8547, 8547_E, 1), + CPU_TYPE_ENTRY(8548, 8548, 1), + CPU_TYPE_ENTRY(8548, 8548_E, 1), + CPU_TYPE_ENTRY(8555, 8555, 1), + CPU_TYPE_ENTRY(8555, 8555_E, 1), + CPU_TYPE_ENTRY(8560, 8560, 1), + CPU_TYPE_ENTRY(8567, 8567, 1), + CPU_TYPE_ENTRY(8567, 8567_E, 1), + CPU_TYPE_ENTRY(8568, 8568, 1), + CPU_TYPE_ENTRY(8568, 8568_E, 1), + CPU_TYPE_ENTRY(8569, 8569, 1), + CPU_TYPE_ENTRY(8569, 8569_E, 1), + CPU_TYPE_ENTRY(8572, 8572, 2), + CPU_TYPE_ENTRY(8572, 8572_E, 2), + CPU_TYPE_ENTRY(P1011, P1011, 1), + CPU_TYPE_ENTRY(P1011, P1011_E, 1), + CPU_TYPE_ENTRY(P1012, P1012, 1), + CPU_TYPE_ENTRY(P1012, P1012_E, 1), + CPU_TYPE_ENTRY(P1013, P1013, 1), + CPU_TYPE_ENTRY(P1013, P1013_E, 1), + CPU_TYPE_ENTRY(P1020, P1020, 2), + CPU_TYPE_ENTRY(P1020, P1020_E, 2), + CPU_TYPE_ENTRY(P1021, P1021, 2), + CPU_TYPE_ENTRY(P1021, P1021_E, 2), + CPU_TYPE_ENTRY(P1022, P1022, 2), + CPU_TYPE_ENTRY(P1022, P1022_E, 2), + CPU_TYPE_ENTRY(P2010, P2010, 1), + CPU_TYPE_ENTRY(P2010, P2010_E, 1), + CPU_TYPE_ENTRY(P2020, P2020, 2), + CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P4040, P4040, 4), + CPU_TYPE_ENTRY(P4040, P4040_E, 4), + CPU_TYPE_ENTRY(P4080, P4080, 8), + CPU_TYPE_ENTRY(P4080, P4080_E, 8), +#elif defined(CONFIG_MPC86xx) + CPU_TYPE_ENTRY(8610, 8610, 1), + CPU_TYPE_ENTRY(8641, 8641, 2), + CPU_TYPE_ENTRY(8641D, 8641D, 2), +#endif +}; + +struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); + +struct cpu_type *identify_cpu(u32 ver) +{ + int i; + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { + if (cpu_type_list[i].soc_ver == ver) + return &cpu_type_list[i]; + } + return &cpu_type_unknown; +} + +int cpu_numcores() { + struct cpu_type *cpu; + cpu = gd->cpu; + return cpu->num_cores; +} + +int probecpu (void) +{ + uint svr; + uint ver; + + svr = get_svr(); + ver = SVR_SOC_VER(svr); + + gd->cpu = identify_cpu(ver); + + return 0; +} + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_ETHER_ON_FCC) + fec_initialize(bis); +#endif + +#if defined(CONFIG_UEC_ETH) + uec_standard_init(bis); +#endif + +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) + tsec_standard_init(bis); +#endif + + return 0; +} diff --git a/cpu/mpc8xxx/ddr/Makefile b/arch/ppc/cpu/mpc8xxx/ddr/Makefile similarity index 100% rename from cpu/mpc8xxx/ddr/Makefile rename to arch/ppc/cpu/mpc8xxx/ddr/Makefile diff --git a/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/ppc/cpu/mpc8xxx/ddr/common_timing_params.h similarity index 100% rename from cpu/mpc8xxx/ddr/common_timing_params.h rename to arch/ppc/cpu/mpc8xxx/ddr/common_timing_params.h diff --git a/arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c new file mode 100644 index 0000000000..03f9c4380d --- /dev/null +++ b/arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -0,0 +1,1366 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +/* + * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Based on code from spd_sdram.c + * Author: James Yang [at freescale.com] + */ + +#include +#include + +#include "ddr.h" + +extern unsigned int picos_to_mclk(unsigned int picos); +/* + * Determine Rtt value. + * + * This should likely be either board or controller specific. + * + * Rtt(nominal) - DDR2: + * 0 = Rtt disabled + * 1 = 75 ohm + * 2 = 150 ohm + * 3 = 50 ohm + * Rtt(nominal) - DDR3: + * 0 = Rtt disabled + * 1 = 60 ohm + * 2 = 120 ohm + * 3 = 40 ohm + * 4 = 20 ohm + * 5 = 30 ohm + * + * FIXME: Apparently 8641 needs a value of 2 + * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 + * + * FIXME: There was some effort down this line earlier: + * + * unsigned int i; + * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { + * if (popts->dimmslot[i].num_valid_cs + * && (popts->cs_local_opts[2*i].odt_rd_cfg + * || popts->cs_local_opts[2*i].odt_wr_cfg)) { + * rtt = 2; + * break; + * } + * } + */ +static inline int fsl_ddr_get_rtt(void) +{ + int rtt; + +#if defined(CONFIG_FSL_DDR1) + rtt = 0; +#elif defined(CONFIG_FSL_DDR2) + rtt = 3; +#else + rtt = 0; +#endif + + return rtt; +} + +/* + * compute the CAS write latency according to DDR3 spec + * CWL = 5 if tCK >= 2.5ns + * 6 if 2.5ns > tCK >= 1.875ns + * 7 if 1.875ns > tCK >= 1.5ns + * 8 if 1.5ns > tCK >= 1.25ns + */ +static inline unsigned int compute_cas_write_latency(void) +{ + unsigned int cwl; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + + if (mclk_ps >= 2500) + cwl = 5; + else if (mclk_ps >= 1875) + cwl = 6; + else if (mclk_ps >= 1500) + cwl = 7; + else if (mclk_ps >= 1250) + cwl = 8; + else + cwl = 8; + return cwl; +} + +/* Chip Select Configuration (CSn_CONFIG) */ +static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const dimm_params_t *dimm_params) +{ + unsigned int cs_n_en = 0; /* Chip Select enable */ + unsigned int intlv_en = 0; /* Memory controller interleave enable */ + unsigned int intlv_ctl = 0; /* Interleaving control */ + unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ + unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ + unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ + unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ + unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ + unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ + + /* Compute CS_CONFIG only for existing ranks of each DIMM. */ + if ((((i&1) == 0) + && (dimm_params[i/2].n_ranks == 1)) + || (dimm_params[i/2].n_ranks == 2)) { + unsigned int n_banks_per_sdram_device; + cs_n_en = 1; + if (i == 0) { + /* These fields only available in CS0_CONFIG */ + intlv_en = popts->memctl_interleaving; + intlv_ctl = popts->memctl_interleaving_mode; + } + ap_n_en = popts->cs_local_opts[i].auto_precharge; + odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; + odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; + n_banks_per_sdram_device + = dimm_params[i/2].n_banks_per_sdram_device; + ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; + row_bits_cs_n = dimm_params[i/2].n_row_addr - 12; + col_bits_cs_n = dimm_params[i/2].n_col_addr - 8; + } + + ddr->cs[i].config = (0 + | ((cs_n_en & 0x1) << 31) + | ((intlv_en & 0x3) << 29) + | ((intlv_ctl & 0xf) << 24) + | ((ap_n_en & 0x1) << 23) + + /* XXX: some implementation only have 1 bit starting at left */ + | ((odt_rd_cfg & 0x7) << 20) + + /* XXX: Some implementation only have 1 bit starting at left */ + | ((odt_wr_cfg & 0x7) << 16) + + | ((ba_bits_cs_n & 0x3) << 14) + | ((row_bits_cs_n & 0x7) << 8) + | ((col_bits_cs_n & 0x7) << 0) + ); + debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); +} + +/* Chip Select Configuration 2 (CSn_CONFIG_2) */ +/* FIXME: 8572 */ +static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int pasr_cfg = 0; /* Partial array self refresh config */ + + ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); + debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); +} + +/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ + +#if !defined(CONFIG_FSL_DDR1) +/* + * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) + * + * Avoid writing for DDR I. The new PQ38 DDR controller + * dreams up non-zero default values to be backwards compatible. + */ +static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ + unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ + /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ + unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ + unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ + + /* Active powerdown exit timing (tXARD and tXARDS). */ + unsigned char act_pd_exit_mclk; + /* Precharge powerdown exit timing (tXP). */ + unsigned char pre_pd_exit_mclk; + /* Precharge powerdown exit timing (tAXPD). */ + unsigned char taxpd_mclk; + /* Mode register set cycle time (tMRD). */ + unsigned char tmrd_mclk; + +#if defined(CONFIG_FSL_DDR3) + /* + * (tXARD and tXARDS). Empirical? + * The DDR3 spec has not tXARD, + * we use the tXP instead of it. + * tXP=max(3nCK, 7.5ns) for DDR3. + * spec has not the tAXPD, we use + * tAXPD=8, need design to confirm. + */ + int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ + act_pd_exit_mclk = picos_to_mclk(tXP); + /* Mode register MR0[A12] is '1' - fast exit */ + pre_pd_exit_mclk = act_pd_exit_mclk; + taxpd_mclk = 8; + tmrd_mclk = 4; +#else /* CONFIG_FSL_DDR2 */ + /* + * (tXARD and tXARDS). Empirical? + * tXARD = 2 for DDR2 + * tXP=2 + * tAXPD=8 + */ + act_pd_exit_mclk = 2; + pre_pd_exit_mclk = 2; + taxpd_mclk = 8; + tmrd_mclk = 2; +#endif + + ddr->timing_cfg_0 = (0 + | ((trwt_mclk & 0x3) << 30) /* RWT */ + | ((twrt_mclk & 0x3) << 28) /* WRT */ + | ((trrt_mclk & 0x3) << 26) /* RRT */ + | ((twwt_mclk & 0x3) << 24) /* WWT */ + | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ + | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ + | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ + | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ + ); + debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); +} +#endif /* defined(CONFIG_FSL_DDR2) */ + +/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ +static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) +{ + /* Extended Activate to precharge interval (tRAS) */ + unsigned int ext_acttopre = 0; + unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */ + unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */ + unsigned int cntl_adj = 0; /* Control Adjust */ + + /* If the tRAS > 19 MCLK, we use the ext mode */ + if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13) + ext_acttopre = 1; + + ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4; + + /* If the CAS latency more than 8, use the ext mode */ + if (cas_latency > 8) + ext_caslat = 1; + + ddr->timing_cfg_3 = (0 + | ((ext_acttopre & 0x1) << 24) + | ((ext_refrec & 0xF) << 16) + | ((ext_caslat & 0x1) << 12) + | ((cntl_adj & 0x7) << 0) + ); + debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); +} + +/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ +static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) +{ + /* Precharge-to-activate interval (tRP) */ + unsigned char pretoact_mclk; + /* Activate to precharge interval (tRAS) */ + unsigned char acttopre_mclk; + /* Activate to read/write interval (tRCD) */ + unsigned char acttorw_mclk; + /* CASLAT */ + unsigned char caslat_ctrl; + /* Refresh recovery time (tRFC) ; trfc_low */ + unsigned char refrec_ctrl; + /* Last data to precharge minimum interval (tWR) */ + unsigned char wrrec_mclk; + /* Activate-to-activate interval (tRRD) */ + unsigned char acttoact_mclk; + /* Last write data pair to read command issue interval (tWTR) */ + unsigned char wrtord_mclk; + + pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps); + acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps); + acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps); + + /* + * Translate CAS Latency to a DDR controller field value: + * + * CAS Lat DDR I DDR II Ctrl + * Clocks SPD Bit SPD Bit Value + * ------- ------- ------- ----- + * 1.0 0 0001 + * 1.5 1 0010 + * 2.0 2 2 0011 + * 2.5 3 0100 + * 3.0 4 3 0101 + * 3.5 5 0110 + * 4.0 4 0111 + * 4.5 1000 + * 5.0 5 1001 + */ +#if defined(CONFIG_FSL_DDR1) + caslat_ctrl = (cas_latency + 1) & 0x07; +#elif defined(CONFIG_FSL_DDR2) + caslat_ctrl = 2 * cas_latency - 1; +#else + /* + * if the CAS latency more than 8 cycle, + * we need set extend bit for it at + * TIMING_CFG_3[EXT_CASLAT] + */ + if (cas_latency > 8) + cas_latency -= 8; + caslat_ctrl = 2 * cas_latency - 1; +#endif + + refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8; + wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); + if (popts->OTF_burst_chop_en) + wrrec_mclk += 2; + + acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps); + /* + * JEDEC has min requirement for tRRD + */ +#if defined(CONFIG_FSL_DDR3) + if (acttoact_mclk < 4) + acttoact_mclk = 4; +#endif + wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps); + /* + * JEDEC has some min requirements for tWTR + */ +#if defined(CONFIG_FSL_DDR2) + if (wrtord_mclk < 2) + wrtord_mclk = 2; +#elif defined(CONFIG_FSL_DDR3) + if (wrtord_mclk < 4) + wrtord_mclk = 4; +#endif + if (popts->OTF_burst_chop_en) + wrtord_mclk += 2; + + ddr->timing_cfg_1 = (0 + | ((pretoact_mclk & 0x0F) << 28) + | ((acttopre_mclk & 0x0F) << 24) + | ((acttorw_mclk & 0xF) << 20) + | ((caslat_ctrl & 0xF) << 16) + | ((refrec_ctrl & 0xF) << 12) + | ((wrrec_mclk & 0x0F) << 8) + | ((acttoact_mclk & 0x07) << 4) + | ((wrtord_mclk & 0x07) << 0) + ); + debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); +} + +/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ +static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) +{ + /* Additive latency */ + unsigned char add_lat_mclk; + /* CAS-to-preamble override */ + unsigned short cpo; + /* Write latency */ + unsigned char wr_lat; + /* Read to precharge (tRTP) */ + unsigned char rd_to_pre; + /* Write command to write data strobe timing adjustment */ + unsigned char wr_data_delay; + /* Minimum CKE pulse width (tCKE) */ + unsigned char cke_pls; + /* Window for four activates (tFAW) */ + unsigned short four_act; + + /* FIXME add check that this must be less than acttorw_mclk */ + add_lat_mclk = additive_latency; + cpo = popts->cpo_override; + +#if defined(CONFIG_FSL_DDR1) + /* + * This is a lie. It should really be 1, but if it is + * set to 1, bits overlap into the old controller's + * otherwise unused ACSM field. If we leave it 0, then + * the HW will magically treat it as 1 for DDR 1. Oh Yea. + */ + wr_lat = 0; +#elif defined(CONFIG_FSL_DDR2) + wr_lat = cas_latency - 1; +#else + wr_lat = compute_cas_write_latency(); +#endif + + rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); + /* + * JEDEC has some min requirements for tRTP + */ +#if defined(CONFIG_FSL_DDR2) + if (rd_to_pre < 2) + rd_to_pre = 2; +#elif defined(CONFIG_FSL_DDR3) + if (rd_to_pre < 4) + rd_to_pre = 4; +#endif + if (additive_latency) + rd_to_pre += additive_latency; + if (popts->OTF_burst_chop_en) + rd_to_pre += 2; /* according to UM */ + + wr_data_delay = popts->write_data_delay; + cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps); + four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps); + + ddr->timing_cfg_2 = (0 + | ((add_lat_mclk & 0xf) << 28) + | ((cpo & 0x1f) << 23) + | ((wr_lat & 0xf) << 19) + | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) + | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) + | ((cke_pls & 0x7) << 6) + | ((four_act & 0x3f) << 0) + ); + debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); +} + +/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ +static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) +{ + unsigned int mem_en; /* DDR SDRAM interface logic enable */ + unsigned int sren; /* Self refresh enable (during sleep) */ + unsigned int ecc_en; /* ECC enable. */ + unsigned int rd_en; /* Registered DIMM enable */ + unsigned int sdram_type; /* Type of SDRAM */ + unsigned int dyn_pwr; /* Dynamic power management mode */ + unsigned int dbw; /* DRAM dta bus width */ + unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ + unsigned int ncap = 0; /* Non-concurrent auto-precharge */ + unsigned int threeT_en; /* Enable 3T timing */ + unsigned int twoT_en; /* Enable 2T timing */ + unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ + unsigned int x32_en = 0; /* x32 enable */ + unsigned int pchb8 = 0; /* precharge bit 8 enable */ + unsigned int hse; /* Global half strength override */ + unsigned int mem_halt = 0; /* memory controller halt */ + unsigned int bi = 0; /* Bypass initialization */ + + mem_en = 1; + sren = popts->self_refresh_in_sleep; + if (common_dimm->all_DIMMs_ECC_capable) { + /* Allow setting of ECC only if all DIMMs are ECC. */ + ecc_en = popts->ECC_mode; + } else { + ecc_en = 0; + } + + rd_en = (common_dimm->all_DIMMs_registered + && !common_dimm->all_DIMMs_unbuffered); + + sdram_type = CONFIG_FSL_SDRAM_TYPE; + + dyn_pwr = popts->dynamic_power; + dbw = popts->data_bus_width; + /* 8-beat burst enable DDR-III case + * we must clear it when use the on-the-fly mode, + * must set it when use the 32-bits bus mode. + */ + if (sdram_type == SDRAM_TYPE_DDR3) { + if (popts->burst_length == DDR_BL8) + eight_be = 1; + if (popts->burst_length == DDR_OTF) + eight_be = 0; + if (dbw == 0x1) + eight_be = 1; + } + + threeT_en = popts->threeT_en; + twoT_en = popts->twoT_en; + ba_intlv_ctl = popts->ba_intlv_ctl; + hse = popts->half_strength_driver_enable; + + ddr->ddr_sdram_cfg = (0 + | ((mem_en & 0x1) << 31) + | ((sren & 0x1) << 30) + | ((ecc_en & 0x1) << 29) + | ((rd_en & 0x1) << 28) + | ((sdram_type & 0x7) << 24) + | ((dyn_pwr & 0x1) << 21) + | ((dbw & 0x3) << 19) + | ((eight_be & 0x1) << 18) + | ((ncap & 0x1) << 17) + | ((threeT_en & 0x1) << 16) + | ((twoT_en & 0x1) << 15) + | ((ba_intlv_ctl & 0x7F) << 8) + | ((x32_en & 0x1) << 5) + | ((pchb8 & 0x1) << 4) + | ((hse & 0x1) << 3) + | ((mem_halt & 0x1) << 1) + | ((bi & 0x1) << 0) + ); + debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); +} + +/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ +static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + unsigned int frc_sr = 0; /* Force self refresh */ + unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ + unsigned int dll_rst_dis; /* DLL reset disable */ + unsigned int dqs_cfg; /* DQS configuration */ + unsigned int odt_cfg; /* ODT configuration */ + unsigned int num_pr; /* Number of posted refreshes */ + unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ + unsigned int ap_en; /* Address Parity Enable */ + unsigned int d_init; /* DRAM data initialization */ + unsigned int rcw_en = 0; /* Register Control Word Enable */ + unsigned int md_en = 0; /* Mirrored DIMM Enable */ + + dll_rst_dis = 1; /* Make this configurable */ + dqs_cfg = popts->DQS_config; + if (popts->cs_local_opts[0].odt_rd_cfg + || popts->cs_local_opts[0].odt_wr_cfg) { + /* FIXME */ + odt_cfg = 2; + } else { + odt_cfg = 0; + } + + num_pr = 1; /* Make this configurable */ + + /* + * 8572 manual says + * {TIMING_CFG_1[PRETOACT] + * + [DDR_SDRAM_CFG_2[NUM_PR] + * * ({EXT_REFREC || REFREC} + 8 + 2)]} + * << DDR_SDRAM_INTERVAL[REFINT] + */ +#if defined(CONFIG_FSL_DDR3) + obc_cfg = popts->OTF_burst_chop_en; +#else + obc_cfg = 0; +#endif + + ap_en = 0; /* Make this configurable? */ + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Use the DDR controller to auto initialize memory. */ + d_init = 1; + ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); +#else + /* Memory will be initialized via DMA, or not at all. */ + d_init = 0; +#endif + +#if defined(CONFIG_FSL_DDR3) + md_en = popts->mirrored_dimm; +#endif + ddr->ddr_sdram_cfg_2 = (0 + | ((frc_sr & 0x1) << 31) + | ((sr_ie & 0x1) << 30) + | ((dll_rst_dis & 0x1) << 29) + | ((dqs_cfg & 0x3) << 26) + | ((odt_cfg & 0x3) << 21) + | ((num_pr & 0xf) << 12) + | ((obc_cfg & 0x1) << 6) + | ((ap_en & 0x1) << 5) + | ((d_init & 0x1) << 4) + | ((rcw_en & 0x1) << 2) + | ((md_en & 0x1) << 0) + ); + debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); +} + +/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ + unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ + +#if defined(CONFIG_FSL_DDR3) + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ + unsigned int srt = 0; /* self-refresh temerature, normal range */ + unsigned int asr = 0; /* auto self-refresh disable */ + unsigned int cwl = compute_cas_write_latency() - 5; + unsigned int pasr = 0; /* partial array self refresh disable */ + + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + + esdmode2 = (0 + | ((rtt_wr & 0x3) << 9) + | ((srt & 0x1) << 7) + | ((asr & 0x1) << 6) + | ((cwl & 0x7) << 3) + | ((pasr & 0x7) << 0)); +#endif + ddr->ddr_sdram_mode_2 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); +} + +/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ +static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) +{ + unsigned int refint; /* Refresh interval */ + unsigned int bstopre; /* Precharge interval */ + + refint = picos_to_mclk(common_dimm->refresh_rate_ps); + + bstopre = popts->bstopre; + + /* refint field used 0x3FFF in earlier controllers */ + ddr->ddr_sdram_interval = (0 + | ((refint & 0xFFFF) << 16) + | ((bstopre & 0x3FFF) << 0) + ); + debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); +} + +#if defined(CONFIG_FSL_DDR3) +/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ +static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) +{ + unsigned short esdmode; /* Extended SDRAM mode */ + unsigned short sdmode; /* SDRAM mode */ + + /* Mode Register - MR1 */ + unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ + unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ + unsigned int rtt; + unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ + unsigned int al = 0; /* Posted CAS# additive latency (AL) */ + unsigned int dic = 1; /* Output driver impedance, 34ohm */ + unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), + 1=Disable (Test/Debug) */ + + /* Mode Register - MR0 */ + unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ + unsigned int wr; /* Write Recovery */ + unsigned int dll_rst; /* DLL Reset */ + unsigned int mode; /* Normal=0 or Test=1 */ + unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ + /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ + unsigned int bt; + unsigned int bl; /* BL: Burst Length */ + + unsigned int wr_mclk; + + const unsigned int mclk_ps = get_memory_clk_period_ps(); + + rtt = fsl_ddr_get_rtt(); + if (popts->rtt_override) + rtt = popts->rtt_override_value; + + if (additive_latency == (cas_latency - 1)) + al = 1; + if (additive_latency == (cas_latency - 2)) + al = 2; + + /* + * The esdmode value will also be used for writing + * MR1 during write leveling for DDR3, although the + * bits specifically related to the write leveling + * scheme will be handled automatically by the DDR + * controller. so we set the wrlvl_en = 0 here. + */ + esdmode = (0 + | ((qoff & 0x1) << 12) + | ((tdqs_en & 0x1) << 11) + | ((rtt & 0x4) << 7) /* rtt field is split */ + | ((wrlvl_en & 0x1) << 7) + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((dic & 0x2) << 4) /* DIC field is split */ + | ((al & 0x3) << 3) + | ((rtt & 0x1) << 2) /* rtt field is split */ + | ((dic & 0x1) << 1) /* DIC field is split */ + | ((dll_en & 0x1) << 0) + ); + + /* + * DLL control for precharge PD + * 0=slow exit DLL off (tXPDLL) + * 1=fast exit DLL on (tXP) + */ + dll_on = 1; + wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps; + if (wr_mclk >= 12) + wr = 6; + else if (wr_mclk >= 9) + wr = 5; + else + wr = wr_mclk - 4; + dll_rst = 0; /* dll no reset */ + mode = 0; /* normal mode */ + + /* look up table to get the cas latency bits */ + if (cas_latency >= 5 && cas_latency <= 11) { + unsigned char cas_latency_table[7] = { + 0x2, /* 5 clocks */ + 0x4, /* 6 clocks */ + 0x6, /* 7 clocks */ + 0x8, /* 8 clocks */ + 0xa, /* 9 clocks */ + 0xc, /* 10 clocks */ + 0xe /* 11 clocks */ + }; + caslat = cas_latency_table[cas_latency - 5]; + } + bt = 0; /* Nibble sequential */ + + switch (popts->burst_length) { + case DDR_BL8: + bl = 0; + break; + case DDR_OTF: + bl = 1; + break; + case DDR_BC4: + bl = 2; + break; + default: + printf("Error: invalid burst length of %u specified. " + " Defaulting to on-the-fly BC4 or BL8 beats.\n", + popts->burst_length); + bl = 1; + break; + } + + sdmode = (0 + | ((dll_on & 0x1) << 12) + | ((wr & 0x7) << 9) + | ((dll_rst & 0x1) << 8) + | ((mode & 0x1) << 7) + | (((caslat >> 1) & 0x7) << 4) + | ((bt & 0x1) << 3) + | ((bl & 0x3) << 0) + ); + + ddr->ddr_sdram_mode = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); +} + +#else /* !CONFIG_FSL_DDR3 */ + +/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ +static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) +{ + unsigned short esdmode; /* Extended SDRAM mode */ + unsigned short sdmode; /* SDRAM mode */ + + /* + * FIXME: This ought to be pre-calculated in a + * technology-specific routine, + * e.g. compute_DDR2_mode_register(), and then the + * sdmode and esdmode passed in as part of common_dimm. + */ + + /* Extended Mode Register */ + unsigned int mrs = 0; /* Mode Register Set */ + unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ + unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ + unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ + unsigned int ocd = 0; /* 0x0=OCD not supported, + 0x7=OCD default state */ + unsigned int rtt; + unsigned int al; /* Posted CAS# additive latency (AL) */ + unsigned int ods = 0; /* Output Drive Strength: + 0 = Full strength (18ohm) + 1 = Reduced strength (4ohm) */ + unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), + 1=Disable (Test/Debug) */ + + /* Mode Register (MR) */ + unsigned int mr; /* Mode Register Definition */ + unsigned int pd; /* Power-Down Mode */ + unsigned int wr; /* Write Recovery */ + unsigned int dll_res; /* DLL Reset */ + unsigned int mode; /* Normal=0 or Test=1 */ + unsigned int caslat = 0;/* CAS# latency */ + /* BT: Burst Type (0=Sequential, 1=Interleaved) */ + unsigned int bt; + unsigned int bl; /* BL: Burst Length */ + +#if defined(CONFIG_FSL_DDR2) + const unsigned int mclk_ps = get_memory_clk_period_ps(); +#endif + + rtt = fsl_ddr_get_rtt(); + + al = additive_latency; + + esdmode = (0 + | ((mrs & 0x3) << 14) + | ((outputs & 0x1) << 12) + | ((rdqs_en & 0x1) << 11) + | ((dqs_en & 0x1) << 10) + | ((ocd & 0x7) << 7) + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((al & 0x7) << 3) + | ((rtt & 0x1) << 2) /* rtt field is split */ + | ((ods & 0x1) << 1) + | ((dll_en & 0x1) << 0) + ); + + mr = 0; /* FIXME: CHECKME */ + + /* + * 0 = Fast Exit (Normal) + * 1 = Slow Exit (Low Power) + */ + pd = 0; + +#if defined(CONFIG_FSL_DDR1) + wr = 0; /* Historical */ +#elif defined(CONFIG_FSL_DDR2) + wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1; +#endif + dll_res = 0; + mode = 0; + +#if defined(CONFIG_FSL_DDR1) + if (1 <= cas_latency && cas_latency <= 4) { + unsigned char mode_caslat_table[4] = { + 0x5, /* 1.5 clocks */ + 0x2, /* 2.0 clocks */ + 0x6, /* 2.5 clocks */ + 0x3 /* 3.0 clocks */ + }; + caslat = mode_caslat_table[cas_latency - 1]; + } else { + printf("Warning: unknown cas_latency %d\n", cas_latency); + } +#elif defined(CONFIG_FSL_DDR2) + caslat = cas_latency; +#endif + bt = 0; + + switch (popts->burst_length) { + case DDR_BL4: + bl = 2; + break; + case DDR_BL8: + bl = 3; + break; + default: + printf("Error: invalid burst length of %u specified. " + " Defaulting to 4 beats.\n", + popts->burst_length); + bl = 2; + break; + } + + sdmode = (0 + | ((mr & 0x3) << 14) + | ((pd & 0x1) << 12) + | ((wr & 0x7) << 9) + | ((dll_res & 0x1) << 8) + | ((mode & 0x1) << 7) + | ((caslat & 0x7) << 4) + | ((bt & 0x1) << 3) + | ((bl & 0x7) << 0) + ); + + ddr->ddr_sdram_mode = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); +} +#endif + +/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ +static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int init_value; /* Initialization value */ + + init_value = 0xDEADBEEF; + ddr->ddr_data_init = init_value; +} + +/* + * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) + * The old controller on the 8540/60 doesn't have this register. + * Hope it's OK to set it (to 0) anyway. + */ +static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + unsigned int clk_adjust; /* Clock adjust */ + + clk_adjust = popts->clk_adjust; + ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; +} + +/* DDR Initialization Address (DDR_INIT_ADDR) */ +static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int init_addr = 0; /* Initialization address */ + + ddr->ddr_init_addr = init_addr; +} + +/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ +static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int uia = 0; /* Use initialization address */ + unsigned int init_ext_addr = 0; /* Initialization address */ + + ddr->ddr_init_ext_addr = (0 + | ((uia & 0x1) << 31) + | (init_ext_addr & 0xF) + ); +} + +/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ +static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ + unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ + unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ + unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ + unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ + +#if defined(CONFIG_FSL_DDR3) + if (popts->burst_length == DDR_BL8) { + /* We set BL/2 for fixed BL8 */ + rrt = 0; /* BL/2 clocks */ + wwt = 0; /* BL/2 clocks */ + } else { + /* We need to set BL/2 + 2 to BC4 and OTF */ + rrt = 2; /* BL/2 + 2 clocks */ + wwt = 2; /* BL/2 + 2 clocks */ + } + dll_lock = 1; /* tDLLK = 512 clocks from spec */ +#endif + ddr->timing_cfg_4 = (0 + | ((rwt & 0xf) << 28) + | ((wrt & 0xf) << 24) + | ((rrt & 0xf) << 20) + | ((wwt & 0xf) << 16) + | (dll_lock & 0x3) + ); + debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); +} + +/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ +static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int rodt_on = 0; /* Read to ODT on */ + unsigned int rodt_off = 0; /* Read to ODT off */ + unsigned int wodt_on = 0; /* Write to ODT on */ + unsigned int wodt_off = 0; /* Write to ODT off */ + +#if defined(CONFIG_FSL_DDR3) + rodt_on = 3; /* 2 clocks */ + rodt_off = 4; /* 4 clocks */ + wodt_on = 2; /* 1 clocks */ + wodt_off = 4; /* 4 clocks */ +#endif + + ddr->timing_cfg_5 = (0 + | ((rodt_on & 0x1f) << 24) + | ((rodt_off & 0x7) << 20) + | ((wodt_on & 0x1f) << 12) + | ((wodt_off & 0x7) << 8) + ); + debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); +} + +/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ +static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) +{ + unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ + /* Normal Operation Full Calibration Time (tZQoper) */ + unsigned int zqoper = 0; + /* Normal Operation Short Calibration Time (tZQCS) */ + unsigned int zqcs = 0; + + if (zq_en) { + zqinit = 9; /* 512 clocks */ + zqoper = 8; /* 256 clocks */ + zqcs = 6; /* 64 clocks */ + } + + ddr->ddr_zq_cntl = (0 + | ((zq_en & 0x1) << 31) + | ((zqinit & 0xF) << 24) + | ((zqoper & 0xF) << 16) + | ((zqcs & 0xF) << 8) + ); +} + +/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ +static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, + const memctl_options_t *popts) +{ + /* + * First DQS pulse rising edge after margining mode + * is programmed (tWL_MRD) + */ + unsigned int wrlvl_mrd = 0; + /* ODT delay after margining mode is programmed (tWL_ODTEN) */ + unsigned int wrlvl_odten = 0; + /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ + unsigned int wrlvl_dqsen = 0; + /* WRLVL_SMPL: Write leveling sample time */ + unsigned int wrlvl_smpl = 0; + /* WRLVL_WLR: Write leveling repeition time */ + unsigned int wrlvl_wlr = 0; + /* WRLVL_START: Write leveling start time */ + unsigned int wrlvl_start = 0; + + /* suggest enable write leveling for DDR3 due to fly-by topology */ + if (wrlvl_en) { + /* tWL_MRD min = 40 nCK, we set it 64 */ + wrlvl_mrd = 0x6; + /* tWL_ODTEN 128 */ + wrlvl_odten = 0x7; + /* tWL_DQSEN min = 25 nCK, we set it 32 */ + wrlvl_dqsen = 0x5; + /* + * Write leveling sample time at least need 6 clocks + * higher than tWLO to allow enough time for progagation + * delay and sampling the prime data bits. + */ + wrlvl_smpl = 0xf; + /* + * Write leveling repetition time + * at least tWLO + 6 clocks clocks + * we set it 32 + */ + wrlvl_wlr = 0x5; + /* + * Write leveling start time + * The value use for the DQS_ADJUST for the first sample + * when write leveling is enabled. + */ + wrlvl_start = 0x8; + /* + * Override the write leveling sample and start time + * according to specific board + */ + if (popts->wrlvl_override) { + wrlvl_smpl = popts->wrlvl_sample; + wrlvl_start = popts->wrlvl_start; + } + } + + ddr->ddr_wrlvl_cntl = (0 + | ((wrlvl_en & 0x1) << 31) + | ((wrlvl_mrd & 0x7) << 24) + | ((wrlvl_odten & 0x7) << 20) + | ((wrlvl_dqsen & 0x7) << 16) + | ((wrlvl_smpl & 0xf) << 12) + | ((wrlvl_wlr & 0x7) << 8) + | ((wrlvl_start & 0x1F) << 0) + ); +} + +/* DDR Self Refresh Counter (DDR_SR_CNTR) */ +static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) +{ + /* Self Refresh Idle Threshold */ + ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; +} + +/* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */ +static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */ + unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */ + unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */ + unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */ + unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */ + unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */ + unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */ + unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */ + + ddr->ddr_sdram_rcw_1 = (0 + | ((rcw0 & 0xF) << 28) + | ((rcw1 & 0xF) << 24) + | ((rcw2 & 0xF) << 20) + | ((rcw3 & 0xF) << 16) + | ((rcw4 & 0xF) << 12) + | ((rcw5 & 0xF) << 8) + | ((rcw6 & 0xF) << 4) + | ((rcw7 & 0xF) << 0) + ); +} + +/* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */ +static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */ + unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */ + unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */ + unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */ + unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */ + unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */ + unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */ + unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */ + + ddr->ddr_sdram_rcw_2 = (0 + | ((rcw8 & 0xF) << 28) + | ((rcw9 & 0xF) << 24) + | ((rcw10 & 0xF) << 20) + | ((rcw11 & 0xF) << 16) + | ((rcw12 & 0xF) << 12) + | ((rcw13 & 0xF) << 8) + | ((rcw14 & 0xF) << 4) + | ((rcw15 & 0xF) << 0) + ); +} + +unsigned int +check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int res = 0; + + /* + * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are + * not set at the same time. + */ + if (ddr->ddr_sdram_cfg & 0x10000000 + && ddr->ddr_sdram_cfg & 0x00008000) { + printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " + " should not be set at the same time.\n"); + res++; + } + + return res; +} + +unsigned int +compute_fsl_memctl_config_regs(const memctl_options_t *popts, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm, + const dimm_params_t *dimm_params, + unsigned int dbw_cap_adj) +{ + unsigned int i; + unsigned int cas_latency; + unsigned int additive_latency; + unsigned int sr_it; + unsigned int zq_en; + unsigned int wrlvl_en; + + memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); + + if (common_dimm == NULL) { + printf("Error: subset DIMM params struct null pointer\n"); + return 1; + } + + /* + * Process overrides first. + * + * FIXME: somehow add dereated caslat to this + */ + cas_latency = (popts->cas_latency_override) + ? popts->cas_latency_override_value + : common_dimm->lowest_common_SPD_caslat; + + additive_latency = (popts->additive_latency_override) + ? popts->additive_latency_override_value + : common_dimm->additive_latency; + + sr_it = (popts->auto_self_refresh_en) + ? popts->sr_it + : 0; + /* ZQ calibration */ + zq_en = (popts->zq_en) ? 1 : 0; + /* write leveling */ + wrlvl_en = (popts->wrlvl_en) ? 1 : 0; + + /* Chip Select Memory Bounds (CSn_BNDS) */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + unsigned long long ea = 0, sa = 0; + + if (popts->ba_intlv_ctl && (i > 0) && + ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) { + /* Don't set up boundaries for other CS + * other than CS0, if bank interleaving + * is enabled and not CS2+CS3 interleaved. + * But we need to set the ODT_RD_CFG and + * ODT_WR_CFG for CS1_CONFIG here. + */ + set_csn_config(i, ddr, popts, dimm_params); + break; + } + + if (dimm_params[i/2].n_ranks == 0) { + debug("Skipping setup of CS%u " + "because n_ranks on DIMM %u is 0\n", i, i/2); + continue; + } + if (popts->memctl_interleaving && popts->ba_intlv_ctl) { + /* + * This works superbank 2CS + * There are 2 memory controllers configured + * identically, memory is interleaved between them, + * and each controller uses rank interleaving within + * itself. Therefore the starting and ending address + * on each controller is twice the amount present on + * each controller. + */ + unsigned long long rank_density + = dimm_params[0].capacity; + ea = (2 * (rank_density >> dbw_cap_adj)) - 1; + } + else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) { + /* + * If memory interleaving between controllers is NOT + * enabled, the starting address for each memory + * controller is distinct. However, because rank + * interleaving is enabled, the starting and ending + * addresses of the total memory on that memory + * controller needs to be programmed into its + * respective CS0_BNDS. + */ + unsigned long long rank_density + = dimm_params[i/2].rank_density; + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS + * needs to be set. + */ + sa = common_dimm->base_address; + ea = sa + (4 * (rank_density >> dbw_cap_adj))-1; + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS + * and CS2_CNDS need to be set. + */ + if (!(i&1)) { + sa = dimm_params[i/2].base_address; + ea = sa + (i * (rank_density >> + dbw_cap_adj)) - 1; + } + break; + case FSL_DDR_CS0_CS1: + /* CS0+CS1 interleaving, CS0_CNDS needs + * to be set + */ + sa = common_dimm->base_address; + ea = sa + (2 * (rank_density >> dbw_cap_adj))-1; + break; + case FSL_DDR_CS2_CS3: + /* CS2+CS3 interleaving*/ + if (i == 2) { + sa = dimm_params[i/2].base_address; + ea = sa + (2 * (rank_density >> + dbw_cap_adj)) - 1; + } + break; + default: /* No bank(chip-select) interleaving */ + break; + } + } + else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) { + /* + * Only the rank on CS0 of each memory controller may + * be used if memory controller interleaving is used + * without rank interleaving within each memory + * controller. However, the ending address programmed + * into each CS0 must be the sum of the amount of + * memory in the two CS0 ranks. + */ + if (i == 0) { + unsigned long long rank_density + = dimm_params[0].rank_density; + ea = (2 * (rank_density >> dbw_cap_adj)) - 1; + } + + } + else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) { + /* + * No rank interleaving and no memory controller + * interleaving. + */ + unsigned long long rank_density + = dimm_params[i/2].rank_density; + sa = dimm_params[i/2].base_address; + ea = sa + (rank_density >> dbw_cap_adj) - 1; + if (i&1) { + if ((dimm_params[i/2].n_ranks == 1)) { + /* Odd chip select, single-rank dimm */ + sa = 0; + ea = 0; + } else { + /* Odd chip select, dual-rank DIMM */ + sa += rank_density >> dbw_cap_adj; + ea += rank_density >> dbw_cap_adj; + } + } + } + + sa >>= 24; + ea >>= 24; + + ddr->cs[i].bnds = (0 + | ((sa & 0xFFF) << 16) /* starting address MSB */ + | ((ea & 0xFFF) << 0) /* ending address MSB */ + ); + + debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); + set_csn_config(i, ddr, popts, dimm_params); + set_csn_config_2(i, ddr); + } + +#if !defined(CONFIG_FSL_DDR1) + set_timing_cfg_0(ddr); +#endif + + set_timing_cfg_3(ddr, common_dimm, cas_latency); + set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_2(ddr, popts, common_dimm, + cas_latency, additive_latency); + + set_ddr_sdram_cfg(ddr, popts, common_dimm); + + set_ddr_sdram_cfg_2(ddr, popts); + set_ddr_sdram_mode(ddr, popts, common_dimm, + cas_latency, additive_latency); + set_ddr_sdram_mode_2(ddr, popts); + set_ddr_sdram_interval(ddr, popts, common_dimm); + set_ddr_data_init(ddr); + set_ddr_sdram_clk_cntl(ddr, popts); + set_ddr_init_addr(ddr); + set_ddr_init_ext_addr(ddr); + set_timing_cfg_4(ddr, popts); + set_timing_cfg_5(ddr); + + set_ddr_zq_cntl(ddr, zq_en); + set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); + + set_ddr_sr_cntr(ddr, sr_it); + + set_ddr_sdram_rcw_1(ddr); + set_ddr_sdram_rcw_2(ddr); + + return check_fsl_memctl_config_regs(ddr); +} diff --git a/cpu/mpc8xxx/ddr/ddr.h b/arch/ppc/cpu/mpc8xxx/ddr/ddr.h similarity index 100% rename from cpu/mpc8xxx/ddr/ddr.h rename to arch/ppc/cpu/mpc8xxx/ddr/ddr.h diff --git a/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/arch/ppc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c similarity index 100% rename from cpu/mpc8xxx/ddr/ddr1_dimm_params.c rename to arch/ppc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c diff --git a/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/ppc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c similarity index 100% rename from cpu/mpc8xxx/ddr/ddr2_dimm_params.c rename to arch/ppc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/ppc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c similarity index 100% rename from cpu/mpc8xxx/ddr/ddr3_dimm_params.c rename to arch/ppc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c diff --git a/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/ppc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c similarity index 100% rename from cpu/mpc8xxx/ddr/lc_common_dimm_params.c rename to arch/ppc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c diff --git a/cpu/mpc8xxx/ddr/main.c b/arch/ppc/cpu/mpc8xxx/ddr/main.c similarity index 100% rename from cpu/mpc8xxx/ddr/main.c rename to arch/ppc/cpu/mpc8xxx/ddr/main.c diff --git a/arch/ppc/cpu/mpc8xxx/ddr/options.c b/arch/ppc/cpu/mpc8xxx/ddr/options.c new file mode 100644 index 0000000000..46731c8153 --- /dev/null +++ b/arch/ppc/cpu/mpc8xxx/ddr/options.c @@ -0,0 +1,297 @@ +/* + * Copyright 2008, 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include +#include + +#include "ddr.h" + +/* Board-specific functions defined in each board's ddr.c */ +extern void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num); + +unsigned int populate_memctl_options(int all_DIMMs_registered, + memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + unsigned int i; + const char *p; + + /* Chip select options. */ + + /* Pick chip-select local options. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */ + + /* only for single CS? */ + popts->cs_local_opts[i].odt_rd_cfg = 0; + + popts->cs_local_opts[i].odt_wr_cfg = 1; + popts->cs_local_opts[i].auto_precharge = 0; + } + + /* Pick interleaving mode. */ + + /* + * 0 = no interleaving + * 1 = interleaving between 2 controllers + */ + popts->memctl_interleaving = 0; + + /* + * 0 = cacheline + * 1 = page + * 2 = (logical) bank + * 3 = superbank (only if CS interleaving is enabled) + */ + popts->memctl_interleaving_mode = 0; + + /* + * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl + * 1: page: bit to the left of the column bits selects the memctl + * 2: bank: bit to the left of the bank bits selects the memctl + * 3: superbank: bit to the left of the chip select selects the memctl + * + * NOTE: ba_intlv (rank interleaving) is independent of memory + * controller interleaving; it is only within a memory controller. + * Must use superbank interleaving if rank interleaving is used and + * memory controller interleaving is enabled. + */ + + /* + * 0 = no + * 0x40 = CS0,CS1 + * 0x20 = CS2,CS3 + * 0x60 = CS0,CS1 + CS2,CS3 + * 0x04 = CS0,CS1,CS2,CS3 + */ + popts->ba_intlv_ctl = 0; + + /* Memory Organization Parameters */ + popts->registered_dimm_en = all_DIMMs_registered; + + /* Operational Mode Paramters */ + + /* Pick ECC modes */ +#ifdef CONFIG_DDR_ECC + popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */ +#else + popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */ +#endif + popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ + + /* + * Choose DQS config + * 0 for DDR1 + * 1 for DDR2 + */ +#if defined(CONFIG_FSL_DDR1) + popts->DQS_config = 0; +#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) + popts->DQS_config = 1; +#endif + + /* Choose self-refresh during sleep. */ + popts->self_refresh_in_sleep = 1; + + /* Choose dynamic power management mode. */ + popts->dynamic_power = 0; + + /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ + popts->data_bus_width = 0; + + /* Choose burst length. */ +#if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_E500MC) + popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ + popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ +#else + popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ + popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ +#endif +#else + popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ +#endif + + /* Choose ddr controller address mirror mode */ +#if defined(CONFIG_FSL_DDR3) + popts->mirrored_dimm = pdimm[0].mirrored_dimm; +#endif + + /* Global Timing Parameters. */ + debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); + + /* Pick a caslat override. */ + popts->cas_latency_override = 0; + popts->cas_latency_override_value = 3; + if (popts->cas_latency_override) { + debug("using caslat override value = %u\n", + popts->cas_latency_override_value); + } + + /* Decide whether to use the computed derated latency */ + popts->use_derated_caslat = 0; + + /* Choose an additive latency. */ + popts->additive_latency_override = 0; + popts->additive_latency_override_value = 3; + if (popts->additive_latency_override) { + debug("using additive latency override value = %u\n", + popts->additive_latency_override_value); + } + + /* + * 2T_EN setting + * + * Factors to consider for 2T_EN: + * - number of DIMMs installed + * - number of components, number of active ranks + * - how much time you want to spend playing around + */ + popts->twoT_en = 0; + popts->threeT_en = 0; + + /* + * BSTTOPRE precharge interval + * + * Set this to 0 for global auto precharge + * + * FIXME: Should this be configured in picoseconds? + * Why it should be in ps: better understanding of this + * relative to actual DRAM timing parameters such as tRAS. + * e.g. tRAS(min) = 40 ns + */ + popts->bstopre = 0x100; + + /* Minimum CKE pulse width -- tCKE(MIN) */ + popts->tCKE_clock_pulse_width_ps + = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR); + + /* + * Window for four activates -- tFAW + * + * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only + * FIXME: varies depending upon number of column addresses or data + * FIXME: width, was considering looking at pdimm->primary_sdram_width + */ +#if defined(CONFIG_FSL_DDR1) + popts->tFAW_window_four_activates_ps = mclk_to_picos(1); + +#elif defined(CONFIG_FSL_DDR2) + /* + * x4/x8; some datasheets have 35000 + * x16 wide columns only? Use 50000? + */ + popts->tFAW_window_four_activates_ps = 37500; + +#elif defined(CONFIG_FSL_DDR3) + popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps; +#endif + popts->zq_en = 0; + popts->wrlvl_en = 0; +#if defined(CONFIG_FSL_DDR3) + /* + * due to ddr3 dimm is fly-by topology + * we suggest to enable write leveling to + * meet the tQDSS under different loading. + */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 0; +#endif + + /* + * Check interleaving configuration from environment. + * Please refer to doc/README.fsl-ddr for the detail. + * + * If memory controller interleaving is enabled, then the data + * bus widths must be programmed identically for the 2 memory + * controllers. + * + * XXX: Attempt to set both controllers to the same chip select + * interleaving mode. It will do a best effort to get the + * requested ranks interleaved together such that the result + * should be a subset of the requested configuration. + */ +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + if ((p = getenv("memctl_intlv_ctl")) != NULL) { + if (pdimm[0].n_ranks == 0) { + printf("There is no rank on CS0. Because only rank on " + "CS0 and ranks chip-select interleaved with CS0" + " are controller interleaved, force non memory " + "controller interleaving\n"); + popts->memctl_interleaving = 0; + } else { + popts->memctl_interleaving = 1; + if (strcmp(p, "cacheline") == 0) + popts->memctl_interleaving_mode = + FSL_DDR_CACHE_LINE_INTERLEAVING; + else if (strcmp(p, "page") == 0) + popts->memctl_interleaving_mode = + FSL_DDR_PAGE_INTERLEAVING; + else if (strcmp(p, "bank") == 0) + popts->memctl_interleaving_mode = + FSL_DDR_BANK_INTERLEAVING; + else if (strcmp(p, "superbank") == 0) + popts->memctl_interleaving_mode = + FSL_DDR_SUPERBANK_INTERLEAVING; + else + popts->memctl_interleaving_mode = + simple_strtoul(p, NULL, 0); + } + } +#endif + + if( ((p = getenv("ba_intlv_ctl")) != NULL) && + (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { + if (strcmp(p, "cs0_cs1") == 0) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; + else if (strcmp(p, "cs2_cs3") == 0) + popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; + else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; + else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; + else + popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0); + + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + case FSL_DDR_CS0_CS1: + if (pdimm[0].n_ranks != 2) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for " + "CS0+CS1, force non-interleaving!\n"); + } + break; + case FSL_DDR_CS2_CS3: + if (pdimm[1].n_ranks !=2){ + popts->ba_intlv_ctl = 0; + printf("Not enough bank(CS) for CS2+CS3, " + "force non-interleaving!\n"); + } + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(CS) for CS0+CS1 or " + "CS2+CS3, force non-interleaving!\n"); + } + break; + default: + popts->ba_intlv_ctl = 0; + break; + } + } + + fsl_ddr_board_options(popts, pdimm, ctrl_num); + + return 0; +} diff --git a/cpu/mpc8xxx/ddr/util.c b/arch/ppc/cpu/mpc8xxx/ddr/util.c similarity index 100% rename from cpu/mpc8xxx/ddr/util.c rename to arch/ppc/cpu/mpc8xxx/ddr/util.c diff --git a/arch/ppc/cpu/mpc8xxx/fdt.c b/arch/ppc/cpu/mpc8xxx/fdt.c new file mode 100644 index 0000000000..e68d6f336b --- /dev/null +++ b/arch/ppc/cpu/mpc8xxx/fdt.c @@ -0,0 +1,55 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This file is derived from arch/ppc/cpu/mpc85xx/cpu.c and + * arch/ppc/cpu/mpc86xx/cpu.c. Basically this file contains + * cpu specific common code for 85xx/86xx processors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +void ft_fixup_num_cores(void *blob) { + int off, num_cores, del_cores; + + del_cores = 0; + num_cores = cpu_numcores(); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + /* if we find a cpu node outside of what we expect delete it + * and reset the offset back to the start since we can't + * trust the offsets anymore + */ + if (*reg > num_cores-1) { + fdt_del_node(blob, off); + del_cores++; + off = -1; + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + debug ("%x core system found\n", num_cores); + debug ("deleted %d extra core entry entries from device tree\n", + del_cores); +} diff --git a/arch/ppc/cpu/mpc8xxx/pci_cfg.c b/arch/ppc/cpu/mpc8xxx/pci_cfg.c new file mode 100644 index 0000000000..9b7181d5b6 --- /dev/null +++ b/arch/ppc/cpu/mpc8xxx/pci_cfg.c @@ -0,0 +1,214 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct pci_info { + u32 cfg; +}; + +/* The cfg field is a bit mask in which each bit represents the value of + * cfg_IO_ports[] signal and the bit is set if the interface would be + * enabled based on the value of cfg_IO_ports[] signal + * + * On MPC86xx/PQ3 based systems: + * we extract cfg_IO_ports from GUTS register PORDEVSR + * + * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems + * without PCIe) + */ + +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8536) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8544) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | + (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .cfg = (1 << 6) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8548) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .cfg = 0, + }, + [LAW_TRGT_IF_PCI_2] = { + .cfg = 0, + }, + /* PCI_2 is always host and we dont use iosel to determine enable/disable */ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8568) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8569) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | + (1 << 8) | (1 << 0xc) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_MPC8572) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 2) | (1 << 3) | (1 << 7) | + (1 << 0xb) | (1 << 0xc) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 3) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8610) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 1) | (1 << 4), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 0) | (1 << 4), + }, +}; +#elif defined(CONFIG_MPC8641) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | + (1 << 7) | (1 << 0xe) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1012) || defined(CONFIG_P1021) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 0xe), + }, +}; +#elif defined(CONFIG_P1013) || defined(CONFIG_P1022) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) | + (1 << 0xb) | (1 << 0xd) | (1 << 0xe) | + (1 << 0xf) | (1 << 0x15) | (1 << 0x16) | + (1 << 0x17) | (1 << 0x18) | (1 << 0x19) | + (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) | + (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | + (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | + (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | + (1 << 0x18) | (1 << 0x1c), + }, + [LAW_TRGT_IF_PCIE_3] = { + .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) | + (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | + (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b), + }, +}; +#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | + (1 << 0xd) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 2) | (1 << 0xe), + }, + [LAW_TRGT_IF_PCIE_3] = { + .cfg = (1 << 2) | (1 << 4), + }, +}; +#elif defined(CONFIG_FSL_CORENET) +#else +#error Need to define pci_config_info for processor +#endif + +#ifndef CONFIG_FSL_CORENET +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) +{ + return ((1 << io_sel) & pci_config_info[trgt].cfg); +} +#endif diff --git a/arch/ppc/cpu/ppc4xx/40x_spd_sdram.c b/arch/ppc/cpu/ppc4xx/40x_spd_sdram.c new file mode 100644 index 0000000000..595d5687d6 --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/40x_spd_sdram.c @@ -0,0 +1,464 @@ +/* + * arch/ppc/cpu/ppc4xx/40x_spd_sdram.c + * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a + * SDRAM controller. Those are all current 405 PPC's. + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com + * + * Based on code by: + * + * Kenneth Johansson ,Ericsson AB. + * kenneth.johansson@etx.ericsson.se + * + * hacked up by bill hunter. fixed so we could run before + * serial_init and console_init. previous version avoided this by + * running out of cache memory during serial/console init, then running + * this code later. + * + * (C) Copyright 2002 + * Jun Gu, Artesyn Technology, jung@artesyncp.com + * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440) + +/* + * Set default values + */ +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 +#endif + +#define ONE_BILLION 1000000000 + +#define SDRAM0_CFG_DCE 0x80000000 +#define SDRAM0_CFG_SRE 0x40000000 +#define SDRAM0_CFG_PME 0x20000000 +#define SDRAM0_CFG_MEMCHK 0x10000000 +#define SDRAM0_CFG_REGEN 0x08000000 +#define SDRAM0_CFG_ECCDD 0x00400000 +#define SDRAM0_CFG_EMDULR 0x00200000 +#define SDRAM0_CFG_DRW_SHIFT (31-6) +#define SDRAM0_CFG_BRPF_SHIFT (31-8) + +#define SDRAM0_TR_CASL_SHIFT (31-8) +#define SDRAM0_TR_PTA_SHIFT (31-13) +#define SDRAM0_TR_CTP_SHIFT (31-15) +#define SDRAM0_TR_LDF_SHIFT (31-17) +#define SDRAM0_TR_RFTA_SHIFT (31-29) +#define SDRAM0_TR_RCD_SHIFT (31-31) + +#define SDRAM0_RTR_SHIFT (31-15) +#define SDRAM0_ECCCFG_SHIFT (31-11) + +/* SDRAM0_CFG enable macro */ +#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT ) + +#define SDRAM0_BXCR_SZ_MASK 0x000e0000 +#define SDRAM0_BXCR_AM_MASK 0x0000e000 + +#define SDRAM0_BXCR_SZ_SHIFT (31-14) +#define SDRAM0_BXCR_AM_SHIFT (31-18) + +#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) +#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) + +#ifdef CONFIG_SPDDRAM_SILENT +# define SPD_ERR(x) do { return 0; } while (0) +#else +# define SPD_ERR(x) do { printf(x); return(0); } while (0) +#endif + +#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) + +/* function prototypes */ +int spd_read(uint addr); + + +/* + * This function is reading data from the DIMM module EEPROM over the SPD bus + * and uses that to program the sdram controller. + * + * This works on boards that has the same schematics that the AMCC walnut has. + * + * Input: null for default I2C spd functions or a pointer to a custom function + * returning spd_data. + */ + +long int spd_sdram(int(read_spd)(uint addr)) +{ + int tmp,row,col; + int total_size,bank_size,bank_code; + int ecc_on; + int mode; + int bank_cnt; + + int sdram0_pmit=0x07c00000; +#ifndef CONFIG_405EP /* not on PPC405EP */ + int sdram0_besr0 = -1; + int sdram0_besr1 = -1; + int sdram0_eccesr = -1; +#endif + int sdram0_ecccfg; + + int sdram0_rtr=0; + int sdram0_tr=0; + + int sdram0_b0cr; + int sdram0_b1cr; + int sdram0_b2cr; + int sdram0_b3cr; + + int sdram0_cfg=0; + + int t_rp; + int t_rcd; + int t_ras; + int t_rc; + int min_cas; + + PPC4xx_SYS_INFO sys_info; + unsigned long bus_period_x_10; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + if (read_spd == 0){ + read_spd=spd_read; + /* + * Make sure I2C controller is initialized + * before continuing. + */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + } + + /* Make shure we are using SDRAM */ + if (read_spd(2) != 0x04) { + SPD_ERR("SDRAM - non SDRAM memory module found\n"); + } + + /* ------------------------------------------------------------------ + * configure memory timing register + * + * data from DIMM: + * 27 IN Row Precharge Time ( t RP) + * 29 MIN RAS to CAS Delay ( t RCD) + * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS + * -------------------------------------------------------------------*/ + + /* + * first figure out which cas latency mode to use + * use the min supported mode + */ + + tmp = read_spd(127) & 0x6; + if (tmp == 0x02) { /* only cas = 2 supported */ + min_cas = 2; +/* t_ck = read_spd(9); */ +/* t_ac = read_spd(10); */ + } else if (tmp == 0x04) { /* only cas = 3 supported */ + min_cas = 3; +/* t_ck = read_spd(9); */ +/* t_ac = read_spd(10); */ + } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ + min_cas = 2; +/* t_ck = read_spd(23); */ +/* t_ac = read_spd(24); */ + } else { + SPD_ERR("SDRAM - unsupported CAS latency \n"); + } + + /* get some timing values, t_rp,t_rcd,t_ras,t_rc + */ + t_rp = read_spd(27); + t_rcd = read_spd(29); + t_ras = read_spd(30); + t_rc = t_ras + t_rp; + + /* The following timing calcs subtract 1 before deviding. + * this has effect of using ceiling instead of floor rounding, + * and also subtracting 1 to convert number to reg value + */ + /* set up CASL */ + sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT; + /* set up PTA */ + sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT; + /* set up CTP */ + tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3; + if (tmp < 1) + tmp = 1; + sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT; + /* set LDF = 2 cycles, reg value = 1 */ + sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT; + /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */ + tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3; + if (tmp < 0) + tmp = 0; + if (tmp > 6) + tmp = 6; + sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT; + /* set RCD = t_rcd/bus_period*/ + sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ; + + + /*------------------------------------------------------------------ + * configure RTR register + * -------------------------------------------------------------------*/ + row = read_spd(3); + col = read_spd(4); + tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */ + switch (tmp) { + case 0x00: + tmp = 15625; + break; + case 0x01: + tmp = 15625 / 4; + break; + case 0x02: + tmp = 15625 / 2; + break; + case 0x03: + tmp = 15625 * 2; + break; + case 0x04: + tmp = 15625 * 4; + break; + case 0x05: + tmp = 15625 * 8; + break; + default: + SPD_ERR("SDRAM - Bad refresh period \n"); + } + /* convert from nsec to bus cycles */ + tmp = (tmp * 10) / bus_period_x_10; + sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; + + /*------------------------------------------------------------------ + * determine the number of banks used + * -------------------------------------------------------------------*/ + /* byte 7:6 is module data width */ + if (read_spd(7) != 0) + SPD_ERR("SDRAM - unsupported module width\n"); + tmp = read_spd(6); + if (tmp < 32) + SPD_ERR("SDRAM - unsupported module width\n"); + else if (tmp < 64) + bank_cnt = 1; /* one bank per sdram side */ + else if (tmp < 73) + bank_cnt = 2; /* need two banks per side */ + else if (tmp < 161) + bank_cnt = 4; /* need four banks per side */ + else + SPD_ERR("SDRAM - unsupported module width\n"); + + /* byte 5 is the module row count (refered to as dimm "sides") */ + tmp = read_spd(5); + if (tmp == 1) + ; + else if (tmp==2) + bank_cnt *= 2; + else if (tmp==4) + bank_cnt *= 4; + else + bank_cnt = 8; /* 8 is an error code */ + + if (bank_cnt > 4) /* we only have 4 banks to work with */ + SPD_ERR("SDRAM - unsupported module rows for this width\n"); + + /* now check for ECC ability of module. We only support ECC + * on 32 bit wide devices with 8 bit ECC. + */ + if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { + sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; + ecc_on = 1; + } else { + sdram0_ecccfg = 0; + ecc_on = 0; + } + + /*------------------------------------------------------------------ + * calculate total size + * -------------------------------------------------------------------*/ + /* calculate total size and do sanity check */ + tmp = read_spd(31); + total_size = 1 << 22; /* total_size = 4MB */ + /* now multiply 4M by the smallest device row density */ + /* note that we don't support asymetric rows */ + while (((tmp & 0x0001) == 0) && (tmp != 0)) { + total_size = total_size << 1; + tmp = tmp >> 1; + } + total_size *= read_spd(5); /* mult by module rows (dimm sides) */ + + /*------------------------------------------------------------------ + * map rows * cols * banks to a mode + * -------------------------------------------------------------------*/ + + switch (row) { + case 11: + switch (col) { + case 8: + mode=4; /* mode 5 */ + break; + case 9: + case 10: + mode=0; /* mode 1 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + case 12: + switch (col) { + case 8: + mode=3; /* mode 4 */ + break; + case 9: + case 10: + mode=1; /* mode 2 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + case 13: + switch (col) { + case 8: + mode=5; /* mode 6 */ + break; + case 9: + case 10: + if (read_spd(17) == 2) + mode = 6; /* mode 7 */ + else + mode = 2; /* mode 3 */ + break; + case 11: + mode = 2; /* mode 3 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + + /*------------------------------------------------------------------ + * using the calculated values, compute the bank + * config register values. + * -------------------------------------------------------------------*/ + sdram0_b1cr = 0; + sdram0_b2cr = 0; + sdram0_b3cr = 0; + + /* compute the size of each bank */ + bank_size = total_size / bank_cnt; + /* convert bank size to bank size code for ppc4xx + by takeing log2(bank_size) - 22 */ + tmp = bank_size; /* start with tmp = bank_size */ + bank_code = 0; /* and bank_code = 0 */ + while (tmp > 1) { /* this takes log2 of tmp */ + bank_code++; /* and stores result in bank_code */ + tmp = tmp >> 1; + } /* bank_code is now log2(bank_size) */ + bank_code -= 22; /* subtract 22 to get the code */ + + tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; + sdram0_b0cr = (bank_size * 0) | tmp; +#ifndef CONFIG_405EP /* not on PPC405EP */ + if (bank_cnt > 1) + sdram0_b2cr = (bank_size * 1) | tmp; + if (bank_cnt > 2) + sdram0_b1cr = (bank_size * 2) | tmp; + if (bank_cnt > 3) + sdram0_b3cr = (bank_size * 3) | tmp; +#else + /* PPC405EP chip only supports two SDRAM banks */ + if (bank_cnt > 1) + sdram0_b1cr = (bank_size * 1) | tmp; + if (bank_cnt > 2) + total_size = 2 * bank_size; +#endif + + /* + * enable sdram controller DCE=1 + * enable burst read prefetch to 32 bytes BRPF=2 + * leave other functions off + */ + + /*------------------------------------------------------------------ + * now that we've done our calculations, we are ready to + * program all the registers. + * -------------------------------------------------------------------*/ + + /* disable memcontroller so updates work */ + mtsdram(SDRAM0_CFG, 0); + +#ifndef CONFIG_405EP /* not on PPC405EP */ + mtsdram(SDRAM0_BESR0, sdram0_besr0); + mtsdram(SDRAM0_BESR1, sdram0_besr1); + mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg); + mtsdram(SDRAM0_ECCESR, sdram0_eccesr); +#endif + mtsdram(SDRAM0_RTR, sdram0_rtr); + mtsdram(SDRAM0_PMIT, sdram0_pmit); + mtsdram(SDRAM0_B0CR, sdram0_b0cr); + mtsdram(SDRAM0_B1CR, sdram0_b1cr); +#ifndef CONFIG_405EP /* not on PPC405EP */ + mtsdram(SDRAM0_B2CR, sdram0_b2cr); + mtsdram(SDRAM0_B3CR, sdram0_b3cr); +#endif + mtsdram(SDRAM0_TR, sdram0_tr); + + /* SDRAM have a power on delay, 500 micro should do */ + udelay(500); + sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; + if (ecc_on) + sdram0_cfg |= SDRAM0_CFG_MEMCHK; + mtsdram(SDRAM0_CFG, sdram0_cfg); + + return (total_size); +} + +int spd_read(uint addr) +{ + uchar data[2]; + + if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0) + return (int)data[0]; + else + return 0; +} + +#endif /* CONFIG_SPD_EEPROM */ diff --git a/arch/ppc/cpu/ppc4xx/44x_spd_ddr.c b/arch/ppc/cpu/ppc4xx/44x_spd_ddr.c new file mode 100644 index 0000000000..9d1994f99e --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/44x_spd_ddr.c @@ -0,0 +1,1248 @@ +/* + * arch/ppc/cpu/ppc4xx/44x_spd_ddr.c + * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a + * DDR controller. Those are 440GP/GX/EP/GR. + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com + * + * Based on code by: + * + * Kenneth Johansson ,Ericsson AB. + * kenneth.johansson@etx.ericsson.se + * + * hacked up by bill hunter. fixed so we could run before + * serial_init and console_init. previous version avoided this by + * running out of cache memory during serial/console init, then running + * this code later. + * + * (C) Copyright 2002 + * Jun Gu, Artesyn Technology, jung@artesyncp.com + * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. + * + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include + +#include "ecc.h" + +#if defined(CONFIG_SPD_EEPROM) && \ + (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR)) + +/* + * Set default values + */ +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 +#endif + +#define ONE_BILLION 1000000000 + +/* + * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed + */ +void __spd_ddr_init_hang (void) +{ + hang (); +} +void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); + +/*-----------------------------------------------------------------------------+ + | General Definition + +-----------------------------------------------------------------------------*/ +#define DEFAULT_SPD_ADDR1 0x53 +#define DEFAULT_SPD_ADDR2 0x52 +#define MAXBANKS 4 /* at most 4 dimm banks */ +#define MAX_SPD_BYTES 256 +#define NUMHALFCYCLES 4 +#define NUMMEMTESTS 8 +#define NUMMEMWORDS 8 +#define MAXBXCR 4 +#define TRUE 1 +#define FALSE 0 + +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory + * region. Right now the cache should still be disabled in U-Boot because of the + * EMAC driver, that need it's buffer descriptor to be located in non cached + * memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CONFIG_4xx_DCACHE in the board config file and this code should setup + * everything correctly. + */ +#ifdef CONFIG_4xx_DCACHE +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#endif + +/* bank_parms is used to sort the bank sizes by descending order */ +struct bank_param { + unsigned long cr; + unsigned long bank_size_bytes; +}; + +typedef struct bank_param BANKPARMS; + +#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM +extern const unsigned char cfg_simulate_spd_eeprom[128]; +#endif + +static unsigned char spd_read(uchar chip, uint addr); +static void get_spd_info(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void check_mem_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void check_volt_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_cfg0(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_cfg1(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_rtr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_tr0(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_tr1(void); + +static unsigned long program_bxcr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); + +/* + * This function is reading data from the DIMM module EEPROM over the SPD bus + * and uses that to program the sdram controller. + * + * This works on boards that has the same schematics that the AMCC walnut has. + * + * BUG: Don't handle ECC memory + * BUG: A few values in the TR register is currently hardcoded + */ +long int spd_sdram(void) { + unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; + unsigned long dimm_populated[sizeof(iic0_dimm_addr)]; + unsigned long total_size; + unsigned long cfg0; + unsigned long mcsts; + unsigned long num_dimm_banks; /* on board dimm banks */ + + num_dimm_banks = sizeof(iic0_dimm_addr); + + /* + * Make sure I2C controller is initialized + * before continuing. + */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + /* + * Read the SPD information using I2C interface. Check to see if the + * DIMM slots are populated. + */ + get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * Check the memory type for the dimms plugged. + */ + check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * Check the voltage type for the dimms plugged. + */ + check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + /* + * Soft-reset SDRAM controller. + */ + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); +#endif + + /* + * program 440GP SDRAM controller options (SDRAM0_CFG0) + */ + program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program 440GP SDRAM controller options (SDRAM0_CFG1) + */ + program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program SDRAM refresh register (SDRAM0_RTR) + */ + program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program SDRAM Timing Register 0 (SDRAM0_TR0) + */ + program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program the BxCR registers to find out total sdram installed + */ + total_size = program_bxcr(dimm_populated, iic0_dimm_addr, + num_dimm_banks); + +#ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */ + /* and program tlb entries for this size (dynamic) */ + program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE); +#endif + + /* + * program SDRAM Clock Timing Register (SDRAM0_CLKTR) + */ + mtsdram(SDRAM0_CLKTR, 0x40000000); + + /* + * delay to ensure 200 usec has elapsed + */ + udelay(400); + + /* + * enable the memory controller + */ + mfsdram(SDRAM0_CFG0, cfg0); + mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN); + + /* + * wait for SDRAM_CFG0_DC_EN to complete + */ + while (1) { + mfsdram(SDRAM0_MCSTS, mcsts); + if ((mcsts & SDRAM_MCSTS_MRSC) != 0) + break; + } + + /* + * program SDRAM Timing Register 1, adding some delays + */ + program_tr1(); + +#ifdef CONFIG_DDR_ECC + /* + * If ecc is enabled, initialize the parity bits. + */ + ecc_init(CONFIG_SYS_SDRAM_BASE, total_size); +#endif + + return total_size; +} + +static unsigned char spd_read(uchar chip, uint addr) +{ + unsigned char data[2]; + +#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM + if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) { + /* + * Onboard spd eeprom requested -> simulate values + */ + return cfg_simulate_spd_eeprom[addr]; + } +#endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */ + + if (i2c_probe(chip) == 0) { + if (i2c_read(chip, addr, 1, data, 1) == 0) { + return data[0]; + } + } + + return 0; +} + +static void get_spd_info(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_found; + unsigned char num_of_bytes; + unsigned char total_size; + + dimm_found = FALSE; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + num_of_bytes = 0; + total_size = 0; + + num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); + total_size = spd_read(iic0_dimm_addr[dimm_num], 1); + + if ((num_of_bytes != 0) && (total_size != 0)) { + dimm_populated[dimm_num] = TRUE; + dimm_found = TRUE; + debug("DIMM slot %lu: populated\n", dimm_num); + } else { + dimm_populated[dimm_num] = FALSE; + debug("DIMM slot %lu: Not populated\n", dimm_num); + } + } + + if (dimm_found == FALSE) { + printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); + spd_ddr_init_hang (); + } +} + +static void check_mem_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned char dimm_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); + switch (dimm_type) { + case 7: + debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); + break; + default: + printf("ERROR: Unsupported DIMM detected in slot %lu.\n", + dimm_num); + printf("Only DDR SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + } + } + } +} + +static void check_volt_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long voltage_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); + if (voltage_type != 0x04) { + printf("ERROR: DIMM %lu with unsupported voltage level.\n", + dimm_num); + spd_ddr_init_hang (); + } else { + debug("DIMM %lu voltage level supported.\n", dimm_num); + } + break; + } + } +} + +static void program_cfg0(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long cfg0; + unsigned long ecc_enabled; + unsigned char ecc; + unsigned char attributes; + unsigned long data_width; + unsigned long dimm_32bit; + unsigned long dimm_64bit; + + /* + * get Memory Controller Options 0 data + */ + mfsdram(SDRAM0_CFG0, cfg0); + + /* + * clear bits + */ + cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK | + SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD | + SDRAM_CFG0_DMWD_MASK | + SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP); + + + /* + * FIXME: assume the DDR SDRAMs in both banks are the same + */ + ecc_enabled = TRUE; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + ecc = spd_read(iic0_dimm_addr[dimm_num], 11); + if (ecc != 0x02) { + ecc_enabled = FALSE; + } + + /* + * program Registered DIMM Enable + */ + attributes = spd_read(iic0_dimm_addr[dimm_num], 21); + if ((attributes & 0x02) != 0x00) { + cfg0 |= SDRAM_CFG0_RDEN; + } + + /* + * program DDR SDRAM Data Width + */ + data_width = + (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) + + (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8); + if (data_width == 64 || data_width == 72) { + dimm_64bit = TRUE; + cfg0 |= SDRAM_CFG0_DMWD_64; + } else if (data_width == 32 || data_width == 40) { + dimm_32bit = TRUE; + cfg0 |= SDRAM_CFG0_DMWD_32; + } else { + printf("WARNING: DIMM with datawidth of %lu bits.\n", + data_width); + printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); + spd_ddr_init_hang (); + } + break; + } + } + + /* + * program Memory Data Error Checking + */ + if (ecc_enabled == TRUE) { + cfg0 |= SDRAM_CFG0_MCHK_GEN; + } else { + cfg0 |= SDRAM_CFG0_MCHK_NON; + } + + /* + * program Page Management Unit (0 == enabled) + */ + cfg0 &= ~SDRAM_CFG0_PMUD; + + /* + * program Memory Controller Options 0 + * Note: DCEN must be enabled after all DDR SDRAM controller + * configuration registers get initialized. + */ + mtsdram(SDRAM0_CFG0, cfg0); +} + +static void program_cfg1(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long cfg1; + mfsdram(SDRAM0_CFG1, cfg1); + + /* + * Self-refresh exit, disable PM + */ + cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN); + + /* + * program Memory Controller Options 1 + */ + mtsdram(SDRAM0_CFG1, cfg1); +} + +static void program_rtr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long bus_period_x_10; + unsigned long refresh_rate = 0; + unsigned char refresh_rate_type; + unsigned long refresh_interval; + unsigned long sdram_rtr; + PPC4xx_SYS_INFO sys_info; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); + switch (refresh_rate_type) { + case 0x00: + refresh_rate = 15625; + break; + case 0x01: + refresh_rate = 15625/4; + break; + case 0x02: + refresh_rate = 15625/2; + break; + case 0x03: + refresh_rate = 15626*2; + break; + case 0x04: + refresh_rate = 15625*4; + break; + case 0x05: + refresh_rate = 15625*8; + break; + default: + printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n", + dimm_num); + printf("Replace the DIMM module with a supported DIMM.\n"); + break; + } + + break; + } + } + + refresh_interval = refresh_rate * 10 / bus_period_x_10; + sdram_rtr = (refresh_interval & 0x3ff8) << 16; + + /* + * program Refresh Timer Register (SDRAM0_RTR) + */ + mtsdram(SDRAM0_RTR, sdram_rtr); +} + +static void program_tr0(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long tr0; + unsigned char wcsbc; + unsigned char t_rp_ns; + unsigned char t_rcd_ns; + unsigned char t_ras_ns; + unsigned long t_rp_clk; + unsigned long t_ras_rcd_clk; + unsigned long t_rcd_clk; + unsigned long t_rfc_clk; + unsigned long plb_check; + unsigned char cas_bit; + unsigned long cas_index; + unsigned char cas_2_0_available; + unsigned char cas_2_5_available; + unsigned char cas_3_0_available; + unsigned long cycle_time_ns_x_10[3]; + unsigned long tcyc_3_0_ns_x_10; + unsigned long tcyc_2_5_ns_x_10; + unsigned long tcyc_2_0_ns_x_10; + unsigned long tcyc_reg; + unsigned long bus_period_x_10; + PPC4xx_SYS_INFO sys_info; + unsigned long residue; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + /* + * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits + */ + mfsdram(SDRAM0_TR0, tr0); + tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | + SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | + SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | + SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK); + + /* + * initialization + */ + wcsbc = 0; + t_rp_ns = 0; + t_rcd_ns = 0; + t_ras_ns = 0; + cas_2_0_available = TRUE; + cas_2_5_available = TRUE; + cas_3_0_available = TRUE; + tcyc_2_0_ns_x_10 = 0; + tcyc_2_5_ns_x_10 = 0; + tcyc_3_0_ns_x_10 = 0; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); + t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; + t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; + t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30); + cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); + + for (cas_index = 0; cas_index < 3; cas_index++) { + switch (cas_index) { + case 0: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); + break; + case 1: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); + break; + default: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); + break; + } + + if ((tcyc_reg & 0x0F) >= 10) { + printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", + dimm_num); + spd_ddr_init_hang (); + } + + cycle_time_ns_x_10[cas_index] = + (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F); + } + + cas_index = 0; + + if ((cas_bit & 0x80) != 0) { + cas_index += 3; + } else if ((cas_bit & 0x40) != 0) { + cas_index += 2; + } else if ((cas_bit & 0x20) != 0) { + cas_index += 1; + } + + if (((cas_bit & 0x10) != 0) && (cas_index < 3)) { + tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_3_0_available = FALSE; + } + + if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { + tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_2_5_available = FALSE; + } + + if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { + tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_2_0_available = FALSE; + } + + break; + } + } + + /* + * Program SD_WR and SD_WCSBC fields + */ + tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ + switch (wcsbc) { + case 0: + tr0 |= SDRAM_TR0_SDWD_0_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDWD_1_CLK; + break; + } + + /* + * Program SD_CASL field + */ + if ((cas_2_0_available == TRUE) && + (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_2_0_CLK; + } else if ((cas_2_5_available == TRUE) && + (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_2_5_CLK; + } else if ((cas_3_0_available == TRUE) && + (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_3_0_CLK; + } else { + printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); + printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); + printf("Make sure the PLB speed is within the supported range.\n"); + spd_ddr_init_hang (); + } + + /* + * Calculate Trp in clock cycles and round up if necessary + * Program SD_PTA field + */ + t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION; + plb_check = ONE_BILLION * t_rp_clk / t_rp_ns; + if (sys_info.freqPLB != plb_check) { + t_rp_clk++; + } + switch ((unsigned long)t_rp_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDPA_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDPA_3_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDPA_4_CLK; + break; + } + + /* + * Program SD_CTP field + */ + t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION; + plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns); + if (sys_info.freqPLB != plb_check) { + t_ras_rcd_clk++; + } + switch (t_ras_rcd_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDCP_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDCP_3_CLK; + break; + case 4: + tr0 |= SDRAM_TR0_SDCP_4_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDCP_5_CLK; + break; + } + + /* + * Program SD_LDF field + */ + tr0 |= SDRAM_TR0_SDLD_2_CLK; + + /* + * Program SD_RFTA field + * FIXME tRFC hardcoded as 75 nanoseconds + */ + t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75); + residue = sys_info.freqPLB % (ONE_BILLION / 75); + if (residue >= (ONE_BILLION / 150)) { + t_rfc_clk++; + } + switch (t_rfc_clk) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + tr0 |= SDRAM_TR0_SDRA_6_CLK; + break; + case 7: + tr0 |= SDRAM_TR0_SDRA_7_CLK; + break; + case 8: + tr0 |= SDRAM_TR0_SDRA_8_CLK; + break; + case 9: + tr0 |= SDRAM_TR0_SDRA_9_CLK; + break; + case 10: + tr0 |= SDRAM_TR0_SDRA_10_CLK; + break; + case 11: + tr0 |= SDRAM_TR0_SDRA_11_CLK; + break; + case 12: + tr0 |= SDRAM_TR0_SDRA_12_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDRA_13_CLK; + break; + } + + /* + * Program SD_RCD field + */ + t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION; + plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns; + if (sys_info.freqPLB != plb_check) { + t_rcd_clk++; + } + switch (t_rcd_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDRD_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDRD_3_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDRD_4_CLK; + break; + } + + debug("tr0: %x\n", tr0); + mtsdram(SDRAM0_TR0, tr0); +} + +static int short_mem_test(void) +{ + unsigned long i, j; + unsigned long bxcr_num; + unsigned long *membase; + const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { + {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, + {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, + {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, + {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, + {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, + {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, + {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, + {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; + + for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { + mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2)); + if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { + /* Bank is enabled */ + membase = (unsigned long*) + (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); + + /* + * Run the short memory test + */ + for (i = 0; i < NUMMEMTESTS; i++) { + for (j = 0; j < NUMMEMWORDS; j++) { + /* printf("bank enabled base:%x\n", &membase[j]); */ + membase[j] = test[i][j]; + ppcDcbf((unsigned long)&(membase[j])); + } + + for (j = 0; j < NUMMEMWORDS; j++) { + if (membase[j] != test[i][j]) { + ppcDcbf((unsigned long)&(membase[j])); + return 0; + } + ppcDcbf((unsigned long)&(membase[j])); + } + + if (j < NUMMEMWORDS) + return 0; + } + + /* + * see if the rdclt value passed + */ + if (i < NUMMEMTESTS) + return 0; + } + } + + return 1; +} + +static void program_tr1(void) +{ + unsigned long tr0; + unsigned long tr1; + unsigned long cfg0; + unsigned long ecc_temp; + unsigned long dlycal; + unsigned long dly_val; + unsigned long k; + unsigned long max_pass_length; + unsigned long current_pass_length; + unsigned long current_fail_length; + unsigned long current_start; + unsigned long rdclt; + unsigned long rdclt_offset; + long max_start; + long max_end; + long rdclt_average; + unsigned char window_found; + unsigned char fail_found; + unsigned char pass_found; + PPC4xx_SYS_INFO sys_info; + + /* + * get the board info + */ + get_sys_info(&sys_info); + + /* + * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits + */ + mfsdram(SDRAM0_TR1, tr1); + tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | + SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); + + mfsdram(SDRAM0_TR0, tr0); + if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && + (sys_info.freqPLB > 100000000)) { + tr1 |= SDRAM_TR1_RDSS_TR2; + tr1 |= SDRAM_TR1_RDSL_STAGE3; + tr1 |= SDRAM_TR1_RDCD_RCD_1_2; + } else { + tr1 |= SDRAM_TR1_RDSS_TR1; + tr1 |= SDRAM_TR1_RDSL_STAGE2; + tr1 |= SDRAM_TR1_RDCD_RCD_0_0; + } + + /* + * save CFG0 ECC setting to a temporary variable and turn ECC off + */ + mfsdram(SDRAM0_CFG0, cfg0); + ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; + mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); + + /* + * get the delay line calibration register value + */ + mfsdram(SDRAM0_DLYCAL, dlycal); + dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; + + max_pass_length = 0; + max_start = 0; + max_end = 0; + current_pass_length = 0; + current_fail_length = 0; + current_start = 0; + rdclt_offset = 0; + window_found = FALSE; + fail_found = FALSE; + pass_found = FALSE; + debug("Starting memory test "); + + for (k = 0; k < NUMHALFCYCLES; k++) { + for (rdclt = 0; rdclt < dly_val; rdclt++) { + /* + * Set the timing reg for the test. + */ + mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); + + if (short_mem_test()) { + if (fail_found == TRUE) { + pass_found = TRUE; + if (current_pass_length == 0) { + current_start = rdclt_offset + rdclt; + } + + current_fail_length = 0; + current_pass_length++; + + if (current_pass_length > max_pass_length) { + max_pass_length = current_pass_length; + max_start = current_start; + max_end = rdclt_offset + rdclt; + } + } + } else { + current_pass_length = 0; + current_fail_length++; + + if (current_fail_length >= (dly_val>>2)) { + if (fail_found == FALSE) { + fail_found = TRUE; + } else if (pass_found == TRUE) { + window_found = TRUE; + break; + } + } + } + } + debug("."); + + if (window_found == TRUE) { + break; + } + + tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; + rdclt_offset += dly_val; + } + debug("\n"); + + /* + * make sure we find the window + */ + if (window_found == FALSE) { + printf("ERROR: Cannot determine a common read delay.\n"); + spd_ddr_init_hang (); + } + + /* + * restore the orignal ECC setting + */ + mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); + + /* + * set the SDRAM TR1 RDCD value + */ + tr1 &= ~SDRAM_TR1_RDCD_MASK; + if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) { + tr1 |= SDRAM_TR1_RDCD_RCD_1_2; + } else { + tr1 |= SDRAM_TR1_RDCD_RCD_0_0; + } + + /* + * set the SDRAM TR1 RDCLT value + */ + tr1 &= ~SDRAM_TR1_RDCT_MASK; + while (max_end >= (dly_val << 1)) { + max_end -= (dly_val << 1); + max_start -= (dly_val << 1); + } + + rdclt_average = ((max_start + max_end) >> 1); + + if (rdclt_average < 0) { + rdclt_average = 0; + } + + if (rdclt_average >= dly_val) { + rdclt_average -= dly_val; + tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; + } + tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average); + + debug("tr1: %x\n", tr1); + + /* + * program SDRAM Timing Register 1 TR1 + */ + mtsdram(SDRAM0_TR1, tr1); +} + +static unsigned long program_bxcr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long bank_base_addr; + unsigned long cr; + unsigned long i; + unsigned long j; + unsigned long temp; + unsigned char num_row_addr; + unsigned char num_col_addr; + unsigned char num_banks; + unsigned char bank_size_id; + unsigned long ctrl_bank_num[MAXBANKS]; + unsigned long bx_cr_num; + unsigned long largest_size_index; + unsigned long largest_size; + unsigned long current_size_index; + BANKPARMS bank_parms[MAXBXCR]; + unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */ + unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/ + + /* + * Set the BxCR regs. First, wipe out the bank config registers. + */ + for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { + mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2)); + mtdcr(SDRAM0_CFGDATA, 0x00000000); + bank_parms[bx_cr_num].bank_size_bytes = 0; + } + +#ifdef CONFIG_BAMBOO + /* + * This next section is hardware dependent and must be programmed + * to match the hardware. For bamboo, the following holds... + * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard) + * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1 + * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1 + * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3 + * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM + */ + ctrl_bank_num[0] = 0; + ctrl_bank_num[1] = 1; + ctrl_bank_num[2] = 3; +#else + /* + * Ocotea, Ebony and the other IBM/AMCC eval boards have + * 2 DIMM slots with each max 2 banks + */ + ctrl_bank_num[0] = 0; + ctrl_bank_num[1] = 2; +#endif + + /* + * reset the bank_base address + */ + bank_base_addr = CONFIG_SYS_SDRAM_BASE; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); + num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); + num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); + bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); + debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num, + num_row_addr, num_col_addr, num_banks); + + /* + * Set the SDRAM0_BxCR regs + */ + cr = 0; + switch (bank_size_id) { + case 0x02: + cr |= SDRAM_BXCR_SDSZ_8; + break; + case 0x04: + cr |= SDRAM_BXCR_SDSZ_16; + break; + case 0x08: + cr |= SDRAM_BXCR_SDSZ_32; + break; + case 0x10: + cr |= SDRAM_BXCR_SDSZ_64; + break; + case 0x20: + cr |= SDRAM_BXCR_SDSZ_128; + break; + case 0x40: + cr |= SDRAM_BXCR_SDSZ_256; + break; + case 0x80: + cr |= SDRAM_BXCR_SDSZ_512; + break; + default: + printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", + dimm_num); + printf("ERROR: Unsupported value for the banksize: %d.\n", + bank_size_id); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + } + + switch (num_col_addr) { + case 0x08: + cr |= SDRAM_BXCR_SDAM_1; + break; + case 0x09: + cr |= SDRAM_BXCR_SDAM_2; + break; + case 0x0A: + cr |= SDRAM_BXCR_SDAM_3; + break; + case 0x0B: + cr |= SDRAM_BXCR_SDAM_4; + break; + default: + printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", + dimm_num); + printf("ERROR: Unsupported value for number of " + "column addresses: %d.\n", num_col_addr); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + } + + /* + * enable the bank + */ + cr |= SDRAM_BXCR_SDBE; + + for (i = 0; i < num_banks; i++) { + bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = + (4 << 20) * bank_size_id; + bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; + debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n", + dimm_num, i, ctrl_bank_num[dimm_num]+i, + bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes); + } + } + } + + /* Initialize sort tables */ + for (i = 0; i < MAXBXCR; i++) { + sorted_bank_num[i] = i; + sorted_bank_size[i] = bank_parms[i].bank_size_bytes; + } + + for (i = 0; i < MAXBXCR-1; i++) { + largest_size = sorted_bank_size[i]; + largest_size_index = 255; + + /* Find the largest remaining value */ + for (j = i + 1; j < MAXBXCR; j++) { + if (sorted_bank_size[j] > largest_size) { + /* Save largest remaining value and its index */ + largest_size = sorted_bank_size[j]; + largest_size_index = j; + } + } + + if (largest_size_index != 255) { + /* Swap the current and largest values */ + current_size_index = sorted_bank_num[largest_size_index]; + sorted_bank_size[largest_size_index] = sorted_bank_size[i]; + sorted_bank_size[i] = largest_size; + sorted_bank_num[largest_size_index] = sorted_bank_num[i]; + sorted_bank_num[i] = current_size_index; + } + } + + /* Set the SDRAM0_BxCR regs thanks to sort tables */ + for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { + if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { + mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2)); + temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | + SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); + temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | + bank_parms[sorted_bank_num[bx_cr_num]].cr; + mtdcr(SDRAM0_CFGDATA, temp); + bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; + debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp); + } + } + + return(bank_base_addr); +} +#endif /* CONFIG_SPD_EEPROM */ diff --git a/arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c new file mode 100644 index 0000000000..ea6c2ac770 --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c @@ -0,0 +1,3174 @@ +/* + * arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c + * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a + * DDR2 controller (non Denali Core). Those currently are: + * + * 405: 405EX(r) + * 440/460: 440SP/440SPe/460EX/460GT + * + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson + + * (C) Copyright 2007-2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * COPYRIGHT AMCC CORPORATION 2004 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ecc.h" + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) + +#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \ + do { \ + u32 data; \ + mfsdram(SDRAM_##mnemonic, data); \ + printf("%20s[%02x] = 0x%08X\n", \ + "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ + } while (0) + +#define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \ + do { \ + u32 data; \ + data = mfdcr(SDRAM_##mnemonic); \ + printf("%20s[%02x] = 0x%08X\n", \ + "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ + } while (0) + +#if defined(CONFIG_440) +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 + * memory region. Right now the cache should still be disabled in U-Boot + * because of the EMAC driver, that need its buffer descriptor to be located + * in non cached memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CONFIG_4xx_DCACHE in the board config file and this code should setup + * everything correctly. + */ +#ifdef CONFIG_4xx_DCACHE +/* enable caching on SDRAM */ +#define MY_TLB_WORD2_I_ENABLE 0 +#else +/* disable caching on SDRAM */ +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE +#endif /* CONFIG_4xx_DCACHE */ + +void dcbz_area(u32 start_address, u32 num_bytes); +#endif /* CONFIG_440 */ + +#define MAXRANKS 4 +#define MAXBXCF 4 + +#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) + +#if !defined(CONFIG_NAND_SPL) +/*-----------------------------------------------------------------------------+ + * sdram_memsize + *-----------------------------------------------------------------------------*/ +phys_size_t sdram_memsize(void) +{ + phys_size_t mem_size; + unsigned long mcopt2; + unsigned long mcstat; + unsigned long mb0cf; + unsigned long sdsz; + unsigned long i; + + mem_size = 0; + + mfsdram(SDRAM_MCOPT2, mcopt2); + mfsdram(SDRAM_MCSTAT, mcstat); + + /* DDR controller must be enabled and not in self-refresh. */ + /* Otherwise memsize is zero. */ + if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) + && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) + && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) + == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { + for (i = 0; i < MAXBXCF; i++) { + mfsdram(SDRAM_MB0CF + (i << 2), mb0cf); + /* Banks enabled */ + if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { +#if defined(CONFIG_440) + sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK; +#else + sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK; +#endif + switch(sdsz) { + case SDRAM_RXBAS_SDSZ_8: + mem_size+=8; + break; + case SDRAM_RXBAS_SDSZ_16: + mem_size+=16; + break; + case SDRAM_RXBAS_SDSZ_32: + mem_size+=32; + break; + case SDRAM_RXBAS_SDSZ_64: + mem_size+=64; + break; + case SDRAM_RXBAS_SDSZ_128: + mem_size+=128; + break; + case SDRAM_RXBAS_SDSZ_256: + mem_size+=256; + break; + case SDRAM_RXBAS_SDSZ_512: + mem_size+=512; + break; + case SDRAM_RXBAS_SDSZ_1024: + mem_size+=1024; + break; + case SDRAM_RXBAS_SDSZ_2048: + mem_size+=2048; + break; + case SDRAM_RXBAS_SDSZ_4096: + mem_size+=4096; + break; + default: + printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n" + , sdsz); + mem_size=0; + break; + } + } + } + } + + return mem_size << 20; +} + +/*-----------------------------------------------------------------------------+ + * is_ecc_enabled + *-----------------------------------------------------------------------------*/ +static unsigned long is_ecc_enabled(void) +{ + unsigned long val; + + mfsdram(SDRAM_MCOPT1, val); + + return SDRAM_MCOPT1_MCHK_CHK_DECODE(val); +} + +/*-----------------------------------------------------------------------------+ + * board_add_ram_info + *-----------------------------------------------------------------------------*/ +void board_add_ram_info(int use_default) +{ + PPC4xx_SYS_INFO board_cfg; + u32 val; + + if (is_ecc_enabled()) + puts(" (ECC"); + else + puts(" (ECC not"); + + get_sys_info(&board_cfg); + +#if defined(CONFIG_405EX) + val = board_cfg.freqPLB; +#else + mfsdr(SDR0_DDR0, val); + val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1); +#endif + printf(" enabled, %d MHz", (val * 2) / 1000000); + + mfsdram(SDRAM_MMODE, val); + val = (val & SDRAM_MMODE_DCL_MASK) >> 4; + printf(", CL%d)", val); +} +#endif /* !CONFIG_NAND_SPL */ + +#if defined(CONFIG_SPD_EEPROM) + +/*-----------------------------------------------------------------------------+ + * Defines + *-----------------------------------------------------------------------------*/ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define SDRAM_DDR1 1 +#define SDRAM_DDR2 2 +#define SDRAM_NONE 0 + +#define MAXDIMMS 2 +#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ + +#define ONE_BILLION 1000000000 + +#define CMD_NOP (7 << 19) +#define CMD_PRECHARGE (2 << 19) +#define CMD_REFRESH (1 << 19) +#define CMD_EMR (0 << 19) +#define CMD_READ (5 << 19) +#define CMD_WRITE (4 << 19) + +#define SELECT_MR (0 << 16) +#define SELECT_EMR (1 << 16) +#define SELECT_EMR2 (2 << 16) +#define SELECT_EMR3 (3 << 16) + +/* MR */ +#define DLL_RESET 0x00000100 + +#define WRITE_RECOV_2 (1 << 9) +#define WRITE_RECOV_3 (2 << 9) +#define WRITE_RECOV_4 (3 << 9) +#define WRITE_RECOV_5 (4 << 9) +#define WRITE_RECOV_6 (5 << 9) + +#define BURST_LEN_4 0x00000002 + +/* EMR */ +#define ODT_0_OHM 0x00000000 +#define ODT_50_OHM 0x00000044 +#define ODT_75_OHM 0x00000004 +#define ODT_150_OHM 0x00000040 + +#define ODS_FULL 0x00000000 +#define ODS_REDUCED 0x00000002 +#define OCD_CALIB_DEF 0x00000380 + +/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */ +#define ODT_EB0R (0x80000000 >> 8) +#define ODT_EB0W (0x80000000 >> 7) +#define CALC_ODT_R(n) (ODT_EB0R << (n << 1)) +#define CALC_ODT_W(n) (ODT_EB0W << (n << 1)) +#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n)) + +/* Defines for the Read Cycle Delay test */ +#define NUMMEMTESTS 8 +#define NUMMEMWORDS 8 +#define NUMLOOPS 64 /* memory test loops */ + +/* + * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. + * To support such configurations, we "only" map the first 2GB via the TLB's. We + * need some free virtual address space for the remaining peripherals like, SoC + * devices, FLASH etc. + * + * Note that ECC is currently not supported on configurations with more than 2GB + * SDRAM. This is because we only map the first 2GB on such systems, and therefore + * the ECC parity byte of the remaining area can't be written. + */ + +/* + * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed + */ +void __spd_ddr_init_hang (void) +{ + hang (); +} +void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); + +/* + * To provide an interface for board specific config values in this common + * DDR setup code, we implement he "weak" default functions here. They return + * the default value back to the caller. + * + * Please see include/configs/yucca.h for an example fora board specific + * implementation. + */ +u32 __ddr_wrdtr(u32 default_val) +{ + return default_val; +} +u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr"))); + +u32 __ddr_clktr(u32 default_val) +{ + return default_val; +} +u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr"))); + + +/* Private Structure Definitions */ + +/* enum only to ease code for cas latency setting */ +typedef enum ddr_cas_id { + DDR_CAS_2 = 20, + DDR_CAS_2_5 = 25, + DDR_CAS_3 = 30, + DDR_CAS_4 = 40, + DDR_CAS_5 = 50 +} ddr_cas_id_t; + +/*-----------------------------------------------------------------------------+ + * Prototypes + *-----------------------------------------------------------------------------*/ +static void get_spd_info(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void check_mem_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void check_frequency(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void check_rank_number(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void check_voltage_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_memory_queue(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_codt(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_mode(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks, + ddr_cas_id_t *selected_cas, + int *write_recovery); +static void program_tr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_rtr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_bxcf(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_copt1(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +static void program_initplr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks, + ddr_cas_id_t selected_cas, + int write_recovery); +#ifdef CONFIG_DDR_ECC +static void program_ecc(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks, + unsigned long tlb_word2_i_value); +#endif +#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) +static void program_DQS_calibration(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); +#ifdef HARD_CODED_DQS /* calibration test with hardvalues */ +static void test(void); +#else +static void DQS_calibration_process(void); +#endif +#endif +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +static unsigned char spd_read(uchar chip, uint addr) +{ + unsigned char data[2]; + + if (i2c_probe(chip) == 0) + if (i2c_read(chip, addr, 1, data, 1) == 0) + return data[0]; + + return 0; +} + +/*-----------------------------------------------------------------------------+ + * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller. + * Note: This routine runs from flash with a stack set up in the chip's + * sram space. It is important that the routine does not require .sbss, .bss or + * .data sections. It also cannot call routines that require these sections. + *-----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures SDRAM memory banks for DDR operation. + * Auto Memory Configuration option reads the DDR SDRAM EEPROMs + * via the IIC bus and then configures the DDR SDRAM memory + * banks appropriately. If Auto Memory Configuration is + * not used, it is assumed that no DIMM is plugged + *-----------------------------------------------------------------------------*/ +phys_size_t initdram(int board_type) +{ + unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; + unsigned char spd0[MAX_SPD_BYTES]; + unsigned char spd1[MAX_SPD_BYTES]; + unsigned char *dimm_spd[MAXDIMMS]; + unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE}; + unsigned long num_dimm_banks; /* on board dimm banks */ + unsigned long val; + ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */ + int write_recovery; + phys_size_t dram_size = 0; + + num_dimm_banks = sizeof(iic0_dimm_addr); + + /*------------------------------------------------------------------ + * Set up an array of SPD matrixes. + *-----------------------------------------------------------------*/ + dimm_spd[0] = spd0; + dimm_spd[1] = spd1; + + /*------------------------------------------------------------------ + * Reset the DDR-SDRAM controller. + *-----------------------------------------------------------------*/ + mtsdr(SDR0_SRST, (0x80000000 >> 10)); + mtsdr(SDR0_SRST, 0x00000000); + + /* + * Make sure I2C controller is initialized + * before continuing. + */ + + /* switch to correct I2C bus */ + I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + /*------------------------------------------------------------------ + * Clear out the serial presence detect buffers. + * Perform IIC reads from the dimm. Fill in the spds. + * Check to see if the dimm slots are populated + *-----------------------------------------------------------------*/ + get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Check the memory type for the dimms plugged. + *-----------------------------------------------------------------*/ + check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Check the frequency supported for the dimms plugged. + *-----------------------------------------------------------------*/ + check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Check the total rank number. + *-----------------------------------------------------------------*/ + check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Check the voltage type for the dimms plugged. + *-----------------------------------------------------------------*/ + check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Program SDRAM controller options 2 register + * Except Enabling of the memory controller. + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, + (val & + ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK | + SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK | + SDRAM_MCOPT2_ISIE_MASK)) + | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE | + SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW | + SDRAM_MCOPT2_ISIE_ENABLE)); + + /*------------------------------------------------------------------ + * Program SDRAM controller options 1 register + * Note: Does not enable the memory controller. + *-----------------------------------------------------------------*/ + program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Set the SDRAM Controller On Die Termination Register + *-----------------------------------------------------------------*/ + program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Program SDRAM refresh register. + *-----------------------------------------------------------------*/ + program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Program SDRAM mode register. + *-----------------------------------------------------------------*/ + program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks, + &selected_cas, &write_recovery); + + /*------------------------------------------------------------------ + * Set the SDRAM Write Data/DM/DQS Clock Timing Reg + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_WRDTR, val); + mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) | + ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV)); + + /*------------------------------------------------------------------ + * Set the SDRAM Clock Timing Register + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_CLKTR, val); + mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | + ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG)); + + /*------------------------------------------------------------------ + * Program the BxCF registers. + *-----------------------------------------------------------------*/ + program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Program SDRAM timing registers. + *-----------------------------------------------------------------*/ + program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Set the Extended Mode register + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_MEMODE, val); + mtsdram(SDRAM_MEMODE, + (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK | + SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) | + (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE + | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE)); + + /*------------------------------------------------------------------ + * Program Initialization preload registers. + *-----------------------------------------------------------------*/ + program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks, + selected_cas, write_recovery); + + /*------------------------------------------------------------------ + * Delay to ensure 200usec have elapsed since reset. + *-----------------------------------------------------------------*/ + udelay(400); + + /*------------------------------------------------------------------ + * Set the memory queue core base addr. + *-----------------------------------------------------------------*/ + program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Program SDRAM controller options 2 register + * Enable the memory controller. + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, + (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK | + SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) | + SDRAM_MCOPT2_IPTR_EXECUTE); + + /*------------------------------------------------------------------ + * Wait for IPTR_EXECUTE init sequence to complete. + *-----------------------------------------------------------------*/ + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP); + + /* enable the controller only after init sequence completes */ + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE)); + + /* Make sure delay-line calibration is done before proceeding */ + do { + mfsdram(SDRAM_DLCR, val); + } while (!(val & SDRAM_DLCR_DLCS_COMPLETE)); + + /* get installed memory size */ + dram_size = sdram_memsize(); + + /* + * Limit size to 2GB + */ + if (dram_size > CONFIG_MAX_MEM_MAPPED) + dram_size = CONFIG_MAX_MEM_MAPPED; + + /* and program tlb entries for this size (dynamic) */ + + /* + * Program TLB entries with caches enabled, for best performace + * while auto-calibrating and ECC generation + */ + program_tlb(0, 0, dram_size, 0); + + /*------------------------------------------------------------------ + * DQS calibration. + *-----------------------------------------------------------------*/ +#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) + DQS_autocalibration(); +#else + program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks); +#endif + +#ifdef CONFIG_DDR_ECC + /*------------------------------------------------------------------ + * If ecc is enabled, initialize the parity bits. + *-----------------------------------------------------------------*/ + program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0); +#endif + + /* + * Now after initialization (auto-calibration and ECC generation) + * remove the TLB entries with caches enabled and program again with + * desired cache functionality + */ + remove_tlb(0, dram_size); + program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); + + ppc4xx_ibm_ddr2_register_dump(); + + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + + return sdram_memsize(); +} + +static void get_spd_info(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_found; + unsigned char num_of_bytes; + unsigned char total_size; + + dimm_found = FALSE; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + num_of_bytes = 0; + total_size = 0; + + num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); + debug("\nspd_read(0x%x) returned %d\n", + iic0_dimm_addr[dimm_num], num_of_bytes); + total_size = spd_read(iic0_dimm_addr[dimm_num], 1); + debug("spd_read(0x%x) returned %d\n", + iic0_dimm_addr[dimm_num], total_size); + + if ((num_of_bytes != 0) && (total_size != 0)) { + dimm_populated[dimm_num] = TRUE; + dimm_found = TRUE; + debug("DIMM slot %lu: populated\n", dimm_num); + } else { + dimm_populated[dimm_num] = FALSE; + debug("DIMM slot %lu: Not populated\n", dimm_num); + } + } + + if (dimm_found == FALSE) { + printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); + spd_ddr_init_hang (); + } +} + + +/*------------------------------------------------------------------ + * For the memory DIMMs installed, this routine verifies that they + * really are DDR specific DIMMs. + *-----------------------------------------------------------------*/ +static void check_mem_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); + switch (dimm_type) { + case 1: + printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in " + "slot %d.\n", (unsigned int)dimm_num); + printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + case 2: + printf("ERROR: EDO DIMM detected in slot %d.\n", + (unsigned int)dimm_num); + printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + case 3: + printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n", + (unsigned int)dimm_num); + printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + case 4: + printf("ERROR: SDRAM DIMM detected in slot %d.\n", + (unsigned int)dimm_num); + printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + case 5: + printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n", + (unsigned int)dimm_num); + printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + case 6: + printf("ERROR: SGRAM DIMM detected in slot %d.\n", + (unsigned int)dimm_num); + printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + case 7: + debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num); + dimm_populated[dimm_num] = SDRAM_DDR1; + break; + case 8: + debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num); + dimm_populated[dimm_num] = SDRAM_DDR2; + break; + default: + printf("ERROR: Unknown DIMM detected in slot %d.\n", + (unsigned int)dimm_num); + printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + } + } + } + for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) { + if ((dimm_populated[dimm_num-1] != SDRAM_NONE) + && (dimm_populated[dimm_num] != SDRAM_NONE) + && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) { + printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n"); + spd_ddr_init_hang (); + } + } +} + +/*------------------------------------------------------------------ + * For the memory DIMMs installed, this routine verifies that + * frequency previously calculated is supported. + *-----------------------------------------------------------------*/ +static void check_frequency(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long tcyc_reg; + unsigned long cycle_time; + unsigned long calc_cycle_time; + unsigned long sdram_freq; + unsigned long sdr_ddrpll; + PPC4xx_SYS_INFO board_cfg; + + /*------------------------------------------------------------------ + * Get the board configuration info. + *-----------------------------------------------------------------*/ + get_sys_info(&board_cfg); + + mfsdr(SDR0_DDR0, sdr_ddrpll); + sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); + + /* + * calc_cycle_time is calculated from DDR frequency set by board/chip + * and is expressed in multiple of 10 picoseconds + * to match the way DIMM cycle time is calculated below. + */ + calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq); + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] != SDRAM_NONE) { + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); + /* + * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles: + * the higher order nibble (bits 4-7) designates the cycle time + * to a granularity of 1ns; + * the value presented by the lower order nibble (bits 0-3) + * has a granularity of .1ns and is added to the value designated + * by the higher nibble. In addition, four lines of the lower order + * nibble are assigned to support +.25,+.33, +.66 and +.75. + */ + /* Convert from hex to decimal */ + if ((tcyc_reg & 0x0F) == 0x0D) + cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75; + else if ((tcyc_reg & 0x0F) == 0x0C) + cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66; + else if ((tcyc_reg & 0x0F) == 0x0B) + cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33; + else if ((tcyc_reg & 0x0F) == 0x0A) + cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25; + else + cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + + ((tcyc_reg & 0x0F)*10); + debug("cycle_time=%lu [10 picoseconds]\n", cycle_time); + + if (cycle_time > (calc_cycle_time + 10)) { + /* + * the provided sdram cycle_time is too small + * for the available DIMM cycle_time. + * The additionnal 100ps is here to accept a small incertainty. + */ + printf("ERROR: DRAM DIMM detected with cycle_time %d ps in " + "slot %d \n while calculated cycle time is %d ps.\n", + (unsigned int)(cycle_time*10), + (unsigned int)dimm_num, + (unsigned int)(calc_cycle_time*10)); + printf("Replace the DIMM, or change DDR frequency via " + "strapping bits.\n\n"); + spd_ddr_init_hang (); + } + } + } +} + +/*------------------------------------------------------------------ + * For the memory DIMMs installed, this routine verifies two + * ranks/banks maximum are availables. + *-----------------------------------------------------------------*/ +static void check_rank_number(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_rank; + unsigned long total_rank = 0; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] != SDRAM_NONE) { + dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5); + if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) + dimm_rank = (dimm_rank & 0x0F) +1; + else + dimm_rank = dimm_rank & 0x0F; + + + if (dimm_rank > MAXRANKS) { + printf("ERROR: DRAM DIMM detected with %lu ranks in " + "slot %lu is not supported.\n", dimm_rank, dimm_num); + printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + } else + total_rank += dimm_rank; + } + if (total_rank > MAXRANKS) { + printf("ERROR: DRAM DIMM detected with a total of %d ranks " + "for all slots.\n", (unsigned int)total_rank); + printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); + printf("Remove one of the DIMM modules.\n\n"); + spd_ddr_init_hang (); + } + } +} + +/*------------------------------------------------------------------ + * only support 2.5V modules. + * This routine verifies this. + *-----------------------------------------------------------------*/ +static void check_voltage_type(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long voltage_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] != SDRAM_NONE) { + voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); + switch (voltage_type) { + case 0x00: + printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); + printf("This DIMM is 5.0 Volt/TTL.\n"); + printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", + (unsigned int)dimm_num); + spd_ddr_init_hang (); + break; + case 0x01: + printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); + printf("This DIMM is LVTTL.\n"); + printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", + (unsigned int)dimm_num); + spd_ddr_init_hang (); + break; + case 0x02: + printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); + printf("This DIMM is 1.5 Volt.\n"); + printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", + (unsigned int)dimm_num); + spd_ddr_init_hang (); + break; + case 0x03: + printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); + printf("This DIMM is 3.3 Volt/TTL.\n"); + printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", + (unsigned int)dimm_num); + spd_ddr_init_hang (); + break; + case 0x04: + /* 2.5 Voltage only for DDR1 */ + break; + case 0x05: + /* 1.8 Voltage only for DDR2 */ + break; + default: + printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); + printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", + (unsigned int)dimm_num); + spd_ddr_init_hang (); + break; + } + } + } +} + +/*-----------------------------------------------------------------------------+ + * program_copt1. + *-----------------------------------------------------------------------------*/ +static void program_copt1(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long mcopt1; + unsigned long ecc_enabled; + unsigned long ecc = 0; + unsigned long data_width = 0; + unsigned long dimm_32bit; + unsigned long dimm_64bit; + unsigned long registered = 0; + unsigned long attribute = 0; + unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */ + unsigned long bankcount; + unsigned long ddrtype; + unsigned long val; + +#ifdef CONFIG_DDR_ECC + ecc_enabled = TRUE; +#else + ecc_enabled = FALSE; +#endif + dimm_32bit = FALSE; + dimm_64bit = FALSE; + buf0 = FALSE; + buf1 = FALSE; + + /*------------------------------------------------------------------ + * Set memory controller options reg 1, SDRAM_MCOPT1. + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_MCOPT1, val); + mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK | + SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK | + SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK | + SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK | + SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK | + SDRAM_MCOPT1_DREF_MASK); + + mcopt1 |= SDRAM_MCOPT1_QDEP; + mcopt1 |= SDRAM_MCOPT1_PMU_OPEN; + mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED; + mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED; + mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED; + mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] != SDRAM_NONE) { + /* test ecc support */ + ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11); + if (ecc != 0x02) /* ecc not supported */ + ecc_enabled = FALSE; + + /* test bank count */ + bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17); + if (bankcount == 0x04) /* bank count = 4 */ + mcopt1 |= SDRAM_MCOPT1_4_BANKS; + else /* bank count = 8 */ + mcopt1 |= SDRAM_MCOPT1_8_BANKS; + + /* test DDR type */ + ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2); + /* test for buffered/unbuffered, registered, differential clocks */ + registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20); + attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21); + + /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */ + if (dimm_num == 0) { + if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */ + mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE; + if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */ + mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE; + if (registered == 1) { /* DDR2 always buffered */ + /* TODO: what about above comments ? */ + mcopt1 |= SDRAM_MCOPT1_RDEN; + buf0 = TRUE; + } else { + /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */ + if ((attribute & 0x02) == 0x00) { + /* buffered not supported */ + buf0 = FALSE; + } else { + mcopt1 |= SDRAM_MCOPT1_RDEN; + buf0 = TRUE; + } + } + } + else if (dimm_num == 1) { + if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */ + mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE; + if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */ + mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE; + if (registered == 1) { + /* DDR2 always buffered */ + mcopt1 |= SDRAM_MCOPT1_RDEN; + buf1 = TRUE; + } else { + if ((attribute & 0x02) == 0x00) { + /* buffered not supported */ + buf1 = FALSE; + } else { + mcopt1 |= SDRAM_MCOPT1_RDEN; + buf1 = TRUE; + } + } + } + + /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */ + data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) + + (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8); + + switch (data_width) { + case 72: + case 64: + dimm_64bit = TRUE; + break; + case 40: + case 32: + dimm_32bit = TRUE; + break; + default: + printf("WARNING: Detected a DIMM with a data width of %lu bits.\n", + data_width); + printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n"); + break; + } + } + } + + /* verify matching properties */ + if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) { + if (buf0 != buf1) { + printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n"); + spd_ddr_init_hang (); + } + } + + if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) { + printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n"); + spd_ddr_init_hang (); + } + else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) { + mcopt1 |= SDRAM_MCOPT1_DMWD_64; + } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) { + mcopt1 |= SDRAM_MCOPT1_DMWD_32; + } else { + printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n"); + spd_ddr_init_hang (); + } + + if (ecc_enabled == TRUE) + mcopt1 |= SDRAM_MCOPT1_MCHK_GEN; + else + mcopt1 |= SDRAM_MCOPT1_MCHK_NON; + + mtsdram(SDRAM_MCOPT1, mcopt1); +} + +/*-----------------------------------------------------------------------------+ + * program_codt. + *-----------------------------------------------------------------------------*/ +static void program_codt(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long codt; + unsigned long modt0 = 0; + unsigned long modt1 = 0; + unsigned long modt2 = 0; + unsigned long modt3 = 0; + unsigned char dimm_num; + unsigned char dimm_rank; + unsigned char total_rank = 0; + unsigned char total_dimm = 0; + unsigned char dimm_type = 0; + unsigned char firstSlot = 0; + + /*------------------------------------------------------------------ + * Set the SDRAM Controller On Die Termination Register + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_CODT, codt); + codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END); + codt |= SDRAM_CODT_IO_NMODE; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] != SDRAM_NONE) { + dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5); + if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) { + dimm_rank = (dimm_rank & 0x0F) + 1; + dimm_type = SDRAM_DDR2; + } else { + dimm_rank = dimm_rank & 0x0F; + dimm_type = SDRAM_DDR1; + } + + total_rank += dimm_rank; + total_dimm++; + if ((dimm_num == 0) && (total_dimm == 1)) + firstSlot = TRUE; + else + firstSlot = FALSE; + } + } + if (dimm_type == SDRAM_DDR2) { + codt |= SDRAM_CODT_DQS_1_8_V_DDR2; + if ((total_dimm == 1) && (firstSlot == TRUE)) { + if (total_rank == 1) { /* PUUU */ + codt |= CALC_ODT_R(0); + modt0 = CALC_ODT_W(0); + modt1 = 0x00000000; + modt2 = 0x00000000; + modt3 = 0x00000000; + } + if (total_rank == 2) { /* PPUU */ + codt |= CALC_ODT_R(0) | CALC_ODT_R(1); + modt0 = CALC_ODT_W(0) | CALC_ODT_W(1); + modt1 = 0x00000000; + modt2 = 0x00000000; + modt3 = 0x00000000; + } + } else if ((total_dimm == 1) && (firstSlot != TRUE)) { + if (total_rank == 1) { /* UUPU */ + codt |= CALC_ODT_R(2); + modt0 = 0x00000000; + modt1 = 0x00000000; + modt2 = CALC_ODT_W(2); + modt3 = 0x00000000; + } + if (total_rank == 2) { /* UUPP */ + codt |= CALC_ODT_R(2) | CALC_ODT_R(3); + modt0 = 0x00000000; + modt1 = 0x00000000; + modt2 = CALC_ODT_W(2) | CALC_ODT_W(3); + modt3 = 0x00000000; + } + } + if (total_dimm == 2) { + if (total_rank == 2) { /* PUPU */ + codt |= CALC_ODT_R(0) | CALC_ODT_R(2); + modt0 = CALC_ODT_RW(2); + modt1 = 0x00000000; + modt2 = CALC_ODT_RW(0); + modt3 = 0x00000000; + } + if (total_rank == 4) { /* PPPP */ + codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | + CALC_ODT_R(2) | CALC_ODT_R(3); + modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3); + modt1 = 0x00000000; + modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1); + modt3 = 0x00000000; + } + } + } else { + codt |= SDRAM_CODT_DQS_2_5_V_DDR1; + modt0 = 0x00000000; + modt1 = 0x00000000; + modt2 = 0x00000000; + modt3 = 0x00000000; + + if (total_dimm == 1) { + if (total_rank == 1) + codt |= 0x00800000; + if (total_rank == 2) + codt |= 0x02800000; + } + if (total_dimm == 2) { + if (total_rank == 2) + codt |= 0x08800000; + if (total_rank == 4) + codt |= 0x2a800000; + } + } + + debug("nb of dimm %d\n", total_dimm); + debug("nb of rank %d\n", total_rank); + if (total_dimm == 1) + debug("dimm in slot %d\n", firstSlot); + + mtsdram(SDRAM_CODT, codt); + mtsdram(SDRAM_MODT0, modt0); + mtsdram(SDRAM_MODT1, modt1); + mtsdram(SDRAM_MODT2, modt2); + mtsdram(SDRAM_MODT3, modt3); +} + +/*-----------------------------------------------------------------------------+ + * program_initplr. + *-----------------------------------------------------------------------------*/ +static void program_initplr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks, + ddr_cas_id_t selected_cas, + int write_recovery) +{ + u32 cas = 0; + u32 odt = 0; + u32 ods = 0; + u32 mr; + u32 wr; + u32 emr; + u32 emr2; + u32 emr3; + int dimm_num; + int total_dimm = 0; + + /****************************************************** + ** Assumption: if more than one DIMM, all DIMMs are the same + ** as already checked in check_memory_type + ******************************************************/ + + if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) { + mtsdram(SDRAM_INITPLR0, 0x81B80000); + mtsdram(SDRAM_INITPLR1, 0x81900400); + mtsdram(SDRAM_INITPLR2, 0x81810000); + mtsdram(SDRAM_INITPLR3, 0xff800162); + mtsdram(SDRAM_INITPLR4, 0x81900400); + mtsdram(SDRAM_INITPLR5, 0x86080000); + mtsdram(SDRAM_INITPLR6, 0x86080000); + mtsdram(SDRAM_INITPLR7, 0x81000062); + } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) { + switch (selected_cas) { + case DDR_CAS_3: + cas = 3 << 4; + break; + case DDR_CAS_4: + cas = 4 << 4; + break; + case DDR_CAS_5: + cas = 5 << 4; + break; + default: + printf("ERROR: ucode error on selected_cas value %d", selected_cas); + spd_ddr_init_hang (); + break; + } + +#if 0 + /* + * ToDo - Still a problem with the write recovery: + * On the Corsair CM2X512-5400C4 module, setting write recovery + * in the INITPLR reg to the value calculated in program_mode() + * results in not correctly working DDR2 memory (crash after + * relocation). + * + * So for now, set the write recovery to 3. This seems to work + * on the Corair module too. + * + * 2007-03-01, sr + */ + switch (write_recovery) { + case 3: + wr = WRITE_RECOV_3; + break; + case 4: + wr = WRITE_RECOV_4; + break; + case 5: + wr = WRITE_RECOV_5; + break; + case 6: + wr = WRITE_RECOV_6; + break; + default: + printf("ERROR: write recovery not support (%d)", write_recovery); + spd_ddr_init_hang (); + break; + } +#else + wr = WRITE_RECOV_3; /* test-only, see description above */ +#endif + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) + if (dimm_populated[dimm_num] != SDRAM_NONE) + total_dimm++; + if (total_dimm == 1) { + odt = ODT_150_OHM; + ods = ODS_FULL; + } else if (total_dimm == 2) { + odt = ODT_75_OHM; + ods = ODS_REDUCED; + } else { + printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm); + spd_ddr_init_hang (); + } + + mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas; + emr = CMD_EMR | SELECT_EMR | odt | ods; + emr2 = CMD_EMR | SELECT_EMR2; + emr3 = CMD_EMR | SELECT_EMR3; + /* NOP - Wait 106 MemClk cycles */ + mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP | + SDRAM_INITPLR_IMWT_ENCODE(106)); + udelay(1000); + /* precharge 4 MemClk cycles */ + mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE | + SDRAM_INITPLR_IMWT_ENCODE(4)); + /* EMR2 - Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 | + SDRAM_INITPLR_IMWT_ENCODE(2)); + /* EMR3 - Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 | + SDRAM_INITPLR_IMWT_ENCODE(2)); + /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr | + SDRAM_INITPLR_IMWT_ENCODE(2)); + /* MR w/ DLL reset - 200 cycle wait for DLL reset */ + mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET | + SDRAM_INITPLR_IMWT_ENCODE(200)); + udelay(1000); + /* precharge 4 MemClk cycles */ + mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE | + SDRAM_INITPLR_IMWT_ENCODE(4)); + /* Refresh 25 MemClk cycles */ + mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH | + SDRAM_INITPLR_IMWT_ENCODE(25)); + /* Refresh 25 MemClk cycles */ + mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH | + SDRAM_INITPLR_IMWT_ENCODE(25)); + /* Refresh 25 MemClk cycles */ + mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH | + SDRAM_INITPLR_IMWT_ENCODE(25)); + /* Refresh 25 MemClk cycles */ + mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH | + SDRAM_INITPLR_IMWT_ENCODE(25)); + /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr | + SDRAM_INITPLR_IMWT_ENCODE(2)); + /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF | + SDRAM_INITPLR_IMWT_ENCODE(2) | emr); + /* EMR OCD Exit */ + mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr | + SDRAM_INITPLR_IMWT_ENCODE(2)); + } else { + printf("ERROR: ucode error as unknown DDR type in program_initplr"); + spd_ddr_init_hang (); + } +} + +/*------------------------------------------------------------------ + * This routine programs the SDRAM_MMODE register. + * the selected_cas is an output parameter, that will be passed + * by caller to call the above program_initplr( ) + *-----------------------------------------------------------------*/ +static void program_mode(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks, + ddr_cas_id_t *selected_cas, + int *write_recovery) +{ + unsigned long dimm_num; + unsigned long sdram_ddr1; + unsigned long t_wr_ns; + unsigned long t_wr_clk; + unsigned long cas_bit; + unsigned long cas_index; + unsigned long sdram_freq; + unsigned long ddr_check; + unsigned long mmode; + unsigned long tcyc_reg; + unsigned long cycle_2_0_clk; + unsigned long cycle_2_5_clk; + unsigned long cycle_3_0_clk; + unsigned long cycle_4_0_clk; + unsigned long cycle_5_0_clk; + unsigned long max_2_0_tcyc_ns_x_100; + unsigned long max_2_5_tcyc_ns_x_100; + unsigned long max_3_0_tcyc_ns_x_100; + unsigned long max_4_0_tcyc_ns_x_100; + unsigned long max_5_0_tcyc_ns_x_100; + unsigned long cycle_time_ns_x_100[3]; + PPC4xx_SYS_INFO board_cfg; + unsigned char cas_2_0_available; + unsigned char cas_2_5_available; + unsigned char cas_3_0_available; + unsigned char cas_4_0_available; + unsigned char cas_5_0_available; + unsigned long sdr_ddrpll; + + /*------------------------------------------------------------------ + * Get the board configuration info. + *-----------------------------------------------------------------*/ + get_sys_info(&board_cfg); + + mfsdr(SDR0_DDR0, sdr_ddrpll); + sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1); + debug("sdram_freq=%lu\n", sdram_freq); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + t_wr_ns = 0; + cas_2_0_available = TRUE; + cas_2_5_available = TRUE; + cas_3_0_available = TRUE; + cas_4_0_available = TRUE; + cas_5_0_available = TRUE; + max_2_0_tcyc_ns_x_100 = 10; + max_2_5_tcyc_ns_x_100 = 10; + max_3_0_tcyc_ns_x_100 = 10; + max_4_0_tcyc_ns_x_100 = 10; + max_5_0_tcyc_ns_x_100 = 10; + sdram_ddr1 = TRUE; + + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_populated[dimm_num] != SDRAM_NONE) { + if (dimm_populated[dimm_num] == SDRAM_DDR1) + sdram_ddr1 = TRUE; + else + sdram_ddr1 = FALSE; + + /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */ + cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); + debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit); + + /* For a particular DIMM, grab the three CAS values it supports */ + for (cas_index = 0; cas_index < 3; cas_index++) { + switch (cas_index) { + case 0: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); + break; + case 1: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); + break; + default: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); + break; + } + + if ((tcyc_reg & 0x0F) >= 10) { + if ((tcyc_reg & 0x0F) == 0x0D) { + /* Convert from hex to decimal */ + cycle_time_ns_x_100[cas_index] = + (((tcyc_reg & 0xF0) >> 4) * 100) + 75; + } else { + printf("ERROR: SPD reported Tcyc is incorrect for DIMM " + "in slot %d\n", (unsigned int)dimm_num); + spd_ddr_init_hang (); + } + } else { + /* Convert from hex to decimal */ + cycle_time_ns_x_100[cas_index] = + (((tcyc_reg & 0xF0) >> 4) * 100) + + ((tcyc_reg & 0x0F)*10); + } + debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index, + cycle_time_ns_x_100[cas_index]); + } + + /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */ + /* supported for a particular DIMM. */ + cas_index = 0; + + if (sdram_ddr1) { + /* + * DDR devices use the following bitmask for CAS latency: + * Bit 7 6 5 4 3 2 1 0 + * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0 + */ + if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) && + (cycle_time_ns_x_100[cas_index] != 0)) { + max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, + cycle_time_ns_x_100[cas_index]); + cas_index++; + } else { + if (cas_index != 0) + cas_index++; + cas_4_0_available = FALSE; + } + + if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && + (cycle_time_ns_x_100[cas_index] != 0)) { + max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, + cycle_time_ns_x_100[cas_index]); + cas_index++; + } else { + if (cas_index != 0) + cas_index++; + cas_3_0_available = FALSE; + } + + if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && + (cycle_time_ns_x_100[cas_index] != 0)) { + max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100, + cycle_time_ns_x_100[cas_index]); + cas_index++; + } else { + if (cas_index != 0) + cas_index++; + cas_2_5_available = FALSE; + } + + if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && + (cycle_time_ns_x_100[cas_index] != 0)) { + max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100, + cycle_time_ns_x_100[cas_index]); + cas_index++; + } else { + if (cas_index != 0) + cas_index++; + cas_2_0_available = FALSE; + } + } else { + /* + * DDR2 devices use the following bitmask for CAS latency: + * Bit 7 6 5 4 3 2 1 0 + * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD + */ + if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) && + (cycle_time_ns_x_100[cas_index] != 0)) { + max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100, + cycle_time_ns_x_100[cas_index]); + cas_index++; + } else { + if (cas_index != 0) + cas_index++; + cas_5_0_available = FALSE; + } + + if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && + (cycle_time_ns_x_100[cas_index] != 0)) { + max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, + cycle_time_ns_x_100[cas_index]); + cas_index++; + } else { + if (cas_index != 0) + cas_index++; + cas_4_0_available = FALSE; + } + + if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && + (cycle_time_ns_x_100[cas_index] != 0)) { + max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, + cycle_time_ns_x_100[cas_index]); + cas_index++; + } else { + if (cas_index != 0) + cas_index++; + cas_3_0_available = FALSE; + } + } + } + } + + /*------------------------------------------------------------------ + * Set the SDRAM mode, SDRAM_MMODE + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_MMODE, mmode); + mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK); + + /* add 10 here because of rounding problems */ + cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10; + cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10; + cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10; + cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10; + cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10; + debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk); + debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk); + debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk); + + if (sdram_ddr1 == TRUE) { /* DDR1 */ + if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) { + mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK; + *selected_cas = DDR_CAS_2; + } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) { + mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK; + *selected_cas = DDR_CAS_2_5; + } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { + mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK; + *selected_cas = DDR_CAS_3; + } else { + printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n"); + printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); + printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n"); + spd_ddr_init_hang (); + } + } else { /* DDR2 */ + debug("cas_3_0_available=%d\n", cas_3_0_available); + debug("cas_4_0_available=%d\n", cas_4_0_available); + debug("cas_5_0_available=%d\n", cas_5_0_available); + if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { + mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK; + *selected_cas = DDR_CAS_3; + } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) { + mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK; + *selected_cas = DDR_CAS_4; + } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) { + mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK; + *selected_cas = DDR_CAS_5; + } else { + printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n"); + printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n"); + printf("Make sure the PLB speed is within the supported range of the DIMMs.\n"); + printf("cas3=%d cas4=%d cas5=%d\n", + cas_3_0_available, cas_4_0_available, cas_5_0_available); + printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n", + sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); + spd_ddr_init_hang (); + } + } + + if (sdram_ddr1 == TRUE) + mmode |= SDRAM_MMODE_WR_DDR1; + else { + + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_populated[dimm_num] != SDRAM_NONE) + t_wr_ns = max(t_wr_ns, + spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); + } + + /* + * convert from nanoseconds to ddr clocks + * round up if necessary + */ + t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns); + if (sdram_freq != ddr_check) + t_wr_clk++; + + switch (t_wr_clk) { + case 0: + case 1: + case 2: + case 3: + mmode |= SDRAM_MMODE_WR_DDR2_3_CYC; + break; + case 4: + mmode |= SDRAM_MMODE_WR_DDR2_4_CYC; + break; + case 5: + mmode |= SDRAM_MMODE_WR_DDR2_5_CYC; + break; + default: + mmode |= SDRAM_MMODE_WR_DDR2_6_CYC; + break; + } + *write_recovery = t_wr_clk; + } + + debug("CAS latency = %d\n", *selected_cas); + debug("Write recovery = %d\n", *write_recovery); + + mtsdram(SDRAM_MMODE, mmode); +} + +/*-----------------------------------------------------------------------------+ + * program_rtr. + *-----------------------------------------------------------------------------*/ +static void program_rtr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + PPC4xx_SYS_INFO board_cfg; + unsigned long max_refresh_rate; + unsigned long dimm_num; + unsigned long refresh_rate_type; + unsigned long refresh_rate; + unsigned long rint; + unsigned long sdram_freq; + unsigned long sdr_ddrpll; + unsigned long val; + + /*------------------------------------------------------------------ + * Get the board configuration info. + *-----------------------------------------------------------------*/ + get_sys_info(&board_cfg); + + /*------------------------------------------------------------------ + * Set the SDRAM Refresh Timing Register, SDRAM_RTR + *-----------------------------------------------------------------*/ + mfsdr(SDR0_DDR0, sdr_ddrpll); + sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); + + max_refresh_rate = 0; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] != SDRAM_NONE) { + + refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12); + refresh_rate_type &= 0x7F; + switch (refresh_rate_type) { + case 0: + refresh_rate = 15625; + break; + case 1: + refresh_rate = 3906; + break; + case 2: + refresh_rate = 7812; + break; + case 3: + refresh_rate = 31250; + break; + case 4: + refresh_rate = 62500; + break; + case 5: + refresh_rate = 125000; + break; + default: + refresh_rate = 0; + printf("ERROR: DIMM %d unsupported refresh rate/type.\n", + (unsigned int)dimm_num); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + break; + } + + max_refresh_rate = max(max_refresh_rate, refresh_rate); + } + } + + rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION); + mfsdram(SDRAM_RTR, val); + mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) | + (SDRAM_RTR_RINT_ENCODE(rint))); +} + +/*------------------------------------------------------------------ + * This routine programs the SDRAM_TRx registers. + *-----------------------------------------------------------------*/ +static void program_tr(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long sdram_ddr1; + unsigned long t_rp_ns; + unsigned long t_rcd_ns; + unsigned long t_rrd_ns; + unsigned long t_ras_ns; + unsigned long t_rc_ns; + unsigned long t_rfc_ns; + unsigned long t_wpc_ns; + unsigned long t_wtr_ns; + unsigned long t_rpc_ns; + unsigned long t_rp_clk; + unsigned long t_rcd_clk; + unsigned long t_rrd_clk; + unsigned long t_ras_clk; + unsigned long t_rc_clk; + unsigned long t_rfc_clk; + unsigned long t_wpc_clk; + unsigned long t_wtr_clk; + unsigned long t_rpc_clk; + unsigned long sdtr1, sdtr2, sdtr3; + unsigned long ddr_check; + unsigned long sdram_freq; + unsigned long sdr_ddrpll; + + PPC4xx_SYS_INFO board_cfg; + + /*------------------------------------------------------------------ + * Get the board configuration info. + *-----------------------------------------------------------------*/ + get_sys_info(&board_cfg); + + mfsdr(SDR0_DDR0, sdr_ddrpll); + sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + t_rp_ns = 0; + t_rrd_ns = 0; + t_rcd_ns = 0; + t_ras_ns = 0; + t_rc_ns = 0; + t_rfc_ns = 0; + t_wpc_ns = 0; + t_wtr_ns = 0; + t_rpc_ns = 0; + sdram_ddr1 = TRUE; + + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_populated[dimm_num] != SDRAM_NONE) { + if (dimm_populated[dimm_num] == SDRAM_DDR2) + sdram_ddr1 = TRUE; + else + sdram_ddr1 = FALSE; + + t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); + t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); + t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2); + t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30)); + t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41)); + t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42)); + } + } + + /*------------------------------------------------------------------ + * Set the SDRAM Timing Reg 1, SDRAM_TR1 + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_SDTR1, sdtr1); + sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK | + SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK); + + /* default values */ + sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK; + sdtr1 |= SDRAM_SDTR1_RTW_2_CLK; + + /* normal operations */ + sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK; + sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK; + + mtsdram(SDRAM_SDTR1, sdtr1); + + /*------------------------------------------------------------------ + * Set the SDRAM Timing Reg 2, SDRAM_TR2 + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_SDTR2, sdtr2); + sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK | + SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK | + SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK | + SDRAM_SDTR2_RRD_MASK); + + /* + * convert t_rcd from nanoseconds to ddr clocks + * round up if necessary + */ + t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns); + if (sdram_freq != ddr_check) + t_rcd_clk++; + + switch (t_rcd_clk) { + case 0: + case 1: + sdtr2 |= SDRAM_SDTR2_RCD_1_CLK; + break; + case 2: + sdtr2 |= SDRAM_SDTR2_RCD_2_CLK; + break; + case 3: + sdtr2 |= SDRAM_SDTR2_RCD_3_CLK; + break; + case 4: + sdtr2 |= SDRAM_SDTR2_RCD_4_CLK; + break; + default: + sdtr2 |= SDRAM_SDTR2_RCD_5_CLK; + break; + } + + if (sdram_ddr1 == TRUE) { /* DDR1 */ + if (sdram_freq < 200000000) { + sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; + sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; + sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; + } else { + sdtr2 |= SDRAM_SDTR2_WTR_2_CLK; + sdtr2 |= SDRAM_SDTR2_WPC_3_CLK; + sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; + } + } else { /* DDR2 */ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_populated[dimm_num] != SDRAM_NONE) { + t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); + t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2); + t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2); + } + } + + /* + * convert from nanoseconds to ddr clocks + * round up if necessary + */ + t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns); + if (sdram_freq != ddr_check) + t_wpc_clk++; + + switch (t_wpc_clk) { + case 0: + case 1: + case 2: + sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; + break; + case 3: + sdtr2 |= SDRAM_SDTR2_WPC_3_CLK; + break; + case 4: + sdtr2 |= SDRAM_SDTR2_WPC_4_CLK; + break; + case 5: + sdtr2 |= SDRAM_SDTR2_WPC_5_CLK; + break; + default: + sdtr2 |= SDRAM_SDTR2_WPC_6_CLK; + break; + } + + /* + * convert from nanoseconds to ddr clocks + * round up if necessary + */ + t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns); + if (sdram_freq != ddr_check) + t_wtr_clk++; + + switch (t_wtr_clk) { + case 0: + case 1: + sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; + break; + case 2: + sdtr2 |= SDRAM_SDTR2_WTR_2_CLK; + break; + case 3: + sdtr2 |= SDRAM_SDTR2_WTR_3_CLK; + break; + default: + sdtr2 |= SDRAM_SDTR2_WTR_4_CLK; + break; + } + + /* + * convert from nanoseconds to ddr clocks + * round up if necessary + */ + t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns); + if (sdram_freq != ddr_check) + t_rpc_clk++; + + switch (t_rpc_clk) { + case 0: + case 1: + case 2: + sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; + break; + case 3: + sdtr2 |= SDRAM_SDTR2_RPC_3_CLK; + break; + default: + sdtr2 |= SDRAM_SDTR2_RPC_4_CLK; + break; + } + } + + /* default value */ + sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK; + + /* + * convert t_rrd from nanoseconds to ddr clocks + * round up if necessary + */ + t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns); + if (sdram_freq != ddr_check) + t_rrd_clk++; + + if (t_rrd_clk == 3) + sdtr2 |= SDRAM_SDTR2_RRD_3_CLK; + else + sdtr2 |= SDRAM_SDTR2_RRD_2_CLK; + + /* + * convert t_rp from nanoseconds to ddr clocks + * round up if necessary + */ + t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns); + if (sdram_freq != ddr_check) + t_rp_clk++; + + switch (t_rp_clk) { + case 0: + case 1: + case 2: + case 3: + sdtr2 |= SDRAM_SDTR2_RP_3_CLK; + break; + case 4: + sdtr2 |= SDRAM_SDTR2_RP_4_CLK; + break; + case 5: + sdtr2 |= SDRAM_SDTR2_RP_5_CLK; + break; + case 6: + sdtr2 |= SDRAM_SDTR2_RP_6_CLK; + break; + default: + sdtr2 |= SDRAM_SDTR2_RP_7_CLK; + break; + } + + mtsdram(SDRAM_SDTR2, sdtr2); + + /*------------------------------------------------------------------ + * Set the SDRAM Timing Reg 3, SDRAM_TR3 + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_SDTR3, sdtr3); + sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK | + SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK); + + /* + * convert t_ras from nanoseconds to ddr clocks + * round up if necessary + */ + t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns); + if (sdram_freq != ddr_check) + t_ras_clk++; + + sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk); + + /* + * convert t_rc from nanoseconds to ddr clocks + * round up if necessary + */ + t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns); + if (sdram_freq != ddr_check) + t_rc_clk++; + + sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk); + + /* default xcs value */ + sdtr3 |= SDRAM_SDTR3_XCS; + + /* + * convert t_rfc from nanoseconds to ddr clocks + * round up if necessary + */ + t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION); + ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns); + if (sdram_freq != ddr_check) + t_rfc_clk++; + + sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk); + + mtsdram(SDRAM_SDTR3, sdtr3); +} + +/*-----------------------------------------------------------------------------+ + * program_bxcf. + *-----------------------------------------------------------------------------*/ +static void program_bxcf(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long num_col_addr; + unsigned long num_ranks; + unsigned long num_banks; + unsigned long mode; + unsigned long ind_rank; + unsigned long ind; + unsigned long ind_bank; + unsigned long bank_0_populated; + + /*------------------------------------------------------------------ + * Set the BxCF regs. First, wipe out the bank config registers. + *-----------------------------------------------------------------*/ + mtsdram(SDRAM_MB0CF, 0x00000000); + mtsdram(SDRAM_MB1CF, 0x00000000); + mtsdram(SDRAM_MB2CF, 0x00000000); + mtsdram(SDRAM_MB3CF, 0x00000000); + + mode = SDRAM_BXCF_M_BE_ENABLE; + + bank_0_populated = 0; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] != SDRAM_NONE) { + num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); + num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5); + if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) + num_ranks = (num_ranks & 0x0F) +1; + else + num_ranks = num_ranks & 0x0F; + + num_banks = spd_read(iic0_dimm_addr[dimm_num], 17); + + for (ind_bank = 0; ind_bank < 2; ind_bank++) { + if (num_banks == 4) + ind = 0; + else + ind = 5 << 8; + switch (num_col_addr) { + case 0x08: + mode |= (SDRAM_BXCF_M_AM_0 + ind); + break; + case 0x09: + mode |= (SDRAM_BXCF_M_AM_1 + ind); + break; + case 0x0A: + mode |= (SDRAM_BXCF_M_AM_2 + ind); + break; + case 0x0B: + mode |= (SDRAM_BXCF_M_AM_3 + ind); + break; + case 0x0C: + mode |= (SDRAM_BXCF_M_AM_4 + ind); + break; + default: + printf("DDR-SDRAM: DIMM %d BxCF configuration.\n", + (unsigned int)dimm_num); + printf("ERROR: Unsupported value for number of " + "column addresses: %d.\n", (unsigned int)num_col_addr); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + } + } + + if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1)) + bank_0_populated = 1; + + for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) { + mtsdram(SDRAM_MB0CF + + ((dimm_num + bank_0_populated + ind_rank) << 2), + mode); + } + } + } +} + +/*------------------------------------------------------------------ + * program memory queue. + *-----------------------------------------------------------------*/ +static void program_memory_queue(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + phys_size_t rank_base_addr; + unsigned long rank_reg; + phys_size_t rank_size_bytes; + unsigned long rank_size_id; + unsigned long num_ranks; + unsigned long baseadd_size; + unsigned long i; + unsigned long bank_0_populated = 0; + phys_size_t total_size = 0; + + /*------------------------------------------------------------------ + * Reset the rank_base_address. + *-----------------------------------------------------------------*/ + rank_reg = SDRAM_R0BAS; + + rank_base_addr = 0x00000000; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] != SDRAM_NONE) { + num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5); + if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) + num_ranks = (num_ranks & 0x0F) + 1; + else + num_ranks = num_ranks & 0x0F; + + rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); + + /*------------------------------------------------------------------ + * Set the sizes + *-----------------------------------------------------------------*/ + baseadd_size = 0; + switch (rank_size_id) { + case 0x01: + baseadd_size |= SDRAM_RXBAS_SDSZ_1024; + total_size = 1024; + break; + case 0x02: + baseadd_size |= SDRAM_RXBAS_SDSZ_2048; + total_size = 2048; + break; + case 0x04: + baseadd_size |= SDRAM_RXBAS_SDSZ_4096; + total_size = 4096; + break; + case 0x08: + baseadd_size |= SDRAM_RXBAS_SDSZ_32; + total_size = 32; + break; + case 0x10: + baseadd_size |= SDRAM_RXBAS_SDSZ_64; + total_size = 64; + break; + case 0x20: + baseadd_size |= SDRAM_RXBAS_SDSZ_128; + total_size = 128; + break; + case 0x40: + baseadd_size |= SDRAM_RXBAS_SDSZ_256; + total_size = 256; + break; + case 0x80: + baseadd_size |= SDRAM_RXBAS_SDSZ_512; + total_size = 512; + break; + default: + printf("DDR-SDRAM: DIMM %d memory queue configuration.\n", + (unsigned int)dimm_num); + printf("ERROR: Unsupported value for the banksize: %d.\n", + (unsigned int)rank_size_id); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + spd_ddr_init_hang (); + } + rank_size_bytes = total_size << 20; + + if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1)) + bank_0_populated = 1; + + for (i = 0; i < num_ranks; i++) { + mtdcr_any(rank_reg+i+dimm_num+bank_0_populated, + (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) | + baseadd_size)); + rank_base_addr += rank_size_bytes; + } + } + } + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + /* + * Enable high bandwidth access + * This is currently not used, but with this setup + * it is possible to use it later on in e.g. the Linux + * EMAC driver for performance gain. + */ + mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */ + mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */ + + /* + * Set optimal value for Memory Queue HB/LL Configuration registers + */ + mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) | + SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE | + SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL); + mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) | + SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE | + SDRAM_CONF1LL_RPLM); + mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); +#endif +} + +#ifdef CONFIG_DDR_ECC +/*-----------------------------------------------------------------------------+ + * program_ecc. + *-----------------------------------------------------------------------------*/ +static void program_ecc(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks, + unsigned long tlb_word2_i_value) +{ + unsigned long dimm_num; + unsigned long ecc; + + ecc = 0; + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_populated[dimm_num] != SDRAM_NONE) + ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11)); + } + if (ecc == 0) + return; + + do_program_ecc(tlb_word2_i_value); +} +#endif + +#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) +/*-----------------------------------------------------------------------------+ + * program_DQS_calibration. + *-----------------------------------------------------------------------------*/ +static void program_DQS_calibration(unsigned long *dimm_populated, + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long val; + +#ifdef HARD_CODED_DQS /* calibration test with hardvalues */ + mtsdram(SDRAM_RQDC, 0x80000037); + mtsdram(SDRAM_RDCC, 0x40000000); + mtsdram(SDRAM_RFDC, 0x000001DF); + + test(); +#else + /*------------------------------------------------------------------ + * Program RDCC register + * Read sample cycle auto-update enable + *-----------------------------------------------------------------*/ + + mfsdram(SDRAM_RDCC, val); + mtsdram(SDRAM_RDCC, + (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK)) + | SDRAM_RDCC_RSAE_ENABLE); + + /*------------------------------------------------------------------ + * Program RQDC register + * Internal DQS delay mechanism enable + *-----------------------------------------------------------------*/ + mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38))); + + /*------------------------------------------------------------------ + * Program RFDC register + * Set Feedback Fractional Oversample + * Auto-detect read sample cycle enable + * Set RFOS to 1/4 of memclk cycle (0x3f) + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_RFDC, val); + mtsdram(SDRAM_RFDC, + (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK | + SDRAM_RFDC_RFFD_MASK)) + | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) | + SDRAM_RFDC_RFFD_ENCODE(0))); + + DQS_calibration_process(); +#endif +} + +static int short_mem_test(void) +{ + u32 *membase; + u32 bxcr_num; + u32 bxcf; + int i; + int j; + phys_size_t base_addr; + u32 test[NUMMEMTESTS][NUMMEMWORDS] = { + {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, + {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, + {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, + {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, + {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, + {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, + {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, + {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} }; + int l; + + for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { + mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf); + + /* Banks enabled */ + if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { + /* Bank is enabled */ + + /* + * Only run test on accessable memory (below 2GB) + */ + base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)); + if (base_addr >= CONFIG_MAX_MEM_MAPPED) + continue; + + /*------------------------------------------------------------------ + * Run the short memory test. + *-----------------------------------------------------------------*/ + membase = (u32 *)(u32)base_addr; + + for (i = 0; i < NUMMEMTESTS; i++) { + for (j = 0; j < NUMMEMWORDS; j++) { + membase[j] = test[i][j]; + ppcDcbf((u32)&(membase[j])); + } + sync(); + for (l=0; l max_pass_length) { + max_pass_length = current_pass_length; + max_start = current_start; + max_end = rffd; + } + } + } else { + current_pass_length = 0; + current_fail_length++; + + if (current_fail_length >= (dly_val >> 2)) { + if (fail_found == FALSE) { + fail_found = TRUE; + } else if (pass_found == TRUE) { + window_found = TRUE; + break; + } + } + } + } /* for rffd */ + + /*------------------------------------------------------------------ + * Set the average RFFD value + *-----------------------------------------------------------------*/ + rffd_average = ((max_start + max_end) >> 1); + + if (rffd_average < 0) + rffd_average = 0; + + if (rffd_average > SDRAM_RFDC_RFFD_MAX) + rffd_average = SDRAM_RFDC_RFFD_MAX; + /* now fix RFDC[RFFD] found and find RQDC[RQFD] */ + mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); + +#if !defined(CONFIG_DDR_RQDC_FIXED) + max_pass_length = 0; + max_start = 0; + max_end = 0; + current_pass_length = 0; + current_fail_length = 0; + current_start = 0; + window_found = FALSE; + fail_found = FALSE; + pass_found = FALSE; + + for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { + mfsdram(SDRAM_RQDC, rqdc_reg); + rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); + + /*------------------------------------------------------------------ + * Set the timing reg for the test. + *-----------------------------------------------------------------*/ + mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd)); + + /*------------------------------------------------------------------ + * See if the rffd value passed. + *-----------------------------------------------------------------*/ + if (short_mem_test()) { + if (fail_found == TRUE) { + pass_found = TRUE; + if (current_pass_length == 0) + current_start = rqfd; + + current_fail_length = 0; + current_pass_length++; + + if (current_pass_length > max_pass_length) { + max_pass_length = current_pass_length; + max_start = current_start; + max_end = rqfd; + } + } + } else { + current_pass_length = 0; + current_fail_length++; + + if (fail_found == FALSE) { + fail_found = TRUE; + } else if (pass_found == TRUE) { + window_found = TRUE; + break; + } + } + } + + rqfd_average = ((max_start + max_end) >> 1); + + /*------------------------------------------------------------------ + * Make sure we found the valid read passing window. Halt if not + *-----------------------------------------------------------------*/ + if (window_found == FALSE) { + if (rqfd_start < SDRAM_RQDC_RQFD_MAX) { + putc('\b'); + putc(slash[loopi++ % 8]); + + /* try again from with a different RQFD start value */ + rqfd_start++; + goto calibration_loop; + } + + printf("\nERROR: Cannot determine a common read delay for the " + "DIMM(s) installed.\n"); + debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__); + ppc4xx_ibm_ddr2_register_dump(); + spd_ddr_init_hang (); + } + + if (rqfd_average < 0) + rqfd_average = 0; + + if (rqfd_average > SDRAM_RQDC_RQFD_MAX) + rqfd_average = SDRAM_RQDC_RQFD_MAX; + + mtsdram(SDRAM_RQDC, + (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | + SDRAM_RQDC_RQFD_ENCODE(rqfd_average)); + + blank_string(strlen(str)); +#endif /* CONFIG_DDR_RQDC_FIXED */ + + /* + * Now complete RDSS configuration as mentioned on page 7 of the AMCC + * PowerPC440SP/SPe DDR2 application note: + * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" + */ + mfsdram(SDRAM_RTSR, val); + if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) { + mfsdram(SDRAM_RDCC, val); + if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) { + val += 0x40000000; + mtsdram(SDRAM_RDCC, val); + } + } + + mfsdram(SDRAM_DLCR, val); + debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val); + mfsdram(SDRAM_RQDC, val); + debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val); + mfsdram(SDRAM_RFDC, val); + debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val); + mfsdram(SDRAM_RDCC, val); + debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val); +} +#else /* calibration test with hardvalues */ +/*-----------------------------------------------------------------------------+ + * DQS_calibration_process. + *-----------------------------------------------------------------------------*/ +static void test(void) +{ + unsigned long dimm_num; + unsigned long ecc_temp; + unsigned long i, j; + unsigned long *membase; + unsigned long bxcf[MAXRANKS]; + unsigned long val; + char window_found; + char begin_found[MAXDIMMS]; + char end_found[MAXDIMMS]; + char search_end[MAXDIMMS]; + unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { + {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, + {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, + {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, + {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, + {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, + {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, + {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, + {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} }; + + /*------------------------------------------------------------------ + * Test to determine the best read clock delay tuning bits. + * + * Before the DDR controller can be used, the read clock delay needs to be + * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD]. + * This value cannot be hardcoded into the program because it changes + * depending on the board's setup and environment. + * To do this, all delay values are tested to see if they + * work or not. By doing this, you get groups of fails with groups of + * passing values. The idea is to find the start and end of a passing + * window and take the center of it to use as the read clock delay. + * + * A failure has to be seen first so that when we hit a pass, we know + * that it is truely the start of the window. If we get passing values + * to start off with, we don't know if we are at the start of the window. + * + * The code assumes that a failure will always be found. + * If a failure is not found, there is no easy way to get the middle + * of the passing window. I guess we can pretty much pick any value + * but some values will be better than others. Since the lowest speed + * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed), + * from experimentation it is safe to say you will always have a failure. + *-----------------------------------------------------------------*/ + mfsdram(SDRAM_MCOPT1, ecc_temp); + ecc_temp &= SDRAM_MCOPT1_MCHK_MASK; + mfsdram(SDRAM_MCOPT1, val); + mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_NON); + + window_found = FALSE; + begin_found[0] = FALSE; + end_found[0] = FALSE; + search_end[0] = FALSE; + begin_found[1] = FALSE; + end_found[1] = FALSE; + search_end[1] = FALSE; + + for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { + mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]); + + /* Banks enabled */ + if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { + + /* Bank is enabled */ + membase = + (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num))); + + /*------------------------------------------------------------------ + * Run the short memory test. + *-----------------------------------------------------------------*/ + for (i = 0; i < NUMMEMTESTS; i++) { + for (j = 0; j < NUMMEMWORDS; j++) { + membase[j] = test[i][j]; + ppcDcbf((u32)&(membase[j])); + } + sync(); + for (j = 0; j < NUMMEMWORDS; j++) { + if (membase[j] != test[i][j]) { + ppcDcbf((u32)&(membase[j])); + break; + } + ppcDcbf((u32)&(membase[j])); + } + sync(); + if (j < NUMMEMWORDS) + break; + } + + /*------------------------------------------------------------------ + * See if the rffd value passed. + *-----------------------------------------------------------------*/ + if (i < NUMMEMTESTS) { + if ((end_found[dimm_num] == FALSE) && + (search_end[dimm_num] == TRUE)) { + end_found[dimm_num] = TRUE; + } + if ((end_found[0] == TRUE) && + (end_found[1] == TRUE)) + break; + } else { + if (begin_found[dimm_num] == FALSE) { + begin_found[dimm_num] = TRUE; + search_end[dimm_num] = TRUE; + } + } + } else { + begin_found[dimm_num] = TRUE; + end_found[dimm_num] = TRUE; + } + } + + if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE)) + window_found = TRUE; + + /*------------------------------------------------------------------ + * Make sure we found the valid read passing window. Halt if not + *-----------------------------------------------------------------*/ + if (window_found == FALSE) { + printf("ERROR: Cannot determine a common read delay for the " + "DIMM(s) installed.\n"); + spd_ddr_init_hang (); + } + + /*------------------------------------------------------------------ + * Restore the ECC variable to what it originally was + *-----------------------------------------------------------------*/ + mtsdram(SDRAM_MCOPT1, + (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK) + | ecc_temp); +} +#endif /* !HARD_CODED_DQS */ +#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */ + +#else /* CONFIG_SPD_EEPROM */ + +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller. + * The configuration is performed using static, compile- + * time parameters. + * Configures the PPC405EX(r) and PPC460EX/GT + *---------------------------------------------------------------------------*/ +phys_size_t initdram(int board_type) +{ + /* + * Only run this SDRAM init code once. For NAND booting + * targets like Kilauea, we call initdram() early from the + * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). + * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) + * which calls initdram() again. This time the controller + * mustn't be reconfigured again since we're already running + * from SDRAM. + */ +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + unsigned long val; + +#if defined(CONFIG_440) + mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS); + mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS); + mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS); + mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS); + mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */ + mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */ + mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL); + mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB); + mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB); +#endif + + /* Set Memory Bank Configuration Registers */ + + mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF); + mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF); + mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF); + mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF); + + /* Set Memory Clock Timing Register */ + + mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR); + + /* Set Refresh Time Register */ + + mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR); + + /* Set SDRAM Timing Registers */ + + mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1); + mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2); + mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3); + + /* Set Mode and Extended Mode Registers */ + + mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE); + mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE); + + /* Set Memory Controller Options 1 Register */ + + mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1); + + /* Set Manual Initialization Control Registers */ + + mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0); + mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1); + mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2); + mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3); + mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4); + mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5); + mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6); + mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7); + mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8); + mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9); + mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10); + mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11); + mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12); + mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13); + mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14); + mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15); + + /* Set On-Die Termination Registers */ + + mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT); + mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0); + mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1); + + /* Set Write Timing Register */ + + mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR); + + /* + * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and + * SDRAM0_MCOPT2[IPTR] = 1 + */ + + mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT | + SDRAM_MCOPT2_IPTR_EXECUTE)); + + /* + * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the + * completion of initialization. + */ + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); + + /* Set Delay Control Registers */ + + mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR); + +#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) + mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC); + mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC); + mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC); +#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ + + /* + * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: + */ + + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); + +#if defined(CONFIG_440) + /* + * Program TLB entries with caches enabled, for best performace + * while auto-calibrating and ECC generation + */ + program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0); +#endif + +#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /*------------------------------------------------------------------ + | DQS calibration. + +-----------------------------------------------------------------*/ + DQS_autocalibration(); +#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ +#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ + +#if defined(CONFIG_DDR_ECC) + do_program_ecc(0); +#endif /* defined(CONFIG_DDR_ECC) */ + +#if defined(CONFIG_440) + /* + * Now after initialization (auto-calibration and ECC generation) + * remove the TLB entries with caches enabled and program again with + * desired cache functionality + */ + remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20)); + program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE); +#endif + + ppc4xx_ibm_ddr2_register_dump(); + +#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); +#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ + +#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ + + return (CONFIG_SYS_MBYTES_SDRAM << 20); +} +#endif /* CONFIG_SPD_EEPROM */ + +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_440) +u32 mfdcr_any(u32 dcr) +{ + u32 val; + + switch (dcr) { + case SDRAM_R0BAS + 0: + val = mfdcr(SDRAM_R0BAS + 0); + break; + case SDRAM_R0BAS + 1: + val = mfdcr(SDRAM_R0BAS + 1); + break; + case SDRAM_R0BAS + 2: + val = mfdcr(SDRAM_R0BAS + 2); + break; + case SDRAM_R0BAS + 3: + val = mfdcr(SDRAM_R0BAS + 3); + break; + default: + printf("DCR %d not defined in case statement!!!\n", dcr); + val = 0; /* just to satisfy the compiler */ + } + + return val; +} + +void mtdcr_any(u32 dcr, u32 val) +{ + switch (dcr) { + case SDRAM_R0BAS + 0: + mtdcr(SDRAM_R0BAS + 0, val); + break; + case SDRAM_R0BAS + 1: + mtdcr(SDRAM_R0BAS + 1, val); + break; + case SDRAM_R0BAS + 2: + mtdcr(SDRAM_R0BAS + 2, val); + break; + case SDRAM_R0BAS + 3: + mtdcr(SDRAM_R0BAS + 3, val); + break; + default: + printf("DCR %d not defined in case statement!!!\n", dcr); + } +} +#endif /* defined(CONFIG_440) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ + +inline void ppc4xx_ibm_ddr2_register_dump(void) +{ +#if defined(DEBUG) + printf("\nPPC4xx IBM DDR2 Register Dump:\n"); + +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS); + PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS); + PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS); + PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS); +#endif /* (defined(CONFIG_440SP) || ... */ +#if defined(CONFIG_405EX) + PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL); + PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH); + PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ); + PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT); + PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA); +#endif /* defined(CONFIG_405EX) */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT); +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS); + /* + * OPART is only used as a trigger register. + * + * No data is contained in this register, and reading or writing + * to is can cause bad things to happen (hangs). Just skip it and + * report "N/A". + */ + printf("%20s = N/A\n", "SDRAM_OPART"); +#endif /* defined(CONFIG_440SP) || ... */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14); + PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC); + PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2); + PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE); + PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE); + PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES); +#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) + PPC4xx_IBM_DDR2_DUMP_REGISTER(CID); +#endif /* defined(CONFIG_440SP) || ... */ + PPC4xx_IBM_DDR2_DUMP_REGISTER(RID); + PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR); + PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR); +#endif /* defined(DEBUG) */ +} + +#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */ diff --git a/arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c new file mode 100644 index 0000000000..72630716c9 --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -0,0 +1,1251 @@ +/* + * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c + * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a + * DDR2 controller (non Denali Core). Those currently are: + * + * 405: 405EX + * 440/460: 440SP/440SPe/460EX/460GT/460SX + * + * (C) Copyright 2008 Applied Micro Circuits Corporation + * Adam Graham + * + * (C) Copyright 2007-2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * COPYRIGHT AMCC CORPORATION 2004 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#undef DEBUG + +#include +#include +#include +#include + +#include "ecc.h" + +#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) + +/* + * Only compile the DDR auto-calibration code for NOR boot and + * not for NAND boot (NAND SPL and NAND U-Boot - NUB) + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + +#define MAXBXCF 4 +#define SDRAM_RXBAS_SHIFT_1M 20 + +#if defined(CONFIG_SYS_DECREMENT_PATTERNS) +#define NUMMEMTESTS 24 +#else +#define NUMMEMTESTS 8 +#endif /* CONFIG_SYS_DECREMENT_PATTERNS */ +#define NUMLOOPS 1 /* configure as you deem approporiate */ +#define NUMMEMWORDS 16 + +#define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n)) + +/* Private Structure Definitions */ + +struct autocal_regs { + u32 rffd; + u32 rqfd; +}; + +struct ddrautocal { + u32 rffd; + u32 rffd_min; + u32 rffd_max; + u32 rffd_size; + u32 rqfd; + u32 rqfd_size; + u32 rdcc; + u32 flags; +}; + +struct sdram_timing { + u32 wrdtr; + u32 clktr; +}; + +struct sdram_timing_clks { + u32 wrdtr; + u32 clktr; + u32 rdcc; + u32 flags; +}; + +struct autocal_clks { + struct sdram_timing_clks clocks; + struct ddrautocal autocal; +}; + +/*--------------------------------------------------------------------------+ + * Prototypes + *--------------------------------------------------------------------------*/ +#if defined(CONFIG_PPC4xx_DDR_METHOD_A) +static u32 DQS_calibration_methodA(struct ddrautocal *); +static u32 program_DQS_calibration_methodA(struct ddrautocal *); +#else +static u32 DQS_calibration_methodB(struct ddrautocal *); +static u32 program_DQS_calibration_methodB(struct ddrautocal *); +#endif +static int short_mem_test(u32 *); + +/* + * To provide an interface for board specific config values in this common + * DDR setup code, we implement he "weak" default functions here. They return + * the default value back to the caller. + * + * Please see include/configs/yucca.h for an example fora board specific + * implementation. + */ + +#if !defined(CONFIG_SPD_EEPROM) +u32 __ddr_wrdtr(u32 default_val) +{ + return default_val; +} +u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr"))); + +u32 __ddr_clktr(u32 default_val) +{ + return default_val; +} +u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr"))); + +/* + * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed + */ +void __spd_ddr_init_hang(void) +{ + hang(); +} +void +spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang"))); +#endif /* defined(CONFIG_SPD_EEPROM) */ + +ulong __ddr_scan_option(ulong default_val) +{ + return default_val; +} +ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option"))); + +u32 __ddr_rdss_opt(u32 default_val) +{ + return default_val; +} +u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt"))); + + +static u32 *get_membase(int bxcr_num) +{ + ulong bxcf; + u32 *membase; + +#if defined(SDRAM_R0BAS) + /* BAS from Memory Queue rank reg. */ + membase = + (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num))); + bxcf = 0; /* just to satisfy the compiler */ +#else + /* BAS from SDRAM_MBxCF mem rank reg. */ + mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); + membase = (u32 *)((bxcf & 0xfff80000) << 3); +#endif + + return membase; +} + +static inline void ecc_clear_status_reg(void) +{ + mtsdram(SDRAM_ECCES, 0xffffffff); +#if defined(SDRAM_R0BAS) + mtdcr(SDRAM_ERRSTATLL, 0xffffffff); +#endif +} + +/* + * Reset and relock memory DLL after SDRAM_CLKTR change + */ +static inline void relock_memory_DLL(void) +{ + u32 reg; + + mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE); + + do { + mfsdram(SDRAM_MCSTAT, reg); + } while (!(reg & SDRAM_MCSTAT_MIC_COMP)); + + mfsdram(SDRAM_MCOPT2, reg); + mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE); +} + +static int ecc_check_status_reg(void) +{ + u32 ecc_status; + + /* + * Compare suceeded, now check + * if got ecc error. If got an + * ecc error, then don't count + * this as a passing value + */ + mfsdram(SDRAM_ECCES, ecc_status); + if (ecc_status != 0x00000000) { + /* clear on error */ + ecc_clear_status_reg(); + /* ecc check failure */ + return 0; + } + ecc_clear_status_reg(); + sync(); + + return 1; +} + +/* return 1 if passes, 0 if fail */ +static int short_mem_test(u32 *base_address) +{ + int i, j, l; + u32 ecc_mode = 0; + + ulong test[NUMMEMTESTS][NUMMEMWORDS] = { + /* 0 */ {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, + /* 1 */ {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, + /* 2 */ {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, + /* 3 */ {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, + /* 4 */ {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, + /* 5 */ {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, + /* 6 */ {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, + /* 7 */ {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}, + +#if defined(CONFIG_SYS_DECREMENT_PATTERNS) + /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}, + /* 9 */ {0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe, + 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe, + 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe, + 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe}, + /* 10 */{0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd, + 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd, + 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd, + 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd}, + /* 11 */{0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, + 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, + 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, + 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc}, + /* 12 */{0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb, + 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb, + 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb, + 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb}, + /* 13 */{0xfffafffa, 0xfffafffa, 0xfffffffa, 0xfffafffa, + 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa, + 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa, + 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa}, + /* 14 */{0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, + 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, + 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, + 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9}, + /* 15 */{0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, + 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, + 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, + 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8}, + /* 16 */{0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7, + 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7, + 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7, + 0xfff7ffff, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7}, + /* 17 */{0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7, + 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7, + 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7, + 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7}, + /* 18 */{0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5, + 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5, + 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5, + 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5}, + /* 19 */{0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4, + 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4, + 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4, + 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4}, + /* 20 */{0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3, + 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3, + 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3, + 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3}, + /* 21 */{0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2, + 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2, + 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2, + 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2}, + /* 22 */{0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1, + 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1, + 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1, + 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1}, + /* 23 */{0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, + 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, + 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, + 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0}, +#endif /* CONFIG_SYS_DECREMENT_PATTERNS */ + }; + + mfsdram(SDRAM_MCOPT1, ecc_mode); + if ((ecc_mode & SDRAM_MCOPT1_MCHK_CHK_REP) == + SDRAM_MCOPT1_MCHK_CHK_REP) { + ecc_clear_status_reg(); + sync(); + ecc_mode = 1; + } else { + ecc_mode = 0; + } + + /* + * Run the short memory test. + */ + for (i = 0; i < NUMMEMTESTS; i++) { + for (j = 0; j < NUMMEMWORDS; j++) { + base_address[j] = test[i][j]; + ppcDcbf((ulong)&(base_address[j])); + } + sync(); + iobarrier_rw(); + for (l = 0; l < NUMLOOPS; l++) { + for (j = 0; j < NUMMEMWORDS; j++) { + if (base_address[j] != test[i][j]) { + ppcDcbf((u32)&(base_address[j])); + return 0; + } else { + if (ecc_mode) { + if (!ecc_check_status_reg()) + return 0; + } + } + ppcDcbf((u32)&(base_address[j])); + } /* for (j = 0; j < NUMMEMWORDS; j++) */ + sync(); + iobarrier_rw(); + } /* for (l=0; lSDRAM_RDCC=0x%08x\n", __func__, temp); +#endif + + pass_result = DQS_calibration_methodA(ddrcal); + + return pass_result; +} + +/* + * DQS_calibration_methodA() + * + * Autocalibration Method A + * + * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros + * ARRAY [Entire FDBK Range] FDBK_Valid_Window; initialized to all zeros + * MEMWRITE(addr, expected_data); + * for (i = 0; i < Entire DQS Range; i++) { RQDC.RQFD + * for (j = 0; j < Entire FDBK Range; j++) { RFDC.RFFD + * MEMREAD(addr, actual_data); + * if (actual_data == expected_data) { + * DQS_Valid_Window[i] = 1; RQDC.RQFD + * FDBK_Valid_Window[i][j] = 1; RFDC.RFFD + * } + * } + * } + */ +static u32 DQS_calibration_methodA(struct ddrautocal *cal) +{ + ulong rfdc_reg; + ulong rffd; + + ulong rqdc_reg; + ulong rqfd; + + u32 *membase; + ulong bxcf; + int rqfd_average; + int bxcr_num; + int rffd_average; + int pass; + u32 passed = 0; + + int in_window; + struct autocal_regs curr_win_min; + struct autocal_regs curr_win_max; + struct autocal_regs best_win_min; + struct autocal_regs best_win_max; + struct autocal_regs loop_win_min; + struct autocal_regs loop_win_max; + +#ifdef DEBUG + ulong temp; +#endif + ulong rdcc; + + char slash[] = "\\|/-\\|/-"; + int loopi = 0; + + /* start */ + in_window = 0; + + memset(&curr_win_min, 0, sizeof(curr_win_min)); + memset(&curr_win_max, 0, sizeof(curr_win_max)); + memset(&best_win_min, 0, sizeof(best_win_min)); + memset(&best_win_max, 0, sizeof(best_win_max)); + memset(&loop_win_min, 0, sizeof(loop_win_min)); + memset(&loop_win_max, 0, sizeof(loop_win_max)); + + rdcc = 0; + + /* + * Program RDCC register + * Read sample cycle auto-update enable + */ + mtsdram(SDRAM_RDCC, + ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE); + +#ifdef DEBUG + mfsdram(SDRAM_RDCC, temp); + debug("<%s>SDRAM_RDCC=0x%x\n", __func__, temp); + mfsdram(SDRAM_RTSR, temp); + debug("<%s>SDRAM_RTSR=0x%x\n", __func__, temp); + mfsdram(SDRAM_FCSR, temp); + debug("<%s>SDRAM_FCSR=0x%x\n", __func__, temp); +#endif + + /* + * Program RQDC register + * Internal DQS delay mechanism enable + */ + mtsdram(SDRAM_RQDC, + SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x00)); + +#ifdef DEBUG + mfsdram(SDRAM_RQDC, temp); + debug("<%s>SDRAM_RQDC=0x%x\n", __func__, temp); +#endif + + /* + * Program RFDC register + * Set Feedback Fractional Oversample + * Auto-detect read sample cycle enable + */ + mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE | + SDRAM_RFDC_RFOS_ENCODE(0) | SDRAM_RFDC_RFFD_ENCODE(0)); + +#ifdef DEBUG + mfsdram(SDRAM_RFDC, temp); + debug("<%s>SDRAM_RFDC=0x%x\n", __func__, temp); +#endif + + putc(' '); + for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { + + mfsdram(SDRAM_RQDC, rqdc_reg); + rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); + mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd)); + + putc('\b'); + putc(slash[loopi++ % 8]); + + curr_win_min.rffd = 0; + curr_win_max.rffd = 0; + in_window = 0; + + for (rffd = 0, pass = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) { + mfsdram(SDRAM_RFDC, rfdc_reg); + rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); + mtsdram(SDRAM_RFDC, + rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd)); + + for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { + mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); + + /* Banks enabled */ + if (bxcf & SDRAM_BXCF_M_BE_MASK) { + /* Bank is enabled */ + membase = get_membase(bxcr_num); + pass = short_mem_test(membase); + } /* if bank enabled */ + } /* for bxcr_num */ + + /* If this value passed update RFFD windows */ + if (pass && !in_window) { /* at the start of window */ + in_window = 1; + curr_win_min.rffd = curr_win_max.rffd = rffd; + curr_win_min.rqfd = curr_win_max.rqfd = rqfd; + mfsdram(SDRAM_RDCC, rdcc); /*record this value*/ + } else if (!pass && in_window) { /* at end of window */ + in_window = 0; + } else if (pass && in_window) { /* within the window */ + curr_win_max.rffd = rffd; + curr_win_max.rqfd = rqfd; + } + /* else if (!pass && !in_window) + skip - no pass, not currently in a window */ + + if (in_window) { + if ((curr_win_max.rffd - curr_win_min.rffd) > + (best_win_max.rffd - best_win_min.rffd)) { + best_win_min.rffd = curr_win_min.rffd; + best_win_max.rffd = curr_win_max.rffd; + + best_win_min.rqfd = curr_win_min.rqfd; + best_win_max.rqfd = curr_win_max.rqfd; + cal->rdcc = rdcc; + } + passed = 1; + } + } /* RFDC.RFFD */ + + /* + * save-off the best window results of the RFDC.RFFD + * for this RQDC.RQFD setting + */ + /* + * if (just ended RFDC.RFDC loop pass window) > + * (prior RFDC.RFFD loop pass window) + */ + if ((best_win_max.rffd - best_win_min.rffd) > + (loop_win_max.rffd - loop_win_min.rffd)) { + loop_win_min.rffd = best_win_min.rffd; + loop_win_max.rffd = best_win_max.rffd; + loop_win_min.rqfd = rqfd; + loop_win_max.rqfd = rqfd; + debug("RQFD.min 0x%08x, RQFD.max 0x%08x, " + "RFFD.min 0x%08x, RFFD.max 0x%08x\n", + loop_win_min.rqfd, loop_win_max.rqfd, + loop_win_min.rffd, loop_win_max.rffd); + } + } /* RQDC.RQFD */ + + putc('\b'); + + debug("\n"); + + if ((loop_win_min.rffd == 0) && (loop_win_max.rffd == 0) && + (best_win_min.rffd == 0) && (best_win_max.rffd == 0) && + (best_win_min.rqfd == 0) && (best_win_max.rqfd == 0)) { + passed = 0; + } + + /* + * Need to program RQDC before RFDC. + */ + debug("<%s> RQFD Min: 0x%x\n", __func__, loop_win_min.rqfd); + debug("<%s> RQFD Max: 0x%x\n", __func__, loop_win_max.rqfd); + rqfd_average = loop_win_max.rqfd; + + if (rqfd_average < 0) + rqfd_average = 0; + + if (rqfd_average > SDRAM_RQDC_RQFD_MAX) + rqfd_average = SDRAM_RQDC_RQFD_MAX; + + debug("<%s> RFFD average: 0x%08x\n", __func__, rqfd_average); + mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | + SDRAM_RQDC_RQFD_ENCODE(rqfd_average)); + + debug("<%s> RFFD Min: 0x%08x\n", __func__, loop_win_min.rffd); + debug("<%s> RFFD Max: 0x%08x\n", __func__, loop_win_max.rffd); + rffd_average = ((loop_win_min.rffd + loop_win_max.rffd) / 2); + + if (rffd_average < 0) + rffd_average = 0; + + if (rffd_average > SDRAM_RFDC_RFFD_MAX) + rffd_average = SDRAM_RFDC_RFFD_MAX; + + debug("<%s> RFFD average: 0x%08x\n", __func__, rffd_average); + mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); + + /* if something passed, then return the size of the largest window */ + if (passed != 0) { + passed = loop_win_max.rffd - loop_win_min.rffd; + cal->rqfd = rqfd_average; + cal->rffd = rffd_average; + cal->rffd_min = loop_win_min.rffd; + cal->rffd_max = loop_win_max.rffd; + } + + return (u32)passed; +} + +#else /* !defined(CONFIG_PPC4xx_DDR_METHOD_A) */ + +/*-----------------------------------------------------------------------------+ +| program_DQS_calibration_methodB. ++-----------------------------------------------------------------------------*/ +static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal) +{ + u32 pass_result = 0; + +#ifdef DEBUG + ulong temp; +#endif + + /* + * Program RDCC register + * Read sample cycle auto-update enable + */ + mtsdram(SDRAM_RDCC, + ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE); + +#ifdef DEBUG + mfsdram(SDRAM_RDCC, temp); + debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp); +#endif + + /* + * Program RQDC register + * Internal DQS delay mechanism enable + */ + mtsdram(SDRAM_RQDC, +#if defined(CONFIG_DDR_RQDC_START_VAL) + SDRAM_RQDC_RQDE_ENABLE | + SDRAM_RQDC_RQFD_ENCODE(CONFIG_DDR_RQDC_START_VAL)); +#else + SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x38)); +#endif + +#ifdef DEBUG + mfsdram(SDRAM_RQDC, temp); + debug("<%s>SDRAM_RQDC=0x%08x\n", __func__, temp); +#endif + + /* + * Program RFDC register + * Set Feedback Fractional Oversample + * Auto-detect read sample cycle enable + */ + mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE | + SDRAM_RFDC_RFOS_ENCODE(0) | + SDRAM_RFDC_RFFD_ENCODE(0)); + +#ifdef DEBUG + mfsdram(SDRAM_RFDC, temp); + debug("<%s>SDRAM_RFDC=0x%08x\n", __func__, temp); +#endif + + pass_result = DQS_calibration_methodB(ddrcal); + + return pass_result; +} + +/* + * DQS_calibration_methodB() + * + * Autocalibration Method B + * + * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros + * ARRAY [Entire Feedback Range] FDBK_Valid_Window; initialized to all zeros + * MEMWRITE(addr, expected_data); + * Initialialize the DQS delay to 80 degrees (MCIF0_RRQDC[RQFD]=0x38). + * + * for (j = 0; j < Entire Feedback Range; j++) { + * MEMREAD(addr, actual_data); + * if (actual_data == expected_data) { + * FDBK_Valid_Window[j] = 1; + * } + * } + * + * Set MCIF0_RFDC[RFFD] to the middle of the FDBK_Valid_Window. + * + * for (i = 0; i < Entire DQS Range; i++) { + * MEMREAD(addr, actual_data); + * if (actual_data == expected_data) { + * DQS_Valid_Window[i] = 1; + * } + * } + * + * Set MCIF0_RRQDC[RQFD] to the middle of the DQS_Valid_Window. + */ +/*-----------------------------------------------------------------------------+ +| DQS_calibration_methodB. ++-----------------------------------------------------------------------------*/ +static u32 DQS_calibration_methodB(struct ddrautocal *cal) +{ + ulong rfdc_reg; + ulong rffd; + + ulong rqdc_reg; + ulong rqfd; + + ulong rdcc; + + u32 *membase; + ulong bxcf; + int rqfd_average; + int bxcr_num; + int rffd_average; + int pass; + uint passed = 0; + + int in_window; + u32 curr_win_min, curr_win_max; + u32 best_win_min, best_win_max; + u32 size = 0; + + /*------------------------------------------------------------------ + | Test to determine the best read clock delay tuning bits. + | + | Before the DDR controller can be used, the read clock delay needs to + | be set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD]. + | This value cannot be hardcoded into the program because it changes + | depending on the board's setup and environment. + | To do this, all delay values are tested to see if they + | work or not. By doing this, you get groups of fails with groups of + | passing values. The idea is to find the start and end of a passing + | window and take the center of it to use as the read clock delay. + | + | A failure has to be seen first so that when we hit a pass, we know + | that it is truely the start of the window. If we get passing values + | to start off with, we don't know if we are at the start of the window + | + | The code assumes that a failure will always be found. + | If a failure is not found, there is no easy way to get the middle + | of the passing window. I guess we can pretty much pick any value + | but some values will be better than others. Since the lowest speed + | we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed), + | from experimentation it is safe to say you will always have a failure + +-----------------------------------------------------------------*/ + + debug("\n\n"); + + in_window = 0; + rdcc = 0; + + curr_win_min = curr_win_max = 0; + best_win_min = best_win_max = 0; + for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) { + mfsdram(SDRAM_RFDC, rfdc_reg); + rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); + mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd)); + + pass = 1; + for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { + mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); + + /* Banks enabled */ + if (bxcf & SDRAM_BXCF_M_BE_MASK) { + /* Bank is enabled */ + membase = get_membase(bxcr_num); + pass &= short_mem_test(membase); + } /* if bank enabled */ + } /* for bxcf_num */ + + /* If this value passed */ + if (pass && !in_window) { /* start of passing window */ + in_window = 1; + curr_win_min = curr_win_max = rffd; + mfsdram(SDRAM_RDCC, rdcc); /* record this value */ + } else if (!pass && in_window) { /* end passing window */ + in_window = 0; + } else if (pass && in_window) { /* within the passing window */ + curr_win_max = rffd; + } + + if (in_window) { + if ((curr_win_max - curr_win_min) > + (best_win_max - best_win_min)) { + best_win_min = curr_win_min; + best_win_max = curr_win_max; + cal->rdcc = rdcc; + } + passed = 1; + } + } /* for rffd */ + + if ((best_win_min == 0) && (best_win_max == 0)) + passed = 0; + else + size = best_win_max - best_win_min; + + debug("RFFD Min: 0x%x\n", best_win_min); + debug("RFFD Max: 0x%x\n", best_win_max); + rffd_average = ((best_win_min + best_win_max) / 2); + + cal->rffd_min = best_win_min; + cal->rffd_max = best_win_max; + + if (rffd_average < 0) + rffd_average = 0; + + if (rffd_average > SDRAM_RFDC_RFFD_MAX) + rffd_average = SDRAM_RFDC_RFFD_MAX; + + mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); + + rffd = rffd_average; + in_window = 0; + + curr_win_min = curr_win_max = 0; + best_win_min = best_win_max = 0; + for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { + mfsdram(SDRAM_RQDC, rqdc_reg); + rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); + mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd)); + + pass = 1; + for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { + + mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); + + /* Banks enabled */ + if (bxcf & SDRAM_BXCF_M_BE_MASK) { + /* Bank is enabled */ + membase = get_membase(bxcr_num); + pass &= short_mem_test(membase); + } /* if bank enabled */ + } /* for bxcf_num */ + + /* If this value passed */ + if (pass && !in_window) { + in_window = 1; + curr_win_min = curr_win_max = rqfd; + } else if (!pass && in_window) { + in_window = 0; + } else if (pass && in_window) { + curr_win_max = rqfd; + } + + if (in_window) { + if ((curr_win_max - curr_win_min) > + (best_win_max - best_win_min)) { + best_win_min = curr_win_min; + best_win_max = curr_win_max; + } + passed = 1; + } + } /* for rqfd */ + + if ((best_win_min == 0) && (best_win_max == 0)) + passed = 0; + + debug("RQFD Min: 0x%x\n", best_win_min); + debug("RQFD Max: 0x%x\n", best_win_max); + rqfd_average = ((best_win_min + best_win_max) / 2); + + if (rqfd_average < 0) + rqfd_average = 0; + + if (rqfd_average > SDRAM_RQDC_RQFD_MAX) + rqfd_average = SDRAM_RQDC_RQFD_MAX; + + mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | + SDRAM_RQDC_RQFD_ENCODE(rqfd_average)); + + mfsdram(SDRAM_RQDC, rqdc_reg); + mfsdram(SDRAM_RFDC, rfdc_reg); + + /* + * Need to program RQDC before RFDC. The value is read above. + * That is the reason why auto cal not work. + * See, comments below. + */ + mtsdram(SDRAM_RQDC, rqdc_reg); + mtsdram(SDRAM_RFDC, rfdc_reg); + + debug("RQDC: 0x%08X\n", rqdc_reg); + debug("RFDC: 0x%08X\n", rfdc_reg); + + /* if something passed, then return the size of the largest window */ + if (passed != 0) { + passed = size; + cal->rqfd = rqfd_average; + cal->rffd = rffd_average; + } + + return (uint)passed; +} +#endif /* defined(CONFIG_PPC4xx_DDR_METHOD_A) */ + +/* + * Default table for DDR auto-calibration of all + * possible WRDTR and CLKTR values. + * Table format is: + * {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} + * + * Table is terminated with {-1, -1} value pair. + * + * Board vendors can specify their own board specific subset of + * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value + * pairs via a board defined ddr_scan_option() function. + */ +struct sdram_timing full_scan_options[] = { + {0, 0}, {0, 1}, {0, 2}, {0, 3}, + {1, 0}, {1, 1}, {1, 2}, {1, 3}, + {2, 0}, {2, 1}, {2, 2}, {2, 3}, + {3, 0}, {3, 1}, {3, 2}, {3, 3}, + {4, 0}, {4, 1}, {4, 2}, {4, 3}, + {5, 0}, {5, 1}, {5, 2}, {5, 3}, + {6, 0}, {6, 1}, {6, 2}, {6, 3}, + {-1, -1} +}; + +/*---------------------------------------------------------------------------+ +| DQS_calibration. ++----------------------------------------------------------------------------*/ +u32 DQS_autocalibration(void) +{ + u32 wdtr; + u32 clkp; + u32 result = 0; + u32 best_result = 0; + u32 best_rdcc; + struct ddrautocal ddrcal; + struct autocal_clks tcal; + ulong rfdc_reg; + ulong rqdc_reg; + u32 val; + int verbose_lvl = 0; + char *str; + char slash[] = "\\|/-\\|/-"; + int loopi = 0; + struct sdram_timing *scan_list; + +#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION) + int i; + char tmp[64]; /* long enough for environment variables */ +#endif + + memset(&tcal, 0, sizeof(tcal)); + + ddr_scan_option((ulong)full_scan_options); + + scan_list = + (struct sdram_timing *)ddr_scan_option((ulong)full_scan_options); + + mfsdram(SDRAM_MCOPT1, val); + if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP) + str = "ECC Auto calibration -"; + else + str = "Auto calibration -"; + + puts(str); + +#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION) + i = getenv_r("autocalib", tmp, sizeof(tmp)); + if (i < 0) + strcpy(tmp, CONFIG_AUTOCALIB); + + if (strcmp(tmp, "final") == 0) { + /* display the final autocalibration results only */ + verbose_lvl = 1; + } else if (strcmp(tmp, "loop") == 0) { + /* display summary autocalibration info per iteration */ + verbose_lvl = 2; + } else if (strcmp(tmp, "display") == 0) { + /* display full debug autocalibration window info. */ + verbose_lvl = 3; + } +#endif /* (DEBUG_PPC4xx_DDR_AUTOCALIBRATION) */ + + best_rdcc = (SDRAM_RDCC_RDSS_T4 >> 30); + + while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) { + wdtr = scan_list->wrdtr; + clkp = scan_list->clktr; + + mfsdram(SDRAM_WRDTR, val); + val &= ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK); + mtsdram(SDRAM_WRDTR, (val | + ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | (wdtr << 25)))); + + mtsdram(SDRAM_CLKTR, clkp << 30); + + relock_memory_DLL(); + + putc('\b'); + putc(slash[loopi++ % 8]); + +#ifdef DEBUG + debug("\n"); + debug("*** --------------\n"); + mfsdram(SDRAM_WRDTR, val); + debug("*** SDRAM_WRDTR set to 0x%08x\n", val); + mfsdram(SDRAM_CLKTR, val); + debug("*** SDRAM_CLKTR set to 0x%08x\n", val); +#endif + + debug("\n"); + if (verbose_lvl > 2) { + printf("*** SDRAM_WRDTR (wdtr) set to %d\n", wdtr); + printf("*** SDRAM_CLKTR (clkp) set to %d\n", clkp); + } + + memset(&ddrcal, 0, sizeof(ddrcal)); + + /* + * DQS calibration. + */ + /* + * program_DQS_calibration_method[A|B]() returns 0 if no + * passing RFDC.[RFFD] window is found or returns the size + * of the best passing window; in the case of a found passing + * window, the ddrcal will contain the values of the best + * window RQDC.[RQFD] and RFDC.[RFFD]. + */ + + /* + * Call PPC4xx SDRAM DDR autocalibration methodA or methodB. + * Default is methodB. + * Defined the autocalibration method in the board specific + * header file. + * Please see include/configs/kilauea.h for an example for + * a board specific implementation. + */ +#if defined(CONFIG_PPC4xx_DDR_METHOD_A) + result = program_DQS_calibration_methodA(&ddrcal); +#else + result = program_DQS_calibration_methodB(&ddrcal); +#endif + + sync(); + + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + + val = ddrcal.rdcc; /* RDCC from the best passing window */ + + udelay(100); + + if (verbose_lvl > 1) { + char *tstr; + switch ((val >> 30)) { + case 0: + if (result != 0) + tstr = "T1"; + else + tstr = "N/A"; + break; + case 1: + tstr = "T2"; + break; + case 2: + tstr = "T3"; + break; + case 3: + tstr = "T4"; + break; + default: + tstr = "unknown"; + break; + } + printf("** WRDTR(%d) CLKTR(%d), Wind (%d), best (%d), " + "max-min(0x%04x)(0x%04x), RDCC: %s\n", + wdtr, clkp, result, best_result, + ddrcal.rffd_min, ddrcal.rffd_max, tstr); + } + + /* + * The DQS calibration "result" is either "0" + * if no passing window was found, or is the + * size of the RFFD passing window. + */ + /* + * want the lowest Read Sample Cycle Select + */ + val = SDRAM_RDCC_RDSS_DECODE(val); + debug("*** (%d) (%d) current_rdcc, best_rdcc\n", + val, best_rdcc); + + if ((result != 0) && + (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) { + if (((result == best_result) && (val < best_rdcc)) || + ((result > best_result) && (val <= best_rdcc))) { + tcal.autocal.flags = 1; + debug("*** (%d)(%d) result passed window " + "size: 0x%08x, rqfd = 0x%08x, " + "rffd = 0x%08x, rdcc = 0x%08x\n", + wdtr, clkp, result, ddrcal.rqfd, + ddrcal.rffd, ddrcal.rdcc); + + /* + * Save the SDRAM_WRDTR and SDRAM_CLKTR + * settings for the largest returned + * RFFD passing window size. + */ + best_rdcc = val; + tcal.clocks.wrdtr = wdtr; + tcal.clocks.clktr = clkp; + tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val); + tcal.autocal.rqfd = ddrcal.rqfd; + tcal.autocal.rffd = ddrcal.rffd; + best_result = result; + + if (verbose_lvl > 2) { + printf("** (%d)(%d) " + "best result: 0x%04x\n", + wdtr, clkp, + best_result); + printf("** (%d)(%d) " + "best WRDTR: 0x%04x\n", + wdtr, clkp, + tcal.clocks.wrdtr); + printf("** (%d)(%d) " + "best CLKTR: 0x%04x\n", + wdtr, clkp, + tcal.clocks.clktr); + printf("** (%d)(%d) " + "best RQDC: 0x%04x\n", + wdtr, clkp, + tcal.autocal.rqfd); + printf("** (%d)(%d) " + "best RFDC: 0x%04x\n", + wdtr, clkp, + tcal.autocal.rffd); + printf("** (%d)(%d) " + "best RDCC: 0x%08x\n", + wdtr, clkp, + (u32)tcal.clocks.rdcc); + mfsdram(SDRAM_RTSR, val); + printf("** (%d)(%d) best " + "loop RTSR: 0x%08x\n", + wdtr, clkp, val); + mfsdram(SDRAM_FCSR, val); + printf("** (%d)(%d) best " + "loop FCSR: 0x%08x\n", + wdtr, clkp, val); + } + } + } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */ + scan_list++; + } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */ + + if (tcal.autocal.flags == 1) { + if (verbose_lvl > 0) { + printf("*** --------------\n"); + printf("*** best_result window size: %d\n", + best_result); + printf("*** best_result WRDTR: 0x%04x\n", + tcal.clocks.wrdtr); + printf("*** best_result CLKTR: 0x%04x\n", + tcal.clocks.clktr); + printf("*** best_result RQFD: 0x%04x\n", + tcal.autocal.rqfd); + printf("*** best_result RFFD: 0x%04x\n", + tcal.autocal.rffd); + printf("*** best_result RDCC: 0x%04x\n", + tcal.clocks.rdcc); + printf("*** --------------\n"); + printf("\n"); + } + + /* + * if got best passing result window, then lock in the + * best CLKTR, WRDTR, RQFD, and RFFD values + */ + mfsdram(SDRAM_WRDTR, val); + mtsdram(SDRAM_WRDTR, (val & + ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) | + ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | + (tcal.clocks.wrdtr << 25))); + + mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30); + + relock_memory_DLL(); + + mfsdram(SDRAM_RQDC, rqdc_reg); + rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); + mtsdram(SDRAM_RQDC, rqdc_reg | + SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd)); + + mfsdram(SDRAM_RQDC, rqdc_reg); + debug("*** best_result: read value SDRAM_RQDC 0x%08x\n", + rqdc_reg); + + mfsdram(SDRAM_RFDC, rfdc_reg); + rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); + mtsdram(SDRAM_RFDC, rfdc_reg | + SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd)); + + mfsdram(SDRAM_RFDC, rfdc_reg); + debug("*** best_result: read value SDRAM_RFDC 0x%08x\n", + rfdc_reg); + mfsdram(SDRAM_RDCC, val); + debug("*** SDRAM_RDCC 0x%08x\n", val); + } else { + /* + * no valid windows were found + */ + printf("DQS memory calibration window can not be determined, " + "terminating u-boot.\n"); + ppc4xx_ibm_ddr2_register_dump(); + spd_ddr_init_hang(); + } + + blank_string(strlen(str)); + + return 0; +} +#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ +u32 DQS_autocalibration(void) +{ + return 0; +} +#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ +#endif /* defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */ diff --git a/cpu/ppc4xx/4xx_pci.c b/arch/ppc/cpu/ppc4xx/4xx_pci.c similarity index 100% rename from cpu/ppc4xx/4xx_pci.c rename to arch/ppc/cpu/ppc4xx/4xx_pci.c diff --git a/arch/ppc/cpu/ppc4xx/4xx_pcie.c b/arch/ppc/cpu/ppc4xx/4xx_pcie.c new file mode 100644 index 0000000000..10b58b7118 --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/4xx_pcie.c @@ -0,0 +1,1298 @@ +/* + * (C) Copyright 2006 - 2008 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include + +#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ + defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE) + +#include + +enum { + PTYPE_ENDPOINT = 0x0, + PTYPE_LEGACY_ENDPOINT = 0x1, + PTYPE_ROOT_PORT = 0x4, + + LNKW_X1 = 0x1, + LNKW_X4 = 0x4, + LNKW_X8 = 0x8 +}; + +static struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS]; + +/* + * Per default, all cards are present, so we need to check if the + * link comes up. + */ +int __board_pcie_card_present(int port) +{ + return 1; +} +int board_pcie_card_present(int port) + __attribute__((weak, alias("__board_pcie_card_present"))); + +/* + * Some boards have runtime detection of the first and last PCIe + * slot used, so let's provide weak default functions for the + * common version. + */ +int __board_pcie_first(void) +{ + return 0; +} +int board_pcie_first(void) + __attribute__((weak, alias("__board_pcie_first"))); + +int __board_pcie_last(void) +{ + return CONFIG_SYS_PCIE_NR_PORTS - 1; +} +int board_pcie_last(void) + __attribute__((weak, alias("__board_pcie_last"))); + +void __board_pcie_setup_port(int port, int rootpoint) +{ + /* noting in this weak default implementation */ +} +void board_pcie_setup_port(int port, int rootpoint) + __attribute__((weak, alias("__board_pcie_setup_port"))); + +void pcie_setup_hoses(int busno) +{ + struct pci_controller *hose; + int i, bus; + int ret = 0; + char *env; + unsigned int delay; + int first = board_pcie_first(); + int last = board_pcie_last(); + + /* + * Assume we're called after the PCI(X) hose(s) are initialized, + * which takes bus ID 0... and therefore start numbering PCIe's + * from the next number. + */ + bus = busno; + + for (i = first; i <= last; i++) { + /* + * Some boards (e.g. Katmai) can detects via hardware + * if a PCIe card is plugged, so let's check this. + */ + if (!board_pcie_card_present(i)) + continue; + + if (is_end_point(i)) { + board_pcie_setup_port(i, 0); + ret = ppc4xx_init_pcie_endport(i); + } else { + board_pcie_setup_port(i, 1); + ret = ppc4xx_init_pcie_rootport(i); + } + if (ret == -ENODEV) + continue; + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + hose->current_busno = bus; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMSIZE, + PCI_REGION_MEM); + hose->region_count = 1; + pci_register_hose(hose); + + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } + } +} + +static int validate_endpoint(struct pci_controller *hose) +{ + if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE) + return (is_end_point(0)); + else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE) + return (is_end_point(1)); +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE) + return (is_end_point(2)); +#endif + + return 0; +} + +static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) +{ + u8 *base = (u8*)hose->cfg_data; + + /* use local configuration space for the first bus */ + if (PCI_BUS(devfn) == 0) { + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE; + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE; +#endif + } + + return base; +} + +static void pcie_dmer_disable(void) +{ + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); +#endif +} + +static void pcie_dmer_enable(void) +{ + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); +#endif +} + +static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 *val) { + + u8 *address; + *val = 0; + + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * NOTICE: configuration space ranges are currenlty mapped only for + * the first 16 buses, so such limit must be imposed. In case more + * buses are required the TLB settings in board/amcc//init.S + * need to be altered accordingly (one bus takes 1 MB of memory space). + */ + if (PCI_BUS(devfn) >= 16) + return 0; + + /* + * Only single device/single function is supported for the primary and + * secondary buses of the 440SPe host bridge. + */ + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); + offset += devfn << 4; + + /* + * Reading from configuration space of non-existing device can + * generate transaction errors. For the read duration we suppress + * assertion of machine check exceptions to avoid those. + */ + pcie_dmer_disable (); + + debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset); + switch (len) { + case 1: + *val = in_8(hose->cfg_data + offset); + break; + case 2: + *val = in_le16((u16 *)(hose->cfg_data + offset)); + break; + default: + *val = in_le32((u32*)(hose->cfg_data + offset)); + break; + } + + pcie_dmer_enable (); + + return 0; +} + +static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 val) { + + u8 *address; + + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * Same constraints as in pcie_read_config(). + */ + if (PCI_BUS(devfn) >= 16) + return 0; + + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); + offset += devfn << 4; + + /* + * Suppress MCK exceptions, similar to pcie_read_config() + */ + pcie_dmer_disable (); + + switch (len) { + case 1: + out_8(hose->cfg_data + offset, val); + break; + case 2: + out_le16((u16 *)(hose->cfg_data + offset), val); + break; + default: + out_le32((u32 *)(hose->cfg_data + offset), val); + break; + } + + pcie_dmer_enable (); + + return 0; +} + +int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 1, &v); + *val = (u8)v; + return rv; +} + +int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 2, &v); + *val = (u16)v; + return rv; +} + +int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 3, &v); + *val = (u32)v; + return rv; +} + +int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) +{ + return pcie_write_config(hose,(u32)dev,offset,1,val); +} + +int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) +{ + return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); +} + +int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) +{ + return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); +} + +#if defined(CONFIG_440SPE) +static void ppc4xx_setup_utl(u32 port) { + + volatile void *utl_base = NULL; + + /* + * Map UTL registers + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); + break; + + case 2: + mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); + break; + } + utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); + out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); +} + +static int check_error(void) +{ + u32 valPE0, valPE1, valPE2; + int err = 0; + + /* SDR0_PEGPLLLCT1 reset */ + if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) + printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); + + valPE0 = SDR_READ(PESDR0_RCSSET); + valPE1 = SDR_READ(PESDR1_RCSSET); + valPE2 = SDR_READ(PESDR2_RCSSET); + + /* SDR0_PExRCSSET rstgu */ + if (!(valPE0 & 0x01000000) || + !(valPE1 & 0x01000000) || + !(valPE2 & 0x01000000)) { + printf("PCIE: SDR0_PExRCSSET rstgu error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstdl */ + if (!(valPE0 & 0x00010000) || + !(valPE1 & 0x00010000) || + !(valPE2 & 0x00010000)) { + printf("PCIE: SDR0_PExRCSSET rstdl error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstpyn */ + if ((valPE0 & 0x00001000) || + (valPE1 & 0x00001000) || + (valPE2 & 0x00001000)) { + printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); + err = -1; + } + + /* SDR0_PExRCSSET hldplb */ + if ((valPE0 & 0x10000000) || + (valPE1 & 0x10000000) || + (valPE2 & 0x10000000)) { + printf("PCIE: SDR0_PExRCSSET hldplb error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rdy */ + if ((valPE0 & 0x00100000) || + (valPE1 & 0x00100000) || + (valPE2 & 0x00100000)) { + printf("PCIE: SDR0_PExRCSSET rdy error\n"); + err = -1; + } + + /* SDR0_PExRCSSET shutdown */ + if ((valPE0 & 0x00000100) || + (valPE1 & 0x00000100) || + (valPE2 & 0x00000100)) { + printf("PCIE: SDR0_PExRCSSET shutdown error\n"); + err = -1; + } + return err; +} + +/* + * Initialize PCI Express core + */ +int ppc4xx_init_pcie(void) +{ + int time_out = 20; + + /* Set PLL clock receiver to LVPECL */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); + + if (check_error()) { + printf("ERROR: failed to set PCIe reference clock receiver --" + "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1)); + + return -1; + } + + /* Did resistance calibration work? */ + if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) { + printf("ERROR: PCIe resistance calibration failed --" + "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2)); + + return -1; + } + /* De-assert reset of PCIe PLL, wait for lock */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); + udelay(300); /* 300 uS is maximum time lock should take */ + + while (time_out) { + if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { + time_out--; + udelay(20); /* Wait 20 uS more if needed */ + } else + break; + } + if (!time_out) { + printf("ERROR: PCIe PLL VCO output not locked to ref clock --" + "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3)); + + return -1; + } + return 0; +} +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +static void ppc4xx_setup_utl(u32 port) +{ + volatile void *utl_base = NULL; + + /* + * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE) + + 0x1000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); + break; + } + utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */ + out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */ + out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */ + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */ +} + +/* + * TODO: double check PCI express SDR based on the latest user manual + * Some registers specified here no longer exist.. has to be + * updated based on the final EAS spec. + */ +static int check_error(void) +{ + u32 valPE0, valPE1; + int err = 0; + + valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0)); + valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1)); + + /* SDR0_PExRCSSET rstgu */ + if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) { + printf("PCIE: SDR0_PExRCSSET rstgu error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstdl */ + if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) { + printf("PCIE: SDR0_PExRCSSET rstdl error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstpyn */ + if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) { + printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); + err = -1; + } + + /* SDR0_PExRCSSET hldplb */ + if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) { + printf("PCIE: SDR0_PExRCSSET hldplb error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rdy */ + if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) { + printf("PCIE: SDR0_PExRCSSET rdy error\n"); + err = -1; + } + + return err; +} + +/* + * Initialize PCI Express core as described in User Manual + * TODO: double check PE SDR PLL Register with the updated user manual. + */ +int ppc4xx_init_pcie(void) +{ + if (check_error()) + return -1; + + return 0; +} +#endif /* CONFIG_460EX */ + +#if defined(CONFIG_405EX) +static void ppc4xx_setup_utl(u32 port) +{ + u32 utl_base; + + /* + * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); + + break; + } + utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE; + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000); + out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000); + out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066); + + out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c); + out_be32((u32 *)(utl_base + PEUTL_RCSTA), + in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000); +} + +int ppc4xx_init_pcie(void) +{ + /* + * Nothing to do on 405EX + */ + return 0; +} +#endif /* CONFIG_405EX */ + +/* + * Board-specific pcie initialization + * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed + */ + +/* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a root port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it + * with default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ +#if defined(CONFIG_440SPE) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val = 1 << 24; + u32 utlset1; + + if (rootport) { + val = PTYPE_ROOT_PORT << 20; + utlset1 = 0x21222222; + } else { + val = PTYPE_LEGACY_ENDPOINT << 20; + utlset1 = 0x20222222; + } + + if (port == 0) + val |= LNKW_X8 << 12; + else + val |= LNKW_X4 << 12; + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); + if (!ppc440spe_revB()) + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000); + SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000); + if (port == 0) { + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + } + SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) & + ~(1 << 24 | 1 << 16)) | 1 << 12); + + return 0; +} +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val; + u32 utlset1; + + if (rootport) + val = PTYPE_ROOT_PORT << 20; + else + val = PTYPE_LEGACY_ENDPOINT << 20; + + if (port == 0) { + val |= LNKW_X1 << 12; + utlset1 = 0x20000000; + } else { + val |= LNKW_X4 << 12; + utlset1 = 0x20101101; + } + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000); + + switch (port) { + case 0: + SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230); + SDR_WRITE(PESDR0_L0DRV, 0x00000130); + SDR_WRITE(PESDR0_L0CLK, 0x00000006); + + SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000); + break; + + case 1: + SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L0DRV, 0x00000130); + SDR_WRITE(PESDR1_L1DRV, 0x00000130); + SDR_WRITE(PESDR1_L2DRV, 0x00000130); + SDR_WRITE(PESDR1_L3DRV, 0x00000130); + SDR_WRITE(PESDR1_L0CLK, 0x00000006); + SDR_WRITE(PESDR1_L1CLK, 0x00000006); + SDR_WRITE(PESDR1_L2CLK, 0x00000006); + SDR_WRITE(PESDR1_L3CLK, 0x00000006); + + SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000); + break; + } + + SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) | + (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); + + /* Poll for PHY reset */ + switch (port) { + case 0: + while (!(SDR_READ(PESDR0_RSTSTA) & 0x1)) + udelay(10); + break; + case 1: + while (!(SDR_READ(PESDR1_RSTSTA) & 0x1)) + udelay(10); + break; + } + + SDR_WRITE(SDRN_PESDR_RCSSET(port), + (SDR_READ(SDRN_PESDR_RCSSET(port)) & + ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | + PESDRx_RCSSET_RSTPYN); + + return 0; +} +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_405EX) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val; + + if (rootport) + val = 0x00401000; + else + val = 0x00101000; + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000); + SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); + SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); + + /* Assert the PE0_PHY reset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000); + udelay(1000); + + /* deassert the PE0_hotreset */ + if (is_end_point(port)) + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000); + else + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); + + /* poll for phy !reset */ + while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) + ; + + /* deassert the PE0_gpl_utl_reset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000); + + if (port == 0) + mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */ + else + mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */ + + return 0; +} +#endif /* CONFIG_405EX */ + +int ppc4xx_init_pcie_port_hw(int port, int rootport) +__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); + +/* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For 440SPe revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For 440SPe revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + * + * For 405EX: + * PCIE0: 0xa000_0000 + * PCIE1: 0xc000_0000 + * + * For 460EX/GT: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + */ +static inline u64 ppc4xx_get_cfgaddr(int port) +{ +#if defined(CONFIG_405EX) + if (port == 0) + return (u64)CONFIG_SYS_PCIE0_CFGBASE; + else + return (u64)CONFIG_SYS_PCIE1_CFGBASE; +#endif +#if defined(CONFIG_440SPE) + if (ppc440spe_revB()) { + switch (port) { + default: /* to satisfy compiler */ + case 0: + return 0x0000000d00000000ULL; + case 1: + return 0x0000000d20000000ULL; + case 2: + return 0x0000000d40000000ULL; + } + } else { + switch (port) { + default: /* to satisfy compiler */ + case 0: + return 0x0000000c40000000ULL; + case 1: + return 0x0000000c80000000ULL; + case 2: + return 0x0000000cc0000000ULL; + } + } +#endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + if (port == 0) + return 0x0000000d00000000ULL; + else + return 0x0000000d20000000ULL; +#endif +} + +/* + * 4xx boards as endpoint and root point setup + * and + * testing inbound and out bound windows + * + * 4xx boards can be plugged into another 4xx boards or you can get PCI-E + * cable which can be used to setup loop back from one port to another port. + * Please rememeber that unless there is a endpoint plugged in to root port it + * will not initialize. It is the same in case of endpoint , unless there is + * root port attached it will not initialize. + * + * In this release of software all the PCI-E ports are configured as either + * endpoint or rootpoint.In future we will have support for selective ports + * setup as endpoint and root point in single board. + * + * Once your board came up as root point , you can verify by reading + * /proc/bus/pci/devices. Where you can see the configuration registers + * of endpoint device attached to the port. + * + * Enpoint cofiguration can be verified by connecting 4xx board to any + * host or another 4xx board. Then try to scan the device. In case of + * linux use "lspci" or appripriate os command. + * + * How do I verify the inbound and out bound windows ? (4xx to 4xx) + * in this configuration inbound and outbound windows are setup to access + * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address + * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, + * This is waere your POM(PLB out bound memory window) mapped. then + * read the data from other 4xx board's u-boot prompt at address + * 0x9000 0000(SRAM). Data should match. + * In case of inbound , write data to u-boot command prompt at 0xb000 0000 + * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check + * data at 0x9000 0000(SRAM).Data should match. + */ +int ppc4xx_init_pcie_port(int port, int rootport) +{ + static int core_init; + volatile u32 val = 0; + int attempts; + u64 addr; + u32 low, high; + + if (!core_init) { + if (ppc4xx_init_pcie()) + return -1; + ++core_init; + } + + /* + * Initialize various parts of the PCI Express core for our port + */ + ppc4xx_init_pcie_port_hw(port, rootport); + + /* + * Notice: the following delay has critical impact on device + * initialization - if too short (<50ms) the link doesn't get up. + */ + mdelay(100); + + val = SDR_READ(SDRN_PESDR_RCSSTS(port)); + if (val & (1 << 20)) { + printf("PCIE%d: PGRST failed %08x\n", port, val); + return -1; + } + + /* + * Verify link is up + */ + val = SDR_READ(SDRN_PESDR_LOOP(port)); + if (!(val & 0x00001000)) { + printf("PCIE%d: link is not up.\n", port); + return -ENODEV; + } + + /* + * Setup UTL registers - but only on revA! + * We use default settings for revB chip. + */ + if (!ppc440spe_revB()) + ppc4xx_setup_utl(port); + + /* + * We map PCI Express configuration access into the 512MB regions + */ + addr = ppc4xx_get_cfgaddr(port); + low = U64_TO_U32_LOW(addr); + high = U64_TO_U32_HIGH(addr); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ + break; + case 1: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ + break; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ + break; +#endif + } + + /* + * Check for VC0 active and assert RDY. + */ + attempts = 10; + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE%d: VC0 not active\n", port); + return -1; + } + mdelay(1000); + } + SDR_WRITE(SDRN_PESDR_RCSSET(port), + SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20); + mdelay(100); + + return 0; +} + +int ppc4xx_init_pcie_rootport(int port) +{ + return ppc4xx_init_pcie_port(port, 1); +} + +int ppc4xx_init_pcie_endport(int port) +{ + return ppc4xx_init_pcie_port(port, 0); +} + +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + volatile void *rmbase = NULL; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch (port) { + case 0: + mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; + break; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; + break; +#endif + } + + /* + * Set bus numbers on our root port + */ + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00000000); + out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH), + in_le32(mbase + PECFG_POM0LAL)); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); + break; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2))); + break; +#endif + } + + /* Set up 4GB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff); + out_le32(mbase + PECFG_BAR0LMPA, 0); + + out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); + out_le32(mbase + PECFG_PIM01SAL, 0x00000000); + out_le32(mbase + PECFG_PIM0LAL, 0); + out_le32(mbase + PECFG_PIM0LAH, 0); + out_le32(mbase + PECFG_PIM1LAL, 0x00000000); + out_le32(mbase + PECFG_PIM1LAH, 0x00000004); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Set Device and Vendor Id */ + out_le16(mbase + 0x200, 0xaaa0 + port); + out_le16(mbase + 0x202, 0xbed0 + port); + + /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ + out_le32(mbase + 0x208, 0x06040001); + + printf("PCIE%d: successfully set as root-complex\n", port); +} + +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + int attempts = 0; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch (port) { + case 0: + mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; + break; +#if defined(CONFIG_SYS_PCIE2_CFGBASE) + case 2: + mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; + break; +#endif + } + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); + out_le32(mbase + PECFG_POM0LAL, 0x00001000); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + break; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + break; +#endif + } + + /* Set up 64MB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + + out_le32(mbase + PECFG_PIM01SAH, 0xffffffff); + out_le32(mbase + PECFG_PIM01SAL, 0xfc000000); + + /* Setup BAR0 */ + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff); + out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64); + + /* Disable BAR1 & BAR2 */ + out_le32(mbase + PECFG_BAR1MPA, 0); + out_le32(mbase + PECFG_BAR2HMPA, 0); + out_le32(mbase + PECFG_BAR2LMPA, 0); + + out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE)); + out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE)); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */ + out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */ + + /* Set Class Code to Processor/PPC */ + out_le32(mbase + 0x208, 0x0b200001); + + attempts = 10; + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE%d: BME not active\n", port); + return -1; + } + mdelay(1000); + } + + printf("PCIE%d: successfully set as endpoint\n", port); + + return 0; +} +#endif /* CONFIG_440SPE && CONFIG_PCI */ diff --git a/cpu/ppc4xx/4xx_uart.c b/arch/ppc/cpu/ppc4xx/4xx_uart.c similarity index 100% rename from cpu/ppc4xx/4xx_uart.c rename to arch/ppc/cpu/ppc4xx/4xx_uart.c diff --git a/arch/ppc/cpu/ppc4xx/Makefile b/arch/ppc/cpu/ppc4xx/Makefile new file mode 100644 index 0000000000..88d53fbb1a --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/Makefile @@ -0,0 +1,92 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START := resetvec.o +START += start.o + +SOBJS := cache.o +SOBJS += dcr.o +SOBJS += kgdb.o + +COBJS := 40x_spd_sdram.o + +COBJS += 44x_spd_ddr.o +COBJS += 44x_spd_ddr2.o +ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION +COBJS += 4xx_ibm_ddr2_autocalib.o +endif +COBJS += 4xx_pci.o +COBJS += 4xx_pcie.o +COBJS += bedbug_405.o +ifdef CONFIG_CMD_CHIP_CONFIG +COBJS += cmd_chip_config.o +endif +COBJS += commproc.o +COBJS += cpu.o +COBJS += cpu_init.o +COBJS += denali_data_eye.o +COBJS += denali_spd_ddr2.o +COBJS += ecc.o +COBJS += fdt.o +COBJS += interrupts.o +COBJS += iop480_uart.o +ifdef CONFIG_CMD_REGINFO +COBJS += reginfo.o +endif +COBJS += sdram.o +COBJS += speed.o +COBJS += tlb.o +COBJS += traps.o +COBJS += usb.o +COBJS += usb_ohci.o +COBJS += usbdev.o +ifndef CONFIG_XILINX_440 +COBJS += 4xx_uart.o +COBJS += gpio.o +COBJS += miiphy.o +COBJS += uic.o +else +COBJS += xilinx_irq.o +endif + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/ppc4xx/bedbug_405.c b/arch/ppc/cpu/ppc4xx/bedbug_405.c similarity index 100% rename from cpu/ppc4xx/bedbug_405.c rename to arch/ppc/cpu/ppc4xx/bedbug_405.c diff --git a/cpu/ppc4xx/cache.S b/arch/ppc/cpu/ppc4xx/cache.S similarity index 100% rename from cpu/ppc4xx/cache.S rename to arch/ppc/cpu/ppc4xx/cache.S diff --git a/cpu/ppc4xx/cmd_chip_config.c b/arch/ppc/cpu/ppc4xx/cmd_chip_config.c similarity index 100% rename from cpu/ppc4xx/cmd_chip_config.c rename to arch/ppc/cpu/ppc4xx/cmd_chip_config.c diff --git a/cpu/ppc4xx/commproc.c b/arch/ppc/cpu/ppc4xx/commproc.c similarity index 100% rename from cpu/ppc4xx/commproc.c rename to arch/ppc/cpu/ppc4xx/commproc.c diff --git a/arch/ppc/cpu/ppc4xx/config.mk b/arch/ppc/cpu/ppc4xx/config.mk new file mode 100644 index 0000000000..ea4d707842 --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float + +cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is440:=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) + +ifneq (,$(findstring CONFIG_440,$(is440))) +PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 +else +PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405 +endif + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/ppc4xx/u-boot.lds diff --git a/cpu/ppc4xx/cpu.c b/arch/ppc/cpu/ppc4xx/cpu.c similarity index 100% rename from cpu/ppc4xx/cpu.c rename to arch/ppc/cpu/ppc4xx/cpu.c diff --git a/arch/ppc/cpu/ppc4xx/cpu_init.c b/arch/ppc/cpu/ppc4xx/cpu_init.c new file mode 100644 index 0000000000..8a6e545c1a --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/cpu_init.c @@ -0,0 +1,456 @@ +/* + * (C) Copyright 2000-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) +DECLARE_GLOBAL_DATA_PTR; +#endif + +#ifndef CONFIG_SYS_PLL_RECONFIG +#define CONFIG_SYS_PLL_RECONFIG 0 +#endif + +void reconfigure_pll(u32 new_cpu_freq) +{ +#if defined(CONFIG_440EPX) + int reset_needed = 0; + u32 reg, temp; + u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */ + fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */ + fbdv, target_fbdv, lfbdv, target_lfbdv, + perdv0, target_perdv0, /* CLK_PERD */ + spcid0, target_spcid0; /* CLK_SPCID */ + + /* Reconfigure clocks if necessary. + * See PPC440EPx User's Manual, sections 8.2 and 14 */ + if (new_cpu_freq == 667) { + target_prbdv0 = 2; + target_fwdva = 2; + target_fwdvb = 4; + target_fbdv = 20; + target_lfbdv = 1; + target_perdv0 = 4; + target_spcid0 = 4; + + mfcpr(CPR0_PRIMBD0, reg); + temp = (reg & PRBDV_MASK) >> 24; + prbdv0 = temp ? temp : 8; + if (prbdv0 != target_prbdv0) { + reg &= ~PRBDV_MASK; + reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); + mtcpr(CPR0_PRIMBD0, reg); + reset_needed = 1; + } + + mfcpr(CPR0_PLLD, reg); + + temp = (reg & PLLD_FWDVA_MASK) >> 16; + fwdva = temp ? temp : 16; + + temp = (reg & PLLD_FWDVB_MASK) >> 8; + fwdvb = temp ? temp : 8; + + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + + if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) { + reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | + PLLD_FBDV_MASK | PLLD_LFBDV_MASK); + reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) | + ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | + ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | + (target_lfbdv == 64 ? 0 : target_lfbdv); + mtcpr(CPR0_PLLD, reg); + reset_needed = 1; + } + + mfcpr(CPR0_PERD, reg); + perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; + if (perdv0 != target_perdv0) { + reg &= ~CPR0_PERD_PERDV0_MASK; + reg |= (target_perdv0 << 24); + mtcpr(CPR0_PERD, reg); + reset_needed = 1; + } + + mfcpr(CPR0_SPCID, reg); + temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; + spcid0 = temp ? temp : 4; + if (spcid0 != target_spcid0) { + reg &= ~CPR0_SPCID_SPCIDV0_MASK; + reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); + mtcpr(CPR0_SPCID, reg); + reset_needed = 1; + } + } + + /* Get current value of FWDVA.*/ + mfcpr(CPR0_PLLD, reg); + temp = (reg & PLLD_FWDVA_MASK) >> 16; + + /* + * Check to see if FWDVA has been set to value of 1. if it has we must + * modify it. + */ + if (temp == 1) { + mfcpr(CPR0_PLLD, reg); + /* Get current value of fbdv. */ + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + /* Get current value of lfbdv. */ + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + /* + * Load register that contains current boot strapping option. + */ + mfcpr(CPR0_ICFG, reg); + /* Shift strapping option into low 3 bits.*/ + reg = (reg >> 28); + + if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || + (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { + /* + * Get current value of FWDVA. Assign current FWDVA to + * new FWDVB. + */ + mfcpr(CPR0_PLLD, reg); + target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; + fwdvb = target_fwdvb ? target_fwdvb : 8; + /* + * Get current value of FWDVB. Assign current FWDVB to + * new FWDVA. + */ + target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; + fwdva = target_fwdva ? target_fwdva : 16; + /* + * Update CPR0_PLLD with switched FWDVA and FWDVB. + */ + reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | + PLLD_FBDV_MASK | PLLD_LFBDV_MASK); + reg |= ((fwdva == 16 ? 0 : fwdva) << 16) | + ((fwdvb == 8 ? 0 : fwdvb) << 8) | + ((fbdv == 32 ? 0 : fbdv) << 24) | + (lfbdv == 64 ? 0 : lfbdv); + mtcpr(CPR0_PLLD, reg); + /* Acknowledge that a reset is required. */ + reset_needed = 1; + } + } + + if (reset_needed) { + /* + * Set reload inhibit so configuration will persist across + * processor resets + */ + mfcpr(CPR0_ICFG, reg); + reg &= ~CPR0_ICFG_RLI_MASK; + reg |= 1 << 31; + mtcpr(CPR0_ICFG, reg); + + /* Reset processor if configuration changed */ + __asm__ __volatile__ ("sync; isync"); + mtspr(SPRN_DBCR0, 0x20000000); + } +#endif +} + +/* + * Breath some life into the CPU... + * + * Reconfigure PLL if necessary, + * set up the memory map, + * initialize a bunch of registers + */ +void +cpu_init_f (void) +{ +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) + u32 val; +#endif + + reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); + +#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) + /* + * GPIO0 setup (select GPIO or alternate function) + */ +#if defined(CONFIG_SYS_GPIO0_OR) + out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */ +#endif +#if defined(CONFIG_SYS_GPIO0_ODR) + out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */ +#endif + out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ + out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); + out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ + out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); + out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); +#if defined(CONFIG_SYS_GPIO0_ISR2H) + out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H); + out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L); +#endif +#if defined (CONFIG_SYS_GPIO0_TCR) + out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ +#endif +#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */ + +#if defined (CONFIG_405EP) + /* + * Set EMAC noise filter bits + */ + mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); +#endif /* CONFIG_405EP */ + +#if defined(CONFIG_SYS_4xx_GPIO_TABLE) + gpio_set_chip_configuration(); +#endif /* CONFIG_SYS_4xx_GPIO_TABLE */ + + /* + * External Bus Controller (EBC) Setup + */ +#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) +#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || defined(CONFIG_405)) + /* + * Move the next instructions into icache, since these modify the flash + * we are running from! + */ + asm volatile(" bl 0f" ::: "lr"); + asm volatile("0: mflr 3" ::: "r3"); + asm volatile(" addi 4, 0, 14" ::: "r4"); + asm volatile(" mtctr 4" ::: "ctr"); + asm volatile("1: icbt 0, 3"); + asm volatile(" addi 3, 3, 32" ::: "r3"); + asm volatile(" bdnz 1b" ::: "ctr", "cr0"); + asm volatile(" addis 3, 0, 0x0" ::: "r3"); + asm volatile(" ori 3, 3, 0xA000" ::: "r3"); + asm volatile(" mtctr 3" ::: "ctr"); + asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); +#endif + + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); +#endif + +#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) + mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP); + mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR); +#endif + +#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) + mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP); + mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR); +#endif + +#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) + mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); + mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); +#endif + +#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) + mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP); + mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR); +#endif + +#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) + mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP); + mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR); +#endif + +#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) + mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP); + mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR); +#endif + +#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) + mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP); + mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR); +#endif + +#if defined (CONFIG_SYS_EBC_CFG) + mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG); +#endif + +#if defined(CONFIG_WATCHDOG) + val = mfspr(tcr); +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + val |= 0xb8000000; /* generate system reset after 1.34 seconds */ +#elif defined(CONFIG_440EPX) + val |= 0xb0000000; /* generate system reset after 1.34 seconds */ +#else + val |= 0xf0000000; /* generate system reset after 2.684 seconds */ +#endif +#if defined(CONFIG_SYS_4xx_RESET_TYPE) + val &= ~0x30000000; /* clear WRC bits */ + val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */ +#endif + mtspr(tcr, val); + + val = mfspr(tsr); + val |= 0x80000000; /* enable watchdog timer */ + mtspr(tsr, val); + + reset_4xx_watchdog(); +#endif /* CONFIG_WATCHDOG */ + +#if defined(CONFIG_440GX) + /* Take the GX out of compatibility mode + * Travis Sawyer, 9 Mar 2004 + * NOTE: 440gx user manual inconsistency here + * Compatibility mode and Ethernet Clock select are not + * correct in the manual + */ + mfsdr(SDR0_MFR, val); + val &= ~0x10000000; + mtsdr(SDR0_MFR,val); +#endif /* CONFIG_440GX */ + +#if defined(CONFIG_460EX) + /* + * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and + * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata + * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA + */ + mfsdr(SDR0_AHB_CFG, val); + val |= 0x80; + val &= ~0x40; + mtsdr(SDR0_AHB_CFG, val); + mfsdr(SDR0_USB2HOST_CFG, val); + val &= ~0xf00; + val |= 0x400; + mtsdr(SDR0_USB2HOST_CFG, val); +#endif /* CONFIG_460EX */ + +#if defined(CONFIG_405EX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + /* + * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read + */ + mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) | + PLB0_ACR_RDP_4DEEP); + mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) | + PLB1_ACR_RDP_4DEEP); +#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ +} + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r (void) +{ +#if defined(CONFIG_405GP) + uint pvr = get_pvr(); + + /* + * Set edge conditioning circuitry on PPC405GPr + * for compatibility to existing PPC405GP designs. + */ + if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { + mtdcr(CPC0_ECR, 0x60606000); + } +#endif /* defined(CONFIG_405GP) */ + + return 0; +} + +#if defined(CONFIG_PCI) && \ + (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX)) +/* + * 440EP(x)/GR(x) PCI async/sync clocking restriction: + * + * In asynchronous PCI mode, the synchronous PCI clock must meet + * certain requirements. The following equation describes the + * relationship that must be maintained between the asynchronous PCI + * clock and synchronous PCI clock. Select an appropriate PCI:PLB + * ratio to maintain the relationship: + * + * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz + */ +static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async) +{ + if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000))) + return 0; + else + return 1; +} + +int ppc4xx_pci_sync_clock_config(u32 async) +{ + sys_info_t sys_info; + u32 sync; + int div; + u32 reg; + u32 spcid_val[] = { + CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2, + CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 }; + + get_sys_info(&sys_info); + sync = sys_info.freqPCI; + + /* + * First check if the equation above is met + */ + if (!ppc4xx_pci_sync_clock_ok(sync, async)) { + /* + * Reconfigure PCI sync clock to meet the equation. + * Start with highest possible PCI sync frequency + * (divider 1). + */ + for (div = 1; div <= 4; div++) { + sync = sys_info.freqPLB / div; + if (ppc4xx_pci_sync_clock_ok(sync, async)) + break; + } + + if (div <= 4) { + mtcpr(CPR0_SPCID, spcid_val[div]); + + mfcpr(CPR0_ICFG, reg); + reg |= CPR0_ICFG_RLI_MASK; + mtcpr(CPR0_ICFG, reg); + + /* do chip reset */ + mtspr(SPRN_DBCR0, 0x20000000); + } else { + /* Impossible to configure the PCI sync clock */ + return -1; + } + } + + return 0; +} +#endif diff --git a/cpu/ppc4xx/dcr.S b/arch/ppc/cpu/ppc4xx/dcr.S similarity index 100% rename from cpu/ppc4xx/dcr.S rename to arch/ppc/cpu/ppc4xx/dcr.S diff --git a/arch/ppc/cpu/ppc4xx/denali_data_eye.c b/arch/ppc/cpu/ppc4xx/denali_data_eye.c new file mode 100644 index 0000000000..15a9b4f3ec --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/denali_data_eye.c @@ -0,0 +1,389 @@ +/* + * arch/ppc/cpu/ppc4xx/denali_data_eye.c + * Extracted from board/amcc/sequoia/sdram.c by Larry Johnson . + * + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +/*-----------------------------------------------------------------------------+ + * denali_wait_for_dlllock. + +----------------------------------------------------------------------------*/ +int denali_wait_for_dlllock(void) +{ + u32 val; + int wait; + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + for (wait = 0; wait != 0xffff; ++wait) { + mfsdram(DDR0_17, val); + if (DDR0_17_DLLLOCKREG_DECODE(val)) { + /* dlllockreg bit on */ + return 0; + } + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + return -1; +} + +#if defined(CONFIG_DDR_DATA_EYE) +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +/*-----------------------------------------------------------------------------+ + * wait_for_dram_init_complete. + +----------------------------------------------------------------------------*/ +static int wait_for_dram_init_complete(void) +{ + unsigned long val; + int wait = 0; + + /* --------------------------------------------------------------+ + * Wait for 'DRAM initialization complete' bit in status register + * -------------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_00); + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) + /* 'DRAM initialization complete' bit */ + return 0; + else + wait++; + } + debug("DRAM initialization complete bit in status register did not " + "rise\n"); + return -1; +} + +#define NUM_TRIES 64 +#define NUM_READS 10 + +/*-----------------------------------------------------------------------------+ + * denali_core_search_data_eye. + +----------------------------------------------------------------------------*/ +void denali_core_search_data_eye(void) +{ + int k, j; + u32 val; + u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; + u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; + u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; + u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; + volatile u32 *ram_pointer; + u32 test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 + }; + + ram_pointer = (volatile u32 *)(CONFIG_SYS_SDRAM_BASE); + + for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { + /* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */ + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | + DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + + passing_cases = 0; + + for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; + dll_dqs_delay_X++) { + /* for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; + dll_dqs_delay_X++) { */ + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* clear any ECC errors */ + mtdcr(ddrcfga, DDR0_00); + mtdcr(ddrcfgd, + mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (denali_wait_for_dlllock() != 0) { + printf("dll lock did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = " + "%d\n", wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + sync(); + eieio(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur!!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = " + "%d\n", wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ + + /* write values */ + for (j = 0; j < NUM_TRIES; j++) { + ram_pointer[j] = test[j]; + + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r"(&ram_pointer[j])); + } + + /* read values back */ + for (j = 0; j < NUM_TRIES; j++) { + for (k = 0; k < NUM_READS; k++) { + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r"(&ram_pointer + [j])); + + if (ram_pointer[j] != test[j]) + break; + } + + /* read error */ + if (k != NUM_READS) + break; + } + + /* See if the dll_dqs_delay_X value passed. */ + mtdcr(ddrcfga, DDR0_00); + if (j < NUM_TRIES + || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & + 0x3F)) { + /* Failed */ + passing_cases = 0; + /* break; */ + } else { + /* Passed */ + if (passing_cases == 0) + dll_dqs_delay_X_sw_val = + dll_dqs_delay_X; + passing_cases++; + if (passing_cases >= max_passing_cases) { + max_passing_cases = passing_cases; + wr_dqs_shift_with_max_passing_cases = + wr_dqs_shift; + dll_dqs_delay_X_start_window = + dll_dqs_delay_X_sw_val; + dll_dqs_delay_X_end_window = + dll_dqs_delay_X; + } + } + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | + DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ + } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ + + /* -----------------------------------------------------------+ + * Largest passing window is now detected. + * ----------------------------------------------------------*/ + + /* Compute dll_dqs_delay_X value */ + dll_dqs_delay_X = (dll_dqs_delay_X_end_window + + dll_dqs_delay_X_start_window) / 2; + wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; + + debug("DQS calibration - Window detected:\n"); + debug("max_passing_cases = %d\n", max_passing_cases); + debug("wr_dqs_shift = %d\n", wr_dqs_shift); + debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); + debug("dll_dqs_delay_X window = %d - %d\n", + dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_09=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_22=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_17=0x%08lx\n", val); + + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_18=0x%08lx\n", val); + + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_19=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + sync(); + eieio(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (denali_wait_for_dlllock() != 0) { + printf("dll lock did not occur !!!\n"); + hang(); + } + sync(); + eieio(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ +} +#endif /* defined(CONFIG_DDR_DATA_EYE) */ +#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ diff --git a/arch/ppc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/ppc/cpu/ppc4xx/denali_spd_ddr2.c new file mode 100644 index 0000000000..72f76cd2fa --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/denali_spd_ddr2.c @@ -0,0 +1,1256 @@ +/* + * arch/ppc/cpu/ppc4xx/denali_spd_ddr2.c + * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core + * DDR2 controller, specifically the 440EPx/GRx. + * + * (C) Copyright 2007-2008 + * Larry Johnson, lrj@acm.org. + * + * Based primarily on arch/ppc/cpu/ppc4xx/4xx_spd_ddr2.c, which is... + * + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * COPYRIGHT AMCC CORPORATION 2004 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPD_EEPROM) && \ + (defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) + +/*-----------------------------------------------------------------------------+ + * Defines + *-----------------------------------------------------------------------------*/ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define MAXDIMMS 2 +#define MAXRANKS 2 + +#define ONE_BILLION 1000000000 + +#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) + +#define DLL_DQS_DELAY 0x19 +#define DLL_DQS_BYPASS 0x0B +#define DQS_OUT_SHIFT 0x7F + +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory + * region. Right now the cache should still be disabled in U-Boot because of the + * EMAC driver, that need it's buffer descriptor to be located in non cached + * memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CONFIG_4xx_DCACHE in the board config file and this code should setup + * everything correctly. + */ +#if defined(CONFIG_4xx_DCACHE) +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#endif + +/*-----------------------------------------------------------------------------+ + * Prototypes + *-----------------------------------------------------------------------------*/ +extern int denali_wait_for_dlllock(void); +extern void denali_core_search_data_eye(void); +extern void dcbz_area(u32 start_address, u32 num_bytes); + +/* + * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed + */ +void __spd_ddr_init_hang(void) +{ + hang(); +} +void spd_ddr_init_hang(void) + __attribute__ ((weak, alias("__spd_ddr_init_hang"))); + +#if defined(DEBUG) +static void print_mcsr(void) +{ + printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR)); +} + +static void denali_sdram_register_dump(void) +{ + unsigned int sdram_data; + + printf("\n Register Dump:\n"); + mfsdram(DDR0_00, sdram_data); + printf(" DDR0_00 = 0x%08X", sdram_data); + mfsdram(DDR0_01, sdram_data); + printf(" DDR0_01 = 0x%08X\n", sdram_data); + mfsdram(DDR0_02, sdram_data); + printf(" DDR0_02 = 0x%08X", sdram_data); + mfsdram(DDR0_03, sdram_data); + printf(" DDR0_03 = 0x%08X\n", sdram_data); + mfsdram(DDR0_04, sdram_data); + printf(" DDR0_04 = 0x%08X", sdram_data); + mfsdram(DDR0_05, sdram_data); + printf(" DDR0_05 = 0x%08X\n", sdram_data); + mfsdram(DDR0_06, sdram_data); + printf(" DDR0_06 = 0x%08X", sdram_data); + mfsdram(DDR0_07, sdram_data); + printf(" DDR0_07 = 0x%08X\n", sdram_data); + mfsdram(DDR0_08, sdram_data); + printf(" DDR0_08 = 0x%08X", sdram_data); + mfsdram(DDR0_09, sdram_data); + printf(" DDR0_09 = 0x%08X\n", sdram_data); + mfsdram(DDR0_10, sdram_data); + printf(" DDR0_10 = 0x%08X", sdram_data); + mfsdram(DDR0_11, sdram_data); + printf(" DDR0_11 = 0x%08X\n", sdram_data); + mfsdram(DDR0_12, sdram_data); + printf(" DDR0_12 = 0x%08X", sdram_data); + mfsdram(DDR0_14, sdram_data); + printf(" DDR0_14 = 0x%08X\n", sdram_data); + mfsdram(DDR0_17, sdram_data); + printf(" DDR0_17 = 0x%08X", sdram_data); + mfsdram(DDR0_18, sdram_data); + printf(" DDR0_18 = 0x%08X\n", sdram_data); + mfsdram(DDR0_19, sdram_data); + printf(" DDR0_19 = 0x%08X", sdram_data); + mfsdram(DDR0_20, sdram_data); + printf(" DDR0_20 = 0x%08X\n", sdram_data); + mfsdram(DDR0_21, sdram_data); + printf(" DDR0_21 = 0x%08X", sdram_data); + mfsdram(DDR0_22, sdram_data); + printf(" DDR0_22 = 0x%08X\n", sdram_data); + mfsdram(DDR0_23, sdram_data); + printf(" DDR0_23 = 0x%08X", sdram_data); + mfsdram(DDR0_24, sdram_data); + printf(" DDR0_24 = 0x%08X\n", sdram_data); + mfsdram(DDR0_25, sdram_data); + printf(" DDR0_25 = 0x%08X", sdram_data); + mfsdram(DDR0_26, sdram_data); + printf(" DDR0_26 = 0x%08X\n", sdram_data); + mfsdram(DDR0_27, sdram_data); + printf(" DDR0_27 = 0x%08X", sdram_data); + mfsdram(DDR0_28, sdram_data); + printf(" DDR0_28 = 0x%08X\n", sdram_data); + mfsdram(DDR0_31, sdram_data); + printf(" DDR0_31 = 0x%08X", sdram_data); + mfsdram(DDR0_32, sdram_data); + printf(" DDR0_32 = 0x%08X\n", sdram_data); + mfsdram(DDR0_33, sdram_data); + printf(" DDR0_33 = 0x%08X", sdram_data); + mfsdram(DDR0_34, sdram_data); + printf(" DDR0_34 = 0x%08X\n", sdram_data); + mfsdram(DDR0_35, sdram_data); + printf(" DDR0_35 = 0x%08X", sdram_data); + mfsdram(DDR0_36, sdram_data); + printf(" DDR0_36 = 0x%08X\n", sdram_data); + mfsdram(DDR0_37, sdram_data); + printf(" DDR0_37 = 0x%08X", sdram_data); + mfsdram(DDR0_38, sdram_data); + printf(" DDR0_38 = 0x%08X\n", sdram_data); + mfsdram(DDR0_39, sdram_data); + printf(" DDR0_39 = 0x%08X", sdram_data); + mfsdram(DDR0_40, sdram_data); + printf(" DDR0_40 = 0x%08X\n", sdram_data); + mfsdram(DDR0_41, sdram_data); + printf(" DDR0_41 = 0x%08X", sdram_data); + mfsdram(DDR0_42, sdram_data); + printf(" DDR0_42 = 0x%08X\n", sdram_data); + mfsdram(DDR0_43, sdram_data); + printf(" DDR0_43 = 0x%08X", sdram_data); + mfsdram(DDR0_44, sdram_data); + printf(" DDR0_44 = 0x%08X\n", sdram_data); +} +#else +static inline void denali_sdram_register_dump(void) +{ +} + +inline static void print_mcsr(void) +{ +} +#endif /* defined(DEBUG) */ + +static int is_ecc_enabled(void) +{ + u32 val; + + mfsdram(DDR0_22, val); + return 0x3 == DDR0_22_CTRL_RAW_DECODE(val); +} + +static unsigned char spd_read(u8 chip, unsigned int addr) +{ + u8 data[2]; + + if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) { + debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr); + return 0; + } + debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n", + chip, addr, data[0]); + return data[0]; +} + +static unsigned long get_tcyc(unsigned char reg) +{ + /* + * Byte 9, et al: Cycle time for CAS Latency=X, is split into two + * nibbles: the higher order nibble (bits 4-7) designates the cycle time + * to a granularity of 1ns; the value presented by the lower order + * nibble (bits 0-3) has a granularity of .1ns and is added to the value + * designated by the higher nibble. In addition, four lines of the lower + * order nibble are assigned to support +.25, +.33, +.66, and +.75. + */ + + unsigned char subfield_b = reg & 0x0F; + + switch (subfield_b & 0x0F) { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + case 0x8: + case 0x9: + return 1000 * (reg >> 4) + 100 * subfield_b; + case 0xA: + return 1000 * (reg >> 4) + 250; + case 0xB: + return 1000 * (reg >> 4) + 333; + case 0xC: + return 1000 * (reg >> 4) + 667; + case 0xD: + return 1000 * (reg >> 4) + 750; + } + return 0; +} + +/*------------------------------------------------------------------ + * Find the installed DIMMs, make sure that the are DDR2, and fill + * in the dimm_ranks array. Then dimm_ranks[dimm_num] > 0 iff the + * DIMM and dimm_num is present. + * Note: Because there are only two chip-select lines, it is assumed + * that a board with a single socket can support two ranks on that + * socket, while a board with two sockets can support only one rank + * on each socket. + *-----------------------------------------------------------------*/ +static void get_spd_info(unsigned long dimm_ranks[], + unsigned long *ranks, + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_found = FALSE; + unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1; + unsigned char num_of_bytes; + unsigned char total_size; + + *ranks = 0; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + num_of_bytes = 0; + total_size = 0; + + num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); + total_size = spd_read(iic0_dimm_addr[dimm_num], 1); + if ((num_of_bytes != 0) && (total_size != 0)) { + unsigned char const dimm_type = + spd_read(iic0_dimm_addr[dimm_num], 2); + + unsigned long ranks_on_dimm = + (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1; + + if (8 != dimm_type) { + switch (dimm_type) { + case 1: + printf("ERROR: Standard Fast Page Mode " + "DRAM DIMM"); + break; + case 2: + printf("ERROR: EDO DIMM"); + break; + case 3: + printf("ERROR: Pipelined Nibble DIMM"); + break; + case 4: + printf("ERROR: SDRAM DIMM"); + break; + case 5: + printf("ERROR: Multiplexed ROM DIMM"); + break; + case 6: + printf("ERROR: SGRAM DIMM"); + break; + case 7: + printf("ERROR: DDR1 DIMM"); + break; + default: + printf("ERROR: Unknown DIMM (type %d)", + (unsigned int)dimm_type); + break; + } + printf(" detected in slot %lu.\n", dimm_num); + printf("Only DDR2 SDRAM DIMMs are supported." + "\n"); + printf("Replace the module with a DDR2 DIMM." + "\n\n"); + spd_ddr_init_hang(); + } + dimm_found = TRUE; + debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM" + "\n", dimm_num, ranks_on_dimm); + if (ranks_on_dimm > max_ranks_per_dimm) { + printf("WARNING: DRAM DIMM in slot %lu has %lu " + "ranks.\n", dimm_num, ranks_on_dimm); + if (1 == max_ranks_per_dimm) { + printf("Only one rank will be used.\n"); + } else { + printf + ("Only two ranks will be used.\n"); + } + ranks_on_dimm = max_ranks_per_dimm; + } + dimm_ranks[dimm_num] = ranks_on_dimm; + *ranks += ranks_on_dimm; + } else { + dimm_ranks[dimm_num] = 0; + debug("DIMM slot %lu: Not populated\n", dimm_num); + } + } + if (dimm_found == FALSE) { + printf("ERROR: No memory installed.\n"); + printf("Install at least one DDR2 DIMM.\n\n"); + spd_ddr_init_hang(); + } + debug("Total number of ranks = %d\n", *ranks); +} + +/*------------------------------------------------------------------ + * For the memory DIMMs installed, this routine verifies that + * frequency previously calculated is supported. + *-----------------------------------------------------------------*/ +static void check_frequency(unsigned long *dimm_ranks, + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long cycle_time; + unsigned long calc_cycle_time; + + /* + * calc_cycle_time is calculated from DDR frequency set by board/chip + * and is expressed in picoseconds to match the way DIMM cycle time is + * calculated below. + */ + calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq); + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + cycle_time = + get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9)); + debug("cycle_time=%d ps\n", cycle_time); + + if (cycle_time > (calc_cycle_time + 10)) { + /* + * the provided sdram cycle_time is too small + * for the available DIMM cycle_time. The + * additionnal 10ps is here to accept a small + * incertainty. + */ + printf + ("ERROR: DRAM DIMM detected with cycle_time %d ps in " + "slot %d \n while calculated cycle time is %d ps.\n", + (unsigned int)cycle_time, + (unsigned int)dimm_num, + (unsigned int)calc_cycle_time); + printf + ("Replace the DIMM, or change DDR frequency via " + "strapping bits.\n\n"); + spd_ddr_init_hang(); + } + } + } +} + +/*------------------------------------------------------------------ + * This routine gets size information for the installed memory + * DIMMs. + *-----------------------------------------------------------------*/ +static void get_dimm_size(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long *const rows, + unsigned long *const banks, + unsigned long *const cols, unsigned long *const width) +{ + unsigned long dimm_num; + + *rows = 0; + *banks = 0; + *cols = 0; + *width = 0; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + unsigned long t; + + /* Rows */ + t = spd_read(iic0_dimm_addr[dimm_num], 3); + if (0 == *rows) { + *rows = t; + } else if (t != *rows) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of rows.\n\n"); + spd_ddr_init_hang(); + } + /* Banks */ + t = spd_read(iic0_dimm_addr[dimm_num], 17); + if (0 == *banks) { + *banks = t; + } else if (t != *banks) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of banks.\n\n"); + spd_ddr_init_hang(); + } + /* Columns */ + t = spd_read(iic0_dimm_addr[dimm_num], 4); + if (0 == *cols) { + *cols = t; + } else if (t != *cols) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same number of columns.\n\n"); + spd_ddr_init_hang(); + } + /* Data width */ + t = spd_read(iic0_dimm_addr[dimm_num], 6); + if (0 == *width) { + *width = t; + } else if (t != *width) { + printf("ERROR: DRAM DIMM modules do not all " + "have the same data width.\n\n"); + spd_ddr_init_hang(); + } + } + } + debug("Number of rows = %d\n", *rows); + debug("Number of columns = %d\n", *cols); + debug("Number of banks = %d\n", *banks); + debug("Data width = %d\n", *width); + if (*rows > 14) { + printf("ERROR: DRAM DIMM modules have %lu address rows.\n", + *rows); + printf("Only modules with 14 or fewer rows are supported.\n\n"); + spd_ddr_init_hang(); + } + if (4 != *banks && 8 != *banks) { + printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks); + printf("Only modules with 4 or 8 banks are supported.\n\n"); + spd_ddr_init_hang(); + } + if (*cols > 12) { + printf("ERROR: DRAM DIMM modules have %lu address columns.\n", + *cols); + printf("Only modules with 12 or fewer columns are " + "supported.\n\n"); + spd_ddr_init_hang(); + } + if (32 != *width && 40 != *width && 64 != *width && 72 != *width) { + printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n", + *width); + printf("Only modules with widths of 32, 40, 64, and 72 bits " + "are supported.\n\n"); + spd_ddr_init_hang(); + } +} + +/*------------------------------------------------------------------ + * Only 1.8V modules are supported. This routine verifies this. + *-----------------------------------------------------------------*/ +static void check_voltage_type(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long voltage_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_ranks[dimm_num]) { + voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); + if (0x05 != voltage_type) { /* 1.8V for DDR2 */ + printf("ERROR: Slot %lu provides 1.8V for DDR2 " + "DIMMs.\n", dimm_num); + switch (voltage_type) { + case 0x00: + printf("This DIMM is 5.0 Volt/TTL.\n"); + break; + case 0x01: + printf("This DIMM is LVTTL.\n"); + break; + case 0x02: + printf("This DIMM is 1.5 Volt.\n"); + break; + case 0x03: + printf("This DIMM is 3.3 Volt/TTL.\n"); + break; + case 0x04: + printf("This DIMM is 2.5 Volt.\n"); + break; + default: + printf("This DIMM is an unknown " + "voltage.\n"); + break; + } + printf("Replace it with a 1.8V DDR2 DIMM.\n\n"); + spd_ddr_init_hang(); + } + } + } +} + +static void program_ddr0_03(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq, + unsigned long rows, unsigned long *cas_latency) +{ + unsigned long dimm_num; + unsigned long cas_index; + unsigned long cycle_2_0_clk; + unsigned long cycle_3_0_clk; + unsigned long cycle_4_0_clk; + unsigned long cycle_5_0_clk; + unsigned long max_2_0_tcyc_ps = 100; + unsigned long max_3_0_tcyc_ps = 100; + unsigned long max_4_0_tcyc_ps = 100; + unsigned long max_5_0_tcyc_ps = 100; + unsigned char cas_available = 0x3C; /* value for DDR2 */ + u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2); + unsigned int const tcyc_addr[3] = { 9, 23, 25 }; + + /*------------------------------------------------------------------ + * Get the board configuration info. + *-----------------------------------------------------------------*/ + debug("sdram_freq = %d\n", sdram_freq); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned char const cas_bit = + spd_read(iic0_dimm_addr[dimm_num], 18); + unsigned char cas_mask; + + cas_available &= cas_bit; + for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) { + if (cas_bit & cas_mask) + break; + } + debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n", + cas_bit, cas_mask); + + for (cas_index = 0; cas_index < 3; + cas_mask >>= 1, cas_index++) { + unsigned long cycle_time_ps; + + if (!(cas_available & cas_mask)) { + continue; + } + cycle_time_ps = + get_tcyc(spd_read(iic0_dimm_addr[dimm_num], + tcyc_addr[cas_index])); + + debug("cas_index = %d: cycle_time_ps = %d\n", + cas_index, cycle_time_ps); + /* + * DDR2 devices use the following bitmask for CAS latency: + * Bit 7 6 5 4 3 2 1 0 + * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD + */ + switch (cas_mask) { + case 0x20: + max_5_0_tcyc_ps = + max(max_5_0_tcyc_ps, cycle_time_ps); + break; + case 0x10: + max_4_0_tcyc_ps = + max(max_4_0_tcyc_ps, cycle_time_ps); + break; + case 0x08: + max_3_0_tcyc_ps = + max(max_3_0_tcyc_ps, cycle_time_ps); + break; + case 0x04: + max_2_0_tcyc_ps = + max(max_2_0_tcyc_ps, cycle_time_ps); + break; + } + } + } + } + debug("cas_available (bit map) = 0x%02X\n", cas_available); + + /*------------------------------------------------------------------ + * Set the SDRAM mode, SDRAM_MMODE + *-----------------------------------------------------------------*/ + + /* add 10 here because of rounding problems */ + cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10; + cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10; + cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10; + cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10; + debug("cycle_2_0_clk = %d\n", cycle_2_0_clk); + debug("cycle_3_0_clk = %d\n", cycle_3_0_clk); + debug("cycle_4_0_clk = %d\n", cycle_4_0_clk); + debug("cycle_5_0_clk = %d\n", cycle_5_0_clk); + + if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) { + *cas_latency = 2; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) | + DDR0_03_CASLAT_LIN_ENCODE(0x4); + } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) { + *cas_latency = 3; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) | + DDR0_03_CASLAT_LIN_ENCODE(0x6); + } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) { + *cas_latency = 4; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) | + DDR0_03_CASLAT_LIN_ENCODE(0x8); + } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) { + *cas_latency = 5; + ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) | + DDR0_03_CASLAT_LIN_ENCODE(0xA); + } else { + printf("ERROR: Cannot find a supported CAS latency with the " + "installed DIMMs.\n"); + printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, " + "and 5.0 are supported.\n"); + printf("Make sure the PLB speed is within the supported range " + "of the DIMMs.\n"); + printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld " + "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk, + cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); + spd_ddr_init_hang(); + } + debug("CAS latency = %d\n", *cas_latency); + mtsdram(DDR0_03, ddr0_03); +} + +static void program_ddr0_04(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rc_ps = 0; + unsigned long t_rrd_ps = 0; + unsigned long t_rtp_ps = 0; + unsigned long t_rc_clk; + unsigned long t_rrd_clk; + unsigned long t_rtp_clk; + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tRC */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41); + switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) { + case 0x1: + ps += 250; + break; + case 0x2: + ps += 333; + break; + case 0x3: + ps += 500; + break; + case 0x4: + ps += 667; + break; + case 0x5: + ps += 750; + break; + } + t_rc_ps = max(t_rc_ps, ps); + /* tRRD */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28); + t_rrd_ps = max(t_rrd_ps, ps); + /* tRTP */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38); + t_rtp_ps = max(t_rtp_ps, ps); + } + } + debug("t_rc_ps = %d\n", t_rc_ps); + t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000; + debug("t_rrd_ps = %d\n", t_rrd_ps); + t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000; + debug("t_rtp_ps = %d\n", t_rtp_ps); + t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) | + DDR0_04_TRRD_ENCODE(t_rrd_clk) | + DDR0_04_TRTP_ENCODE(t_rtp_clk)); +} + +static void program_ddr0_05(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rp_ps = 0; + unsigned long t_ras_ps = 0; + unsigned long t_rp_clk; + unsigned long t_ras_clk; + u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tRP */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27); + t_rp_ps = max(t_rp_ps, ps); + /* tRAS */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30); + t_ras_ps = max(t_ras_ps, ps); + } + } + debug("t_rp_ps = %d\n", t_rp_ps); + t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000; + debug("t_ras_ps = %d\n", t_ras_ps); + t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) | + DDR0_05_TRAS_MIN_ENCODE(t_ras_clk)); +} + +static void program_ddr0_06(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned char spd_40; + unsigned long t_wtr_ps = 0; + unsigned long t_rfc_ps = 0; + unsigned long t_wtr_clk; + unsigned long t_rfc_clk; + u32 ddr0_06 = + DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + /* tWTR */ + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37); + t_wtr_ps = max(t_wtr_ps, ps); + /* tRFC */ + ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42); + spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40); + ps += 256000 * (spd_40 & 0x01); + switch ((spd_40 & 0x0E) >> 1) { + case 0x1: + ps += 250; + break; + case 0x2: + ps += 333; + break; + case 0x3: + ps += 500; + break; + case 0x4: + ps += 667; + break; + case 0x5: + ps += 750; + break; + } + t_rfc_ps = max(t_rfc_ps, ps); + } + } + debug("t_wtr_ps = %d\n", t_wtr_ps); + t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000; + debug("t_rfc_ps = %d\n", t_rfc_ps); + t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) | + DDR0_06_TRFC_ENCODE(t_rfc_clk)); +} + +static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks) +{ + unsigned long csmap; + + if (2 == ranks) { + /* Both chip selects in use */ + csmap = 0x03; + } else { + /* One chip select in use */ + csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2; + } + mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) | + DDR0_10_CS_MAP_ENCODE(csmap) | + DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0)); +} + +static void program_ddr0_11(unsigned long sdram_freq) +{ + unsigned long const t_xsnr_ps = 200000; /* 200 ns */ + unsigned long t_xsnr_clk; + + debug("t_xsnr_ps = %d\n", t_xsnr_ps); + t_xsnr_clk = + (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) | + DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200)); +} + +static void program_ddr0_22(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, unsigned long width) +{ +#if defined(CONFIG_DDR_ECC) + unsigned long dimm_num; + unsigned long ecc_available = width >= 64; + u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | + DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS); + + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + /* Check for ECC */ + if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) & + 0x02)) { + ecc_available = FALSE; + } + } + } + if (ecc_available) { + debug("ECC found on all DIMMs present\n"); + mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3)); + } else { + debug("ECC not found on some or all DIMMs present\n"); + mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0)); + } +#else + mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) | + DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | + DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | + DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS)); +#endif /* defined(CONFIG_DDR_ECC) */ +} + +static void program_ddr0_24(unsigned long ranks) +{ + u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */ + DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0); + + if (2 == ranks) { + /* Both chip selects in use */ + ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) | + DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2); + } else { + /* One chip select in use */ + /* One of the two fields added to ddr0_24 is a "don't care" */ + ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) | + DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1); + } + mtsdram(DDR0_24, ddr0_24); +} + +static void program_ddr0_26(unsigned long sdram_freq) +{ + unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */ + /* TODO: check definition of tRAS_MAX */ + unsigned long const t_ras_max_ps = 9 * t_ref_ps; + unsigned long t_ras_max_clk; + unsigned long t_ref_clk; + + /* Round down t_ras_max_clk and t_ref_clk */ + debug("t_ras_max_ps = %d\n", t_ras_max_ps); + t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000; + debug("t_ref_ps = %d\n", t_ref_ps); + t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000; + mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) | + DDR0_26_TREF_ENCODE(t_ref_clk)); +} + +static void program_ddr0_27(unsigned long sdram_freq) +{ + unsigned long const t_init_ps = 200000000; /* 200 us. init */ + unsigned long t_init_clk; + + debug("t_init_ps = %d\n", t_init_ps); + t_init_clk = + (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) | + DDR0_27_TINIT_ENCODE(t_init_clk)); +} + +static void program_ddr0_43(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq, + unsigned long cols, unsigned long banks) +{ + unsigned long dimm_num; + unsigned long t_wr_ps = 0; + unsigned long t_wr_clk; + u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) | + DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) | + DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0); + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36); + t_wr_ps = max(t_wr_ps, ps); + } + } + debug("t_wr_ps = %d\n", t_wr_ps); + t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk)); +} + +static void program_ddr0_44(unsigned long dimm_ranks[], + unsigned char const iic0_dimm_addr[], + unsigned long num_dimm_banks, + unsigned long sdram_freq) +{ + unsigned long dimm_num; + unsigned long t_rcd_ps = 0; + unsigned long t_rcd_clk; + + /*------------------------------------------------------------------ + * Handle the timing. We need to find the worst case timing of all + * the dimm modules installed. + *-----------------------------------------------------------------*/ + /* loop through all the DIMM slots on the board */ + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + /* If a dimm is installed in a particular slot ... */ + if (dimm_ranks[dimm_num]) { + unsigned long ps; + + ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29); + t_rcd_ps = max(t_rcd_ps, ps); + } + } + debug("t_rcd_ps = %d\n", t_rcd_ps); + t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000; + mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk)); +} + +/*-----------------------------------------------------------------------------+ + * initdram. Initializes the 440EPx/GPx DDR SDRAM controller. + * Note: This routine runs from flash with a stack set up in the chip's + * sram space. It is important that the routine does not require .sbss, .bss or + * .data sections. It also cannot call routines that require these sections. + *-----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures SDRAM memory banks for DDR operation. + * Auto Memory Configuration option reads the DDR SDRAM EEPROMs + * via the IIC bus and then configures the DDR SDRAM memory + * banks appropriately. If Auto Memory Configuration is + * not used, it is assumed that no DIMM is plugged + *-----------------------------------------------------------------------------*/ +phys_size_t initdram(int board_type) +{ + unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; + unsigned long dimm_ranks[MAXDIMMS]; + unsigned long ranks; + unsigned long rows; + unsigned long banks; + unsigned long cols; + unsigned long width; + unsigned long const sdram_freq = get_bus_freq(0); + unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */ + unsigned long cas_latency = 0; /* to quiet initialization warning */ + unsigned long dram_size; + + debug("\nEntering initdram()\n"); + + /*------------------------------------------------------------------ + * Stop the DDR-SDRAM controller. + *-----------------------------------------------------------------*/ + mtsdram(DDR0_02, DDR0_02_START_ENCODE(0)); + + /* + * Make sure I2C controller is initialized + * before continuing. + */ + /* switch to correct I2C bus */ + I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + /*------------------------------------------------------------------ + * Clear out the serial presence detect buffers. + * Perform IIC reads from the dimm. Fill in the spds. + * Check to see if the dimm slots are populated + *-----------------------------------------------------------------*/ + get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Check the frequency supported for the dimms plugged. + *-----------------------------------------------------------------*/ + check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + /*------------------------------------------------------------------ + * Check and get size information. + *-----------------------------------------------------------------*/ + get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks, + &cols, &width); + + /*------------------------------------------------------------------ + * Check the voltage type for the dimms plugged. + *-----------------------------------------------------------------*/ + check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks); + + /*------------------------------------------------------------------ + * Program registers for SDRAM controller. + *-----------------------------------------------------------------*/ + mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | + DDR0_00_DLL_START_POINT_DECODE(0x0A)); + + mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) | + DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) | + DDR0_01_INT_MASK_ENCODE(0xFF)); + + program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, + rows, &cas_latency); + + program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + /* + * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia + * board SDRAM, but may be overly conservative. + */ + mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | + DDR0_07_TFAW_ENCODE(13) | + DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | + DDR0_07_AREFRESH_ENCODE(0)); + + mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) | + DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) | + DDR0_08_DDRII_ENCODE(1)); + + mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) | + DDR0_09_RTT_0_ENCODE(0x1) | + DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) | + DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20)); + + program_ddr0_10(dimm_ranks, ranks); + + program_ddr0_11(sdram_freq); + + mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3)); + + mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) | + DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) | + DDR0_14_REG_DIMM_ENABLE_ENCODE(0)); + + mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) | + DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) | + DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY)); + + mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) | + DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS)); + + mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) | + DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS)); + + program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width); + + mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) | + DDR0_23_FWC_ENCODE(0)); + + program_ddr0_24(ranks); + + program_ddr0_26(sdram_freq); + + program_ddr0_27(sdram_freq); + + mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) | + DDR0_28_EMRS2_DATA_ENCODE(0x0000)); + + mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); + + mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) | + DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); + + program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, + cols, banks); + + program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); + + denali_sdram_register_dump(); + + dram_size = (width >= 64) ? 8 : 4; + dram_size *= 1 << cols; + dram_size *= banks; + dram_size *= 1 << rows; + dram_size *= ranks; + debug("dram_size = %lu\n", dram_size); + + /* Start the SDRAM controler */ + mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); + denali_wait_for_dlllock(); + +#if defined(CONFIG_DDR_DATA_EYE) + /* + * Map the first 1 MiB of memory in the TLB, and perform the data eye + * search. + */ + program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); + denali_core_search_data_eye(); + denali_sdram_register_dump(); + remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE); +#endif + +#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) + program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0); + sync(); + /* Zero the memory */ + debug("Zeroing SDRAM..."); +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE); +#else +#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file +#endif + /* Write modified dcache lines back to memory */ + clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE); + debug("Completed\n"); + sync(); + remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size); + +#if defined(CONFIG_DDR_ECC) + /* + * If ECC is enabled, clear and enable interrupts + */ + if (is_ecc_enabled()) { + u32 val; + + sync(); + /* Clear error status */ + mfsdram(DDR0_00, val); + mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + /* Set 'int_mask' parameter to functionnal value */ + mfsdram(DDR0_01, val); + mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) | + DDR0_01_INT_MASK_ALL_OFF); +#if defined(CONFIG_DDR_DATA_EYE) + /* + * Running denali_core_search_data_eye() when ECC is enabled + * causes non-ECC machine checks. This clears them. + */ + print_mcsr(); + mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); + print_mcsr(); +#endif + sync(); + } +#endif /* defined(CONFIG_DDR_ECC) */ +#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ + + program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); + return dram_size; +} + +void board_add_ram_info(int use_default) +{ + u32 val; + + printf(" (ECC"); + if (!is_ecc_enabled()) { + printf(" not"); + } + printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000); + + mfsdram(DDR0_03, val); + printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1); +} +#endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/ecc.c b/arch/ppc/cpu/ppc4xx/ecc.c similarity index 100% rename from cpu/ppc4xx/ecc.c rename to arch/ppc/cpu/ppc4xx/ecc.c diff --git a/cpu/ppc4xx/ecc.h b/arch/ppc/cpu/ppc4xx/ecc.h similarity index 100% rename from cpu/ppc4xx/ecc.h rename to arch/ppc/cpu/ppc4xx/ecc.h diff --git a/cpu/ppc4xx/fdt.c b/arch/ppc/cpu/ppc4xx/fdt.c similarity index 100% rename from cpu/ppc4xx/fdt.c rename to arch/ppc/cpu/ppc4xx/fdt.c diff --git a/cpu/ppc4xx/gpio.c b/arch/ppc/cpu/ppc4xx/gpio.c similarity index 100% rename from cpu/ppc4xx/gpio.c rename to arch/ppc/cpu/ppc4xx/gpio.c diff --git a/cpu/ppc4xx/interrupts.c b/arch/ppc/cpu/ppc4xx/interrupts.c similarity index 100% rename from cpu/ppc4xx/interrupts.c rename to arch/ppc/cpu/ppc4xx/interrupts.c diff --git a/cpu/ppc4xx/iop480_uart.c b/arch/ppc/cpu/ppc4xx/iop480_uart.c similarity index 100% rename from cpu/ppc4xx/iop480_uart.c rename to arch/ppc/cpu/ppc4xx/iop480_uart.c diff --git a/cpu/ppc4xx/kgdb.S b/arch/ppc/cpu/ppc4xx/kgdb.S similarity index 100% rename from cpu/ppc4xx/kgdb.S rename to arch/ppc/cpu/ppc4xx/kgdb.S diff --git a/cpu/ppc4xx/miiphy.c b/arch/ppc/cpu/ppc4xx/miiphy.c similarity index 100% rename from cpu/ppc4xx/miiphy.c rename to arch/ppc/cpu/ppc4xx/miiphy.c diff --git a/cpu/ppc4xx/reginfo.c b/arch/ppc/cpu/ppc4xx/reginfo.c similarity index 100% rename from cpu/ppc4xx/reginfo.c rename to arch/ppc/cpu/ppc4xx/reginfo.c diff --git a/cpu/ppc4xx/resetvec.S b/arch/ppc/cpu/ppc4xx/resetvec.S similarity index 100% rename from cpu/ppc4xx/resetvec.S rename to arch/ppc/cpu/ppc4xx/resetvec.S diff --git a/cpu/ppc4xx/sdram.c b/arch/ppc/cpu/ppc4xx/sdram.c similarity index 100% rename from cpu/ppc4xx/sdram.c rename to arch/ppc/cpu/ppc4xx/sdram.c diff --git a/cpu/ppc4xx/sdram.h b/arch/ppc/cpu/ppc4xx/sdram.h similarity index 100% rename from cpu/ppc4xx/sdram.h rename to arch/ppc/cpu/ppc4xx/sdram.h diff --git a/cpu/ppc4xx/speed.c b/arch/ppc/cpu/ppc4xx/speed.c similarity index 100% rename from cpu/ppc4xx/speed.c rename to arch/ppc/cpu/ppc4xx/speed.c diff --git a/arch/ppc/cpu/ppc4xx/start.S b/arch/ppc/cpu/ppc4xx/start.S new file mode 100644 index 0000000000..c739deb9b4 --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/start.S @@ -0,0 +1,2170 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000,2001,2002 Wolfgang Denk + * Copyright (C) 2007 Stefan Roese , DENX Software Engineering + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/*------------------------------------------------------------------------------+ + * This source code is dual-licensed. You may use it under the terms of the + * GNU General Public License version 2, or under the license below. + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *------------------------------------------------------------------------------- + */ + +/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards + * + * + * The processor starts at 0xfffffffc and the code is executed + * from flash/rom. + * in memory, but as long we don't jump around before relocating. + * board_init lies at a quite high address and when the cpu has + * jumped there, everything is ok. + * This works because the cpu gives the FLASH (CS0) the whole + * address space at startup, and board_init lies as a echo of + * the flash somewhere up there in the memorymap. + * + * board_init will change CS0 to be positioned at the correct + * address and (s)dram will be positioned at address 0 + */ +#include +#include +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#ifdef CONFIG_SYS_INIT_DCACHE_CS +# if (CONFIG_SYS_INIT_DCACHE_CS == 0) +# define PBxAP PB1AP +# define PBxCR PB0CR +# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR +# endif +# endif +# if (CONFIG_SYS_INIT_DCACHE_CS == 1) +# define PBxAP PB1AP +# define PBxCR PB1CR +# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR +# endif +# endif +# if (CONFIG_SYS_INIT_DCACHE_CS == 2) +# define PBxAP PB2AP +# define PBxCR PB2CR +# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR +# endif +# endif +# if (CONFIG_SYS_INIT_DCACHE_CS == 3) +# define PBxAP PB3AP +# define PBxCR PB3CR +# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR +# endif +# endif +# if (CONFIG_SYS_INIT_DCACHE_CS == 4) +# define PBxAP PB4AP +# define PBxCR PB4CR +# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR +# endif +# endif +# if (CONFIG_SYS_INIT_DCACHE_CS == 5) +# define PBxAP PB5AP +# define PBxCR PB5CR +# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR +# endif +# endif +# if (CONFIG_SYS_INIT_DCACHE_CS == 6) +# define PBxAP PB6AP +# define PBxCR PB6CR +# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR +# endif +# endif +# if (CONFIG_SYS_INIT_DCACHE_CS == 7) +# define PBxAP PB7AP +# define PBxCR PB7CR +# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR +# endif +# endif +# ifndef PBxAP_VAL +# define PBxAP_VAL 0 +# endif +# ifndef PBxCR_VAL +# define PBxCR_VAL 0 +# endif +/* + * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB + * used as temporary stack pointer for the primordial stack + */ +# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR +# define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ +# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR +# define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) +# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ +# ifndef CONFIG_SYS_INIT_RAM_PATTERN +# define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD +# endif +#endif /* CONFIG_SYS_INIT_DCACHE_CS */ + +#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10))) +#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END! +#endif + +/* + * Unless otherwise overriden, enable two 128MB cachable instruction regions + * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering + * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. + */ +#if !defined(CONFIG_SYS_FLASH_BASE) +/* If not already defined, set it to the "last" 128MByte region */ +# define CONFIG_SYS_FLASH_BASE 0xf8000000 +#endif +#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) +# define CONFIG_SYS_ICACHE_SACR_VALUE \ + (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ + PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ + PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) +#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ + +#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) +# define CONFIG_SYS_DCACHE_SACR_VALUE \ + (0x00000000) +#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ + +#define function_prolog(func_name) .text; \ + .align 2; \ + .globl func_name; \ + func_name: +#define function_epilog(func_name) .type func_name,@function; \ + .size func_name,.-func_name + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ + + + .extern ext_bus_cntlr_init +#ifdef CONFIG_NAND_U_BOOT + .extern reconfig_tlb0 +#endif + +/* + * Set up GOT: Global Offset Table + * + * Use r12 to access the GOT + */ +#if !defined(CONFIG_NAND_SPL) + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT +#endif /* CONFIG_NAND_SPL */ + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /* + * NAND U-Boot image is started from offset 0 + */ + .text +#if defined(CONFIG_440) + bl reconfig_tlb0 +#endif + GET_GOT + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + bl board_init_f +#endif + +#if defined(CONFIG_SYS_RAMBOOT) + /* + * 4xx RAM-booting U-Boot image is started from offset 0 + */ + .text + bl _start_440 +#endif + +/* + * 440 Startup -- on reset only the top 4k of the effective + * address space is mapped in by an entry in the instruction + * and data shadow TLB. The .bootpg section is located in the + * top 4k & does only what's necessary to map in the the rest + * of the boot rom. Once the boot rom is mapped in we can + * proceed with normal startup. + * + * NOTE: CS0 only covers the top 2MB of the effective address + * space after reset. + */ + +#if defined(CONFIG_440) +#if !defined(CONFIG_NAND_SPL) + .section .bootpg,"ax" +#endif + .globl _start_440 + +/**************************************************************************/ +_start_440: + /*--------------------------------------------------------------------+ + | 440EPX BUP Change - Hardware team request + +--------------------------------------------------------------------*/ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + sync + nop + nop +#endif + /*----------------------------------------------------------------+ + | Core bug fix. Clear the esr + +-----------------------------------------------------------------*/ + li r0,0 + mtspr SPRN_ESR,r0 + /*----------------------------------------------------------------*/ + /* Clear and set up some registers. */ + /*----------------------------------------------------------------*/ + iccci r0,r0 /* NOTE: operands not used for 440 */ + dccci r0,r0 /* NOTE: operands not used for 440 */ + sync + li r0,0 + mtspr SPRN_SRR0,r0 + mtspr SPRN_SRR1,r0 + mtspr SPRN_CSRR0,r0 + mtspr SPRN_CSRR1,r0 + /* NOTE: 440GX adds machine check status regs */ +#if defined(CONFIG_440) && !defined(CONFIG_440GP) + mtspr SPRN_MCSRR0,r0 + mtspr SPRN_MCSRR1,r0 + mfspr r1,SPRN_MCSR + mtspr SPRN_MCSR,r1 +#endif + + /*----------------------------------------------------------------*/ + /* CCR0 init */ + /*----------------------------------------------------------------*/ + /* Disable store gathering & broadcast, guarantee inst/data + * cache block touch, force load/store alignment + * (see errata 1.12: 440_33) + */ + lis r1,0x0030 /* store gathering & broadcast disable */ + ori r1,r1,0x6000 /* cache touch */ + mtspr SPRN_CCR0,r1 + + /*----------------------------------------------------------------*/ + /* Initialize debug */ + /*----------------------------------------------------------------*/ + mfspr r1,SPRN_DBCR0 + andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ + bne skip_debug_init /* if set, don't clear debug register */ + mtspr SPRN_DBCR0,r0 + mtspr SPRN_DBCR1,r0 + mtspr SPRN_DBCR2,r0 + mtspr SPRN_IAC1,r0 + mtspr SPRN_IAC2,r0 + mtspr SPRN_IAC3,r0 + mtspr SPRN_DAC1,r0 + mtspr SPRN_DAC2,r0 + mtspr SPRN_DVC1,r0 + mtspr SPRN_DVC2,r0 + + mfspr r1,SPRN_DBSR + mtspr SPRN_DBSR,r1 /* Clear all valid bits */ +skip_debug_init: + +#if defined (CONFIG_440SPE) + /*----------------------------------------------------------------+ + | Initialize Core Configuration Reg1. + | a. ICDPEI: Record even parity. Normal operation. + | b. ICTPEI: Record even parity. Normal operation. + | c. DCTPEI: Record even parity. Normal operation. + | d. DCDPEI: Record even parity. Normal operation. + | e. DCUPEI: Record even parity. Normal operation. + | f. DCMPEI: Record even parity. Normal operation. + | g. FCOM: Normal operation + | h. MMUPEI: Record even parity. Normal operation. + | i. FFF: Flush only as much data as necessary. + | j. TCS: Timebase increments from CPU clock. + +-----------------------------------------------------------------*/ + li r0,0 + mtspr SPRN_CCR1, r0 + + /*----------------------------------------------------------------+ + | Reset the timebase. + | The previous write to CCR1 sets the timebase source. + +-----------------------------------------------------------------*/ + mtspr SPRN_TBWL, r0 + mtspr SPRN_TBWU, r0 +#endif + + /*----------------------------------------------------------------*/ + /* Setup interrupt vectors */ + /*----------------------------------------------------------------*/ + mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ + li r1,0x0100 + mtspr SPRN_IVOR0,r1 /* Critical input */ + li r1,0x0200 + mtspr SPRN_IVOR1,r1 /* Machine check */ + li r1,0x0300 + mtspr SPRN_IVOR2,r1 /* Data storage */ + li r1,0x0400 + mtspr SPRN_IVOR3,r1 /* Instruction storage */ + li r1,0x0500 + mtspr SPRN_IVOR4,r1 /* External interrupt */ + li r1,0x0600 + mtspr SPRN_IVOR5,r1 /* Alignment */ + li r1,0x0700 + mtspr SPRN_IVOR6,r1 /* Program check */ + li r1,0x0800 + mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ + li r1,0x0c00 + mtspr SPRN_IVOR8,r1 /* System call */ + li r1,0x0a00 + mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ + li r1,0x0900 + mtspr SPRN_IVOR10,r1 /* Decrementer */ + li r1,0x1300 + mtspr SPRN_IVOR13,r1 /* Data TLB error */ + li r1,0x1400 + mtspr SPRN_IVOR14,r1 /* Instr TLB error */ + li r1,0x2000 + mtspr SPRN_IVOR15,r1 /* Debug */ + + /*----------------------------------------------------------------*/ + /* Configure cache regions */ + /*----------------------------------------------------------------*/ + mtspr SPRN_INV0,r0 + mtspr SPRN_INV1,r0 + mtspr SPRN_INV2,r0 + mtspr SPRN_INV3,r0 + mtspr SPRN_DNV0,r0 + mtspr SPRN_DNV1,r0 + mtspr SPRN_DNV2,r0 + mtspr SPRN_DNV3,r0 + mtspr SPRN_ITV0,r0 + mtspr SPRN_ITV1,r0 + mtspr SPRN_ITV2,r0 + mtspr SPRN_ITV3,r0 + mtspr SPRN_DTV0,r0 + mtspr SPRN_DTV1,r0 + mtspr SPRN_DTV2,r0 + mtspr SPRN_DTV3,r0 + + /*----------------------------------------------------------------*/ + /* Cache victim limits */ + /*----------------------------------------------------------------*/ + /* floors 0, ceiling max to use the entire cache -- nothing locked + */ + lis r1,0x0001 + ori r1,r1,0xf800 + mtspr SPRN_IVLIM,r1 + mtspr SPRN_DVLIM,r1 + + /*----------------------------------------------------------------+ + |Initialize MMUCR[STID] = 0. + +-----------------------------------------------------------------*/ + mfspr r0,SPRN_MMUCR + addis r1,0,0xFFFF + ori r1,r1,0xFF00 + and r0,r0,r1 + mtspr SPRN_MMUCR,r0 + + /*----------------------------------------------------------------*/ + /* Clear all TLB entries -- TID = 0, TS = 0 */ + /*----------------------------------------------------------------*/ + addis r0,0,0x0000 +#ifdef CONFIG_SYS_RAMBOOT + li r4,0 /* Start with TLB #0 */ +#else + li r4,1 /* Start with TLB #1 */ +#endif + li r1,64 /* 64 TLB entries */ + sub r1,r1,r4 /* calculate last TLB # */ + mtctr r1 +rsttlb: +#ifdef CONFIG_SYS_RAMBOOT + tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ + rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */ + beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */ +#endif + tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/ + tlbwe r0,r4,1 + tlbwe r0,r4,2 +tlbnxt: addi r4,r4,1 /* Next TLB */ + bdnz rsttlb + + /*----------------------------------------------------------------*/ + /* TLB entry setup -- step thru tlbtab */ + /*----------------------------------------------------------------*/ +#if defined(CONFIG_440SPE_REVA) + /*----------------------------------------------------------------*/ + /* We have different TLB tables for revA and rev B of 440SPe */ + /*----------------------------------------------------------------*/ + mfspr r1, PVR + lis r0,0x5342 + ori r0,r0,0x1891 + cmpw r7,r1,r0 + bne r7,..revA + bl tlbtabB + b ..goon +..revA: + bl tlbtabA +..goon: +#else + bl tlbtab /* Get tlbtab pointer */ +#endif + mr r5,r0 + li r1,0x003f /* 64 TLB entries max */ + mtctr r1 + li r4,0 /* TLB # */ + + addi r5,r5,-4 +1: +#ifdef CONFIG_SYS_RAMBOOT + tlbre r3,r4,0 /* Read contents from TLB word #0 */ + rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */ + bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */ +#endif + lwzu r0,4(r5) + cmpwi r0,0 + beq 2f /* 0 marks end */ + lwzu r1,4(r5) + lwzu r2,4(r5) + tlbwe r0,r4,0 /* TLB Word 0 */ + tlbwe r1,r4,1 /* TLB Word 1 */ + tlbwe r2,r4,2 /* TLB Word 2 */ +tlbnx2: addi r4,r4,1 /* Next TLB */ + bdnz 1b + + /*----------------------------------------------------------------*/ + /* Continue from 'normal' start */ + /*----------------------------------------------------------------*/ +2: + bl 3f + b _start + +3: li r0,0 + mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ + mflr r1 + mtspr SPRN_SRR0,r1 + rfi +#endif /* CONFIG_440 */ + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ +#ifndef CONFIG_NAND_SPL + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start_of_vectors +_start_of_vectors: + +/* Critical input. */ + CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) + +#ifdef CONFIG_440 +/* Machine check */ + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) +#else + CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) +#endif /* CONFIG_440 */ + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) + +#ifdef CONFIG_440 + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) + STD_EXCEPTION(0xa00, APU, UnknownException) +#endif + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + +#ifdef CONFIG_440 + STD_EXCEPTION(0x1300, DataTLBError, UnknownException) + STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) +#else + STD_EXCEPTION(0x1000, PIT, DecrementerPITException) + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) +#endif + CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) + + .globl _end_of_vectors +_end_of_vectors: + . = _START_OFFSET +#endif + .globl _start +_start: + +/*****************************************************************************/ +#if defined(CONFIG_440) + + /*----------------------------------------------------------------*/ + /* Clear and set up some registers. */ + /*----------------------------------------------------------------*/ + li r0,0x0000 + lis r1,0xffff + mtspr SPRN_DEC,r0 /* prevent dec exceptions */ + mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ + mtspr SPRN_TBWU,r0 + mtspr SPRN_TSR,r1 /* clear all timer exception status */ + mtspr SPRN_TCR,r0 /* disable all */ + mtspr SPRN_ESR,r0 /* clear exception syndrome register */ + mtxer r0 /* clear integer exception register */ + + /*----------------------------------------------------------------*/ + /* Debug setup -- some (not very good) ice's need an event*/ + /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ + /* value you need in this case 0x8cff 0000 should do the trick */ + /*----------------------------------------------------------------*/ +#if defined(CONFIG_SYS_INIT_DBCR) + lis r1,0xffff + ori r1,r1,0xffff + mtspr SPRN_DBSR,r1 /* Clear all status bits */ + lis r0,CONFIG_SYS_INIT_DBCR@h + ori r0,r0,CONFIG_SYS_INIT_DBCR@l + mtspr SPRN_DBCR0,r0 + isync +#endif + + /*----------------------------------------------------------------*/ + /* Setup the internal SRAM */ + /*----------------------------------------------------------------*/ + li r0,0 + +#ifdef CONFIG_SYS_INIT_RAM_DCACHE + /* Clear Dcache to use as RAM */ + addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + addis r4,r0,CONFIG_SYS_INIT_RAM_END@h + ori r4,r4,CONFIG_SYS_INIT_RAM_END@l + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ran + addi r5,r5,0x0001 +..d_ran: + mtctr r5 +..d_ag: + dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag + + /* + * Lock the init-ram/stack in d-cache, so that other regions + * may use d-cache as well + * Note, that this current implementation locks exactly 4k + * of d-cache, so please make sure that you don't define a + * bigger init-ram area. Take a look at the lwmon5 440EPx + * implementation as a reference. + */ + msync + isync + /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ + lis r1,0x0201 + ori r1,r1,0xf808 + mtspr SPRN_DVLIM,r1 + lis r1,0x0808 + ori r1,r1,0x0808 + mtspr SPRN_DNV0,r1 + mtspr SPRN_DNV1,r1 + mtspr SPRN_DNV2,r1 + mtspr SPRN_DNV3,r1 + mtspr SPRN_DTV0,r1 + mtspr SPRN_DTV1,r1 + mtspr SPRN_DTV2,r1 + mtspr SPRN_DTV3,r1 + msync + isync +#endif /* CONFIG_SYS_INIT_RAM_DCACHE */ + + /* 440EP & 440GR are only 440er PPC's without internal SRAM */ +#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) + /* not all PPC's have internal SRAM usable as L2-cache */ +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460SX) + mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r1, 0x0000 + ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ + mtdcr L2_CACHE_CFG,r1 +#endif + + lis r2,0x7fff + ori r2,r2,0xffff + mfdcr r1,ISRAM0_DPC + and r1,r1,r2 /* Disable parity check */ + mtdcr ISRAM0_DPC,r1 + mfdcr r1,ISRAM0_PMEG + and r1,r1,r2 /* Disable pwr mgmt */ + mtdcr ISRAM0_PMEG,r1 + + lis r1,0x8000 /* BAS = 8000_0000 */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) + ori r1,r1,0x0980 /* first 64k */ + mtdcr ISRAM0_SB0CR,r1 + lis r1,0x8001 + ori r1,r1,0x0980 /* second 64k */ + mtdcr ISRAM0_SB1CR,r1 + lis r1, 0x8002 + ori r1,r1, 0x0980 /* third 64k */ + mtdcr ISRAM0_SB2CR,r1 + lis r1, 0x8003 + ori r1,r1, 0x0980 /* fourth 64k */ + mtdcr ISRAM0_SB3CR,r1 +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r1,0x0000 /* BAS = X_0000_0000 */ + ori r1,r1,0x0984 /* first 64k */ + mtdcr ISRAM0_SB0CR,r1 + lis r1,0x0001 + ori r1,r1,0x0984 /* second 64k */ + mtdcr ISRAM0_SB1CR,r1 + lis r1, 0x0002 + ori r1,r1, 0x0984 /* third 64k */ + mtdcr ISRAM0_SB2CR,r1 + lis r1, 0x0003 + ori r1,r1, 0x0984 /* fourth 64k */ + mtdcr ISRAM0_SB3CR,r1 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r2,0x7fff + ori r2,r2,0xffff + mfdcr r1,ISRAM1_DPC + and r1,r1,r2 /* Disable parity check */ + mtdcr ISRAM1_DPC,r1 + mfdcr r1,ISRAM1_PMEG + and r1,r1,r2 /* Disable pwr mgmt */ + mtdcr ISRAM1_PMEG,r1 + + lis r1,0x0004 /* BAS = 4_0004_0000 */ + ori r1,r1,0x0984 /* 64k */ + mtdcr ISRAM1_SB0CR,r1 +#endif +#elif defined(CONFIG_460SX) + lis r1,0x0000 /* BAS = 0000_0000 */ + ori r1,r1,0x0B84 /* first 128k */ + mtdcr ISRAM0_SB0CR,r1 + lis r1,0x0001 + ori r1,r1,0x0B84 /* second 128k */ + mtdcr ISRAM0_SB1CR,r1 + lis r1, 0x0002 + ori r1,r1, 0x0B84 /* third 128k */ + mtdcr ISRAM0_SB2CR,r1 + lis r1, 0x0003 + ori r1,r1, 0x0B84 /* fourth 128k */ + mtdcr ISRAM0_SB3CR,r1 +#elif defined(CONFIG_440GP) + ori r1,r1,0x0380 /* 8k rw */ + mtdcr ISRAM0_SB0CR,r1 + mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ +#endif +#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ + + /*----------------------------------------------------------------*/ + /* Setup the stack in internal SRAM */ + /*----------------------------------------------------------------*/ + lis r1,CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l + li r0,0 + stwu r0,-4(r1) + stwu r0,-4(r1) /* Terminate call chain */ + + stwu r1,-8(r1) /* Save back chain and move SP */ + lis r0,RESET_VECTOR@h /* Address of reset vector */ + ori r0,r0, RESET_VECTOR@l + stwu r1,-8(r1) /* Save back chain and move SP */ + stw r0,+12(r1) /* Save return addr (underflow vect) */ + +#ifdef CONFIG_NAND_SPL + bl nand_boot_common /* will not return */ +#else + GET_GOT + + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + bl board_init_f +#endif + +#endif /* CONFIG_440 */ + +/*****************************************************************************/ +#ifdef CONFIG_IOP480 + /*----------------------------------------------------------------------- */ + /* Set up some machine state registers. */ + /*----------------------------------------------------------------------- */ + addi r0,r0,0x0000 /* initialize r0 to zero */ + mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ + mttcr r0 /* timer control register */ + mtexier r0 /* disable all interrupts */ + addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ + ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ + mtdbsr r4 /* clear/reset the dbsr */ + mtexisr r4 /* clear all pending interrupts */ + addis r4,r0,0x8000 + mtexier r4 /* enable critical exceptions */ + addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ + ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ + mtiocr r4 /* since bit not used) & DRC to latch */ + /* data bus on rising edge of CAS */ + /*----------------------------------------------------------------------- */ + /* Clear XER. */ + /*----------------------------------------------------------------------- */ + mtxer r0 + /*----------------------------------------------------------------------- */ + /* Invalidate i-cache and d-cache TAG arrays. */ + /*----------------------------------------------------------------------- */ + addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ + addi r4,0,1024 /* 1/4 of I-cache */ +..cloop: + iccci 0,r3 + iccci r4,r3 + dccci 0,r3 + addic. r3,r3,-16 /* move back one cache line */ + bne ..cloop /* loop back to do rest until r3 = 0 */ + + /* */ + /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ + /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ + /* */ + + /* first copy IOP480 register base address into r3 */ + addis r3,0,0x5000 /* IOP480 register base address hi */ +/* ori r3,r3,0x0000 / IOP480 register base address lo */ + +#ifdef CONFIG_ADCIOP + /* use r4 as the working variable */ + /* turn on CS3 (LOCCTL.7) */ + lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ + andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ + stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ +#endif + +#ifdef CONFIG_DASA_SIM + /* use r4 as the working variable */ + /* turn on MA17 (LOCCTL.7) */ + lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ + ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ + stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ +#endif + + /* turn on MA16..13 (LCS0BRD.12 = 0) */ + lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ + andi. r4,r4,0xefff /* make bit 12 = 0 */ + stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ + + /* make sure above stores all comlete before going on */ + sync + + /* last thing, set local init status done bit (DEVINIT.31) */ + lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ + oris r4,r4,0x8000 /* make bit 31 = 1 */ + stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ + + /* clear all pending interrupts and disable all interrupts */ + li r4,-1 /* set p1 to 0xffffffff */ + stw r4,0x1b0(r3) /* clear all pending interrupts */ + stw r4,0x1b8(r3) /* clear all pending interrupts */ + li r4,0 /* set r4 to 0 */ + stw r4,0x1b4(r3) /* disable all interrupts */ + stw r4,0x1bc(r3) /* disable all interrupts */ + + /* make sure above stores all comlete before going on */ + sync + + /* Set-up icache cacheability. */ + lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h + ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l + mticcr r1 + isync + + /* Set-up dcache cacheability. */ + lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h + ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l + mtdccr r1 + + addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + GET_GOT /* initialize GOT access */ + + bl board_init_f /* run first part of init code (from Flash) */ + +#endif /* CONFIG_IOP480 */ + +/*****************************************************************************/ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || defined(CONFIG_405) + /*----------------------------------------------------------------------- */ + /* Clear and set up some registers. */ + /*----------------------------------------------------------------------- */ + addi r4,r0,0x0000 +#if !defined(CONFIG_405EX) + mtspr SPRN_SGR,r4 +#else + /* + * On 405EX, completely clearing the SGR leads to PPC hangup + * upon PCIe configuration access. The PCIe memory regions + * need to be guarded! + */ + lis r3,0x0000 + ori r3,r3,0x7FFC + mtspr SPRN_SGR,r3 +#endif + mtspr SPRN_DCWR,r4 + mtesr r4 /* clear Exception Syndrome Reg */ + mttcr r4 /* clear Timer Control Reg */ + mtxer r4 /* clear Fixed-Point Exception Reg */ + mtevpr r4 /* clear Exception Vector Prefix Reg */ + addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ + /* dbsr is cleared by setting bits to 1) */ + mtdbsr r4 /* clear/reset the dbsr */ + + /* Invalidate the i- and d-caches. */ + bl invalidate_icache + bl invalidate_dcache + + /* Set-up icache cacheability. */ + lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h + ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l + mticcr r4 + isync + + /* Set-up dcache cacheability. */ + lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h + ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l + mtdccr r4 + +#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ + && !defined (CONFIG_XILINX_405) + /*----------------------------------------------------------------------- */ + /* Tune the speed and size for flash CS0 */ + /*----------------------------------------------------------------------- */ + bl ext_bus_cntlr_init +#endif + +#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) + /* + * For boards that don't have OCM and can't use the data cache + * for their primordial stack, setup stack here directly after the + * SDRAM is initialized in ext_bus_cntlr_init. + */ + lis r1, CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + lis r0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ +#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ + +#if defined(CONFIG_405EP) + /*----------------------------------------------------------------------- */ + /* DMA Status, clear to come up clean */ + /*----------------------------------------------------------------------- */ + addis r3,r0, 0xFFFF /* Clear all existing DMA status */ + ori r3,r3, 0xFFFF + mtdcr DMASR, r3 + + bl ppc405ep_init /* do ppc405ep specific init */ +#endif /* CONFIG_405EP */ + +#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) +#if defined(CONFIG_405EZ) + /******************************************************************** + * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 + *******************************************************************/ + /* + * We can map the OCM on the PLB3, so map it at + * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 + */ + lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ + mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ + mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ + isync + + lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ + mtdcr OCM0_DSRC1, r3 /* Set Data Side */ + mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ + mtdcr OCM0_DSRC2, r3 /* Set Data Side */ + mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ + addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ + mtdcr OCM0_DISDPC,r3 + + isync +#else /* CONFIG_405EZ */ + /******************************************************************** + * Setup OCM - On Chip Memory + *******************************************************************/ + /* Setup OCM */ + lis r0, 0x7FFF + ori r0, r0, 0xFFFF + mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ + mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ + and r3, r3, r0 /* disable data-side IRAM */ + and r4, r4, r0 /* disable data-side IRAM */ + mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ + mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ + isync + + lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l + mtdcr OCM0_DSARC, r3 + addis r4, 0, 0xC000 /* OCM data area enabled */ + mtdcr OCM0_DSCNTL, r4 + isync +#endif /* CONFIG_405EZ */ +#endif + + /*----------------------------------------------------------------------- */ + /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ + /*----------------------------------------------------------------------- */ +#ifdef CONFIG_SYS_INIT_DCACHE_CS + li r4, PBxAP + mtdcr EBC0_CFGADDR, r4 + lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h + ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l + mtdcr EBC0_CFGDATA, r4 + + addi r4, 0, PBxCR + mtdcr EBC0_CFGADDR, r4 + lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h + ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l + mtdcr EBC0_CFGDATA, r4 + + /* + * Enable the data cache for the 128MB storage access control region + * at CONFIG_SYS_INIT_RAM_ADDR. + */ + mfdccr r4 + oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l + mtdccr r4 + + /* + * Preallocate data cache lines to be used to avoid a subsequent + * cache miss and an ensuing machine check exception when exceptions + * are enabled. + */ + li r0, 0 + + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l + + lis r4, CONFIG_SYS_INIT_RAM_END@h + ori r4, r4, CONFIG_SYS_INIT_RAM_END@l + + /* + * Convert the size, in bytes, to the number of cache lines/blocks + * to preallocate. + */ + clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) + srwi r5, r4, L1_CACHE_SHIFT + beq ..load_counter + addi r5, r5, 0x0001 +..load_counter: + mtctr r5 + + /* Preallocate the computed number of cache blocks. */ +..alloc_dcache_block: + dcba r0, r3 + addi r3, r3, L1_CACHE_BYTES + bdnz ..alloc_dcache_block + sync + + /* + * Load the initial stack pointer and data area and convert the size, + * in bytes, to the number of words to initialize to a known value. + */ + lis r1, CONFIG_SYS_INIT_RAM_ADDR@h + ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l + + lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h + ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l + mtctr r4 + + lis r2, CONFIG_SYS_INIT_RAM_ADDR@h + ori r2, r2, CONFIG_SYS_INIT_RAM_END@l + + lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h + ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l + +..stackloop: + stwu r4, -4(r2) + bdnz ..stackloop + + /* + * Make room for stack frame header and clear final stack frame so + * that stack backtraces terminate cleanly. + */ + stwu r0, -4(r1) + stwu r0, -4(r1) + + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ + +#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ + (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) + /* + * Stack in OCM. + */ + + /* Set up Stack at top of OCM */ + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l + + /* Set up a zeroized stack frame so that backtrace works right */ + li r0, 0 + stwu r0, -4(r1) + stwu r0, -4(r1) + + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + lis r0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ +#endif /* CONFIG_SYS_INIT_DCACHE_CS */ + +#ifdef CONFIG_NAND_SPL + bl nand_boot_common /* will not return */ +#else + GET_GOT /* initialize GOT access */ + + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + + /* NEVER RETURNS! */ + bl board_init_f /* run first part of init code (from Flash) */ +#endif /* CONFIG_NAND_SPL */ + +#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ + /*----------------------------------------------------------------------- */ + + +#ifndef CONFIG_NAND_SPL +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +crit_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SPRN_CSRR0,r2 + mtspr SPRN_CSRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfci + +#ifdef CONFIG_440 +mck_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SPRN_MCSRR0,r2 + mtspr SPRN_MCSRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfmci +#endif /* CONFIG_440 */ + + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,r0,r3 + blr + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = Relocated stack pointer + * r4 = Relocated global data pointer + * r5 = Relocated text pointer + */ + .globl relocate_code +relocate_code: +#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) + /* + * We need to flush the initial global data (gd_t) before the dcache + * will be invalidated. + */ + + /* Save registers */ + mr r9, r3 + mr r10, r4 + mr r11, r5 + + /* Flush initial global data range */ + mr r3, r4 + addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l + bl flush_dcache_range + +#if defined(CONFIG_SYS_INIT_DCACHE_CS) + /* + * Undo the earlier data cache set-up for the primordial stack and + * data area. First, invalidate the data cache and then disable data + * cacheability for that area. Finally, restore the EBC values, if + * any. + */ + + /* Invalidate the primordial stack and data area in cache */ + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l + + lis r4, CONFIG_SYS_INIT_RAM_END@h + ori r4, r4, CONFIG_SYS_INIT_RAM_END@l + add r4, r4, r3 + + bl invalidate_dcache_range + + /* Disable cacheability for the region */ + mfdccr r3 + lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l + and r3, r3, r4 + mtdccr r3 + + /* Restore the EBC parameters */ + li r3, PBxAP + mtdcr EBC0_CFGADDR, r3 + lis r3, PBxAP_VAL@h + ori r3, r3, PBxAP_VAL@l + mtdcr EBC0_CFGDATA, r3 + + li r3, PBxCR + mtdcr EBC0_CFGADDR, r3 + lis r3, PBxCR_VAL@h + ori r3, r3, PBxCR_VAL@l + mtdcr EBC0_CFGDATA, r3 +#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ + + /* Restore registers */ + mr r3, r9 + mr r4, r10 + mr r5, r11 +#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ + +#ifdef CONFIG_SYS_INIT_RAM_DCACHE + /* + * Unlock the previously locked d-cache + */ + msync + isync + /* set TFLOOR/NFLOOR to 0 again */ + lis r6,0x0001 + ori r6,r6,0xf800 + mtspr SPRN_DVLIM,r6 + lis r6,0x0000 + ori r6,r6,0x0000 + mtspr SPRN_DNV0,r6 + mtspr SPRN_DNV1,r6 + mtspr SPRN_DNV2,r6 + mtspr SPRN_DNV3,r6 + mtspr SPRN_DTV0,r6 + mtspr SPRN_DTV1,r6 + mtspr SPRN_DTV2,r6 + mtspr SPRN_DTV3,r6 + msync + isync +#endif /* CONFIG_SYS_INIT_RAM_DCACHE */ + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + /* + * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) + * to speed up the boot process. Now this cache needs to be disabled. + */ + iccci 0,0 /* Invalidate inst cache */ + dccci 0,0 /* Invalidate data cache, now no longer our stack */ + sync + isync + + /* Clear all potential pending exceptions */ + mfspr r1,SPRN_MCSR + mtspr SPRN_MCSR,r1 +#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH + addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ +#else + addi r1,r0,0x0000 /* Default TLB entry is #0 */ +#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */ + tlbre r0,r1,0x0002 /* Read contents */ + ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ + tlbwe r0,r1,0x0002 /* Save it out */ + sync + isync +#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Init Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + GET_GOT + mr r3, r5 /* Destination Address */ + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, L1_CACHE_BYTES /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r12, r12, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + _START_OFFSET + mtlr r0 + blr /* NEVER RETURNS! */ + +in_ram: + + /* + * Relocation Function, r12 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f + add r0,r0,r11 + stw r0,0(r3) +2: bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ + li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 7f + + li r0, 0 + + andi. r5, r4, 3 + beq 6f + sub r4, r4, r5 + mtctr r5 + mr r5, r4 +5: stb r0, 0(r5) + addi r5, r5, 1 + bdnz 5b +6: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 6b + +7: + mr r3, r9 /* Init Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + mflr r4 /* save link register */ + GET_GOT + lwz r7, GOT(_start_of_vectors) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + _START_OFFSET + li r8, Alignment - _start + _START_OFFSET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + _START_OFFSET + bl trap_reloc + +#ifdef CONFIG_440 + li r7, .L_FPUnavailable - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_Decrementer - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_APU - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_InstructionTLBError - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_DataTLBError - _start + _START_OFFSET + bl trap_reloc +#else /* CONFIG_440 */ + li r7, .L_PIT - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_InstructionTLBMiss - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_DataTLBMiss - _start + _START_OFFSET + bl trap_reloc +#endif /* CONFIG_440 */ + + li r7, .L_DebugBreakpoint - _start + _START_OFFSET + bl trap_reloc + +#if !defined(CONFIG_440) + addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ + oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ + mtmsr r7 /* change MSR */ +#else + bl __440_msr_set + b __440_msr_continue + +__440_msr_set: + addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ + oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ + mtspr SPRN_SRR1,r7 + mflr r7 + mtspr SPRN_SRR0,r7 + rfi +__440_msr_continue: +#endif + + mtlr r4 /* restore link register */ + blr + +#if defined(CONFIG_440) +/*----------------------------------------------------------------------------+ +| dcbz_area. ++----------------------------------------------------------------------------*/ + function_prolog(dcbz_area) + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 +..d_ra2:mtctr r5 +..d_ag2:dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag2 + sync + blr + function_epilog(dcbz_area) +#endif /* CONFIG_440 */ +#endif /* CONFIG_NAND_SPL */ + +/*------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr + +/**************************************************************************/ +/* PPC405EP specific stuff */ +/**************************************************************************/ +#ifdef CONFIG_405EP +ppc405ep_init: + +#ifdef CONFIG_BUBINGA + /* + * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate + * function) to support FPGA and NVRAM accesses below. + */ + + lis r3,GPIO0_OSRH@h /* config GPIO output select */ + ori r3,r3,GPIO0_OSRH@l + lis r4,CONFIG_SYS_GPIO0_OSRH@h + ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l + stw r4,0(r3) + lis r3,GPIO0_OSRL@h + ori r3,r3,GPIO0_OSRL@l + lis r4,CONFIG_SYS_GPIO0_OSRL@h + ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l + stw r4,0(r3) + + lis r3,GPIO0_ISR1H@h /* config GPIO input select */ + ori r3,r3,GPIO0_ISR1H@l + lis r4,CONFIG_SYS_GPIO0_ISR1H@h + ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l + stw r4,0(r3) + lis r3,GPIO0_ISR1L@h + ori r3,r3,GPIO0_ISR1L@l + lis r4,CONFIG_SYS_GPIO0_ISR1L@h + ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l + stw r4,0(r3) + + lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ + ori r3,r3,GPIO0_TSRH@l + lis r4,CONFIG_SYS_GPIO0_TSRH@h + ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l + stw r4,0(r3) + lis r3,GPIO0_TSRL@h + ori r3,r3,GPIO0_TSRL@l + lis r4,CONFIG_SYS_GPIO0_TSRL@h + ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l + stw r4,0(r3) + + lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ + ori r3,r3,GPIO0_TCR@l + lis r4,CONFIG_SYS_GPIO0_TCR@h + ori r4,r4,CONFIG_SYS_GPIO0_TCR@l + stw r4,0(r3) + + li r3,PB1AP /* program EBC bank 1 for RTC access */ + mtdcr EBC0_CFGADDR,r3 + lis r3,CONFIG_SYS_EBC_PB1AP@h + ori r3,r3,CONFIG_SYS_EBC_PB1AP@l + mtdcr EBC0_CFGDATA,r3 + li r3,PB1CR + mtdcr EBC0_CFGADDR,r3 + lis r3,CONFIG_SYS_EBC_PB1CR@h + ori r3,r3,CONFIG_SYS_EBC_PB1CR@l + mtdcr EBC0_CFGDATA,r3 + + li r3,PB1AP /* program EBC bank 1 for RTC access */ + mtdcr EBC0_CFGADDR,r3 + lis r3,CONFIG_SYS_EBC_PB1AP@h + ori r3,r3,CONFIG_SYS_EBC_PB1AP@l + mtdcr EBC0_CFGDATA,r3 + li r3,PB1CR + mtdcr EBC0_CFGADDR,r3 + lis r3,CONFIG_SYS_EBC_PB1CR@h + ori r3,r3,CONFIG_SYS_EBC_PB1CR@l + mtdcr EBC0_CFGDATA,r3 + + li r3,PB4AP /* program EBC bank 4 for FPGA access */ + mtdcr EBC0_CFGADDR,r3 + lis r3,CONFIG_SYS_EBC_PB4AP@h + ori r3,r3,CONFIG_SYS_EBC_PB4AP@l + mtdcr EBC0_CFGDATA,r3 + li r3,PB4CR + mtdcr EBC0_CFGADDR,r3 + lis r3,CONFIG_SYS_EBC_PB4CR@h + ori r3,r3,CONFIG_SYS_EBC_PB4CR@l + mtdcr EBC0_CFGDATA,r3 +#endif + + /* + !----------------------------------------------------------------------- + ! Check to see if chip is in bypass mode. + ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a + ! CPU reset Otherwise, skip this step and keep going. + ! Note: Running BIOS in bypass mode is not supported since PLB speed + ! will not be fast enough for the SDRAM (min 66MHz) + !----------------------------------------------------------------------- + */ + mfdcr r5, CPC0_PLLMR1 + rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ + cmpi cr0,0,r4,0x1 + + beq pll_done /* if SSCS =b'1' then PLL has */ + /* already been set */ + /* and CPU has been reset */ + /* so skip to next section */ + +#ifdef CONFIG_BUBINGA + /* + !----------------------------------------------------------------------- + ! Read NVRAM to get value to write in PLLMR. + ! If value has not been correctly saved, write default value + ! Default config values (assuming on-board 33MHz SYS_CLK) are above. + ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. + ! + ! WARNING: This code assumes the first three words in the nvram_t + ! structure in openbios.h. Changing the beginning of + ! the structure will break this code. + ! + !----------------------------------------------------------------------- + */ + addis r3,0,NVRAM_BASE@h + addi r3,r3,NVRAM_BASE@l + + lwz r4, 0(r3) + addis r5,0,NVRVFY1@h + addi r5,r5,NVRVFY1@l + cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ + bne ..no_pllset + addi r3,r3,4 + lwz r4, 0(r3) + addis r5,0,NVRVFY2@h + addi r5,r5,NVRVFY2@l + cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ + bne ..no_pllset + addi r3,r3,8 /* Skip over conf_size */ + lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ + lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ + rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ + cmpi cr0,0,r5,1 /* See if PLL is locked */ + beq pll_write +..no_pllset: +#endif /* CONFIG_BUBINGA */ + +#ifdef CONFIG_TAIHU + mfdcr r4, CPC0_BOOT + andi. r5, r4, CPC0_BOOT_SEP@l + bne strap_1 /* serial eeprom present */ + addis r5,0,CPLD_REG0_ADDR@h + ori r5,r5,CPLD_REG0_ADDR@l + andi. r5, r5, 0x10 + bne _pci_66mhz +#endif /* CONFIG_TAIHU */ + +#if defined(CONFIG_ZEUS) + mfdcr r4, CPC0_BOOT + andi. r5, r4, CPC0_BOOT_SEP@l + bne strap_1 /* serial eeprom present */ + lis r3,0x0000 + addi r3,r3,0x3030 + lis r4,0x8042 + addi r4,r4,0x223e + b 1f +strap_1: + mfdcr r3, CPC0_PLLMR0 + mfdcr r4, CPC0_PLLMR1 + b 1f +#endif + + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ + ori r3,r3,PLLMR0_DEFAULT@l /* */ + addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ + ori r4,r4,PLLMR1_DEFAULT@l /* */ + +#ifdef CONFIG_TAIHU + b 1f +_pci_66mhz: + addis r3,0,PLLMR0_DEFAULT_PCI66@h + ori r3,r3,PLLMR0_DEFAULT_PCI66@l + addis r4,0,PLLMR1_DEFAULT_PCI66@h + ori r4,r4,PLLMR1_DEFAULT_PCI66@l + b 1f +strap_1: + mfdcr r3, CPC0_PLLMR0 + mfdcr r4, CPC0_PLLMR1 +#endif /* CONFIG_TAIHU */ + +1: + b pll_write /* Write the CPC0_PLLMR with new value */ + +pll_done: + /* + !----------------------------------------------------------------------- + ! Clear Soft Reset Register + ! This is needed to enable PCI if not booting from serial EPROM + !----------------------------------------------------------------------- + */ + addi r3, 0, 0x0 + mtdcr CPC0_SRR, r3 + + addis r3,0,0x0010 + mtctr r3 +pci_wait: + bdnz pci_wait + + blr /* return to main code */ + +/* +!----------------------------------------------------------------------------- +! Function: pll_write +! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation +! That is: +! 1. Pll is first disabled (de-activated by putting in bypass mode) +! 2. PLL is reset +! 3. Clock dividers are set while PLL is held in reset and bypassed +! 4. PLL Reset is cleared +! 5. Wait 100us for PLL to lock +! 6. A core reset is performed +! Input: r3 = Value to write to CPC0_PLLMR0 +! Input: r4 = Value to write to CPC0_PLLMR1 +! Output r3 = none +!----------------------------------------------------------------------------- +*/ + .globl pll_write +pll_write: + mfdcr r5, CPC0_UCR + andis. r5,r5,0xFFFF + ori r5,r5,0x0101 /* Stop the UART clocks */ + mtdcr CPC0_UCR,r5 /* Before changing PLL */ + + mfdcr r5, CPC0_PLLMR1 + rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ + mtdcr CPC0_PLLMR1,r5 + oris r5,r5,0x4000 /* Set PLL Reset */ + mtdcr CPC0_PLLMR1,r5 + + mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ + rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ + oris r5,r5,0x4000 /* Set PLL Reset */ + mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ + rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ + mtdcr CPC0_PLLMR1,r5 + + /* + ! Wait min of 100us for PLL to lock. + ! See CMOS 27E databook for more info. + ! At 200MHz, that means waiting 20,000 instructions + */ + addi r3,0,20000 /* 2000 = 0x4e20 */ + mtctr r3 +pll_wait: + bdnz pll_wait + + oris r5,r5,0x8000 /* Enable PLL */ + mtdcr CPC0_PLLMR1,r5 /* Engage */ + + /* + * Reset CPU to guarantee timings are OK + * Not sure if this is needed... + */ + addis r3,0,0x1000 + mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ + /* execution will continue from the poweron */ + /* vector of 0xfffffffc */ +#endif /* CONFIG_405EP */ + +#if defined(CONFIG_440) +/*----------------------------------------------------------------------------+ +| mttlb3. ++----------------------------------------------------------------------------*/ + function_prolog(mttlb3) + TLBWE(4,3,2) + blr + function_epilog(mttlb3) + +/*----------------------------------------------------------------------------+ +| mftlb3. ++----------------------------------------------------------------------------*/ + function_prolog(mftlb3) + TLBRE(3,3,2) + blr + function_epilog(mftlb3) + +/*----------------------------------------------------------------------------+ +| mttlb2. ++----------------------------------------------------------------------------*/ + function_prolog(mttlb2) + TLBWE(4,3,1) + blr + function_epilog(mttlb2) + +/*----------------------------------------------------------------------------+ +| mftlb2. ++----------------------------------------------------------------------------*/ + function_prolog(mftlb2) + TLBRE(3,3,1) + blr + function_epilog(mftlb2) + +/*----------------------------------------------------------------------------+ +| mttlb1. ++----------------------------------------------------------------------------*/ + function_prolog(mttlb1) + TLBWE(4,3,0) + blr + function_epilog(mttlb1) + +/*----------------------------------------------------------------------------+ +| mftlb1. ++----------------------------------------------------------------------------*/ + function_prolog(mftlb1) + TLBRE(3,3,0) + blr + function_epilog(mftlb1) +#endif /* CONFIG_440 */ + +#if defined(CONFIG_NAND_SPL) +/* + * void nand_boot_relocate(dst, src, bytes) + * + * r3 = Destination address to copy code to (in SDRAM) + * r4 = Source address to copy code from + * r5 = size to copy in bytes + */ +nand_boot_relocate: + mr r6,r3 + mr r7,r4 + mflr r8 + + /* + * Copy SPL from icache into SDRAM + */ + subi r3,r3,4 + subi r4,r4,4 + srwi r5,r5,2 + mtctr r5 +..spl_loop: + lwzu r0,4(r4) + stwu r0,4(r3) + bdnz ..spl_loop + + /* + * Calculate "corrected" link register, so that we "continue" + * in execution in destination range + */ + sub r3,r7,r6 /* r3 = src - dst */ + sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ + mtlr r8 + blr + +nand_boot_common: + /* + * First initialize SDRAM. It has to be available *before* calling + * nand_boot(). + */ + lis r3,CONFIG_SYS_SDRAM_BASE@h + ori r3,r3,CONFIG_SYS_SDRAM_BASE@l + bl initdram + + /* + * Now copy the 4k SPL code into SDRAM and continue execution + * from there. + */ + lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h + ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l + lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h + ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l + lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h + ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l + bl nand_boot_relocate + + /* + * We're running from SDRAM now!!! + * + * It is necessary for 4xx systems to relocate from running at + * the original location (0xfffffxxx) to somewhere else (SDRAM + * preferably). This is because CS0 needs to be reconfigured for + * NAND access. And we can't reconfigure this CS when currently + * "running" from it. + */ + + /* + * Finally call nand_boot() to load main NAND U-Boot image from + * NAND and jump to it. + */ + bl nand_boot /* will not return */ +#endif /* CONFIG_NAND_SPL */ diff --git a/cpu/ppc4xx/tlb.c b/arch/ppc/cpu/ppc4xx/tlb.c similarity index 100% rename from cpu/ppc4xx/tlb.c rename to arch/ppc/cpu/ppc4xx/tlb.c diff --git a/cpu/ppc4xx/traps.c b/arch/ppc/cpu/ppc4xx/traps.c similarity index 100% rename from cpu/ppc4xx/traps.c rename to arch/ppc/cpu/ppc4xx/traps.c diff --git a/arch/ppc/cpu/ppc4xx/u-boot.lds b/arch/ppc/cpu/ppc4xx/u-boot.lds new file mode 100644 index 0000000000..3704d8a695 --- /dev/null +++ b/arch/ppc/cpu/ppc4xx/u-boot.lds @@ -0,0 +1,169 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "config.h" /* CONFIG_BOARDDIR */ + +#ifndef RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + +#ifdef CONFIG_440 + .bootpg RESET_VECTOR_ADDRESS - 0xffc : + { + arch/ppc/cpu/ppc4xx/start.o (.bootpg) + + /* + * PPC440 board need a board specific object with the + * TLB definitions. This needs to get included right after + * start.o, since the first shadow TLB only covers 4k + * of address space. + */ + CONFIG_BOARDDIR/init.o (.bootpg) + } :text = 0xffff +#endif + + .resetvec RESET_VECTOR_ADDRESS : + { + *(.resetvec) + } :text = 0xffff + + . = RESET_VECTOR_ADDRESS + 0x4; + + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. Note that + * this is a temporary fix. Code to dynamically the fixup the bss + * location will be added in the future. When the bss relocation + * fixup code is present this workaround should be removed. + */ +#if (RESET_VECTOR_ADDRESS == 0xfffffffc) + . |= 0x10; +#endif + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/ppc4xx/uic.c b/arch/ppc/cpu/ppc4xx/uic.c similarity index 100% rename from cpu/ppc4xx/uic.c rename to arch/ppc/cpu/ppc4xx/uic.c diff --git a/cpu/ppc4xx/usb.c b/arch/ppc/cpu/ppc4xx/usb.c similarity index 100% rename from cpu/ppc4xx/usb.c rename to arch/ppc/cpu/ppc4xx/usb.c diff --git a/cpu/ppc4xx/usb_ohci.c b/arch/ppc/cpu/ppc4xx/usb_ohci.c similarity index 100% rename from cpu/ppc4xx/usb_ohci.c rename to arch/ppc/cpu/ppc4xx/usb_ohci.c diff --git a/cpu/ppc4xx/usb_ohci.h b/arch/ppc/cpu/ppc4xx/usb_ohci.h similarity index 100% rename from cpu/ppc4xx/usb_ohci.h rename to arch/ppc/cpu/ppc4xx/usb_ohci.h diff --git a/cpu/ppc4xx/usbdev.c b/arch/ppc/cpu/ppc4xx/usbdev.c similarity index 100% rename from cpu/ppc4xx/usbdev.c rename to arch/ppc/cpu/ppc4xx/usbdev.c diff --git a/cpu/ppc4xx/usbdev.h b/arch/ppc/cpu/ppc4xx/usbdev.h similarity index 100% rename from cpu/ppc4xx/usbdev.h rename to arch/ppc/cpu/ppc4xx/usbdev.h diff --git a/cpu/ppc4xx/xilinx_irq.c b/arch/ppc/cpu/ppc4xx/xilinx_irq.c similarity index 100% rename from cpu/ppc4xx/xilinx_irq.c rename to arch/ppc/cpu/ppc4xx/xilinx_irq.c diff --git a/include/asm-ppc/4xx_pci.h b/arch/ppc/include/asm/4xx_pci.h similarity index 100% rename from include/asm-ppc/4xx_pci.h rename to arch/ppc/include/asm/4xx_pci.h diff --git a/include/asm-ppc/4xx_pcie.h b/arch/ppc/include/asm/4xx_pcie.h similarity index 100% rename from include/asm-ppc/4xx_pcie.h rename to arch/ppc/include/asm/4xx_pcie.h diff --git a/include/asm-ppc/5xx_immap.h b/arch/ppc/include/asm/5xx_immap.h similarity index 100% rename from include/asm-ppc/5xx_immap.h rename to arch/ppc/include/asm/5xx_immap.h diff --git a/include/asm-ppc/8xx_immap.h b/arch/ppc/include/asm/8xx_immap.h similarity index 100% rename from include/asm-ppc/8xx_immap.h rename to arch/ppc/include/asm/8xx_immap.h diff --git a/include/asm-ppc/atomic.h b/arch/ppc/include/asm/atomic.h similarity index 100% rename from include/asm-ppc/atomic.h rename to arch/ppc/include/asm/atomic.h diff --git a/include/asm-ppc/bitops.h b/arch/ppc/include/asm/bitops.h similarity index 100% rename from include/asm-ppc/bitops.h rename to arch/ppc/include/asm/bitops.h diff --git a/include/asm-ppc/byteorder.h b/arch/ppc/include/asm/byteorder.h similarity index 100% rename from include/asm-ppc/byteorder.h rename to arch/ppc/include/asm/byteorder.h diff --git a/include/asm-ppc/cache.h b/arch/ppc/include/asm/cache.h similarity index 100% rename from include/asm-ppc/cache.h rename to arch/ppc/include/asm/cache.h diff --git a/arch/ppc/include/asm/config.h b/arch/ppc/include/asm/config.h new file mode 100644 index 0000000000..fc3facb307 --- /dev/null +++ b/arch/ppc/include/asm/config.h @@ -0,0 +1,79 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#define CONFIG_LMB + +#ifndef CONFIG_MAX_MEM_MAPPED +#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#else +#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#endif +#endif + +/* Check if boards need to enable FSL DMA engine for SDRAM init */ +#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) +#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ + ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ + !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) +#define CONFIG_FSL_DMA +#endif +#endif + +#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ + defined(CONFIG_P2020) || defined(CONFIG_MPC8641) +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_P4080) +#define CONFIG_MAX_CPUS 8 +#else +#define CONFIG_MAX_CPUS 1 +#endif + +/* + * Provide a default boot page translation virtual address that lines up with + * Freescale's default e500 reset page. + */ +#if (defined(CONFIG_E500) && defined(CONFIG_MP)) +#ifndef CONFIG_BPTR_VIRT_ADDR +#define CONFIG_BPTR_VIRT_ADDR 0xfffff000 +#endif +#endif + +/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ +#if defined(CONFIG_TSEC_ENET) && \ + (defined(CONFIG_P1020) || defined(CONFIG_P1011)) +#define CONFIG_TSECV2 +#endif + +/* Number of TLB CAM entries we have on FSL Book-E chips */ +#if defined(CONFIG_E500MC) +#define CONFIG_SYS_NUM_TLBCAMS 64 +#elif defined(CONFIG_E500) +#define CONFIG_SYS_NUM_TLBCAMS 16 +#endif + +/* Relocation to SDRAM works on all PPC boards */ +#define CONFIG_RELOC_FIXUP_WORKS + +#endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/cpm_8260.h b/arch/ppc/include/asm/cpm_8260.h similarity index 100% rename from include/asm-ppc/cpm_8260.h rename to arch/ppc/include/asm/cpm_8260.h diff --git a/include/asm-ppc/cpm_85xx.h b/arch/ppc/include/asm/cpm_85xx.h similarity index 100% rename from include/asm-ppc/cpm_85xx.h rename to arch/ppc/include/asm/cpm_85xx.h diff --git a/include/asm-ppc/e300.h b/arch/ppc/include/asm/e300.h similarity index 100% rename from include/asm-ppc/e300.h rename to arch/ppc/include/asm/e300.h diff --git a/include/asm-sh/errno.h b/arch/ppc/include/asm/errno.h similarity index 100% rename from include/asm-sh/errno.h rename to arch/ppc/include/asm/errno.h diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/arch/ppc/include/asm/fsl_ddr_dimm_params.h similarity index 100% rename from include/asm-ppc/fsl_ddr_dimm_params.h rename to arch/ppc/include/asm/fsl_ddr_dimm_params.h diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/arch/ppc/include/asm/fsl_ddr_sdram.h similarity index 100% rename from include/asm-ppc/fsl_ddr_sdram.h rename to arch/ppc/include/asm/fsl_ddr_sdram.h diff --git a/include/asm-ppc/fsl_dma.h b/arch/ppc/include/asm/fsl_dma.h similarity index 100% rename from include/asm-ppc/fsl_dma.h rename to arch/ppc/include/asm/fsl_dma.h diff --git a/include/asm-ppc/fsl_i2c.h b/arch/ppc/include/asm/fsl_i2c.h similarity index 100% rename from include/asm-ppc/fsl_i2c.h rename to arch/ppc/include/asm/fsl_i2c.h diff --git a/include/asm-ppc/fsl_law.h b/arch/ppc/include/asm/fsl_law.h similarity index 100% rename from include/asm-ppc/fsl_law.h rename to arch/ppc/include/asm/fsl_law.h diff --git a/include/asm-ppc/fsl_lbc.h b/arch/ppc/include/asm/fsl_lbc.h similarity index 100% rename from include/asm-ppc/fsl_lbc.h rename to arch/ppc/include/asm/fsl_lbc.h diff --git a/include/asm-ppc/fsl_pci.h b/arch/ppc/include/asm/fsl_pci.h similarity index 100% rename from include/asm-ppc/fsl_pci.h rename to arch/ppc/include/asm/fsl_pci.h diff --git a/include/asm-ppc/fsl_serdes.h b/arch/ppc/include/asm/fsl_serdes.h similarity index 100% rename from include/asm-ppc/fsl_serdes.h rename to arch/ppc/include/asm/fsl_serdes.h diff --git a/include/asm-ppc/global_data.h b/arch/ppc/include/asm/global_data.h similarity index 100% rename from include/asm-ppc/global_data.h rename to arch/ppc/include/asm/global_data.h diff --git a/include/asm-ppc/gpio.h b/arch/ppc/include/asm/gpio.h similarity index 100% rename from include/asm-ppc/gpio.h rename to arch/ppc/include/asm/gpio.h diff --git a/include/asm-ppc/immap_512x.h b/arch/ppc/include/asm/immap_512x.h similarity index 100% rename from include/asm-ppc/immap_512x.h rename to arch/ppc/include/asm/immap_512x.h diff --git a/include/asm-ppc/immap_8220.h b/arch/ppc/include/asm/immap_8220.h similarity index 100% rename from include/asm-ppc/immap_8220.h rename to arch/ppc/include/asm/immap_8220.h diff --git a/include/asm-ppc/immap_8260.h b/arch/ppc/include/asm/immap_8260.h similarity index 100% rename from include/asm-ppc/immap_8260.h rename to arch/ppc/include/asm/immap_8260.h diff --git a/include/asm-ppc/immap_83xx.h b/arch/ppc/include/asm/immap_83xx.h similarity index 100% rename from include/asm-ppc/immap_83xx.h rename to arch/ppc/include/asm/immap_83xx.h diff --git a/include/asm-ppc/immap_85xx.h b/arch/ppc/include/asm/immap_85xx.h similarity index 100% rename from include/asm-ppc/immap_85xx.h rename to arch/ppc/include/asm/immap_85xx.h diff --git a/include/asm-ppc/immap_86xx.h b/arch/ppc/include/asm/immap_86xx.h similarity index 100% rename from include/asm-ppc/immap_86xx.h rename to arch/ppc/include/asm/immap_86xx.h diff --git a/include/asm-ppc/immap_qe.h b/arch/ppc/include/asm/immap_qe.h similarity index 100% rename from include/asm-ppc/immap_qe.h rename to arch/ppc/include/asm/immap_qe.h diff --git a/include/asm-ppc/interrupt.h b/arch/ppc/include/asm/interrupt.h similarity index 100% rename from include/asm-ppc/interrupt.h rename to arch/ppc/include/asm/interrupt.h diff --git a/include/asm-ppc/io.h b/arch/ppc/include/asm/io.h similarity index 100% rename from include/asm-ppc/io.h rename to arch/ppc/include/asm/io.h diff --git a/include/asm-ppc/iopin_8260.h b/arch/ppc/include/asm/iopin_8260.h similarity index 100% rename from include/asm-ppc/iopin_8260.h rename to arch/ppc/include/asm/iopin_8260.h diff --git a/include/asm-ppc/iopin_85xx.h b/arch/ppc/include/asm/iopin_85xx.h similarity index 100% rename from include/asm-ppc/iopin_85xx.h rename to arch/ppc/include/asm/iopin_85xx.h diff --git a/include/asm-ppc/iopin_8xx.h b/arch/ppc/include/asm/iopin_8xx.h similarity index 100% rename from include/asm-ppc/iopin_8xx.h rename to arch/ppc/include/asm/iopin_8xx.h diff --git a/include/asm-ppc/m8260_pci.h b/arch/ppc/include/asm/m8260_pci.h similarity index 100% rename from include/asm-ppc/m8260_pci.h rename to arch/ppc/include/asm/m8260_pci.h diff --git a/include/asm-ppc/mc146818rtc.h b/arch/ppc/include/asm/mc146818rtc.h similarity index 100% rename from include/asm-ppc/mc146818rtc.h rename to arch/ppc/include/asm/mc146818rtc.h diff --git a/arch/ppc/include/asm/mmu.h b/arch/ppc/include/asm/mmu.h new file mode 100644 index 0000000000..ce7f081005 --- /dev/null +++ b/arch/ppc/include/asm/mmu.h @@ -0,0 +1,763 @@ +/* + * PowerPC memory management structures + */ + +#ifndef _PPC_MMU_H_ +#define _PPC_MMU_H_ + +#include + +#ifndef __ASSEMBLY__ +/* Hardware Page Table Entry */ +typedef struct _PTE { +#ifdef CONFIG_PPC64BRIDGE + unsigned long long vsid:52; + unsigned long api:5; + unsigned long :5; + unsigned long h:1; + unsigned long v:1; + unsigned long long rpn:52; +#else /* CONFIG_PPC64BRIDGE */ + unsigned long v:1; /* Entry is valid */ + unsigned long vsid:24; /* Virtual segment identifier */ + unsigned long h:1; /* Hash algorithm indicator */ + unsigned long api:6; /* Abbreviated page index */ + unsigned long rpn:20; /* Real (physical) page number */ +#endif /* CONFIG_PPC64BRIDGE */ + unsigned long :3; /* Unused */ + unsigned long r:1; /* Referenced */ + unsigned long c:1; /* Changed */ + unsigned long w:1; /* Write-thru cache mode */ + unsigned long i:1; /* Cache inhibited */ + unsigned long m:1; /* Memory coherence */ + unsigned long g:1; /* Guarded */ + unsigned long :1; /* Unused */ + unsigned long pp:2; /* Page protection */ +} PTE; + +/* Values for PP (assumes Ks=0, Kp=1) */ +#define PP_RWXX 0 /* Supervisor read/write, User none */ +#define PP_RWRX 1 /* Supervisor read/write, User read */ +#define PP_RWRW 2 /* Supervisor read/write, User read/write */ +#define PP_RXRX 3 /* Supervisor read, User read */ + +/* Segment Register */ +typedef struct _SEGREG { + unsigned long t:1; /* Normal or I/O type */ + unsigned long ks:1; /* Supervisor 'key' (normally 0) */ + unsigned long kp:1; /* User 'key' (normally 1) */ + unsigned long n:1; /* No-execute */ + unsigned long :4; /* Unused */ + unsigned long vsid:24; /* Virtual Segment Identifier */ +} SEGREG; + +/* Block Address Translation (BAT) Registers */ +typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ + unsigned long bepi:15; /* Effective page index (virtual address) */ + unsigned long :8; /* unused */ + unsigned long w:1; + unsigned long i:1; /* Cache inhibit */ + unsigned long m:1; /* Memory coherence */ + unsigned long ks:1; /* Supervisor key (normally 0) */ + unsigned long kp:1; /* User key (normally 1) */ + unsigned long pp:2; /* Page access protections */ +} P601_BATU; + +typedef struct _BATU { /* Upper part of BAT (all except 601) */ +#ifdef CONFIG_PPC64BRIDGE + unsigned long long bepi:47; +#else /* CONFIG_PPC64BRIDGE */ + unsigned long bepi:15; /* Effective page index (virtual address) */ +#endif /* CONFIG_PPC64BRIDGE */ + unsigned long :4; /* Unused */ + unsigned long bl:11; /* Block size mask */ + unsigned long vs:1; /* Supervisor valid */ + unsigned long vp:1; /* User valid */ +} BATU; + +typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ + unsigned long brpn:15; /* Real page index (physical address) */ + unsigned long :10; /* Unused */ + unsigned long v:1; /* Valid bit */ + unsigned long bl:6; /* Block size mask */ +} P601_BATL; + +typedef struct _BATL { /* Lower part of BAT (all except 601) */ +#ifdef CONFIG_PPC64BRIDGE + unsigned long long brpn:47; +#else /* CONFIG_PPC64BRIDGE */ + unsigned long brpn:15; /* Real page index (physical address) */ +#endif /* CONFIG_PPC64BRIDGE */ + unsigned long :10; /* Unused */ + unsigned long w:1; /* Write-thru cache */ + unsigned long i:1; /* Cache inhibit */ + unsigned long m:1; /* Memory coherence */ + unsigned long g:1; /* Guarded (MBZ in IBAT) */ + unsigned long :1; /* Unused */ + unsigned long pp:2; /* Page access protections */ +} BATL; + +typedef struct _BAT { + BATU batu; /* Upper register */ + BATL batl; /* Lower register */ +} BAT; + +typedef struct _P601_BAT { + P601_BATU batu; /* Upper register */ + P601_BATL batl; /* Lower register */ +} P601_BAT; + +/* + * Simulated two-level MMU. This structure is used by the kernel + * to keep track of MMU mappings and is used to update/maintain + * the hardware HASH table which is really a cache of mappings. + * + * The simulated structures mimic the hardware available on other + * platforms, notably the 80x86 and 680x0. + */ + +typedef struct _pte { + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ +} pte; + +#define PD_SHIFT (10+12) /* Page directory */ +#define PD_MASK 0x02FF +#define PT_SHIFT (12) /* Page Table */ +#define PT_MASK 0x02FF +#define PG_SHIFT (12) /* Page Entry */ + + +/* MMU context */ + +typedef struct _MMU_context { + SEGREG segs[16]; /* Segment registers */ + pte **pmap; /* Two-level page-map structure */ +} MMU_context; + +extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ +extern void _tlbia(void); /* invalidate all TLB entries */ + +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif + +typedef enum { + IBAT0 = 0, IBAT1, IBAT2, IBAT3, + DBAT0, DBAT1, DBAT2, DBAT3, +#ifdef CONFIG_HIGH_BATS + IBAT4, IBAT5, IBAT6, IBAT7, + DBAT4, DBAT5, DBAT6, DBAT7 +#endif +} ppc_bat_t; + +extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); +extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); +extern void print_bats(void); + +#endif /* __ASSEMBLY__ */ + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +/* BAT Block size values */ +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +/* Block lengths for processors that support extended block length */ +#ifdef HID0_XBSEN +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc +#define BATU_BL_MAX BATU_BL_4G +#else +#define BATU_BL_MAX BATU_BL_256M +#endif + +/* BAT Access Protection */ +#define BPP_XX 0x00 /* No access */ +#define BPP_RX 0x01 /* Read only */ +#define BPP_RW 0x02 /* Read/write */ + +/* Macros to get values from BATs, once data is in the BAT register format */ +#define BATU_VALID(x) (x & 0x3) +#define BATU_VADDR(x) (x & 0xfffe0000) +#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ + | ((x & 0x0e00ULL) << 24) \ + | ((x & 0x04ULL) << 30))) +#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17)) + +/* bytes into BATU_BL */ +#define TO_BATU_BL(x) \ + (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4) + +/* Used to set up SDR1 register */ +#define HASH_TABLE_SIZE_64K 0x00010000 +#define HASH_TABLE_SIZE_128K 0x00020000 +#define HASH_TABLE_SIZE_256K 0x00040000 +#define HASH_TABLE_SIZE_512K 0x00080000 +#define HASH_TABLE_SIZE_1M 0x00100000 +#define HASH_TABLE_SIZE_2M 0x00200000 +#define HASH_TABLE_SIZE_4M 0x00400000 +#define HASH_TABLE_MASK_64K 0x000 +#define HASH_TABLE_MASK_128K 0x001 +#define HASH_TABLE_MASK_256K 0x003 +#define HASH_TABLE_MASK_512K 0x007 +#define HASH_TABLE_MASK_1M 0x00F +#define HASH_TABLE_MASK_2M 0x01F +#define HASH_TABLE_MASK_4M 0x03F + +/* Control/status registers for the MPC8xx. + * A write operation to these registers causes serialized access. + * During software tablewalk, the registers used perform mask/shift-add + * operations when written/read. A TLB entry is created when the Mx_RPN + * is written, and the contents of several registers are used to + * create the entry. + */ +#define MI_CTR 784 /* Instruction TLB control register */ +#define MI_GPM 0x80000000 /* Set domain manager mode */ +#define MI_PPM 0x40000000 /* Set subpage protection */ +#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ +#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ +#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ +#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ +#define MI_RESETVAL 0x00000000 /* Value of register at reset */ + +/* These are the Ks and Kp from the PowerPC books. For proper operation, + * Ks = 0, Kp = 1. + */ +#define MI_AP 786 +#define MI_Ks 0x80000000 /* Should not be set */ +#define MI_Kp 0x40000000 /* Should always be set */ + +/* The effective page number register. When read, contains the information + * about the last instruction TLB miss. When MI_RPN is written, bits in + * this register are used to create the TLB entry. + */ +#define MI_EPN 787 +#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ +#define MI_EVALID 0x00000200 /* Entry is valid */ +#define MI_ASIDMASK 0x0000000f /* ASID match value */ + /* Reset value is undefined */ + +/* A "level 1" or "segment" or whatever you want to call it register. + * For the instruction TLB, it contains bits that get loaded into the + * TLB entry when the MI_RPN is written. + */ +#define MI_TWC 789 +#define MI_APG 0x000001e0 /* Access protection group (0) */ +#define MI_GUARDED 0x00000010 /* Guarded storage */ +#define MI_PSMASK 0x0000000c /* Mask of page size bits */ +#define MI_PS8MEG 0x0000000c /* 8M page size */ +#define MI_PS512K 0x00000004 /* 512K page size */ +#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ +#define MI_SVALID 0x00000001 /* Segment entry is valid */ + /* Reset value is undefined */ + +/* Real page number. Defined by the pte. Writing this register + * causes a TLB entry to be created for the instruction TLB, using + * additional information from the MI_EPN, and MI_TWC registers. + */ +#define MI_RPN 790 + +/* Define an RPN value for mapping kernel memory to large virtual + * pages for boot initialization. This has real page number of 0, + * large page size, shared page, cache enabled, and valid. + * Also mark all subpages valid and write access. + */ +#define MI_BOOTINIT 0x000001fd + +#define MD_CTR 792 /* Data TLB control register */ +#define MD_GPM 0x80000000 /* Set domain manager mode */ +#define MD_PPM 0x40000000 /* Set subpage protection */ +#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ +#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ +#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ +#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ +#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ +#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ +#define MD_RESETVAL 0x04000000 /* Value of register at reset */ + +#define M_CASID 793 /* Address space ID (context) to match */ +#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ + + +/* These are the Ks and Kp from the PowerPC books. For proper operation, + * Ks = 0, Kp = 1. + */ +#define MD_AP 794 +#define MD_Ks 0x80000000 /* Should not be set */ +#define MD_Kp 0x40000000 /* Should always be set */ + +/* The effective page number register. When read, contains the information + * about the last instruction TLB miss. When MD_RPN is written, bits in + * this register are used to create the TLB entry. + */ +#define MD_EPN 795 +#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ +#define MD_EVALID 0x00000200 /* Entry is valid */ +#define MD_ASIDMASK 0x0000000f /* ASID match value */ + /* Reset value is undefined */ + +/* The pointer to the base address of the first level page table. + * During a software tablewalk, reading this register provides the address + * of the entry associated with MD_EPN. + */ +#define M_TWB 796 +#define M_L1TB 0xfffff000 /* Level 1 table base address */ +#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ + /* Reset value is undefined */ + +/* A "level 1" or "segment" or whatever you want to call it register. + * For the data TLB, it contains bits that get loaded into the TLB entry + * when the MD_RPN is written. It is also provides the hardware assist + * for finding the PTE address during software tablewalk. + */ +#define MD_TWC 797 +#define MD_L2TB 0xfffff000 /* Level 2 table base address */ +#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ +#define MD_APG 0x000001e0 /* Access protection group (0) */ +#define MD_GUARDED 0x00000010 /* Guarded storage */ +#define MD_PSMASK 0x0000000c /* Mask of page size bits */ +#define MD_PS8MEG 0x0000000c /* 8M page size */ +#define MD_PS512K 0x00000004 /* 512K page size */ +#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ +#define MD_WT 0x00000002 /* Use writethrough page attribute */ +#define MD_SVALID 0x00000001 /* Segment entry is valid */ + /* Reset value is undefined */ + + +/* Real page number. Defined by the pte. Writing this register + * causes a TLB entry to be created for the data TLB, using + * additional information from the MD_EPN, and MD_TWC registers. + */ +#define MD_RPN 798 + +/* This is a temporary storage register that could be used to save + * a processor working register during a tablewalk. + */ +#define M_TW 799 + +/* + * At present, all PowerPC 400-class processors share a similar TLB + * architecture. The instruction and data sides share a unified, + * 64-entry, fully-associative TLB which is maintained totally under + * software control. In addition, the instruction side has a + * hardware-managed, 4-entry, fully- associative TLB which serves as a + * first level to the shared TLB. These two TLBs are known as the UTLB + * and ITLB, respectively. + */ + +#define PPC4XX_TLB_SIZE 64 + +/* + * TLB entries are defined by a "high" tag portion and a "low" data + * portion. On all architectures, the data portion is 32-bits. + * + * TLB entries are managed entirely under software control by reading, + * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx + * instructions. + */ + +/* + * FSL Book-E support + */ + +#define MAS0_TLBSEL_MSK 0x30000000 +#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) +#define MAS0_ESEL_MSK 0x0FFF0000 +#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) +#define MAS0_NV(x) ((x) & 0x00000FFF) + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) +#define MAS1_TS 0x00001000 +#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) + +#define MAS2_EPN 0xFFFFF000 +#define MAS2_X0 0x00000040 +#define MAS2_X1 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 + +#define MAS3_RPN 0xFFFFF000 +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 + +#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) +#define MAS4_TIDDSEL 0x000F0000 +#define MAS4_TSIZED(x) MAS1_TSIZE(x) +#define MAS4_X0D 0x00000040 +#define MAS4_X1D 0x00000020 +#define MAS4_WD 0x00000010 +#define MAS4_ID 0x00000008 +#define MAS4_MD 0x00000004 +#define MAS4_GD 0x00000002 +#define MAS4_ED 0x00000001 + +#define MAS6_SPID0 0x3FFF0000 +#define MAS6_SPID1 0x00007FFE +#define MAS6_SAS 0x00000001 +#define MAS6_SPID MAS6_SPID0 + +#define MAS7_RPN 0xFFFFFFFF + +#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \ + (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) +#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \ + ((((v) << 31) & MAS1_VALID) |\ + (((iprot) << 30) & MAS1_IPROT) |\ + (MAS1_TID(tid)) |\ + (((ts) << 12) & MAS1_TS) |\ + (MAS1_TSIZE(tsize))) +#define FSL_BOOKE_MAS2(epn, wimge) \ + (((epn) & MAS3_RPN) | (wimge)) +#define FSL_BOOKE_MAS3(rpn, user, perms) \ + (((rpn) & MAS3_RPN) | (user) | (perms)) +#define FSL_BOOKE_MAS7(rpn) \ + (((u64)(rpn)) >> 32) + +#define BOOKE_PAGESZ_1K 0 +#define BOOKE_PAGESZ_4K 1 +#define BOOKE_PAGESZ_16K 2 +#define BOOKE_PAGESZ_64K 3 +#define BOOKE_PAGESZ_256K 4 +#define BOOKE_PAGESZ_1M 5 +#define BOOKE_PAGESZ_4M 6 +#define BOOKE_PAGESZ_16M 7 +#define BOOKE_PAGESZ_64M 8 +#define BOOKE_PAGESZ_256M 9 +#define BOOKE_PAGESZ_1G 10 +#define BOOKE_PAGESZ_4G 11 +#define BOOKE_PAGESZ_16GB 12 +#define BOOKE_PAGESZ_64GB 13 +#define BOOKE_PAGESZ_256GB 14 +#define BOOKE_PAGESZ_1TB 15 + +#ifdef CONFIG_E500 +#ifndef __ASSEMBLY__ +extern void set_tlb(u8 tlb, u32 epn, u64 rpn, + u8 perms, u8 wimge, + u8 ts, u8 esel, u8 tsize, u8 iprot); +extern void disable_tlb(u8 esel); +extern void invalidate_tlb(u8 tlb); +extern void init_tlbs(void); +extern int find_tlb_idx(void *addr, u8 tlbsel); +extern void init_used_tlb_cams(void); +extern int find_free_tlbcam(void); + +extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); + +extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); + +#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ + { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ + .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ + .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ + .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ + .mas7 = FSL_BOOKE_MAS7(_rpn), } + +struct fsl_e_tlb_entry { + u32 mas0; + u32 mas1; + u32 mas2; + u32 mas3; + u32 mas7; +}; + +extern struct fsl_e_tlb_entry tlb_table[]; +extern int num_tlb_entries; +#endif +#endif + +#ifdef CONFIG_E300 +#define LAWAR_EN 0x80000000 +#define LAWAR_SIZE 0x0000003F + +#define LAWAR_TRGT_IF_PCI 0x00000000 +#define LAWAR_TRGT_IF_PCI1 0x00000000 +#define LAWAR_TRGT_IF_PCIX 0x00000000 +#define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_PCIE1 0x00200000 +#define LAWAR_TRGT_IF_PCIE2 0x00100000 +#define LAWAR_TRGT_IF_PCIE3 0x00300000 +#define LAWAR_TRGT_IF_LBC 0x00400000 +#define LAWAR_TRGT_IF_CCSR 0x00800000 +#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 +#define LAWAR_TRGT_IF_RIO 0x00c00000 +#define LAWAR_TRGT_IF_DDR 0x00f00000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 + +#define LAWAR_SIZE_BASE 0xa +#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) +#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2) +#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3) +#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4) +#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5) +#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6) +#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7) +#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8) +#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9) +#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10) +#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11) +#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12) +#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13) +#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14) +#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15) +#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16) +#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17) +#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) +#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) +#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) +#endif + +#ifdef CONFIG_440 +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID )) +#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn)) +#define TLB2(a) ((a) & 0x00000fbf) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ;\ +0: mflr r0 ;\ + mtlr r1 ;\ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + +/*----------------------------------------------------------------------------+ +| TLB specific defines. ++----------------------------------------------------------------------------*/ +#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL +#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL +#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL +#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL +#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL +#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL +#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL +#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL +#define TLB_256MB_SIZE 0x10000000 +#define TLB_16MB_SIZE 0x01000000 +#define TLB_1MB_SIZE 0x00100000 +#define TLB_256KB_SIZE 0x00040000 +#define TLB_64KB_SIZE 0x00010000 +#define TLB_16KB_SIZE 0x00004000 +#define TLB_4KB_SIZE 0x00001000 +#define TLB_1KB_SIZE 0x00000400 + +#define TLB_WORD0_EPN_MASK 0xFFFFFC00 +#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) +#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) +#define TLB_WORD0_V_MASK 0x00000200 +#define TLB_WORD0_V_ENABLE 0x00000200 +#define TLB_WORD0_V_DISABLE 0x00000000 +#define TLB_WORD0_TS_MASK 0x00000100 +#define TLB_WORD0_TS_1 0x00000100 +#define TLB_WORD0_TS_0 0x00000000 +#define TLB_WORD0_SIZE_MASK 0x000000F0 +#define TLB_WORD0_SIZE_1KB 0x00000000 +#define TLB_WORD0_SIZE_4KB 0x00000010 +#define TLB_WORD0_SIZE_16KB 0x00000020 +#define TLB_WORD0_SIZE_64KB 0x00000030 +#define TLB_WORD0_SIZE_256KB 0x00000040 +#define TLB_WORD0_SIZE_1MB 0x00000050 +#define TLB_WORD0_SIZE_16MB 0x00000070 +#define TLB_WORD0_SIZE_256MB 0x00000090 +#define TLB_WORD0_TPAR_MASK 0x0000000F +#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) +#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) + +#define TLB_WORD1_RPN_MASK 0xFFFFFC00 +#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) +#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) +#define TLB_WORD1_PAR1_MASK 0x00000300 +#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) +#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03) +#define TLB_WORD1_PAR1_0 0x00000000 +#define TLB_WORD1_PAR1_1 0x00000100 +#define TLB_WORD1_PAR1_2 0x00000200 +#define TLB_WORD1_PAR1_3 0x00000300 +#define TLB_WORD1_ERPN_MASK 0x0000000F +#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) +#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) + +#define TLB_WORD2_PAR2_MASK 0xC0000000 +#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30) +#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03) +#define TLB_WORD2_PAR2_0 0x00000000 +#define TLB_WORD2_PAR2_1 0x40000000 +#define TLB_WORD2_PAR2_2 0x80000000 +#define TLB_WORD2_PAR2_3 0xC0000000 +#define TLB_WORD2_U0_MASK 0x00008000 +#define TLB_WORD2_U0_ENABLE 0x00008000 +#define TLB_WORD2_U0_DISABLE 0x00000000 +#define TLB_WORD2_U1_MASK 0x00004000 +#define TLB_WORD2_U1_ENABLE 0x00004000 +#define TLB_WORD2_U1_DISABLE 0x00000000 +#define TLB_WORD2_U2_MASK 0x00002000 +#define TLB_WORD2_U2_ENABLE 0x00002000 +#define TLB_WORD2_U2_DISABLE 0x00000000 +#define TLB_WORD2_U3_MASK 0x00001000 +#define TLB_WORD2_U3_ENABLE 0x00001000 +#define TLB_WORD2_U3_DISABLE 0x00000000 +#define TLB_WORD2_W_MASK 0x00000800 +#define TLB_WORD2_W_ENABLE 0x00000800 +#define TLB_WORD2_W_DISABLE 0x00000000 +#define TLB_WORD2_I_MASK 0x00000400 +#define TLB_WORD2_I_ENABLE 0x00000400 +#define TLB_WORD2_I_DISABLE 0x00000000 +#define TLB_WORD2_M_MASK 0x00000200 +#define TLB_WORD2_M_ENABLE 0x00000200 +#define TLB_WORD2_M_DISABLE 0x00000000 +#define TLB_WORD2_G_MASK 0x00000100 +#define TLB_WORD2_G_ENABLE 0x00000100 +#define TLB_WORD2_G_DISABLE 0x00000000 +#define TLB_WORD2_E_MASK 0x00000080 +#define TLB_WORD2_E_ENABLE 0x00000080 +#define TLB_WORD2_E_DISABLE 0x00000000 +#define TLB_WORD2_UX_MASK 0x00000020 +#define TLB_WORD2_UX_ENABLE 0x00000020 +#define TLB_WORD2_UX_DISABLE 0x00000000 +#define TLB_WORD2_UW_MASK 0x00000010 +#define TLB_WORD2_UW_ENABLE 0x00000010 +#define TLB_WORD2_UW_DISABLE 0x00000000 +#define TLB_WORD2_UR_MASK 0x00000008 +#define TLB_WORD2_UR_ENABLE 0x00000008 +#define TLB_WORD2_UR_DISABLE 0x00000000 +#define TLB_WORD2_SX_MASK 0x00000004 +#define TLB_WORD2_SX_ENABLE 0x00000004 +#define TLB_WORD2_SX_DISABLE 0x00000000 +#define TLB_WORD2_SW_MASK 0x00000002 +#define TLB_WORD2_SW_ENABLE 0x00000002 +#define TLB_WORD2_SW_DISABLE 0x00000000 +#define TLB_WORD2_SR_MASK 0x00000001 +#define TLB_WORD2_SR_ENABLE 0x00000001 +#define TLB_WORD2_SR_DISABLE 0x00000000 + +/*----------------------------------------------------------------------------+ +| Following instructions are not available in Book E mode of the GNU assembler. ++----------------------------------------------------------------------------*/ +#define DCCCI(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(454<<1) + +#define ICCCI(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(966<<1) + +#define DCREAD(rt,ra,rb) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(rb<<11)|(486<<1) + +#define ICREAD(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(998<<1) + +#define TLBSX(rt,ra,rb) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) + +#define TLBWE(rs,ra,ws) .long 0x7c000000|\ + (rs<<21)|(ra<<16)|(ws<<11)|(978<<1) + +#define TLBRE(rt,ra,ws) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) + +#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\ + (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) + +#define MSYNC .long 0x7c000000|\ + (598<<1) + +#define MBAR_INST .long 0x7c000000|\ + (854<<1) + +#ifndef __ASSEMBLY__ +/* Prototypes */ +void mttlb1(unsigned long index, unsigned long value); +void mttlb2(unsigned long index, unsigned long value); +void mttlb3(unsigned long index, unsigned long value); +unsigned long mftlb1(unsigned long index); +unsigned long mftlb2(unsigned long index); +unsigned long mftlb3(unsigned long index); + +void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); +void remove_tlb(u32 vaddr, u32 size); +void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_440 */ +#endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/mp.h b/arch/ppc/include/asm/mp.h similarity index 100% rename from include/asm-ppc/mp.h rename to arch/ppc/include/asm/mp.h diff --git a/include/asm-ppc/mpc512x.h b/arch/ppc/include/asm/mpc512x.h similarity index 100% rename from include/asm-ppc/mpc512x.h rename to arch/ppc/include/asm/mpc512x.h diff --git a/include/asm-ppc/mpc8349_pci.h b/arch/ppc/include/asm/mpc8349_pci.h similarity index 100% rename from include/asm-ppc/mpc8349_pci.h rename to arch/ppc/include/asm/mpc8349_pci.h diff --git a/include/asm-ppc/mpc8xxx_spi.h b/arch/ppc/include/asm/mpc8xxx_spi.h similarity index 100% rename from include/asm-ppc/mpc8xxx_spi.h rename to arch/ppc/include/asm/mpc8xxx_spi.h diff --git a/include/asm-ppc/pci_io.h b/arch/ppc/include/asm/pci_io.h similarity index 100% rename from include/asm-ppc/pci_io.h rename to arch/ppc/include/asm/pci_io.h diff --git a/include/asm-ppc/pnp.h b/arch/ppc/include/asm/pnp.h similarity index 100% rename from include/asm-ppc/pnp.h rename to arch/ppc/include/asm/pnp.h diff --git a/include/asm-ppc/posix_types.h b/arch/ppc/include/asm/posix_types.h similarity index 100% rename from include/asm-ppc/posix_types.h rename to arch/ppc/include/asm/posix_types.h diff --git a/include/asm-ppc/ppc4xx-ebc.h b/arch/ppc/include/asm/ppc4xx-ebc.h similarity index 100% rename from include/asm-ppc/ppc4xx-ebc.h rename to arch/ppc/include/asm/ppc4xx-ebc.h diff --git a/include/asm-ppc/ppc4xx-isram.h b/arch/ppc/include/asm/ppc4xx-isram.h similarity index 100% rename from include/asm-ppc/ppc4xx-isram.h rename to arch/ppc/include/asm/ppc4xx-isram.h diff --git a/include/asm-ppc/ppc4xx-sdram.h b/arch/ppc/include/asm/ppc4xx-sdram.h similarity index 100% rename from include/asm-ppc/ppc4xx-sdram.h rename to arch/ppc/include/asm/ppc4xx-sdram.h diff --git a/include/asm-ppc/ppc4xx-uic.h b/arch/ppc/include/asm/ppc4xx-uic.h similarity index 100% rename from include/asm-ppc/ppc4xx-uic.h rename to arch/ppc/include/asm/ppc4xx-uic.h diff --git a/include/asm-ppc/ppc4xx_config.h b/arch/ppc/include/asm/ppc4xx_config.h similarity index 100% rename from include/asm-ppc/ppc4xx_config.h rename to arch/ppc/include/asm/ppc4xx_config.h diff --git a/arch/ppc/include/asm/processor.h b/arch/ppc/include/asm/processor.h new file mode 100644 index 0000000000..9ec319ae17 --- /dev/null +++ b/arch/ppc/include/asm/processor.h @@ -0,0 +1,1285 @@ +#ifndef __ASM_PPC_PROCESSOR_H +#define __ASM_PPC_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include + +#include +#include + +/* Machine State Register (MSR) Fields */ + +#ifdef CONFIG_PPC64BRIDGE +#define MSR_SF (1<<63) +#define MSR_ISF (1<<61) +#endif /* CONFIG_PPC64BRIDGE */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ +#define MSR_SPE (1<<25) /* Enable SPE(e500) */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait State Enable */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_ILE (1<<16) /* Interrupt Little Endian */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_PR (1<<14) /* Problem State / Privilege Level */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IS (1<<5) /* Book E Instruction space */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DS (1<<4) /* Book E Data space */ +#define MSR_PE (1<<3) /* Protection Enable */ +#define MSR_PX (1<<2) /* Protection Exclusive Mode */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little Endian */ + +#ifdef CONFIG_APUS_FAST_EXCEPT +#define MSR_ MSR_ME|MSR_IP|MSR_RI +#else +#define MSR_ MSR_ME|MSR_RI +#endif +#ifndef CONFIG_E500 +#define MSR_KERNEL MSR_|MSR_IR|MSR_DR +#else +#define MSR_KERNEL MSR_ME +#endif + +/* Floating Point Status and Control Register (FPSCR) Fields */ + +#define FPSCR_FX 0x80000000 /* FPU exception summary */ +#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ +#define FPSCR_VX 0x20000000 /* Invalid operation summary */ +#define FPSCR_OX 0x10000000 /* Overflow exception summary */ +#define FPSCR_UX 0x08000000 /* Underflow exception summary */ +#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ +#define FPSCR_XX 0x02000000 /* Inexact exception summary */ +#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ +#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ +#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ +#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ +#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ +#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ +#define FPSCR_FR 0x00040000 /* Fraction rounded */ +#define FPSCR_FI 0x00020000 /* Fraction inexact */ +#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ +#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ +#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ +#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ +#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ +#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ +#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ +#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ +#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ +#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ +#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ +#define FPSCR_RN 0x00000003 /* FPU rounding control */ + +/* Special Purpose Registers (SPRNs)*/ + +/* PPC440 Architecture is BOOK-E */ +#ifdef CONFIG_440 +#define CONFIG_BOOKE +#endif + +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#ifdef CONFIG_BOOKE +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#endif +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#ifndef CONFIG_BOOKE +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#else +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define DBCR_EDM 0x80000000 +#define DBCR_IDM 0x40000000 +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#else +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#endif /* CONFIG_BOOKE */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#else +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#endif +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ +#ifndef CONFIG_BOOKE +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#endif +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ +#ifndef CONFIG_BOOKE +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#else +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#endif +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#endif +#define SPRN_EAR 0x11A /* External Address Register */ +#ifndef CONFIG_BOOKE +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#else +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#endif /* CONFIG_BOOKE */ +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ + +#define HID0_ICE_SHIFT 15 +#define HID0_DCE_SHIFT 14 +#define HID0_DLOCK_SHIFT 12 + +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ + +#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ +#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ +#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ +#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ +#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ +#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ +#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ + +/* Processor Version Register */ + +/* Processor Version Register (PVR) field extraction */ + +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ + +/* + * AMCC has further subdivided the standard PowerPC 16-bit version and + * revision subfields of the PVR for the PowerPC 403s into the following: + */ + +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ + +/* e600 core PVR fields */ + +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ + +/* Processor Version Numbers */ + +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 +#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ +#define PVR_405CR_RA 0x40110041 +#define PVR_405CR_RB 0x401100C5 +#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405EP_RA 0x51210950 +#define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ +#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ +#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ +#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ +#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ +#define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */ +#define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */ +#define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */ +#define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */ +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC 0x40120481 +#define PVR_440EP_RA 0x42221850 +#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ +#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ +#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ +#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ +#define PVR_440GX_RA 0x51B21850 +#define PVR_440GX_RB 0x51B21851 +#define PVR_440GX_RC 0x51B21892 +#define PVR_440GX_RF 0x51B21894 +#define PVR_405EP_RB 0x51210950 +#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ +#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ +#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ +#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ +#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ +#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ +#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ +#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ +#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ +#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/ +#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ +#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/ +#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 + +#define PVR_85xx 0x80200000 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010) +#define PVR_85xx_REV2 (PVR_85xx | 0x0020) + +#define PVR_86xx 0x80040000 + +#define PVR_VIRTEX5 0x7ff21912 + +/* + * For the 8xx processors, all of them report the same PVR family for + * the PowerPC core. The various versions of these processors must be + * differentiated by the version number in the Communication Processor + * Module (CPM). + */ +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_7400 0x000C0000 +#define PVR_8240 0x00810100 + +/* + * PowerQUICC II family processors report different PVR values depending + * on silicon process (HiP3, HiP4, HiP7, etc.) + */ +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 +#define PVR_8260_HIP7R1 0x80822013 +#define PVR_8260_HIP7RA 0x80822014 + +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + +/* + * System Version Register + */ + +/* System Version Register (SVR) field extraction */ + +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ + +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ + +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ + +/* Some parts define SVR[0:23] as the SOC version */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ + +/* whether MPC8xxxE (i.e. has SEC) */ +#if defined(CONFIG_MPC85xx) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) +#else +#if defined(CONFIG_MPC83xx) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) +#endif +#endif + +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) + +/* + * SVR_SOC_VER() Version Values + */ + +#define SVR_8533 0x803400 +#define SVR_8533_E 0x803C00 +#define SVR_8535 0x803701 +#define SVR_8535_E 0x803F01 +#define SVR_8536 0x803700 +#define SVR_8536_E 0x803F00 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8541_E 0x807A00 +#define SVR_8543 0x803200 +#define SVR_8543_E 0x803A00 +#define SVR_8544 0x803401 +#define SVR_8544_E 0x803C01 +#define SVR_8545 0x803102 +#define SVR_8545_E 0x803902 +#define SVR_8547_E 0x803901 +#define SVR_8548 0x803100 +#define SVR_8548_E 0x803900 +#define SVR_8555 0x807100 +#define SVR_8555_E 0x807900 +#define SVR_8560 0x807000 +#define SVR_8567 0x807600 +#define SVR_8567_E 0x807E00 +#define SVR_8568 0x807500 +#define SVR_8568_E 0x807D00 +#define SVR_8569 0x808000 +#define SVR_8569_E 0x808800 +#define SVR_8572 0x80E000 +#define SVR_8572_E 0x80E800 +#define SVR_P1011 0x80E500 +#define SVR_P1011_E 0x80ED00 +#define SVR_P1012 0x80E501 +#define SVR_P1012_E 0x80ED01 +#define SVR_P1013 0x80E700 +#define SVR_P1013_E 0x80EF00 +#define SVR_P1020 0x80E400 +#define SVR_P1020_E 0x80EC00 +#define SVR_P1021 0x80E401 +#define SVR_P1021_E 0x80EC01 +#define SVR_P1022 0x80E600 +#define SVR_P1022_E 0x80EE00 +#define SVR_P2010 0x80E300 +#define SVR_P2010_E 0x80EB00 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 +#define SVR_P4040 0x820100 +#define SVR_P4040_E 0x820900 +#define SVR_P4080 0x820000 +#define SVR_P4080_E 0x820800 + +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 + +#define SVR_Unknown 0xFFFFFF + +#define _GLOBAL(n)\ + .globl n;\ +n: + +/* Macros for setting and retrieving special purpose registers */ + +#define stringify(s) tostring(s) +#define tostring(s) #s + +#define mfdcr(rn) ({unsigned int rval; \ + asm volatile("mfdcr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) + +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) + +#define mfspr(rn) ({unsigned int rval; \ + asm volatile("mfspr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) + +#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) + +/* Segment Registers */ + +#define SR0 0 +#define SR1 1 +#define SR2 2 +#define SR3 3 +#define SR4 4 +#define SR5 5 +#define SR6 6 +#define SR7 7 +#define SR8 8 +#define SR9 9 +#define SR10 10 +#define SR11 11 +#define SR12 12 +#define SR13 13 +#define SR14 14 +#define SR15 15 + +#ifndef __ASSEMBLY__ + +struct cpu_type { + char name[15]; + u32 soc_ver; + u32 num_cores; +}; + +struct cpu_type *identify_cpu(u32 ver); + +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#define CPU_TYPE_ENTRY(n, v, nc) \ + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), } +#else +#if defined(CONFIG_MPC83xx) +#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} +#endif +#endif + + +#ifndef CONFIG_MACH_SPECIFIC +extern int _machine; +extern int have_of; +#endif /* CONFIG_MACH_SPECIFIC */ + +/* what kind of prep workstation we are */ +extern int _prep_type; +/* + * This is used to identify the board type from a given PReP board + * vendor. Board revision is also made available. + */ +extern unsigned char ucSystemType; +extern unsigned char ucBoardRev; +extern unsigned char ucBoardRevMaj, ucBoardRevMin; + +struct task_struct; +void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); +void release_thread(struct task_struct *); + +/* + * Create a new kernel thread. + */ +extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* + * Bus types + */ +#define EISA_bus 0 +#define EISA_bus__is_a_macro /* for versions in ksyms.c */ +#define MCA_bus 0 +#define MCA_bus__is_a_macro /* for versions in ksyms.c */ + +/* Lazy FPU handling on uni-processor */ +extern struct task_struct *last_task_used_math; +extern struct task_struct *last_task_used_altivec; + +/* + * this is the minimum allowable io space due to the location + * of the io areas on prep (first one at 0x80000000) but + * as soon as I get around to remapping the io areas with the BATs + * to match the mac we can raise this. -- Cort + */ +#define TASK_SIZE (0x80000000UL) + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) + +typedef struct { + unsigned long seg; +} mm_segment_t; + +struct thread_struct { + unsigned long ksp; /* Kernel stack pointer */ + unsigned long wchan; /* Event task is sleeping on */ + struct pt_regs *regs; /* Pointer to saved register state */ + mm_segment_t fs; /* for get_fs() validation */ + void *pgdir; /* root of page-table tree */ + signed long last_syscall; + double fpr[32]; /* Complete floating point set */ + unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ + unsigned long fpscr; /* Floating point status */ +#ifdef CONFIG_ALTIVEC + vector128 vr[32]; /* Complete AltiVec set */ + vector128 vscr; /* AltiVec status */ + unsigned long vrsave; +#endif /* CONFIG_ALTIVEC */ +}; + +#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) + +#define INIT_THREAD { \ + INIT_SP, /* ksp */ \ + 0, /* wchan */ \ + (struct pt_regs *)INIT_SP - 1, /* regs */ \ + KERNEL_DS, /*fs*/ \ + swapper_pg_dir, /* pgdir */ \ + 0, /* last_syscall */ \ + {0}, 0, 0 \ +} + +/* + * Note: the vm_start and vm_end fields here should *not* + * be in kernel space. (Could vm_end == vm_start perhaps?) + */ +#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ + PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ + 1, NULL, NULL } + +/* + * Return saved PC of a blocked thread. For now, this is the "user" PC + */ +static inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + return (t->regs) ? t->regs->nip : 0; +} + +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) +#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) + +/* + * NOTE! The task struct and the stack go together + */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + +/* in process.c - for early bootup debug -- Cort */ +int ll_printk(const char *, ...); +void ll_puts(const char *); + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +/* In misc.c */ +void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); + +#endif /* ndef ASSEMBLY*/ + +#ifdef CONFIG_MACH_SPECIFIC +#if defined(CONFIG_8xx) +#define _machine _MACH_8xx +#define have_of 0 +#elif defined(CONFIG_OAK) +#define _machine _MACH_oak +#define have_of 0 +#elif defined(CONFIG_WALNUT) +#define _machine _MACH_walnut +#define have_of 0 +#elif defined(CONFIG_APUS) +#define _machine _MACH_apus +#define have_of 0 +#elif defined(CONFIG_GEMINI) +#define _machine _MACH_gemini +#define have_of 0 +#elif defined(CONFIG_8260) +#define _machine _MACH_8260 +#define have_of 0 +#elif defined(CONFIG_SANDPOINT) +#define _machine _MACH_sandpoint +#elif defined(CONFIG_HIDDEN_DRAGON) +#define _machine _MACH_hidden_dragon +#define have_of 0 +#else +#error "Machine not defined correctly" +#endif +#endif /* CONFIG_MACH_SPECIFIC */ + +#endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/include/asm-ppc/ptrace.h b/arch/ppc/include/asm/ptrace.h similarity index 100% rename from include/asm-ppc/ptrace.h rename to arch/ppc/include/asm/ptrace.h diff --git a/include/asm-ppc/residual.h b/arch/ppc/include/asm/residual.h similarity index 100% rename from include/asm-ppc/residual.h rename to arch/ppc/include/asm/residual.h diff --git a/include/asm-ppc/sigcontext.h b/arch/ppc/include/asm/sigcontext.h similarity index 100% rename from include/asm-ppc/sigcontext.h rename to arch/ppc/include/asm/sigcontext.h diff --git a/include/asm-ppc/signal.h b/arch/ppc/include/asm/signal.h similarity index 100% rename from include/asm-ppc/signal.h rename to arch/ppc/include/asm/signal.h diff --git a/include/asm-ppc/status_led.h b/arch/ppc/include/asm/status_led.h similarity index 100% rename from include/asm-ppc/status_led.h rename to arch/ppc/include/asm/status_led.h diff --git a/include/asm-ppc/string.h b/arch/ppc/include/asm/string.h similarity index 100% rename from include/asm-ppc/string.h rename to arch/ppc/include/asm/string.h diff --git a/include/asm-ppc/types.h b/arch/ppc/include/asm/types.h similarity index 100% rename from include/asm-ppc/types.h rename to arch/ppc/include/asm/types.h diff --git a/include/asm-ppc/u-boot.h b/arch/ppc/include/asm/u-boot.h similarity index 100% rename from include/asm-ppc/u-boot.h rename to arch/ppc/include/asm/u-boot.h diff --git a/include/asm-ppc/unaligned.h b/arch/ppc/include/asm/unaligned.h similarity index 100% rename from include/asm-ppc/unaligned.h rename to arch/ppc/include/asm/unaligned.h diff --git a/include/asm-ppc/xilinx_irq.h b/arch/ppc/include/asm/xilinx_irq.h similarity index 100% rename from include/asm-ppc/xilinx_irq.h rename to arch/ppc/include/asm/xilinx_irq.h diff --git a/lib_ppc/Makefile b/arch/ppc/lib/Makefile similarity index 100% rename from lib_ppc/Makefile rename to arch/ppc/lib/Makefile diff --git a/lib_ppc/bat_rw.c b/arch/ppc/lib/bat_rw.c similarity index 100% rename from lib_ppc/bat_rw.c rename to arch/ppc/lib/bat_rw.c diff --git a/lib_ppc/board.c b/arch/ppc/lib/board.c similarity index 100% rename from lib_ppc/board.c rename to arch/ppc/lib/board.c diff --git a/lib_ppc/bootm.c b/arch/ppc/lib/bootm.c similarity index 100% rename from lib_ppc/bootm.c rename to arch/ppc/lib/bootm.c diff --git a/lib_ppc/cache.c b/arch/ppc/lib/cache.c similarity index 100% rename from lib_ppc/cache.c rename to arch/ppc/lib/cache.c diff --git a/lib_ppc/extable.c b/arch/ppc/lib/extable.c similarity index 100% rename from lib_ppc/extable.c rename to arch/ppc/lib/extable.c diff --git a/lib_ppc/interrupts.c b/arch/ppc/lib/interrupts.c similarity index 100% rename from lib_ppc/interrupts.c rename to arch/ppc/lib/interrupts.c diff --git a/lib_ppc/kgdb.c b/arch/ppc/lib/kgdb.c similarity index 100% rename from lib_ppc/kgdb.c rename to arch/ppc/lib/kgdb.c diff --git a/lib_ppc/ppccache.S b/arch/ppc/lib/ppccache.S similarity index 100% rename from lib_ppc/ppccache.S rename to arch/ppc/lib/ppccache.S diff --git a/lib_ppc/ppcstring.S b/arch/ppc/lib/ppcstring.S similarity index 100% rename from lib_ppc/ppcstring.S rename to arch/ppc/lib/ppcstring.S diff --git a/lib_ppc/reloc.S b/arch/ppc/lib/reloc.S similarity index 100% rename from lib_ppc/reloc.S rename to arch/ppc/lib/reloc.S diff --git a/lib_ppc/ticks.S b/arch/ppc/lib/ticks.S similarity index 100% rename from lib_ppc/ticks.S rename to arch/ppc/lib/ticks.S diff --git a/lib_ppc/time.c b/arch/ppc/lib/time.c similarity index 100% rename from lib_ppc/time.c rename to arch/ppc/lib/time.c diff --git a/arch/sh/config.mk b/arch/sh/config.mk new file mode 100644 index 0000000000..797bf4c226 --- /dev/null +++ b/arch/sh/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CROSS_COMPILE ?= sh4-linux- + +STANDALONE_LOAD_ADDR = 0x8C000000 +ifeq ($(CPU),sh2) +STANDALONE_LOAD_ADDR += -EB +endif + +PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ +PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE) + +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/cpu/sh2/Makefile b/arch/sh/cpu/sh2/Makefile similarity index 100% rename from cpu/sh2/Makefile rename to arch/sh/cpu/sh2/Makefile diff --git a/cpu/sh2/cache.c b/arch/sh/cpu/sh2/cache.c similarity index 100% rename from cpu/sh2/cache.c rename to arch/sh/cpu/sh2/cache.c diff --git a/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk similarity index 100% rename from cpu/sh2/config.mk rename to arch/sh/cpu/sh2/config.mk diff --git a/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c similarity index 100% rename from cpu/sh2/cpu.c rename to arch/sh/cpu/sh2/cpu.c diff --git a/cpu/sh2/interrupts.c b/arch/sh/cpu/sh2/interrupts.c similarity index 100% rename from cpu/sh2/interrupts.c rename to arch/sh/cpu/sh2/interrupts.c diff --git a/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S similarity index 100% rename from cpu/sh2/start.S rename to arch/sh/cpu/sh2/start.S diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds new file mode 100644 index 0000000000..e4e8b60696 --- /dev/null +++ b/arch/sh/cpu/sh2/u-boot.lds @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + arch/sh/cpu/sh2/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/cpu/sh2/watchdog.c b/arch/sh/cpu/sh2/watchdog.c similarity index 100% rename from cpu/sh2/watchdog.c rename to arch/sh/cpu/sh2/watchdog.c diff --git a/cpu/sh3/Makefile b/arch/sh/cpu/sh3/Makefile similarity index 100% rename from cpu/sh3/Makefile rename to arch/sh/cpu/sh3/Makefile diff --git a/cpu/sh3/cache.c b/arch/sh/cpu/sh3/cache.c similarity index 100% rename from cpu/sh3/cache.c rename to arch/sh/cpu/sh3/cache.c diff --git a/cpu/sh3/config.mk b/arch/sh/cpu/sh3/config.mk similarity index 100% rename from cpu/sh3/config.mk rename to arch/sh/cpu/sh3/config.mk diff --git a/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c similarity index 100% rename from cpu/sh3/cpu.c rename to arch/sh/cpu/sh3/cpu.c diff --git a/cpu/sh3/interrupts.c b/arch/sh/cpu/sh3/interrupts.c similarity index 100% rename from cpu/sh3/interrupts.c rename to arch/sh/cpu/sh3/interrupts.c diff --git a/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S similarity index 100% rename from cpu/sh3/start.S rename to arch/sh/cpu/sh3/start.S diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/sh3/u-boot.lds new file mode 100644 index 0000000000..8afe1603ee --- /dev/null +++ b/arch/sh/cpu/sh3/u-boot.lds @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2007 + * Yoshihiro Shimoda + * + * Copyright (C) 2007 + * Nobuhiro Iwamatsu + * + * Copyright (C) 2008 + * Mark Jonas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + arch/sh/cpu/sh3/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/cpu/sh3/watchdog.c b/arch/sh/cpu/sh3/watchdog.c similarity index 100% rename from cpu/sh3/watchdog.c rename to arch/sh/cpu/sh3/watchdog.c diff --git a/cpu/sh4/Makefile b/arch/sh/cpu/sh4/Makefile similarity index 100% rename from cpu/sh4/Makefile rename to arch/sh/cpu/sh4/Makefile diff --git a/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c similarity index 100% rename from cpu/sh4/cache.c rename to arch/sh/cpu/sh4/cache.c diff --git a/cpu/sh4/config.mk b/arch/sh/cpu/sh4/config.mk similarity index 100% rename from cpu/sh4/config.mk rename to arch/sh/cpu/sh4/config.mk diff --git a/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c similarity index 100% rename from cpu/sh4/cpu.c rename to arch/sh/cpu/sh4/cpu.c diff --git a/cpu/sh4/interrupts.c b/arch/sh/cpu/sh4/interrupts.c similarity index 100% rename from cpu/sh4/interrupts.c rename to arch/sh/cpu/sh4/interrupts.c diff --git a/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S similarity index 100% rename from cpu/sh4/start.S rename to arch/sh/cpu/sh4/start.S diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds new file mode 100644 index 0000000000..d3719df543 --- /dev/null +++ b/arch/sh/cpu/sh4/u-boot.lds @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu + * + * Copyright (C) 2008-2009 + * Yoshihiro Shimoda + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + arch/sh/cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss (NOLOAD) : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/cpu/sh4/watchdog.c b/arch/sh/cpu/sh4/watchdog.c similarity index 100% rename from cpu/sh4/watchdog.c rename to arch/sh/cpu/sh4/watchdog.c diff --git a/include/asm-sh/bitops.h b/arch/sh/include/asm/bitops.h similarity index 100% rename from include/asm-sh/bitops.h rename to arch/sh/include/asm/bitops.h diff --git a/include/asm-sh/byteorder.h b/arch/sh/include/asm/byteorder.h similarity index 100% rename from include/asm-sh/byteorder.h rename to arch/sh/include/asm/byteorder.h diff --git a/include/asm-sh/cache.h b/arch/sh/include/asm/cache.h similarity index 100% rename from include/asm-sh/cache.h rename to arch/sh/include/asm/cache.h diff --git a/include/asm-sh/clk.h b/arch/sh/include/asm/clk.h similarity index 100% rename from include/asm-sh/clk.h rename to arch/sh/include/asm/clk.h diff --git a/include/asm-sh/config.h b/arch/sh/include/asm/config.h similarity index 100% rename from include/asm-sh/config.h rename to arch/sh/include/asm/config.h diff --git a/include/asm-sh/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h similarity index 100% rename from include/asm-sh/cpu_sh2.h rename to arch/sh/include/asm/cpu_sh2.h diff --git a/include/asm-sh/cpu_sh3.h b/arch/sh/include/asm/cpu_sh3.h similarity index 100% rename from include/asm-sh/cpu_sh3.h rename to arch/sh/include/asm/cpu_sh3.h diff --git a/include/asm-sh/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h similarity index 100% rename from include/asm-sh/cpu_sh4.h rename to arch/sh/include/asm/cpu_sh4.h diff --git a/include/asm-sh/cpu_sh7203.h b/arch/sh/include/asm/cpu_sh7203.h similarity index 100% rename from include/asm-sh/cpu_sh7203.h rename to arch/sh/include/asm/cpu_sh7203.h diff --git a/include/asm-sh/cpu_sh7710.h b/arch/sh/include/asm/cpu_sh7710.h similarity index 100% rename from include/asm-sh/cpu_sh7710.h rename to arch/sh/include/asm/cpu_sh7710.h diff --git a/include/asm-sh/cpu_sh7720.h b/arch/sh/include/asm/cpu_sh7720.h similarity index 100% rename from include/asm-sh/cpu_sh7720.h rename to arch/sh/include/asm/cpu_sh7720.h diff --git a/include/asm-sh/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h similarity index 100% rename from include/asm-sh/cpu_sh7722.h rename to arch/sh/include/asm/cpu_sh7722.h diff --git a/include/asm-sh/cpu_sh7723.h b/arch/sh/include/asm/cpu_sh7723.h similarity index 100% rename from include/asm-sh/cpu_sh7723.h rename to arch/sh/include/asm/cpu_sh7723.h diff --git a/include/asm-sh/cpu_sh7750.h b/arch/sh/include/asm/cpu_sh7750.h similarity index 100% rename from include/asm-sh/cpu_sh7750.h rename to arch/sh/include/asm/cpu_sh7750.h diff --git a/include/asm-sh/cpu_sh7763.h b/arch/sh/include/asm/cpu_sh7763.h similarity index 100% rename from include/asm-sh/cpu_sh7763.h rename to arch/sh/include/asm/cpu_sh7763.h diff --git a/include/asm-sh/cpu_sh7780.h b/arch/sh/include/asm/cpu_sh7780.h similarity index 100% rename from include/asm-sh/cpu_sh7780.h rename to arch/sh/include/asm/cpu_sh7780.h diff --git a/include/asm-sh/cpu_sh7785.h b/arch/sh/include/asm/cpu_sh7785.h similarity index 100% rename from include/asm-sh/cpu_sh7785.h rename to arch/sh/include/asm/cpu_sh7785.h diff --git a/include/asm-sparc/errno.h b/arch/sh/include/asm/errno.h similarity index 100% rename from include/asm-sparc/errno.h rename to arch/sh/include/asm/errno.h diff --git a/include/asm-sh/global_data.h b/arch/sh/include/asm/global_data.h similarity index 100% rename from include/asm-sh/global_data.h rename to arch/sh/include/asm/global_data.h diff --git a/include/asm-sh/io.h b/arch/sh/include/asm/io.h similarity index 100% rename from include/asm-sh/io.h rename to arch/sh/include/asm/io.h diff --git a/include/asm-sh/irqflags.h b/arch/sh/include/asm/irqflags.h similarity index 100% rename from include/asm-sh/irqflags.h rename to arch/sh/include/asm/irqflags.h diff --git a/include/asm-sh/macro.h b/arch/sh/include/asm/macro.h similarity index 100% rename from include/asm-sh/macro.h rename to arch/sh/include/asm/macro.h diff --git a/include/asm-sh/pci.h b/arch/sh/include/asm/pci.h similarity index 100% rename from include/asm-sh/pci.h rename to arch/sh/include/asm/pci.h diff --git a/include/asm-sh/posix_types.h b/arch/sh/include/asm/posix_types.h similarity index 100% rename from include/asm-sh/posix_types.h rename to arch/sh/include/asm/posix_types.h diff --git a/include/asm-sh/processor.h b/arch/sh/include/asm/processor.h similarity index 100% rename from include/asm-sh/processor.h rename to arch/sh/include/asm/processor.h diff --git a/include/asm-sh/ptrace.h b/arch/sh/include/asm/ptrace.h similarity index 100% rename from include/asm-sh/ptrace.h rename to arch/sh/include/asm/ptrace.h diff --git a/include/asm-sh/string.h b/arch/sh/include/asm/string.h similarity index 100% rename from include/asm-sh/string.h rename to arch/sh/include/asm/string.h diff --git a/include/asm-sh/system.h b/arch/sh/include/asm/system.h similarity index 100% rename from include/asm-sh/system.h rename to arch/sh/include/asm/system.h diff --git a/include/asm-sh/types.h b/arch/sh/include/asm/types.h similarity index 100% rename from include/asm-sh/types.h rename to arch/sh/include/asm/types.h diff --git a/include/asm-sh/u-boot.h b/arch/sh/include/asm/u-boot.h similarity index 100% rename from include/asm-sh/u-boot.h rename to arch/sh/include/asm/u-boot.h diff --git a/include/asm-sh/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h similarity index 100% rename from include/asm-sh/unaligned-sh4a.h rename to arch/sh/include/asm/unaligned-sh4a.h diff --git a/include/asm-sh/unaligned.h b/arch/sh/include/asm/unaligned.h similarity index 100% rename from include/asm-sh/unaligned.h rename to arch/sh/include/asm/unaligned.h diff --git a/lib_sh/Makefile b/arch/sh/lib/Makefile similarity index 100% rename from lib_sh/Makefile rename to arch/sh/lib/Makefile diff --git a/lib_sh/board.c b/arch/sh/lib/board.c similarity index 100% rename from lib_sh/board.c rename to arch/sh/lib/board.c diff --git a/lib_sh/bootm.c b/arch/sh/lib/bootm.c similarity index 100% rename from lib_sh/bootm.c rename to arch/sh/lib/bootm.c diff --git a/lib_sh/time.c b/arch/sh/lib/time.c similarity index 100% rename from lib_sh/time.c rename to arch/sh/lib/time.c diff --git a/lib_sh/time_sh2.c b/arch/sh/lib/time_sh2.c similarity index 100% rename from lib_sh/time_sh2.c rename to arch/sh/lib/time_sh2.c diff --git a/lib_sparc/config.mk b/arch/sparc/config.mk similarity index 100% rename from lib_sparc/config.mk rename to arch/sparc/config.mk diff --git a/cpu/leon2/Makefile b/arch/sparc/cpu/leon2/Makefile similarity index 100% rename from cpu/leon2/Makefile rename to arch/sparc/cpu/leon2/Makefile diff --git a/cpu/leon2/config.mk b/arch/sparc/cpu/leon2/config.mk similarity index 100% rename from cpu/leon2/config.mk rename to arch/sparc/cpu/leon2/config.mk diff --git a/cpu/leon2/cpu.c b/arch/sparc/cpu/leon2/cpu.c similarity index 100% rename from cpu/leon2/cpu.c rename to arch/sparc/cpu/leon2/cpu.c diff --git a/cpu/leon2/cpu_init.c b/arch/sparc/cpu/leon2/cpu_init.c similarity index 100% rename from cpu/leon2/cpu_init.c rename to arch/sparc/cpu/leon2/cpu_init.c diff --git a/cpu/leon2/interrupts.c b/arch/sparc/cpu/leon2/interrupts.c similarity index 100% rename from cpu/leon2/interrupts.c rename to arch/sparc/cpu/leon2/interrupts.c diff --git a/cpu/leon2/prom.c b/arch/sparc/cpu/leon2/prom.c similarity index 100% rename from cpu/leon2/prom.c rename to arch/sparc/cpu/leon2/prom.c diff --git a/cpu/leon2/serial.c b/arch/sparc/cpu/leon2/serial.c similarity index 100% rename from cpu/leon2/serial.c rename to arch/sparc/cpu/leon2/serial.c diff --git a/cpu/leon2/start.S b/arch/sparc/cpu/leon2/start.S similarity index 100% rename from cpu/leon2/start.S rename to arch/sparc/cpu/leon2/start.S diff --git a/cpu/leon3/Makefile b/arch/sparc/cpu/leon3/Makefile similarity index 100% rename from cpu/leon3/Makefile rename to arch/sparc/cpu/leon3/Makefile diff --git a/cpu/leon3/ambapp.c b/arch/sparc/cpu/leon3/ambapp.c similarity index 100% rename from cpu/leon3/ambapp.c rename to arch/sparc/cpu/leon3/ambapp.c diff --git a/cpu/leon3/config.mk b/arch/sparc/cpu/leon3/config.mk similarity index 100% rename from cpu/leon3/config.mk rename to arch/sparc/cpu/leon3/config.mk diff --git a/cpu/leon3/cpu.c b/arch/sparc/cpu/leon3/cpu.c similarity index 100% rename from cpu/leon3/cpu.c rename to arch/sparc/cpu/leon3/cpu.c diff --git a/cpu/leon3/cpu_init.c b/arch/sparc/cpu/leon3/cpu_init.c similarity index 100% rename from cpu/leon3/cpu_init.c rename to arch/sparc/cpu/leon3/cpu_init.c diff --git a/cpu/leon3/interrupts.c b/arch/sparc/cpu/leon3/interrupts.c similarity index 100% rename from cpu/leon3/interrupts.c rename to arch/sparc/cpu/leon3/interrupts.c diff --git a/cpu/leon3/prom.c b/arch/sparc/cpu/leon3/prom.c similarity index 100% rename from cpu/leon3/prom.c rename to arch/sparc/cpu/leon3/prom.c diff --git a/cpu/leon3/serial.c b/arch/sparc/cpu/leon3/serial.c similarity index 100% rename from cpu/leon3/serial.c rename to arch/sparc/cpu/leon3/serial.c diff --git a/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S similarity index 100% rename from cpu/leon3/start.S rename to arch/sparc/cpu/leon3/start.S diff --git a/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c similarity index 100% rename from cpu/leon3/usb_uhci.c rename to arch/sparc/cpu/leon3/usb_uhci.c diff --git a/cpu/leon3/usb_uhci.h b/arch/sparc/cpu/leon3/usb_uhci.h similarity index 100% rename from cpu/leon3/usb_uhci.h rename to arch/sparc/cpu/leon3/usb_uhci.h diff --git a/include/asm-sparc/arch-leon2/asi.h b/arch/sparc/include/asm/arch-leon2/asi.h similarity index 100% rename from include/asm-sparc/arch-leon2/asi.h rename to arch/sparc/include/asm/arch-leon2/asi.h diff --git a/include/asm-sparc/arch-leon3/asi.h b/arch/sparc/include/asm/arch-leon3/asi.h similarity index 100% rename from include/asm-sparc/arch-leon3/asi.h rename to arch/sparc/include/asm/arch-leon3/asi.h diff --git a/include/asm-sparc/asi.h b/arch/sparc/include/asm/asi.h similarity index 100% rename from include/asm-sparc/asi.h rename to arch/sparc/include/asm/asi.h diff --git a/include/asm-sparc/asmmacro.h b/arch/sparc/include/asm/asmmacro.h similarity index 100% rename from include/asm-sparc/asmmacro.h rename to arch/sparc/include/asm/asmmacro.h diff --git a/include/asm-sparc/atomic.h b/arch/sparc/include/asm/atomic.h similarity index 100% rename from include/asm-sparc/atomic.h rename to arch/sparc/include/asm/atomic.h diff --git a/include/asm-sparc/bitops.h b/arch/sparc/include/asm/bitops.h similarity index 100% rename from include/asm-sparc/bitops.h rename to arch/sparc/include/asm/bitops.h diff --git a/include/asm-sparc/byteorder.h b/arch/sparc/include/asm/byteorder.h similarity index 100% rename from include/asm-sparc/byteorder.h rename to arch/sparc/include/asm/byteorder.h diff --git a/include/asm-sparc/cache.h b/arch/sparc/include/asm/cache.h similarity index 100% rename from include/asm-sparc/cache.h rename to arch/sparc/include/asm/cache.h diff --git a/include/asm-sparc/config.h b/arch/sparc/include/asm/config.h similarity index 100% rename from include/asm-sparc/config.h rename to arch/sparc/include/asm/config.h diff --git a/arch/sparc/include/asm/errno.h b/arch/sparc/include/asm/errno.h new file mode 100644 index 0000000000..4c82b503d9 --- /dev/null +++ b/arch/sparc/include/asm/errno.h @@ -0,0 +1 @@ +#include diff --git a/include/asm-sparc/global_data.h b/arch/sparc/include/asm/global_data.h similarity index 100% rename from include/asm-sparc/global_data.h rename to arch/sparc/include/asm/global_data.h diff --git a/include/asm-sparc/io.h b/arch/sparc/include/asm/io.h similarity index 100% rename from include/asm-sparc/io.h rename to arch/sparc/include/asm/io.h diff --git a/include/asm-sparc/irq.h b/arch/sparc/include/asm/irq.h similarity index 100% rename from include/asm-sparc/irq.h rename to arch/sparc/include/asm/irq.h diff --git a/include/asm-sparc/leon.h b/arch/sparc/include/asm/leon.h similarity index 100% rename from include/asm-sparc/leon.h rename to arch/sparc/include/asm/leon.h diff --git a/include/asm-sparc/leon2.h b/arch/sparc/include/asm/leon2.h similarity index 100% rename from include/asm-sparc/leon2.h rename to arch/sparc/include/asm/leon2.h diff --git a/include/asm-sparc/leon3.h b/arch/sparc/include/asm/leon3.h similarity index 100% rename from include/asm-sparc/leon3.h rename to arch/sparc/include/asm/leon3.h diff --git a/include/asm-sparc/machines.h b/arch/sparc/include/asm/machines.h similarity index 100% rename from include/asm-sparc/machines.h rename to arch/sparc/include/asm/machines.h diff --git a/include/asm-sparc/page.h b/arch/sparc/include/asm/page.h similarity index 100% rename from include/asm-sparc/page.h rename to arch/sparc/include/asm/page.h diff --git a/include/asm-sparc/posix_types.h b/arch/sparc/include/asm/posix_types.h similarity index 100% rename from include/asm-sparc/posix_types.h rename to arch/sparc/include/asm/posix_types.h diff --git a/include/asm-sparc/processor.h b/arch/sparc/include/asm/processor.h similarity index 100% rename from include/asm-sparc/processor.h rename to arch/sparc/include/asm/processor.h diff --git a/include/asm-sparc/prom.h b/arch/sparc/include/asm/prom.h similarity index 100% rename from include/asm-sparc/prom.h rename to arch/sparc/include/asm/prom.h diff --git a/include/asm-sparc/psr.h b/arch/sparc/include/asm/psr.h similarity index 100% rename from include/asm-sparc/psr.h rename to arch/sparc/include/asm/psr.h diff --git a/include/asm-sparc/ptrace.h b/arch/sparc/include/asm/ptrace.h similarity index 100% rename from include/asm-sparc/ptrace.h rename to arch/sparc/include/asm/ptrace.h diff --git a/include/asm-sparc/srmmu.h b/arch/sparc/include/asm/srmmu.h similarity index 100% rename from include/asm-sparc/srmmu.h rename to arch/sparc/include/asm/srmmu.h diff --git a/include/asm-sparc/stack.h b/arch/sparc/include/asm/stack.h similarity index 100% rename from include/asm-sparc/stack.h rename to arch/sparc/include/asm/stack.h diff --git a/include/asm-sparc/string.h b/arch/sparc/include/asm/string.h similarity index 100% rename from include/asm-sparc/string.h rename to arch/sparc/include/asm/string.h diff --git a/include/asm-sparc/types.h b/arch/sparc/include/asm/types.h similarity index 100% rename from include/asm-sparc/types.h rename to arch/sparc/include/asm/types.h diff --git a/include/asm-sparc/u-boot.h b/arch/sparc/include/asm/u-boot.h similarity index 100% rename from include/asm-sparc/u-boot.h rename to arch/sparc/include/asm/u-boot.h diff --git a/include/asm-sparc/winmacro.h b/arch/sparc/include/asm/winmacro.h similarity index 100% rename from include/asm-sparc/winmacro.h rename to arch/sparc/include/asm/winmacro.h diff --git a/lib_sparc/Makefile b/arch/sparc/lib/Makefile similarity index 100% rename from lib_sparc/Makefile rename to arch/sparc/lib/Makefile diff --git a/lib_sparc/board.c b/arch/sparc/lib/board.c similarity index 100% rename from lib_sparc/board.c rename to arch/sparc/lib/board.c diff --git a/lib_sparc/bootm.c b/arch/sparc/lib/bootm.c similarity index 100% rename from lib_sparc/bootm.c rename to arch/sparc/lib/bootm.c diff --git a/lib_sparc/cache.c b/arch/sparc/lib/cache.c similarity index 100% rename from lib_sparc/cache.c rename to arch/sparc/lib/cache.c diff --git a/lib_sparc/interrupts.c b/arch/sparc/lib/interrupts.c similarity index 100% rename from lib_sparc/interrupts.c rename to arch/sparc/lib/interrupts.c diff --git a/lib_sparc/time.c b/arch/sparc/lib/time.c similarity index 100% rename from lib_sparc/time.c rename to arch/sparc/lib/time.c diff --git a/board/BuS/EB+MCF-EV123/u-boot.lds b/board/BuS/EB+MCF-EV123/u-boot.lds index 34507938fd..0fa633a1fe 100644 --- a/board/BuS/EB+MCF-EV123/u-boot.lds +++ b/board/BuS/EB+MCF-EV123/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) common/dlmalloc.o (.text) - lib_generic/string.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + lib/string.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) /* . = env_offset; */ common/env_embedded.o(.text) diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index 3c44b3ef29..e26792cc2f 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -64,17 +64,17 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_generic/string.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/extable.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + lib/string.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/extable.o (.text) + arch/ppc/lib/time.o (.text) + arch/ppc/lib/ticks.o (.text) . = env_offset; common/env_embedded.o (.text) diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug index 5126083425..707ff7a6b0 100644 --- a/board/LEOX/elpt860/u-boot.lds.debug +++ b/board/LEOX/elpt860/u-boot.lds.debug @@ -64,10 +64,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o (.text) diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds index 18510a8e7e..1f55c6571d 100644 --- a/board/MAI/AmigaOneG3SE/u-boot.lds +++ b/board/MAI/AmigaOneG3SE/u-boot.lds @@ -59,7 +59,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ common/env_embedded.o(.text) diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds index d021331148..6dff003dc1 100644 --- a/board/Marvell/db64360/u-boot.lds +++ b/board/Marvell/db64360/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds index d021331148..6dff003dc1 100644 --- a/board/Marvell/db64460/u-boot.lds +++ b/board/Marvell/db64460/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index 47247ec813..f7de95dc87 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) /* XXX ? . = env_offset; */ diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index a2d940f048..57cc305868 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index 47247ec813..f7de95dc87 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) /* XXX ? . = env_offset; */ diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index a2d940f048..57cc305868 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index 7ae7be0c02..a2db9a6288 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) /* XXX ? . = env_offset; */ diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index 83fdc15011..723f562911 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index f22b25fc3d..b323768fb0 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = env_offset; common/env_embedded.o (.ppcenv) diff --git a/board/actux1/config.mk b/board/actux1/config.mk index 119140d8c3..a0dbe0bc48 100644 --- a/board/actux1/config.mk +++ b/board/actux1/config.mk @@ -1,6 +1,6 @@ TEXT_BASE = 0x00e00000 # include NPE ethernet driver -BOARDLIBS = cpu/ixp/npe/libnpe.a +BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 836775f0fe..5c1ece79c8 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -30,12 +30,12 @@ SECTIONS . = ALIGN (4); .text : { - cpu/ixp/start.o(.text) - lib_generic/string.o(.text) - lib_generic/vsprintf.o(.text) - lib_arm/board.o(.text) + arch/arm/cpu/ixp/start.o(.text) + lib/string.o(.text) + lib/vsprintf.o(.text) + arch/arm/lib/board.o(.text) common/dlmalloc.o(.text) - cpu/ixp/cpu.o(.text) + arch/arm/cpu/ixp/cpu.o(.text) . = env_offset; common/env_embedded.o(.ppcenv) * (.text) diff --git a/board/actux2/config.mk b/board/actux2/config.mk index 119140d8c3..a0dbe0bc48 100644 --- a/board/actux2/config.mk +++ b/board/actux2/config.mk @@ -1,6 +1,6 @@ TEXT_BASE = 0x00e00000 # include NPE ethernet driver -BOARDLIBS = cpu/ixp/npe/libnpe.a +BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 0752656b59..707c027ab5 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -30,12 +30,12 @@ SECTIONS . = ALIGN (4); .text : { - cpu/ixp/start.o(.text) - lib_generic/string.o(.text) - lib_generic/vsprintf.o(.text) - lib_arm/board.o(.text) + arch/arm/cpu/ixp/start.o(.text) + lib/string.o(.text) + lib/vsprintf.o(.text) + arch/arm/lib/board.o(.text) common/dlmalloc.o(.text) - cpu/ixp/cpu.o(.text) + arch/arm/cpu/ixp/cpu.o(.text) . = env_offset; common/env_embedded.o (.ppcenv) diff --git a/board/actux3/config.mk b/board/actux3/config.mk index 119140d8c3..a0dbe0bc48 100644 --- a/board/actux3/config.mk +++ b/board/actux3/config.mk @@ -1,6 +1,6 @@ TEXT_BASE = 0x00e00000 # include NPE ethernet driver -BOARDLIBS = cpu/ixp/npe/libnpe.a +BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index a69e7db9ca..497ab97690 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -30,12 +30,12 @@ SECTIONS . = ALIGN (4); .text : { - cpu/ixp/start.o (.text) - lib_generic/string.o (.text) - lib_generic/vsprintf.o (.text) - lib_arm/board.o (.text) + arch/arm/cpu/ixp/start.o (.text) + lib/string.o (.text) + lib/vsprintf.o (.text) + arch/arm/lib/board.o (.text) common/dlmalloc.o (.text) - cpu/ixp/cpu.o (.text) + arch/arm/cpu/ixp/cpu.o (.text) . = env_offset; common/env_embedded.o (.ppcenv) diff --git a/board/actux4/config.mk b/board/actux4/config.mk index 9a634cdffa..f2b5fc911a 100644 --- a/board/actux4/config.mk +++ b/board/actux4/config.mk @@ -1,4 +1,4 @@ TEXT_BASE = 0x00e00000 # include NPE ethernet driver -BOARDLIBS = cpu/ixp/npe/libnpe.a +BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index 397ee2f053..018bcf1a26 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) . = ALIGN(16); diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c index 0fcf354cdc..7a1b4d3c2f 100644 --- a/board/altera/common/AMDLV065D.c +++ b/board/altera/common/AMDLV065D.c @@ -122,12 +122,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr2 = (unsigned char *) info->start[sect]; - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr, 0x80); - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr2, 0x30); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x80, addr); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x30, addr2); /* Now just wait for 0xff & provide some user * feedback while we wait. */ @@ -169,10 +169,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return (2); } - writeb (cmd, 0xaa); - writeb (cmd, 0x55); - writeb (cmd, 0xa0); - writeb (dst, b); + writeb (0xaa, cmd); + writeb (0x55, cmd); + writeb (0xa0, cmd); + writeb (b, dst); /* Verify write */ start = get_timer (0); diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c index e5e7705761..d0197358f4 100644 --- a/board/altera/common/epled.c +++ b/board/altera/common/epled.c @@ -39,7 +39,7 @@ void __led_init (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_set (led_id_t mask, int state) @@ -50,7 +50,7 @@ void __led_set (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_toggle (led_id_t mask) @@ -58,5 +58,5 @@ void __led_toggle (led_id_t mask) nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; val ^= mask; - writel (&pio->data, val); + writel (val, &pio->data); } diff --git a/board/altera/dk1c20/u-boot.lds b/board/altera/dk1c20/u-boot.lds index 98ee8f8323..50c3fe75a0 100644 --- a/board/altera/dk1c20/u-boot.lds +++ b/board/altera/dk1c20/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { .text : { - cpu/nios/start.o (.text) + arch/nios/cpu/start.o (.text) *(.text) } __text_end = .; diff --git a/board/altera/dk1s10/u-boot.lds b/board/altera/dk1s10/u-boot.lds index 98ee8f8323..50c3fe75a0 100644 --- a/board/altera/dk1s10/u-boot.lds +++ b/board/altera/dk1s10/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { .text : { - cpu/nios/start.o (.text) + arch/nios/cpu/start.o (.text) *(.text) } __text_end = .; diff --git a/board/altera/ep1c20/u-boot.lds b/board/altera/ep1c20/u-boot.lds index e2eb3aa431..b909e94f8f 100644 --- a/board/altera/ep1c20/u-boot.lds +++ b/board/altera/ep1c20/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { .text : { - cpu/nios2/start.o (.text) + arch/nios/cpu2/start.o (.text) *(.text) *(.text.*) *(.gnu.linkonce.t*) diff --git a/board/altera/ep1s10/u-boot.lds b/board/altera/ep1s10/u-boot.lds index e2eb3aa431..b909e94f8f 100644 --- a/board/altera/ep1s10/u-boot.lds +++ b/board/altera/ep1s10/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { .text : { - cpu/nios2/start.o (.text) + arch/nios/cpu2/start.o (.text) *(.text) *(.text.*) *(.gnu.linkonce.t*) diff --git a/board/altera/ep1s40/u-boot.lds b/board/altera/ep1s40/u-boot.lds index e2eb3aa431..b909e94f8f 100644 --- a/board/altera/ep1s40/u-boot.lds +++ b/board/altera/ep1s40/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { .text : { - cpu/nios2/start.o (.text) + arch/nios/cpu2/start.o (.text) *(.text) *(.text.*) *(.gnu.linkonce.t*) diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index 738caa0c5f..bfca582715 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -53,7 +53,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) /* Align to next NAND block */ . = ALIGN(0x4000); diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index a5c9d6d764..7439c805c2 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -25,7 +25,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index 738caa0c5f..bfca582715 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -53,7 +53,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) /* Align to next NAND block */ . = ALIGN(0x4000); diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 13a0daced7..71a5701916 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BOARD_ARCHES 4 /* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. */ #if defined(CONFIG_ARCHES) diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index 0b667968ac..993bec30ea 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -23,7 +23,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index 47c6bd9211..b04b05e38a 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -53,7 +53,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) /* Align to next NAND block */ . = ALIGN(0x20000); diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S index 811a96a1f4..153fa811c4 100644 --- a/board/amcc/ebony/init.S +++ b/board/amcc/ebony/init.S @@ -22,7 +22,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 1c74a82c3d..90598f63bc 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -25,7 +25,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 54e2a39aa1..15291f96b5 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -249,7 +249,7 @@ int checkboard (void) } /* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. */ u32 ddr_wrdtr(u32 default_val) { diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index 738caa0c5f..bfca582715 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -53,7 +53,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) /* Align to next NAND block */ . = ALIGN(0x4000); diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S index fb54dea3a0..513b0fc560 100644 --- a/board/amcc/luan/init.S +++ b/board/amcc/luan/init.S @@ -25,7 +25,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 332d170d61..6542565f08 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -119,7 +119,7 @@ int checkboard(void) } /* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. */ u32 ddr_clktr(u32 default_val) { diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S index 8bcfbb197e..e7c75dfac5 100644 --- a/board/amcc/ocotea/init.S +++ b/board/amcc/ocotea/init.S @@ -22,7 +22,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S index 363d7932ac..4da586918d 100644 --- a/board/amcc/redwood/init.S +++ b/board/amcc/redwood/init.S @@ -23,7 +23,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c index bc8cb0c443..32fb8c584b 100644 --- a/board/amcc/redwood/redwood.c +++ b/board/amcc/redwood/redwood.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include int compare_to_true(char *str); char *remove_l_w_space(char *in_str); diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 3c0e400f95..f090070b4d 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -22,7 +22,7 @@ */ #include -#include +#include #include /* diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index bde471c2ef..b5c7d6d506 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -40,7 +40,7 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); #if defined(CONFIG_NAND_SPL) -/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big +/* Using arch/ppc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big * for the 4k NAND boot image so define bus_frequency to 133MHz here * which is save for the refresh counter setup. */ diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index fb629e0c5e..8a71bfa44e 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -53,7 +53,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) /* Align to next NAND block */ . = ALIGN(0x4000); diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds index e22dbecbf7..c6a321e400 100644 --- a/board/amcc/sequoia/u-boot-ram.lds +++ b/board/amcc/sequoia/u-boot-ram.lds @@ -50,7 +50,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) *(.text) *(.got1) diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index 9308fdac20..f51035ff68 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -25,7 +25,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 8c65cfb6fe..241f484491 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -555,7 +555,7 @@ int checkboard (void) } /* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. */ static int ppc440spe_rev_a(void) diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds index 707203d60f..faeefe8bdd 100644 --- a/board/amirix/ap1000/u-boot.lds +++ b/board/amirix/ap1000/u-boot.lds @@ -55,18 +55,18 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) board/amirix/ap1000/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) + arch/ppc/cpu/ppc4xx/kgdb.o (.text) + arch/ppc/cpu/ppc4xx/traps.o (.text) + arch/ppc/cpu/ppc4xx/interrupts.o (.text) + arch/ppc/cpu/ppc4xx/4xx_uart.o (.text) + arch/ppc/cpu/ppc4xx/cpu_init.o (.text) + arch/ppc/cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) /* . = env_offset;*/ /* common/env_embedded.o(.text)*/ diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 518944e077..9bb56b5208 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -132,9 +132,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif -#ifdef CONFIG_PCI rc += pci_eth_init(bis); -#endif return rc; } #endif diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile new file mode 100644 index 0000000000..c7a1d05518 --- /dev/null +++ b/board/astro/mcf5373l/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h new file mode 100644 index 0000000000..b55a6f785c --- /dev/null +++ b/board/astro/mcf5373l/astro.h @@ -0,0 +1,44 @@ +#ifndef __ASTRO_H__ +#define __ASTRO_H__ + +/* in mcf5373l.c */ +int rs_serial_init(int port, int baud); +void astro_put_char(char ch); +int astro_is_char(void); +int astro_get_char(void); + +/* in fpga.c */ +int astro5373l_altera_load(void); +int astro5373l_xilinx_load(void); + +/* data structures used for communication (update.c) */ +typedef struct card_id { + char card_type; + char hardware_version; + char software_version; + char software_subversion; /* " ","a".."z" */ + char fpga_version_altera; + char fpga_version_xilinx; +} card_id_t; + +typedef struct { + unsigned char mode; + unsigned char deviation; + unsigned short freq; +} __attribute__ ((packed)) output_params_t; + +typedef struct { + unsigned short satfreq; + unsigned char satdatallg; + unsigned short symbolrate; + unsigned char viterbirate; + unsigned char symbolrate_l; + output_params_t output_params; + unsigned char reserve; + unsigned char card_error; + unsigned short dummy_ts_id; + unsigned char dummy_pat_ver; + unsigned char dummy_sdt_ver; +} __attribute__ ((packed)) parameters_t; + +#endif /* __ASTRO_H__ */ diff --git a/board/astro/mcf5373l/config.mk b/board/astro/mcf5373l/config.mk new file mode 100644 index 0000000000..6316a3029a --- /dev/null +++ b/board/astro/mcf5373l/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = $(CONFIG_TEXT_BASE) + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c new file mode 100644 index 0000000000..467461b8e8 --- /dev/null +++ b/board/astro/mcf5373l/fpga.c @@ -0,0 +1,425 @@ +/* + * (C) Copyright 2006 + * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, + * w.wegner@astro-kom.de + * + * based on the files by + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * and + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +int altera_pre_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char tmp_char; + unsigned short tmp_short; + + /* first, set the required pins to GPIO function */ + /* PAR_T0IN -> GPIO */ + tmp_char = readb(&gpiop->par_timer); + tmp_char &= 0xfc; + writeb(tmp_char, &gpiop->par_timer); + /* all QSPI pins -> GPIO */ + writew(0x0000, &gpiop->par_qspi); + /* U0RTS, U0CTS -> GPIO */ + tmp_short = __raw_readw(&gpiop->par_uart); + tmp_short &= 0xfff3; + __raw_writew(tmp_short, &gpiop->par_uart); + /* all PWM pins -> GPIO */ + writeb(0x00, &gpiop->par_pwm); + /* next, set data direction registers */ + writeb(0x01, &gpiop->pddr_timer); + writeb(0x25, &gpiop->pddr_qspi); + writeb(0x0c, &gpiop->pddr_uart); + writeb(0x04, &gpiop->pddr_pwm); + + /* ensure other SPI peripherals are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x38, &gpiop->ppd_qspi); + + /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ + writeb(0xFB, &gpiop->pclrr_uart); + /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ + writeb(0xFE, &gpiop->pclrr_timer); + writeb(0xDF, &gpiop->pclrr_qspi); + return FPGA_SUCCESS; +} + +/* Set the state of CONFIG Pin */ +int altera_config_fn(int assert_config, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_config) + writeb(0x04, &gpiop->ppd_uart); + else + writeb(0xFB, &gpiop->pclrr_uart); + return FPGA_SUCCESS; +} + +/* Returns the state of STATUS Pin */ +int altera_status_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (readb(&gpiop->ppd_pwm) & 0x08) + return FPGA_FAIL; + return FPGA_SUCCESS; +} + +/* Returns the state of CONF_DONE Pin */ +int altera_done_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (readb(&gpiop->ppd_pwm) & 0x20) + return FPGA_FAIL; + return FPGA_SUCCESS; +} + +/* + * writes the complete buffer to the FPGA + * writing the complete buffer in one function is much faster, + * then calling it for every bit + */ +int altera_write_fn(void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char *data = (unsigned char *)buf; + unsigned char val = 0; + int i; + int len_40 = len / 40; + + while (bytecount < len) { + val = data[bytecount++]; + i = 8; + do { + writeb(0xFB, &gpiop->pclrr_qspi); + if (val & 0x01) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + writeb(0x04, &gpiop->ppd_qspi); + val >>= 1; + i--; + } while (i > 0); + + if (bytecount % len_40 == 0) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('.'); /* let them know we are alive */ +#endif +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) + return FPGA_FAIL; +#endif + } + } + return FPGA_SUCCESS; +} + +/* called, when programming is aborted */ +int altera_abort_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + writeb(0x20, &gpiop->ppd_qspi); + writeb(0x08, &gpiop->ppd_uart); + return FPGA_SUCCESS; +} + +/* called, when programming was succesful */ +int altera_post_fn(int cookie) +{ + return altera_abort_fn(cookie); +} + +/* + * Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * FIXME: relocation not yet working for coldfire, see below! + */ +Altera_CYC2_Passive_Serial_fns altera_fns = { + altera_pre_fn, + altera_config_fn, + altera_status_fn, + altera_done_fn, + altera_write_fn, + altera_abort_fn, + altera_post_fn +}; + +Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = { + {Altera_CYC2, + passive_serial, + 85903, + (void *)&altera_fns, + NULL, + 0} +}; + +/* Initialize the fpga. Return 1 on success, 0 on failure. */ +int astro5373l_altera_load(void) +{ + int i; + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + /* + * I did not yet manage to get relocation work properly, + * so set stuff here instead of static initialisation: + */ + altera_fns.pre = altera_pre_fn; + altera_fns.config = altera_config_fn; + altera_fns.status = altera_status_fn; + altera_fns.done = altera_done_fn; + altera_fns.write = altera_write_fn; + altera_fns.abort = altera_abort_fn; + altera_fns.post = altera_post_fn; + altera_fpga[i].iface_fns = (void *)&altera_fns; + fpga_add(fpga_altera, &altera_fpga[i]); + } + return 1; +} + +/* Set the FPGA's PROG_B line to the specified level */ +int xilinx_pgm_fn(int assert, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert) + writeb(0xFB, &gpiop->pclrr_uart); + else + writeb(0x04, &gpiop->ppd_uart); + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int xilinx_init_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + return (readb(&gpiop->ppd_pwm) & 0x08) == 0; +} + +/* Test the state of the active-high FPGA DONE pin */ +int xilinx_done_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; +} + +/* Abort an FPGA operation */ +int xilinx_abort_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + /* ensure all SPI peripherals and FPGAs are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x01, &gpiop->ppd_timer); + writeb(0x38, &gpiop->ppd_qspi); + return FPGA_FAIL; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +int xilinx_pre_config_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char tmp_char; + unsigned short tmp_short; + + /* first, set the required pins to GPIO function */ + /* PAR_T0IN -> GPIO */ + tmp_char = readb(&gpiop->par_timer); + tmp_char &= 0xfc; + writeb(tmp_char, &gpiop->par_timer); + /* all QSPI pins -> GPIO */ + writew(0x0000, &gpiop->par_qspi); + /* U0RTS, U0CTS -> GPIO */ + tmp_short = __raw_readw(&gpiop->par_uart); + tmp_short &= 0xfff3; + __raw_writew(tmp_short, &gpiop->par_uart); + /* all PWM pins -> GPIO */ + writeb(0x00, &gpiop->par_pwm); + /* next, set data direction registers */ + writeb(0x01, &gpiop->pddr_timer); + writeb(0x25, &gpiop->pddr_qspi); + writeb(0x0c, &gpiop->pddr_uart); + writeb(0x04, &gpiop->pddr_pwm); + + /* ensure other SPI peripherals are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x38, &gpiop->ppd_qspi); + writeb(0x01, &gpiop->ppd_timer); + + /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */ + writeb(0xFB, &gpiop->pclrr_uart); + /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ + writeb(0xF7, &gpiop->pclrr_uart); + writeb(0xDF, &gpiop->pclrr_qspi); + return 0; +} + +/* + * FPGA post configuration function. Should perform a test if FPGA is running. + */ +int xilinx_post_config_fn(int cookie) +{ + int rc = 0; + + /* + * no test yet + */ + return rc; +} + +int xilinx_clk_fn(int assert_clk, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_clk) + writeb(0x04, &gpiop->ppd_qspi); + else + writeb(0xFB, &gpiop->pclrr_qspi); + return assert_clk; +} + +int xilinx_wr_fn(int assert_write, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_write) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + return assert_write; +} + +int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char *data = (unsigned char *)buf; + unsigned char val = 0; + int i; + int len_40 = len / 40; + + for (bytecount = 0; bytecount < len; bytecount++) { + val = *(data++); + for (i = 8; i > 0; i--) { + writeb(0xFB, &gpiop->pclrr_qspi); + if (val & 0x80) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + writeb(0x04, &gpiop->ppd_qspi); + val <<= 1; + } + if (bytecount % len_40 == 0) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('.'); /* let them know we are alive */ +#endif +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) + return FPGA_FAIL; +#endif + } + } + return FPGA_SUCCESS; +} + +/* + * Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * FIXME: relocation not yet working for coldfire, see below! + */ +Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { + xilinx_pre_config_fn, + xilinx_pgm_fn, + xilinx_clk_fn, + xilinx_init_fn, + xilinx_done_fn, + xilinx_wr_fn, + 0, + xilinx_fastwr_fn +}; + +Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { + {Xilinx_Spartan3, + slave_serial, + XILINX_XC3S4000_SIZE, + (void *)&xilinx_fns, + 0} +}; + +/* Initialize the fpga. Return 1 on success, 0 on failure. */ +int astro5373l_xilinx_load(void) +{ + int i; + + fpga_init(); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + /* + * I did not yet manage to get relocation work properly, + * so set stuff here instead of static initialisation: + */ + xilinx_fns.pre = xilinx_pre_config_fn; + xilinx_fns.pgm = xilinx_pgm_fn; + xilinx_fns.clk = xilinx_clk_fn; + xilinx_fns.init = xilinx_init_fn; + xilinx_fns.done = xilinx_done_fn; + xilinx_fns.wr = xilinx_wr_fn; + xilinx_fns.bwr = xilinx_fastwr_fn; + xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; + fpga_add(fpga_xilinx, &xilinx_fpga[i]); + } + return 1; +} diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c new file mode 100644 index 0000000000..3c09a21eed --- /dev/null +++ b/board/astro/mcf5373l/mcf5373l.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * modified by Wolfgang Wegner for ASTRO 5373l + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* needed for astro bus: */ +#include +#include "astro.h" + +DECLARE_GLOBAL_DATA_PTR; +extern void uart_port_conf(void); + +int checkboard(void) +{ + puts("Board: "); + puts("ASTRO MCF5373L (Urmel) Board\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); + + /* + * GPIO configuration for bus should be set correctly from reset, + * so we do not care! First, set up address space: at this point, + * we should be running from internal SRAM; + * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, + * and do not care where it is + */ + __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, + &sdp->cs0); + __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, + &sdp->cs1); + /* + * I am not sure from the data sheet, but it seems burst length + * has to be 8 for the 16 bit data bus we use; + * so these values are for BL = 8 + */ + __raw_writel(0x33211530, &sdp->cfg1); + __raw_writel(0x56570000, &sdp->cfg2); + /* send PrechargeALL, REF and IREF remain cleared! */ + __raw_writel(0xE1462C02, &sdp->ctrl); + udelay(1); + /* refresh SDRAM twice */ + __raw_writel(0xE1462C04, &sdp->ctrl); + udelay(1); + __raw_writel(0xE1462C04, &sdp->ctrl); + /* init MR */ + __raw_writel(0x008D0000, &sdp->mode); + /* initialize EMR */ + __raw_writel(0x80010000, &sdp->mode); + /* wait until DLL is locked */ + udelay(1); + /* + * enable automatic refresh, lock mode register, + * clear iref and ipall + */ + __raw_writel(0x71462C00, &sdp->ctrl); + /* Dummy write to start SDRAM */ + writel(0, CONFIG_SYS_SDRAM_BASE); +#endif + + /* + * for get_ram_size() to work, both CS areas have to be + * configured, i.e. CS1 has to be explicitely disabled, else + * probing for memory will cause the SDRAM bus to hang! + * (Do not rely on the SDCS register(s) being set to 0x00000000 + * during reset as stated in the data sheet.) + */ + return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE, + 0x80000000 - CONFIG_SYS_SDRAM_BASE); +} + +#define UART_BASE MMAP_UART0 +int rs_serial_init(int port, int baud) +{ + uart_t *uart; + u32 counter; + + switch (port) { + case 0: + uart = (uart_t *)(MMAP_UART0); + break; + case 1: + uart = (uart_t *)(MMAP_UART1); + break; + case 2: + uart = (uart_t *)(MMAP_UART2); + break; + default: + uart = (uart_t *)(MMAP_UART0); + } + + uart_port_conf(); + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + writeb(UART_UCR_RESET_RX, &uart->ucr); + writeb(UART_UCR_RESET_TX, &uart->ucr); + writeb(UART_UCR_RESET_ERROR, &uart->ucr); + writeb(UART_UCR_RESET_MR, &uart->ucr); + __asm__ ("nop"); + + writeb(0, &uart->uimr); + + /* write to CSR: RX/TX baud rate from timers */ + writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); + + writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); + writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); + + /* Setting up BaudRate */ + counter = (u32) (gd->bus_clk / (baud)); + counter >>= 5; + + /* write to CTUR: divide counter upper byte */ + writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); + /* write to CTLR: divide counter lower byte */ + writeb((u8) (counter & 0x00ff), &uart->ubg2); + + writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); + + return 0; +} + +void astro_put_char(char ch) +{ + uart_t *uart; + unsigned long timer; + + uart = (uart_t *)(MMAP_UART0); + /* + * Wait for last character to go. Timeout of 6ms should + * be enough for our lowest baud rate of 2400. + */ + timer = get_timer(0); + while (get_timer(timer) < 6) { + if (readb(&uart->usr) & UART_USR_TXRDY) + break; + } + writeb(ch, &uart->utb); + + return; +} + +int astro_is_char(void) +{ + uart_t *uart; + + uart = (uart_t *)(MMAP_UART0); + return readb(&uart->usr) & UART_USR_RXRDY; +} + +int astro_get_char(void) +{ + uart_t *uart; + + uart = (uart_t *)(MMAP_UART0); + while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; + return readb(&uart->urb); +} + +int misc_init_r(void) +{ + int retval = 0; + + puts("Configure Xilinx FPGA..."); + retval = astro5373l_xilinx_load(); + if (!retval) { + puts("failed!\n"); + return retval; + } + puts("done\n"); + + puts("Configure Altera FPGA..."); + retval = astro5373l_altera_load(); + if (!retval) { + puts("failed!\n"); + return retval; + } + puts("done\n"); + + return retval; +} diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds new file mode 100644 index 0000000000..167a0a3f12 --- /dev/null +++ b/board/astro/mcf5373l/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + arch/m68k/cpu/mcf532x/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/lib/interrupts.o (.text) + common/dlmalloc.o (.text) + lib/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) +/* *(.fixup)*/ + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c index 6fb0096bed..3117b5fbff 100644 --- a/board/bc3450/bc3450.c +++ b/board/bc3450/bc3450.c @@ -104,7 +104,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -204,57 +203,6 @@ phys_size_t initdram (int board_type) return dramsize; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined (CONFIG_TQM5200) @@ -276,10 +224,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h index 3f1e1691bb..48b43213dc 100644 --- a/board/bc3450/mt48lc16m16a2-75.h +++ b/board/bc3450/mt48lc16m16a2-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 /* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ @@ -33,15 +32,3 @@ /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk index f85bef5e2a..3f9d41f371 100644 --- a/board/bf518f-ezbrd/config.mk +++ b/board/bf518f-ezbrd/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk index f85bef5e2a..3f9d41f371 100644 --- a/board/bf526-ezbrd/config.mk +++ b/board/bf526-ezbrd/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk index f85bef5e2a..3f9d41f371 100644 --- a/board/bf527-ezkit/config.mk +++ b/board/bf527-ezkit/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index 3c0b46f721..bc046f129f 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index 3c0b46f721..bc046f129f 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c index e65c4f8359..317f088497 100644 --- a/board/bf537-stamp/cmd_bf537led.c +++ b/board/bf537-stamp/cmd_bf537led.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #ifdef CONFIG_BF537_STAMP_LEDCMD /* Define the command usage in a reusable way */ diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index bc14257489..5766829115 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk index 3c0b46f721..bc046f129f 100644 --- a/board/bf538f-ezkit/config.mk +++ b/board/bf538f-ezkit/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk index 42ff946673..ce96c0d479 100644 --- a/board/bf548-ezkit/config.mk +++ b/board/bf548-ezkit/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk index cfad21a2a4..a90b193388 100644 --- a/board/bf561-acvilon/config.mk +++ b/board/bf561-acvilon/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index cfad21a2a4..a90b193388 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds index 2d0efb3161..5bd5a75c61 100644 --- a/board/c2mon/u-boot.lds +++ b/board/c2mon/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug index ad36953915..e62f6be5aa 100644 --- a/board/c2mon/u-boot.lds.debug +++ b/board/c2mon/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index dce07bf785..6ddc858ea4 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -81,7 +81,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -183,57 +182,6 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { puts ("Board: CANMB\n"); diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h index ffdf0396a5..15477259ca 100644 --- a/board/canmb/mt48lc16m32s2-75.h +++ b/board/canmb/mt48lc16m32s2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk index f85bef5e2a..3f9d41f371 100644 --- a/board/cm-bf527/config.mk +++ b/board/cm-bf527/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk index 3c0b46f721..bc046f129f 100644 --- a/board/cm-bf533/config.mk +++ b/board/cm-bf533/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk index 3c0b46f721..bc046f129f 100644 --- a/board/cm-bf537e/config.mk +++ b/board/cm-bf537e/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk index 3c0b46f721..bc046f129f 100644 --- a/board/cm-bf537u/config.mk +++ b/board/cm-bf537u/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk index 0c95b39627..f071a39d75 100644 --- a/board/cm-bf548/config.mk +++ b/board/cm-bf548/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c index 80cfff7242..5741f64107 100644 --- a/board/cm-bf561/cm-bf561.c +++ b/board/cm-bf561/cm-bf561.c @@ -18,9 +18,9 @@ int checkboard(void) return 0; } -#ifdef CONFIG_SMC91111 +#ifdef CONFIG_SMC911X int board_eth_init(bd_t *bis) { - return smc91111_initialize(0, CONFIG_SMC91111_BASE); + return smc911x_initialize(0, CONFIG_SMC911X_BASE); } #endif diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk index cfad21a2a4..a90b193388 100644 --- a/board/cm-bf561/config.mk +++ b/board/cm-bf561/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/cm5200/u-boot.lds b/board/cm5200/u-boot.lds index 5887f774e9..30a37d9fb2 100644 --- a/board/cm5200/u-boot.lds +++ b/board/cm5200/u-boot.lds @@ -50,7 +50,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc5xxx/start.o (.text) + arch/ppc/cpu/mpc5xxx/start.o (.text) *(.text) *(.got1) . = ALIGN(16); diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index 7e716bb09a..ec0f5e9faa 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -54,12 +54,12 @@ SECTIONS { /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - cpu/mcf52x2/cpu_init.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/cpu/mcf52x2/cpu_init.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/cpu/mcf52x2/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index a2d940f048..57cc305868 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index 970628d556..09c0191e5f 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -57,9 +57,9 @@ SECTIONS mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) common/env_embedded.o(.text) diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index d6d65cf45c..5a00afe402 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -129,7 +129,7 @@ phys_size_t initdram (int board_type) /* * ToDo: Move the asm init routine sdram_init() to this C file, * or even better use some common ppc4xx code available - * in cpu/ppc4xx + * in arch/ppc/cpu/ppc4xx */ sdram_init(); diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 20d34adfdd..996a67b4ed 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -97,7 +97,7 @@ phys_size_t initdram (int board_type) /* * ToDo: Move the asm init routine sdram_init() to this C file, * or even better use some common ppc4xx code available - * in cpu/ppc4xx + * in arch/ppc/cpu/ppc4xx */ sdram_init(); diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c index ed668afccc..6385443666 100644 --- a/board/davinci/da830evm/da830evm.c +++ b/board/davinci/da830evm/da830evm.c @@ -150,7 +150,7 @@ int board_init(void) DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(2) | DAVINCI_ABCR_ASIZE_8BIT), - &davinci_emif_regs->AB2CR); + &davinci_emif_regs->ab2cr); #endif /* arch number of the board */ diff --git a/board/davinci/dvevm/board_init.S b/board/davinci/dvevm/board_init.S index 22d8adc18c..81b23d0436 100644 --- a/board/davinci/dvevm/board_init.S +++ b/board/davinci/dvevm/board_init.S @@ -2,7 +2,7 @@ * Copyright (C) 2007 Sergey Kubushyn * * Board-specific low level initialization code. Called at the very end - * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no * initialization required. * * This program is free software; you can redistribute it and/or diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S index 22d8adc18c..81b23d0436 100644 --- a/board/davinci/schmoogie/board_init.S +++ b/board/davinci/schmoogie/board_init.S @@ -2,7 +2,7 @@ * Copyright (C) 2007 Sergey Kubushyn * * Board-specific low level initialization code. Called at the very end - * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no * initialization required. * * This program is free software; you can redistribute it and/or diff --git a/board/davinci/sffsdr/board_init.S b/board/davinci/sffsdr/board_init.S index 22d8adc18c..81b23d0436 100644 --- a/board/davinci/sffsdr/board_init.S +++ b/board/davinci/sffsdr/board_init.S @@ -2,7 +2,7 @@ * Copyright (C) 2007 Sergey Kubushyn * * Board-specific low level initialization code. Called at the very end - * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no * initialization required. * * This program is free software; you can redistribute it and/or diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S index fbb9ea73e9..3e4c7a2c54 100644 --- a/board/davinci/sonata/board_init.S +++ b/board/davinci/sonata/board_init.S @@ -2,7 +2,7 @@ * Copyright (C) 2007 Sergey Kubushyn * * Board-specific low level initialization code. Called at the very end - * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no * initialization required. * * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index 42756f5b82..b3c6d512e7 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -37,7 +37,7 @@ phys_size_t initdram(int board_type) #define BCSR_PCMCIA_PC0DRVEN 0x0010 #define BCSR_PCMCIA_PC0RST 0x0080 -/* In cpu/mips/cpu.c */ +/* In arch/mips/cpu/cpu.c */ void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); int checkboard (void) diff --git a/board/eNET/config.mk b/board/eNET/config.mk index 5c64804fb2..dcde7fcedb 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -22,7 +22,7 @@ # TEXT_BASE = 0x38040000 -CFLAGS_dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing +CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing PLATFORM_RELFLAGS += -fvisibility=hidden PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk index b2fc6fac31..b627869c25 100644 --- a/board/edb93xx/config.mk +++ b/board/edb93xx/config.mk @@ -1,4 +1,4 @@ -LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds +LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds ifdef CONFIG_EDB9301 TEXT_BASE = 0x05700000 diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds index d021331148..6dff003dc1 100644 --- a/board/eltec/bab7xx/u-boot.lds +++ b/board/eltec/bab7xx/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/eltec/elppc/u-boot.lds b/board/eltec/elppc/u-boot.lds index d021331148..6dff003dc1 100644 --- a/board/eltec/elppc/u-boot.lds +++ b/board/eltec/elppc/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index 5c847fbf84..dc370eacf2 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index ad36953915..e62f6be5aa 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index 46dca96e60..3fb6d12692 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug index bfe85134e5..3229a23a3e 100644 --- a/board/emk/top860/u-boot.lds.debug +++ b/board/emk/top860/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index 70b84e4c8a..f9579a6430 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) . = ALIGN(16); diff --git a/board/eric/eric.c b/board/eric/eric.c index cfcfa525a9..96c0b8385d 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -132,7 +132,7 @@ phys_size_t initdram (int board_type) /* * ToDo: Move the asm init routine sdram_init() to this C file, * or even better use some common ppc4xx code available - * in cpu/ppc4xx + * in arch/ppc/cpu/ppc4xx */ sdram_init(); diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h index 22d0a55444..cf63806a58 100644 --- a/board/esd/cpci5200/mt46v16m16-75.h +++ b/board/esd/cpci5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds index d021331148..6dff003dc1 100644 --- a/board/esd/cpci750/u-boot.lds +++ b/board/esd/cpci750/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index b044649ebf..3d33d0f022 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S index 3cac6b11bb..afcf9c4a53 100644 --- a/board/esd/du440/init.S +++ b/board/esd/du440/init.S @@ -22,7 +22,7 @@ */ #include -#include +#include #include /* diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h index 22d0a55444..cf63806a58 100644 --- a/board/esd/mecp5200/mt46v16m16-75.h +++ b/board/esd/mecp5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h index 22d0a55444..cf63806a58 100644 --- a/board/esd/pf5200/mt46v16m16-75.h +++ b/board/esd/pf5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index 6585fed664..d51cd0cf05 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -20,7 +20,7 @@ */ #include -#include +#include #include /* diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index fb629e0c5e..8a71bfa44e 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -53,7 +53,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) /* Align to next NAND block */ . = ALIGN(0x4000); diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index e3230b9f20..d4fd705ce1 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/cpu/mcf52x2/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 3e4490ec49..4490f19a1f 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds index 1d34e68fd7..94b13422af 100644 --- a/board/etx094/u-boot.lds +++ b/board/etx094/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - cpu/mpc8xx/interrupts.o (.text) - cpu/mpc8xx/serial.o (.text) - cpu/mpc8xx/cpu_init.o (.text) - cpu/mpc8xx/speed.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/interrupts.o (.text) + arch/ppc/cpu/mpc8xx/serial.o (.text) + arch/ppc/cpu/mpc8xx/cpu_init.o (.text) + arch/ppc/cpu/mpc8xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/etx094/u-boot.lds.debug b/board/etx094/u-boot.lds.debug index 1af61fb2b5..458d4e076c 100644 --- a/board/etx094/u-boot.lds.debug +++ b/board/etx094/u-boot.lds.debug @@ -55,17 +55,17 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - cpu/mpc8xx/interrupts.o (.text) - cpu/mpc8xx/cpu.o (.text) - cpu/mpc8xx/cpu_init.o (.text) - cpu/mpc8xx/speed.o (.text) - cpu/mpc8xx/serial.o (.text) - lib_ppc/extable.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/string.o (.text) - lib_generic/crc32.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/interrupts.o (.text) + arch/ppc/cpu/mpc8xx/cpu.o (.text) + arch/ppc/cpu/mpc8xx/cpu_init.o (.text) + arch/ppc/cpu/mpc8xx/speed.o (.text) + arch/ppc/cpu/mpc8xx/serial.o (.text) + arch/ppc/lib/extable.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/string.o (.text) + lib/crc32.o (.text) common/dlmalloc.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index d021331148..6dff003dc1 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index ce3e32e0d5..d6476cdb71 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -50,7 +50,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) /*. = DEFINED(env_offset) ? env_offset : .;*/ common/env_embedded.o (.ppcenv) diff --git a/board/fads/u-boot.lds.debug b/board/fads/u-boot.lds.debug index 0a3b958fad..61c0d68d78 100644 --- a/board/fads/u-boot.lds.debug +++ b/board/fads/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index 877e82c84c..fbfba6ec9a 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index ad36953915..e62f6be5aa 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 02a824d9f4..620eb16d44 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -33,6 +33,7 @@ COBJS-${CONFIG_FSL_CADMUS} += cadmus.o COBJS-${CONFIG_FSL_VIA} += cds_via.o COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o COBJS-${CONFIG_FSL_PIXIS} += pixis.o +COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c new file mode 100644 index 0000000000..bb6794e859 --- /dev/null +++ b/board/freescale/common/ngpixis.c @@ -0,0 +1,136 @@ +/** + * Copyright 2010 Freescale Semiconductor + * Author: Timur Tabi + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + * + * A "switch" is black rectangular block on the motherboard. It contains + * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that + * shadow the actual physical switches. There is also another set of + * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be + * used to override the values of the bits in the physical switches. + * + * The following macros need to be defined: + * + * PIXIS_BASE - The virtual address of the base of the PIXIS register map + * + * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value + * is used in the PIXIS_SW() macro to determine which offset in + * the PIXIS register map corresponds to the physical switch that controls + * the boot bank. + * + * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use. + * + * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK. + * + * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to + * boot from the alternate bank. + */ + +#include +#include +#include +#include +#include + +#include "ngpixis.h" + +/* + * Reset the board. This ignores the ENx registers. + */ +void pixis_reset(void) +{ + out_8(&pixis->rst, 0); + + while (1); +} + +/* + * Reset the board. Like pixis_reset(), but it honors the ENx registers. + */ +void pixis_bank_reset(void) +{ + out_8(&pixis->vctl, 0); + out_8(&pixis->vctl, 1); + + while (1); +} + +/** + * Set the boot bank to the power-on default bank + */ +void clear_altbank(void) +{ + /* Tell the ngPIXIS to use this the bits in the physical switch for the + * boot bank value, instead of the SWx register. We need to be careful + * only to set the bits in SWx that correspond to the boot bank. + */ + clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK); +} + +/** + * Set the boot bank to the alternate bank + */ +void set_altbank(void) +{ + /* Program the alternate bank number into the SWx register. + */ + clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK, + PIXIS_LBMAP_ALTBANK); + + /* Tell the ngPIXIS to use this the bits in the SWx register for the + * boot bank value, instead of the physical switch. We need to be + * careful only to set the bits in SWx that correspond to the boot bank. + */ + setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK); +} + + +int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int i; + char *p_altbank = NULL; + char *unknown_param = NULL; + + /* No args is a simple reset request. + */ + if (argc <= 1) + pixis_reset(); + + for (i = 1; i < argc; i++) { + if (strcmp(argv[i], "altbank") == 0) { + p_altbank = argv[i]; + continue; + } + + unknown_param = argv[i]; + } + + if (unknown_param) { + printf("Invalid option: %s\n", unknown_param); + return 1; + } + + if (p_altbank) + set_altbank(); + else + clear_altbank(); + + pixis_bank_reset(); + + /* Shouldn't be reached. */ + return 0; +} + +U_BOOT_CMD( + pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, + "Reset the board using the FPGA sequencer", + "- hard reset to default bank\n" + "pixis_reset altbank - reset to alternate bank\n" + ); diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h new file mode 100644 index 0000000000..284d044c88 --- /dev/null +++ b/board/freescale/common/ngpixis.h @@ -0,0 +1,57 @@ +/** + * Copyright 2010 Freescale Semiconductor + * Author: Timur Tabi + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* ngPIXIS register set. Hopefully, this won't change too much over time. + * Feel free to add board-specific #ifdefs where necessary. + */ +typedef struct ngpixis { + u8 id; + u8 arch; + u8 scver; + u8 csr; + u8 rst; + u8 res1; + u8 aux; + u8 spd; + u8 brdcfg0; + u8 dma; + u8 addr; + u8 res2[2]; + u8 data; + u8 led; + u8 res3; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 res4; + u8 ocmcsr; + u8 ocmmsg; + u8 gmdbg; + u8 res5[2]; + u8 sclk[3]; + u8 dclk[3]; + u8 watch; + struct { + u8 sw; + u8 en; + } s[8]; +} ngpixis_t __attribute__ ((aligned(1))); + +/* Pointer to the PIXIS register set */ +#define pixis ((ngpixis_t *)PIXIS_BASE) + +/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */ +#define PIXIS_SW(x) (pixis->s[(x) - 1].sw) + +/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */ +#define PIXIS_EN(x) (pixis->s[(x) - 1].en) diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 7210512bfb..119eaf95af 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -1,5 +1,5 @@ /* - * Copyright 2006 Freescale Semiconductor + * Copyright 2006,2010 Freescale Semiconductor * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -24,33 +24,26 @@ #include #include -#include -#include #include -#include "pixis.h" - - -static ulong strfractoint(uchar *strptr); - +#define pixis_base (u8 *)PIXIS_BASE /* * Simple board reset. */ void pixis_reset(void) { - u8 *pixis_base = (u8 *)PIXIS_BASE; out_8(pixis_base + PIXIS_RST, 0); -} + while (1); +} /* * Per table 27, page 58 of MPC8641HPCN spec. */ -int set_px_sysclk(ulong sysclk) +static int set_px_sysclk(unsigned long sysclk) { u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; - u8 *pixis_base = (u8 *)PIXIS_BASE; switch (sysclk) { case 33: @@ -117,13 +110,13 @@ int set_px_sysclk(ulong sysclk) return 1; } - -int set_px_mpxpll(ulong mpxpll) +/* Set the CFG_SYSPLL bits + * + * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if + * read_from_px_regs() is called. + */ +static int set_px_mpxpll(unsigned long mpxpll) { - u8 tmp; - u8 val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - switch (mpxpll) { case 2: case 4: @@ -133,28 +126,19 @@ int set_px_mpxpll(ulong mpxpll) case 12: case 14: case 16: - val = (u8) mpxpll; - break; - default: - printf("Unsupported MPXPLL ratio.\n"); - return 0; + clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll); + return 1; } - tmp = in_8(pixis_base + PIXIS_VSPEED1); - tmp = (tmp & 0xF0) | (val & 0x0F); - out_8(pixis_base + PIXIS_VSPEED1, tmp); - - return 1; + printf("Unsupported MPXPLL ratio.\n"); + return 0; } - -int set_px_corepll(ulong corepll) +static int set_px_corepll(unsigned long corepll) { - u8 tmp; u8 val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - switch ((int)corepll) { + switch (corepll) { case 20: val = 0x08; break; @@ -178,113 +162,132 @@ int set_px_corepll(ulong corepll) return 0; } - tmp = in_8(pixis_base + PIXIS_VSPEED0); - tmp = (tmp & 0xE0) | (val & 0x1F); - out_8(pixis_base + PIXIS_VSPEED0, tmp); - + clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val); return 1; } +#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE +#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C +#endif -void read_from_px_regs(int set) +/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values + * + * The PIXIS can be programmed to look at either the on-board dip switches + * or various other PIXIS registers to determine the values for COREPLL, + * MPXPLL, and SYSCLK. + * + * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0 + * register that tells the pixis to use the various PIXIS register. + */ +static void read_from_px_regs(int set) { - u8 *pixis_base = (u8 *)PIXIS_BASE; - u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); if (set) - tmp = tmp | mask; + tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE; else - tmp = tmp & ~mask; + tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE; + out_8(pixis_base + PIXIS_VCFGEN0, tmp); } +/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1 + * register that tells the pixis to use the PX_VBOOT[LBMAP] register. + */ +#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE +#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04 +#endif -void read_from_px_regs_altbank(int set) +/* Configure the source of the boot location + * + * The PIXIS can be programmed to look at either the on-board dip switches + * or the PX_VBOOT[LBMAP] register to determine where we should boot. + * + * If we want to boot from the alternate boot bank, we need to tell the PIXIS + * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead. + */ +static void read_from_px_regs_altbank(int set) { - u8 *pixis_base = (u8 *)PIXIS_BASE; - u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); if (set) - tmp = tmp | mask; + tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE; else - tmp = tmp & ~mask; + tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE; + out_8(pixis_base + PIXIS_VCFGEN1, tmp); } +/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that + * tells the PIXIS what the alternate flash bank is. + * + * Note that it's not really a mask. It contains the actual LBMAP bits that + * must be set to select the alternate bank. This code assumes that the + * primary bank has these bits set to 0, and the alternate bank has these + * bits set to 1. + */ #ifndef CONFIG_SYS_PIXIS_VBOOT_MASK #define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40) #endif -void clear_altbank(void) +/* Tell the PIXIS to boot from the default flash bank + * + * Program the default flash bank into the VBOOT register. This register is + * used only if PX_VCFGEN1[FLASH]=1. + */ +static void clear_altbank(void) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - tmp = in_8(pixis_base + PIXIS_VBOOT); - tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK; - - out_8(pixis_base + PIXIS_VBOOT, tmp); + clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK); } - -void set_altbank(void) +/* Tell the PIXIS to boot from the alternate flash bank + * + * Program the alternate flash bank into the VBOOT register. This register is + * used only if PX_VCFGEN1[FLASH]=1. + */ +static void set_altbank(void) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - tmp = in_8(pixis_base + PIXIS_VBOOT); - tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK; - - out_8(pixis_base + PIXIS_VBOOT, tmp); + setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK); } - -void set_px_go(void) +/* Reset the board with watchdog disabled. + * + * This respects the altbank setting. + */ +static void set_px_go(void) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; + /* Disable the VELA sequencer and watchdog */ + clrbits_8(pixis_base + PIXIS_VCTL, 9); - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp & 0x1E; /* clear GO bit */ - out_8(pixis_base + PIXIS_VCTL, tmp); + /* Reboot by starting the VELA sequencer */ + setbits_8(pixis_base + PIXIS_VCTL, 0x1); - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp | 0x01; /* set GO bit - start reset sequencer */ - out_8(pixis_base + PIXIS_VCTL, tmp); + while (1); } - -void set_px_go_with_watchdog(void) +/* Reset the board with watchdog enabled. + * + * This respects the altbank setting. + */ +static void set_px_go_with_watchdog(void) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; + /* Disable the VELA sequencer */ + clrbits_8(pixis_base + PIXIS_VCTL, 1); - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp & 0x1E; - out_8(pixis_base + PIXIS_VCTL, tmp); + /* Enable the watchdog and reboot by starting the VELA sequencer */ + setbits_8(pixis_base + PIXIS_VCTL, 0x9); - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp | 0x09; - out_8(pixis_base + PIXIS_VCTL, tmp); + while (1); } - -int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, - int flag, int argc, char *argv[]) +/* Disable the watchdog + * + */ +static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char *argv[]) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp & 0x1E; - out_8(pixis_base + PIXIS_VCTL, tmp); - - /* setting VCTL[WDEN] to 0 to disable watch dog */ - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp &= ~0x08; - out_8(pixis_base + PIXIS_VCTL, tmp); + /* Disable the VELA sequencer and the watchdog */ + clrbits_8(pixis_base + PIXIS_VCTL, 9); return 0; } @@ -296,16 +299,17 @@ U_BOOT_CMD( ); #ifdef CONFIG_PIXIS_SGMII_CMD -int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + +/* Enable or disable SGMII mode for a TSEC + */ +static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int which_tsec = -1; - u8 *pixis_base = (u8 *)PIXIS_BASE; - uchar mask; - uchar switch_mask; + unsigned char mask; + unsigned char switch_mask; - if (argc > 2) - if (strcmp(argv[1], "all") != 0) - which_tsec = simple_strtoul(argv[1], NULL, 0); + if ((argc > 2) && (strcmp(argv[1], "all") != 0)) + which_tsec = simple_strtoul(argv[1], NULL, 0); switch (which_tsec) { #ifdef CONFIG_TSEC1 @@ -363,6 +367,7 @@ U_BOOT_CMD( " off - disables SGMII\n" " switch - use switch settings" ); + #endif /* @@ -371,14 +376,13 @@ U_BOOT_CMD( * FPGA register values. * input: strptr i.e. argv[2] */ - -static ulong strfractoint(uchar *strptr) +static unsigned long strfractoint(char *strptr) { - int i, j, retval; + int i, j; int mulconst; - int intarr_len = 0, decarr_len = 0, no_dec = 0; - ulong intval = 0, decval = 0; - uchar intarr[3], decarr[3]; + int intarr_len, no_dec = 0; + unsigned long intval = 0, decval = 0; + char intarr[3], decarr[3]; /* Assign the integer part to intarr[] * If there is no decimal point i.e. @@ -412,26 +416,21 @@ static ulong strfractoint(uchar *strptr) j++; } - decarr_len = j; decarr[j] = '\0'; mulconst = 1; - for (i = 0; i < decarr_len; i++) + for (i = 0; i < j; i++) mulconst *= 10; - decval = simple_strtoul((char *)decarr, NULL, 10); + decval = simple_strtoul(decarr, NULL, 10); } - intval = simple_strtoul((char *)intarr, NULL, 10); + intval = simple_strtoul(intarr, NULL, 10); intval = intval * mulconst; - retval = intval + decval; - - return retval; + return intval + decval; } - -int -pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { unsigned int i; char *p_cf = NULL; @@ -440,7 +439,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *p_cf_mpxpll = NULL; char *p_altbank = NULL; char *p_wd = NULL; - unsigned int unknown_param = 0; + int unknown_param = 0; /* * No args is a simple reset request. @@ -493,9 +492,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ read_from_px_regs(0); - if (p_altbank) { + if (p_altbank) read_from_px_regs_altbank(0); - } + clear_altbank(); /* @@ -507,7 +506,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) unsigned long mpxpll; sysclk = simple_strtoul(p_cf_sysclk, NULL, 10); - corepll = strfractoint((uchar *) p_cf_corepll); + corepll = strfractoint(p_cf_corepll); mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10); if (!(set_px_sysclk(sysclk) @@ -536,11 +535,10 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Reset with watchdog specified. */ - if (p_wd) { + if (p_wd) set_px_go_with_watchdog(); - } else { + else set_px_go(); - } /* * Shouldn't be reached. diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h deleted file mode 100644 index ff62a62c74..0000000000 --- a/board/freescale/common/pixis.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2006 Freescale Semiconductor - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -extern void pixis_reset(void); -extern int set_px_sysclk(ulong sysclk); -extern int set_px_mpxpll(ulong mpxpll); -extern int set_px_corepll(ulong corepll); -extern void read_from_px_regs(int set); -extern void read_from_px_regs_altbank(int set); -extern void set_altbank(void); -extern void set_px_go(void); -extern void set_px_go_with_watchdog(void); diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds index bc9d5cd0d6..507e21a03b 100644 --- a/board/freescale/m5208evbe/u-boot.lds +++ b/board/freescale/m5208evbe/u-boot.lds @@ -55,9 +55,9 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - cpu/mcf52x2/libmcf52x2.a (.text) - lib_m68k/libm68k.a (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/cpu/mcf52x2/libmcf52x2.a (.text) + arch/m68k/lib/libm68k.a (.text) common/dlmalloc.o (.text) . = DEFINED(env_offset) ? env_offset : .; diff --git a/board/freescale/m52277evb/u-boot.spa b/board/freescale/m52277evb/u-boot.spa index 7ae70d455f..4591196e68 100644 --- a/board/freescale/m52277evb/u-boot.spa +++ b/board/freescale/m52277evb/u-boot.spa @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf5227x/start.o (.text) - cpu/mcf5227x/libmcf5227x.a (.text) - lib_m68k/libm68k.a (.text) - lib_generic/libgeneric.a (.text) + arch/m68k/cpu/mcf5227x/start.o (.text) + arch/m68k/cpu/mcf5227x/libmcf5227x.a (.text) + arch/m68k/lib/libm68k.a (.text) + lib/libgeneric.a (.text) common/cmd_mem.o (.text) common/main.o (.text) diff --git a/board/freescale/m52277evb/u-boot.stm b/board/freescale/m52277evb/u-boot.stm index 03ff532964..1ec83e9490 100644 --- a/board/freescale/m52277evb/u-boot.stm +++ b/board/freescale/m52277evb/u-boot.stm @@ -55,7 +55,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf5227x/start.o (.text) + arch/m68k/cpu/mcf5227x/start.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m5235evb/u-boot.16 b/board/freescale/m5235evb/u-boot.16 index c134884375..d7bd10fd96 100644 --- a/board/freescale/m5235evb/u-boot.16 +++ b/board/freescale/m5235evb/u-boot.16 @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf523x/start.o (.text) - cpu/mcf523x/cpu_init.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + arch/m68k/cpu/mcf523x/start.o (.text) + arch/m68k/cpu/mcf523x/cpu_init.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/lib/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m5235evb/u-boot.32 b/board/freescale/m5235evb/u-boot.32 index 53c337df89..45ff158905 100644 --- a/board/freescale/m5235evb/u-boot.32 +++ b/board/freescale/m5235evb/u-boot.32 @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf523x/start.o (.text) - cpu/mcf523x/cpu.o (.text) - cpu/mcf523x/cpu_init.o (.text) - cpu/mcf523x/interrupts.o (.text) - cpu/mcf523x/speed.o (.text) - lib_m68k/libm68k.a (.text) + arch/m68k/cpu/mcf523x/start.o (.text) + arch/m68k/cpu/mcf523x/cpu.o (.text) + arch/m68k/cpu/mcf523x/cpu_init.o (.text) + arch/m68k/cpu/mcf523x/interrupts.o (.text) + arch/m68k/cpu/mcf523x/speed.o (.text) + arch/m68k/lib/libm68k.a (.text) common/dlmalloc.o (.text) common/cmd_bootm.o (.text) common/cmd_flash.o (.text) @@ -68,7 +68,7 @@ SECTIONS common/cmd_mem.o (.text) common/console.o (.text) common/main.o (.text) - lib_generic/libgeneric.a (.text) + lib/libgeneric.a (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds index e3230b9f20..d4fd705ce1 100644 --- a/board/freescale/m5249evb/u-boot.lds +++ b/board/freescale/m5249evb/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/cpu/mcf52x2/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds index 6cb5ee05f3..4f8bb20d45 100644 --- a/board/freescale/m5253demo/u-boot.lds +++ b/board/freescale/m5253demo/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/cpu/mcf52x2/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds index 132fccf104..797c83785c 100644 --- a/board/freescale/m5253evbe/u-boot.lds +++ b/board/freescale/m5253evbe/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/cpu/mcf52x2/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c index 5505cc42c6..446f102e58 100644 --- a/board/freescale/m5271evb/m5271evb.c +++ b/board/freescale/m5271evb/m5271evb.c @@ -47,6 +47,7 @@ phys_size_t initdram (int board_type) { MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | MCF_GPIO_SDRAM_SDCS_11); + asm(" nop"); /* * Check to see if the SDRAM has already been initialized @@ -55,8 +56,9 @@ phys_size_t initdram (int board_type) { if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { /* Initialize DRAM Control Register: DCR */ mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(0x01) - | MCF_SDRAMC_DCR_RC(0x30)); + MCF_SDRAMC_DCR_RTIM(2) + | MCF_SDRAMC_DCR_RC(0x2E)); + asm(" nop"); /* * Initialize DACR0 @@ -70,15 +72,18 @@ phys_size_t initdram (int board_type) { | MCF_SDRAMC_DACRn_CASL(1) | MCF_SDRAMC_DACRn_CBM(3) | MCF_SDRAMC_DACRn_PS(0)); + asm(" nop"); /* Initialize DMR0 */ mbar_writeLong(MCF_SDRAMC_DMR0, MCF_SDRAMC_DMRn_BAM_16M | MCF_SDRAMC_DMRn_V); + asm(" nop"); /* Set IP bit in DACR */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | MCF_SDRAMC_DACRn_IP); + asm(" nop"); /* Wait at least 20ns to allow banks to precharge */ for (i = 0; i < 5; i++) @@ -86,6 +91,7 @@ phys_size_t initdram (int board_type) { /* Write to this block to initiate precharge */ *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + asm(" nop"); /* Set RE bit in DACR */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) @@ -98,6 +104,7 @@ phys_size_t initdram (int board_type) { /* Finish the configuration by issuing the MRS */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | MCF_SDRAMC_DACRn_MRS); + asm(" nop"); /* * Write to the SDRAM Mode Register A0-A11 = 0x400 @@ -109,6 +116,7 @@ phys_size_t initdram (int board_type) { * Burst Length = 1 */ *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5; + asm(" nop"); } return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds index 00c1f2a52e..ca41232c64 100644 --- a/board/freescale/m5271evb/u-boot.lds +++ b/board/freescale/m5271evb/u-boot.lds @@ -56,11 +56,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/cpu/mcf52x2/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds index 9d20b228cb..8b011df532 100644 --- a/board/freescale/m5272c3/u-boot.lds +++ b/board/freescale/m5272c3/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/cpu/mcf52x2/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds index daf8724ae2..cd17b0abf2 100644 --- a/board/freescale/m5275evb/u-boot.lds +++ b/board/freescale/m5275evb/u-boot.lds @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) common/dlmalloc.o (.text) - lib_generic/string.o (.text) - lib_generic/zlib.o (.text) + lib/string.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o(.text) diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index f46e0251ef..5ad0fad684 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) common/dlmalloc.o (.text) - lib_generic/string.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/string.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o(.text) diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index c79d06c64a..6577299c25 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf532x/start.o (.text) - cpu/mcf532x/libmcf532x.a (.text) - lib_m68k/libm68k.a (.text) + arch/m68k/cpu/mcf532x/start.o (.text) + arch/m68k/cpu/mcf532x/libmcf532x.a (.text) + arch/m68k/lib/libm68k.a (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds index af310988ff..ba7ca27733 100644 --- a/board/freescale/m5329evb/u-boot.lds +++ b/board/freescale/m5329evb/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf532x/start.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + arch/m68k/cpu/mcf532x/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/lib/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds index dff74b6543..a2540bbc74 100644 --- a/board/freescale/m5373evb/u-boot.lds +++ b/board/freescale/m5373evb/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf532x/start.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + arch/m68k/cpu/mcf532x/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/lib/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m54451evb/u-boot.spa b/board/freescale/m54451evb/u-boot.spa index d8caefad64..09ac481dd1 100644 --- a/board/freescale/m54451evb/u-boot.spa +++ b/board/freescale/m54451evb/u-boot.spa @@ -55,14 +55,14 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf5445x/start.o (.text) - cpu/mcf5445x/libmcf5445x.a (.text) - lib_m68k/libm68k.a (.text) + arch/m68k/cpu/mcf5445x/start.o (.text) + arch/m68k/cpu/mcf5445x/libmcf5445x.a (.text) + arch/m68k/lib/libm68k.a (.text) common/cmd_flash.o (.text) common/dlmalloc.o (.text) common/main.o (.text) common/image.o (.text) - lib_generic/libgeneric.a (.text) + lib/libgeneric.a (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m54451evb/u-boot.stm b/board/freescale/m54451evb/u-boot.stm index e9eac67b90..e64a56c59b 100644 --- a/board/freescale/m54451evb/u-boot.stm +++ b/board/freescale/m54451evb/u-boot.stm @@ -55,16 +55,16 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf5445x/start.o (.text) -/* cpu/mcf5445x/cpu_init.o (.text) - cpu/mcf5445x/cpu.o (.text) - cpu/mcf5445x/dspi.o (.text) - cpu/mcf5445x/interrupt.o (.text) - cpu/mcf5445x/speed.o (.text) - lib_m68k/board.o (.text) + arch/m68k/cpu/mcf5445x/start.o (.text) +/* arch/m68k/cpu/mcf5445x/cpu_init.o (.text) + arch/m68k/cpu/mcf5445x/cpu.o (.text) + arch/m68k/cpu/mcf5445x/dspi.o (.text) + arch/m68k/cpu/mcf5445x/interrupt.o (.text) + arch/m68k/cpu/mcf5445x/speed.o (.text) + arch/m68k/lib/board.o (.text) common/serial.o (.text) common/console.o (.text) - lib_generic/display_options.o (.text) + lib/display_options.o (.text) board/freescale/m54455evb/m54455evb.o (.text) . = DEFINED(env_offset) ? env_offset : .; diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 293b5b0e41..2a84514a3d 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -107,7 +107,7 @@ int ide_preinit(void) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10; + gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; gpio->par_feci2c |= (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); @@ -185,7 +185,7 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) info->flash_id = 0x01000000; info->portwidth = 1; info->chipwidth = 1; - info->buffer_size = 32; + info->buffer_size = 1; info->erase_blk_tout = 16384; info->write_tout = 2; info->buffer_write_tout = 5; diff --git a/board/freescale/m54455evb/u-boot.atm b/board/freescale/m54455evb/u-boot.atm index 08e184c1e6..ebf801ac71 100644 --- a/board/freescale/m54455evb/u-boot.atm +++ b/board/freescale/m54455evb/u-boot.atm @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf5445x/start.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + arch/m68k/cpu/mcf5445x/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/lib/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/freescale/m54455evb/u-boot.int b/board/freescale/m54455evb/u-boot.int index 4d504a22f1..153556fe9b 100644 --- a/board/freescale/m54455evb/u-boot.int +++ b/board/freescale/m54455evb/u-boot.int @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf5445x/start.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + arch/m68k/cpu/mcf5445x/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/lib/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m54455evb/u-boot.stm b/board/freescale/m54455evb/u-boot.stm index 3dd9a6b047..9cda1029d3 100644 --- a/board/freescale/m54455evb/u-boot.stm +++ b/board/freescale/m54455evb/u-boot.stm @@ -55,7 +55,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf5445x/start.o (.text) + arch/m68k/cpu/mcf5445x/start.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds index a3014bd104..54bf2785aa 100644 --- a/board/freescale/m547xevb/u-boot.lds +++ b/board/freescale/m547xevb/u-boot.lds @@ -55,9 +55,9 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf547x_8x/start.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + arch/m68k/cpu/mcf547x_8x/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/lib/interrupts.o (.text) common/dlmalloc.o (.text) . = DEFINED(env_offset) ? env_offset : .; diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds index a3014bd104..54bf2785aa 100644 --- a/board/freescale/m548xevb/u-boot.lds +++ b/board/freescale/m548xevb/u-boot.lds @@ -55,9 +55,9 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf547x_8x/start.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + arch/m68k/cpu/mcf547x_8x/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/lib/interrupts.o (.text) common/dlmalloc.o (.text) . = DEFINED(env_offset) ? env_offset : .; diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c index 74bb564ed9..c6a3ade2c3 100644 --- a/board/freescale/mpc7448hpc2/tsi108_init.c +++ b/board/freescale/mpc7448hpc2/tsi108_init.c @@ -323,7 +323,7 @@ int board_early_init_r (void) * We will over-ride the env_init called in board_init_f * This is really a work-around because, the HLP bank 1 * where NVRAM resides is not visible during board_init_f - * (lib_ppc/board.c) + * (arch/ppc/lib/board.c) * Alternatively, we could use the I2C EEPROM at start-up to configure * and enable all HLP banks and not just HLP 0 as is being done for * Taiga Rev. 2. diff --git a/board/freescale/mpc7448hpc2/u-boot.lds b/board/freescale/mpc7448hpc2/u-boot.lds index 247779f6c2..c4266cec50 100644 --- a/board/freescale/mpc7448hpc2/u-boot.lds +++ b/board/freescale/mpc7448hpc2/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index e38af731be..3f5447a436 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -26,7 +26,7 @@ ifndef NAND_SPL ifeq ($(CONFIG_MK_NAND), y) TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) -LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds endif endif diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 81a56b55e0..253ed181fc 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -39,7 +39,6 @@ #include #include -#include "../common/pixis.h" #include "../common/sgmii_riser.h" phys_size_t fixed_sdram(void); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index b35e02f685..0be2d892d3 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -35,7 +35,6 @@ #include #include -#include "../common/pixis.h" #include "../common/sgmii_riser.h" int checkboard (void) diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk index 7de0f7cf7d..86f138c19c 100644 --- a/board/freescale/mpc8569mds/config.mk +++ b/board/freescale/mpc8569mds/config.mk @@ -26,7 +26,7 @@ ifndef NAND_SPL ifeq ($(CONFIG_MK_NAND), y) TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) -LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds endif endif diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 74085c3260..6029a5185c 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -36,7 +36,6 @@ #include #include -#include "../common/pixis.h" #include "../common/sgmii_riser.h" long int fixed_sdram(void); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 784a2ed686..2ef7b2323d 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -34,8 +34,6 @@ #include #include -#include "../common/pixis.h" - void sdram_init(void); phys_size_t fixed_sdram(void); void mpc8610hpcd_diu_init(void); @@ -127,6 +125,8 @@ initdram(int board_type) dram_size = fixed_sdram(); #endif + setup_ddr_bat(dram_size); + puts(" DDR: "); return dram_size; } diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index 4186a2ecda..94fb1ebf8f 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -29,7 +29,6 @@ #ifdef CONFIG_FSL_DIU_FB -#include "../common/pixis.h" #include "../common/fsl_diu_fb.h" #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds index b573807fe9..1f9f8eb949 100644 --- a/board/freescale/mpc8610hpcd/u-boot.lds +++ b/board/freescale/mpc8610hpcd/u-boot.lds @@ -50,16 +50,16 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc86xx/start.o (.text) - cpu/mpc86xx/traps.o (.text) - cpu/mpc86xx/interrupts.o (.text) - cpu/mpc86xx/cpu_init.o (.text) - cpu/mpc86xx/cpu.o (.text) - cpu/mpc86xx/speed.o (.text) + arch/ppc/cpu/mpc86xx/start.o (.text) + arch/ppc/cpu/mpc86xx/traps.o (.text) + arch/ppc/cpu/mpc86xx/interrupts.o (.text) + arch/ppc/cpu/mpc86xx/cpu_init.o (.text) + arch/ppc/cpu/mpc86xx/cpu.o (.text) + arch/ppc/cpu/mpc86xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) *(.text) *(.got1) } diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index c521527d89..b352c334cf 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -31,8 +31,6 @@ #include #include -#include "../common/pixis.h" - phys_size_t fixed_sdram(void); int board_early_init_f(void) @@ -74,6 +72,8 @@ initdram(int board_type) dram_size = fixed_sdram(); #endif + setup_ddr_bat(dram_size); + puts(" DDR: "); return dram_size; } diff --git a/board/freescale/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds index 2b98b5a9cc..d7c65ce217 100644 --- a/board/freescale/mpc8641hpcn/u-boot.lds +++ b/board/freescale/mpc8641hpcn/u-boot.lds @@ -50,16 +50,16 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc86xx/start.o (.text) - cpu/mpc86xx/traps.o (.text) - cpu/mpc86xx/interrupts.o (.text) - cpu/mpc86xx/cpu_init.o (.text) - cpu/mpc86xx/cpu.o (.text) - cpu/mpc86xx/speed.o (.text) + arch/ppc/cpu/mpc86xx/start.o (.text) + arch/ppc/cpu/mpc86xx/traps.o (.text) + arch/ppc/cpu/mpc86xx/interrupts.o (.text) + arch/ppc/cpu/mpc86xx/cpu_init.o (.text) + arch/ppc/cpu/mpc86xx/cpu.o (.text) + arch/ppc/cpu/mpc86xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) drivers/bios_emulator/atibios.o (.text) *(.text) *(.got1) diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 3182aa675e..273129457b 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -37,9 +37,9 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/arm1136/start.o (.text) + arch/arm/cpu/arm1136/start.o (.text) board/freescale/mx31ads/libmx31ads.a (.text) - lib_arm/libarm.a (.text) + arch/arm/lib/libarm.a (.text) net/libnet.a (.text) drivers/mtd/libmtd.a (.text) diff --git a/board/freescale/mx51evk/config.mk b/board/freescale/mx51evk/config.mk index c8279ec8cb..af70ec250f 100644 --- a/board/freescale/mx51evk/config.mk +++ b/board/freescale/mx51evk/config.mk @@ -20,6 +20,6 @@ # MA 02111-1307 USA # -LDSCRIPT = cpu/$(CPU)/$(SOC)/u-boot.lds +LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds TEXT_BASE = 0x97800000 IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 8754563802..f0b7abcf52 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -72,72 +72,6 @@ static void setup_iomux_uart(void) mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); } -static void setup_expio(void) -{ - u32 reg; - struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; - struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR; - - /* CS5 setup */ - mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0); - writel(0x00410089, &pweim[5].csgcr1); - writel(0x00000002, &pweim[5].csgcr2); - - /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ - writel(0x32260000, &pweim[5].csrcr1); - - /* APR = 0 */ - writel(0x00000000, &pweim[5].csrcr2); - - /* - * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, - * WCSA=0, WCSN=0 - */ - writel(0x72080F00, &pweim[5].cswcr1); - - mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR + - IO_BOARD_OFFSET); - if ((readw(&mx51_io_board->id1) == 0xAAAA) && - (readw(&mx51_io_board->id2) == 0x5555)) { - if (is_soc_rev(CHIP_REV_2_0) < 0) { - reg = readl(&pclkctl->cbcdr); - reg = (reg & (~0x70000)) | 0x30000; - writel(reg, &pclkctl->cbcdr); - /* make sure divider effective */ - while (readl(&pclkctl->cdhipr) != 0) - ; - writel(0x0, &pclkctl->ccdr); - } - } else { - /* CS1 */ - writel(0x00410089, &pweim[1].csgcr1); - writel(0x00000002, &pweim[1].csgcr2); - /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ - writel(0x32260000, &pweim[1].csrcr1); - /* APR=0 */ - writel(0x00000000, &pweim[1].csrcr2); - /* - * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, - * WEN=0, WCSA=0, WCSN=0 - */ - writel(0x72080F00, &pweim[1].cswcr1); - mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR + - IO_BOARD_OFFSET); - } - - /* Reset interrupt status reg */ - writew(0x1F, &(mx51_io_board->int_rest)); - writew(0x00, &(mx51_io_board->int_rest)); - writew(0xFFFF, &(mx51_io_board->int_mask)); - - /* Reset the XUART and Ethernet controllers */ - reg = readw(&(mx51_io_board->sw_reset)); - reg |= 0x9; - writew(reg, &(mx51_io_board->sw_reset)); - reg &= ~0x9; - writew(reg, &(mx51_io_board->sw_reset)); -} - static void setup_iomux_fec(void) { /*FEC_MDIO*/ @@ -349,7 +283,6 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; setup_iomux_uart(); - setup_expio(); setup_iomux_fec(); return 0; } diff --git a/board/freescale/mx51evk/mx51evk.h b/board/freescale/mx51evk/mx51evk.h index 524cdcced4..2854e71e8d 100644 --- a/board/freescale/mx51evk/mx51evk.h +++ b/board/freescale/mx51evk/mx51evk.h @@ -47,5 +47,4 @@ struct io_board_ctrl { }; #endif -#define IO_BOARD_OFFSET (0x20000) #endif diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk index 0f7a0487e0..1f9f7b68a2 100644 --- a/board/freescale/p1_p2_rdb/config.mk +++ b/board/freescale/p1_p2_rdb/config.mk @@ -27,7 +27,7 @@ ifndef NAND_SPL ifeq ($(CONFIG_MK_NAND), y) TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) -LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds endif endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index f6eae55d1d..f0ff209c0c 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -38,7 +38,7 @@ #include #include -#include "../common/pixis.h" +#include "../common/ngpixis.h" #include "../common/sgmii_riser.h" DECLARE_GLOBAL_DATA_PTR; @@ -47,30 +47,24 @@ phys_size_t fixed_sdram(void); int checkboard(void) { - u8 sw7; - u8 *pixis_base = (u8 *)PIXIS_BASE; + u8 sw; puts("Board: P2020DS "); #ifdef CONFIG_PHYS_64BIT puts("(36-bit addrmap) "); #endif - printf("Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); - sw7 = in_8(pixis_base + PIXIS_SW(7)); - switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) { - case 0: - case 1: - printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4)); - break; - case 2: - case 3: - puts ("Promjet\n"); - break; - } + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + /* The lower two bits are the actual vbank number */ + printf("vBank: %d\n", sw & 3); + else + puts("Promjet\n"); return 0; } @@ -371,30 +365,22 @@ unsigned long get_board_ddr_clk(ulong dummy) return gd->mem_clk; } -unsigned long -calculate_board_sys_clk(ulong dummy) +unsigned long calculate_board_sys_clk(ulong dummy) { ulong val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - val = ics307_clk_freq( - in_8(pixis_base + PIXIS_VSYSCLK0), - in_8(pixis_base + PIXIS_VSYSCLK1), - in_8(pixis_base + PIXIS_VSYSCLK2)); + val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]), + in_8(&pixis->sclk[2])); debug("sysclk val = %lu\n", val); return val; } -unsigned long -calculate_board_ddr_clk(ulong dummy) +unsigned long calculate_board_ddr_clk(ulong dummy) { ulong val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - val = ics307_clk_freq( - in_8(pixis_base + PIXIS_VDDRCLK0), - in_8(pixis_base + PIXIS_VDDRCLK1), - in_8(pixis_base + PIXIS_VDDRCLK2)); + val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]), + in_8(&pixis->dclk[2])); debug("ddrclk val = %lu\n", val); return val; } @@ -403,9 +389,8 @@ unsigned long get_board_sys_clk(ulong dummy) { u8 i; ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in_8(pixis_base + PIXIS_SPD); + i = in_8(&pixis->spd); i &= 0x07; switch (i) { @@ -442,9 +427,8 @@ unsigned long get_board_ddr_clk(ulong dummy) { u8 i; ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in_8(pixis_base + PIXIS_SPD); + i = in_8(&pixis->spd); i &= 0x38; i >>= 3; diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds index d5d7842157..22826823cc 100644 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS _text = .; *(.start) - cpu/leon3/start.o (.text) + arch/sparc/cpu/leon3/start.o (.text) /* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds index 99aa0addaf..0ca2651703 100644 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ b/board/gaisler/gr_ep2s60/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS _text = .; *(.start) - cpu/leon3/start.o (.text) + arch/sparc/cpu/leon3/start.o (.text) /* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds index 3b13190cb0..67222ac8e3 100644 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ b/board/gaisler/gr_xc3s_1500/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS _text = .; *(.start) - cpu/leon3/start.o (.text) + arch/sparc/cpu/leon3/start.o (.text) /* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds index 0fa6627df5..681fd8d01b 100644 --- a/board/gaisler/grsim/u-boot.lds +++ b/board/gaisler/grsim/u-boot.lds @@ -59,7 +59,7 @@ SECTIONS _text = .; *(.start) - cpu/leon3/start.o (.text) + arch/sparc/cpu/leon3/start.o (.text) /* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds index c5311a6c1f..a12e7fb9ce 100644 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ b/board/gaisler/grsim_leon2/u-boot.lds @@ -59,7 +59,7 @@ SECTIONS _text = .; *(.start) - cpu/leon2/start.o (.text) + arch/sparc/cpu/leon2/start.o (.text) /* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c index 5aa9d3a6f1..d4a2245b2b 100644 --- a/board/galaxy5200/galaxy5200.c +++ b/board/galaxy5200/galaxy5200.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #ifndef CONFIG_SYS_RAMBOOT static void sdram_start(int hi_addr) diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S index e205c9d7e8..a8e8b6c1c2 100644 --- a/board/gdsys/intip/init.S +++ b/board/gdsys/intip/init.S @@ -27,7 +27,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c index d8c3006a6b..146573e1df 100644 --- a/board/gen860t/ioport.c +++ b/board/gen860t/ioport.c @@ -197,7 +197,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* * Configure the MPC8XX I/O ports per the ioport configuration table - * (taken from ./cpu/mpc8260/cpu_init.c) + * (taken from ./arch/ppc/cpu/mpc8260/cpu_init.c) */ void config_mpc8xx_ioports (volatile immap_t * immr) { diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index 7b83b25b65..0e129253e7 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -55,7 +55,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) } diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index 8f40b303bf..d184379dbc 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -54,7 +54,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) } diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 716efcdd0b..22ada9ae1d 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index 3568e6de69..e5aa625b5c 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds index f6175d9d57..0e68e14142 100644 --- a/board/gth/u-boot.lds +++ b/board/gth/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o(.text) + arch/ppc/cpu/mpc8xx/start.o(.text) *(.text) common/env_embedded.o(.text) *(.got1) diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c index 59873d5ef6..8c3b55af42 100644 --- a/board/gth2/gth2.c +++ b/board/gth2/gth2.c @@ -93,7 +93,7 @@ phys_size_t initdram(int board_type) return (SDRAM_SIZE); } -/* In cpu/mips/cpu.c */ +/* In arch/mips/cpu/cpu.c */ void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); void set_ledcard(u32 value){ diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index 7b74cb7d5f..23e3e3bc5e 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -55,13 +55,13 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) - lib_ppc/cache.o (.text) - lib_generic/crc32.o (.text) + arch/ppc/cpu/mpc8xx/interrupts.o (.text) + arch/ppc/lib/time.o (.text) + arch/ppc/lib/ticks.o (.text) + arch/ppc/lib/cache.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index 3801206931..47e3927ec6 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - lib_ppc/ppcstring.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/lib/ppcstring.o (.text) + arch/ppc/cpu/mpc8xx/interrupts.o (.text) + arch/ppc/lib/time.o (.text) + arch/ppc/lib/ticks.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/hmi1001/config.mk b/board/hmi1001/config.mk index 4fe18316e5..aebf30411e 100644 --- a/board/hmi1001/config.mk +++ b/board/hmi1001/config.mk @@ -39,4 +39,4 @@ TEXT_BASE = 0xFFF00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board -LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 52d66a2df3..7086ced348 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -55,13 +55,13 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8260/start.o (.text) + arch/ppc/cpu/mpc8260/start.o (.text) /* common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; */ diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index a2d940f048..57cc305868 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 75244610cf..47b2195557 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -134,7 +134,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -258,65 +257,12 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined (CONFIG_LITE5200B) puts ("Board: Freescale Lite5200B\n"); -#elif defined(CONFIG_MPC5200) +#else puts ("Board: Motorola MPC5200 (IceCube)\n"); -#elif defined(CONFIG_MGT5100) - puts ("Board: Motorola MGT5100 (IceCube)\n"); #endif return 0; } @@ -329,10 +275,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h index 4c0f9a7406..eb857404f1 100644 --- a/board/icecube/mt46v16m16-75.h +++ b/board/icecube/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h index de2b48bc60..519bf6d0f0 100644 --- a/board/icecube/mt46v32m16.h +++ b/board/icecube/mt46v32m16.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h index ffdf0396a5..15477259ca 100644 --- a/board/icecube/mt48lc16m16a2-75.h +++ b/board/icecube/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index b43be81b69..d6837005f6 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -55,14 +55,14 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) /* - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 653e0be45c..b331d5afc1 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds index 00c1f2a52e..ca41232c64 100644 --- a/board/idmr/u-boot.lds +++ b/board/idmr/u-boot.lds @@ -56,11 +56,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) + arch/m68k/cpu/mcf52x2/start.o (.text) + arch/m68k/lib/traps.o (.text) + arch/m68k/cpu/mcf52x2/interrupts.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/inka4x0/config.mk b/board/inka4x0/config.mk index fc70efeeed..761efa1d17 100644 --- a/board/inka4x0/config.mk +++ b/board/inka4x0/config.mk @@ -39,4 +39,4 @@ TEXT_BASE = 0xFFE00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board -LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds diff --git a/board/ip04/Makefile b/board/ip04/Makefile new file mode 100644 index 0000000000..e7ce304f13 --- /dev/null +++ b/board/ip04/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2010 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ip04/config.mk b/board/ip04/config.mk new file mode 100644 index 0000000000..bc14257489 --- /dev/null +++ b/board/ip04/config.mk @@ -0,0 +1,35 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c new file mode 100644 index 0000000000..c8ae5128b0 --- /dev/null +++ b/board/ip04/ip04.c @@ -0,0 +1,42 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2007 David Rowe, + * (c) 2006 Ivan Danov + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include + +int checkboard(void) +{ + printf("Board: IP04 IP-PBX\n"); + printf(" http://www.rowetel.com/ucasterisk/ip04.html\n"); + return 0; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} + +int misc_init_r(void) +{ + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(enetaddr); + eth_setenv_enetaddr("ethaddr", enetaddr); + } + + return 0; +} +#endif diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index a786bf23e1..d856042373 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) + arch/ppc/lib/ppcstring.o (.text) + arch/ppc/cpu/mpc8xx/interrupts.o (.text) + arch/ppc/lib/time.o (.text) + arch/ppc/lib/ticks.o (.text) /** . = env_offset; common/env_embedded.o(.text) diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index dc2f6e12f5..dd39b9ac79 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - lib_ppc/ppcstring.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/lib/ppcstring.o (.text) + arch/ppc/cpu/mpc8xx/interrupts.o (.text) + arch/ppc/lib/time.o (.text) + arch/ppc/lib/ticks.o (.text) /** . = env_offset; common/env_embedded.o(.text) diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index 8d7ff70117..767408b52b 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) *(.got1) diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index b5206c50fd..5ec82f441d 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/jse/jse.c b/board/jse/jse.c index 1849ca47d7..e4c7b9dd94 100644 --- a/board/jse/jse.c +++ b/board/jse/jse.c @@ -26,7 +26,7 @@ /* * This function is run very early, out of flash, and before devices are - * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue * of being in the init_sequence array. * * The SDRAM has been initialized already -- start.S:start called @@ -85,7 +85,7 @@ int board_pre_init (void) #endif /* - * This function is also called by lib_ppc/board.c:board_init_f (it is + * This function is also called by arch/ppc/lib/board.c:board_init_f (it is * also in the init_sequence array) but later. Many more things are * configured, but we are still running from flash. */ @@ -149,7 +149,7 @@ int checkboard (void) /* **** No more functions called by board_init_f. **** */ /* - * This function is called by lib_ppc/board.c:board_init_r. At this + * This function is called by arch/ppc/lib/board.c:board_init_r. At this * point, basic setup is done, U-Boot has been moved into SDRAM and * PCI has been set up. From here we done late setup. */ diff --git a/board/jse/sdram.c b/board/jse/sdram.c index 88fdd84130..a12ebde236 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -27,7 +27,7 @@ /* * this is even after checkboard. It returns the size of the SDRAM * that we have installed. This function is called by board_init_f - * in lib_ppc/board.c to initialize the memory and return what I + * in arch/ppc/lib/board.c to initialize the memory and return what I * found. */ phys_size_t initdram (int board_type) diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index 6e752c6554..967aabdcfa 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -227,10 +227,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } @@ -248,10 +244,8 @@ void flash_afterinit(ulong size) *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } -#if defined(CONFIG_MPC5200) *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif } int update_flash_size (int flash_size) diff --git a/board/keymile/common/keymile_hdlc_enet.c b/board/keymile/common/keymile_hdlc_enet.c index 2e913adc55..ceddaf752e 100644 --- a/board/keymile/common/keymile_hdlc_enet.c +++ b/board/keymile/common/keymile_hdlc_enet.c @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. * - * Based in part on cpu/mpc8260/ether_scc.c. + * Based in part on arch/ppc/cpu/mpc8260/ether_scc.c. * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/keymile/km8xx/km8xx_hdlc_enet.c b/board/keymile/km8xx/km8xx_hdlc_enet.c index 9b93131f0c..543deafb9e 100644 --- a/board/keymile/km8xx/km8xx_hdlc_enet.c +++ b/board/keymile/km8xx/km8xx_hdlc_enet.c @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. * - * Based in part on cpu/mpc8xx/scc.c. + * Based in part on arch/ppc/cpu/mpc8xx/scc.c. * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/keymile/km8xx/u-boot.lds b/board/keymile/km8xx/u-boot.lds index a8057f225b..19936bd4b1 100644 --- a/board/keymile/km8xx/u-boot.lds +++ b/board/keymile/km8xx/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/keymile/mgcoge/mgcoge_hdlc_enet.c b/board/keymile/mgcoge/mgcoge_hdlc_enet.c index 34f04f5626..6b8e7eaf7e 100644 --- a/board/keymile/mgcoge/mgcoge_hdlc_enet.c +++ b/board/keymile/mgcoge/mgcoge_hdlc_enet.c @@ -2,7 +2,7 @@ * (C) Copyright 2008 * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. * - * Based in part on cpu/mpc8260/ether_scc.c. + * Based in part on arch/ppc/cpu/mpc8260/ether_scc.c. * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/korat/init.S b/board/korat/init.S index ea43a1f898..c725bbbb44 100644 --- a/board/korat/init.S +++ b/board/korat/init.S @@ -20,7 +20,7 @@ */ #include -#include +#include #include /************************************************************************** diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index cbad8668e3..e483394539 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -33,7 +33,7 @@ SECTIONS .bootpg 0xF7FBF000 : { - cpu/ppc4xx/start.o (.bootpg) + arch/ppc/cpu/ppc4xx/start.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -65,7 +65,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) *(.text) *(.got1) diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index 79b886af21..18cecaf510 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -55,14 +55,14 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) /* - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index 83fdc15011..723f562911 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index 79b886af21..18cecaf510 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -55,14 +55,14 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) /* - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index 83fdc15011..723f562911 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds index 854ed68932..160f5cf386 100644 --- a/board/lantec/u-boot.lds +++ b/board/lantec/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug index 3b4799e1ef..172482f880 100644 --- a/board/lantec/u-boot.lds.debug +++ b/board/lantec/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c index 63375d5da0..442741547b 100644 --- a/board/logicpd/imx27lite/imx27lite.c +++ b/board/logicpd/imx27lite/imx27lite.c @@ -29,6 +29,10 @@ DECLARE_GLOBAL_DATA_PTR; int board_init (void) { struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; +#if defined(CONFIG_SYS_NAND_LARGEPAGE) + struct system_control_regs *sc_regs = + (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; +#endif gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -43,9 +47,20 @@ int board_init (void) ®s->port[PORTC].dr); #endif #ifdef CONFIG_MXC_MMC +#if defined(CONFIG_MAGNESIUM) + mx27_sd1_init_pins(); +#else mx27_sd2_init_pins(); #endif +#endif +#if defined(CONFIG_SYS_NAND_LARGEPAGE) + /* + * set in FMCR NF_FMS Bit(5) to 1 + * (NAND Flash with 2 Kbyte page size) + */ + writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr); +#endif return 0; } @@ -68,6 +83,7 @@ int dram_init (void) int checkboard(void) { - printf("LogicPD imx27lite\n"); + puts ("Board: "); + puts(CONFIG_BOARDNAME); return 0; } diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c index 387ed2d396..6455d1dc3c 100644 --- a/board/logicpd/zoom2/zoom2.c +++ b/board/logicpd/zoom2/zoom2.c @@ -46,7 +46,7 @@ /* * This the the zoom2, board specific, gpmc configuration for the * quad uart on the debug board. The more general gpmc configurations - * are setup at the cpu level in cpu/arm_cortexa8/omap3/mem.c + * are setup at the cpu level in arch/arm/cpu/arm_cortexa8/omap3/mem.c * * The details of the setting of the serial gpmc setup are not available. * The values were provided by another party. diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c index ba58e39346..cfbad13478 100644 --- a/board/logicpd/zoom2/zoom2_serial.c +++ b/board/logicpd/zoom2/zoom2_serial.c @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * - * This file was adapted from cpu/mpc5xxx/serial.c + * This file was adapted from arch/ppc/cpu/mpc5xxx/serial.c * */ diff --git a/board/lpc2292sodimm/flash.c b/board/lpc2292sodimm/flash.c index a7e175d8ed..fd5389fb98 100644 --- a/board/lpc2292sodimm/flash.c +++ b/board/lpc2292sodimm/flash.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2006 Embedded Artists AB * - * Modified to use the routines in cpu/arm720t/lpc2292/flash.c by + * Modified to use the routines in arch/arm/cpu/arm720t/lpc2292/flash.c by * Gary Jennejohn * * This program is free software; you can redistribute it and/or diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index cc8ad7d3db..ff2f56640b 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) *(.got1) diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 987c4ddb9b..fcf2cbb96d 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S index 718cec6af5..c714fb7ad9 100644 --- a/board/lwmon5/init.S +++ b/board/lwmon5/init.S @@ -25,7 +25,7 @@ #include #include -#include +#include /************************************************************************** * TLB TABLE diff --git a/board/m501sk/m501sk.h b/board/m501sk/m501sk.h index 42a67573da..51d10f58a9 100644 --- a/board/m501sk/m501sk.h +++ b/board/m501sk/m501sk.h @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-at91/hardware.h + * linux/include/asm/arch-at91/hardware.h * * Copyright (C) 2003 SAN People * @@ -21,9 +21,9 @@ #define __M501SK_H #ifndef __ASSEMBLY__ -#include +#include #else -#include +#include #endif #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */ diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile new file mode 100644 index 0000000000..b179e6d78f --- /dev/null +++ b/board/matrix_vision/mvsmr/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004-2008 +# Matrix-Vision GmbH, info@matrix-vision.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + @mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript new file mode 100644 index 0000000000..02c802c8c7 --- /dev/null +++ b/board/matrix_vision/mvsmr/bootscript @@ -0,0 +1,42 @@ +echo +echo "==== running autoscript ====" +echo +setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}' +setenv ramkernel 'setenv kernel_boot ${loadaddr}' +setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}' +setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}' +setenv bootfromflash run flashkernel cpird addcons boot24 +setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel' +if test ${console} = yes; +then +setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8' +else +setenv addcons 'setenv bootargs ${bootargs} console=tty0' +fi +setenv set_static_ip 'setenv ipaddr ${static_ipaddr}' +setenv set_static_nm 'setenv netmask ${static_netmask}' +setenv set_static_gw 'setenv gatewayip ${static_gateway}' +setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}' +if test ${servicemode} != yes; +then + echo "=== forced flash mode ===" + run set_static_ip set_static_nm set_static_gw set_ip bootfromflash +fi +if test ${autoscript_boot} != no; +then + if test ${netboot} = yes; + then + bootp + if test $? = 0; + then + echo "=== bootp succeeded -> netboot ===" + run set_ip bootfromnet addcons boot24 + else + echo "=== netboot failed ===" + fi + fi + echo "=== bootfromflash ===" + run set_static_ip set_static_nm set_static_gw set_ip bootfromflash +else + echo "=== boot stopped with autoscript_boot no ===" +fi diff --git a/board/matrix_vision/mvsmr/config.mk b/board/matrix_vision/mvsmr/config.mk new file mode 100644 index 0000000000..b1da812c49 --- /dev/null +++ b/board/matrix_vision/mvsmr/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFF800000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board +LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c new file mode 100644 index 0000000000..6320a6903f --- /dev/null +++ b/board/matrix_vision/mvsmr/fpga.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2010 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include "fpga.h" +#include "mvsmr.h" + +Xilinx_Spartan3_Slave_Serial_fns fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_clk_fn, + fpga_init_fn, + fpga_done_fn, + fpga_wr_fn, + 0 +}; + +Xilinx_desc spartan3 = { + Xilinx_Spartan2, + slave_serial, + XILINX_XC3S200_SIZE, + (void *) &fpga_fns, + 0, +}; + +DECLARE_GLOBAL_DATA_PTR; + +int mvsmr_init_fpga(void) +{ + fpga_init(); + fpga_add(fpga_xilinx, &spartan3); + + return 1; +} + +int fpga_init_fn(int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (in_be32(&gpio->simple_ival) & FPGA_CONFIG) + return 0; + + return 1; +} + +int fpga_done_fn(int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + int result = 0; + + udelay(10); + if (in_be32(&gpio->simple_ival) & FPGA_DONE) + result = 1; + + return result; +} + +int fpga_pgm_fn(int assert, int flush, int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (!assert) + setbits_8(&gpio->sint_dvo, FPGA_STATUS); + else + clrbits_8(&gpio->sint_dvo, FPGA_STATUS); + + return assert; +} + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (assert_clk) + setbits_be32(&gpio->simple_dvo, FPGA_CCLK); + else + clrbits_be32(&gpio->simple_dvo, FPGA_CCLK); + + return assert_clk; +} + +int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (assert_write) + setbits_be32(&gpio->simple_dvo, FPGA_DIN); + else + clrbits_be32(&gpio->simple_dvo, FPGA_DIN); + + return assert_write; +} + +int fpga_pre_config_fn(int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + setbits_8(&gpio->sint_dvo, FPGA_STATUS); + + return 0; +} diff --git a/board/matrix_vision/mvsmr/fpga.h b/board/matrix_vision/mvsmr/fpga.h new file mode 100644 index 0000000000..ee690e6816 --- /dev/null +++ b/board/matrix_vision/mvsmr/fpga.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +extern int mvsmr_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_init_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(int assert_write, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_pre_config_fn(int cookie); diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c new file mode 100644 index 0000000000..69655c4cfe --- /dev/null +++ b/board/matrix_vision/mvsmr/mvsmr.c @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2005-2010 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fpga.h" +#include "mvsmr.h" +#include "../common/mv_common.h" + +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x715f0f00 +#define SDRAM_CONFIG1 0xd3722930 +#define SDRAM_CONFIG2 0x46770000 + +DECLARE_GLOBAL_DATA_PTR; + +static void sdram_start(int hi_addr) +{ + long hi_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | + hi_bit); + + /* precharge all banks */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | + hi_bit); + + /* set mode register: extended mode */ + out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); + + /* set mode register: reset DLL */ + out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); + + /* precharge all banks */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | + hi_bit); + + /* auto refresh */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | + hi_bit); + + /* set mode register */ + out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); + + /* normal operation */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); +} + +phys_addr_t initdram(int board_type) +{ + ulong dramsize = 0; + ulong test1, + test2; + + /* setup SDRAM chip selects */ + out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); + + /* setup config registers */ + out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); + out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + if (dramsize < (1 << 20)) + dramsize = 0; + + if (dramsize > 0) + out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 + + __builtin_ffs(dramsize >> 20) - 1); + else + out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0); + + return dramsize; +} + +void mvsmr_init_gpio(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + printf("Ports : 0x%08x\n", gpio->port_config); + printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG)); + + out_be32(&gpio->simple_ddr, SIMPLE_DDR); + out_be32(&gpio->simple_dvo, SIMPLE_DVO); + out_be32(&gpio->simple_ode, SIMPLE_ODE); + out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); + + out_8(&gpio->sint_ode, SINT_ODE); + out_8(&gpio->sint_ddr, SINT_DDR); + out_8(&gpio->sint_dvo, SINT_DVO); + out_8(&gpio->sint_inten, SINT_INTEN); + out_be16(&gpio->sint_itype, SINT_ITYPE); + out_8(&gpio->sint_gpioe, SINT_GPIOEN); + + out_8(&wu_gpio->ode, WKUP_ODE); + out_8(&wu_gpio->ddr, WKUP_DIR); + out_8(&wu_gpio->dvo, WKUP_DO); + out_8(&wu_gpio->enable, WKUP_EN); + + out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */ + out_be32(&timers->gpt1.emsr, 0x00000234); + out_be32(&timers->gpt2.emsr, 0x00000234); + out_be32(&timers->gpt3.emsr, 0x00000234); + out_be32(&timers->gpt4.emsr, 0x00000234); + out_be32(&timers->gpt5.emsr, 0x00000234); + out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */ + out_be32(&timers->gpt7.emsr, 0x00000024); +} + +int misc_init_r(void) +{ + char *s = getenv("reset_env"); + + if (s) { + printf(" === FACTORY RESET ===\n"); + mv_reset_environment(); + saveenv(); + } + + return -1; +} + +void mvsmr_get_dbg_present(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + if (in_be32(&gpio->simple_ival) & COP_PRESENT) { + setenv("dbg_present", "no\0"); + setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0"); + } else { + setenv("dbg_present", "yes\0"); + setenv("bootstopkey", "s\0"); + setbits_8(&psc->command, PSC_RX_ENABLE); + } +} + +void mvsmr_get_service_mode(void) +{ + struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + + if (in_8(&wu_gpio->ival) & SERVICE_MODE) + setenv("servicemode", "no\0"); + else + setenv("servicemode", "yes\0"); +} + +int mvsmr_get_mac(void) +{ + unsigned char mac[6]; + struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + + if (in_8(&wu_gpio->ival) & LAN_PRSNT) { + setenv("lan_present", "no\0"); + return -1; + } else + setenv("lan_present", "yes\0"); + + i2c_read(0x50, 0, 1, mac, 6); + + eth_setenv_enetaddr("ethaddr", mac); + + return 0; +} + +int checkboard(void) +{ + mvsmr_init_gpio(); + printf("Board: Matrix Vision mvSMR\n"); + + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1); +} + +void flash_afterinit(ulong size) +{ + out_be32((u32 *)MPC5XXX_BOOTCS_START, + START_REG(CONFIG_SYS_BOOTCS_START | size)); + out_be32((u32 *)MPC5XXX_CS0_START, + START_REG(CONFIG_SYS_BOOTCS_START | size)); + out_be32((u32 *)MPC5XXX_BOOTCS_STOP, + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); + out_be32((u32 *)MPC5XXX_CS0_STOP, + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); +} + +struct pci_controller hose; + +void pci_init_board(void) +{ + mvsmr_get_dbg_present(); + mvsmr_get_service_mode(); + mvsmr_init_fpga(); + mv_load_fpga(); + pci_mpc5xxx_init(&hose); +} + +int board_eth_init(bd_t *bis) +{ + if (!mvsmr_get_mac()) + return cpu_eth_init(bis); + + return pci_eth_init(bis); +} diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h new file mode 100644 index 0000000000..b8320f1e6e --- /dev/null +++ b/board/matrix_vision/mvsmr/mvsmr.h @@ -0,0 +1,43 @@ +#include + +extern void pci_mpc5xxx_init(struct pci_controller *); + +#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 +#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 +#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 +#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 +#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 +#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5 +#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6 +#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7 +#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8 +#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9 + +#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 +#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 +#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 +#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 +#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6 +#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 +#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4 +#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4 + +#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\ + S_FPGA_CCLK) +#define SIMPLE_DVO (FPGA_CONFIG) +#define SIMPLE_ODE (FPGA_CONFIG) +#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\ + S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT) + +#define SINT_ODE 0x1 +#define SINT_DDR 0x3 +#define SINT_DVO 0x1 +#define SINT_INTEN 0 +#define SINT_ITYPE 0 +#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG) + +#define WKUP_ODE (MAN_RST | S_FPGA_STATUS) +#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS) +#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS) +#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\ + FLASH_RBY | UART_EN1 | LAN_PRSNT) diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds new file mode 100644 index 0000000000..cfbb6ef398 --- /dev/null +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2010 + * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the first two sectors (=8KB) of our S29GL flash chip */ + cpu/mpc5xxx/start.o (.text) + cpu/mpc5xxx/traps.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + /* This is only needed to force failure if size of above code will ever */ + /* increase and grow into reserved space. */ + . = ALIGN(0x2000); /* location counter has to be 0x4000 now */ + . += 0x4000; /* ->0x8000, i.e. move to env_offset */ + + . = env_offset; /* ld error as soon as above ALIGN misplaces lc */ + common/env_embedded.o (.ppcenv) + + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index dc3e580fb1..3572f1ad32 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index 0a3b958fad..61c0d68d78 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h index f650faaa10..423febe20a 100644 --- a/board/mcc200/mt46v16m16-75.h +++ b/board/mcc200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h index ffdf0396a5..15477259ca 100644 --- a/board/mcc200/mt48lc16m16a2-75.h +++ b/board/mcc200/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h index ffdf0396a5..15477259ca 100644 --- a/board/mcc200/mt48lc16m32s2-75.h +++ b/board/mcc200/mt48lc16m32s2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 0dcacb9f1b..cc0f137121 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -31,7 +31,7 @@ #include #include -#include "../../../cpu/at32ap/hsmc3.h" +#include "../../../arch/avr32/cpu/hsmc3.h" #if defined(CONFIG_LCD) /* 480x272x16 @ 72 Hz */ diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds index 8fea3be41b..e382283ea2 100644 --- a/board/ml2/u-boot.lds +++ b/board/ml2/u-boot.lds @@ -55,18 +55,18 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) board/ml2/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) + arch/ppc/cpu/ppc4xx/kgdb.o (.text) + arch/ppc/cpu/ppc4xx/traps.o (.text) + arch/ppc/cpu/ppc4xx/interrupts.o (.text) + arch/ppc/cpu/ppc4xx/4xx_uart.o (.text) + arch/ppc/cpu/ppc4xx/cpu_init.o (.text) + arch/ppc/cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) /* . = env_offset;*/ /* common/env_embedded.o(.text)*/ diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug index 970628d556..09c0191e5f 100644 --- a/board/ml2/u-boot.lds.debug +++ b/board/ml2/u-boot.lds.debug @@ -57,9 +57,9 @@ SECTIONS mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) common/env_embedded.o(.text) diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 5100542e73..ed5492d45e 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -52,12 +52,12 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/cpu/mpc824x/start.o (.text) + arch/ppc/lib/board.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) *(.got1) . = ALIGN(16); diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram index d048e52d35..d3169489b5 100644 --- a/board/mousse/u-boot.lds.ram +++ b/board/mousse/u-boot.lds.ram @@ -37,7 +37,7 @@ SECTIONS PROVIDE(_f_init_rom = .); .init : { - cpu/mpc824x/start.o (.text) + arch/ppc/cpu/mpc824x/start.o (.text) *(.init) } > ram _init_size = SIZEOF(.init); diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom index f79c39f716..2721fdc6f8 100644 --- a/board/mousse/u-boot.lds.rom +++ b/board/mousse/u-boot.lds.rom @@ -52,12 +52,12 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc824x/start.o (.text) + arch/ppc/cpu/mpc824x/start.o (.text) common/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o (.text) diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index 970628d556..09c0191e5f 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -57,9 +57,9 @@ SECTIONS mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) common/env_embedded.o(.text) diff --git a/board/mucmc52/config.mk b/board/mucmc52/config.mk index 90d9ce2c9c..4e9ee73e6a 100644 --- a/board/mucmc52/config.mk +++ b/board/mucmc52/config.mk @@ -42,4 +42,4 @@ TEXT_BASE = 0xFFF00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board -LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h index ffdf0396a5..15477259ca 100644 --- a/board/munices/mt48lc16m16a2-75.h +++ b/board/munices/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/munices/u-boot.lds b/board/munices/u-boot.lds index 8db7f26a52..2cd6d3c1ad 100644 --- a/board/munices/u-boot.lds +++ b/board/munices/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc5xxx/start.o (.text) + arch/ppc/cpu/mpc5xxx/start.o (.text) *(.text) *(.got1) . = ALIGN(16); diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds index 21fed6262c..90ca165c44 100644 --- a/board/nc650/u-boot.lds +++ b/board/nc650/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) } diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug index 5f8dc9d2c6..1405b1730b 100644 --- a/board/nc650/u-boot.lds.debug +++ b/board/nc650/u-boot.lds.debug @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) *(.text) *(.got1) } diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index d64274b683..d6e2404f9a 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -52,15 +52,15 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index 4ef16f1ffe..ec479b1533 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 8efbc23c89..1c99405bea 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include "../common/nm.h" DECLARE_GLOBAL_DATA_PTR; @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * This function is run very early, out of flash, and before devices are - * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue * of being in the init_sequence array. * * The SDRAM has been initialized already -- start.S:start called diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt index f64987637a..0be51925c1 100644 --- a/board/netstal/hcu5/README.txt +++ b/board/netstal/hcu5/README.txt @@ -83,11 +83,11 @@ System-LEDs ??? (Analog zu HCU4 ???) Startup sequence ---------------- -(cpu/ppc4xx/resetvec.S) +(arch/ppc/cpu/ppc4xx/resetvec.S) depending on configs option call _start_440 _start_pci oder _start -(cpu/ppc4xx/start.S) +(arch/ppc/cpu/ppc4xx/start.S) _start_440: initialize register like @@ -109,7 +109,7 @@ _start: call cpu_init_f /* run low-level CPU init code (from Flash) */ call cpu_init_f - board_init_f: (lib_ppc\board.c) + board_init_f: (arch/ppc/lib\board.c) init_sequence defines a list of function to be called board_early_init_f: (board/netstal/hcu5/hcu5.c) We are using Bootstrap-Option A @@ -136,18 +136,18 @@ _start: * - board info struct Save local variables to board info struct call relocate_code() does not return - relocate_code: (cpu/ppc4xx/start.S) + relocate_code: (arch/ppc/cpu/ppc4xx/start.S) ------------------------------------------------------- From now on our copy is in RAM and we will run from there, starting with board_init_r ------------------------------------------------------- - board_init_r: (lib_ppc\board.c) + board_init_r: (arch/ppc/lib\board.c) setup bd function pointers trap_init flash_init: (board/netstal/hcu5/flash.c) /* setup for u-boot erase, update */ setup bd flash info - cpu_init_r: (cpu/ppc4xx/cpu_init.c) + cpu_init_r: (arch/ppc/cpu/ppc4xx/cpu_init.c) peripheral chip select in using defines like CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h mem_malloc_init @@ -161,8 +161,8 @@ From now on our copy is in RAM and we will run from there, Most of the HW specific code for the HCU5 may be found in include/configs/hcu5.h board/netstal/hcu5/* -cpu/ppc4xx/* -lib_ppc/* +arch/ppc/cpu/ppc4xx/* +arch/ppc/lib/* include/ppc440.h Drivers for serial etc are found under drivers/ diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index c545cc01ea..90433fe82d 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -49,7 +49,7 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* * This function is run very early, out of flash, and before devices are - * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue * of being in the init_sequence array. * * The SDRAM has been initialized already -- start.S:start called diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index c66ab97ac5..87bc45edb4 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include "../common/nm.h" DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * This function is run very early, out of flash, and before devices are - * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue * of being in the init_sequence array. * * The SDRAM has been initialized already -- start.S:start called diff --git a/board/netstar/Makefile b/board/netstar/Makefile index c435762964..5773c13f4d 100644 --- a/board/netstar/Makefile +++ b/board/netstar/Makefile @@ -72,7 +72,7 @@ $(obj)crcit: $(obj)crcit.o $(obj)crc32.o $(obj)crcit.o: crcit.c $(HOSTCC) $(HOSTCFLAGS) -o $@ -c $< -$(obj)crc32.o: $(SRCTREE)/lib_generic/crc32.c +$(obj)crc32.o: $(SRCTREE)/lib/crc32.c $(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \ -o $@ -c $< diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index 860c887c25..c4df378c97 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -52,15 +52,15 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index 4ef16f1ffe..ec479b1533 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index 860c887c25..c4df378c97 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -52,15 +52,15 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index 4ef16f1ffe..ec479b1533 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index a7d290ae88..6683361ea4 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -52,15 +52,15 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index c3c99b35c2..cef1a428bd 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index 5c847fbf84..dc370eacf2 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index ad36953915..e62f6be5aa 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c index 773e446c0c..2510ddfd69 100644 --- a/board/pb1x00/pb1x00.c +++ b/board/pb1x00/pb1x00.c @@ -37,7 +37,7 @@ phys_size_t initdram(int board_type) #define BCSR_PCMCIA_PC0DRVEN 0x0010 #define BCSR_PCMCIA_PC0RST 0x0080 -/* In cpu/mips/cpu.c */ +/* In arch/mips/cpu/cpu.c */ void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); int checkboard (void) diff --git a/board/pcippc2/u-boot.lds b/board/pcippc2/u-boot.lds index d11bb056fb..b2be328124 100644 --- a/board/pcippc2/u-boot.lds +++ b/board/pcippc2/u-boot.lds @@ -59,7 +59,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index ce1e616679..bed385c44b 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -148,7 +148,7 @@ int board_early_init_f(void) mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- - * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c + * GPIO's are alreay setup in arch/ppc/cpu/ppc4xx/cpu_init.c * via define from board config file. *-------------------------------------------------------------------*/ diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c index 416d3070b5..77ce3899ef 100644 --- a/board/phytec/pcm030/pcm030.c +++ b/board/phytec/pcm030/pcm030.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include "mt46v32m16-75.h" diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c index dc6fac46d3..97c37eaa39 100644 --- a/board/pleb2/pleb2.c +++ b/board/pleb2/pleb2.c @@ -26,7 +26,7 @@ */ #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h index f650faaa10..423febe20a 100644 --- a/board/pm520/mt46v16m16-75.h +++ b/board/pm520/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h index ffdf0396a5..15477259ca 100644 --- a/board/pm520/mt48lc16m16a2-75.h +++ b/board/pm520/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c index 9da1041733..d6914343fa 100644 --- a/board/pm520/pm520.c +++ b/board/pm520/pm520.c @@ -84,7 +84,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -186,64 +185,9 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { -#if defined(CONFIG_MPC5200) puts ("Board: MicroSys PM520 \n"); -#elif defined(CONFIG_MGT5100) - puts ("Board: MicroSys PM510 \n"); -#endif return 0; } @@ -255,10 +199,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/ppmc7xx/u-boot.lds b/board/ppmc7xx/u-boot.lds index 30e8972afa..aae1057160 100644 --- a/board/ppmc7xx/u-boot.lds +++ b/board/ppmc7xx/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index 7571cd950c..f3bc1fa7a1 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include "fpga.h" diff --git a/board/prodrive/p3mx/u-boot.lds b/board/prodrive/p3mx/u-boot.lds index d021331148..6dff003dc1 100644 --- a/board/prodrive/p3mx/u-boot.lds +++ b/board/prodrive/p3mx/u-boot.lds @@ -56,7 +56,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/74xx_7xx/start.o (.text) + arch/ppc/cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c index 0fcf354cdc..72b0a9f807 100644 --- a/board/psyent/common/AMDLV065D.c +++ b/board/psyent/common/AMDLV065D.c @@ -122,12 +122,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr2 = (unsigned char *) info->start[sect]; - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr, 0x80); - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr2, 0x30); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x80, addr); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x30, addr2); /* Now just wait for 0xff & provide some user * feedback while we wait. */ @@ -169,9 +169,9 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return (2); } - writeb (cmd, 0xaa); - writeb (cmd, 0x55); - writeb (cmd, 0xa0); + writeb (0xaa, cmd); + writeb (0x55, cmd); + writeb (0xa0, cmd); writeb (dst, b); /* Verify write */ diff --git a/board/psyent/pci5441/u-boot.lds b/board/psyent/pci5441/u-boot.lds index b2d88a5586..f155800a64 100644 --- a/board/psyent/pci5441/u-boot.lds +++ b/board/psyent/pci5441/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { .text : { - cpu/nios2/start.o (.text) + arch/nios/cpu2/start.o (.text) *(.text) *(.text.*) *(.gnu.linkonce.t*) diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c index e5e7705761..d0197358f4 100644 --- a/board/psyent/pk1c20/led.c +++ b/board/psyent/pk1c20/led.c @@ -39,7 +39,7 @@ void __led_init (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_set (led_id_t mask, int state) @@ -50,7 +50,7 @@ void __led_set (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_toggle (led_id_t mask) @@ -58,5 +58,5 @@ void __led_toggle (led_id_t mask) nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; val ^= mask; - writel (&pio->data, val); + writel (val, &pio->data); } diff --git a/board/psyent/pk1c20/u-boot.lds b/board/psyent/pk1c20/u-boot.lds index b2d88a5586..f155800a64 100644 --- a/board/psyent/pk1c20/u-boot.lds +++ b/board/psyent/pk1c20/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { .text : { - cpu/nios2/start.o (.text) + arch/nios/cpu2/start.o (.text) *(.text) *(.text.*) *(.gnu.linkonce.t*) diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 04a641a473..1881e651c0 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -34,13 +34,13 @@ SECTIONS . = ALIGN(4); .text : { - cpu/mips/start.o (.text) + arch/mips/cpu/start.o (.text) board/purple/lowlevel_init.o (.text) - cpu/mips/cache.o (.text) + arch/mips/cpu/cache.o (.text) common/main.o (.text) common/dlmalloc.o (.text) common/cmd_boot.o (.text) - lib_generic/zlib.o (.text) + lib/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index 47247ec813..f7de95dc87 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) /* XXX ? . = env_offset; */ diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug index ec01fe256b..a2b7bc70d9 100644 --- a/board/quantum/u-boot.lds.debug +++ b/board/quantum/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 9089f7d6b6..4fc18fcf2d 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/cpu_init.o (.text) - cpu/mpc8xx/interrupts.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/cpu_init.o (.text) + arch/ppc/cpu/mpc8xx/interrupts.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) /*** . = env_offset; common/env_embedded.o (.text) diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index e0ea600d28..2161501fff 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/rmu/u-boot.lds b/board/rmu/u-boot.lds index 47247ec813..f7de95dc87 100644 --- a/board/rmu/u-boot.lds +++ b/board/rmu/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) /* XXX ? . = env_offset; */ diff --git a/board/rmu/u-boot.lds.debug b/board/rmu/u-boot.lds.debug index ec01fe256b..a2b7bc70d9 100644 --- a/board/rmu/u-boot.lds.debug +++ b/board/rmu/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index 396c3e7340..ff21ce667b 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -26,19 +26,21 @@ #include #include #include -#include +#include #include void coloured_LED_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer); - at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + at91_set_pio_output(CONFIG_RED_LED, 1); + at91_set_pio_output(CONFIG_GREEN_LED, 1); + at91_set_pio_output(CONFIG_YELLOW_LED, 1); - at91_set_gpio_value(CONFIG_RED_LED, 0); - at91_set_gpio_value(CONFIG_GREEN_LED, 1); - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + at91_set_pio_value(CONFIG_RED_LED, 0); + at91_set_pio_value(CONFIG_GREEN_LED, 1); + at91_set_pio_value(CONFIG_YELLOW_LED, 1); } diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 8662339581..53d8c48281 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -27,13 +27,14 @@ #include #include #include -#include #include #include #include #include +#include +#include #include -#include +#include #include #include #include @@ -55,39 +56,48 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9261_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + writel(1 << AT91SAM9261_ID_PIOA | + 1 << AT91SAM9261_ID_PIOC, + &pmc->pcer); /* Configure RDY/BSY */ - at91_set_gpio_input(AT91_PIN_PA16, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(AT91_PIN_PC14, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ - at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ } #endif @@ -95,23 +105,30 @@ static void pm9261_nand_hw_init(void) #ifdef CONFIG_DRIVER_DM9000 static void pm9261_dm9000_hw_init(void) { + at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Configure SMC CS2 for DM9000 */ - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + + writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), + &smc->cs[2].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); /* Configure Interrupt pin as input, no pull-up */ - at91_set_gpio_input(AT91_PIN_PA24, 0); + writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer); + at91_set_pio_input(AT91_PIO_PORTA, 24, 0); } #endif @@ -135,40 +152,42 @@ vidinfo_t panel_info = { void lcd_enable(void) { - at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */ + at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */ } void lcd_disable(void) { - at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */ + at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */ } static void pm9261_lcd_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ - at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ - at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ - at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ - at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ - at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ - at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ - at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ - at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */ + at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */ + at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */ + at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */ + at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */ + at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */ + + writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */ gd->fb_base = AT91SAM9261_SRAM_BASE; } @@ -222,11 +241,14 @@ void lcd_show_board_info(void) int board_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Enable Ctrlc */ console_init_f(); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + writel(1 << AT91SAM9261_ID_PIOA | + 1 << AT91SAM9261_ID_PIOC, + &pmc->pcer); /* arch number of PM9261-Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9261; diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index 0d4a9efb79..0c51d48127 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8260/start.o (.text) + arch/ppc/cpu/mpc8260/start.o (.text) *(.text) *(.got1) /*. = env_offset; */ diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds index a074420c15..29a4f61e36 100644 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ b/board/samsung/smdk6400/u-boot-nand.lds @@ -34,8 +34,8 @@ SECTIONS . = ALIGN(4); .text : { - cpu/arm1176/start.o (.text) - cpu/arm1176/s3c64xx/cpu_init.o (.text) + arch/arm/cpu/arm1176/start.o (.text) + arch/arm/cpu/arm1176/s3c64xx/cpu_init.o (.text) *(.text) } diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c index 35c4e60b5a..007f875f0f 100644 --- a/board/sandburst/common/ppc440gx_i2c.c +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -21,7 +21,7 @@ */ /* - * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by + * Ported from arch/ppc/cpu/ppc4xx/i2c.c by AS HARNOIS by * Travis B. Sawyer * Sandburst Corporation. */ @@ -31,7 +31,7 @@ #include #include #include "ppc440gx_i2c.h" -#include +#include #ifdef CONFIG_I2C_BUS1 diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 48fd579162..c174398537 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -56,19 +56,19 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) board/sandburst/karef/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) + arch/ppc/cpu/ppc4xx/kgdb.o (.text) + arch/ppc/cpu/ppc4xx/traps.o (.text) + arch/ppc/cpu/ppc4xx/interrupts.o (.text) + arch/ppc/cpu/ppc4xx/4xx_uart.o (.text) + arch/ppc/cpu/ppc4xx/cpu_init.o (.text) + arch/ppc/cpu/ppc4xx/speed.o (.text) drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) /* common/env_embedded.o(.text) */ diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index 4bc5ceac02..845841607c 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -56,19 +56,19 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) board/sandburst/metrobox/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) + arch/ppc/cpu/ppc4xx/kgdb.o (.text) + arch/ppc/cpu/ppc4xx/traps.o (.text) + arch/ppc/cpu/ppc4xx/interrupts.o (.text) + arch/ppc/cpu/ppc4xx/4xx_uart.o (.text) + arch/ppc/cpu/ppc4xx/cpu_init.o (.text) + arch/ppc/cpu/ppc4xx/speed.o (.text) drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) /* common/env_embedded.o(.text) */ diff --git a/board/sbc8641d/u-boot.lds b/board/sbc8641d/u-boot.lds index b71a7d6e58..2f8730bf2b 100644 --- a/board/sbc8641d/u-boot.lds +++ b/board/sbc8641d/u-boot.lds @@ -50,16 +50,16 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc86xx/start.o (.text) - cpu/mpc86xx/traps.o (.text) - cpu/mpc86xx/interrupts.o (.text) - cpu/mpc86xx/cpu_init.o (.text) - cpu/mpc86xx/cpu.o (.text) - cpu/mpc86xx/speed.o (.text) + arch/ppc/cpu/mpc86xx/start.o (.text) + arch/ppc/cpu/mpc86xx/traps.o (.text) + arch/ppc/cpu/mpc86xx/interrupts.o (.text) + arch/ppc/cpu/mpc86xx/cpu_init.o (.text) + arch/ppc/cpu/mpc86xx/cpu.o (.text) + arch/ppc/cpu/mpc86xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) *(.text) *(.got1) } diff --git a/board/sc3/u-boot.lds b/board/sc3/u-boot.lds index 16dc384015..573fbee937 100644 --- a/board/sc3/u-boot.lds +++ b/board/sc3/u-boot.lds @@ -60,18 +60,18 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) board/sc3/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) + arch/ppc/cpu/ppc4xx/kgdb.o (.text) + arch/ppc/cpu/ppc4xx/traps.o (.text) + arch/ppc/cpu/ppc4xx/interrupts.o (.text) + arch/ppc/cpu/ppc4xx/4xx_uart.o (.text) + arch/ppc/cpu/ppc4xx/cpu_init.o (.text) + arch/ppc/cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) /* . = env_offset;*/ /* common/env_embedded.o(.text)*/ diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds index 2d0efb3161..5bd5a75c61 100644 --- a/board/siemens/CCM/u-boot.lds +++ b/board/siemens/CCM/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug index 29657e93ef..460a983215 100644 --- a/board/siemens/CCM/u-boot.lds.debug +++ b/board/siemens/CCM/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) /* . = env_offset; common/env_embedded.o(.text) diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds index 104b44ccff..904d45fccc 100644 --- a/board/siemens/IAD210/u-boot.lds +++ b/board/siemens/IAD210/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + arch/ppc/cpu/mpc8xx/interrupts.o (.text) + arch/ppc/lib/time.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c index 8cf17b8576..fc91574f85 100644 --- a/board/siemens/SMN42/flash.c +++ b/board/siemens/SMN42/flash.c @@ -2,7 +2,7 @@ * (C) Copyright 2006 Embedded Artists AB * * (C) Copyright 2007 Gary Jennejohn garyj@denx.de - * Modified to use the routines in cpu/arm720t/lpc2292/flash.c. + * Modified to use the routines in arch/arm/cpu/arm720t/lpc2292/flash.c. * Heavily modified to support the SMN42 board from Siemens * * This program is free software; you can redistribute it and/or diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds index cc8ad7d3db..ff2f56640b 100644 --- a/board/siemens/pcu_e/u-boot.lds +++ b/board/siemens/pcu_e/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) *(.got1) diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug index 987c4ddb9b..fcf2cbb96d 100644 --- a/board/siemens/pcu_e/u-boot.lds.debug +++ b/board/siemens/pcu_e/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index dd632a44ce..c3e7f501cb 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) *(.got1) diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index 9ef2c201a2..f2154c429b 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index 9ef2c201a2..f2154c429b 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index d6711b5bf2..c000746c54 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index 7b9455b252..c4d83574d6 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) *(.got1) diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index 0a3b958fad..61c0d68d78 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/ssv/adnpesc1/u-boot.lds b/board/ssv/adnpesc1/u-boot.lds index 98ee8f8323..50c3fe75a0 100644 --- a/board/ssv/adnpesc1/u-boot.lds +++ b/board/ssv/adnpesc1/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { .text : { - cpu/nios/start.o (.text) + arch/nios/cpu/start.o (.text) *(.text) } __text_end = .; diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 73dddf3e0c..678ec5850f 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -259,7 +259,7 @@ board_early_init_f(void) #endif /* Why is the phy reset done _after_ the ethernet - * initialization in lib_ppc/board.c? + * initialization in arch/ppc/lib/board.c? * Do it here so it's done before the TSECs are used. */ reset_phy(); diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds index 860c887c25..c4df378c97 100644 --- a/board/stx/stxxtc/u-boot.lds +++ b/board/stx/stxxtc/u-boot.lds @@ -52,15 +52,15 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug index 4ef16f1ffe..ec479b1533 100644 --- a/board/stx/stxxtc/u-boot.lds.debug +++ b/board/stx/stxxtc/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index 02aa9dd987..90270954e4 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) . = env_offset; common/env_embedded.o (.ppcenv) diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug index ec01fe256b..a2b7bc70d9 100644 --- a/board/svm_sc8xx/u-boot.lds.debug +++ b/board/svm_sc8xx/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk index f85bef5e2a..3f9d41f371 100644 --- a/board/tcm-bf518/config.mk +++ b/board/tcm-bf518/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk index 3c0b46f721..bc046f129f 100644 --- a/board/tcm-bf537/config.mk +++ b/board/tcm-bf537/config.mk @@ -26,8 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me -CFLAGS_lib_generic += -O2 -CFLAGS_lzma += -O2 +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h index 5b0923e3e8..ae237c6cab 100644 --- a/board/total5200/mt48lc16m16a2-75.h +++ b/board/total5200/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h index 4b5ac80b35..cb4b43d63e 100644 --- a/board/total5200/mt48lc32m16a2-75.h +++ b/board/total5200/mt48lc32m16a2-75.h @@ -28,13 +28,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x514F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#else -#error CONFIG_MPC5200 is not defined -#endif diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c index dc4c6f18c2..d883eb656d 100644 --- a/board/total5200/sdram.c +++ b/board/total5200/sdram.c @@ -76,7 +76,6 @@ static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) { ulong dramsize = 0; @@ -174,54 +173,3 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) return dramsize + dramsize2; } - -#elif defined(CONFIG_MGT5100) - -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel; - __asm__ volatile ("sync"); - - /* find RAM size */ - mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - mpc5xxx_sdram_start(sdram_conf, 0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h index bc21e1d300..396a190145 100644 --- a/board/total5200/sdram.h +++ b/board/total5200/sdram.h @@ -28,12 +28,7 @@ typedef struct { ulong control; ulong config1; ulong config2; -#if defined(CONFIG_MPC5200) ulong tapdelay; -#endif -#if defined(CONFIG_MGT5100) - ulong addrsel; -#endif } sdram_conf_t; long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf); diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c index c524d63f93..61b5b807af 100644 --- a/board/total5200/total5200.c +++ b/board/total5200/total5200.c @@ -47,26 +47,17 @@ phys_size_t initdram (int board_type) sdram_conf.control = SDRAM_CONTROL; sdram_conf.config1 = SDRAM_CONFIG1; sdram_conf.config2 = SDRAM_CONFIG2; -#if defined(CONFIG_MPC5200) sdram_conf.tapdelay = 0; -#endif -#if defined(CONFIG_MGT5100) - sdram_conf.addrsel = SDRAM_ADDRSEL; -#endif return mpc5xxx_sdram_init (&sdram_conf); } int checkboard (void) { -#if defined(CONFIG_MPC5200) #if CONFIG_TOTAL5200_REV==2 puts ("Board: Total5200 Rev.2 "); #else puts ("Board: Total5200 "); #endif -#elif defined(CONFIG_MGT5100) - puts ("Board: Total5100 "); -#endif /* * Retrieve FPGA Revision. @@ -85,20 +76,6 @@ int checkboard (void) return 0; } -#if defined(CONFIG_MGT5100) -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable CS0 - * because CS_BOOT cannot be written. - */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ - - return 0; -} -#endif - #ifdef CONFIG_PCI static struct pci_controller hose; @@ -266,9 +243,7 @@ static const S1D_REGS init_regs [] = void video_get_info_str (int line_number, char *info) { if (line_number == 1) { -#ifdef CONFIG_MGT5100 - strcpy (info, " Total5100"); -#elif CONFIG_TOTAL5200_REV==1 +#if CONFIG_TOTAL5200_REV==1 strcpy (info, " Total5200"); #elif CONFIG_TOTAL5200_REV==2 strcpy (info, " Total5200 Rev.2"); diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h index 3f1e1691bb..48b43213dc 100644 --- a/board/tqc/tqm5200/mt48lc16m16a2-75.h +++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 /* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ @@ -33,15 +32,3 @@ /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 4fd8cd6969..e5648799a6 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 2df8d8459c..a2277c260d 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -55,14 +55,14 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/tqc/tqm8xx/u-boot.lds.debug b/board/tqc/tqm8xx/u-boot.lds.debug index a2d940f048..57cc305868 100644 --- a/board/tqc/tqm8xx/u-boot.lds.debug +++ b/board/tqc/tqm8xx/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/trab/Makefile b/board/trab/Makefile index 27d75f3a00..0b13dc475e 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -48,7 +48,7 @@ $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB) $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \ -L$(obj)../../examples/standalone -lstubs \ - -L$(obj)../../lib_generic -lgeneric \ + -L$(obj)../../lib -lgeneric \ $(PLATFORM_LIBS) $(OBJCOPY) -O srec $(<:.o=) $@ diff --git a/board/trab/rs485.c b/board/trab/rs485.c index ad0c13665e..6a3a4cda9c 100644 --- a/board/trab/rs485.c +++ b/board/trab/rs485.c @@ -2,7 +2,7 @@ * (C) Copyright 2003 * Martin Krause, TQ-Systems GmbH, * - * Based on cpu/arm920t/serial.c, by Gary Jennejohn + * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, * * This program is free software; you can redistribute it and/or modify diff --git a/board/trab/rs485.h b/board/trab/rs485.h index 16d69bbd5c..19e32446c3 100644 --- a/board/trab/rs485.h +++ b/board/trab/rs485.h @@ -2,7 +2,7 @@ * (C) Copyright 2003 * Martin Krause, TQ-Systems GmbH, * - * Based on cpu/arm920t/serial.c, by Gary Jennejohn + * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, * * This program is free software; you can redistribute it and/or modify diff --git a/board/trab/u-boot.lds b/board/trab/u-boot.lds index c3d5c49a9b..cd50e85242 100644 --- a/board/trab/u-boot.lds +++ b/board/trab/u-boot.lds @@ -32,10 +32,10 @@ SECTIONS . = ALIGN(4); .text : { - cpu/arm920t/start.o (.text) - lib_generic/zlib.o (.text) - lib_generic/crc32.o (.text) - lib_generic/string.o (.text) + arch/arm/cpu/arm920t/start.o (.text) + lib/zlib.o (.text) + lib/crc32.o (.text) + lib/string.o (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv) diff --git a/board/uc100/u-boot.lds b/board/uc100/u-boot.lds index e3ea52aede..f67b1d9c19 100644 --- a/board/uc100/u-boot.lds +++ b/board/uc100/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) common/env_embedded.o (.text) diff --git a/board/uc100/u-boot.lds.debug b/board/uc100/u-boot.lds.debug index edaa4020a9..84b338a75d 100644 --- a/board/uc100/u-boot.lds.debug +++ b/board/uc100/u-boot.lds.debug @@ -55,10 +55,10 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) common/env_embedded.o(.text) diff --git a/board/uc101/config.mk b/board/uc101/config.mk index 4fe18316e5..aebf30411e 100644 --- a/board/uc101/config.mk +++ b/board/uc101/config.mk @@ -39,4 +39,4 @@ TEXT_BASE = 0xFFF00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board -LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds +LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index 6f2ea9a613..bc47060f25 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -55,15 +55,15 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/traps.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) + arch/ppc/lib/cache.o (.text) + arch/ppc/lib/time.o (.text) /* . = env_offset; diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index 8bb4929a46..369c15a18c 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -57,9 +57,9 @@ SECTIONS mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) common/env_embedded.o(.text) diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index a818808ba0..96a12d73e5 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -157,7 +157,7 @@ phys_size_t initdram (int board_type) /* * ToDo: Move the asm init routine sdram_init() to this C file, * or even better use some common ppc4xx code available - * in cpu/ppc4xx + * in arch/ppc/cpu/ppc4xx */ sdram_init(); diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds index 2d0efb3161..5bd5a75c61 100644 --- a/board/westel/amx860/u-boot.lds +++ b/board/westel/amx860/u-boot.lds @@ -55,12 +55,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) + arch/ppc/lib/ppcstring.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + lib/zlib.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug index 653e0be45c..b331d5afc1 100644 --- a/board/westel/amx860/u-boot.lds.debug +++ b/board/westel/amx860/u-boot.lds.debug @@ -55,11 +55,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mpc8xx/start.o (.text) + arch/ppc/cpu/mpc8xx/start.o (.text) common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) . = env_offset; common/env_embedded.o(.text) diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug index d00834eef3..c3f6fefb45 100644 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ b/board/xes/xpedite1000/u-boot.lds.debug @@ -55,18 +55,18 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) + arch/ppc/cpu/ppc4xx/start.o (.text) board/xes/xpedite1000/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) + arch/ppc/cpu/ppc4xx/kgdb.o (.text) + arch/ppc/cpu/ppc4xx/traps.o (.text) + arch/ppc/cpu/ppc4xx/interrupts.o (.text) + arch/ppc/cpu/ppc4xx/4xx_uart.o (.text) + arch/ppc/cpu/ppc4xx/cpu_init.o (.text) + arch/ppc/cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) /* common/env_embedded.o(.text) */ diff --git a/board/xes/xpedite5170/u-boot.lds b/board/xes/xpedite5170/u-boot.lds index b71a7d6e58..2f8730bf2b 100644 --- a/board/xes/xpedite5170/u-boot.lds +++ b/board/xes/xpedite5170/u-boot.lds @@ -50,16 +50,16 @@ SECTIONS .plt : { *(.plt) } .text : { - cpu/mpc86xx/start.o (.text) - cpu/mpc86xx/traps.o (.text) - cpu/mpc86xx/interrupts.o (.text) - cpu/mpc86xx/cpu_init.o (.text) - cpu/mpc86xx/cpu.o (.text) - cpu/mpc86xx/speed.o (.text) + arch/ppc/cpu/mpc86xx/start.o (.text) + arch/ppc/cpu/mpc86xx/traps.o (.text) + arch/ppc/cpu/mpc86xx/interrupts.o (.text) + arch/ppc/cpu/mpc86xx/cpu_init.o (.text) + arch/ppc/cpu/mpc86xx/cpu.o (.text) + arch/ppc/cpu/mpc86xx/speed.o (.text) common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + lib/crc32.o (.text) + arch/ppc/lib/extable.o (.text) + lib/zlib.o (.text) *(.text) *(.got1) } diff --git a/board/xilinx/microblaze-generic/u-boot.lds b/board/xilinx/microblaze-generic/u-boot.lds index c20c6dd1d6..ee41145bb5 100644 --- a/board/xilinx/microblaze-generic/u-boot.lds +++ b/board/xilinx/microblaze-generic/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS .text ALIGN(0x4): { __text_start = .; - cpu/microblaze/start.o (.text) + arch/microblaze/cpu/start.o (.text) *(.text) __text_end = .; } diff --git a/board/xilinx/ml300/Makefile b/board/xilinx/ml300/Makefile deleted file mode 100644 index b8a2d64c4f..0000000000 --- a/board/xilinx/ml300/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../xilinx_enet) -$(shell mkdir -p $(obj)../xilinx_iic) -endif - -INCS := -I../common -I../xilinx_enet -I../xilinx_iic -CFLAGS += $(INCS) -HOSTCFLAGS += $(INCS) - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o \ - serial.o \ - ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \ - ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \ - ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \ - ../xilinx_enet/xemac_intr_dma.o ../xilinx_iic/iic_adapter.o \ - ../xilinx_iic/xiic_l.o ../common/xipif_v1_23_b.o \ - ../common/xbasic_types.o ../common/xdma_channel.o \ - ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \ - ../common/xversion.o \ - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/xilinx/ml300/config.mk b/board/xilinx/ml300/config.mk deleted file mode 100644 index 208a25ba11..0000000000 --- a/board/xilinx/ml300/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0x04000000 - -# Use board specific linker script -LDSCRIPT := $(SRCTREE)/board/xilinx/ml300/u-boot.lds diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S deleted file mode 100644 index a282c9ae22..0000000000 --- a/board/xilinx/ml300/init.S +++ /dev/null @@ -1,44 +0,0 @@ -/* - * init.S: Stubs for U-Boot initialization - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING - * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx hardware products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * - * (c) Copyright 2002-2004 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * - */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - blr diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c deleted file mode 100644 index e64beccc1c..0000000000 --- a/board/xilinx/ml300/ml300.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * ml300.c: U-Boot platform support for Xilinx ML300 board - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING - * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx hardware products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * - * (c) Copyright 2002-2004 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include -#include -#include - -#ifdef CONFIG_ENV_IS_IN_EEPROM -extern void convert_env(void); -#endif - -int -board_pre_init(void) -{ - return 0; -} - -int -checkboard(void) -{ - char tmp[64]; /* long enough for environment variables */ - char *s, *e; - int i = getenv_r("L", tmp, sizeof (tmp)); - - if (i < 0) { - printf("### No HW ID - assuming ML300"); - } else { - for (e = tmp; *e; ++e) { - if (*e == ' ') - break; - } - - printf("### Board Serial# is "); - - for (s = tmp; s < e; ++s) { - putc(*s); - } - - } - putc('\n'); - - return (0); -} - -phys_size_t -initdram(int board_type) -{ - return 128 * 1024 * 1024; -} - -int -testdram(void) -{ - printf("test: xxx MB - ok\n"); - - return (0); -} - -/* implement functions originally in cpu/ppc4xx/speed.c */ -void -get_sys_info(sys_info_t * sysInfo) -{ - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - - /* only correct if the PLB and OPB run at the same frequency */ - sysInfo->freqPLB = XPAR_UARTNS550_0_CLOCK_FREQ_HZ; - sysInfo->freqPCI = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3; -} - -ulong -get_PCI_freq(void) -{ - ulong val; - PPC4xx_SYS_INFO sys_info; - - get_sys_info(&sys_info); - val = sys_info.freqPCI; - return val; -} - -#ifdef CONFIG_MISC_INIT_R - -int -misc_init_r() -{ - /* convert env name and value to u-boot standard */ - convert_env(); - return 0; -} - -#endif diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c deleted file mode 100644 index 4215513375..0000000000 --- a/board/xilinx/ml300/serial.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING - * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx hardware products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * - * (c) Copyright 2002-2004 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define USE_CHAN1 \ - ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN1)) -#define USE_CHAN2 \ - ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN2)) - -#if USE_CHAN1 -#include -#endif - -#if USE_CHAN1 -const NS16550_t COM_PORTS[] = { (NS16550_t) (XPAR_UARTNS550_0_BASEADDR + 3) -#if USE_CHAN2 - , (NS16550_t) (XPAR_UARTNS550_1_BASEADDR + 3) -#endif -}; -#endif - -int -serial_init(void) -{ -#if USE_CHAN1 - int clock_divisor; - - clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; - (void) NS16550_init(COM_PORTS[0], clock_divisor); -#if USE_CHAN2 - clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; - (void) NS16550_init(COM_PORTS[1], clock_divisor); -#endif -#endif - return 0; - -} - -void -serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - - NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c); -} - -int -serial_getc(void) -{ - return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -int -serial_tstc(void) -{ - return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -void -serial_setbrg(void) -{ -#if USE_CHAN1 - int clock_divisor; - - clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; - NS16550_reinit(COM_PORTS[0], clock_divisor); -#if USE_CHAN2 - clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif -#endif -} - -void -serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - -#if defined(CONFIG_CMD_KGDB) -void -kgdb_serial_init(void) -{ -} - -void -putDebugChar(int c) -{ - serial_putc(c); -} - -void -putDebugStr(const char *str) -{ - serial_puts(str); -} - -int -getDebugChar(void) -{ - return serial_getc(); -} - -void -kgdb_interruptible(int yes) -{ - return; -} -#endif diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds deleted file mode 100644 index b9899408d8..0000000000 --- a/board/xilinx/ml300/u-boot.lds +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -ENTRY(_start) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ -/* - cpu/ppc4xx/start.o (.text) - board/xilinx/ml300/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) -*/ -/* . = env_offset;*/ -/* common/env_embedded.o(.text)*/ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/xilinx/ml300/u-boot.lds.debug b/board/xilinx/ml300/u-boot.lds.debug deleted file mode 100644 index 970628d556..0000000000 --- a/board/xilinx/ml300/u-boot.lds.debug +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/xilinx/ml300/xparameters.h b/board/xilinx/ml300/xparameters.h deleted file mode 100644 index 2c56737dc5..0000000000 --- a/board/xilinx/ml300/xparameters.h +++ /dev/null @@ -1,196 +0,0 @@ -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 6.2 EDK_Gm.11 -* DO NOT EDIT. -* -* Copyright (c) 2003 Xilinx, Inc. All rights reserved. -* -* Description: Driver parameters -* -*******************************************************************/ - -/******************************************************************/ - -/* U-Boot Redefines */ - -/******************************************************************/ - -#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) -#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID -#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000) -#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR -#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID - -/******************************************************************/ - -#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR -#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR -#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR -#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR -#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR -#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT -#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST -#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST -#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ - -/******************************************************************/ - -#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 -#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF -#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 - -/******************************************************************/ - -#define XPAR_XPCI_NUM_INSTANCES 1 -#define XPAR_XPCI_CLOCK_HZ 33333333 -#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0 -#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000 -#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF -#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000 -#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004 -#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000 -#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000 -#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF -#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000 -#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF - -/******************************************************************/ - -#define XPAR_XEMAC_NUM_INSTANCES 1 -#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF -#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 -#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 -#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 -#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 - -/******************************************************************/ - -#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0 -#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000 -#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7) -#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1 -#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8) -#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F) -#define XPAR_XGPIO_NUM_INSTANCES 2 - -/******************************************************************/ - -#define XPAR_XIIC_NUM_INSTANCES 1 -#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 -#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF -#define XPAR_OPB_IIC_0_DEVICE_ID 0 -#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 - -/******************************************************************/ - -#define XPAR_XUARTNS550_NUM_INSTANCES 2 -#define XPAR_XUARTNS550_CLOCK_HZ 100000000 -#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 -#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF -#define XPAR_OPB_UART16550_0_DEVICE_ID 0 -#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000 -#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF -#define XPAR_OPB_UART16550_1_DEVICE_ID 1 - -/******************************************************************/ - -#define XPAR_XSPI_NUM_INSTANCES 1 -#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000 -#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F -#define XPAR_OPB_SPI_0_DEVICE_ID 0 -#define XPAR_OPB_SPI_0_FIFO_EXIST 1 -#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0 -#define XPAR_OPB_SPI_0_NUM_SS_BITS 1 - -/******************************************************************/ - -#define XPAR_XPS2_NUM_INSTANCES 2 -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) - -/******************************************************************/ - -#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1 -#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000 -#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007 -#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 -#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF -#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000 -#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF -#define XPAR_PLB_DDR_0_BASEADDR 0x00000000 -#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF - -/******************************************************************/ - -#define XPAR_XINTC_HAS_IPR 1 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18 -#define XPAR_XINTC_USE_DCR 0 -#define XPAR_XINTC_NUM_INSTANCES 1 -#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0 -#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF -#define XPAR_DCR_INTC_0_DEVICE_ID 0 -#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000 - -/******************************************************************/ - -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0 -#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1 -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2 -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3 -#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4 -#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5 -#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6 -#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7 -#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 -#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9 -#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10 -#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11 -#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12 -#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13 -#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14 -#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15 -#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16 -#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17 - -/******************************************************************/ - -#define XPAR_XTFT_NUM_INSTANCES 1 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 -#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_XSYSACE_MEM_WIDTH 8 -#define XPAR_XSYSACE_NUM_INSTANCES 1 -#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 -#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF -#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 -#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8 - -/******************************************************************/ - -#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 - -/******************************************************************/ diff --git a/board/xilinx/ppc405-generic/u-boot-rom.lds b/board/xilinx/ppc405-generic/u-boot-rom.lds index 02044e43d5..8fafbd59c0 100644 --- a/board/xilinx/ppc405-generic/u-boot-rom.lds +++ b/board/xilinx/ppc405-generic/u-boot-rom.lds @@ -33,7 +33,7 @@ SECTIONS .bootpg 0xFFFFF000 : { - cpu/ppc4xx/start.o (.bootpg) + arch/ppc/cpu/ppc4xx/start.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S index 1409467ea0..54f2d7fbc1 100644 --- a/board/xilinx/ppc440-generic/init.S +++ b/board/xilinx/ppc440-generic/init.S @@ -19,7 +19,7 @@ #include #include -#include +#include .section .bootpg,"ax" .globl tlbtab diff --git a/board/xilinx/ppc440-generic/u-boot-rom.lds b/board/xilinx/ppc440-generic/u-boot-rom.lds index 57c809e4cb..0cbed8ea57 100644 --- a/board/xilinx/ppc440-generic/u-boot-rom.lds +++ b/board/xilinx/ppc440-generic/u-boot-rom.lds @@ -33,7 +33,7 @@ SECTIONS .bootpg 0xFFFFF000 : { - cpu/ppc4xx/start.o (.bootpg) + arch/ppc/cpu/ppc4xx/start.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c deleted file mode 100644 index 58aaeb7695..0000000000 --- a/board/xilinx/xilinx_iic/iic_adapter.c +++ /dev/null @@ -1,529 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ - -#include -#include -#include -#include - -#ifdef CONFIG_ENV_IS_IN_EEPROM -#include -#include "xiic_l.h" - -#define IIC_DELAY 5000 - -static u8 envStep = 0; /* 0 means crc has not been read */ -const u8 hex[] = "0123456789ABCDEF"; /* lookup table for ML300 CRC */ - -/************************************************************************ - * Use Xilinx provided driver to send data to EEPROM using iic bus. - */ -static void -send(u32 adr, u8 * data, u32 len) -{ - u8 sendBuf[34]; /* first 2-bit is address and others are data */ - u32 pos, wlen; - u32 ret; - - wlen = 32; - for (pos = 0; pos < len; pos += 32) { - if ((len - pos) < 32) - wlen = len - pos; - - /* Put address and data bits together */ - sendBuf[0] = (u8) ((adr + pos) >> 8); - sendBuf[1] = (u8) (adr + pos); - memcpy(&sendBuf[2], &data[pos], wlen); - - /* Send to EEPROM through iic bus */ - ret = XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, - sendBuf, wlen + 2); - - udelay(IIC_DELAY); - } -} - -/************************************************************************ - * Use Xilinx provided driver to read data from EEPROM using the iic bus. - */ -static void -receive(u32 adr, u8 * data, u32 len) -{ - u8 address[2]; - u32 ret; - - address[0] = (u8) (adr >> 8); - address[1] = (u8) adr; - - /* Provide EEPROM address */ - ret = - XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, address, - 2); - /* Receive data from EEPROM */ - ret = - XIic_Recv(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, data, len); -} - -/************************************************************************ - * Convert a hexadecimal string to its equivalent integer value. - */ -static u8 -axtoi(u8 * hexStg) -{ - u8 n; /* position in string */ - u8 m; /* position in digit[] to shift */ - u8 count; /* loop index */ - u8 intValue; /* integer value of hex string */ - u8 digit[2]; /* hold values to convert */ - - for (n = 0; n < 2; n++) { - if (hexStg[n] == '\0') - break; - if (hexStg[n] > 0x29 && hexStg[n] < 0x40) - digit[n] = hexStg[n] & 0x0f; - else if (hexStg[n] >= 'a' && hexStg[n] <= 'f') - digit[n] = (hexStg[n] & 0x0f) + 9; - else if (hexStg[n] >= 'A' && hexStg[n] <= 'F') - digit[n] = (hexStg[n] & 0x0f) + 9; - else - break; - } - - intValue = 0; - count = n; - m = n - 1; - n = 0; - while (n < count) { - intValue = intValue | (digit[n] << (m << 2)); - m--; /* adjust the position to set */ - n++; /* next digit to process */ - } - - return (intValue); -} - -/************************************************************************ - * Convert an integer string to its equivalent value. - */ -static u8 -atoi(uchar * string) -{ - u8 res = 0; - while (*string >= '0' && *string <= '9') { - res *= 10; - res += *string - '0'; - string++; - } - - return res; -} - -/************************************************************************ - * Key-value pairs are separated by "=" sign. - */ -static void -findKey(uchar * buffer, int *loc, u8 len) -{ - u32 i; - - for (i = 0; i < len; i++) - if (buffer[i] == '=') { - *loc = i; - return; - } - - /* return -1 is no "=" sign found */ - *loc = -1; -} - -/************************************************************************ - * Compute a new ML300 CRC when user calls the saveenv command. - * Also update EEPROM with new CRC value. - */ -static u8 -update_crc(u32 len, uchar * data) -{ - uchar temp[6] = { 'C', '=', 0x00, 0x00, 0x00, 0x00 }; - u32 crc; /* new crc value */ - u32 i; - - crc = 0; - - /* calculate new CRC */ - for (i = 0; i < len; i++) - crc += data[i]; - - /* CRC includes key for check sum */ - crc += 'C' + '='; - - /* compose new CRC to be updated */ - temp[2] = hex[(crc >> 4) & 0xf]; - temp[3] = hex[crc & 0xf]; - - /* check to see if env size exceeded */ - if (len + 6 > ENV_SIZE) { - printf("ERROR: not enough space to store CRC on EEPROM"); - return 1; - } - - memcpy(data + len, temp, 6); - return 0; -} - -/************************************************************************ - * Read out ML300 CRC and compare it with a runtime calculated ML300 CRC. - * If equal, then pass back a u-boot CRC value, otherwise pass back - * junk to indicate CRC error. -*/ -static void -read_crc(uchar * buffer, int len) -{ - u32 addr, n; - u32 crc; /* runtime crc */ - u8 old[2] = { 0xff, 0xff }; /* current CRC in EEPROM */ - u8 stop; /* indication of end of env data */ - u8 pre; /* previous EEPROM data bit */ - int i, loc; - - addr = CONFIG_ENV_OFFSET; /* start from first env address */ - n = 0; - pre = 1; - stop = 1; - crc = 0; - - /* calculate runtime CRC according to ML300 and read back - old CRC stored in the EEPROM */ - while (n < CONFIG_ENV_SIZE) { - receive(addr, buffer, len); - - /* found two null chars, end of env */ - if ((pre || buffer[0]) == 0) - break; - - findKey(buffer, &loc, len); - - /* found old check sum, read and store old CRC */ - if ((loc == 0 && pre == 'C') - || (loc > 0 && buffer[loc - 1] == 'C')) - receive(addr + loc + 1, old, 2); - - pre = buffer[len - 1]; - - /* calculate runtime ML300 CRC */ - crc += buffer[0]; - i = 1; - do { - crc += buffer[i]; - stop = buffer[i] || buffer[i - 1]; - i++; - } while (stop && (i < len)); - - if (stop == 0) - break; - - n += len; - addr += len; - } - - /* exclude old CRC from runtime calculation */ - crc -= (old[0] + old[1]); - - /* match CRC values, send back u-boot CRC */ - if ((old[0] == hex[(crc >> 4) & 0xf]) - && (old[1] == hex[crc & 0xf])) { - crc = 0; - n = 0; - addr = - CONFIG_ENV_OFFSET - offsetof(env_t, crc) + offsetof(env_t, - data); - /* calculate u-boot crc */ - while (n < ENV_SIZE) { - receive(addr, buffer, len); - crc = crc32(crc, buffer, len); - n += len; - addr += len; - } - - memcpy(buffer, &crc, 4); - } -} - -/************************************************************************ - * Convert IP address to hexadecimals. - */ -static void -ip_ml300(uchar * s, uchar * res) -{ - char temp[2]; - u8 i; - - res[0] = 0x00; - - for (i = 0; i < 4; i++) { - sprintf(temp, "%02x", atoi(s)); - s = (uchar *)strchr((char *)s, '.') + 1; - strcat((char *)res, temp); - } -} - -/************************************************************************ - * Change 0xff (255), a dummy null char to 0x00. - */ -static void -change_null(uchar * s) -{ - if (s != NULL) { - change_null((uchar *)strchr((char *)s + 1, 255)); - *(strchr((char *)s, 255)) = '\0'; - } -} - -/************************************************************************ - * Update environment variable name and values to u-boot standard. - */ -void -convert_env(void) -{ - char *s; /* pointer to env value */ - char temp[20]; /* temp storage for addresses */ - - /* E -> ethaddr */ - s = getenv("E"); - if (s != NULL) { - sprintf(temp, "%c%c.%c%c.%c%c.%c%c.%c%c.%c%c", - s[0], s[1], s[ 2], s[ 3], - s[4], s[5], s[ 6], s[ 7], - s[8], s[9], s[10], s[11] ); - setenv("ethaddr", temp); - setenv("E", NULL); - } - - /* L -> serial# */ - s = getenv("L"); - if (s != NULL) { - setenv("serial#", s); - setenv("L", NULL); - } - - /* I -> ipaddr */ - s = getenv("I"); - if (s != NULL) { - sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)), - axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6))); - setenv("ipaddr", temp); - setenv("I", NULL); - } - - /* S -> serverip */ - s = getenv("S"); - if (s != NULL) { - sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)), - axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6))); - setenv("serverip", temp); - setenv("S", NULL); - } - - /* A -> bootargs */ - s = getenv("A"); - if (s != NULL) { - setenv("bootargs", s); - setenv("A", NULL); - } - - /* F -> bootfile */ - s = getenv("F"); - if (s != NULL) { - setenv("bootfile", s); - setenv("F", NULL); - } - - /* M -> bootcmd */ - s = getenv("M"); - if (s != NULL) { - setenv("bootcmd", s); - setenv("M", NULL); - } - - /* Don't include C (CRC) */ - setenv("C", NULL); -} - -/************************************************************************ - * Save user modified environment values back to EEPROM. - */ -static void -save_env(void) -{ - char eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */ - char *s, temp[20]; - char ff[] = { 0xff, 0x00 }; /* dummy null value */ - u32 len; /* length of env to be written to EEPROM */ - - eprom[0] = 0x00; - - /* ethaddr -> E */ - s = getenv("ethaddr"); - if (s != NULL) { - strcat(eprom, "E="); - sprintf(temp, "%c%c%c%c%c%c%c%c%c%c%c%c", - *s, *(s + 1), *(s + 3), *(s + 4), *(s + 6), *(s + 7), - *(s + 9), *(s + 10), *(s + 12), *(s + 13), *(s + 15), - *(s + 16)); - strcat(eprom, temp); - strcat(eprom, ff); - } - - /* serial# -> L */ - s = getenv("serial#"); - if (s != NULL) { - strcat(eprom, "L="); - strcat(eprom, s); - strcat(eprom, ff); - } - - /* ipaddr -> I */ - s = getenv("ipaddr"); - if (s != NULL) { - strcat(eprom, "I="); - ip_ml300((uchar *)s, (uchar *)temp); - strcat(eprom, temp); - strcat(eprom, ff); - } - - /* serverip -> S */ - s = getenv("serverip"); - if (s != NULL) { - strcat(eprom, "S="); - ip_ml300((uchar *)s, (uchar *)temp); - strcat(eprom, temp); - strcat(eprom, ff); - } - - /* bootargs -> A */ - s = getenv("bootargs"); - if (s != NULL) { - strcat(eprom, "A="); - strcat(eprom, s); - strcat(eprom, ff); - } - - /* bootfile -> F */ - s = getenv("bootfile"); - if (s != NULL) { - strcat(eprom, "F="); - strcat(eprom, s); - strcat(eprom, ff); - } - - /* bootcmd -> M */ - s = getenv("bootcmd"); - if (s != NULL) { - strcat(eprom, "M="); - strcat(eprom, s); - strcat(eprom, ff); - } - - len = strlen(eprom); /* find env length without crc */ - change_null((uchar *)eprom); /* change 0xff to 0x00 */ - - /* update EEPROM env values if there is enough space */ - if (update_crc(len, (uchar *)eprom) == 0) - send(CONFIG_ENV_OFFSET, (uchar *)eprom, len + 6); -} - -/************************************************************************ - * U-boot call for EEPROM read associated activities. - */ -int -i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - - if (envStep == 0) { - /* first read call is for crc */ - read_crc(buffer, len); - ++envStep; - return 0; - } else if (envStep == 1) { - /* then read out EEPROM content for runtime u-boot CRC calculation */ - receive(addr, buffer, len); - - if (addr + len - CONFIG_ENV_OFFSET == CONFIG_ENV_SIZE) - /* end of runtime crc read */ - ++envStep; - return 0; - } - - if (len < 2) { - /* when call getenv_r */ - receive(addr, buffer, len); - } else if (addr + len < CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) { - /* calling env_relocate(), but don't read out - crc value from EEPROM */ - receive(addr, buffer + 4, len); - } else { - receive(addr, buffer + 4, len - 4); - } - - return 0; - -} - -/************************************************************************ - * U-boot call for EEPROM write acativities. - */ -int -i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - /* save env on last page write called by u-boot */ - if (addr + len >= CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) - save_env(); - - return 0; -} - -/************************************************************************ - * Dummy function. - */ -int -i2c_probe(uchar chip) -{ - return 1; -} - -#endif diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index f8400bcc04..d22eb6634a 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; static void print_num(const char *, ulong); -#if !defined(CONFIG_ARM) || defined(CONFIG_CMD_NET) +#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET) static void print_eth(int idx); #endif @@ -350,7 +350,7 @@ static void print_num(const char *name, ulong value) printf ("%-12s= 0x%08lX\n", name, value); } -#if !defined(CONFIG_ARM) || defined(CONFIG_CMD_NET) +#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET) static void print_eth(int idx) { char name[10], *val; diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index 74ab24ca94..583b0090cb 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -90,6 +90,54 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) } #endif +static int do_bmp_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + switch (argc) { + case 1: /* use load_addr as default address */ + addr = load_addr; + break; + case 2: /* use argument */ + addr = simple_strtoul(argv[1], NULL, 16); + break; + default: + cmd_usage(cmdtp); + return 1; + } + + return (bmp_info(addr)); +} + +static int do_bmp_display(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + int x = 0, y = 0; + + switch (argc) { + case 1: /* use load_addr as default address */ + addr = load_addr; + break; + case 2: /* use argument */ + addr = simple_strtoul(argv[1], NULL, 16); + break; + case 4: + addr = simple_strtoul(argv[1], NULL, 16); + x = simple_strtoul(argv[2], NULL, 10); + y = simple_strtoul(argv[3], NULL, 10); + break; + default: + cmd_usage(cmdtp); + return 1; + } + + return (bmp_display(addr, x, y)); +} + +static cmd_tbl_t cmd_bmp_sub[] = { + U_BOOT_CMD_MKENT(info, 3, 0, do_bmp_info, "", ""), + U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""), +}; /* * Subroutine: do_bmp @@ -101,35 +149,18 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) * Return: None * */ -int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong addr; - int x = 0, y = 0; + cmd_tbl_t *c; - switch (argc) { - case 2: /* use load_addr as default address */ - addr = load_addr; - break; - case 3: /* use argument */ - addr = simple_strtoul(argv[2], NULL, 16); - break; - case 5: - addr = simple_strtoul(argv[2], NULL, 16); - x = simple_strtoul(argv[3], NULL, 10); - y = simple_strtoul(argv[4], NULL, 10); - break; - default: - cmd_usage(cmdtp); - return 1; - } + /* Strip off leading 'bmp' command argument */ + argc--; + argv++; - /* Allow for short names - * Adjust length if more sub-commands get added - */ - if (strncmp(argv[1],"info",1) == 0) { - return (bmp_info(addr)); - } else if (strncmp(argv[1],"display",1) == 0) { - return (bmp_display(addr, x, y)); + c = find_cmd_tbl(argv[0], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub)); + + if (c) { + return c->cmd(cmdtp, flag, argc, argv); } else { cmd_usage(cmdtp); return 1; diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 23ab0c4aae..452686dd3d 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -291,7 +291,8 @@ static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - if ((images.os.type == IH_TYPE_KERNEL) && + if (((images.os.type == IH_TYPE_KERNEL) || + (images.os.type == IH_TYPE_MULTI)) && (images.os.os == IH_OS_LINUX)) { /* find ramdisk */ ret = boot_get_ramdisk (argc, argv, &images, IH_INITRD_ARCH, @@ -462,7 +463,7 @@ static int bootm_start_standalone(ulong iflag, int argc, char *argv[]) /* we overload the cmd field with our state machine info instead of a * function pointer */ -cmd_tbl_t cmd_bootm_sub[] = { +static cmd_tbl_t cmd_bootm_sub[] = { U_BOOT_CMD_MKENT(start, 0, 1, (void *)BOOTM_STATE_START, "", ""), U_BOOT_CMD_MKENT(loados, 0, 1, (void *)BOOTM_STATE_LOADOS, "", ""), #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 62cbd335e5..8b9c2c9490 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -130,6 +130,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif +#define DISP_LINE_LEN 16 + /* TODO: Implement architecture-specific get/set functions */ unsigned int __def_i2c_get_bus_speed(void) { @@ -148,13 +150,83 @@ int __def_i2c_set_bus_speed(unsigned int speed) int i2c_set_bus_speed(unsigned int) __attribute__((weak, alias("__def_i2c_set_bus_speed"))); +/* + * get_alen: small parser helper function to get address length + * returns the address length,or 0 on error + */ +static uint get_alen(char *arg) +{ + int j; + int alen; + + alen = 1; + for (j = 0; j < 8; j++) { + if (arg[j] == '.') { + alen = arg[j+1] - '0'; + if (alen > 3) { + return 0; + } + break; + } else if (arg[j] == '\0') + break; + } + return alen; +} + +/* + * Syntax: + * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr} + */ + +static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u_char chip; + uint devaddr, alen, length; + u_char *memaddr; + + if (argc != 5) { + cmd_usage(cmdtp); + return 1; + } + + /* + * I2C chip address + */ + chip = simple_strtoul(argv[1], NULL, 16); + + /* + * I2C data address within the chip. This can be 1 or + * 2 bytes long. Some day it might be 3 bytes long :-). + */ + devaddr = simple_strtoul(argv[2], NULL, 16); + alen = get_alen(argv[2]); + if (alen == 0) { + cmd_usage(cmdtp); + return 1; + } + + /* + * Length is the number of objects, not number of bytes. + */ + length = simple_strtoul(argv[3], NULL, 16); + + /* + * memaddr is the address where to store things in memory + */ + memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16); + + if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) { + puts ("Error reading the chip.\n"); + return 1; + } + return 0; +} + /* * Syntax: * i2c md {i2c_chip} {addr}{.0, .1, .2} {len} */ -#define DISP_LINE_LEN 16 - -int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { u_char chip; uint addr, alen, length; @@ -177,7 +249,6 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * New command specified. */ - alen = 1; /* * I2C chip address @@ -189,17 +260,10 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * 2 bytes long. Some day it might be 3 bytes long :-). */ addr = simple_strtoul(argv[2], NULL, 16); - alen = 1; - for (j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; - if (alen > 4) { - cmd_usage(cmdtp); - return 1; - } - break; - } else if (argv[2][j] == '\0') - break; + alen = get_alen(argv[2]); + if (alen == 0) { + cmd_usage(cmdtp); + return 1; } /* @@ -260,14 +324,13 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Syntax: * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] */ -int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { uchar chip; ulong addr; uint alen; uchar byte; int count; - int j; if ((argc < 4) || (argc > 5)) { cmd_usage(cmdtp); @@ -283,17 +346,10 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); - alen = 1; - for (j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; - if (alen > 4) { - cmd_usage(cmdtp); - return 1; - } - break; - } else if (argv[2][j] == '\0') - break; + alen = get_alen(argv[2]); + if (alen == 0) { + cmd_usage(cmdtp); + return 1; } /* @@ -332,7 +388,7 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Syntax: * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count} */ -int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { uchar chip; ulong addr; @@ -341,7 +397,6 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) uchar byte; ulong crc; ulong err; - int j; if (argc < 4) { cmd_usage(cmdtp); @@ -357,17 +412,10 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); - alen = 1; - for (j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; - if (alen > 4) { - cmd_usage(cmdtp); - return 1; - } - break; - } else if (argv[2][j] == '\0') - break; + alen = get_alen(argv[2]); + if (alen == 0) { + cmd_usage(cmdtp); + return 1; } /* @@ -412,7 +460,6 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) ulong data; int size = 1; int nbytes; - int j; extern char console_buffer[]; if (argc != 3) { @@ -447,17 +494,10 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); - alen = 1; - for (j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; - if (alen > 4) { - cmd_usage(cmdtp); - return 1; - } - break; - } else if (argv[2][j] == '\0') - break; + alen = get_alen(argv[2]); + if (alen == 0) { + cmd_usage(cmdtp); + return 1; } } @@ -535,7 +575,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) * Syntax: * i2c probe {addr}{.0, .1, .2} */ -int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int j; #if defined(CONFIG_SYS_I2C_NOPROBES) @@ -579,7 +619,7 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * {length} - Number of bytes to read * {delay} - A DECIMAL number and defaults to 1000 uSec */ -int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { u_char chip; ulong alen; @@ -587,7 +627,6 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) uint length; u_char bytes[16]; int delay; - int j; if (argc < 3) { cmd_usage(cmdtp); @@ -603,17 +642,10 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); - alen = 1; - for (j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; - if (alen > 4) { - cmd_usage(cmdtp); - return 1; - } - break; - } else if (argv[2][j] == '\0') - break; + alen = get_alen(argv[2]); + if (alen == 0) { + cmd_usage(cmdtp); + return 1; } /* @@ -699,7 +731,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once) * Syntax: * i2c sdram {i2c_chip} */ -int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { enum { unknown, EDO, SDRAM, DDR2 } type; @@ -1176,7 +1208,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #endif #if defined(CONFIG_I2C_MUX) -int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int ret=0; @@ -1207,7 +1239,7 @@ int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #endif /* CONFIG_I2C_MUX */ #if defined(CONFIG_I2C_MULTI_BUS) -int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int bus_idx, ret=0; @@ -1225,7 +1257,7 @@ int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } #endif /* CONFIG_I2C_MULTI_BUS */ -int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int speed, ret=0; @@ -1242,46 +1274,60 @@ int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return ret; } -int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { + return mod_i2c_mem (cmdtp, 1, flag, argc, argv); +} + +static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + return mod_i2c_mem (cmdtp, 0, flag, argc, argv); +} + +static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + return 0; +} + +static cmd_tbl_t cmd_i2c_sub[] = { +#if defined(CONFIG_I2C_MUX) + U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""), +#endif /* CONFIG_I2C_MUX */ + U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""), +#if defined(CONFIG_I2C_MULTI_BUS) + U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""), +#endif /* CONFIG_I2C_MULTI_BUS */ + U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""), + U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""), + U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""), + U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""), + U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""), + U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""), + U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""), + U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""), +#if defined(CONFIG_CMD_SDRAM) + U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""), +#endif + U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""), +}; + +static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + cmd_tbl_t *c; + /* Strip off leading 'i2c' command argument */ argc--; argv++; -#if defined(CONFIG_I2C_MUX) - if (!strncmp(argv[0], "bu", 2)) - return do_i2c_add_bus(cmdtp, flag, argc, argv); -#endif /* CONFIG_I2C_MUX */ - if (!strncmp(argv[0], "sp", 2)) - return do_i2c_bus_speed(cmdtp, flag, argc, argv); -#if defined(CONFIG_I2C_MULTI_BUS) - if (!strncmp(argv[0], "de", 2)) - return do_i2c_bus_num(cmdtp, flag, argc, argv); -#endif /* CONFIG_I2C_MULTI_BUS */ - if (!strncmp(argv[0], "md", 2)) - return do_i2c_md(cmdtp, flag, argc, argv); - if (!strncmp(argv[0], "mm", 2)) - return mod_i2c_mem (cmdtp, 1, flag, argc, argv); - if (!strncmp(argv[0], "mw", 2)) - return do_i2c_mw(cmdtp, flag, argc, argv); - if (!strncmp(argv[0], "nm", 2)) - return mod_i2c_mem (cmdtp, 0, flag, argc, argv); - if (!strncmp(argv[0], "cr", 2)) - return do_i2c_crc(cmdtp, flag, argc, argv); - if (!strncmp(argv[0], "pr", 2)) - return do_i2c_probe(cmdtp, flag, argc, argv); - if (!strncmp(argv[0], "re", 2)) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 0; + c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub)); + + if (c) { + return c->cmd(cmdtp, flag, argc, argv); + } else { + cmd_usage(cmdtp); + return 1; } - if (!strncmp(argv[0], "lo", 2)) - return do_i2c_loop(cmdtp, flag, argc, argv); -#if defined(CONFIG_CMD_SDRAM) - if (!strncmp(argv[0], "sd", 2)) - return do_sdram(cmdtp, flag, argc, argv); -#endif - cmd_usage(cmdtp); - return 0; } /***************************************************/ @@ -1289,30 +1335,29 @@ int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( i2c, 6, 1, do_i2c, "I2C sub-system", - "speed [speed] - show or set I2C bus speed\n" #if defined(CONFIG_I2C_MUX) - "i2c bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\n" + "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c " #endif /* CONFIG_I2C_MUX */ + "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" #if defined(CONFIG_I2C_MULTI_BUS) "i2c dev [dev] - show or set current I2C bus\n" #endif /* CONFIG_I2C_MULTI_BUS */ + "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n" "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n" "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n" "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" - "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" "i2c probe - show devices on the I2C bus\n" + "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n" "i2c reset - re-init the I2C Controller\n" - "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device" #if defined(CONFIG_CMD_SDRAM) - "\n" - "i2c sdram chip - print SDRAM configuration information" + "i2c sdram chip - print SDRAM configuration information\n" #endif + "i2c speed [speed] - show or set I2C bus speed" ); #if defined(CONFIG_I2C_MUX) - -int i2c_mux_add_device(I2C_MUX_DEVICE *dev) +static int i2c_mux_add_device(I2C_MUX_DEVICE *dev) { I2C_MUX_DEVICE *devtmp = i2c_mux_devices; diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c index 20fed2aadc..0b5f747141 100644 --- a/common/cmd_mtdparts.c +++ b/common/cmd_mtdparts.c @@ -776,7 +776,7 @@ static int device_del(struct mtd_device *dev) * @param num device number * @return NULL if requested device does not exist */ -static struct mtd_device* device_find(u8 type, u8 num) +struct mtd_device *device_find(u8 type, u8 num) { struct list_head *entry; struct mtd_device *dev_tmp; diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 075a8afb60..9b0c930530 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -327,8 +327,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "are sure of what you are doing!\n" "\nReally scrub this NAND flash? \n"); - if (getc() == 'y' && getc() == '\r') { - opts.scrub = 1; + if (getc() == 'y') { + puts("y"); + if (getc() == '\r') + opts.scrub = 1; + else { + puts("scrub aborted\n"); + return -1; + } } else { puts("scrub aborted\n"); return -1; diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c index f8b5d4dcfe..2d3719755e 100644 --- a/common/cmd_setexpr.c +++ b/common/cmd_setexpr.c @@ -28,10 +28,33 @@ #include #include +static ulong get_arg(char *s, int w) +{ + ulong *p; + + /* + * if the parameter starts with a '*' then assume + * it is a pointer to the value we want + */ + + if (s[0] == '*') { + p = (ulong *)simple_strtoul(&s[1], NULL, 16); + switch (w) { + case 1: return((ulong)(*(uchar *)p)); + case 2: return((ulong)(*(ushort *)p)); + case 4: + default: return(*p); + } + } else { + return simple_strtoul(s, NULL, 16); + } +} + int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong a, b; char buf[16]; + int w; /* Validate arguments */ if ((argc != 5) || (strlen(argv[3]) != 1)) { @@ -39,8 +62,10 @@ int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - a = simple_strtoul(argv[2], NULL, 16); - b = simple_strtoul(argv[4], NULL, 16); + w = cmd_get_data_size(argv[0], 4); + + a = get_arg(argv[2], w); + b = get_arg(argv[4], w); switch (argv[3][0]) { case '|': sprintf(buf, "%lx", (a | b)); break; @@ -64,7 +89,8 @@ int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( setexpr, 5, 0, do_setexpr, "set environment variable as the result of eval expression", - "name value1 value2\n" + "[.b, .w, .l] name value1 value2\n" " - set environment variable 'name' to the result of the evaluated\n" - " express specified by . can be &, |, ^, +, -, *, /, %" + " express specified by . can be &, |, ^, +, -, *, /, %\n" + " size argument is only meaningful if value1 and/or value2 are memory addresses" ); diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 54faac1c93..2484b40491 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -190,7 +190,7 @@ static int ubi_remove_vol(char *volume) { int i, err, reserved_pebs; int found = 0, vol_id = 0; - struct ubi_volume *vol; + struct ubi_volume *vol = NULL; for (i = 0; i < ubi->vtbl_slots; i++) { vol = ubi->volumes[i]; diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 9de515c323..ee3755c121 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -387,7 +387,7 @@ int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) dev = simple_strtoul(boot_device, &ep, 16); stor_dev = usb_stor_get_dev(dev); - if (stor_dev->type == DEV_TYPE_UNKNOWN) { + if (stor_dev == NULL || stor_dev->type == DEV_TYPE_UNKNOWN) { printf("\n** Device %d not available\n", dev); return 1; } @@ -595,22 +595,25 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (strncmp(argv[1], "part", 4) == 0) { int devno, ok = 0; if (argc == 2) { - for (devno = 0; devno < USB_MAX_STOR_DEV; ++devno) { + for (devno = 0; ; ++devno) { stor_dev = usb_stor_get_dev(devno); + if (stor_dev == NULL) + break; if (stor_dev->type != DEV_TYPE_UNKNOWN) { ok++; if (devno) printf("\n"); - printf("print_part of %x\n", devno); + debug("print_part of %x\n", devno); print_part(stor_dev); } } } else { devno = simple_strtoul(argv[2], NULL, 16); stor_dev = usb_stor_get_dev(devno); - if (stor_dev->type != DEV_TYPE_UNKNOWN) { + if (stor_dev != NULL && + stor_dev->type != DEV_TYPE_UNKNOWN) { ok++; - printf("print_part of %x\n", devno); + debug("print_part of %x\n", devno); print_part(stor_dev); } } @@ -668,12 +671,12 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (argc == 3) { int dev = (int)simple_strtoul(argv[2], NULL, 10); printf("\nUSB device %d: ", dev); - if (dev >= USB_MAX_STOR_DEV) { + stor_dev = usb_stor_get_dev(dev); + if (stor_dev == NULL) { printf("unknown device\n"); return 1; } printf("\n Device %d: ", dev); - stor_dev = usb_stor_get_dev(dev); dev_print(stor_dev); if (stor_dev->type == DEV_TYPE_UNKNOWN) return 1; diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 205fc40ac8..2276532da7 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1515,7 +1515,7 @@ void *sbrk(ptrdiff_t increment) ulong new = old + increment; if ((new < mem_malloc_start) || (new > mem_malloc_end)) - return NULL; + return (void *)MORECORE_FAILURE; mem_malloc_brk = new; diff --git a/common/fdt_support.c b/common/fdt_support.c index f89a3eef66..b6f252a87b 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -757,3 +757,235 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size) return -1; } #endif + +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include + +struct reg_cell { + unsigned int r0; + unsigned int r1; +}; + +int fdt_del_subnodes(const void *blob, int parent_offset) +{ + int off, ndepth; + int ret; + + for (ndepth = 0, off = fdt_next_node(blob, parent_offset, &ndepth); + (off >= 0) && (ndepth > 0); + off = fdt_next_node(blob, off, &ndepth)) { + if (ndepth == 1) { + debug("delete %s: offset: %x\n", + fdt_get_name(blob, off, 0), off); + ret = fdt_del_node((void *)blob, off); + if (ret < 0) { + printf("Can't delete node: %s\n", + fdt_strerror(ret)); + return ret; + } else { + ndepth = 0; + off = parent_offset; + } + } + } + return 0; +} + +int fdt_increase_size(void *fdt, int add_len) +{ + int newlen; + + newlen = fdt_totalsize(fdt) + add_len; + + /* Open in place with a new len */ + return fdt_open_into(fdt, fdt, newlen); +} + +int fdt_del_partitions(void *blob, int parent_offset) +{ + const void *prop; + int ndepth = 0; + int off; + int ret; + + off = fdt_next_node(blob, parent_offset, &ndepth); + if (off > 0 && ndepth == 1) { + prop = fdt_getprop(blob, off, "label", NULL); + if (prop == NULL) { + /* + * Could not find label property, nand {}; node? + * Check subnode, delete partitions there if any. + */ + return fdt_del_partitions(blob, off); + } else { + ret = fdt_del_subnodes(blob, parent_offset); + if (ret < 0) { + printf("Can't remove subnodes: %s\n", + fdt_strerror(ret)); + return ret; + } + } + } + return 0; +} + +int fdt_node_set_part_info(void *blob, int parent_offset, + struct mtd_device *dev) +{ + struct list_head *pentry; + struct part_info *part; + struct reg_cell cell; + int off, ndepth = 0; + int part_num, ret; + char buf[64]; + + ret = fdt_del_partitions(blob, parent_offset); + if (ret < 0) + return ret; + + /* + * Check if it is nand {}; subnode, adjust + * the offset in this case + */ + off = fdt_next_node(blob, parent_offset, &ndepth); + if (off > 0 && ndepth == 1) + parent_offset = off; + + part_num = 0; + list_for_each_prev(pentry, &dev->parts) { + int newoff; + + part = list_entry(pentry, struct part_info, link); + + debug("%2d: %-20s0x%08x\t0x%08x\t%d\n", + part_num, part->name, part->size, + part->offset, part->mask_flags); + + sprintf(buf, "partition@%x", part->offset); +add_sub: + ret = fdt_add_subnode(blob, parent_offset, buf); + if (ret == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob, 512); + if (!ret) + goto add_sub; + else + goto err_size; + } else if (ret < 0) { + printf("Can't add partition node: %s\n", + fdt_strerror(ret)); + return ret; + } + newoff = ret; + + /* Check MTD_WRITEABLE_CMD flag */ + if (part->mask_flags & 1) { +add_ro: + ret = fdt_setprop(blob, newoff, "read_only", NULL, 0); + if (ret == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob, 512); + if (!ret) + goto add_ro; + else + goto err_size; + } else if (ret < 0) + goto err_prop; + } + + cell.r0 = cpu_to_fdt32(part->offset); + cell.r1 = cpu_to_fdt32(part->size); +add_reg: + ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell)); + if (ret == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob, 512); + if (!ret) + goto add_reg; + else + goto err_size; + } else if (ret < 0) + goto err_prop; + +add_label: + ret = fdt_setprop_string(blob, newoff, "label", part->name); + if (ret == -FDT_ERR_NOSPACE) { + ret = fdt_increase_size(blob, 512); + if (!ret) + goto add_label; + else + goto err_size; + } else if (ret < 0) + goto err_prop; + + part_num++; + } + return 0; +err_size: + printf("Can't increase blob size: %s\n", fdt_strerror(ret)); + return ret; +err_prop: + printf("Can't add property: %s\n", fdt_strerror(ret)); + return ret; +} + +/* + * Update partitions in nor/nand nodes using info from + * mtdparts environment variable. The nodes to update are + * specified by node_info structure which contains mtd device + * type and compatible string: E. g. the board code in + * ft_board_setup() could use: + * + * struct node_info nodes[] = { + * { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, }, + * { "cfi-flash", MTD_DEV_TYPE_NOR, }, + * }; + * + * fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + */ +void fdt_fixup_mtdparts(void *blob, void *node_info, int node_info_size) +{ + struct node_info *ni = node_info; + struct mtd_device *dev; + char *parts; + int i, idx; + int noff; + + parts = getenv("mtdparts"); + if (!parts) + return; + + if (mtdparts_init() != 0) + return; + + for (i = 0; i < node_info_size; i++) { + idx = 0; + noff = fdt_node_offset_by_compatible(blob, -1, ni[i].compat); + while (noff != -FDT_ERR_NOTFOUND) { + debug("%s: %s, mtd dev type %d\n", + fdt_get_name(blob, noff, 0), + ni[i].compat, ni[i].type); + dev = device_find(ni[i].type, idx++); + if (dev) { + if (fdt_node_set_part_info(blob, noff, dev)) + return; /* return on error */ + } + + /* Jump to next flash node */ + noff = fdt_node_offset_by_compatible(blob, noff, + ni[i].compat); + } + } +} +#endif + +void fdt_del_node_and_alias(void *blob, const char *alias) +{ + int off = fdt_path_offset(blob, alias); + + if (off < 0) + return; + + fdt_del_node(blob, off); + + off = fdt_path_offset(blob, "/aliases"); + fdt_delprop(blob, off, alias); +} diff --git a/common/lcd.c b/common/lcd.c index db799db6b2..64fb1c6408 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -63,7 +63,7 @@ /************************************************************************/ #ifdef CONFIG_LCD_LOGO # include /* Get logo data, width and height */ -# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) +# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP != LCD_COLOR16) # error Default Color Map overlaps with Logo Color Map # endif #endif @@ -218,8 +218,12 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { uchar *s = str; - uchar *d = dest; int i; +#if LCD_BPP == LCD_COLOR16 + ushort *d = (ushort *)dest; +#else + uchar *d = dest; +#endif #if LCD_BPP == LCD_MONOCHROME uchar rest = *d & -(1 << (8-off)); @@ -244,7 +248,7 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) bits <<= 1; } #elif LCD_BPP == LCD_COLOR16 - for (c=0; c<16; ++c) { + for (c=0; c<8; ++c) { *d++ = (bits & 0x80) ? lcd_color_fg : lcd_color_bg; bits <<= 1; @@ -521,6 +525,13 @@ void bitmap_plot (int x, int y) cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); #elif defined(CONFIG_ATMEL_LCD) cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0)); +#else + /* + * default case: generic system with no cmap (most likely 16bpp) + * We set cmap to the source palette, so no change is done. + * This avoids even more ifdef in the next stanza + */ + cmap = bmp_logo_palette; #endif WATCHDOG_RESET(); @@ -559,10 +570,15 @@ void bitmap_plot (int x, int y) } } else { /* true color mode */ + u16 col16; fb16 = (ushort *)(lcd_base + y * lcd_line_length + x); for (i=0; i= 0 && get_ticks() > endtime) return (-2); /* timed out */ + WATCHDOG_RESET(); } #endif @@ -997,6 +998,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) while (!tstc()) { /* while no incoming data */ if (retry_time >= 0 && get_ticks() > endtime) return (-2); /* timed out */ + WATCHDOG_RESET(); } #endif WATCHDOG_RESET(); /* Trigger watchdog, if needed */ @@ -1005,6 +1007,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) while (!tstc()) { extern void show_activity(int arg); show_activity(0); + WATCHDOG_RESET(); } #endif c = getc(); diff --git a/common/usb_storage.c b/common/usb_storage.c index a8642c9cc5..4fc01a22b4 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -175,7 +175,7 @@ void uhci_show_temp_int_td(void); block_dev_desc_t *usb_stor_get_dev(int index) { - return (index < USB_MAX_STOR_DEV) ? &usb_dev_desc[index] : NULL; + return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL; } @@ -244,7 +244,7 @@ int usb_stor_scan(int mode) * get info and fill it in */ if (usb_stor_get_info(dev, &usb_stor[usb_max_devs], - &usb_dev_desc[usb_max_devs])) + &usb_dev_desc[usb_max_devs]) == 1) usb_max_devs++; } /* if storage device */ @@ -888,7 +888,7 @@ static int usb_inquiry(ccb *srb, struct us_data *ss) USB_STOR_PRINTF("inquiry returns %d\n", i); if (i == 0) break; - } while (retry--); + } while (--retry); if (!retry) { printf("error in inquiry\n"); diff --git a/config.mk b/config.mk index cb1c4af977..73b5195cb6 100644 --- a/config.mk +++ b/config.mk @@ -110,14 +110,20 @@ RANLIB = $(CROSS_COMPILE)RANLIB # Load generated board configuration sinclude $(OBJTREE)/include/autoconf.mk -ifdef ARCH -sinclude $(TOPDIR)/lib_$(ARCH)/config.mk # include architecture dependend rules -endif -ifdef CPU -sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules +# Some architecture config.mk files need to know what CPUDIR is set to, +# so calculate CPUDIR before including ARCH/SOC/CPU config.mk files. +# Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains +# CPU-specific code. +CPUDIR=arch/$(ARCH)/cpu/$(CPU) +ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR))) +CPUDIR=arch/$(ARCH)/cpu endif + +sinclude $(TOPDIR)/arch/$(ARCH)/config.mk # include architecture dependend rules +sinclude $(TOPDIR)/$(CPUDIR)/config.mk # include CPU specific rules + ifdef SOC -sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk # include SoC specific rules +sinclude $(TOPDIR)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules endif ifdef VENDOR BOARDDIR = $(VENDOR)/$(BOARD) @@ -235,16 +241,21 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS ######################################################################### # Allow boards to use custom optimize flags on a per dir/file basis -BCURDIR := $(notdir $(CURDIR)) +BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%)) $(obj)%.s: %.S - $(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< + $(CPP) $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) \ + -o $@ $< $(obj)%.o: %.S - $(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c + $(CC) $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) \ + -o $@ $< -c $(obj)%.o: %.c - $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c + $(CC) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ + -o $@ $< -c $(obj)%.i: %.c - $(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c + $(CPP) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ + -o $@ $< -c $(obj)%.s: %.c - $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S + $(CC) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ + -o $@ $< -c -S ######################################################################### diff --git a/cpu/arm1136/u-boot.lds b/cpu/arm1136/u-boot.lds deleted file mode 100644 index 7181a569ea..0000000000 --- a/cpu/arm1136/u-boot.lds +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, - * - * Copyright (C) 2005-2007 Samsung Electronics - * Kyungin Park - * - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm1176/u-boot.lds b/cpu/arm1176/u-boot.lds deleted file mode 100644 index cc682f54df..0000000000 --- a/cpu/arm1176/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1176/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm720t/u-boot.lds b/cpu/arm720t/u-boot.lds deleted file mode 100644 index 111c3f5a6a..0000000000 --- a/cpu/arm720t/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm720t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c deleted file mode 100644 index 31304b7f97..0000000000 --- a/cpu/arm920t/ep93xx/timer.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Cirrus Logic EP93xx timer support. - * - * Copyright (C) 2009, 2010 - * Matthias Kaehlcke - * - * Copyright (C) 2004, 2005 - * Cory T. Tusar, Videon Central, Inc., - * - * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support, - * author unknown. - * - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#define TIMER_CLKSEL (1 << 3) -#define TIMER_ENABLE (1 << 7) - -#define TIMER_FREQ 508469 /* ticks / second */ -#define TIMER_MAX_VAL 0xFFFFFFFF - -static struct ep93xx_timer -{ - unsigned long long ticks; - unsigned long last_update; -} timer; - -static inline unsigned long clk_to_systicks(unsigned long long clk_ticks) -{ - unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ); - do_div(sys_ticks, TIMER_FREQ); - - return (unsigned long)sys_ticks; -} - -static inline unsigned long long usecs_to_ticks(unsigned long usecs) -{ - unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ; - do_div(ticks, 1000 * 1000); - - return ticks; -} - -static inline unsigned long read_timer(void) -{ - struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; - - return TIMER_MAX_VAL - readl(&timer->timer3.value); -} - -/* - * Get the number of ticks (in CONFIG_SYS_HZ resolution) - */ -unsigned long long get_ticks(void) -{ - const unsigned long now = read_timer(); - - if (now >= timer.last_update) - timer.ticks += now - timer.last_update; - else - /* an overflow occurred */ - timer.ticks += TIMER_MAX_VAL - timer.last_update + now; - - timer.last_update = now; - - return clk_to_systicks(timer.ticks); -} - -unsigned long get_timer_masked(void) -{ - return get_ticks(); -} - -unsigned long get_timer(unsigned long base) -{ - return get_timer_masked() - base; -} - -void reset_timer_masked(void) -{ - timer.last_update = read_timer(); - timer.ticks = 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -void __udelay(unsigned long usec) -{ - /* read the timer and update timer.ticks */ - get_ticks(); - - const unsigned long long target = timer.ticks + usecs_to_ticks(usec); - - while (timer.ticks < target) - get_ticks(); -} - -int timer_init(void) -{ - struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; - - /* use timer 3 with 508KHz and free running */ - writel(TIMER_CLKSEL, &timer->timer3.control); - - /* set initial timer value 3 */ - writel(TIMER_MAX_VAL, &timer->timer3.load); - - /* Enable the timer */ - writel(TIMER_ENABLE | TIMER_CLKSEL, - &timer->timer3.control); - - reset_timer_masked(); - - return 0; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -unsigned long get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/cpu/arm920t/ep93xx/u-boot.lds b/cpu/arm920t/ep93xx/u-boot.lds deleted file mode 100644 index 737c9d8c1b..0000000000 --- a/cpu/arm920t/ep93xx/u-boot.lds +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ - . = 0x1000; - LONG(0x53555243) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/cpu/arm920t/u-boot.lds b/cpu/arm920t/u-boot.lds deleted file mode 100644 index d9bfbee73b..0000000000 --- a/cpu/arm920t/u-boot.lds +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * Ming-Len Wu - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm925t/u-boot.lds b/cpu/arm925t/u-boot.lds deleted file mode 100644 index 694780eba2..0000000000 --- a/cpu/arm925t/u-boot.lds +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm925t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c deleted file mode 100644 index b06d7601b9..0000000000 --- a/cpu/arm926ejs/at91/clock.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] - * - * Copyright (C) 2005 David Brownell - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include - -static unsigned long cpu_clk_rate_hz; -static unsigned long main_clk_rate_hz; -static unsigned long mck_rate_hz; -static unsigned long plla_rate_hz; -static unsigned long pllb_rate_hz; -static u32 at91_pllb_usb_init; - -unsigned long get_cpu_clk_rate(void) -{ - return cpu_clk_rate_hz; -} - -unsigned long get_main_clk_rate(void) -{ - return main_clk_rate_hz; -} - -unsigned long get_mck_clk_rate(void) -{ - return mck_rate_hz; -} - -unsigned long get_plla_clk_rate(void) -{ - return plla_rate_hz; -} - -unsigned long get_pllb_clk_rate(void) -{ - return pllb_rate_hz; -} - -u32 get_pllb_init(void) -{ - return at91_pllb_usb_init; -} - -static unsigned long at91_css_to_rate(unsigned long css) -{ - switch (css) { - case AT91_PMC_MCKR_CSS_SLOW: - return AT91_SLOW_CLOCK; - case AT91_PMC_MCKR_CSS_MAIN: - return main_clk_rate_hz; - case AT91_PMC_MCKR_CSS_PLLA: - return plla_rate_hz; - case AT91_PMC_MCKR_CSS_PLLB: - return pllb_rate_hz; - } - - return 0; -} - -#ifdef CONFIG_USB_ATMEL -static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) -{ - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; - - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; - - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - * Warning: some newer products need 2MHz min. - */ - input = main_freq / i; -#if defined(CONFIG_AT91SAM9G20) - if (input < 2000000) - continue; -#endif - if (input < 100000) - continue; - if (input > 32000000) - continue; - - mul1 = out_freq / input; -#if defined(CONFIG_AT91SAM9G20) - if (mul > 63) - continue; -#endif - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; - - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; -fail: - return 0; -} -#endif - -static u32 at91_pll_rate(u32 freq, u32 reg) -{ - unsigned mul, div; - - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; - - return freq; -} - -int at91_clock_init(unsigned long main_clock) -{ - unsigned freq, mckr; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK - unsigned tmp; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = readl(&pmc->mcfr); - } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); - tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (AT91_SLOW_CLOCK / 16); - } -#endif - main_clk_rate_hz = main_clock; - - /* report if PLLA is more than mildly overclocked */ - plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); - -#ifdef CONFIG_USB_ATMEL - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | - AT91_PMC_PLLBR_USBDIV_2; - pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init); -#endif - - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = readl(&pmc->mckr); -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - /* plla divisor by 2 */ - plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); -#endif - mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); - freq = mck_rate_hz; - - freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ -#if defined(CONFIG_AT91RM9200) - /* mdiv */ - mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); -#elif defined(CONFIG_AT91SAM9G20) - /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ - mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? - freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; - if (mckr & AT91_PMC_MCKR_MDIV_MASK) - freq /= 2; /* processor clock division */ -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3 - ? freq / 3 - : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); -#else - mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); -#endif - cpu_clk_rate_hz = freq; - - return 0; -} diff --git a/cpu/arm926ejs/mx25/Makefile b/cpu/arm926ejs/mx25/Makefile deleted file mode 100644 index 55c1e899be..0000000000 --- a/cpu/arm926ejs/mx25/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).a - -COBJS = generic.o timer.o -MX27OBJS = reset.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -SRCS += $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c deleted file mode 100644 index 30cf544712..0000000000 --- a/cpu/arm926ejs/mx27/generic.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright (c) 2008 Eric Jarrige - * Copyright (c) 2009 Ilya Yanok - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#ifdef CONFIG_MXC_MMC -#include -#endif - -/* - * get the system pll clock in Hz - * - * mfi + mfn / (mfd +1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) -{ - unsigned int mfi = (pll >> 10) & 0xf; - unsigned int mfn = pll & 0x3ff; - unsigned int mfd = (pll >> 16) & 0x3ff; - unsigned int pd = (pll >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn), - (mfd + 1) * (pd + 1)); -} - -static ulong clk_in_32k(void) -{ - return 1024 * CONFIG_MX27_CLK32; -} - -static ulong clk_in_26m(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { - /* divide by 1.5 */ - return 26000000 * 2 / 3; - } else { - return 26000000; - } -} - -ulong imx_get_mpllclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref; - - if (cscr & CSCR_MCU_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(readl(&pll->mpctl0), fref); -} - -ulong imx_get_armclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref = imx_get_mpllclk(); - ulong div; - - if (!(cscr & CSCR_ARM_SRC_MPLL)) - fref = lldiv((fref * 2), 3); - - div = ((cscr >> 12) & 0x3) + 1; - - return lldiv(fref, div); -} - -ulong imx_get_ahbclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref = imx_get_mpllclk(); - ulong div; - - div = ((cscr >> 8) & 0x3) + 1; - - return lldiv(fref * 2, 3 * div); -} - -ulong imx_get_spllclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref; - - if (cscr & CSCR_SP_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(readl(&pll->spctl0), fref); -} - -static ulong imx_decode_perclk(ulong div) -{ - return lldiv((imx_get_mpllclk() * 2), (div * 3)); -} - -ulong imx_get_perclk1(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); -} - -ulong imx_get_perclk2(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); -} - -ulong imx_get_perclk3(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); -} - -ulong imx_get_perclk4(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1); -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) -{ - char buf[32]; - - printf("CPU: Freescale i.MX27 at %s MHz\n\n", - strmhz(buf, imx_get_mpllclk())); - return 0; -} -#endif - -int cpu_eth_init(bd_t *bis) -{ -#if defined(CONFIG_FEC_MXC) - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - /* enable FEC clock */ - writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); - writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); - return fecmxc_initialize(bis); -#else - return 0; -#endif -} - -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(bd_t *bis) -{ -#ifdef CONFIG_MXC_MMC - return mxc_mmc_init(bis); -#else - return 0; -#endif -} - -void imx_gpio_mode(int gpio_mode) -{ - struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT; - unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT; - unsigned int tmp; - - /* Pullup enable */ - if (gpio_mode & GPIO_PUEN) { - writel(readl(®s->port[port].puen) | (1 << pin), - ®s->port[port].puen); - } else { - writel(readl(®s->port[port].puen) & ~(1 << pin), - ®s->port[port].puen); - } - - /* Data direction */ - if (gpio_mode & GPIO_OUT) { - writel(readl(®s->port[port].ddir) | 1 << pin, - ®s->port[port].ddir); - } else { - writel(readl(®s->port[port].ddir) & ~(1 << pin), - ®s->port[port].ddir); - } - - /* Primary / alternate function */ - if (gpio_mode & GPIO_AF) { - writel(readl(®s->port[port].gpr) | (1 << pin), - ®s->port[port].gpr); - } else { - writel(readl(®s->port[port].gpr) & ~(1 << pin), - ®s->port[port].gpr); - } - - /* use as gpio? */ - if (!(gpio_mode & (GPIO_PF | GPIO_AF))) { - writel(readl(®s->port[port].gius) | (1 << pin), - ®s->port[port].gius); - } else { - writel(readl(®s->port[port].gius) & ~(1 << pin), - ®s->port[port].gius); - } - - /* Output / input configuration */ - if (pin < 16) { - tmp = readl(®s->port[port].ocr1); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - writel(tmp, ®s->port[port].ocr1); - - writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)), - ®s->port[port].iconfa1); - writel(readl(®s->port[port].iconfa1) | aout << (pin * 2), - ®s->port[port].iconfa1); - writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)), - ®s->port[port].iconfb1); - writel(readl(®s->port[port].iconfb1) | bout << (pin * 2), - ®s->port[port].iconfb1); - } else { - pin -= 16; - - tmp = readl(®s->port[port].ocr2); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - writel(tmp, ®s->port[port].ocr2); - - writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)), - ®s->port[port].iconfa2); - writel(readl(®s->port[port].iconfa2) | aout << (pin * 2), - ®s->port[port].iconfa2); - writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)), - ®s->port[port].iconfb2); - writel(readl(®s->port[port].iconfb2) | bout << (pin * 2), - ®s->port[port].iconfb2); - } -} - -#ifdef CONFIG_MXC_UART -void mx27_uart_init_pins(void) -{ - int i; - unsigned int mode[] = { - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} -#endif /* CONFIG_MXC_UART */ - -#ifdef CONFIG_FEC_MXC -void mx27_fec_init_pins(void) -{ - int i; - unsigned int mode[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_CLR, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); -} -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_MXC_MMC -void mx27_sd2_init_pins(void) -{ - int i; - unsigned int mode[] = { - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} -#endif /* CONFIG_MXC_MMC */ diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c deleted file mode 100644 index 047b9e3513..0000000000 --- a/cpu/arm926ejs/nomadik/timer.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * The timer is a decrementer, we'll left it free running at 2.4MHz. - * We have 2.4 ticks per microsecond and an overflow in almost 30min - */ -#define TIMER_CLOCK (24 * 100 * 1000) -#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */ -#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */ -#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) -#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) - -/* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) - -/* Configure a free-running, auto-wrap counter with no prescaler */ -int timer_init(void) -{ - writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, - CONFIG_SYS_TIMERBASE + MTU_CR(0)); - reset_timer(); - return 0; -} - -/* Restart counting from 0 */ -void reset_timer(void) -{ - writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */ -} - -/* Return how many HZ passed since "base" */ -ulong get_timer(ulong base) -{ - return TICKS_TO_HZ(READ_TIMER()) - base; -} - -/* Delay x useconds */ -void __udelay(unsigned long usec) -{ - ulong ini, end; - - ini = READ_TIMER(); - end = ini + USEC_TO_COUNT(usec); - while ((signed)(end - READ_TIMER()) > 0) - ; -} diff --git a/cpu/arm926ejs/u-boot.lds b/cpu/arm926ejs/u-boot.lds deleted file mode 100644 index ee5eeb590a..0000000000 --- a/cpu/arm926ejs/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm926ejs/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm946es/u-boot.lds b/cpu/arm946es/u-boot.lds deleted file mode 100644 index 5bd4390fb5..0000000000 --- a/cpu/arm946es/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm946es/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/arm_cortexa8/mx51/lowlevel_init.S b/cpu/arm_cortexa8/mx51/lowlevel_init.S deleted file mode 100644 index 31af9e2b58..0000000000 --- a/cpu/arm_cortexa8/mx51/lowlevel_init.S +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * L2CC Cache setup/invalidation/disable - */ -.macro init_l2cc - /* explicitly disable L2 cache */ - mrc 15, 0, r0, c1, c0, 1 - bic r0, r0, #0x2 - mcr 15, 0, r0, c1, c0, 1 - - /* reconfigure L2 cache aux control reg */ - mov r0, #0xC0 /* tag RAM */ - add r0, r0, #0x4 /* data RAM */ - orr r0, r0, #(1 << 24) /* disable write allocate delay */ - orr r0, r0, #(1 << 23) /* disable write allocate combine */ - orr r0, r0, #(1 << 22) /* disable write allocate */ - - cmp r3, #0x10 /* r3 contains the silicon rev */ - - /* disable write combine for TO 2 and lower revs */ - orrls r0, r0, #(1 << 25) - - mcr 15, 1, r0, c9, c0, 2 -.endm /* init_l2cc */ - -/* AIPS setup - Only setup MPROTx registers. - * The PACR default values are good.*/ -.macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =0x77777777 - str r1, [r0, #0x0] - str r1, [r0, #0x4] - ldr r0, =AIPS2_BASE_ADDR - str r1, [r0, #0x0] - str r1, [r0, #0x4] - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ -.endm /* init_aips */ - -/* M4IF setup */ -.macro init_m4if - /* VPU and IPU given higher priority (0x4) - * IPU accesses with ID=0x1 given highest priority (=0xA) - */ - ldr r0, =M4IF_BASE_ADDR - - ldr r1, =0x00000203 - str r1, [r0, #0x40] - - ldr r1, =0x0 - str r1, [r0, #0x44] - - ldr r1, =0x00120125 - str r1, [r0, #0x9C] - - ldr r1, =0x001901A3 - str r1, [r0, #0x48] - -.endm /* init_m4if */ - -.macro setup_pll pll, freq - ldr r2, =\pll - ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ - mov r1, #0x2 - str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ - - str r3, [r2, #PLL_DP_OP] - str r3, [r2, #PLL_DP_HFS_OP] - - str r4, [r2, #PLL_DP_MFD] - str r4, [r2, #PLL_DP_HFS_MFD] - - str r5, [r2, #PLL_DP_MFN] - str r5, [r2, #PLL_DP_HFS_MFN] - - ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] -1: ldr r1, [r2, #PLL_DP_CTL] - ands r1, r1, #0x1 - beq 1b -.endm - -.macro init_clock - ldr r0, =CCM_BASE_ADDR - - /* Gate of clocks to the peripherals first */ - ldr r1, =0x3FFFFFFF - str r1, [r0, #CLKCTL_CCGR0] - ldr r1, =0x0 - str r1, [r0, #CLKCTL_CCGR1] - str r1, [r0, #CLKCTL_CCGR2] - str r1, [r0, #CLKCTL_CCGR3] - - ldr r1, =0x00030000 - str r1, [r0, #CLKCTL_CCGR4] - ldr r1, =0x00FFF030 - str r1, [r0, #CLKCTL_CCGR5] - ldr r1, =0x00000300 - str r1, [r0, #CLKCTL_CCGR6] - - /* Disable IPU and HSC dividers */ - mov r1, #0x60000 - str r1, [r0, #CLKCTL_CCDR] - - /* Make sure to switch the DDR away from PLL 1 */ - ldr r1, =0x19239145 - str r1, [r0, #CLKCTL_CBCDR] - /* make sure divider effective */ -1: ldr r1, [r0, #CLKCTL_CDHIPR] - cmp r1, #0x0 - bne 1b - - /* Switch ARM to step clock */ - mov r1, #0x4 - str r1, [r0, #CLKCTL_CCSR] - mov r3, #DP_OP_800 - mov r4, #DP_MFD_800 - mov r5, #DP_MFN_800 - setup_pll PLL1_BASE_ADDR - - mov r3, #DP_OP_665 - mov r4, #DP_MFD_665 - mov r5, #DP_MFN_665 - setup_pll PLL3_BASE_ADDR - - /* Switch peripheral to PLL 3 */ - ldr r0, =CCM_BASE_ADDR - ldr r1, =0x000010C0 - str r1, [r0, #CLKCTL_CBCMR] - ldr r1, =0x13239145 - str r1, [r0, #CLKCTL_CBCDR] - mov r3, #DP_OP_665 - mov r4, #DP_MFD_665 - mov r5, #DP_MFN_665 - setup_pll PLL2_BASE_ADDR - - /* Switch peripheral to PLL2 */ - ldr r0, =CCM_BASE_ADDR - ldr r1, =0x19239145 - str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 - str r1, [r0, #CLKCTL_CBCMR] - - mov r3, #DP_OP_216 - mov r4, #DP_MFD_216 - mov r5, #DP_MFN_216 - setup_pll PLL3_BASE_ADDR - - - /* Set the platform clock dividers */ - ldr r0, =ARM_BASE_ADDR - ldr r1, =0x00000725 - str r1, [r0, #0x14] - - ldr r0, =CCM_BASE_ADDR - - /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ - ldr r1, =0x0 - ldr r3, [r1, #ROM_SI_REV] - cmp r3, #0x10 - movls r1, #0x1 - movhi r1, #0 - str r1, [r0, #CLKCTL_CACRR] - - /* Switch ARM back to PLL 1 */ - mov r1, #0 - str r1, [r0, #CLKCTL_CCSR] - - /* setup the rest */ - /* Use lp_apm (24MHz) source for perclk */ - ldr r1, =0x000020C2 - str r1, [r0, #CLKCTL_CBCMR] - /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ - ldr r1, =0x59E35100 - str r1, [r0, #CLKCTL_CBCDR] - - /* Restore the default values in the Gate registers */ - ldr r1, =0xFFFFFFFF - str r1, [r0, #CLKCTL_CCGR0] - str r1, [r0, #CLKCTL_CCGR1] - str r1, [r0, #CLKCTL_CCGR2] - str r1, [r0, #CLKCTL_CCGR3] - str r1, [r0, #CLKCTL_CCGR4] - str r1, [r0, #CLKCTL_CCGR5] - str r1, [r0, #CLKCTL_CCGR6] - - /* Use PLL 2 for UART's, get 66.5MHz from it */ - ldr r1, =0xA5A2A020 - str r1, [r0, #CLKCTL_CSCMR1] - ldr r1, =0x00C30321 - str r1, [r0, #CLKCTL_CSCDR1] - - /* make sure divider effective */ -1: ldr r1, [r0, #CLKCTL_CDHIPR] - cmp r1, #0x0 - bne 1b - - mov r1, #0x0 - str r1, [r0, #CLKCTL_CCDR] - - /* for cko - for ARM div by 8 */ - mov r1, #0x000A0000 - add r1, r1, #0x00000F0 - str r1, [r0, #CLKCTL_CCOSR] -.endm - -.macro setup_wdog - ldr r0, =WDOG1_BASE_ADDR - mov r1, #0x30 - strh r1, [r0] -.endm - -.section ".text.init", "x" - -.globl lowlevel_init -lowlevel_init: - ldr r0, =GPIO1_BASE_ADDR - ldr r1, [r0, #0x0] - orr r1, r1, #(1 << 23) - str r1, [r0, #0x0] - ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 23) - str r1, [r0, #0x4] - -#ifdef ENABLE_IMPRECISE_ABORT - mrs r1, spsr /* save old spsr */ - mrs r0, cpsr /* read out the cpsr */ - bic r0, r0, #0x100 /* clear the A bit */ - msr spsr, r0 /* update spsr */ - add lr, pc, #0x8 /* update lr */ - movs pc, lr /* update cpsr */ - nop - nop - nop - nop - msr spsr, r1 /* restore old spsr */ -#endif - - init_l2cc - - init_aips - - init_m4if - - init_clock - - /* r12 saved upper lr*/ - mov pc,lr - -/* Board level setting value */ -DDR_PERCHARGE_CMD: .word 0x04008008 -DDR_REFRESH_CMD: .word 0x00008010 -DDR_LMR1_W: .word 0x00338018 -DDR_LMR_CMD: .word 0xB2220000 -DDR_TIMING_W: .word 0xB02567A9 -DDR_MISC_W: .word 0x000A0104 diff --git a/cpu/arm_cortexa8/mx51/u-boot.lds b/cpu/arm_cortexa8/mx51/u-boot.lds deleted file mode 100644 index 84c173ac71..0000000000 --- a/cpu/arm_cortexa8/mx51/u-boot.lds +++ /dev/null @@ -1,61 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm_cortexa8/start.o - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/cpu/arm_cortexa8/s5pc1xx/cache.S b/cpu/arm_cortexa8/s5pc1xx/cache.S deleted file mode 100644 index 23f527a485..0000000000 --- a/cpu/arm_cortexa8/s5pc1xx/cache.S +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Minkyu Kang - * - * based on cpu/arm_cortexa8/omap3/cache.S - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -.align 5 -.global invalidate_dcache -.global l2_cache_enable -.global l2_cache_disable - -/* - * invalidate_dcache() - * Invalidate the whole D-cache. - * - * Corrupted registers: r0-r5, r7, r9-r11 - */ -invalidate_dcache: - stmfd r13!, {r0 - r5, r7, r9 - r12, r14} - - cmp r0, #0xC100 @ check if the cpu is s5pc100 - - beq finished_inval @ s5pc100 doesn't need this - @ routine - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished_inval @ if loc is 0, then no need to - @ clean - mov r10, #0 @ start clean at cache level 0 -inval_loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache - @ level - mov r1, r0, lsr r2 @ extract cache type bits from - @ clidr - and r1, r1, #7 @ mask of the bits for current - @ cache only - cmp r1, #2 @ see what cache we have at - @ this level - blt skip_inval @ skip if no cache, or just - @ i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mov r2, #0 @ operand for mcr SBZ - mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to - @ sych the new cssr&csidr, - @ with armv7 this is 'isb', - @ but we compile with armv5 - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the - @ cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the - @ way size - clz r5, r4 @ find bit position of way - @ size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the - @ index size -inval_loop2: - mov r9, r4 @ create working copy of max - @ way size -inval_loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number - @ into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge inval_loop3 - subs r7, r7, #1 @ decrement the index - bge inval_loop2 -skip_inval: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt inval_loop1 -finished_inval: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, - @ with armv7 this is 'isb', - @ but we compile with armv5 - - ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} - -l2_cache_enable: - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} - -l2_cache_disable: - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} diff --git a/cpu/arm_cortexa8/u-boot.lds b/cpu/arm_cortexa8/u-boot.lds deleted file mode 100644 index 4f1711cca0..0000000000 --- a/cpu/arm_cortexa8/u-boot.lds +++ /dev/null @@ -1,58 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm_cortexa8/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/cpu/arm_intcm/u-boot.lds b/cpu/arm_intcm/u-boot.lds deleted file mode 100644 index 5eb87fbee7..0000000000 --- a/cpu/arm_intcm/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm_intcm/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/ixp/npe/Makefile b/cpu/ixp/npe/Makefile deleted file mode 100644 index 8fefd29eb5..0000000000 --- a/cpu/ixp/npe/Makefile +++ /dev/null @@ -1,98 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB := $(obj)libnpe.a - -LOCAL_CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux -CFLAGS += $(LOCAL_CFLAGS) -HOSTCFLAGS += $(LOCAL_CFLAGS) - -COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \ - miiphy.o \ - IxOsalBufferMgt.o \ - IxOsalIoMem.o \ - IxOsalOsCacheMMU.o \ - IxOsalOsMsgQ.o \ - IxOsalOsSemaphore.o \ - IxOsalOsServices.o \ - IxOsalOsThread.o \ - IxEthAcc.o \ - IxEthAccCommon.o \ - IxEthAccControlInterface.o \ - IxEthAccDataPlane.o \ - IxEthAccMac.o \ - IxEthAccMii.o \ - IxEthDBAPI.o \ - IxEthDBAPISupport.o \ - IxEthDBCore.o \ - IxEthDBEvents.o \ - IxEthDBFeatures.o \ - IxEthDBFirewall.o \ - IxEthDBHashtable.o \ - IxEthDBLearning.o \ - IxEthDBMem.o \ - IxEthDBNPEAdaptor.o \ - IxEthDBPortUpdate.o \ - IxEthDBReports.o \ - IxEthDBSearch.o \ - IxEthDBSpanningTree.o \ - IxEthDBUtil.o \ - IxEthDBVlan.o \ - IxEthDBWiFi.o \ - IxEthMii.o \ - IxQMgrAqmIf.o \ - IxQMgrDispatcher.o \ - IxQMgrInit.o \ - IxQMgrQAccess.o \ - IxQMgrQCfg.o \ - IxFeatureCtrl.o \ - IxNpeDl.o \ - IxNpeDlImageMgr.o \ - IxNpeDlNpeMgr.o \ - IxNpeDlNpeMgrUtils.o \ - IxNpeMh.o \ - IxNpeMhConfig.o \ - IxNpeMhReceive.o \ - IxNpeMhSend.o \ - IxNpeMhSolicitedCbMgr.o \ - IxNpeMhUnsolicitedCbMgr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/ixp/u-boot.lds b/cpu/ixp/u-boot.lds deleted file mode 100644 index 85209caf74..0000000000 --- a/cpu/ixp/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/ixp/start.o(.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/lh7a40x/u-boot.lds b/cpu/lh7a40x/u-boot.lds deleted file mode 100644 index e7543c97ce..0000000000 --- a/cpu/lh7a40x/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/lh7a40x/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c deleted file mode 100644 index e160ee1aff..0000000000 --- a/cpu/mcf5227x/cpu_init.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include -#include - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; - -#if !defined(CONFIG_CF_SBF) - /* Workaround, must place before fbcs */ - pll->psr = 0x12; - - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; - scm1->pacri = 0; - -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; -#endif -#endif /* CONFIG_CF_SBF */ - -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; -#endif - -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; -#endif - -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; -#endif - -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ - && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; -#endif - -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ - && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; -#endif - -#ifdef CONFIG_FSL_I2C - gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA; -#endif - - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ -#ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; - - rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; -#endif - - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->par_uart &= - (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK); - gpio->par_uart |= - (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); - break; - case 1: - gpio->par_uart &= - (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK); - gpio->par_uart |= - (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); - break; - case 2: - gpio->par_dspi &= - (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK); - gpio->par_dspi = - (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); - break; - } -} - -#ifdef CONFIG_CF_DSPI -void cfspi_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - gpio->par_dspi = - GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK; -} - -int cfspi_claim_bus(uint bus, uint cs) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) - return -1; - - /* Clear FIFO and resume transfer */ - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); - - switch (cs) { - case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; - break; - case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; - gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; - break; - } - - return 0; -} - -void cfspi_release_bus(uint bus, uint cs) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ - - switch (cs) { - case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; - break; - case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; - break; - } -} -#endif diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S deleted file mode 100644 index 0c9c89c402..0000000000 --- a/cpu/mcf5227x/start.S +++ /dev/null @@ -1,597 +0,0 @@ -/* - * Copyright (C) 2003 Josef Baumgartner - * Based on code from Bernhard Kuhn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "version.h" - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* last three long word reserved for cache status */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) - -#define _START _start -#define _FAULT _fault - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte; - -#if defined(CONFIG_CF_SBF) -#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) -#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) -#endif - -.text -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: - -#if defined(CONFIG_CF_SBF) -INITSP: .long 0 /* Initial SP */ -INITPC: .long ASM_DRAMINIT /* Initial PC */ -#else -INITSP: .long 0 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -#endif - -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ - -/* Reserved */ -vector10_17: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ - -#if !defined(CONFIG_CF_SBF) -/* TRAP #0 - #15 */ -vector20_2F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector30_3F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector64_127: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector128_191: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector192_255: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -#endif - -#if defined(CONFIG_CF_SBF) - /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ -asm_sbf_img_hdr: - .long 0x00000000 /* checksum, not yet implemented */ - .long 0x00020000 /* image length */ - .long TEXT_BASE /* image to be relocated at */ - -asm_dram_init: - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 /* init Rambar */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- - - /* Must disable global address */ - move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) - move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) - move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) - - /* - * Dram Initialization - * a1, a2, and d0 - */ - /* mscr sdram */ - move.l #0xFC0A4074, %a1 - move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) - nop - - /* SDRAM Chip 0 and 1 */ - move.l #0xFC0B8110, %a1 - move.l #0xFC0B8114, %a2 - - /* calculate the size */ - move.l #0x13, %d1 - move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 -#ifdef CONFIG_SYS_SDRAM_BASE1 - lsr.l #1, %d2 -#endif - -dramsz_loop: - lsr.l #1, %d2 - add.l #1, %d1 - cmp.l #1, %d2 - bne dramsz_loop - - /* SDRAM Chip 0 and 1 */ - move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) - or.l %d1, (%a1) -#ifdef CONFIG_SYS_SDRAM_BASE1 - move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) - or.l %d1, (%a2) -#endif - nop - - /* dram cfg1 and cfg2 */ - move.l #0xFC0B8008, %a1 - move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) - nop - move.l #0xFC0B800C, %a2 - move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) - nop - - move.l #0xFC0B8000, %a1 /* Mode */ - move.l #0xFC0B8004, %a2 /* Ctrl */ - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - /* Issue LEMR */ - move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) - nop - move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) - nop - - move.l #1000, %d0 -wait1000: - nop - subq.l #1, %d0 - bne wait1000 - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - /* Perform two refresh cycles */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 - nop - move.l %d0, (%a2) - move.l %d0, (%a2) - nop - - move.l #(CONFIG_SYS_SDRAM_CTRL), %d0 - and.l #0x7FFFFFFF, %d0 - or.l #0x10000c00, %d0 - move.l %d0, (%a2) - nop - - /* - * DSPI Initialization - * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h - * a1 - dspi status - * a2 - dtfr - * a3 - drfr - * a4 - Dst addr - */ - - /* Enable pins for DSPI mode - chip-selects are enabled later */ - move.l #0xFC0A4036, %a0 - move.b #0x3F, %d0 - move.b %d0, (%a0) - - /* DSPI CS */ -#ifdef CONFIG_SYS_DSPI_CS0 - move.b (%a0), %d0 - or.l #0xC0, %d0 - move.b %d0, (%a0) -#endif -#ifdef CONFIG_SYS_DSPI_CS2 - move.l #0xFC0A4037, %a0 - move.b (%a0), %d0 - or.l #0x10, %d0 - move.b %d0, (%a0) -#endif - nop - - /* Configure DSPI module */ - move.l #0xFC05C000, %a0 - move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ - - move.l #0xFC05C00C, %a0 - move.l #0x3E000011, (%a0) - - move.l #0xFC05C034, %a2 /* dtfr */ - move.l #0xFC05C03B, %a3 /* drfr */ - - move.l #(ASM_SBF_IMG_HDR + 4), %a1 - move.l (%a1)+, %d5 - move.l (%a1), %a4 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 - move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 - - move.l #0xFC05C02C, %a1 /* dspi status */ - - /* Issue commands and address */ - move.l #0x8004000B, %d2 /* Fast Read Cmd */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80040000, %d2 /* Address byte 2 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80040000, %d2 /* Address byte 1 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80040000, %d2 /* Address byte 0 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80040000, %d2 /* Dummy Wr and Rd */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - /* Transfer serial boot header to sram */ -asm_dspi_rd_loop1: - move.l #0x80040000, %d2 - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.b %d1, (%a0) /* read, copy to dst */ - - add.l #1, %a0 /* inc dst by 1 */ - sub.l #1, %d4 /* dec cnt by 1 */ - bne asm_dspi_rd_loop1 - - /* Transfer u-boot from serial flash to memory */ -asm_dspi_rd_loop2: - move.l #0x80040000, %d2 - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.b %d1, (%a4) /* read, copy to dst */ - - add.l #1, %a4 /* inc dst by 1 */ - sub.l #1, %d5 /* dec cnt by 1 */ - bne asm_dspi_rd_loop2 - - move.l #0x00040000, %d2 /* Terminate */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - /* jump to memory and execute */ - move.l #(TEXT_BASE + 0x400), %a0 - move.l %a0, (%a1) - jmp (%a0) - -asm_dspi_wr_status: - move.l (%a1), %d0 /* status */ - and.l #0x0000F000, %d0 - cmp.l #0x00003000, %d0 - bgt asm_dspi_wr_status - - move.l %d2, (%a2) - rts - -asm_dspi_rd_status: - move.l (%a1), %d0 /* status */ - and.l #0x000000F0, %d0 - lsr.l #4, %d0 - cmp.l #0, %d0 - beq asm_dspi_rd_status - - move.b (%a3), %d1 - rts -#endif /* CONFIG_CF_SBF */ - - .text - . = 0x400 - .globl _start -_start: - nop - nop - move.w #0x2700,%sr /* Mask off Interrupt */ - - /* Set vector base register at the beginning of the Flash */ -#if defined(CONFIG_CF_SBF) - move.l #TEXT_BASE, %d0 - movec %d0, %VBR -#else - move.l #CONFIG_SYS_FLASH_BASE, %d0 - movec %d0, %VBR - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 -#endif - - /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l #(CACR_STATUS), %a3 /* CACR */ - move.l %d0, (%a1) - move.l %d0, (%a2) - move.l %d0, (%a3) - - /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - /* set stackpointer to end of internal ram to get some stackspace for - the first c-code */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- - - move.l #__got_start, %a5 /* put relocation table address to a5 */ - - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ - - /* board_init_f() does not return */ - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ - jsr (%a1) - -/*------------------------------------------------------------------------------*/ -/* exception code */ - .globl _fault -_fault: - jmp _fault - .globl _exc_handler - -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - - .globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01200000, %d0 /* Invalid cache */ - movec %d0, %CACR - - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 - movec %d0, %ACR0 - - move.l #0x81600610, %d0 /* Enable cache */ - movec %d0, %CACR - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x01F00000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - clr.l %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x80600610, %d0 /* Invalidate icache */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #0x01200000, %d0 /* Invalid cache */ - movec %d0, %CACR - - move.l #0x81300610, %d0 - movec %d0, %CACR - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #0x81600610, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_invalid -dcache_invalid: - move.l #0x81100610, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ - - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - .align 4 diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c deleted file mode 100644 index 3c04fd4134..0000000000 --- a/cpu/mcf523x/cpu_init.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_NET) -#include -#include -#include -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; - volatile scm_t *scm = (scm_t *) MMAP_SCM; - - /* watchdog is enabled by default - disable the watchdog */ -#ifndef CONFIG_WATCHDOG - wdog->cr = 0; -#endif - - scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); - - /* Port configuration */ - gpio->par_cs = 0; - -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; -#endif - -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; -#endif - -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS2; - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; -#endif - -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS3; - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; -#endif - -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; -#endif - -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; -#endif - -#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS6; - fbcs->csar6 = CONFIG_SYS_CS6_BASE; - fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; - fbcs->csmr6 = CONFIG_SYS_CS6_MASK; -#endif - -#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS7; - fbcs->csar7 = CONFIG_SYS_CS7_BASE; - fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; - fbcs->csmr7 = CONFIG_SYS_CS7_MASK; -#endif - -#ifdef CONFIG_FSL_I2C - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; -#endif - - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); - break; - case 1: - gpio->par_uart = - (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); - break; - case 2: - gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO); - } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); - } - - return 0; -} -#endif diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S deleted file mode 100644 index d44da37ec7..0000000000 --- a/cpu/mcf523x/start.S +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright (C) 2003 Josef Baumgartner - * Based on code from Bernhard Kuhn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "version.h" - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -#define _START _start -#define _FAULT _fault - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte; - -.text -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: - -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ - -/* Reserved */ -vector10_17: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ - -/* TRAP #0 - #15 */ -vector20_2F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector30_3F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector64_127: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector128_191: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector192_255: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - - .text - - .globl _start -_start: - nop - nop - move.w #0x2700,%sr /* Mask off Interrupt */ - - /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 - movec %d0, %VBR - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 - - /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - nop - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 - move.l %d0, (%a1) - move.l %d0, (%a2) - - /* set stackpointer to end of internal ram to get some stackspace for the - first c-code */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- - - move.l #__got_start, %a5 /* put relocation table address to a5 */ - - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ - - /* board_init_f() does not return */ - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ - jsr (%a1) - -/*------------------------------------------------------------------------------*/ -/* exception code */ - .globl _fault -_fault: - jmp _fault - .globl _exc_handler - -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - - .globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - nop - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #(CONFIG_SYS_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - - move.l #0x80400100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x80600100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - rts - - .globl dcache_enable -dcache_enable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - /* No dcache, just a dummy function */ - .globl dcache_disable -dcache_disable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ - - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - .align 4 diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c deleted file mode 100644 index 7cea6558fd..0000000000 --- a/cpu/mcf52x2/cpu_init.c +++ /dev/null @@ -1,731 +0,0 @@ -/* - * (C) Copyright 2003 - * Josef Baumgartner - * - * MCF5282 additionals - * (C) Copyright 2005 - * BuS Elektronik GmbH & Co. KG - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * Hayden Fraser (Hayden.Fraser@freescale.com) - * - * MCF5275 additions - * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_NET) -#include -#include -#include -#endif - -#ifndef CONFIG_M5272 -/* Only 5272 Flexbus chipselect is different from the rest */ -void init_fbcs(void) -{ - volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); - -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; -#else -#warning "Chip Select 0 are not initialized/used" -#endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; -#endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; -#endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; -#endif -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ - && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; -#endif -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ - && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; -#endif -#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ - && defined(CONFIG_SYS_CS6_CTRL)) - fbcs->csar6 = CONFIG_SYS_CS6_BASE; - fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; - fbcs->csmr6 = CONFIG_SYS_CS6_MASK; -#endif -#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ - && defined(CONFIG_SYS_CS7_CTRL)) - fbcs->csar7 = CONFIG_SYS_CS7_BASE; - fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; - fbcs->csmr7 = CONFIG_SYS_CS7_MASK; -#endif -} -#endif - -#if defined(CONFIG_M5208) -void cpu_init_f(void) -{ - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - -#ifndef CONFIG_WATCHDOG - volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG; - - /* Disable the watchdog if we aren't using it */ - wdg->cr = 0; -#endif - - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - - /* FlexBus Chipselect */ - init_fbcs(); - - icache_enable(); -} - -/* initialize higher level parts of CPU like timers */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->par_uart &= GPIO_PAR_UART0_MASK; - gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); - break; - case 1: - gpio->par_uart &= GPIO_PAR_UART0_MASK; - gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); - break; - case 2: -#ifdef CONFIG_SYS_UART2_PRI_GPIO - gpio->par_timer &= - (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK); - gpio->par_timer |= - (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); -#endif -#ifdef CONFIG_SYS_UART2_ALT1_GPIO - gpio->par_feci2c &= - (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); -#endif -#ifdef CONFIG_SYS_UART2_ALT1_GPIO - gpio->par_feci2c &= - (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); -#endif - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->par_fec |= - GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO; - } else { - gpio->par_fec &= - (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK; - } - return 0; -} -#endif /* CONFIG_CMD_NET */ -#endif /* CONFIG_M5208 */ - -#if defined(CONFIG_M5253) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ - mbar_writeByte(MCFSIM_SYPCR, 0x00); - mbar_writeByte(MCFSIM_SWIVR, 0x0f); - mbar_writeByte(MCFSIM_SWSR, 0x00); - mbar_writeByte(MCFSIM_SWDICR, 0x00); - mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); - mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); - mbar_writeByte(MCFSIM_I2CICR, 0x00); - mbar_writeByte(MCFSIM_UART1ICR, 0x00); - mbar_writeByte(MCFSIM_UART2ICR, 0x00); - mbar_writeByte(MCFSIM_ICR6, 0x00); - mbar_writeByte(MCFSIM_ICR7, 0x00); - mbar_writeByte(MCFSIM_ICR8, 0x00); - mbar_writeByte(MCFSIM_ICR9, 0x00); - mbar_writeByte(MCFSIM_QSPIICR, 0x00); - - mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); - mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ - mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - - /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ - - /* FlexBus Chipselect */ - init_fbcs(); - -#ifdef CONFIG_FSL_I2C - CONFIG_SYS_I2C_PINMUX_REG = - CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; -#ifdef CONFIG_SYS_I2C2_OFFSET - CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; - CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; -#endif -#endif - - /* enable instruction cache now */ - icache_enable(); -} - -/*initialize higher level parts of CPU like timers */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - break; - case 1: - break; - case 2: - break; - } -} -#endif /* #if defined(CONFIG_M5253) */ - -#if defined(CONFIG_M5271) -void cpu_init_f(void) -{ -#ifndef CONFIG_WATCHDOG - /* Disable the watchdog if we aren't using it */ - mbar_writeShort(MCF_WTM_WCR, 0); -#endif - - /* FlexBus Chipselect */ - init_fbcs(); - -#ifdef CONFIG_SYS_MCF_SYNCR - /* Set clockspeed according to board header file */ - mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); -#else - /* Set clockspeed to 100MHz */ - mbar_writeLong(MCF_FMPLL_SYNCR, - MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); -#endif - while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | - MCF_GPIO_PAR_UART_U0RXD); - break; - case 1: - mbar_writeShort(MCF_GPIO_PAR_UART, - MCF_GPIO_PAR_UART_U1RXD_UART1 | - MCF_GPIO_PAR_UART_U1TXD_UART1); - break; - case 2: - mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000); - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - if (setclear) { - /* Enable Ethernet pins */ - mbar_writeByte(MCF_GPIO_PAR_FECI2C, - (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0)); - } else { - } - - return 0; -} -#endif /* CONFIG_CMD_NET */ -#endif - -#if defined(CONFIG_M5272) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - /* if we come from RAM we assume the CPU is - * already initialized. - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM - volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); - volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); - volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - - sysctrl->sc_scr = CONFIG_SYS_SCR; - sysctrl->sc_spr = CONFIG_SYS_SPR; - - /* Setup Ports: */ - gpio->gpio_pacnt = CONFIG_SYS_PACNT; - gpio->gpio_paddr = CONFIG_SYS_PADDR; - gpio->gpio_padat = CONFIG_SYS_PADAT; - gpio->gpio_pbcnt = CONFIG_SYS_PBCNT; - gpio->gpio_pbddr = CONFIG_SYS_PBDDR; - gpio->gpio_pbdat = CONFIG_SYS_PBDAT; - gpio->gpio_pdcnt = CONFIG_SYS_PDCNT; - - /* Memory Controller: */ - csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM; - csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM; - -#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) - csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM; - csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM; - csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) - csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM; - csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) - csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM; - csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) - csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM; - csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) - csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM; - csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) - csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM; - csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM; -#endif - -#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ - - /* enable instruction cache now */ - icache_enable(); - -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); - gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); - break; - case 1: - gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); - gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | - GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | - GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | - GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; - } else { - } - return 0; -} -#endif /* CONFIG_CMD_NET */ -#endif /* #if defined(CONFIG_M5272) */ - -#if defined(CONFIG_M5275) - -/* - * Breathe some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - /* - * if we come from RAM we assume the CPU is - * already initialized. - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM - volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); - volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); - - /* Kill watchdog so we can initialize the PLL */ - wdog_reg->wcr = 0; - - /* FlexBus Chipselect */ - init_fbcs(); -#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ - -#ifdef CONFIG_FSL_I2C - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; -#endif - - /* enable instruction cache now */ - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->par_uart |= UART0_ENABLE_MASK; - break; - case 1: - gpio->par_uart |= UART1_ENABLE_MASK; - break; - case 2: - gpio->par_uart |= UART2_ENABLE_MASK; - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - struct fec_info_s *info = (struct fec_info_s *) dev->priv; - volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; - - if (setclear) { - /* Enable Ethernet pins */ - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_feci2c |= 0x0F00; - gpio->par_fec0hl |= 0xC0; - } else { - gpio->par_feci2c |= 0x00A0; - gpio->par_fec1hl |= 0xC0; - } - } else { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_feci2c &= ~0x0F00; - gpio->par_fec0hl &= ~0xC0; - } else { - gpio->par_feci2c &= ~0x00A0; - gpio->par_fec1hl &= ~0xC0; - } - } - - return 0; -} -#endif /* CONFIG_CMD_NET */ -#endif /* #if defined(CONFIG_M5275) */ - -#if defined(CONFIG_M5282) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ -#ifndef CONFIG_WATCHDOG - /* disable watchdog if we aren't using it */ - MCFWTM_WCR = 0; -#endif - -#ifndef CONFIG_MONITOR_IS_IN_RAM - /* Set speed /PLL */ - MCFCLOCK_SYNCR = - MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | - MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); - while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; - - MCFGPIO_PBCDPAR = 0xc0; - - /* Set up the GPIO ports */ -#ifdef CONFIG_SYS_PEPAR - MCFGPIO_PEPAR = CONFIG_SYS_PEPAR; -#endif -#ifdef CONFIG_SYS_PFPAR - MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; -#endif -#ifdef CONFIG_SYS_PJPAR - MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; -#endif -#ifdef CONFIG_SYS_PSDPAR - MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; -#endif -#ifdef CONFIG_SYS_PASPAR - MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; -#endif -#ifdef CONFIG_SYS_PEHLPAR - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; -#endif -#ifdef CONFIG_SYS_PQSPAR - MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; -#endif -#ifdef CONFIG_SYS_PTCPAR - MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; -#endif -#ifdef CONFIG_SYS_PTDPAR - MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; -#endif -#ifdef CONFIG_SYS_PUAPAR - MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; -#endif - -#ifdef CONFIG_SYS_DDRUA - MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; -#endif - - /* FlexBus Chipselect */ - init_fbcs(); - -#endif /* CONFIG_MONITOR_IS_IN_RAM */ - - /* defer enabling cache until boot (see do_go) */ - /* icache_enable(); */ -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - MCFGPIO_PUAPAR &= 0xFc; - MCFGPIO_PUAPAR |= 0x03; - break; - case 1: - MCFGPIO_PUAPAR &= 0xF3; - MCFGPIO_PUAPAR |= 0x0C; - break; - case 2: - MCFGPIO_PASPAR &= 0xFF0F; - MCFGPIO_PASPAR |= 0x00A0; - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - if (setclear) { - MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; - } else { - MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; - } - return 0; -} -#endif /* CONFIG_CMD_NET */ -#endif - -#if defined(CONFIG_M5249) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - /* - * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins - * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins - * which is their primary function. - * ~Jeremy - */ - mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); - mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); - mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); - mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); - mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); - mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); - - /* - * dBug Compliance: - * You can verify these values by using dBug's 'ird' - * (Internal Register Display) command - * ~Jeremy - * - */ - mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ - mbar_writeByte(MCFSIM_SYPCR, 0x00); - mbar_writeByte(MCFSIM_SWIVR, 0x0f); - mbar_writeByte(MCFSIM_SWSR, 0x00); - mbar_writeLong(MCFSIM_IMR, 0xfffffbff); - mbar_writeByte(MCFSIM_SWDICR, 0x00); - mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); - mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); - mbar_writeByte(MCFSIM_I2CICR, 0x00); - mbar_writeByte(MCFSIM_UART1ICR, 0x00); - mbar_writeByte(MCFSIM_UART2ICR, 0x00); - mbar_writeByte(MCFSIM_ICR6, 0x00); - mbar_writeByte(MCFSIM_ICR7, 0x00); - mbar_writeByte(MCFSIM_ICR8, 0x00); - mbar_writeByte(MCFSIM_ICR9, 0x00); - mbar_writeByte(MCFSIM_QSPIICR, 0x00); - - mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); - mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ - mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ - - /* Setup interrupt priorities for gpio7 */ - /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ - - /* IDE Config registers */ - mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); - mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); - - /* FlexBus Chipselect */ - init_fbcs(); - - /* enable instruction cache now */ - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - break; - case 1: - break; - } -} -#endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S deleted file mode 100644 index 0dd4de5160..0000000000 --- a/cpu/mcf52x2/start.S +++ /dev/null @@ -1,495 +0,0 @@ -/* - * Copyright (C) 2003 Josef Baumgartner - * Based on code from Bernhard Kuhn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "version.h" - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - - -#define _START _start -#define _FAULT _fault - - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; \ - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte - -/* If we come from a pre-loader we don't need an initial exception - * table. - */ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - -.text -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: - -.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ -#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) -.long _start - TEXT_BASE -#else -.long _START -#endif - -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -#endif - - .text - - -#if defined(CONFIG_SYS_INT_FLASH_BASE) && \ - (defined(CONFIG_M5282) || defined(CONFIG_M5281)) - #if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ - .long 0xFFFFFFFF /* all sectors protected */ - .long 0x00000000 /* supervisor/User restriction */ - .long 0x00000000 /* programm/data space restriction */ - .long 0x00000000 /* Flash security */ - #endif -#endif - .globl _start -_start: - nop - nop - move.w #0x2700,%sr - -#if defined(CONFIG_M5208) - /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 -#endif - -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) - move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */ - move.c %d0, %MBAR - - /*** The 5249 has MBAR2 as well ***/ -#ifdef CONFIG_SYS_MBAR2 - move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */ - movec %d0, #0xc0e /* Set MBAR2 */ -#endif - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 - movec %d0, %RAMBAR0 -#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ - -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) - /* Initialize IPSBAR */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ - move.l %d0, 0x40000000 - - /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 - movec %d0, %RAMBAR1 - -#if defined(CONFIG_M5282) -#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */ - - move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 - move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 -_copy_flash: - move.l (%a0)+, (%a2)+ - cmp.l %a0, %a1 - bgt.s _copy_flash - jmp CONFIG_SYS_INIT_RAM_ADDR - -_flashbar_setup: - /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 - movec %d0, %FLASHBAR - jmp _after_flashbar_copy.L /* Force jump to absolute address */ -_flashbar_setup_end: - nop -_after_flashbar_copy: -#else - /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 - movec %d0, %FLASHBAR -#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */ - -#endif -#endif - /* if we come from a pre-loader we have no exception table and - * therefore no VBR to set - */ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) -#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - move.l #CONFIG_SYS_INT_FLASH_BASE, %d0 -#else - move.l #CONFIG_SYS_FLASH_BASE, %d0 -#endif - movec %d0, %VBR -#endif - -#ifdef CONFIG_M5275 - /* Initialize IPSBAR */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ - move.l %d0, 0x40000000 -/* movec %d0, %MBAR */ - - /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 - movec %d0, %RAMBAR1 -#endif - - /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- - - move.l #__got_start, %a5 /* put relocation table address to a5 */ - - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ - - /* board_init_f() does not return */ - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - -#if defined(CONFIG_M5281) || defined(CONFIG_M5282) - /* patch the 3 accesspoints to 3 ichache_state */ - /* quick and dirty */ - - move.l %a0,%d1 - add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1 - move.l %a0,%a1 - add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) - move.l %a0,%a1 - add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) - move.l %a0,%a1 - add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) -#endif - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ -#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \ - defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) - halt -#endif - jsr (%a1) - -/*------------------------------------------------------------------------------*/ -/* exception code */ - .globl _fault -_fault: - jmp _fault - - .globl _exc_handler -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - - .globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/*------------------------------------------------------------------------------*/ -/* cache functions */ -#ifdef CONFIG_M5208 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts -#endif - -#ifdef CONFIG_M5271 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts -#endif - -#ifdef CONFIG_M5272 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0xff00c000, %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - -#if defined(CONFIG_M5275) -/* - * Instruction cache only - */ - .globl icache_enable -icache_enable: - move.l #0x01400000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup SDRAM caching */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0x00000000, %d0 /* No other caching */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80400100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - -#ifdef CONFIG_M5282 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0xff00c000, %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 -icache_state_access_1: - move.l %d0, icache_state - rts -#endif - -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) - .globl icache_enable -icache_enable: - /* - * Note: The 5249 Documentation doesn't give a bit position for CINV! - * From the 5272 and the 5307 documentation, I have deduced that it is - * probably CACR[24]. Should someone say something to Motorola? - * ~Jeremy - */ - move.l #0x01000000, %d0 /* Invalidate whole cache */ - move.c %d0,%CACR - move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */ - move.c %d0, %ACR0 - move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */ - move.c %d0, %ACR1 - move.l #0x90000200, %d0 /* Set cache enable cmd */ - move.c %d0,%CACR - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - - .globl icache_disable -icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - movec %d0, %ACR1 /* Enable cache */ - moveq #0, %d0 -icache_state_access_2: - move.l %d0, icache_state - rts - - .globl icache_status -icache_status: -icache_state_access_3: - move.l #(icache_state), %a0 - move.l (%a0), %d0 - rts - - .data -icache_state: - .long 0 /* cache is diabled on inirialization */ - - .globl dcache_enable -dcache_enable: - /* dummy function */ - rts - - .globl dcache_disable -dcache_disable: - /* dummy function */ - rts - - .globl dcache_status -dcache_status: - /* dummy function */ - rts - -/*------------------------------------------------------------------------------*/ - - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - .align 4 diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk deleted file mode 100644 index 0cb90ac4e2..0000000000 --- a/cpu/mcf532x/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) -PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC -else -PLATFORM_CPPFLAGS += -m5307 -fPIC -endif diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c deleted file mode 100644 index 4f1695cef8..0000000000 --- a/cpu/mcf532x/cpu_init.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_NET) -#include -#include -#include -#endif - -#ifdef CONFIG_MCF5301x -void cpu_init_f(void) -{ - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - - /* watchdog is enabled by default - disable the watchdog */ -#ifndef CONFIG_WATCHDOG - /*wdog->cr = 0; */ -#endif - - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; - -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - gpio->par_cs |= GPIO_PAR_CS0_CS0; - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; -#endif - -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - gpio->par_cs |= GPIO_PAR_CS1_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; -#endif - -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; -#endif - -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; -#endif - -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ - && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; -#endif - -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ - && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; -#endif - -#ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL; -#endif - - icache_enable(); -} - -/* initialize higher level parts of CPU like timers */ -int cpu_init_r(void) -{ -#ifdef CONFIG_MCFFEC - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; -#endif -#ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended; - - rtcex->gocu = CONFIG_SYS_RTC_CNT; - rtcex->gocl = CONFIG_SYS_RTC_SETUP; - -#endif -#ifdef CONFIG_MCFFEC - if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) - ccm->misccr |= CCM_MISCCR_FECM; - else - ccm->misccr &= ~CCM_MISCCR_FECM; -#endif - - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); - break; - case 1: -#ifdef CONFIG_SYS_UART1_ALT1_GPIO - gpio->par_simp1h &= - ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK); - gpio->par_simp1h |= - (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); -#elif defined(CONFIG_SYS_UART1_ALT2_GPIO) - gpio->par_ssih &= - ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK); - gpio->par_ssih |= - (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); -#endif - break; - case 2: -#ifdef CONFIG_SYS_UART2_PRI_GPIO - gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); -#elif defined(CONFIG_SYS_UART2_ALT1_GPIO) - gpio->par_dspih &= - ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK); - gpio->par_dspih |= - (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); -#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); -#endif - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_s *info = (struct fec_info_s *)dev->priv; - - if (setclear) { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_fec |= - GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0; - } else { - gpio->par_fec |= - GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1; - } - } else { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_fec &= - ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK; - } else { - gpio->par_fec &= - ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK; - } - } - return 0; -} -#endif /* CONFIG_CMD_NET */ -#endif /* CONFIG_MCF5301x */ - -#ifdef CONFIG_MCF532x -void cpu_init_f(void) -{ - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; - - /* watchdog is enabled by default - disable the watchdog */ -#ifndef CONFIG_WATCHDOG - wdog->cr = 0; -#endif - - scm1->mpr0 = 0x77777777; - scm2->pacra = 0; - scm2->pacrb = 0; - scm2->pacrc = 0; - scm2->pacrd = 0; - scm2->pacre = 0; - scm2->pacrf = 0; - scm2->pacrg = 0; - scm1->pacrh = 0; - - /* Port configuration */ - gpio->par_cs = 0; - -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; -#endif - -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - /* Latch chipselect */ - gpio->par_cs |= GPIO_PAR_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; -#endif - -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - gpio->par_cs |= GPIO_PAR_CS2; - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; -#endif - -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - gpio->par_cs |= GPIO_PAR_CS3; - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; -#endif - -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ - && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; -#endif - -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ - && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; -#endif - -#ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; -#endif - - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); - break; - case 1: - gpio->par_uart = - (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); - break; - case 2: - gpio->par_timer &= 0x0F; - gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; - } else { - gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); - } - return 0; -} -#endif -#endif /* CONFIG_MCF532x */ diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c deleted file mode 100644 index 67f08c7602..0000000000 --- a/cpu/mcf532x/speed.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* PLL min/max specifications */ -#define MAX_FVCO 500000 /* KHz */ -#define MAX_FSYS 80000 /* KHz */ -#define MIN_FSYS 58333 /* KHz */ - -#ifdef CONFIG_MCF5301x -#define FREF 20000 /* KHz */ -#define MAX_MFD 63 /* Multiplier */ -#define MIN_MFD 0 /* Multiplier */ -#define USBDIV 8 - -/* Low Power Divider specifications */ -#define MIN_LPD (0) /* Divider (not encoded) */ -#define MAX_LPD (15) /* Divider (not encoded) */ -#define DEFAULT_LPD (0) /* Divider (not encoded) */ -#endif - -#ifdef CONFIG_MCF532x -#define FREF 16000 /* KHz */ -#define MAX_MFD 135 /* Multiplier */ -#define MIN_MFD 88 /* Multiplier */ - -/* Low Power Divider specifications */ -#define MIN_LPD (1 << 0) /* Divider (not encoded) */ -#define MAX_LPD (1 << 15) /* Divider (not encoded) */ -#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ -#endif - -#define BUSDIV 6 /* Divider */ - -/* Get the value of the current system clock */ -int get_sys_clock(void) -{ - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); - int divider; - - /* Test to see if device is in LIMP mode */ - if (ccm->misccr & CCM_MISCCR_LIMP) { - divider = ccm->cdr & CCM_CDR_LPDIV(0xF); -#ifdef CONFIG_MCF5301x - return (FREF / (3 * (1 << divider))); -#endif -#ifdef CONFIG_MCF532x - return (FREF / (2 << divider)); -#endif - } else { -#ifdef CONFIG_MCF5301x - u32 pfdr = (pll->pcr & 0x3F) + 1; - u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8)); - u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1; - - return (((FREF * pfdr) / refdiv) / busdiv); -#endif -#ifdef CONFIG_MCF532x - return ((FREF * pll->pfdr) / (BUSDIV * 4)); -#endif - } -} - -/* - * Initialize the Low Power Divider circuit - * - * Parameters: - * div Desired system frequency divider - * - * Return Value: - * The resulting output system frequency - */ -int clock_limp(int div) -{ - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); - u32 temp; - - /* Check bounds of divider */ - if (div < MIN_LPD) - div = MIN_LPD; - if (div > MAX_LPD) - div = MAX_LPD; - - /* Save of the current value of the SSIDIV so we don't overwrite the value */ - temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF)); - - /* Apply the divider to the system clock */ - ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); - - ccm->misccr |= CCM_MISCCR_LIMP; - - return (FREF / (3 * (1 << div))); -} - -/* Exit low power LIMP mode */ -int clock_exit_limp(void) -{ - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); - int fout; - - /* Exit LIMP mode */ - ccm->misccr &= (~CCM_MISCCR_LIMP); - - /* Wait for PLL to lock */ - while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ; - - fout = get_sys_clock(); - - return fout; -} - -/* Initialize the PLL - * - * Parameters: - * fref PLL reference clock frequency in KHz - * fsys Desired PLL output frequency in KHz - * flags Operating parameters - * - * Return Value: - * The resulting output system frequency - */ -int clock_pll(int fsys, int flags) -{ -#ifdef CONFIG_MCF532x - volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); -#endif - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); - int fref, temp, fout, mfd; - u32 i; - - fref = FREF; - - if (fsys == 0) { - /* Return current PLL output */ -#ifdef CONFIG_MCF5301x - u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1; - mfd = (pll->pcr & 0x3F) + 1; - - return (fref * mfd) / busdiv; -#endif -#ifdef CONFIG_MCF532x - mfd = pll->pfdr; - - return (fref * mfd / (BUSDIV * 4)); -#endif - } - - /* Check bounds of requested system clock */ - if (fsys > MAX_FSYS) - fsys = MAX_FSYS; - - if (fsys < MIN_FSYS) - fsys = MIN_FSYS; - - /* - * Multiplying by 100 when calculating the temp value, - * and then dividing by 100 to calculate the mfd allows - * for exact values without needing to include floating - * point libraries. - */ - temp = (100 * fsys) / fref; -#ifdef CONFIG_MCF5301x - mfd = (BUSDIV * temp) / 100; - - /* Determine the output frequency for selected values */ - fout = ((fref * mfd) / BUSDIV); -#endif -#ifdef CONFIG_MCF532x - mfd = (4 * BUSDIV * temp) / 100; - - /* Determine the output frequency for selected values */ - fout = ((fref * mfd) / (BUSDIV * 4)); -#endif - -/* must not tamper with SDRAMC if running from SDRAM */ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - /* - * Check to see if the SDRAM has already been initialized. - * If it has then the SDRAM needs to be put into self refresh - * mode before reprogramming the PLL. - */ - if (sdram->ctrl & SDRAMC_SDCR_REF) - sdram->ctrl &= ~SDRAMC_SDCR_CKE; - - /* - * Initialize the PLL to generate the new system clock frequency. - * The device must be put into LIMP mode to reprogram the PLL. - */ - - /* Enter LIMP mode */ - clock_limp(DEFAULT_LPD); - -#ifdef CONFIG_MCF5301x - pll->pdr = - PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | - PLL_PDR_OUTDIV2(BUSDIV - 1) | - PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | - PLL_PDR_OUTDIV4(USBDIV - 1); - - pll->pcr &= PLL_PCR_FBDIV_MASK; - pll->pcr |= PLL_PCR_FBDIV(mfd - 1); -#endif -#ifdef CONFIG_MCF532x - /* Reprogram PLL for desired fsys */ - pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); - - pll->pfdr = mfd; -#endif - - /* Exit LIMP mode */ - clock_exit_limp(); - - /* Return the SDRAM to normal operation if it is in use. */ - if (sdram->ctrl & SDRAMC_SDCR_REF) - sdram->ctrl |= SDRAMC_SDCR_CKE; - -#ifdef CONFIG_MCF532x - /* - * software workaround for SDRAM opeartion after exiting LIMP - * mode errata - */ - *sdram_workaround = CONFIG_SYS_SDRAM_BASE; -#endif - - /* wait for DQS logic to relock */ - for (i = 0; i < 0x200; i++) ; -#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ - - return fout; -} - -/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ -int get_clocks(void) -{ - gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; - gd->cpu_clk = (gd->bus_clk * 3); - -#ifdef CONFIG_FSL_I2C - gd->i2c1_clk = gd->bus_clk; -#endif - - return (0); -} diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S deleted file mode 100644 index 5b134aa47c..0000000000 --- a/cpu/mcf532x/start.S +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (C) 2003 Josef Baumgartner - * Based on code from Bernhard Kuhn - * - * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "version.h" - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -#define _START _start -#define _FAULT _fault - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte; - -#if !defined(CONFIG_MONITOR_IS_IN_RAM) -.text -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: - -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ - -/* Reserved */ -vector10_17: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ - -/* TRAP #0 - #15 */ -vector20_2F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector30_3F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector64_127: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector128_191: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector192_255: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ - - .text - - .globl _start -_start: - nop - nop - move.w #0x2700,%sr /* Mask off Interrupt */ - -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 - movec %d0, %VBR -#endif - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 - - /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - -#ifdef CONFIG_MCF5301x - move.l #(0xFC0a0010), %a0 - move.w (%a0), %d0 - and.l %d0, 0xEFFF - - move.w %d0, (%a0) -#endif - - /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 - move.l %d0, (%a1) - move.l %d0, (%a2) - - /* set stackpointer to end of internal ram to get some stackspace for the - first c-code */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- - - move.l #__got_start, %a5 /* put relocation table address to a5 */ - - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ - - /* board_init_f() does not return */ - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ - jsr (%a1) - -/*------------------------------------------------------------------------------*/ -/* exception code */ - .globl _fault -_fault: - jmp _fault - .globl _exc_handler - -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - - .globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0) << 11)), %d0 - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x01000000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x81000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - /* No dcache, just a dummy function */ - .globl dcache_disable -dcache_disable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ - - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - .align 4 diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c deleted file mode 100644 index 48b37dfe7d..0000000000 --- a/cpu/mcf5445x/cpu_init.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#if defined(CONFIG_CMD_NET) -#include -#include -#include -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; - - /* FlexBus */ - gpio->par_be = - GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | - GPIO_PAR_BE_BE0_BE0; - gpio->par_fbctl = - GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | - GPIO_PAR_FBCTL_TS_TS; - -#if !defined(CONFIG_CF_SBF) -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; -#endif -#endif - -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - /* Latch chipselect */ - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; -#endif - -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; -#endif - -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; -#endif - -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; -#endif - -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; -#endif - -#ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; -#endif - - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ -#ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; - - rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; -#endif - - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->par_uart = - (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); - break; - case 1: - gpio->par_uart = - (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); - break; - } -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_s *info = (struct fec_info_s *)dev->priv; - - if (setclear) { - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; - else - gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; - } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; - else - gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; - } - return 0; -} -#endif - -#ifdef CONFIG_CF_DSPI -void cfspi_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK; -} - -int cfspi_claim_bus(uint bus, uint cs) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) - return -1; - - /* Clear FIFO and resume transfer */ - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); - - switch (cs) { - case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; - break; - case 1: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1; - break; - case 2: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; - break; - case 5: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; - break; - } - - return 0; -} - -void cfspi_release_bus(uint bus, uint cs) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ - - switch (cs) { - case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; - break; - case 1: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; - break; - case 2: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; - break; - case 5: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; - break; - } -} -#endif diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S deleted file mode 100644 index d2d4439151..0000000000 --- a/cpu/mcf5445x/start.S +++ /dev/null @@ -1,654 +0,0 @@ -/* - * Copyright (C) 2003 Josef Baumgartner - * Based on code from Bernhard Kuhn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "version.h" - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* last three long word reserved for cache status */ -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) - -#define _START _start -#define _FAULT _fault - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte; - -#if defined(CONFIG_CF_SBF) -#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) -#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) -#endif - -.text - -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: -#if defined(CONFIG_CF_SBF) - -INITSP: .long 0 /* Initial SP */ -INITPC: .long ASM_DRAMINIT /* Initial PC */ - -#else - -INITSP: .long 0 /* Initial SP */ -INITPC: .long _START /* Initial PC */ - -#endif - -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ - -/* Reserved */ -vector10_17: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ - -#if !defined(CONFIG_CF_SBF) - -/* TRAP #0 - #15 */ -vector20_2F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector30_3F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector64_127: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector128_191: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector192_255: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -#endif - -#if defined(CONFIG_CF_SBF) - /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ -asm_sbf_img_hdr: - .long 0x00000000 /* checksum, not yet implemented */ - .long 0x00030000 /* image length */ - .long TEXT_BASE /* image to be relocated at */ - -asm_dram_init: - move.w #0x2700,%sr /* Mask off Interrupt */ - - move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 - movec %d0, %VBR - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 - - /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(CACR_STATUS), %a1 /* CACR */ - move.l #(ICACHE_STATUS), %a2 /* icache */ - move.l #(DCACHE_STATUS), %a3 /* dcache */ - move.l %d0, (%a1) - move.l %d0, (%a2) - move.l %d0, (%a3) - - /* invalidate and disable cache */ - move.l #0x01004100, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - movec %d0, %ACR2 - movec %d0, %ACR3 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- - - /* Must disable global address */ - move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) - move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) - move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) - - /* Dram Initialization a1, a2, and d0 */ - /* mscr sdram */ - move.l #0xFC0A4074, %a1 - move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) - nop - - /* SDRAM Chip 0 and 1 */ - move.l #0xFC0B8110, %a1 - move.l #0xFC0B8114, %a2 - - /* calculate the size */ - move.l #0x13, %d1 - move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 -#ifdef CONFIG_SYS_SDRAM_BASE1 - lsr.l #1, %d2 -#endif - -dramsz_loop: - lsr.l #1, %d2 - add.l #1, %d1 - cmp.l #1, %d2 - bne dramsz_loop - - /* SDRAM Chip 0 and 1 */ - move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) - or.l %d1, (%a1) -#ifdef CONFIG_SYS_SDRAM_BASE1 - move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) - or.l %d1, (%a2) -#endif - nop - - /* dram cfg1 and cfg2 */ - move.l #0xFC0B8008, %a1 - move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) - nop - move.l #0xFC0B800C, %a2 - move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) - nop - - move.l #0xFC0B8000, %a1 /* Mode */ - move.l #0xFC0B8004, %a2 /* Ctrl */ - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - -#ifdef CONFIG_M54455EVB - /* Issue LEMR */ - move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) - nop - move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) - nop -#endif - - move.l #1000, %d1 - jsr asm_delay - - /* Issue PALL */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) - nop - - /* Perform two refresh cycles */ - move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 - nop - move.l %d0, (%a2) - move.l %d0, (%a2) - nop - -#ifdef CONFIG_M54455EVB - move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1) - nop -#elif defined(CONFIG_M54451EVB) - /* Issue LEMR */ - move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) - nop - move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) -#endif - - move.l #500, %d1 - jsr asm_delay - - move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 - and.l #0x7FFFFFFF, %d1 -#ifdef CONFIG_M54455EVB - or.l #0x10000C00, %d1 -#elif defined(CONFIG_M54451EVB) - or.l #0x10000C00, %d1 -#endif - move.l %d1, (%a2) - nop - - move.l #2000, %d1 - jsr asm_delay - - /* - * DSPI Initialization - * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h - * a1 - dspi status - * a2 - dtfr - * a3 - drfr - * a4 - Dst addr - */ - /* Enable pins for DSPI mode - chip-selects are enabled later */ -asm_dspi_init: - move.l #0xFC0A4063, %a0 - move.b #0x7F, (%a0) - - /* Configure DSPI module */ - move.l #0xFC05C000, %a0 - move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ - - move.l #0xFC05C00C, %a0 - move.l #0x3E000011, (%a0) - - move.l #0xFC05C034, %a2 /* dtfr */ - move.l #0xFC05C03B, %a3 /* drfr */ - - move.l #(ASM_SBF_IMG_HDR + 4), %a1 - move.l (%a1)+, %d5 - move.l (%a1), %a4 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 - move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 - - move.l #0xFC05C02C, %a1 /* dspi status */ - - /* Issue commands and address */ - move.l #0x8002000B, %d2 /* Fast Read Cmd */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80020000, %d2 /* Address byte 2 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80020000, %d2 /* Address byte 1 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80020000, %d2 /* Address byte 0 */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.l #0x80020000, %d2 /* Dummy Wr and Rd */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - /* Transfer serial boot header to sram */ -asm_dspi_rd_loop1: - move.l #0x80020000, %d2 - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.b %d1, (%a0) /* read, copy to dst */ - - add.l #1, %a0 /* inc dst by 1 */ - sub.l #1, %d4 /* dec cnt by 1 */ - bne asm_dspi_rd_loop1 - - /* Transfer u-boot from serial flash to memory */ -asm_dspi_rd_loop2: - move.l #0x80020000, %d2 - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - move.b %d1, (%a4) /* read, copy to dst */ - - add.l #1, %a4 /* inc dst by 1 */ - sub.l #1, %d5 /* dec cnt by 1 */ - bne asm_dspi_rd_loop2 - - move.l #0x00020000, %d2 /* Terminate */ - jsr asm_dspi_wr_status - jsr asm_dspi_rd_status - - /* jump to memory and execute */ - move.l #(TEXT_BASE + 0x400), %a0 - jmp (%a0) - -asm_dspi_wr_status: - move.l (%a1), %d0 /* status */ - and.l #0x0000F000, %d0 - cmp.l #0x00003000, %d0 - bgt asm_dspi_wr_status - - move.l %d2, (%a2) - rts - -asm_dspi_rd_status: - move.l (%a1), %d0 /* status */ - and.l #0x000000F0, %d0 - lsr.l #4, %d0 - cmp.l #0, %d0 - beq asm_dspi_rd_status - - move.b (%a3), %d1 - rts - -asm_delay: - nop - subq.l #1, %d1 - bne asm_delay - rts -#endif /* CONFIG_CF_SBF */ - - .text - . = 0x400 - .globl _start -_start: -#if !defined(CONFIG_CF_SBF) - nop - nop - move.w #0x2700,%sr /* Mask off Interrupt */ - - /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 - movec %d0, %VBR - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 - - /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(CACR_STATUS), %a1 /* CACR */ - move.l #(ICACHE_STATUS), %a2 /* icache */ - move.l #(DCACHE_STATUS), %a3 /* dcache */ - move.l %d0, (%a1) - move.l %d0, (%a2) - move.l %d0, (%a3) - - /* invalidate and disable cache */ - move.l #0x01004100, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - movec %d0, %ACR2 - movec %d0, %ACR3 - - /* set stackpointer to end of internal ram to get some stackspace for - the first c-code */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- -#endif - - move.l #__got_start, %a5 /* put relocation table address to a5 */ - - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ - - /* board_init_f() does not return */ - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ - jsr (%a1) - -/*------------------------------------------------------------------------------*/ -/* exception code */ - .globl _fault -_fault: - bra _fault - .globl _exc_handler - -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - - .globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d1 - - move.l #0x00040100, %d0 /* Invalidate icache */ - movec %d0, %CACR - - move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */ - movec %d0, %ACR2 - - move.l #0x04088020, %d0 /* Enable bcache and icache */ - movec %d0, %CACR - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0xFFF77BFF, %d0 - or.l #0x00040100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - clr.l %d0 - movec %d0, %ACR2 - movec %d0, %ACR3 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0x00040100, %d0 /* Invalidate icache */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d1 - - move.l #0x01040100, %d0 - movec %d0, %CACR /* Invalidate dcache */ - - move.l #0x80088020, %d0 /* Enable bcache and icache */ - movec %d0, %CACR - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - and.l #0x7FFFFFFF, %d0 - or.l #0x01000000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable dcache */ - clr.l %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_invalid -dcache_invalid: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0x81088020, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ - - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - .align 4 diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c deleted file mode 100644 index 96a3132b78..0000000000 --- a/cpu/mcf547x_8x/cpu_init.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_NET) -#include -#include -#include -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; - - xlbarb->adrto = 0x2000; - xlbarb->datto = 0x2500; - xlbarb->busto = 0x3000; - - xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT; - - /* Master Priority Enable */ - xlbarb->prien = 0xff; - xlbarb->pri = 0; - -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; -#endif - -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; -#endif - -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; -#endif - -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; -#endif - -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; -#endif - -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; -#endif - -#ifdef CONFIG_FSL_I2C - gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; -#endif - - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ -#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC) - MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512), - MCD_RELOC_TASKS); -#endif - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); - - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); - break; - case 1: - gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); - break; - case 2: - gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); - break; - case 3: - gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); - break; - } - - *pscsicr &= 0xF8; -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; - - if (setclear) { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq |= 0xF000; - else - gpio->par_feci2cirq |= 0x0FC0; - } else { - if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq &= 0x0FFF; - else - gpio->par_feci2cirq &= 0xF03F; - } - return 0; -} -#endif diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S deleted file mode 100644 index 94ef14bf3d..0000000000 --- a/cpu/mcf547x_8x/start.S +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (C) 2003 Josef Baumgartner - * Based on code from Bernhard Kuhn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "version.h" - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* last three long word reserved for cache status */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) - -#define _START _start -#define _FAULT _fault - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte; - -.text -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: - -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ - -/* Reserved */ -vector10_17: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ - -/* TRAP #0 - #15 */ -vector20_2F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector30_3F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector64_127: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector128_191: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector192_255: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - - .text - - .globl _start -_start: - nop - nop - move.w #0x2700,%sr /* Mask off Interrupt */ - - /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 - movec %d0, %VBR - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR0 - - move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0 - movec %d0, %RAMBAR1 - - move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */ - move.c %d0, %MBAR - - /* invalidate and disable cache */ - move.l #0x01040100, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - movec %d0, %ACR2 - movec %d0, %ACR3 - - /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l #(CACR_STATUS), %a3 /* CACR */ - move.l %d0, (%a1) - move.l %d0, (%a2) - move.l %d0, (%a3) - - /* set stackpointer to end of internal ram to get some stackspace for the - first c-code */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- - - move.l #__got_start, %a5 /* put relocation table address to a5 */ - - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ - - /* board_init_f() does not return */ - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ - jsr (%a1) - -/*------------------------------------------------------------------------------*/ -/* exception code */ - .globl _fault -_fault: - bra _fault - .globl _exc_handler - -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - - .globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 - movec %d0, %ACR2 /* Enable cache */ - - move.l #0x020C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x000C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR2 - movec %d0, %ACR3 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_invalid -icache_invalid: - move.l #0x000C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl dcache_enable -dcache_enable: - bsr icache_disable - - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 - movec %d0, %ACR0 /* Enable cache */ - - move.l #0xA30C8100, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #0xA30C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ - - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - .align 4 diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile deleted file mode 100644 index 427db7ae04..0000000000 --- a/cpu/mpc512x/Makefile +++ /dev/null @@ -1,63 +0,0 @@ -# -# (C) Copyright 2007-2009 DENX Software Engineering -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -$(shell mkdir -p $(OBJTREE)/board/freescale/common) - -LIB = $(obj)lib$(CPU).a - -START = start.o -COBJS-y := cpu.o -COBJS-y += traps.o -COBJS-y += cpu_init.o -COBJS-y += fixed_sdram.o -COBJS-y += i2c.o -COBJS-y += interrupts.o -COBJS-y += iopin.o -COBJS-y += serial.o -COBJS-y += speed.o -COBJS-${CONFIG_FSL_DIU_FB} += diu.o -COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o -COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o -COBJS-${CONFIG_CMD_IDE} += ide.o -COBJS-${CONFIG_IIM} += iim.o -COBJS-$(CONFIG_PCI) += pci.o - -COBJS := $(COBJS-y) -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h deleted file mode 100644 index 4b147783fb..0000000000 --- a/cpu/mpc512x/asm-offsets.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * needed for cpu/mpc512x/start.S - * - * These should be auto-generated - */ -#define LPCS0AW 0x0024 -#define SRAMBAR 0x00C4 -#define SWCRR 0x0904 -#define LPC_OFFSET 0x10000 -#define CS0_CONFIG 0x00000 -#define CS_CTRL 0x00020 -#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ - -#define EXC_OFF_SYS_RESET 0x0100 -#define _START_OFFSET EXC_OFF_SYS_RESET diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk deleted file mode 100644 index fb0a563e6f..0000000000 --- a/cpu/mpc512x/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2007-2009 DENX Software Engineering -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -PLATFORM_RELFLAGS += -fPIC -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ - -ffixed-r2 -msoft-float -mcpu=603e - -# Use default linker script. -# A board port can override this setting in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc512x/u-boot.lds diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c deleted file mode 100644 index ca459a101e..0000000000 --- a/cpu/mpc512x/diu.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * York Sun - * - * FSL DIU Framebuffer driver - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "../../board/freescale/common/pixis.h" -#include "../../board/freescale/common/fsl_diu_fb.h" - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) -#include -#include -#endif - -#ifdef CONFIG_FSL_DIU_LOGO_BMP -extern unsigned int FSL_Logo_BMP[]; -#else -#define FSL_Logo_BMP NULL -#endif - -static int xres, yres; - -void diu_set_pixel_clock(unsigned int pixclock) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile clk512x_t *clk = &immap->clk; - volatile unsigned int *clkdvdr = &clk->scfr[0]; - unsigned long speed_ccb, temp, pixval; - - speed_ccb = get_bus_freq(0) * 4; - temp = 1000000000/pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - debug("DIU pixval = %lu\n", pixval); - - /* Modify PXCLK in GUTS CLKDVDR */ - debug("DIU: Current value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); - temp = in_be32(clkdvdr) & 0xFFFFFF00; - out_be32(clkdvdr, temp | (pixval & 0xFF)); - debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); -} - -char *valid_bmp(char *addr) -{ - unsigned long h_addr; - - h_addr = simple_strtoul(addr, NULL, 16); - if (h_addr < CONFIG_SYS_FLASH_BASE || - h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) { - printf("bmp addr %lx is not a valid flash address\n", h_addr); - return 0; - } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) { - printf("bmp addr is not a bmp\n"); - return 0; - } else - return (char *)h_addr; -} - -int mpc5121_diu_init(void) -{ - unsigned int pixel_format; - char *bmp = NULL; - char *bmp_env; - - xres = 1024; - yres = 768; - pixel_format = 0x88883316; - - debug("mpc5121_diu_init\n"); - bmp_env = getenv("diu_bmp_addr"); - if (bmp_env) { - bmp = valid_bmp(bmp_env); - } - if (!bmp) - bmp = (char *)FSL_Logo_BMP; - return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp); -} - -int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp, - int flag, int argc, char *argv[]) -{ - unsigned int addr; - - if (argc < 2) { - cmd_usage(cmdtp); - return 1; - } - - if (!strncmp(argv[1], "init", 4)) { -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - fsl_diu_clear_screen(); - drv_video_init(); -#else - return mpc5121_diu_init(); -#endif - } else { - addr = simple_strtoul(argv[1], NULL, 16); - fsl_diu_clear_screen(); - fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); - } - - return 0; -} - -U_BOOT_CMD( - diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp, - "Init or Display BMP file", - "init\n - initialize DIU\n" - "addr\n - display bmp at address 'addr'" - ); - - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - -/* - * The Graphic Device - */ -GraphicDevice ctfb; -void *video_hw_init(void) -{ - GraphicDevice *pGD = (GraphicDevice *) &ctfb; - struct fb_info *info; - - if (mpc5121_diu_init() < 0) - return NULL; - - /* fill in Graphic device struct */ - sprintf(pGD->modeIdent, "%dx%dx%d %dkHz %dHz", - xres, yres, 32, 64, 60); - - pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); - pGD->winSizeX = xres; - pGD->winSizeY = yres - info->logo_height; - pGD->plnSizeX = pGD->winSizeX; - pGD->plnSizeY = pGD->winSizeY; - - pGD->gdfBytesPP = 4; - pGD->gdfIndex = GDF_32BIT_X888RGB; - - pGD->isaBase = 0; - pGD->pciBase = 0; - pGD->memSize = info->screen_size - info->logo_size; - - /* Cursor Start Address */ - pGD->dprBase = 0; - pGD->vprBase = 0; - pGD->cprBase = 0; - - return (void *)pGD; -} - -/** - * Set the LUT - * - * @index: color number - * @r: red - * @b: blue - * @g: green - */ -void video_set_lut - (unsigned int index, unsigned char r, unsigned char g, unsigned char b) -{ - return; -} - -#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/cpu/mpc512x/u-boot.lds b/cpu/mpc512x/u-boot.lds deleted file mode 100644 index 2e260eb2af..0000000000 --- a/cpu/mpc512x/u-boot.lds +++ /dev/null @@ -1,120 +0,0 @@ -/* - * (C) Copyright 2007 DENX Software Engineering. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc512x/start.o (.text) - *(.text) - *(.got1) - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/cpu/mpc5xx/Makefile b/cpu/mpc5xx/Makefile deleted file mode 100644 index 8aab0189d7..0000000000 --- a/cpu/mpc5xx/Makefile +++ /dev/null @@ -1,59 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# File: cpu/mpc5xx/Makefile -# -# Discription: Makefile to build mpc5xx cpu configuration. -# Will include top config.mk which itselfs -# uses the definitions made in cpu/mpc5xx/config.mk -# - - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).a - -START = start.o -COBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk deleted file mode 100644 index 78549249bd..0000000000 --- a/cpu/mpc5xx/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# File: config.mk -# -# Discription: compiler flags and make definitions -# - - -PLATFORM_RELFLAGS += -fPIC -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds deleted file mode 100644 index deeb06ae26..0000000000 --- a/cpu/mpc5xx/u-boot.lds +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc5xx/start.o (.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - - _end = . ; - PROVIDE (end = .); -/* . = env_start; - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } -*/ -} diff --git a/cpu/mpc5xxx/Makefile b/cpu/mpc5xxx/Makefile deleted file mode 100644 index 06fdbcfb72..0000000000 --- a/cpu/mpc5xxx/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).a - -START = start.o -SOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o -COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \ - loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk deleted file mode 100644 index 5e82f67ea9..0000000000 --- a/cpu/mpc5xxx/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ - -mstring -mcpu=603e -mmultiple - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c deleted file mode 100644 index edfb8282b7..0000000000 --- a/cpu/mpc5xxx/cpu.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code for the MPC5xxx CPUs - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#include -#endif - -#if defined(CONFIG_OF_IDE_FIXUP) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int checkcpu (void) -{ - ulong clock = gd->cpu_clk; - char buf[32]; -#ifndef CONFIG_MGT5100 - uint svr, pvr; -#endif - - puts ("CPU: "); - -#ifdef CONFIG_MGT5100 - puts (CPU_ID_STR); - printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID); -#else - svr = get_svr(); - pvr = get_pvr(); - - switch (pvr) { - case PVR_5200: - printf("MPC5200"); - break; - case PVR_5200B: - printf("MPC5200B"); - break; - default: - printf("Unknown MPC5xxx"); - break; - } - - printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), - PVR_MAJ(pvr), PVR_MIN(pvr)); -#endif - printf (" at %s MHz\n", strmhz (buf, clock)); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int -do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - ulong msr; - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* Charge the watchdog timer */ - *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f; - *(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */ - while(1); - - return 1; - -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - */ -unsigned long get_tbclk (void) -{ - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return (tbclk); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) -void ft_cpu_setup(void *blob, bd_t *bd) -{ - int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4; - char * cpu_path = "/cpus/" OF_CPU; -#ifdef CONFIG_MPC5xxx_FEC - uchar enetaddr[6]; - char * eth_path = "/" OF_SOC "/ethernet@3000"; -#endif - - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1); - do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency", - bd->bi_busfreq*div, 1); -#ifdef CONFIG_MPC5xxx_FEC - eth_getenv_enetaddr("ethaddr", enetaddr); - do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0); - do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0); -#endif -#if defined(CONFIG_OF_IDE_FIXUP) - if (!ide_device_present(0)) { - /* NO CF card detected -> delete ata node in DTS */ - int nodeoffset = 0; - char nodename[] = "/soc5200@f0000000/ata@3a00"; - - nodeoffset = fdt_path_offset(blob, nodename); - if (nodeoffset >= 0) { - fdt_del_node(blob, nodeoffset); - } else { - printf("%s: cannot find %s node err:%s\n", - __func__, nodename, fdt_strerror(nodeoffset)); - } - } - -#endif - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} -#endif - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB); - - *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB); - - if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) - return 0; - else - return (*save_addr & 0x0000ffff); -} -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - -#ifdef CONFIG_MPC5xxx_FEC -/* Default initializations for FEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) - */ - -int cpu_eth_init(bd_t *bis) -{ - return mpc5xxx_fec_initialize(bis); -} -#endif - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset(void) -{ - int re_enable = disable_interrupts(); - reset_5xxx_watchdog(); - if (re_enable) enable_interrupts(); -} - -void reset_5xxx_watchdog(void) -{ - volatile struct mpc5xxx_gpt *gpt0 = - (struct mpc5xxx_gpt *) MPC5XXX_GPT; - - /* Trigger TIMER_0 by writing A5 to OCPW */ - clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000); -} -#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c deleted file mode 100644 index 560c9b311c..0000000000 --- a/cpu/mpc5xxx/cpu_init.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers. - */ -void cpu_init_f (void) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - volatile struct mpc5xxx_lpb *lpb = - (struct mpc5xxx_lpb *) MPC5XXX_LPB; - volatile struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *) MPC5XXX_GPIO; - volatile struct mpc5xxx_xlb *xlb = - (struct mpc5xxx_xlb *) MPC5XXX_XLBARB; -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *) MPC5XXX_CDM; -#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ -#if defined(CONFIG_WATCHDOG) - volatile struct mpc5xxx_gpt *gpt0 = - (struct mpc5xxx_gpt *) MPC5XXX_GPT; -#endif /* CONFIG_WATCHDOG */ - unsigned long addecr = (1 << 25); /* Boot_CS */ - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100) - addecr |= (1 << 22); /* SDRAM enable */ -#endif - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* - * Memory Controller: configure chip selects and enable them - */ -#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE) - out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START)); - out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START, - CONFIG_SYS_BOOTCS_SIZE)); -#endif -#if defined(CONFIG_SYS_BOOTCS_CFG) - out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG); -#endif - -#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) - out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START)); - out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START, - CONFIG_SYS_CS0_SIZE)); - /* CS0 and BOOT_CS cannot be enabled at once. */ - /* addecr |= (1 << 16); */ -#endif -#if defined(CONFIG_SYS_CS0_CFG) - out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG); -#endif - -#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) - out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START)); - out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START, - CONFIG_SYS_CS1_SIZE)); - addecr |= (1 << 17); -#endif -#if defined(CONFIG_SYS_CS1_CFG) - out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG); -#endif - -#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE) - out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START)); - out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START, - CONFIG_SYS_CS2_SIZE)); - addecr |= (1 << 18); -#endif -#if defined(CONFIG_SYS_CS2_CFG) - out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG); -#endif - -#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) - out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START)); - out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START, - CONFIG_SYS_CS3_SIZE)); - addecr |= (1 << 19); -#endif -#if defined(CONFIG_SYS_CS3_CFG) - out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG); -#endif - -#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) - out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START)); - out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START, - CONFIG_SYS_CS4_SIZE)); - addecr |= (1 << 20); -#endif -#if defined(CONFIG_SYS_CS4_CFG) - out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG); -#endif - -#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) - out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START)); - out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START, - CONFIG_SYS_CS5_SIZE)); - addecr |= (1 << 21); -#endif -#if defined(CONFIG_SYS_CS5_CFG) - out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG); -#endif - -#if defined(CONFIG_MPC5200) - addecr |= 1; -#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) - out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START)); - out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START, - CONFIG_SYS_CS6_SIZE)); - addecr |= (1 << 26); -#endif -#if defined(CONFIG_SYS_CS6_CFG) - out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG); -#endif - -#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) - out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START)); - out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START, - CONFIG_SYS_CS7_SIZE)); - addecr |= (1 << 27); -#endif -#if defined(CONFIG_SYS_CS7_CFG) - out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG); -#endif - -#if defined(CONFIG_SYS_CS_BURST) - out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST); -#endif -#if defined(CONFIG_SYS_CS_DEADCYCLE) - out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE); -#endif -#endif /* CONFIG_MPC5200 */ - - /* Enable chip selects */ -#if defined(CONFIG_MGT5100) - out_be32(&mm->addecr, addecr); -#elif defined(CONFIG_MPC5200) - out_be32(&mm->ipbi_ws_ctrl, addecr); -#endif - out_be32(&lpb->cs_ctrl, (1 << 24)); - - /* Setup pin multiplexing */ -#if defined(CONFIG_SYS_GPS_PORT_CONFIG) - out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG); -#endif - -#if defined(CONFIG_MPC5200) - /* enable timebase */ - setbits_be32(&xlb->config, (1 << 13)); - - /* Enable snooping for RAM */ - setbits_be32(&xlb->config, (1 << 15)); - out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d); - -# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) - /* Motorola reports IPB should better run at 133 MHz. */ -# if defined(CONFIG_MGT5100) - setbits_be32(&mm->addecr, 1); -# elif defined(CONFIG_MPC5200) - setbits_be32(&mm->ipbi_ws_ctrl, 1); -# endif - /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ - addecr = in_be32(&cdm->cfg); - addecr &= ~0x103; -# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) - /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ - addecr |= 0x01; -# else - /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ - addecr |= 0x02; -# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ - out_be32(&cdm->cfg, addecr); -# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ - /* Configure the XLB Arbiter */ - out_be32(&xlb->master_pri_enable, 0xff); - out_be32(&xlb->master_priority, 0x11111111); - -# if defined(CONFIG_SYS_XLB_PIPELINING) - /* Enable piplining */ - clrbits_be32(&xlb->config, (1 << 31)); -# endif - -#if defined(CONFIG_WATCHDOG) - /* Charge the watchdog timer - prescaler = 64k, count = 64k*/ - out_be32(&gpt0->cir, 0x0000ffff); - out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */ - - reset_5xxx_watchdog(); -#endif /* CONFIG_WATCHDOG */ - -#endif /* CONFIG_MPC5200 */ -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ - volatile struct mpc5xxx_intr *intr = - (struct mpc5xxx_intr *) MPC5XXX_ICTL; - - /* mask all interrupts */ -#if defined(CONFIG_MGT5100) - out_be32(&intr->per_mask, 0xfffffc00); -#elif defined(CONFIG_MPC5200) - out_be32(&intr->per_mask, 0xffffff00); -#endif - setbits_be32(&intr->main_mask, 0x0001ffff); - clrbits_be32(&intr->ctrl, 0x00000f00); - /* route critical ints to normal ints */ - setbits_be32(&intr->ctrl, 0x00000001); - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) - /* load FEC microcode */ - loadtask(0, 2); -#endif - - return (0); -} diff --git a/cpu/mpc5xxx/firmware_sc_task.impl.S b/cpu/mpc5xxx/firmware_sc_task.impl.S deleted file mode 100644 index b668ee5cf8..0000000000 --- a/cpu/mpc5xxx/firmware_sc_task.impl.S +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (C) 2001, Software Center, Motorola China. - * - * This file contains microcode for the FEC controller of the MGT5100 CPU. - */ - -#include - -#if defined(CONFIG_MGT5100) - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x000000a4 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long 0xf0000000 -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000d0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long 0xf0000000 - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010c504c /* 0020: DRD2B1: var4 = EU1(); EU1(var1,var12) */ -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c504e /* 0030: DRD2B1: var6 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020c504f /* 0038: DRD2B1: var8 = EU1(); EU1(var1,var15) */ -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504c /* 00A0: DRD2B1: idx0 = EU1(); EU1(var1,var12) */ -.long 0x000001f8 /* 00A4(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80014800 /* 0000: LCDEXT: idx0 = 0xf0004800; ; */ -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024c504d /* 0020: DRD2B1: var9 = EU1(); EU1(var1,var13) */ -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010c504e /* 0034: DRD2B1: var4 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014c504f /* 003C: DRD2B1: var5 = EU1(); EU1(var1,var15) */ -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028c5050 /* 0044: DRD2B1: var10 = EU1(); EU1(var1,var16) */ -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c5051 /* 004C: DRD2B1: var6 = EU1(); EU1(var1,var17) */ -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01cc50a1 /* 0058: DRD2B1: var7 = EU1(); EU1(var2,idx1) */ -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000100 /* 0088: DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x0c4c5c4d /* 008C: DRD2B1: *idx1 = EU1(); EU1(*idx1,var13) */ -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504d /* 00CC: DRD2B1: idx0 = EU1(); EU1(var1,var13) */ -.long 0x000001f8 /* 00D0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0xf0004800 /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x000005e4 /* var[16] */ -.long 0x0000000e /* var[17] */ -.long 0x000005e0 /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000001 /* inc[2] */ -.long 0x80000000 /* inc[3] */ -.long 0x40000000 /* inc[4] */ -.long 0x00000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long 0xf0004800 /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000008 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0x4000ffff /* inc[3] */ -.long 0xe0000001 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.align 8 -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 256, 0x0 - - -.align 8 -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 256, 0x0 - -#endif /* CONFIG_MGT5100 */ diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S deleted file mode 100644 index d140c7e989..0000000000 --- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (C) 2001, Software Center, Motorola China. - * - * This file contains microcode for the FEC controller of the MPC5200 CPU. - */ - -#include - -#if defined(CONFIG_MPC5200) - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.align 9 -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x000000a4 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long CONFIG_SYS_MBAR -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000d0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long CONFIG_SYS_MBAR - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010cf04c /* 0020: DRD2B1: var4 = EU3(); EU3(var1,var12) */ -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018cf04e /* 0030: DRD2B1: var6 = EU3(); EU3(var1,var14) */ -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020cf04f /* 0038: DRD2B1: var8 = EU3(); EU3(var1,var15) */ -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080cf04c /* 00A0: DRD2B1: idx0 = EU3(); EU3(var1,var12) */ -.long 0x000001f8 /* 00A4(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80024800 /* 0000: LCDEXT: idx0 = 0xf0008800; ; */ -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024cf04d /* 0020: DRD2B1: var9 = EU3(); EU3(var1,var13) */ -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010cf04e /* 0034: DRD2B1: var4 = EU3(); EU3(var1,var14) */ -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014cf04f /* 003C: DRD2B1: var5 = EU3(); EU3(var1,var15) */ -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028cf050 /* 0044: DRD2B1: var10 = EU3(); EU3(var1,var16) */ -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018cf051 /* 004C: DRD2B1: var6 = EU3(); EU3(var1,var17) */ -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01ccf0a1 /* 0058: DRD2B1: var7 = EU3(); EU3(var2,idx1) */ -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000001 /* 0088: DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */ -.long 0x0c4cfc4d /* 008C: DRD2B1: *idx1 = EU3(); EU3(*idx1,var13) */ -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080cf04d /* 00CC: DRD2B1: idx0 = EU3(); EU3(var1,var13) */ -.long 0x000001f8 /* 00D0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long (CONFIG_SYS_MBAR + 0x8800) /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x000005e4 /* var[16] */ -.long 0x0000000e /* var[17] */ -.long 0x000005e0 /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000001 /* inc[2] */ -.long 0x80000000 /* inc[3] */ -.long 0x40000000 /* inc[4] */ -.long 0x00000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long (CONFIG_SYS_MBAR + 0x8800) /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000008 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0x4000ffff /* inc[3] */ -.long 0xe0000001 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x21800000 /* and(), EU# 3 */ -.long 0x21400000 /* andn(), EU# 3 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x21800000 /* and(), EU# 3 */ -.long 0x21400000 /* andn(), EU# 3 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 128, 0x0 - - -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 128, 0x0 - -#endif /* CONFIG_MPC5200 */ diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c deleted file mode 100644 index 225738a073..0000000000 --- a/cpu/mpc5xxx/pci_mpc5200.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200) - -#include -#include -#include -#include - -/* System RAM mapped over PCI */ -#define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024) - -/* PCIIWCR bit fields */ -#define IWCR_MEM (0 << 3) -#define IWCR_IO (1 << 3) -#define IWCR_READ (0 << 1) -#define IWCR_READLINE (1 << 1) -#define IWCR_READMULT (2 << 1) -#define IWCR_EN (1 << 0) - -static int mpc5200_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; - eieio(); - udelay(10); -#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200) - if (dev & 0x00ff0000) { - u32 val; - val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2)); - udelay(10); - val = val << 16; - val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0)); - *value = val; - } else { - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); - } - udelay(10); -#else - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); -#endif - eieio(); - *(volatile u32 *)MPC5XXX_PCI_CAR = 0; - udelay(10); - return 0; -} - -static int mpc5200_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; - eieio(); - udelay(10); - out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value); - eieio(); - *(volatile u32 *)MPC5XXX_PCI_CAR = 0; - udelay(10); - return 0; -} - -void pci_mpc5xxx_init (struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEMORY_BUS, - CONFIG_PCI_MEMORY_PHYS, - CONFIG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose(hose); - - /* GPIO Multiplexing - enable PCI */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15); - - /* Set host bridge as pci master and enable memory decoding */ - *(vu_long *)MPC5XXX_PCI_CMD |= - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - - /* Set maximum latency timer */ - *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800); - - /* Set cache line size */ - *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) | - (CONFIG_SYS_CACHELINE_SIZE / 4); - - /* Map MBAR to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR; - *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1; - - /* Map RAM to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); - *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1; - - /* Park XLB on PCI */ - *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5)); - *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5); - - /* Disable interrupts from PCI controller */ - *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12); - *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24); - - /* Set PCI retry counter to 0 = infinite retry. */ - /* The default of 255 is too short for slow devices. */ - *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00; - - /* Disable initiator windows */ - *(vu_long *)MPC5XXX_PCI_IWCR = 0; - - /* Map PCI memory to physical space */ - *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS | - (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) | - (CONFIG_PCI_MEM_BUS >> 16); - *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24; - - /* Map PCI I/O to physical space */ - *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS | - (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) | - (CONFIG_PCI_IO_BUS >> 16); - *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16; - - /* Reset the PCI bus */ - *(vu_long *)MPC5XXX_PCI_GSCR |= 1; - udelay(1000); - *(vu_long *)MPC5XXX_PCI_GSCR &= ~1; - udelay(1000); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - mpc5200_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - mpc5200_write_config_dword); - - udelay(1000); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCI && CONFIG_MPC5200 */ diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c deleted file mode 100644 index a8a384aa58..0000000000 --- a/cpu/mpc5xxx/serial.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * (C) Copyright 2000 - 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with - * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the - * Linux/PPC sources (m8260_tty.c had no copyright info in it). - * - * Martin Krause, 8 Jun 2006 - * Added CONFIG_SERIAL_MULTI support - */ - -/* - * Minimal serial functions needed to use one of the PSC ports - * as serial console interface. - */ - -#include -#include - -#if defined (CONFIG_SERIAL_MULTI) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_PSC_CONSOLE) - -#if CONFIG_PSC_CONSOLE == 1 -#define PSC_BASE MPC5XXX_PSC1 -#elif CONFIG_PSC_CONSOLE == 2 -#define PSC_BASE MPC5XXX_PSC2 -#elif CONFIG_PSC_CONSOLE == 3 -#define PSC_BASE MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PSC_CONSOLE must be in 1, 2 or 3 -#elif CONFIG_PSC_CONSOLE == 4 -#define PSC_BASE MPC5XXX_PSC4 -#elif CONFIG_PSC_CONSOLE == 5 -#define PSC_BASE MPC5XXX_PSC5 -#elif CONFIG_PSC_CONSOLE == 6 -#define PSC_BASE MPC5XXX_PSC6 -#else -#error CONFIG_PSC_CONSOLE must be in 1 ... 6 -#endif - -#if defined(CONFIG_SERIAL_MULTI) && !defined(CONFIG_PSC_CONSOLE2) -#error you must define CONFIG_PSC_CONSOLE2 if CONFIG_SERIAL_MULTI is set -#endif - -#if defined(CONFIG_SERIAL_MULTI) -#if CONFIG_PSC_CONSOLE2 == 1 -#define PSC_BASE2 MPC5XXX_PSC1 -#elif CONFIG_PSC_CONSOLE2 == 2 -#define PSC_BASE2 MPC5XXX_PSC2 -#elif CONFIG_PSC_CONSOLE2 == 3 -#define PSC_BASE2 MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3 -#elif CONFIG_PSC_CONSOLE2 == 4 -#define PSC_BASE2 MPC5XXX_PSC4 -#elif CONFIG_PSC_CONSOLE2 == 5 -#define PSC_BASE2 MPC5XXX_PSC5 -#elif CONFIG_PSC_CONSOLE2 == 6 -#define PSC_BASE2 MPC5XXX_PSC6 -#else -#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6 -#endif -#endif /* CONFIG_SERIAL_MULTI */ - -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init (void) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - unsigned long baseclk; - int div; - - /* reset PSC */ - psc->command = PSC_SEL_MODE_REG_1; - - /* select clock sources */ -#if defined(CONFIG_MGT5100) - psc->psc_clock_select = 0xdd00; - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) - psc->psc_clock_select = 0; - baseclk = (gd->ipb_clk + 16) / 32; -#endif - - /* switch to UART mode */ - psc->sicr = 0; - - /* configure parity, bit length and so on */ -#if defined(CONFIG_MGT5100) - psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#elif defined(CONFIG_MPC5200) - psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#endif - psc->mode = PSC_MODE_ONE_STOP; - - /* set up UART divisor */ - div = (baseclk + (gd->baudrate/2)) / gd->baudrate; - psc->ctur = (div >> 8) & 0xff; - psc->ctlr = div & 0xff; - - /* disable all interrupts */ - psc->psc_imr = 0; - - /* reset and enable Rx/Tx */ - psc->command = PSC_RST_RX; - psc->command = PSC_RST_TX; - psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; - - return (0); -} - -#if defined(CONFIG_SERIAL_MULTI) -void serial_putc_dev (unsigned long dev_base, const char c) -#else -void serial_putc(const char c) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - - if (c == '\n') -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, '\r'); -#else - serial_putc('\r'); -#endif - - /* Wait for last character to go. */ - while (!(psc->psc_status & PSC_SR_TXEMP)) - ; - - psc->psc_buffer_8 = c; -} - -#if defined(CONFIG_SERIAL_MULTI) -void serial_putc_raw_dev(unsigned long dev_base, const char c) -#else -void serial_putc_raw(const char c) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - /* Wait for last character to go. */ - while (!(psc->psc_status & PSC_SR_TXEMP)) - ; - - psc->psc_buffer_8 = c; -} - - -#if defined(CONFIG_SERIAL_MULTI) -void serial_puts_dev (unsigned long dev_base, const char *s) -#else -void serial_puts (const char *s) -#endif -{ - while (*s) { -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, *s++); -#else - serial_putc (*s++); -#endif - } -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial_getc_dev (unsigned long dev_base) -#else -int serial_getc(void) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - - /* Wait for a character to arrive. */ - while (!(psc->psc_status & PSC_SR_RXRDY)) - ; - - return psc->psc_buffer_8; -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial_tstc_dev (unsigned long dev_base) -#else -int serial_tstc(void) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - - return (psc->psc_status & PSC_SR_RXRDY); -} - -#if defined(CONFIG_SERIAL_MULTI) -void serial_setbrg_dev (unsigned long dev_base) -#else -void serial_setbrg(void) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - unsigned long baseclk, div; - -#if defined(CONFIG_MGT5100) - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) - baseclk = (gd->ipb_clk + 16) / 32; -#endif - - /* set up UART divisor */ - div = (baseclk + (gd->baudrate/2)) / gd->baudrate; - psc->ctur = (div >> 8) & 0xFF; - psc->ctlr = div & 0xff; -} - -#if defined(CONFIG_SERIAL_MULTI) -void serial_setrts_dev (unsigned long dev_base, int s) -#else -void serial_setrts(int s) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - - if (s) { - /* Assert RTS (become LOW) */ - psc->op1 = 0x1; - } - else { - /* Negate RTS (become HIGH) */ - psc->op0 = 0x1; - } -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial_getcts_dev (unsigned long dev_base) -#else -int serial_getcts(void) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - - return (psc->ip & 0x1) ? 0 : 1; -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial0_init(void) -{ - return (serial_init_dev(PSC_BASE)); -} - -int serial1_init(void) -{ - return (serial_init_dev(PSC_BASE2)); -} -void serial0_setbrg (void) -{ - serial_setbrg_dev(PSC_BASE); -} -void serial1_setbrg (void) -{ - serial_setbrg_dev(PSC_BASE2); -} - -void serial0_putc(const char c) -{ - serial_putc_dev(PSC_BASE,c); -} - -void serial1_putc(const char c) -{ - serial_putc_dev(PSC_BASE2, c); -} -void serial0_puts(const char *s) -{ - serial_puts_dev(PSC_BASE, s); -} - -void serial1_puts(const char *s) -{ - serial_puts_dev(PSC_BASE2, s); -} - -int serial0_getc(void) -{ - return(serial_getc_dev(PSC_BASE)); -} - -int serial1_getc(void) -{ - return(serial_getc_dev(PSC_BASE2)); -} -int serial0_tstc(void) -{ - return (serial_tstc_dev(PSC_BASE)); -} - -int serial1_tstc(void) -{ - return (serial_tstc_dev(PSC_BASE2)); -} - -struct serial_device serial0_device = -{ - "serial0", - "UART0", - serial0_init, - serial0_setbrg, - serial0_getc, - serial0_tstc, - serial0_putc, - serial0_puts, -}; - -struct serial_device serial1_device = -{ - "serial1", - "UART1", - serial1_init, - serial1_setbrg, - serial1_getc, - serial1_tstc, - serial1_putc, - serial1_puts, -}; -#endif /* CONFIG_SERIAL_MULTI */ - -#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S deleted file mode 100644 index d499da5036..0000000000 --- a/cpu/mpc5xxx/start.S +++ /dev/null @@ -1,785 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 - 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * U-Boot - Startup Code for MPC5xxx CPUs - */ -#include -#include -#include -#include - -#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Floating Point enable, Machine Check and Recoverable Interr. */ -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * Version string - */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - -/* - * Exception vectors - */ - .text - . = EXC_OFF_SYS_RESET - .globl _start -_start: - li r21, BOOTFLAG_COLD /* Normal Power-On */ - nop - b boot_cold - - . = EXC_OFF_SYS_RESET + 0x10 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - -boot_cold: -boot_warm: - mfmsr r5 /* save msr contents */ - - /* Move CSBoot and adjust instruction pointer */ - /*--------------------------------------------------------------*/ - -#if defined(CONFIG_SYS_LOWBOOT) -# if defined(CONFIG_SYS_RAMBOOT) -# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT -# endif /* CONFIG_SYS_RAMBOOT */ -# if defined(CONFIG_MGT5100) -# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100 -# endif /* CONFIG_MGT5100 */ - lis r4, CONFIG_SYS_DEFAULT_MBAR@h - lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h - ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l - stw r3, 0x4(r4) /* CS0 start */ - lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h - ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l - stw r3, 0x8(r4) /* CS0 stop */ - lis r3, 0x02010000@h - ori r3, r3, 0x02010000@l - stw r3, 0x54(r4) /* CS0 and Boot enable */ - - lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */ - ori r3, r3, lowboot_reentry@l /* to the address space the linker used */ - mtlr r3 - blr - -lowboot_reentry: - lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h - ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l - stw r3, 0x4c(r4) /* Boot start */ - lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h - ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l - stw r3, 0x50(r4) /* Boot stop */ - lis r3, 0x02000001@h - ori r3, r3, 0x02000001@l - stw r3, 0x54(r4) /* Boot enable, CS0 disable */ -#endif /* CONFIG_SYS_LOWBOOT */ - -#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT) - lis r3, CONFIG_SYS_MBAR@h - ori r3, r3, CONFIG_SYS_MBAR@l -#if defined(CONFIG_MPC5200) - /* MBAR is mirrored into the MBAR SPR */ - mtspr MBAR,r3 - rlwinm r3, r3, 16, 16, 31 -#endif -#if defined(CONFIG_MGT5100) - rlwinm r3, r3, 17, 15, 31 -#endif - lis r4, CONFIG_SYS_DEFAULT_MBAR@h - stw r3, 0(r4) -#endif /* CONFIG_SYS_DEFAULT_MBAR */ - - /* Initialise the MPC5xxx processor core */ - /*--------------------------------------------------------------*/ - - bl init_5xxx_core - - /* initialize some things that are hard to access from C */ - /*--------------------------------------------------------------*/ - - /* set up stack in on-chip SRAM */ - lis r3, CONFIG_SYS_INIT_RAM_ADDR@h - ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l - ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*--------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (in Flash)*/ - - mr r3, r21 - /* r3: BOOTFLAG */ - bl board_init_f /* run 1st part of board init code (in Flash)*/ - -/* - * Vector Table - */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) -#ifdef DEBUG - . = 0x1300 - /* - * This exception occurs when the program counter matches the - * Instruction Address Breakpoint Register (IABR). - * - * I want the cpu to halt if this occurs so I can hunt around - * with the debugger and look at things. - * - * When DEBUG is defined, both machine check enable (in the MSR) - * and checkstop reset enable (in the reset mode register) are - * turned off and so a checkstop condition will result in the cpu - * halting. - * - * I force the cpu into a checkstop condition by putting an illegal - * instruction here (at least this is the theory). - * - * well - that didnt work, so just do an infinite loop! - */ -1: b 1b -#else - STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) -#endif - STD_EXCEPTION(0x1400, SMI, UnknownException) - - STD_EXCEPTION(0x1500, Trap_15, UnknownException) - STD_EXCEPTION(0x1600, Trap_16, UnknownException) - STD_EXCEPTION(0x1700, Trap_17, UnknownException) - STD_EXCEPTION(0x1800, Trap_18, UnknownException) - STD_EXCEPTION(0x1900, Trap_19, UnknownException) - STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) - STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) - STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) - STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) - STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) - STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) - STD_EXCEPTION(0x2000, Trap_20, UnknownException) - STD_EXCEPTION(0x2100, Trap_21, UnknownException) - STD_EXCEPTION(0x2200, Trap_22, UnknownException) - STD_EXCEPTION(0x2300, Trap_23, UnknownException) - STD_EXCEPTION(0x2400, Trap_24, UnknownException) - STD_EXCEPTION(0x2500, Trap_25, UnknownException) - STD_EXCEPTION(0x2600, Trap_26, UnknownException) - STD_EXCEPTION(0x2700, Trap_27, UnknownException) - STD_EXCEPTION(0x2800, Trap_28, UnknownException) - STD_EXCEPTION(0x2900, Trap_29, UnknownException) - STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) - STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) - STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) - STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) - STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) - STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* - * This code initialises the MPC5xxx processor core - * (conforms to PowerPC 603e spec) - * Note: expects original MSR contents to be in r5. - */ - - .globl init_5xx_core -init_5xxx_core: - - /* Initialize machine status; enable machine check interrupt */ - /*--------------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ -#endif - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*--------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_HID0_INIT@h - ori r3, r3, CONFIG_SYS_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CONFIG_SYS_HID0_FINAL@h - ori r3, r3, CONFIG_SYS_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - /* clear all BAT's */ - /*--------------------------------------------------------------*/ - - li r0, 0 - mtspr DBAT0U, r0 - mtspr DBAT0L, r0 - mtspr DBAT1U, r0 - mtspr DBAT1L, r0 - mtspr DBAT2U, r0 - mtspr DBAT2L, r0 - mtspr DBAT3U, r0 - mtspr DBAT3L, r0 - mtspr DBAT4U, r0 - mtspr DBAT4L, r0 - mtspr DBAT5U, r0 - mtspr DBAT5L, r0 - mtspr DBAT6U, r0 - mtspr DBAT6L, r0 - mtspr DBAT7U, r0 - mtspr DBAT7L, r0 - mtspr IBAT0U, r0 - mtspr IBAT0L, r0 - mtspr IBAT1U, r0 - mtspr IBAT1L, r0 - mtspr IBAT2U, r0 - mtspr IBAT2L, r0 - mtspr IBAT3U, r0 - mtspr IBAT3L, r0 - mtspr IBAT4U, r0 - mtspr IBAT4L, r0 - mtspr IBAT5U, r0 - mtspr IBAT5L, r0 - mtspr IBAT6U, r0 - mtspr IBAT6L, r0 - mtspr IBAT7U, r0 - mtspr IBAT7L, r0 - SYNC - - /* invalidate all tlb's */ - /* */ - /* From the 603e User Manual: "The 603e provides the ability to */ - /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ - /* instruction invalidates the TLB entry indexed by the EA, and */ - /* operates on both the instruction and data TLBs simultaneously*/ - /* invalidating four TLB entries (both sets in each TLB). The */ - /* index corresponds to bits 15-19 of the EA. To invalidate all */ - /* entries within both TLBs, 32 tlbie instructions should be */ - /* issued, incrementing this field by one each time." */ - /* */ - /* "Note that the tlbia instruction is not implemented on the */ - /* 603e." */ - /* */ - /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ - /* incrementing by 0x1000 each time. The code below is sort of */ - /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ - /* */ - /*--------------------------------------------------------------*/ - - li r3, 32 - mtctr r3 - li r3, 0 -1: tlbie r3 - addi r3, r3, 0x1000 - bdnz 1b - SYNC - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_DCE - lis r4, 0 - ori r4, r4, HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 - blr - - .globl get_svr -get_svr: - mfspr r3, SVR - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ - rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 - cmpwi r7,0 - beq 9f - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 - cmpwi r7,0 - beq 7f - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds deleted file mode 100644 index c340086619..0000000000 --- a/cpu/mpc5xxx/u-boot-customlayout.lds +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc5xxx/start.o (.text) - cpu/mpc5xxx/traps.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv) - - *(.text) - *(.got1) - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds deleted file mode 100644 index 7fe1e95129..0000000000 --- a/cpu/mpc5xxx/u-boot.lds +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.got1) - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c deleted file mode 100644 index 66a4af8d8e..0000000000 --- a/cpu/mpc5xxx/usb_ohci.c +++ /dev/null @@ -1,1653 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200. - * - * (C) Copyright 2003-2004 - * Gary Jennejohn, DENX Software Engineering - * - * (C) Copyright 2004 - * Pierre Aubert, Staubli Faverges - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* - * IMPORTANT NOTES - * 1 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include - -#ifdef CONFIG_USB_OHCI - -#include -#include -#include "usb_ohci.h" - -#include - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ -#undef DEBUG -#undef SHOW_INFO -#undef OHCI_FILL_TRACE - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#define readl(a) (*((volatile u32 *)(a))) -#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) - -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -#ifdef CONFIG_MPC5200 -#define ohci_cpu_to_le16(x) (x) -#define ohci_cpu_to_le32(x) (x) -#else -#define ohci_cpu_to_le16(x) swap_16(x) -#define ohci_cpu_to_le32(x) swap_32(x) -#endif - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; -/* flag guarding URB transation */ -int urb_finished = 0; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* if we have an unfinished URB from previous transaction let's - * fail and scream as quickly as possible so as not to corrupt - * further communication */ - if (!urb_finished) { - err("sohci_submit_job: URB NOT FINISHED"); - return -1; - } - /* we're about to begin a new transaction here so mark the URB unfinished */ - urb_finished = 0; - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return ohci_cpu_to_le16 (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel (ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel (ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = ohci_cpu_to_le32 (info); - td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); - if (data) - td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); - else - td->hwBE = 0; - td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdINFO = ohci_cpu_to_le32 (td->hwINFO); - tdBE = ohci_cpu_to_le32 (td->hwBE); - tdCBP = ohci_cpu_to_le32 (td->hwCBP); - - - if (!(usb_pipecontrol(lurb_priv->pipe) && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | - (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); - } -#ifdef CONFIG_MPC5200 - td_list->hwNextTD = 0; -#endif - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; - } - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (++(lurb_priv->td_cnt) == lurb_priv->length) { - if ((ed->state & (ED_OPER | ED_UNLINK)) - && (lurb_priv->state != URB_DEL)) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - urb_finished = 1; - } - } - - if (ed->state != ED_NEW) { - edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; - edTailP = ohci_cpu_to_le32 (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#endif - if (usb_pipeint(pipe)) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipebulk(pipe)) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - - /* NOTE: since we are not interrupt driven in U-Boot and always - * handle only one URB at a time, we cannot assume the - * transaction finished on the first successful return from - * hc_interrupt().. unless the flag for current URB is set, - * meaning that all TD's to/from device got actually - * transferred and processed. If the current URB is not - * finished we need to re-iterate this loop so as - * hc_interrupt() gets called again as there needs to be some - * more TD's to process still */ - if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { - /* 0xff is returned for an SF-interrupt */ - break; - } - - if (--timeout) { - wait_ms(1); - if (!urb_finished) - dbg("\%"); - - } else { - err("CTL:TIMEOUT "); - dbg("submit_common_msg: TO status %x\n", stat); - stat = USB_ST_CRC_ERR; - urb_finished = 1; - break; - } - } -#if 0 - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } -#endif - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, - readl (&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - ohci->hc_control = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - -#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && - !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { - - ints = OHCI_INTR_WDH; - - } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { - ohci->disabled++; - err ("%s device removed!", ohci->slot_name); - return -1; - - } else if ((ints &= readl (®s->intrenable)) == 0) { - dbg("hc_interrupt: returning..\n"); - return 0xff; - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - stat = 0xff; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; - wait_ms(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(void) -{ - - /* Set the USB Clock */ - *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; - -#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */ - /* remove all PSC3 USB bits first before ORing in ours */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00; -#else - /* remove all USB bits first before ORing in ours */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000; -#endif - /* Activate USB port */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG; - - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)MPC5XXX_USB; - - gohci.flags = 0; - gohci.slot_name = "mpc5200"; - - if (hc_reset (&gohci) < 0) { - hc_release_ohci (&gohci); - return -1; - } - - if (hc_start (&gohci) < 0) { - err ("can't start usb-%s", gohci.slot_name); - hc_release_ohci (&gohci); - return -1; - } - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#endif - ohci_inited = 1; - urb_finished = 1; - - return 0; -} - -int usb_lowlevel_stop(void) -{ - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/mpc5xxx/usb_ohci.h b/cpu/mpc5xxx/usb_ohci.h deleted file mode 100644 index 6eedbdd1d9..0000000000 --- a/cpu/mpc5xxx/usb_ohci.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ - -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute__((aligned(16))); -typedef struct ed ed_t; - - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute__((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ -#if defined(CONFIG_MPC5200) - __u16 pad1; /* set to 0 on each frame_no change */ - __u16 frame_no; /* current frame number */ -#else - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ -#endif - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute__((aligned(256))); - - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute__((aligned(32))); - - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct -{ - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) - { - if (ptd[i].usb_dev == NULL) - { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk deleted file mode 100644 index 3ce40c0dbe..0000000000 --- a/cpu/mpc8220/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \ - -mstring -mcpu=603e -mmultiple - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc8220/u-boot.lds diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds deleted file mode 100644 index 4400e60c8f..0000000000 --- a/cpu/mpc8220/u-boot.lds +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8220/start.o (.text) - *(.text) - *(.got1) - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk deleted file mode 100644 index 940474bbd9..0000000000 --- a/cpu/mpc824x/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds deleted file mode 100644 index 0eac48f2cd..0000000000 --- a/cpu/mpc824x/u-boot.lds +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2001-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - *(.text) - *(.got1) - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk deleted file mode 100644 index 39d81eef8b..0000000000 --- a/cpu/mpc8260/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ - -mstring -mcpu=603e -mmultiple - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc8260/u-boot.lds diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds deleted file mode 100644 index c777cf9da9..0000000000 --- a/cpu/mpc8260/u-boot.lds +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2001-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.got1) - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk deleted file mode 100644 index e80919bc28..0000000000 --- a/cpu/mpc83xx/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \ - -ffixed-r2 -msoft-float - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds deleted file mode 100644 index c84d4b0222..0000000000 --- a/cpu/mpc83xx/u-boot.lds +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc83xx/start.o (.text) - *(.text) - *(.got1) - . = ALIGN(16); - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile deleted file mode 100644 index 56de7eb381..0000000000 --- a/cpu/mpc85xx/Makefile +++ /dev/null @@ -1,91 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002,2003 Motorola Inc. -# Xianghua Xiao,X.Xiao@motorola.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).a - -START = start.o resetvec.o -SOBJS-$(CONFIG_MP) += release.o -SOBJS = $(SOBJS-y) - -COBJS-$(CONFIG_CPM2) += commproc.o - -# supports ddr1 -COBJS-$(CONFIG_MPC8540) += ddr-gen1.o -COBJS-$(CONFIG_MPC8560) += ddr-gen1.o -COBJS-$(CONFIG_MPC8541) += ddr-gen1.o -COBJS-$(CONFIG_MPC8555) += ddr-gen1.o - -# supports ddr1/2 -COBJS-$(CONFIG_MPC8548) += ddr-gen2.o -COBJS-$(CONFIG_MPC8568) += ddr-gen2.o -COBJS-$(CONFIG_MPC8544) += ddr-gen2.o - -# supports ddr1/2/3 -COBJS-$(CONFIG_MPC8572) += ddr-gen3.o -COBJS-$(CONFIG_MPC8536) += ddr-gen3.o -COBJS-$(CONFIG_MPC8569) += ddr-gen3.o -COBJS-$(CONFIG_P1011) += ddr-gen3.o -COBJS-$(CONFIG_P1020) += ddr-gen3.o -COBJS-$(CONFIG_P2010) += ddr-gen3.o -COBJS-$(CONFIG_P2020) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o - -COBJS-$(CONFIG_CPM2) += ether_fcc.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_QE) += qe_io.o -COBJS-$(CONFIG_CPM2) += serial_scc.o - -COBJS = $(COBJS-y) -COBJS += cpu.o -COBJS += cpu_init.o -COBJS += cpu_init_early.o -COBJS += interrupts.o -COBJS += speed.o -COBJS += tlb.o -COBJS += traps.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk deleted file mode 100644 index 408184ad15..0000000000 --- a/cpu/mpc85xx/config.mk +++ /dev/null @@ -1,35 +0,0 @@ -# -# (C) Copyright 2002,2003 Motorola Inc. -# Xianghua Xiao, X.Xiao@motorola.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -meabi - -PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string - -# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; -# see "[PATCH,rs6000] make -mno-spe work as expected" on -# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html -PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=yes) -PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe) - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc85xx/u-boot.lds diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S deleted file mode 100644 index 00c4c547fd..0000000000 --- a/cpu/mpc85xx/release.S +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * Kumar Gala - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -/* To boot secondary cpus, we need a place for them to start up. - * Normally, they start at 0xfffffffc, but that's usually the - * firmware, and we don't want to have to run the firmware again. - * Instead, the primary cpu will set the BPTR to point here to - * this page. We then set up the core, and head to - * start_secondary. Note that this means that the code below - * must never exceed 1023 instructions (the branch at the end - * would then be the 1024th). - */ - .globl __secondary_start_page - .align 12 -__secondary_start_page: -/* First do some preliminary setup */ - lis r3, HID0_EMCP@h /* enable machine check */ -#ifndef CONFIG_E500MC - ori r3,r3,HID0_TBEN@l /* enable Timebase */ -#endif -#ifdef CONFIG_PHYS_64BIT - ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ -#endif - mtspr SPRN_HID0,r3 - -#ifndef CONFIG_E500MC - li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ - mtspr SPRN_HID1,r3 -#endif - - /* Enable branch prediction */ - li r3,0x201 - mtspr SPRN_BUCSR,r3 - - /* Ensure TB is 0 */ - li r3,0 - mttbl r3 - mttbu r3 - - /* Enable/invalidate the I-Cache */ - mfspr r0,SPRN_L1CSR1 - ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE) - mtspr SPRN_L1CSR1,r0 - isync - - /* Enable/invalidate the D-Cache */ - mfspr r0,SPRN_L1CSR0 - ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE) - msync - isync - mtspr SPRN_L1CSR0,r0 - isync - -#define toreset(x) (x - __secondary_start_page + 0xfffff000) - - /* get our PIR to figure out our table entry */ - lis r3,toreset(__spin_table)@h - ori r3,r3,toreset(__spin_table)@l - - /* r10 has the base address for the entry */ - mfspr r0,SPRN_PIR -#ifdef CONFIG_E500MC - rlwinm r4,r0,27,27,31 -#else - mr r4,r0 -#endif - slwi r8,r4,5 - add r10,r3,r8 - -#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) - /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ - slwi r8,r4,1 - addi r8,r8,32 - mtspr L1CSR2,r8 -#endif - -#ifdef CONFIG_BACKSIDE_L2_CACHE - /* Enable/invalidate the L2 cache */ - msync - lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h - ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l - mtspr SPRN_L2CSR0,r2 -1: - mfspr r3,SPRN_L2CSR0 - and. r1,r3,r2 - bne 1b - -#ifdef CONFIG_SYS_CACHE_STASHING - /* set stash id to (coreID) * 2 + 32 + L2 (1) */ - addi r3,r8,1 - mtspr SPRN_L2CSR1,r3 -#endif - - lis r3,CONFIG_SYS_INIT_L2CSR0@h - ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l - mtspr SPRN_L2CSR0,r3 - isync -2: - mfspr r3,SPRN_L2CSR0 - andis. r1,r3,L2CSR0_L2E@h - beq 2b -#endif - -#define EPAPR_MAGIC (0x45504150) -#define ENTRY_ADDR_UPPER 0 -#define ENTRY_ADDR_LOWER 4 -#define ENTRY_R3_UPPER 8 -#define ENTRY_R3_LOWER 12 -#define ENTRY_RESV 16 -#define ENTRY_PIR 20 -#define ENTRY_R6_UPPER 24 -#define ENTRY_R6_LOWER 28 -#define ENTRY_SIZE 32 - - /* setup the entry */ - li r3,0 - li r8,1 - stw r0,ENTRY_PIR(r10) - stw r3,ENTRY_ADDR_UPPER(r10) - stw r8,ENTRY_ADDR_LOWER(r10) - stw r3,ENTRY_R3_UPPER(r10) - stw r4,ENTRY_R3_LOWER(r10) - stw r3,ENTRY_R6_UPPER(r10) - stw r3,ENTRY_R6_LOWER(r10) - - /* load r13 with the address of the 'bootpg' in SDRAM */ - lis r13,toreset(__bootpg_addr)@h - ori r13,r13,toreset(__bootpg_addr)@l - lwz r13,0(r13) - - /* setup mapping for AS = 1, and jump there */ - lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h - mtspr SPRN_MAS0,r11 - lis r11,(MAS1_VALID|MAS1_IPROT)@h - ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l - mtspr SPRN_MAS1,r11 - oris r11,r13,(MAS2_I|MAS2_G)@h - ori r11,r13,(MAS2_I|MAS2_G)@l - mtspr SPRN_MAS2,r11 - oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h - ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l - mtspr SPRN_MAS3,r11 - tlbwe - - bl 1f -1: mflr r11 - /* - * OR in 0xfff to create a mask of the bootpg SDRAM address. We use - * this mask to fixup the cpu spin table and the address that we want - * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the - * bootpg is at 0x7ffff000 in SDRAM. - */ - ori r13,r13,0xfff - and r11, r11, r13 - and r10, r10, r13 - - addi r11,r11,(2f-1b) - mfmsr r13 - ori r12,r13,MSR_IS|MSR_DS@l - - mtspr SPRN_SRR0,r11 - mtspr SPRN_SRR1,r12 - rfi - - /* spin waiting for addr */ -2: - lwz r4,ENTRY_ADDR_LOWER(r10) - andi. r11,r4,1 - bne 2b - isync - - /* setup IVORs to match fixed offsets */ -#include "fixed_ivor.S" - - /* get the upper bits of the addr */ - lwz r11,ENTRY_ADDR_UPPER(r10) - - /* setup branch addr */ - mtspr SPRN_SRR0,r4 - - /* mark the entry as released */ - li r8,3 - stw r8,ENTRY_ADDR_LOWER(r10) - - /* mask by ~64M to setup our tlb we will jump to */ - rlwinm r12,r4,0,0,5 - - /* setup r3, r4, r5, r6, r7, r8, r9 */ - lwz r3,ENTRY_R3_LOWER(r10) - li r4,0 - li r5,0 - lwz r6,ENTRY_R6_LOWER(r10) - lis r7,(64*1024*1024)@h - li r8,0 - li r9,0 - - /* load up the pir */ - lwz r0,ENTRY_PIR(r10) - mtspr SPRN_PIR,r0 - mfspr r0,SPRN_PIR - stw r0,ENTRY_PIR(r10) - - mtspr IVPR,r12 -/* - * Coming here, we know the cpu has one TLB mapping in TLB1[0] - * which maps 0xfffff000-0xffffffff one-to-one. We set up a - * second mapping that maps addr 1:1 for 64M, and then we jump to - * addr - */ - lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h - mtspr SPRN_MAS0,r10 - lis r10,(MAS1_VALID|MAS1_IPROT)@h - ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l - mtspr SPRN_MAS1,r10 - /* WIMGE = 0b00000 for now */ - mtspr SPRN_MAS2,r12 - ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) - mtspr SPRN_MAS3,r12 -#ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr SPRN_MAS7,r11 -#endif - tlbwe - -/* Now we have another mapping for this page, so we jump to that - * mapping - */ - mtspr SPRN_SRR1,r13 - rfi - - /* - * Allocate some space for the SDRAM address of the bootpg. - * This variable has to be in the boot page so that it can - * be accessed by secondary cores when they come out of reset. - */ - .globl __bootpg_addr -__bootpg_addr: - .long 0 - - .align L1_CACHE_SHIFT - .globl __spin_table -__spin_table: - .space CONFIG_MAX_CPUS*ENTRY_SIZE - - /* Fill in the empty space. The actual reset vector is - * the last word of the page */ -__secondary_start_code_end: - .space 4092 - (__secondary_start_code_end - __secondary_start_page) -__secondary_reset_vector: - b __secondary_start_page diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S deleted file mode 100644 index 386fa81990..0000000000 --- a/cpu/mpc85xx/start.S +++ /dev/null @@ -1,1159 +0,0 @@ -/* - * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. - * Copyright (C) 2003 Motorola,Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards - * - * The processor starts at 0xfffffffc and the code is first executed in the - * last 4K page(0xfffff000-0xffffffff) in flash/rom. - * - */ - -#include -#include -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - -#ifndef CONFIG_NAND_SPL - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) -#endif - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * e500 Startup -- after reset only the last 4KB of the effective - * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg - * section is located at THIS LAST page and basically does three - * things: clear some registers, set up exception tables and - * add more TLB entries for 'larger spaces'(e.g. the boot rom) to - * continue the boot procedure. - - * Once the boot rom is mapped by TLB entries we can proceed - * with normal startup. - * - */ - - .section .bootpg,"ax" - .globl _start_e500 - -_start_e500: - -/* clear registers/arrays not reset by hardware */ - - /* L1 */ - li r0,2 - mtspr L1CSR0,r0 /* invalidate d-cache */ - mtspr L1CSR1,r0 /* invalidate i-cache */ - - mfspr r1,DBSR - mtspr DBSR,r1 /* Clear all valid bits */ - - /* - * Enable L1 Caches early - * - */ - -#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) - /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ - li r2,(32 + 0) - mtspr L1CSR2,r2 -#endif - - lis r2,L1CSR0_CPE@H /* enable parity */ - ori r2,r2,L1CSR0_DCE - mtspr L1CSR0,r2 /* enable L1 Dcache */ - isync - mtspr L1CSR1,r2 /* enable L1 Icache */ - isync - msync - - /* Setup interrupt vectors */ - lis r1,TEXT_BASE@h - mtspr IVPR,r1 - - li r1,0x0100 - mtspr IVOR0,r1 /* 0: Critical input */ - li r1,0x0200 - mtspr IVOR1,r1 /* 1: Machine check */ - li r1,0x0300 - mtspr IVOR2,r1 /* 2: Data storage */ - li r1,0x0400 - mtspr IVOR3,r1 /* 3: Instruction storage */ - li r1,0x0500 - mtspr IVOR4,r1 /* 4: External interrupt */ - li r1,0x0600 - mtspr IVOR5,r1 /* 5: Alignment */ - li r1,0x0700 - mtspr IVOR6,r1 /* 6: Program check */ - li r1,0x0800 - mtspr IVOR7,r1 /* 7: floating point unavailable */ - li r1,0x0900 - mtspr IVOR8,r1 /* 8: System call */ - /* 9: Auxiliary processor unavailable(unsupported) */ - li r1,0x0a00 - mtspr IVOR10,r1 /* 10: Decrementer */ - li r1,0x0b00 - mtspr IVOR11,r1 /* 11: Interval timer */ - li r1,0x0c00 - mtspr IVOR12,r1 /* 12: Watchdog timer */ - li r1,0x0d00 - mtspr IVOR13,r1 /* 13: Data TLB error */ - li r1,0x0e00 - mtspr IVOR14,r1 /* 14: Instruction TLB error */ - li r1,0x0f00 - mtspr IVOR15,r1 /* 15: Debug */ - - /* Clear and set up some registers. */ - li r0,0x0000 - lis r1,0xffff - mtspr DEC,r0 /* prevent dec exceptions */ - mttbl r0 /* prevent fit & wdt exceptions */ - mttbu r0 - mtspr TSR,r1 /* clear all timer exception status */ - mtspr TCR,r0 /* disable all */ - mtspr ESR,r0 /* clear exception syndrome register */ - mtspr MCSR,r0 /* machine check syndrome register */ - mtxer r0 /* clear integer exception register */ - -#ifdef CONFIG_SYS_BOOK3E_HV - mtspr MAS8,r0 /* make sure MAS8 is clear */ -#endif - - /* Enable Time Base and Select Time Base Clock */ - lis r0,HID0_EMCP@h /* Enable machine check */ -#if defined(CONFIG_ENABLE_36BIT_PHYS) - ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ -#endif -#ifndef CONFIG_E500MC - ori r0,r0,HID0_TBEN@l /* Enable Timebase */ -#endif - mtspr HID0,r0 - -#ifndef CONFIG_E500MC - li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ - mtspr HID1,r0 -#endif - - /* Enable Branch Prediction */ -#if defined(CONFIG_BTB) - li r0,0x201 /* BBFI = 1, BPEN = 1 */ - mtspr BUCSR,r0 -#endif - -#if defined(CONFIG_SYS_INIT_DBCR) - lis r1,0xffff - ori r1,r1,0xffff - mtspr DBSR,r1 /* Clear all status bits */ - lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ - ori r0,r0,CONFIG_SYS_INIT_DBCR@l - mtspr DBCR0,r0 -#endif - -#ifdef CONFIG_MPC8569 -#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) -#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) - - /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to - * use address space which is more than 12bits, and it must be done in - * the 4K boot page. So we set this bit here. - */ - - /* create a temp mapping TLB0[0] for LBCR */ - lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h - ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l - - lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l - - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@l - - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - - /* Set LBCR register */ - lis r4,CONFIG_SYS_LBCR_ADDR@h - ori r4,r4,CONFIG_SYS_LBCR_ADDR@l - - lis r5,CONFIG_SYS_LBC_LBCR@h - ori r5,r5,CONFIG_SYS_LBC_LBCR@l - stw r5,0(r4) - isync - - /* invalidate this temp TLB */ - lis r4,CONFIG_SYS_LBC_ADDR@h - ori r4,r4,CONFIG_SYS_LBC_ADDR@l - tlbivax 0,r4 - isync - -#endif /* CONFIG_MPC8569 */ - - lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h - ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l - -#ifndef CONFIG_SYS_RAMBOOT - /* create a temp mapping in AS=1 to the 4M boot window */ - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l - - lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l - - /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ - lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l -#else - /* - * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main - * image has been relocated to TEXT_BASE on the second stage. - */ - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l - - lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l - - lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l -#endif - - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - - /* create a temp mapping in AS=1 to the stack */ - lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h - ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l - - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l - - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l - - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - - lis r6,MSR_IS|MSR_DS@h - ori r6,r6,MSR_IS|MSR_DS@l - lis r7,switch_as@h - ori r7,r7,switch_as@l - - mtspr SPRN_SRR0,r7 - mtspr SPRN_SRR1,r6 - rfi - -switch_as: -/* L1 DCache is used for initial RAM */ - - /* Allocate Initial RAM in data cache. - */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l - mfspr r2, L1CFG0 - andi. r2, r2, 0x1ff - /* cache size * 1024 / (2 * L1 line size) */ - slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) - mtctr r2 - li r0,0 -1: - dcbz r0,r3 - dcbtls 0,r0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - - /* Jump out the last 4K page and continue to 'normal' start */ -#ifdef CONFIG_SYS_RAMBOOT - b _start_cont -#else - /* Calculate absolute address in FLASH and jump there */ - /*--------------------------------------------------------------*/ - lis r3,CONFIG_SYS_MONITOR_BASE@h - ori r3,r3,CONFIG_SYS_MONITOR_BASE@l - addi r3,r3,_start_cont - _start + _START_OFFSET - mtlr r3 - blr -#endif - - .text - .globl _start -_start: - .long 0x27051956 /* U-BOOT Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - .align 4 - .globl _start_cont -_start_cont: - /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r1,CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l - - li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0,RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ - - GET_GOT - bl cpu_init_early_f - - /* switch back to AS = 0 */ - lis r3,(MSR_CE|MSR_ME|MSR_DE)@h - ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l - mtmsr r3 - isync - - bl cpu_init_f - bl board_init_f - isync - -#ifndef CONFIG_NAND_SPL - . = EXC_OFF_SYS_RESET - .globl _start_of_vectors -_start_of_vectors: - -/* Critical input. */ - CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) - -/* Machine check */ - MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x0300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x0400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) - -/* Alignment exception. */ - . = 0x0600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x0700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* No FPU on MPC85xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) - - . = 0x0900 -/* - * r0 - SYSCALL number - * r3-... arguments - */ -SystemCall: - addis r11,r0,0 /* get functions table addr */ - ori r11,r11,0 /* Note: this code is patched in trap_init */ - addis r12,r0,0 /* get number of functions */ - ori r12,r12,0 - - cmplw 0,r0,r12 - bge 1f - - rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ - add r11,r11,r0 - lwz r11,0(r11) - - li r20,0xd00-4 /* Get stack pointer */ - lwz r12,0(r20) - subi r12,r12,12 /* Adjust stack pointer */ - li r0,0xc00+_end_back-SystemCall - cmplw 0,r0,r12 /* Check stack overflow */ - bgt 1f - stw r12,0(r20) - - mflr r0 - stw r0,0(r12) - mfspr r0,SRR0 - stw r0,4(r12) - mfspr r0,SRR1 - stw r0,8(r12) - - li r12,0xc00+_back-SystemCall - mtlr r12 - mtspr SRR0,r11 - -1: SYNC - rfi -_back: - - mfmsr r11 /* Disable interrupts */ - li r12,0 - ori r12,r12,MSR_EE - andc r11,r11,r12 - SYNC /* Some chip revs need this... */ - mtmsr r11 - SYNC - - li r12,0xd00-4 /* restore regs */ - lwz r12,0(r12) - - lwz r11,0(r12) - mtlr r11 - lwz r11,4(r12) - mtspr SRR0,r11 - lwz r11,8(r12) - mtspr SRR1,r11 - - addi r12,r12,12 /* Adjust stack pointer */ - li r20,0xd00-4 - stw r12,0(r20) - - SYNC - rfi -_end_back: - - STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) - STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) - STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) - - STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) - STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) - - CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) - - .globl _end_of_vectors -_end_of_vectors: - - - . = . + (0x100 - ( . & 0xff )) /* align for debug */ - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -crit_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SPRN_CSRR0,r2 - mtspr SPRN_CSRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfci - -mck_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SPRN_MCSRR0,r2 - mtspr SPRN_MCSRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfmci - -/* Cache functions. -*/ -.globl invalidate_icache -invalidate_icache: - mfspr r0,L1CSR1 - ori r0,r0,L1CSR1_ICFI - msync - isync - mtspr L1CSR1,r0 - isync - blr /* entire I cache */ - -.globl invalidate_dcache -invalidate_dcache: - mfspr r0,L1CSR0 - ori r0,r0,L1CSR0_DCFI - msync - isync - mtspr L1CSR0,r0 - isync - blr - - .globl icache_enable -icache_enable: - mflr r8 - bl invalidate_icache - mtlr r8 - isync - mfspr r4,L1CSR1 - ori r4,r4,0x0001 - oris r4,r4,0x0001 - mtspr L1CSR1,r4 - isync - blr - - .globl icache_disable -icache_disable: - mfspr r0,L1CSR1 - lis r3,0 - ori r3,r3,L1CSR1_ICE - andc r0,r0,r3 - mtspr L1CSR1,r0 - isync - blr - - .globl icache_status -icache_status: - mfspr r3,L1CSR1 - andi. r3,r3,L1CSR1_ICE - blr - - .globl dcache_enable -dcache_enable: - mflr r8 - bl invalidate_dcache - mtlr r8 - isync - mfspr r0,L1CSR0 - ori r0,r0,0x0001 - oris r0,r0,0x0001 - msync - isync - mtspr L1CSR0,r0 - isync - blr - - .globl dcache_disable -dcache_disable: - mfspr r3,L1CSR0 - lis r4,0 - ori r4,r4,L1CSR0_DCE - andc r3,r3,r4 - mtspr L1CSR0,r0 - isync - blr - - .globl dcache_status -dcache_status: - mfspr r3,L1CSR0 - andi. r3,r3,L1CSR0_DCE - blr - - .globl get_pir -get_pir: - mfspr r3,PIR - blr - - .globl get_pvr -get_pvr: - mfspr r3,PVR - blr - - .globl get_svr -get_svr: - mfspr r3,SVR - blr - - .globl wr_tcr -wr_tcr: - mtspr TCR,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0x0000(r3) - sync - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0x0000(r3) - sync - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,r0,r3 - sync - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0x0000(r3) - sync - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,r0,r3 - sync - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0x0000(3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,r0,r3 - blr -#endif /* !CONFIG_NAND_SPL */ - -/*------------------------------------------------------------------------------*/ - -/* - * void write_tlb(mas0, mas1, mas2, mas3, mas7) - */ - .globl write_tlb -write_tlb: - mtspr MAS0,r3 - mtspr MAS1,r4 - mtspr MAS2,r5 - mtspr MAS3,r6 -#ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr MAS7,r7 -#endif - li r3,0 -#ifdef CONFIG_SYS_BOOK3E_HV - mtspr MAS8,r3 -#endif - isync - tlbwe - msync - isync - blr - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1,r3 /* Set new stack pointer */ - mr r9,r4 /* Save copy of Init Data pointer */ - mr r10,r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3,r5 /* Destination Address */ - lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4,r4,CONFIG_SYS_MONITOR_BASE@l - lwz r5,GOT(__init_end) - sub r5,r5,r4 - li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15,r10,r4 - - /* First our own GOT */ - add r12,r12,r15 - /* the the one used by the C code */ - add r30,r30,r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - - /* - * Re-point the IVPR at RAM - */ - mtspr IVPR,r10 - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0,r10,in_ram - _start + _START_OFFSET - mtlr r0 - blr /* NEVER RETURNS! */ - .globl in_ram -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0,r3,r4 - beq 6f - - li r0,0 -5: - stw r0,0(r3) - addi r3,r3,4 - cmplw 0,r3,r4 - bne 5b -6: - - mr r3,r9 /* Init Data pointer */ - mr r4,r10 /* Destination Address */ - bl board_init_r - -#ifndef CONFIG_NAND_SPL - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7,GOT(_start_of_vectors) - lwz r8,GOT(_end_of_vectors) - - li r9,0x100 /* reset vector always at 0x100 */ - - cmplw 0,r7,r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0,0(r7) - stw r0,0(r9) - addi r7,r7,4 - addi r9,r9,4 - cmplw 0,r7,r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7,.L_CriticalInput - _start + _START_OFFSET - bl trap_reloc - li r7,.L_MachineCheck - _start + _START_OFFSET - bl trap_reloc - li r7,.L_DataStorage - _start + _START_OFFSET - bl trap_reloc - li r7,.L_InstStorage - _start + _START_OFFSET - bl trap_reloc - li r7,.L_ExtInterrupt - _start + _START_OFFSET - bl trap_reloc - li r7,.L_Alignment - _start + _START_OFFSET - bl trap_reloc - li r7,.L_ProgramCheck - _start + _START_OFFSET - bl trap_reloc - li r7,.L_FPUnavailable - _start + _START_OFFSET - bl trap_reloc - li r7,.L_Decrementer - _start + _START_OFFSET - bl trap_reloc - li r7,.L_IntervalTimer - _start + _START_OFFSET - li r8,_end_of_vectors - _start + _START_OFFSET -2: - bl trap_reloc - addi r7,r7,0x100 /* next exception vector */ - cmplw 0,r7,r8 - blt 2b - - lis r7,0x0 - mtspr IVPR,r7 - - mtlr r4 /* restore link register */ - blr - -.globl unlock_ram_in_cache -unlock_ram_in_cache: - /* invalidate the INIT_RAM section */ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h - ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l - mfspr r4,L1CFG0 - andi. r4,r4,0x1ff - slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) - mtctr r4 -1: dcbi r0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - sync - - /* Invalidate the TLB entries for the cache */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l - tlbivax 0,r3 - addi r3,r3,0x1000 - tlbivax 0,r3 - addi r3,r3,0x1000 - tlbivax 0,r3 - addi r3,r3,0x1000 - tlbivax 0,r3 - isync - blr - -.globl flush_dcache -flush_dcache: - mfspr r3,SPRN_L1CFG0 - - rlwinm r5,r3,9,3 /* Extract cache block size */ - twlgti r5,1 /* Only 32 and 64 byte cache blocks - * are currently defined. - */ - li r4,32 - subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - - * log2(number of ways) - */ - slw r5,r4,r5 /* r5 = cache block size */ - - rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ - mulli r7,r7,13 /* An 8-way cache will require 13 - * loads per set. - */ - slw r7,r7,r6 - - /* save off HID0 and set DCFA */ - mfspr r8,SPRN_HID0 - ori r9,r8,HID0_DCFA@l - mtspr SPRN_HID0,r9 - isync - - lis r4,0 - mtctr r7 - -1: lwz r3,0(r4) /* Load... */ - add r4,r4,r5 - bdnz 1b - - msync - lis r4,0 - mtctr r7 - -1: dcbf 0,r4 /* ...and flush. */ - add r4,r4,r5 - bdnz 1b - - /* restore HID0 */ - mtspr SPRN_HID0,r8 - isync - - blr - -.globl setup_ivors -setup_ivors: - -#include "fixed_ivor.S" - blr -#endif /* !CONFIG_NAND_SPL */ diff --git a/cpu/mpc85xx/u-boot-nand.lds b/cpu/mpc85xx/u-boot-nand.lds deleted file mode 100644 index b4c63e2a2a..0000000000 --- a/cpu/mpc85xx/u-boot-nand.lds +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - *(.text) - *(.got1) - } :text - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - .bootpg ADDR(.text) - 0x1000 : - { - cpu/mpc85xx/start.o (.bootpg) - } :text = 0xffff - - . = ADDR(.text) + 0x80000; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } :bss - - . = ALIGN(4); - _end = . ; - PROVIDE (end = .); -} diff --git a/cpu/mpc85xx/u-boot.lds b/cpu/mpc85xx/u-boot.lds deleted file mode 100644 index 183dce9514..0000000000 --- a/cpu/mpc85xx/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef RESET_VECTOR_ADDRESS -#define RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - *(.text) - *(.got1) - } :text - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - .bootpg RESET_VECTOR_ADDRESS - 0xffc : - { - cpu/mpc85xx/start.o (.bootpg) - } :text = 0xffff - - .resetvec RESET_VECTOR_ADDRESS : - { - *(.resetvec) - } :text = 0xffff - - . = RESET_VECTOR_ADDRESS + 0x4; - - /* - * Make sure that the bss segment isn't linked at 0x0, otherwise its - * address won't be updated during relocation fixups. Note that - * this is a temporary fix. Code to dynamically the fixup the bss - * location will be added in the future. When the bss relocation - * fixup code is present this workaround should be removed. - */ -#if (RESET_VECTOR_ADDRESS == 0xfffffffc) - . |= 0x10; -#endif - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } :bss - - . = ALIGN(4); - _end = . ; - PROVIDE (end = .); -} diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c deleted file mode 100644 index f7e012db57..0000000000 --- a/cpu/mpc86xx/cpu.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright 2006,2009 Freescale Semiconductor, Inc. - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Default board reset function - */ -static void -__board_reset(void) -{ - /* Do nothing */ -} -void board_reset(void) __attribute__((weak, alias("__board_reset"))); - - -int -checkcpu(void) -{ - sys_info_t sysinfo; - uint pvr, svr; - uint ver; - uint major, minor; - char buf1[32], buf2[32]; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - struct cpu_type *cpu; - uint msscr0 = mfspr(MSSCR0); - - svr = get_svr(); - ver = SVR_SOC_VER(svr); - major = SVR_MAJ(svr); - minor = SVR_MIN(svr); - - if (cpu_numcores() > 1) { -#ifndef CONFIG_MP - puts("Unicore software on multiprocessor system!!\n" - "To enable mutlticore build define CONFIG_MP\n"); -#endif - } - puts("CPU: "); - - cpu = gd->cpu; - - puts(cpu->name); - - printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); - puts("Core: "); - - pvr = get_pvr(); - ver = PVR_E600_VER(pvr); - major = PVR_E600_MAJ(pvr); - minor = PVR_E600_MIN(pvr); - - printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); - if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) - puts("\n Core1Translation Enabled"); - debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); - - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); - - get_sys_info(&sysinfo); - - puts("Clock Configuration:\n"); - printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); - printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); - printf(" DDR:%-4s MHz (%s MT/s data rate), ", - strmhz(buf1, sysinfo.freqSystemBus / 2), - strmhz(buf2, sysinfo.freqSystemBus)); - - if (sysinfo.freqLocalBus > LCRR_CLKDIV) { - printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); - } else { - printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", - sysinfo.freqLocalBus); - } - - puts("L1: D-cache 32 KB enabled\n"); - puts(" I-cache 32 KB enabled\n"); - - puts("L2: "); - if (get_l2cr() & 0x80000000) { -#if defined(CONFIG_MPC8610) - puts("256"); -#elif defined(CONFIG_MPC8641) - puts("512"); -#endif - puts(" KB enabled\n"); - } else { - puts("Disabled\n"); - } - - return 0; -} - - -void -do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - - /* Attempt board-specific reset */ - board_reset(); - - /* Next try asserting HRESET_REQ */ - out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ); - - while (1) - ; -} - - -/* - * Get timebase clock frequency - */ -unsigned long -get_tbclk(void) -{ - sys_info_t sys_info; - - get_sys_info(&sys_info); - return (sys_info.freqSystemBus + 3L) / 4L; -} - - -#if defined(CONFIG_WATCHDOG) -void -watchdog_reset(void) -{ -#if defined(CONFIG_MPC8610) - /* - * This actually feed the hard enabled watchdog. - */ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_wdt_t *wdt = &immap->im_wdt; - volatile ccsr_gur_t *gur = &immap->im_gur; - u32 tmp = gur->pordevsr; - - if (tmp & 0x4000) { - wdt->swsrr = 0x556c; - wdt->swsrr = 0xaa39; - } -#endif -} -#endif /* CONFIG_WATCHDOG */ - -/* - * Print out the state of various machine registers. - * Currently prints out LAWs, BR0/OR0, and BATs - */ -void mpc86xx_reginfo(void) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - ccsr_lbc_t *lbc = &immap->im_lbc; - - print_bats(); - print_laws(); - - printf ("Local Bus Controller Registers\n" - "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0)); - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1)); - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2)); - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3)); - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4)); - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5)); - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6)); - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); - -} diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c deleted file mode 100644 index 5a78a9cdc7..0000000000 --- a/cpu/mpc86xx/cpu_init.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2004,2009 Freescale Semiconductor, Inc. - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * cpu_init.c - low level cpu init - */ - -#include -#include -#include -#include -#include -#include - -void setup_bats(void); - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Breathe some life into the CPU... - * - * Set up the memory map - * initialize a bunch of registers - */ - -void cpu_init_f(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - -#ifdef CONFIG_FSL_LAW - init_laws(); -#endif - - setup_bats(); - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CONFIG_SYS_OR0_REMAP) - memctl->or0 = CONFIG_SYS_OR0_REMAP; -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - memctl->or1 = CONFIG_SYS_OR1_REMAP; -#endif - - /* now restrict to preliminary range */ -#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) - memctl->br0 = CONFIG_SYS_BR0_PRELIM; - memctl->or0 = CONFIG_SYS_OR0_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - memctl->or1 = CONFIG_SYS_OR1_PRELIM; - memctl->br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - memctl->or2 = CONFIG_SYS_OR2_PRELIM; - memctl->br2 = CONFIG_SYS_BR2_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - memctl->or3 = CONFIG_SYS_OR3_PRELIM; - memctl->br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - memctl->or4 = CONFIG_SYS_OR4_PRELIM; - memctl->br4 = CONFIG_SYS_BR4_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - memctl->or5 = CONFIG_SYS_OR5_PRELIM; - memctl->br5 = CONFIG_SYS_BR5_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - memctl->or6 = CONFIG_SYS_OR6_PRELIM; - memctl->br6 = CONFIG_SYS_BR6_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - memctl->or7 = CONFIG_SYS_OR7_PRELIM; - memctl->br7 = CONFIG_SYS_BR7_PRELIM; -#endif -#if defined(CONFIG_FSL_DMA) - dma_init(); -#endif - - /* enable the timebase bit in HID0 */ - set_hid0(get_hid0() | 0x4000000); - - /* enable EMCP, SYNCBE | ABE bits in HID1 */ - set_hid1(get_hid1() | 0x80000C00); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ -#if defined(CONFIG_MP) - setup_mp(); -#endif - return 0; -} - -/* Set up BAT registers */ -void setup_bats(void) -{ - write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); - write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); - write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); - write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); - write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); - write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); - write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); - write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); - write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); - write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); - write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); - write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); - write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); - write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); - write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); - write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); - - return; -} - -#ifdef CONFIG_ADDR_MAP -/* Initialize address mapping array */ -void init_addr_map(void) -{ - int i; - ppc_bat_t bat = DBAT0; - phys_size_t size; - unsigned long upper, lower; - - for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { - if (read_bat(bat, &upper, &lower) != -1) { - if (!BATU_VALID(upper)) - size = 0; - else - size = BATU_SIZE(upper); - addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), - size, i); - } -#ifdef CONFIG_HIGH_BATS - /* High bats are not contiguous with low BAT numbers */ - if (bat == DBAT3) - bat = DBAT4 - 1; -#endif - } -} -#endif diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c deleted file mode 100644 index d191263f50..0000000000 --- a/cpu/mpc8xxx/cpu.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c. - * Basically this file contains cpu specific common code for 85xx/86xx - * processors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct cpu_type cpu_type_list [] = { -#if defined(CONFIG_MPC85xx) - CPU_TYPE_ENTRY(8533, 8533, 1), - CPU_TYPE_ENTRY(8533, 8533_E, 1), - CPU_TYPE_ENTRY(8535, 8535, 1), - CPU_TYPE_ENTRY(8535, 8535_E, 1), - CPU_TYPE_ENTRY(8536, 8536, 1), - CPU_TYPE_ENTRY(8536, 8536_E, 1), - CPU_TYPE_ENTRY(8540, 8540, 1), - CPU_TYPE_ENTRY(8541, 8541, 1), - CPU_TYPE_ENTRY(8541, 8541_E, 1), - CPU_TYPE_ENTRY(8543, 8543, 1), - CPU_TYPE_ENTRY(8543, 8543_E, 1), - CPU_TYPE_ENTRY(8544, 8544, 1), - CPU_TYPE_ENTRY(8544, 8544_E, 1), - CPU_TYPE_ENTRY(8545, 8545, 1), - CPU_TYPE_ENTRY(8545, 8545_E, 1), - CPU_TYPE_ENTRY(8547, 8547_E, 1), - CPU_TYPE_ENTRY(8548, 8548, 1), - CPU_TYPE_ENTRY(8548, 8548_E, 1), - CPU_TYPE_ENTRY(8555, 8555, 1), - CPU_TYPE_ENTRY(8555, 8555_E, 1), - CPU_TYPE_ENTRY(8560, 8560, 1), - CPU_TYPE_ENTRY(8567, 8567, 1), - CPU_TYPE_ENTRY(8567, 8567_E, 1), - CPU_TYPE_ENTRY(8568, 8568, 1), - CPU_TYPE_ENTRY(8568, 8568_E, 1), - CPU_TYPE_ENTRY(8569, 8569, 1), - CPU_TYPE_ENTRY(8569, 8569_E, 1), - CPU_TYPE_ENTRY(8572, 8572, 2), - CPU_TYPE_ENTRY(8572, 8572_E, 2), - CPU_TYPE_ENTRY(P1011, P1011, 1), - CPU_TYPE_ENTRY(P1011, P1011_E, 1), - CPU_TYPE_ENTRY(P1020, P1020, 2), - CPU_TYPE_ENTRY(P1020, P1020_E, 2), - CPU_TYPE_ENTRY(P2010, P2010, 1), - CPU_TYPE_ENTRY(P2010, P2010_E, 1), - CPU_TYPE_ENTRY(P2020, P2020, 2), - CPU_TYPE_ENTRY(P2020, P2020_E, 2), - CPU_TYPE_ENTRY(P4040, P4040, 4), - CPU_TYPE_ENTRY(P4040, P4040_E, 4), - CPU_TYPE_ENTRY(P4080, P4080, 8), - CPU_TYPE_ENTRY(P4080, P4080_E, 8), -#elif defined(CONFIG_MPC86xx) - CPU_TYPE_ENTRY(8610, 8610, 1), - CPU_TYPE_ENTRY(8641, 8641, 2), - CPU_TYPE_ENTRY(8641D, 8641D, 2), -#endif -}; - -struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); - -struct cpu_type *identify_cpu(u32 ver) -{ - int i; - for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { - if (cpu_type_list[i].soc_ver == ver) - return &cpu_type_list[i]; - } - return &cpu_type_unknown; -} - -int cpu_numcores() { - struct cpu_type *cpu; - cpu = gd->cpu; - return cpu->num_cores; -} - -int probecpu (void) -{ - uint svr; - uint ver; - - svr = get_svr(); - ver = SVR_SOC_VER(svr); - - gd->cpu = identify_cpu(ver); - - return 0; -} - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(bd_t *bis) -{ -#if defined(CONFIG_ETHER_ON_FCC) - fec_initialize(bis); -#endif - -#if defined(CONFIG_UEC_ETH) - uec_standard_init(bis); -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) - tsec_standard_init(bis); -#endif - - return 0; -} diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c deleted file mode 100644 index adc4f6ee37..0000000000 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ /dev/null @@ -1,1358 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - */ - -#include -#include - -#include "ddr.h" - -extern unsigned int picos_to_mclk(unsigned int picos); -/* - * Determine Rtt value. - * - * This should likely be either board or controller specific. - * - * Rtt(nominal) - DDR2: - * 0 = Rtt disabled - * 1 = 75 ohm - * 2 = 150 ohm - * 3 = 50 ohm - * Rtt(nominal) - DDR3: - * 0 = Rtt disabled - * 1 = 60 ohm - * 2 = 120 ohm - * 3 = 40 ohm - * 4 = 20 ohm - * 5 = 30 ohm - * - * FIXME: Apparently 8641 needs a value of 2 - * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 - * - * FIXME: There was some effort down this line earlier: - * - * unsigned int i; - * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { - * if (popts->dimmslot[i].num_valid_cs - * && (popts->cs_local_opts[2*i].odt_rd_cfg - * || popts->cs_local_opts[2*i].odt_wr_cfg)) { - * rtt = 2; - * break; - * } - * } - */ -static inline int fsl_ddr_get_rtt(void) -{ - int rtt; - -#if defined(CONFIG_FSL_DDR1) - rtt = 0; -#elif defined(CONFIG_FSL_DDR2) - rtt = 3; -#else - rtt = 0; -#endif - - return rtt; -} - -/* - * compute the CAS write latency according to DDR3 spec - * CWL = 5 if tCK >= 2.5ns - * 6 if 2.5ns > tCK >= 1.875ns - * 7 if 1.875ns > tCK >= 1.5ns - * 8 if 1.5ns > tCK >= 1.25ns - */ -static inline unsigned int compute_cas_write_latency(void) -{ - unsigned int cwl; - const unsigned int mclk_ps = get_memory_clk_period_ps(); - - if (mclk_ps >= 2500) - cwl = 5; - else if (mclk_ps >= 1875) - cwl = 6; - else if (mclk_ps >= 1500) - cwl = 7; - else if (mclk_ps >= 1250) - cwl = 8; - else - cwl = 8; - return cwl; -} - -/* Chip Select Configuration (CSn_CONFIG) */ -static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const dimm_params_t *dimm_params) -{ - unsigned int cs_n_en = 0; /* Chip Select enable */ - unsigned int intlv_en = 0; /* Memory controller interleave enable */ - unsigned int intlv_ctl = 0; /* Interleaving control */ - unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ - unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ - unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ - unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ - unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ - unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ - - /* Compute CS_CONFIG only for existing ranks of each DIMM. */ - if ((((i&1) == 0) - && (dimm_params[i/2].n_ranks == 1)) - || (dimm_params[i/2].n_ranks == 2)) { - unsigned int n_banks_per_sdram_device; - cs_n_en = 1; - if (i == 0) { - /* These fields only available in CS0_CONFIG */ - intlv_en = popts->memctl_interleaving; - intlv_ctl = popts->memctl_interleaving_mode; - } - ap_n_en = popts->cs_local_opts[i].auto_precharge; - odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; - odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; - n_banks_per_sdram_device - = dimm_params[i/2].n_banks_per_sdram_device; - ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; - row_bits_cs_n = dimm_params[i/2].n_row_addr - 12; - col_bits_cs_n = dimm_params[i/2].n_col_addr - 8; - } - - ddr->cs[i].config = (0 - | ((cs_n_en & 0x1) << 31) - | ((intlv_en & 0x3) << 29) - | ((intlv_ctl & 0xf) << 24) - | ((ap_n_en & 0x1) << 23) - - /* XXX: some implementation only have 1 bit starting at left */ - | ((odt_rd_cfg & 0x7) << 20) - - /* XXX: Some implementation only have 1 bit starting at left */ - | ((odt_wr_cfg & 0x7) << 16) - - | ((ba_bits_cs_n & 0x3) << 14) - | ((row_bits_cs_n & 0x7) << 8) - | ((col_bits_cs_n & 0x7) << 0) - ); - debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); -} - -/* Chip Select Configuration 2 (CSn_CONFIG_2) */ -/* FIXME: 8572 */ -static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int pasr_cfg = 0; /* Partial array self refresh config */ - - ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); - debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); -} - -/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ - -#if !defined(CONFIG_FSL_DDR1) -/* - * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) - * - * Avoid writing for DDR I. The new PQ38 DDR controller - * dreams up non-zero default values to be backwards compatible. - */ -static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ - unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ - /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ - unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ - unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ - - /* Active powerdown exit timing (tXARD and tXARDS). */ - unsigned char act_pd_exit_mclk; - /* Precharge powerdown exit timing (tXP). */ - unsigned char pre_pd_exit_mclk; - /* Precharge powerdown exit timing (tAXPD). */ - unsigned char taxpd_mclk; - /* Mode register set cycle time (tMRD). */ - unsigned char tmrd_mclk; - -#if defined(CONFIG_FSL_DDR3) - /* - * (tXARD and tXARDS). Empirical? - * The DDR3 spec has not tXARD, - * we use the tXP instead of it. - * tXP=max(3nCK, 7.5ns) for DDR3. - * spec has not the tAXPD, we use - * tAXPD=8, need design to confirm. - */ - int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - act_pd_exit_mclk = picos_to_mclk(tXP); - /* Mode register MR0[A12] is '1' - fast exit */ - pre_pd_exit_mclk = act_pd_exit_mclk; - taxpd_mclk = 8; - tmrd_mclk = 4; -#else /* CONFIG_FSL_DDR2 */ - /* - * (tXARD and tXARDS). Empirical? - * tXARD = 2 for DDR2 - * tXP=2 - * tAXPD=8 - */ - act_pd_exit_mclk = 2; - pre_pd_exit_mclk = 2; - taxpd_mclk = 8; - tmrd_mclk = 2; -#endif - - ddr->timing_cfg_0 = (0 - | ((trwt_mclk & 0x3) << 30) /* RWT */ - | ((twrt_mclk & 0x3) << 28) /* WRT */ - | ((trrt_mclk & 0x3) << 26) /* RRT */ - | ((twwt_mclk & 0x3) << 24) /* WWT */ - | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ - | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ - | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ - | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ - ); - debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); -} -#endif /* defined(CONFIG_FSL_DDR2) */ - -/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ -static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) -{ - /* Extended Activate to precharge interval (tRAS) */ - unsigned int ext_acttopre = 0; - unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */ - unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */ - unsigned int cntl_adj = 0; /* Control Adjust */ - - /* If the tRAS > 19 MCLK, we use the ext mode */ - if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13) - ext_acttopre = 1; - - ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4; - - /* If the CAS latency more than 8, use the ext mode */ - if (cas_latency > 8) - ext_caslat = 1; - - ddr->timing_cfg_3 = (0 - | ((ext_acttopre & 0x1) << 24) - | ((ext_refrec & 0xF) << 16) - | ((ext_caslat & 0x1) << 12) - | ((cntl_adj & 0x7) << 0) - ); - debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); -} - -/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ -static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) -{ - /* Precharge-to-activate interval (tRP) */ - unsigned char pretoact_mclk; - /* Activate to precharge interval (tRAS) */ - unsigned char acttopre_mclk; - /* Activate to read/write interval (tRCD) */ - unsigned char acttorw_mclk; - /* CASLAT */ - unsigned char caslat_ctrl; - /* Refresh recovery time (tRFC) ; trfc_low */ - unsigned char refrec_ctrl; - /* Last data to precharge minimum interval (tWR) */ - unsigned char wrrec_mclk; - /* Activate-to-activate interval (tRRD) */ - unsigned char acttoact_mclk; - /* Last write data pair to read command issue interval (tWTR) */ - unsigned char wrtord_mclk; - - pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps); - acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps); - acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps); - - /* - * Translate CAS Latency to a DDR controller field value: - * - * CAS Lat DDR I DDR II Ctrl - * Clocks SPD Bit SPD Bit Value - * ------- ------- ------- ----- - * 1.0 0 0001 - * 1.5 1 0010 - * 2.0 2 2 0011 - * 2.5 3 0100 - * 3.0 4 3 0101 - * 3.5 5 0110 - * 4.0 4 0111 - * 4.5 1000 - * 5.0 5 1001 - */ -#if defined(CONFIG_FSL_DDR1) - caslat_ctrl = (cas_latency + 1) & 0x07; -#elif defined(CONFIG_FSL_DDR2) - caslat_ctrl = 2 * cas_latency - 1; -#else - /* - * if the CAS latency more than 8 cycle, - * we need set extend bit for it at - * TIMING_CFG_3[EXT_CASLAT] - */ - if (cas_latency > 8) - cas_latency -= 8; - caslat_ctrl = 2 * cas_latency - 1; -#endif - - refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); - if (popts->OTF_burst_chop_en) - wrrec_mclk += 2; - - acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps); - /* - * JEDEC has min requirement for tRRD - */ -#if defined(CONFIG_FSL_DDR3) - if (acttoact_mclk < 4) - acttoact_mclk = 4; -#endif - wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps); - /* - * JEDEC has some min requirements for tWTR - */ -#if defined(CONFIG_FSL_DDR2) - if (wrtord_mclk < 2) - wrtord_mclk = 2; -#elif defined(CONFIG_FSL_DDR3) - if (wrtord_mclk < 4) - wrtord_mclk = 4; -#endif - if (popts->OTF_burst_chop_en) - wrtord_mclk += 2; - - ddr->timing_cfg_1 = (0 - | ((pretoact_mclk & 0x0F) << 28) - | ((acttopre_mclk & 0x0F) << 24) - | ((acttorw_mclk & 0xF) << 20) - | ((caslat_ctrl & 0xF) << 16) - | ((refrec_ctrl & 0xF) << 12) - | ((wrrec_mclk & 0x0F) << 8) - | ((acttoact_mclk & 0x07) << 4) - | ((wrtord_mclk & 0x07) << 0) - ); - debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); -} - -/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ -static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) -{ - /* Additive latency */ - unsigned char add_lat_mclk; - /* CAS-to-preamble override */ - unsigned short cpo; - /* Write latency */ - unsigned char wr_lat; - /* Read to precharge (tRTP) */ - unsigned char rd_to_pre; - /* Write command to write data strobe timing adjustment */ - unsigned char wr_data_delay; - /* Minimum CKE pulse width (tCKE) */ - unsigned char cke_pls; - /* Window for four activates (tFAW) */ - unsigned short four_act; - - /* FIXME add check that this must be less than acttorw_mclk */ - add_lat_mclk = additive_latency; - cpo = popts->cpo_override; - -#if defined(CONFIG_FSL_DDR1) - /* - * This is a lie. It should really be 1, but if it is - * set to 1, bits overlap into the old controller's - * otherwise unused ACSM field. If we leave it 0, then - * the HW will magically treat it as 1 for DDR 1. Oh Yea. - */ - wr_lat = 0; -#elif defined(CONFIG_FSL_DDR2) - wr_lat = cas_latency - 1; -#else - wr_lat = compute_cas_write_latency(); -#endif - - rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); - /* - * JEDEC has some min requirements for tRTP - */ -#if defined(CONFIG_FSL_DDR2) - if (rd_to_pre < 2) - rd_to_pre = 2; -#elif defined(CONFIG_FSL_DDR3) - if (rd_to_pre < 4) - rd_to_pre = 4; -#endif - if (additive_latency) - rd_to_pre += additive_latency; - if (popts->OTF_burst_chop_en) - rd_to_pre += 2; /* according to UM */ - - wr_data_delay = popts->write_data_delay; - cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps); - four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps); - - ddr->timing_cfg_2 = (0 - | ((add_lat_mclk & 0xf) << 28) - | ((cpo & 0x1f) << 23) - | ((wr_lat & 0xf) << 19) - | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) - | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) - | ((cke_pls & 0x7) << 6) - | ((four_act & 0x3f) << 0) - ); - debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); -} - -/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ -static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - unsigned int mem_en; /* DDR SDRAM interface logic enable */ - unsigned int sren; /* Self refresh enable (during sleep) */ - unsigned int ecc_en; /* ECC enable. */ - unsigned int rd_en; /* Registered DIMM enable */ - unsigned int sdram_type; /* Type of SDRAM */ - unsigned int dyn_pwr; /* Dynamic power management mode */ - unsigned int dbw; /* DRAM dta bus width */ - unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ - unsigned int ncap = 0; /* Non-concurrent auto-precharge */ - unsigned int threeT_en; /* Enable 3T timing */ - unsigned int twoT_en; /* Enable 2T timing */ - unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ - unsigned int x32_en = 0; /* x32 enable */ - unsigned int pchb8 = 0; /* precharge bit 8 enable */ - unsigned int hse; /* Global half strength override */ - unsigned int mem_halt = 0; /* memory controller halt */ - unsigned int bi = 0; /* Bypass initialization */ - - mem_en = 1; - sren = popts->self_refresh_in_sleep; - if (common_dimm->all_DIMMs_ECC_capable) { - /* Allow setting of ECC only if all DIMMs are ECC. */ - ecc_en = popts->ECC_mode; - } else { - ecc_en = 0; - } - - rd_en = (common_dimm->all_DIMMs_registered - && !common_dimm->all_DIMMs_unbuffered); - - sdram_type = CONFIG_FSL_SDRAM_TYPE; - - dyn_pwr = popts->dynamic_power; - dbw = popts->data_bus_width; - /* 8-beat burst enable DDR-III case - * we must clear it when use the on-the-fly mode, - * must set it when use the 32-bits bus mode. - */ - if (sdram_type == SDRAM_TYPE_DDR3) { - if (popts->burst_length == DDR_BL8) - eight_be = 1; - if (popts->burst_length == DDR_OTF) - eight_be = 0; - if (dbw == 0x1) - eight_be = 1; - } - - threeT_en = popts->threeT_en; - twoT_en = popts->twoT_en; - ba_intlv_ctl = popts->ba_intlv_ctl; - hse = popts->half_strength_driver_enable; - - ddr->ddr_sdram_cfg = (0 - | ((mem_en & 0x1) << 31) - | ((sren & 0x1) << 30) - | ((ecc_en & 0x1) << 29) - | ((rd_en & 0x1) << 28) - | ((sdram_type & 0x7) << 24) - | ((dyn_pwr & 0x1) << 21) - | ((dbw & 0x3) << 19) - | ((eight_be & 0x1) << 18) - | ((ncap & 0x1) << 17) - | ((threeT_en & 0x1) << 16) - | ((twoT_en & 0x1) << 15) - | ((ba_intlv_ctl & 0x7F) << 8) - | ((x32_en & 0x1) << 5) - | ((pchb8 & 0x1) << 4) - | ((hse & 0x1) << 3) - | ((mem_halt & 0x1) << 1) - | ((bi & 0x1) << 0) - ); - debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); -} - -/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ -static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned int frc_sr = 0; /* Force self refresh */ - unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ - unsigned int dll_rst_dis; /* DLL reset disable */ - unsigned int dqs_cfg; /* DQS configuration */ - unsigned int odt_cfg; /* ODT configuration */ - unsigned int num_pr; /* Number of posted refreshes */ - unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ - unsigned int ap_en; /* Address Parity Enable */ - unsigned int d_init; /* DRAM data initialization */ - unsigned int rcw_en = 0; /* Register Control Word Enable */ - unsigned int md_en = 0; /* Mirrored DIMM Enable */ - - dll_rst_dis = 1; /* Make this configurable */ - dqs_cfg = popts->DQS_config; - if (popts->cs_local_opts[0].odt_rd_cfg - || popts->cs_local_opts[0].odt_wr_cfg) { - /* FIXME */ - odt_cfg = 2; - } else { - odt_cfg = 0; - } - - num_pr = 1; /* Make this configurable */ - - /* - * 8572 manual says - * {TIMING_CFG_1[PRETOACT] - * + [DDR_SDRAM_CFG_2[NUM_PR] - * * ({EXT_REFREC || REFREC} + 8 + 2)]} - * << DDR_SDRAM_INTERVAL[REFINT] - */ -#if defined(CONFIG_FSL_DDR3) - obc_cfg = popts->OTF_burst_chop_en; -#else - obc_cfg = 0; -#endif - - ap_en = 0; /* Make this configurable? */ - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Use the DDR controller to auto initialize memory. */ - d_init = 1; - ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; - debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); -#else - /* Memory will be initialized via DMA, or not at all. */ - d_init = 0; -#endif - -#if defined(CONFIG_FSL_DDR3) - md_en = popts->mirrored_dimm; -#endif - ddr->ddr_sdram_cfg_2 = (0 - | ((frc_sr & 0x1) << 31) - | ((sr_ie & 0x1) << 30) - | ((dll_rst_dis & 0x1) << 29) - | ((dqs_cfg & 0x3) << 26) - | ((odt_cfg & 0x3) << 21) - | ((num_pr & 0xf) << 12) - | ((obc_cfg & 0x1) << 6) - | ((ap_en & 0x1) << 5) - | ((d_init & 0x1) << 4) - | ((rcw_en & 0x1) << 2) - | ((md_en & 0x1) << 0) - ); - debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); -} - -/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ - unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ - -#if defined(CONFIG_FSL_DDR3) - unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ - unsigned int srt = 0; /* self-refresh temerature, normal range */ - unsigned int asr = 0; /* auto self-refresh disable */ - unsigned int cwl = compute_cas_write_latency() - 5; - unsigned int pasr = 0; /* partial array self refresh disable */ - - if (popts->rtt_override) - rtt_wr = popts->rtt_wr_override_value; - - esdmode2 = (0 - | ((rtt_wr & 0x3) << 9) - | ((srt & 0x1) << 7) - | ((asr & 0x1) << 6) - | ((cwl & 0x7) << 3) - | ((pasr & 0x7) << 0)); -#endif - ddr->ddr_sdram_mode_2 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); -} - -/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ -static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - unsigned int refint; /* Refresh interval */ - unsigned int bstopre; /* Precharge interval */ - - refint = picos_to_mclk(common_dimm->refresh_rate_ps); - - bstopre = popts->bstopre; - - /* refint field used 0x3FFF in earlier controllers */ - ddr->ddr_sdram_interval = (0 - | ((refint & 0xFFFF) << 16) - | ((bstopre & 0x3FFF) << 0) - ); - debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); -} - -#if defined(CONFIG_FSL_DDR3) -/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) -{ - unsigned short esdmode; /* Extended SDRAM mode */ - unsigned short sdmode; /* SDRAM mode */ - - /* Mode Register - MR1 */ - unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ - unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ - unsigned int rtt; - unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ - unsigned int al = 0; /* Posted CAS# additive latency (AL) */ - unsigned int dic = 1; /* Output driver impedance, 34ohm */ - unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), - 1=Disable (Test/Debug) */ - - /* Mode Register - MR0 */ - unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ - unsigned int wr; /* Write Recovery */ - unsigned int dll_rst; /* DLL Reset */ - unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ - /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ - unsigned int bt; - unsigned int bl; /* BL: Burst Length */ - - unsigned int wr_mclk; - - const unsigned int mclk_ps = get_memory_clk_period_ps(); - - rtt = fsl_ddr_get_rtt(); - if (popts->rtt_override) - rtt = popts->rtt_override_value; - - if (additive_latency == (cas_latency - 1)) - al = 1; - if (additive_latency == (cas_latency - 2)) - al = 2; - - /* - * The esdmode value will also be used for writing - * MR1 during write leveling for DDR3, although the - * bits specifically related to the write leveling - * scheme will be handled automatically by the DDR - * controller. so we set the wrlvl_en = 0 here. - */ - esdmode = (0 - | ((qoff & 0x1) << 12) - | ((tdqs_en & 0x1) << 11) - | ((rtt & 0x4) << 7) /* rtt field is split */ - | ((wrlvl_en & 0x1) << 7) - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((dic & 0x2) << 4) /* DIC field is split */ - | ((al & 0x3) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ - | ((dic & 0x1) << 1) /* DIC field is split */ - | ((dll_en & 0x1) << 0) - ); - - /* - * DLL control for precharge PD - * 0=slow exit DLL off (tXPDLL) - * 1=fast exit DLL on (tXP) - */ - dll_on = 1; - wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps; - if (wr_mclk >= 12) - wr = 6; - else if (wr_mclk >= 9) - wr = 5; - else - wr = wr_mclk - 4; - dll_rst = 0; /* dll no reset */ - mode = 0; /* normal mode */ - - /* look up table to get the cas latency bits */ - if (cas_latency >= 5 && cas_latency <= 11) { - unsigned char cas_latency_table[7] = { - 0x2, /* 5 clocks */ - 0x4, /* 6 clocks */ - 0x6, /* 7 clocks */ - 0x8, /* 8 clocks */ - 0xa, /* 9 clocks */ - 0xc, /* 10 clocks */ - 0xe /* 11 clocks */ - }; - caslat = cas_latency_table[cas_latency - 5]; - } - bt = 0; /* Nibble sequential */ - - switch (popts->burst_length) { - case DDR_BL8: - bl = 0; - break; - case DDR_OTF: - bl = 1; - break; - case DDR_BC4: - bl = 2; - break; - default: - printf("Error: invalid burst length of %u specified. " - " Defaulting to on-the-fly BC4 or BL8 beats.\n", - popts->burst_length); - bl = 1; - break; - } - - sdmode = (0 - | ((dll_on & 0x1) << 12) - | ((wr & 0x7) << 9) - | ((dll_rst & 0x1) << 8) - | ((mode & 0x1) << 7) - | (((caslat >> 1) & 0x7) << 4) - | ((bt & 0x1) << 3) - | ((bl & 0x3) << 0) - ); - - ddr->ddr_sdram_mode = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - - debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); -} - -#else /* !CONFIG_FSL_DDR3 */ - -/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) -{ - unsigned short esdmode; /* Extended SDRAM mode */ - unsigned short sdmode; /* SDRAM mode */ - - /* - * FIXME: This ought to be pre-calculated in a - * technology-specific routine, - * e.g. compute_DDR2_mode_register(), and then the - * sdmode and esdmode passed in as part of common_dimm. - */ - - /* Extended Mode Register */ - unsigned int mrs = 0; /* Mode Register Set */ - unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ - unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ - unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ - unsigned int ocd = 0; /* 0x0=OCD not supported, - 0x7=OCD default state */ - unsigned int rtt; - unsigned int al; /* Posted CAS# additive latency (AL) */ - unsigned int ods = 0; /* Output Drive Strength: - 0 = Full strength (18ohm) - 1 = Reduced strength (4ohm) */ - unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), - 1=Disable (Test/Debug) */ - - /* Mode Register (MR) */ - unsigned int mr; /* Mode Register Definition */ - unsigned int pd; /* Power-Down Mode */ - unsigned int wr; /* Write Recovery */ - unsigned int dll_res; /* DLL Reset */ - unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat = 0;/* CAS# latency */ - /* BT: Burst Type (0=Sequential, 1=Interleaved) */ - unsigned int bt; - unsigned int bl; /* BL: Burst Length */ - -#if defined(CONFIG_FSL_DDR2) - const unsigned int mclk_ps = get_memory_clk_period_ps(); -#endif - - rtt = fsl_ddr_get_rtt(); - - al = additive_latency; - - esdmode = (0 - | ((mrs & 0x3) << 14) - | ((outputs & 0x1) << 12) - | ((rdqs_en & 0x1) << 11) - | ((dqs_en & 0x1) << 10) - | ((ocd & 0x7) << 7) - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((al & 0x7) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ - | ((ods & 0x1) << 1) - | ((dll_en & 0x1) << 0) - ); - - mr = 0; /* FIXME: CHECKME */ - - /* - * 0 = Fast Exit (Normal) - * 1 = Slow Exit (Low Power) - */ - pd = 0; - -#if defined(CONFIG_FSL_DDR1) - wr = 0; /* Historical */ -#elif defined(CONFIG_FSL_DDR2) - wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1; -#endif - dll_res = 0; - mode = 0; - -#if defined(CONFIG_FSL_DDR1) - if (1 <= cas_latency && cas_latency <= 4) { - unsigned char mode_caslat_table[4] = { - 0x5, /* 1.5 clocks */ - 0x2, /* 2.0 clocks */ - 0x6, /* 2.5 clocks */ - 0x3 /* 3.0 clocks */ - }; - caslat = mode_caslat_table[cas_latency - 1]; - } else { - printf("Warning: unknown cas_latency %d\n", cas_latency); - } -#elif defined(CONFIG_FSL_DDR2) - caslat = cas_latency; -#endif - bt = 0; - - switch (popts->burst_length) { - case DDR_BL4: - bl = 2; - break; - case DDR_BL8: - bl = 3; - break; - default: - printf("Error: invalid burst length of %u specified. " - " Defaulting to 4 beats.\n", - popts->burst_length); - bl = 2; - break; - } - - sdmode = (0 - | ((mr & 0x3) << 14) - | ((pd & 0x1) << 12) - | ((wr & 0x7) << 9) - | ((dll_res & 0x1) << 8) - | ((mode & 0x1) << 7) - | ((caslat & 0x7) << 4) - | ((bt & 0x1) << 3) - | ((bl & 0x7) << 0) - ); - - ddr->ddr_sdram_mode = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); -} -#endif - -/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ -static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_value; /* Initialization value */ - - init_value = 0xDEADBEEF; - ddr->ddr_data_init = init_value; -} - -/* - * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) - * The old controller on the 8540/60 doesn't have this register. - * Hope it's OK to set it (to 0) anyway. - */ -static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned int clk_adjust; /* Clock adjust */ - - clk_adjust = popts->clk_adjust; - ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; -} - -/* DDR Initialization Address (DDR_INIT_ADDR) */ -static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_addr = 0; /* Initialization address */ - - ddr->ddr_init_addr = init_addr; -} - -/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ -static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int uia = 0; /* Use initialization address */ - unsigned int init_ext_addr = 0; /* Initialization address */ - - ddr->ddr_init_ext_addr = (0 - | ((uia & 0x1) << 31) - | (init_ext_addr & 0xF) - ); -} - -/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ -static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ - unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ - unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ - unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ - unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ - -#if defined(CONFIG_FSL_DDR3) - /* We need set BL/2 + 4 for BC4 or OTF */ - rrt = 4; /* BL/2 + 4 clocks */ - wwt = 4; /* BL/2 + 4 clocks */ - dll_lock = 1; /* tDLLK = 512 clocks from spec */ -#endif - ddr->timing_cfg_4 = (0 - | ((rwt & 0xf) << 28) - | ((wrt & 0xf) << 24) - | ((rrt & 0xf) << 20) - | ((wwt & 0xf) << 16) - | (dll_lock & 0x3) - ); - debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); -} - -/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ -static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int rodt_on = 0; /* Read to ODT on */ - unsigned int rodt_off = 0; /* Read to ODT off */ - unsigned int wodt_on = 0; /* Write to ODT on */ - unsigned int wodt_off = 0; /* Write to ODT off */ - -#if defined(CONFIG_FSL_DDR3) - rodt_on = 3; /* 2 clocks */ - rodt_off = 4; /* 4 clocks */ - wodt_on = 2; /* 1 clocks */ - wodt_off = 4; /* 4 clocks */ -#endif - - ddr->timing_cfg_5 = (0 - | ((rodt_on & 0x1f) << 24) - | ((rodt_off & 0x7) << 20) - | ((wodt_on & 0x1f) << 12) - | ((wodt_off & 0x7) << 8) - ); - debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); -} - -/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ -static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) -{ - unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ - /* Normal Operation Full Calibration Time (tZQoper) */ - unsigned int zqoper = 0; - /* Normal Operation Short Calibration Time (tZQCS) */ - unsigned int zqcs = 0; - - if (zq_en) { - zqinit = 9; /* 512 clocks */ - zqoper = 8; /* 256 clocks */ - zqcs = 6; /* 64 clocks */ - } - - ddr->ddr_zq_cntl = (0 - | ((zq_en & 0x1) << 31) - | ((zqinit & 0xF) << 24) - | ((zqoper & 0xF) << 16) - | ((zqcs & 0xF) << 8) - ); -} - -/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ -static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, - const memctl_options_t *popts) -{ - /* - * First DQS pulse rising edge after margining mode - * is programmed (tWL_MRD) - */ - unsigned int wrlvl_mrd = 0; - /* ODT delay after margining mode is programmed (tWL_ODTEN) */ - unsigned int wrlvl_odten = 0; - /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ - unsigned int wrlvl_dqsen = 0; - /* WRLVL_SMPL: Write leveling sample time */ - unsigned int wrlvl_smpl = 0; - /* WRLVL_WLR: Write leveling repeition time */ - unsigned int wrlvl_wlr = 0; - /* WRLVL_START: Write leveling start time */ - unsigned int wrlvl_start = 0; - - /* suggest enable write leveling for DDR3 due to fly-by topology */ - if (wrlvl_en) { - /* tWL_MRD min = 40 nCK, we set it 64 */ - wrlvl_mrd = 0x6; - /* tWL_ODTEN 128 */ - wrlvl_odten = 0x7; - /* tWL_DQSEN min = 25 nCK, we set it 32 */ - wrlvl_dqsen = 0x5; - /* - * Write leveling sample time at least need 6 clocks - * higher than tWLO to allow enough time for progagation - * delay and sampling the prime data bits. - */ - wrlvl_smpl = 0xf; - /* - * Write leveling repetition time - * at least tWLO + 6 clocks clocks - * we set it 32 - */ - wrlvl_wlr = 0x5; - /* - * Write leveling start time - * The value use for the DQS_ADJUST for the first sample - * when write leveling is enabled. - */ - wrlvl_start = 0x8; - /* - * Override the write leveling sample and start time - * according to specific board - */ - if (popts->wrlvl_override) { - wrlvl_smpl = popts->wrlvl_sample; - wrlvl_start = popts->wrlvl_start; - } - } - - ddr->ddr_wrlvl_cntl = (0 - | ((wrlvl_en & 0x1) << 31) - | ((wrlvl_mrd & 0x7) << 24) - | ((wrlvl_odten & 0x7) << 20) - | ((wrlvl_dqsen & 0x7) << 16) - | ((wrlvl_smpl & 0xf) << 12) - | ((wrlvl_wlr & 0x7) << 8) - | ((wrlvl_start & 0x1F) << 0) - ); -} - -/* DDR Self Refresh Counter (DDR_SR_CNTR) */ -static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) -{ - /* Self Refresh Idle Threshold */ - ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; -} - -/* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */ -static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */ - unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */ - unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */ - unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */ - unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */ - unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */ - unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */ - unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */ - - ddr->ddr_sdram_rcw_1 = (0 - | ((rcw0 & 0xF) << 28) - | ((rcw1 & 0xF) << 24) - | ((rcw2 & 0xF) << 20) - | ((rcw3 & 0xF) << 16) - | ((rcw4 & 0xF) << 12) - | ((rcw5 & 0xF) << 8) - | ((rcw6 & 0xF) << 4) - | ((rcw7 & 0xF) << 0) - ); -} - -/* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */ -static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */ - unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */ - unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */ - unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */ - unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */ - unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */ - unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */ - unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */ - - ddr->ddr_sdram_rcw_2 = (0 - | ((rcw8 & 0xF) << 28) - | ((rcw9 & 0xF) << 24) - | ((rcw10 & 0xF) << 20) - | ((rcw11 & 0xF) << 16) - | ((rcw12 & 0xF) << 12) - | ((rcw13 & 0xF) << 8) - | ((rcw14 & 0xF) << 4) - | ((rcw15 & 0xF) << 0) - ); -} - -unsigned int -check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int res = 0; - - /* - * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are - * not set at the same time. - */ - if (ddr->ddr_sdram_cfg & 0x10000000 - && ddr->ddr_sdram_cfg & 0x00008000) { - printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " - " should not be set at the same time.\n"); - res++; - } - - return res; -} - -unsigned int -compute_fsl_memctl_config_regs(const memctl_options_t *popts, - fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm, - const dimm_params_t *dimm_params, - unsigned int dbw_cap_adj) -{ - unsigned int i; - unsigned int cas_latency; - unsigned int additive_latency; - unsigned int sr_it; - unsigned int zq_en; - unsigned int wrlvl_en; - - memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); - - if (common_dimm == NULL) { - printf("Error: subset DIMM params struct null pointer\n"); - return 1; - } - - /* - * Process overrides first. - * - * FIXME: somehow add dereated caslat to this - */ - cas_latency = (popts->cas_latency_override) - ? popts->cas_latency_override_value - : common_dimm->lowest_common_SPD_caslat; - - additive_latency = (popts->additive_latency_override) - ? popts->additive_latency_override_value - : common_dimm->additive_latency; - - sr_it = (popts->auto_self_refresh_en) - ? popts->sr_it - : 0; - /* ZQ calibration */ - zq_en = (popts->zq_en) ? 1 : 0; - /* write leveling */ - wrlvl_en = (popts->wrlvl_en) ? 1 : 0; - - /* Chip Select Memory Bounds (CSn_BNDS) */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - unsigned long long ea = 0, sa = 0; - - if (popts->ba_intlv_ctl && (i > 0) && - ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) { - /* Don't set up boundaries for other CS - * other than CS0, if bank interleaving - * is enabled and not CS2+CS3 interleaved. - * But we need to set the ODT_RD_CFG and - * ODT_WR_CFG for CS1_CONFIG here. - */ - set_csn_config(i, ddr, popts, dimm_params); - break; - } - - if (dimm_params[i/2].n_ranks == 0) { - debug("Skipping setup of CS%u " - "because n_ranks on DIMM %u is 0\n", i, i/2); - continue; - } - if (popts->memctl_interleaving && popts->ba_intlv_ctl) { - /* - * This works superbank 2CS - * There are 2 memory controllers configured - * identically, memory is interleaved between them, - * and each controller uses rank interleaving within - * itself. Therefore the starting and ending address - * on each controller is twice the amount present on - * each controller. - */ - unsigned long long rank_density - = dimm_params[0].capacity; - ea = (2 * (rank_density >> dbw_cap_adj)) - 1; - } - else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) { - /* - * If memory interleaving between controllers is NOT - * enabled, the starting address for each memory - * controller is distinct. However, because rank - * interleaving is enabled, the starting and ending - * addresses of the total memory on that memory - * controller needs to be programmed into its - * respective CS0_BNDS. - */ - unsigned long long rank_density - = dimm_params[i/2].rank_density; - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS - * needs to be set. - */ - sa = common_dimm->base_address; - ea = sa + (4 * (rank_density >> dbw_cap_adj))-1; - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS - * and CS2_CNDS need to be set. - */ - if (!(i&1)) { - sa = dimm_params[i/2].base_address; - ea = sa + (i * (rank_density >> - dbw_cap_adj)) - 1; - } - break; - case FSL_DDR_CS0_CS1: - /* CS0+CS1 interleaving, CS0_CNDS needs - * to be set - */ - sa = common_dimm->base_address; - ea = sa + (2 * (rank_density >> dbw_cap_adj))-1; - break; - case FSL_DDR_CS2_CS3: - /* CS2+CS3 interleaving*/ - if (i == 2) { - sa = dimm_params[i/2].base_address; - ea = sa + (2 * (rank_density >> - dbw_cap_adj)) - 1; - } - break; - default: /* No bank(chip-select) interleaving */ - break; - } - } - else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) { - /* - * Only the rank on CS0 of each memory controller may - * be used if memory controller interleaving is used - * without rank interleaving within each memory - * controller. However, the ending address programmed - * into each CS0 must be the sum of the amount of - * memory in the two CS0 ranks. - */ - if (i == 0) { - unsigned long long rank_density - = dimm_params[0].rank_density; - ea = (2 * (rank_density >> dbw_cap_adj)) - 1; - } - - } - else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) { - /* - * No rank interleaving and no memory controller - * interleaving. - */ - unsigned long long rank_density - = dimm_params[i/2].rank_density; - sa = dimm_params[i/2].base_address; - ea = sa + (rank_density >> dbw_cap_adj) - 1; - if (i&1) { - if ((dimm_params[i/2].n_ranks == 1)) { - /* Odd chip select, single-rank dimm */ - sa = 0; - ea = 0; - } else { - /* Odd chip select, dual-rank DIMM */ - sa += rank_density >> dbw_cap_adj; - ea += rank_density >> dbw_cap_adj; - } - } - } - - sa >>= 24; - ea >>= 24; - - ddr->cs[i].bnds = (0 - | ((sa & 0xFFF) << 16) /* starting address MSB */ - | ((ea & 0xFFF) << 0) /* ending address MSB */ - ); - - debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); - set_csn_config(i, ddr, popts, dimm_params); - set_csn_config_2(i, ddr); - } - -#if !defined(CONFIG_FSL_DDR1) - set_timing_cfg_0(ddr); -#endif - - set_timing_cfg_3(ddr, common_dimm, cas_latency); - set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_2(ddr, popts, common_dimm, - cas_latency, additive_latency); - - set_ddr_sdram_cfg(ddr, popts, common_dimm); - - set_ddr_sdram_cfg_2(ddr, popts); - set_ddr_sdram_mode(ddr, popts, common_dimm, - cas_latency, additive_latency); - set_ddr_sdram_mode_2(ddr, popts); - set_ddr_sdram_interval(ddr, popts, common_dimm); - set_ddr_data_init(ddr); - set_ddr_sdram_clk_cntl(ddr, popts); - set_ddr_init_addr(ddr); - set_ddr_init_ext_addr(ddr); - set_timing_cfg_4(ddr); - set_timing_cfg_5(ddr); - - set_ddr_zq_cntl(ddr, zq_en); - set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); - - set_ddr_sr_cntr(ddr, sr_it); - - set_ddr_sdram_rcw_1(ddr); - set_ddr_sdram_rcw_2(ddr); - - return check_fsl_memctl_config_regs(ddr); -} diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c deleted file mode 100644 index 3dcd33ddf2..0000000000 --- a/cpu/mpc8xxx/ddr/options.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include "ddr.h" - -/* Board-specific functions defined in each board's ddr.c */ -extern void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num); - -unsigned int populate_memctl_options(int all_DIMMs_registered, - memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - unsigned int i; - const char *p; - - /* Chip select options. */ - - /* Pick chip-select local options. */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */ - - /* only for single CS? */ - popts->cs_local_opts[i].odt_rd_cfg = 0; - - popts->cs_local_opts[i].odt_wr_cfg = 1; - popts->cs_local_opts[i].auto_precharge = 0; - } - - /* Pick interleaving mode. */ - - /* - * 0 = no interleaving - * 1 = interleaving between 2 controllers - */ - popts->memctl_interleaving = 0; - - /* - * 0 = cacheline - * 1 = page - * 2 = (logical) bank - * 3 = superbank (only if CS interleaving is enabled) - */ - popts->memctl_interleaving_mode = 0; - - /* - * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl - * 1: page: bit to the left of the column bits selects the memctl - * 2: bank: bit to the left of the bank bits selects the memctl - * 3: superbank: bit to the left of the chip select selects the memctl - * - * NOTE: ba_intlv (rank interleaving) is independent of memory - * controller interleaving; it is only within a memory controller. - * Must use superbank interleaving if rank interleaving is used and - * memory controller interleaving is enabled. - */ - - /* - * 0 = no - * 0x40 = CS0,CS1 - * 0x20 = CS2,CS3 - * 0x60 = CS0,CS1 + CS2,CS3 - * 0x04 = CS0,CS1,CS2,CS3 - */ - popts->ba_intlv_ctl = 0; - - /* Memory Organization Parameters */ - popts->registered_dimm_en = all_DIMMs_registered; - - /* Operational Mode Paramters */ - - /* Pick ECC modes */ -#ifdef CONFIG_DDR_ECC - popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */ -#else - popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */ -#endif - popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ - - /* - * Choose DQS config - * 0 for DDR1 - * 1 for DDR2 - */ -#if defined(CONFIG_FSL_DDR1) - popts->DQS_config = 0; -#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) - popts->DQS_config = 1; -#endif - - /* Choose self-refresh during sleep. */ - popts->self_refresh_in_sleep = 1; - - /* Choose dynamic power management mode. */ - popts->dynamic_power = 0; - - /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ - popts->data_bus_width = 0; - - /* Choose burst length. */ -#if defined(CONFIG_FSL_DDR3) - popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ - popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ -#else - popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ -#endif - - /* Choose ddr controller address mirror mode */ -#if defined(CONFIG_FSL_DDR3) - popts->mirrored_dimm = pdimm[0].mirrored_dimm; -#endif - - /* Global Timing Parameters. */ - debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); - - /* Pick a caslat override. */ - popts->cas_latency_override = 0; - popts->cas_latency_override_value = 3; - if (popts->cas_latency_override) { - debug("using caslat override value = %u\n", - popts->cas_latency_override_value); - } - - /* Decide whether to use the computed derated latency */ - popts->use_derated_caslat = 0; - - /* Choose an additive latency. */ - popts->additive_latency_override = 0; - popts->additive_latency_override_value = 3; - if (popts->additive_latency_override) { - debug("using additive latency override value = %u\n", - popts->additive_latency_override_value); - } - - /* - * 2T_EN setting - * - * Factors to consider for 2T_EN: - * - number of DIMMs installed - * - number of components, number of active ranks - * - how much time you want to spend playing around - */ - popts->twoT_en = 0; - popts->threeT_en = 0; - - /* - * BSTTOPRE precharge interval - * - * Set this to 0 for global auto precharge - * - * FIXME: Should this be configured in picoseconds? - * Why it should be in ps: better understanding of this - * relative to actual DRAM timing parameters such as tRAS. - * e.g. tRAS(min) = 40 ns - */ - popts->bstopre = 0x100; - - /* Minimum CKE pulse width -- tCKE(MIN) */ - popts->tCKE_clock_pulse_width_ps - = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR); - - /* - * Window for four activates -- tFAW - * - * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only - * FIXME: varies depending upon number of column addresses or data - * FIXME: width, was considering looking at pdimm->primary_sdram_width - */ -#if defined(CONFIG_FSL_DDR1) - popts->tFAW_window_four_activates_ps = mclk_to_picos(1); - -#elif defined(CONFIG_FSL_DDR2) - /* - * x4/x8; some datasheets have 35000 - * x16 wide columns only? Use 50000? - */ - popts->tFAW_window_four_activates_ps = 37500; - -#elif defined(CONFIG_FSL_DDR3) - popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps; -#endif - popts->zq_en = 0; - popts->wrlvl_en = 0; -#if defined(CONFIG_FSL_DDR3) - /* - * due to ddr3 dimm is fly-by topology - * we suggest to enable write leveling to - * meet the tQDSS under different loading. - */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 0; -#endif - - /* - * Check interleaving configuration from environment. - * Please refer to doc/README.fsl-ddr for the detail. - * - * If memory controller interleaving is enabled, then the data - * bus widths must be programmed identically for the 2 memory - * controllers. - * - * XXX: Attempt to set both controllers to the same chip select - * interleaving mode. It will do a best effort to get the - * requested ranks interleaved together such that the result - * should be a subset of the requested configuration. - */ -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) - if ((p = getenv("memctl_intlv_ctl")) != NULL) { - if (pdimm[0].n_ranks == 0) { - printf("There is no rank on CS0. Because only rank on " - "CS0 and ranks chip-select interleaved with CS0" - " are controller interleaved, force non memory " - "controller interleaving\n"); - popts->memctl_interleaving = 0; - } else { - popts->memctl_interleaving = 1; - if (strcmp(p, "cacheline") == 0) - popts->memctl_interleaving_mode = - FSL_DDR_CACHE_LINE_INTERLEAVING; - else if (strcmp(p, "page") == 0) - popts->memctl_interleaving_mode = - FSL_DDR_PAGE_INTERLEAVING; - else if (strcmp(p, "bank") == 0) - popts->memctl_interleaving_mode = - FSL_DDR_BANK_INTERLEAVING; - else if (strcmp(p, "superbank") == 0) - popts->memctl_interleaving_mode = - FSL_DDR_SUPERBANK_INTERLEAVING; - else - popts->memctl_interleaving_mode = - simple_strtoul(p, NULL, 0); - } - } -#endif - - if( ((p = getenv("ba_intlv_ctl")) != NULL) && - (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { - if (strcmp(p, "cs0_cs1") == 0) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; - else if (strcmp(p, "cs2_cs3") == 0) - popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; - else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; - else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; - else - popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0); - - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - case FSL_DDR_CS0_CS1: - if (pdimm[0].n_ranks != 2) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for " - "CS0+CS1, force non-interleaving!\n"); - } - break; - case FSL_DDR_CS2_CS3: - if (pdimm[1].n_ranks !=2){ - popts->ba_intlv_ctl = 0; - printf("Not enough bank(CS) for CS2+CS3, " - "force non-interleaving!\n"); - } - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(CS) for CS0+CS1 or " - "CS2+CS3, force non-interleaving!\n"); - } - break; - default: - popts->ba_intlv_ctl = 0; - break; - } - } - - fsl_ddr_board_options(popts, pdimm, ctrl_num); - - return 0; -} diff --git a/cpu/mpc8xxx/fdt.c b/cpu/mpc8xxx/fdt.c deleted file mode 100644 index 3a9b5841b6..0000000000 --- a/cpu/mpc8xxx/fdt.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c. - * Basically this file contains cpu specific common code for 85xx/86xx - * processors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -void ft_fixup_num_cores(void *blob) { - int off, num_cores, del_cores; - - del_cores = 0; - num_cores = cpu_numcores(); - - off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); - while (off != -FDT_ERR_NOTFOUND) { - u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - - /* if we find a cpu node outside of what we expect delete it - * and reset the offset back to the start since we can't - * trust the offsets anymore - */ - if (*reg > num_cores-1) { - fdt_del_node(blob, off); - del_cores++; - off = -1; - } - off = fdt_node_offset_by_prop_value(blob, off, - "device_type", "cpu", 4); - } - debug ("%x core system found\n", num_cores); - debug ("deleted %d extra core entry entries from device tree\n", - del_cores); -} diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c deleted file mode 100644 index d53781b62b..0000000000 --- a/cpu/mpc8xxx/pci_cfg.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -struct pci_info { - u16 cfg; -}; - -/* The cfg field is a bit mask in which each bit represents the value of - * cfg_IO_ports[] signal and the bit is set if the interface would be - * enabled based on the value of cfg_IO_ports[] signal - * - * On MPC86xx/PQ3 based systems: - * we extract cfg_IO_ports from GUTS register PORDEVSR - * - * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems - * without PCIe) - */ - -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, -}; -#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, -}; -#elif defined(CONFIG_MPC8536) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 5) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8544) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | - (1 << 6) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 6) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8548) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI_1] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCI_2] = { - .cfg = 0, - }, - /* PCI_2 is always host and we dont use iosel to determine enable/disable */ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 3) | (1 << 4) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8568) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 3) | (1 << 4) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8569) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | - (1 << 8) | (1 << 0xc) | (1 << 0xf), - }, -}; -#elif defined(CONFIG_MPC8572) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 7) | - (1 << 0xb) | (1 << 0xc) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 3) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8610) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI_1] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 1) | (1 << 4), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 0) | (1 << 4), - }, -}; -#elif defined(CONFIG_MPC8641) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | - (1 << 7) | (1 << 0xe) | (1 << 0xf), - }, -}; -#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 0xe), - }, -}; -#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | - (1 << 0xd) | (1 << 0xe) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 2) | (1 << 0xe), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 2) | (1 << 4), - }, -}; -#elif defined(CONFIG_FSL_CORENET) -#else -#error Need to define pci_config_info for processor -#endif - -#ifndef CONFIG_FSL_CORENET -int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) -{ - return ((1 << io_sel) & pci_config_info[trgt].cfg); -} -#endif diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile deleted file mode 100644 index 75f30b43a8..0000000000 --- a/cpu/nios2/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).a - -START = start.o -SOBJS = exceptions.o -COBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c deleted file mode 100644 index 483b249cd5..0000000000 --- a/cpu/nios2/epcs.c +++ /dev/null @@ -1,729 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CONFIG_SYS_NIOS_EPCSBASE) -#include -#include -#include -#include - - -/*-----------------------------------------------------------------------*/ -#define SHORT_HELP\ - "epcs - read/write Cyclone EPCS configuration device.\n" - -#define LONG_HELP\ - "\n"\ - "epcs erase start [end]\n"\ - " - erase sector start or sectors start through end.\n"\ - "epcs info\n"\ - " - display EPCS device information.\n"\ - "epcs protect on | off\n"\ - " - turn device protection on or off.\n"\ - "epcs read addr offset count\n"\ - " - read count bytes from offset to addr.\n"\ - "epcs write addr offset count\n"\ - " - write count bytes to offset from addr.\n"\ - "epcs verify addr offset count\n"\ - " - verify count bytes at offset from addr." - - -/*-----------------------------------------------------------------------*/ -/* Operation codes for serial configuration devices - */ -#define EPCS_WRITE_ENA 0x06 /* Write enable */ -#define EPCS_WRITE_DIS 0x04 /* Write disable */ -#define EPCS_READ_STAT 0x05 /* Read status */ -#define EPCS_READ_BYTES 0x03 /* Read bytes */ -#define EPCS_READ_ID 0xab /* Read silicon id */ -#define EPCS_WRITE_STAT 0x01 /* Write status */ -#define EPCS_WRITE_BYTES 0x02 /* Write bytes */ -#define EPCS_ERASE_BULK 0xc7 /* Erase entire device */ -#define EPCS_ERASE_SECT 0xd8 /* Erase sector */ - -/* Device status register bits - */ -#define EPCS_STATUS_WIP (1<<0) /* Write in progress */ -#define EPCS_STATUS_WEL (1<<1) /* Write enable latch */ - -/* Misc - */ -#define EPCS_TIMEOUT 100 /* 100 msec timeout */ - -static nios_spi_t *epcs = (nios_spi_t *)CONFIG_SYS_NIOS_EPCSBASE; - -/*********************************************************************** - * Device access - ***********************************************************************/ -static int epcs_cs (int assert) -{ - ulong start; - unsigned tmp; - - - if (assert) { - tmp = readl (&epcs->control); - writel (&epcs->control, tmp | NIOS_SPI_SSO); - } else { - /* Let all bits shift out */ - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - tmp = readl (&epcs->control); - writel (&epcs->control, tmp & ~NIOS_SPI_SSO); - } - return (0); -} - -static int epcs_tx (unsigned char c) -{ - ulong start; - - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - writel (&epcs->txdata, c); - return (0); -} - -static int epcs_rx (void) -{ - ulong start; - - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - return (readl (&epcs->rxdata)); -} - -static unsigned char bitrev[] = { - 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, - 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f -}; - -static unsigned char epcs_bitrev (unsigned char c) -{ - unsigned char val; - - val = bitrev[c>>4]; - val |= bitrev[c & 0x0f]<<4; - return (val); -} - -static void epcs_rcv (unsigned char *dst, int len) -{ - while (len--) { - epcs_tx (0); - *dst++ = epcs_rx (); - } -} - -static void epcs_rrcv (unsigned char *dst, int len) -{ - while (len--) { - epcs_tx (0); - *dst++ = epcs_bitrev (epcs_rx ()); - } -} - -static void epcs_snd (unsigned char *src, int len) -{ - while (len--) { - epcs_tx (*src++); - epcs_rx (); - } -} - -static void epcs_rsnd (unsigned char *src, int len) -{ - while (len--) { - epcs_tx (epcs_bitrev (*src++)); - epcs_rx (); - } -} - -static void epcs_wr_enable (void) -{ - epcs_cs (1); - epcs_tx (EPCS_WRITE_ENA); - epcs_rx (); - epcs_cs (0); -} - -static unsigned char epcs_status_rd (void) -{ - unsigned char status; - - epcs_cs (1); - epcs_tx (EPCS_READ_STAT); - epcs_rx (); - epcs_tx (0); - status = epcs_rx (); - epcs_cs (0); - return (status); -} - -static void epcs_status_wr (unsigned char status) -{ - epcs_wr_enable (); - epcs_cs (1); - epcs_tx (EPCS_WRITE_STAT); - epcs_rx (); - epcs_tx (status); - epcs_rx (); - epcs_cs (0); - return; -} - -/*********************************************************************** - * Device information - ***********************************************************************/ - -static struct epcs_devinfo_t devinfo[] = { - { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, - { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, - { 0, 0, 0, 0, 0, 0 } -}; - -int epcs_reset (void) -{ - /* When booting from an epcs controller, the epcs bootrom - * code may leave the slave select in an asserted state. - * This causes two problems: (1) The initial epcs access - * will fail -- not a big deal, and (2) a software reset - * will cause the bootrom code to hang since it does not - * ensure the select is negated prior to first access -- a - * big deal. Here we just negate chip select and everything - * gets better :-) - */ - epcs_cs (0); /* Negate chip select */ - return (0); -} - -epcs_devinfo_t *epcs_dev_find (void) -{ - unsigned char buf[4]; - unsigned char id; - int i; - struct epcs_devinfo_t *dev = NULL; - - /* Read silicon id requires 3 "dummy bytes" before it's put - * on the wire. - */ - buf[0] = EPCS_READ_ID; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rcv (buf,1); - if (epcs_cs (0) == -1) - return (NULL); - id = buf[0]; - - /* Find the info struct */ - i = 0; - while (devinfo[i].name) { - if (id == devinfo[i].id) { - dev = &devinfo[i]; - break; - } - i++; - } - - return (dev); -} - -/*********************************************************************** - * Misc Utilities - ***********************************************************************/ -int epcs_cfgsz (void) -{ - int sz = 0; - unsigned char buf[128]; - unsigned char *p; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - /* Read in the first 128 bytes of the device */ - buf[0] = EPCS_READ_BYTES; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rrcv (buf, sizeof(buf)); - epcs_cs (0); - - /* Search for the starting 0x6a which is followed by the - * 4-byte 'register' and 4-byte bit-count. - */ - p = buf; - while (p < buf + sizeof(buf)-8) { - if ( *p == 0x6a ) { - /* Point to bit count and extract */ - p += 5; - sz = *p++; - sz |= *p++ << 8; - sz |= *p++ << 16; - sz |= *p++ << 24; - /* Convert to byte count */ - sz += 7; - sz >>= 3; - } else if (*p == 0xff) { - /* 0xff is ok ... just skip */ - p++; - continue; - } else { - /* Not 0xff or 0x6a ... something's not - * right ... report 'unknown' (sz=0). - */ - break; - } - } - return (sz); -} - -int epcs_erase (unsigned start, unsigned end) -{ - unsigned off, sectsz; - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev || (start>end)) - return (-1); - - /* Erase the requested sectors. An address is required - * that lies within the requested sector -- we'll just - * use the first address in the sector. - */ - printf ("epcs erasing sector %d ", start); - if (start != end) - printf ("to %d ", end); - sectsz = (1 << dev->sz_sect); - while (start <= end) { - off = start * sectsz; - start++; - - buf[0] = EPCS_ERASE_SECT; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_wr_enable (); - epcs_cs (1); - epcs_snd (buf,4); - epcs_cs (0); - - printf ("."); /* Some user feedback */ - - /* Wait for erase to complete */ - while (epcs_status_rd() & EPCS_STATUS_WIP) - ; - } - printf (" done.\n"); - return (0); -} - -int epcs_read (ulong addr, ulong off, ulong cnt) -{ - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - buf[0] = EPCS_READ_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rrcv ((unsigned char *)addr, cnt); - epcs_cs (0); - - return (0); -} - -int epcs_write (ulong addr, ulong off, ulong cnt) -{ - ulong wrcnt; - unsigned pgsz; - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - pgsz = (1<sz_page); - while (cnt) { - if (off % pgsz) - wrcnt = pgsz - (off % pgsz); - else - wrcnt = pgsz; - wrcnt = (wrcnt > cnt) ? cnt : wrcnt; - - buf[0] = EPCS_WRITE_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_wr_enable (); - epcs_cs (1); - epcs_snd (buf,4); - epcs_rsnd ((unsigned char *)addr, wrcnt); - epcs_cs (0); - - /* Wait for write to complete */ - while (epcs_status_rd() & EPCS_STATUS_WIP) - ; - - cnt -= wrcnt; - off += wrcnt; - addr += wrcnt; - } - - return (0); -} - -int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err) -{ - ulong rdcnt; - unsigned char buf[256]; - unsigned char *start,*end; - int i; - - start = end = (unsigned char *)addr; - while (cnt) { - rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; - epcs_read ((ulong)buf, off, rdcnt); - for (i=0; isz_sect); - off = sectsz * sect; - end = off + sectsz; - - while (off < end) { - epcs_read ((ulong)buf, off, sizeof(buf)); - for (i=0; i < sizeof(buf); i++) { - if (buf[i] != 0xff) { - *offset = off + i; - return (0); - } - } - off += sizeof(buf); - } - return (1); -} - - -/*********************************************************************** - * Commands - ***********************************************************************/ -static -void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - int i; - unsigned char stat; - unsigned tmp; - int erased; - - /* Basic device info */ - printf ("%s: %d kbytes (%d sectors x %d kbytes," - " %d bytes/page)\n", - dev->name, 1 << (dev->size-10), - dev->num_sects, 1 << (dev->sz_sect-10), - 1 << dev->sz_page ); - - /* Status -- for now protection is all-or-nothing */ - stat = epcs_status_rd(); - printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", - stat, - (stat & EPCS_STATUS_WIP) ? 1 : 0, - (stat & EPCS_STATUS_WEL) ? 1 : 0, - (stat & dev->prot_mask) ? "on" : "off" ); - - /* Configuration */ - tmp = epcs_cfgsz (); - if (tmp) { - printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); - } else { - printf ("config: unknown\n" ); - } - - /* Sector info */ - for (i=0; inum_sects; i++) { - erased = epcs_sect_erased (i, &tmp, dev); - printf (" %d: %06x ", - i, i*(1<sz_sect) ); - if (erased) - printf ("erased\n"); - else - printf ("data @ 0x%06x\n", tmp); - } - - return; -} - -static -void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - unsigned start,end; - - if ((argc < 3) || (argc > 4)) { - printf ("USAGE: epcs erase sect [end]\n"); - return; - } - if ((epcs_status_rd() & dev->prot_mask) != 0) { - printf ( "epcs: device protected.\n"); - return; - } - - start = simple_strtoul (argv[2], NULL, 10); - if (argc > 3) - end = simple_strtoul (argv[3], NULL, 10); - else - end = start; - if ((start >= dev->num_sects) || (start > end)) { - printf ("epcs: invalid sector range: [%d:%d]\n", - start, end ); - return; - } - - epcs_erase (start, end); - - return; -} - -static -void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - unsigned char stat; - - /* For now protection is all-or-nothing to keep things - * simple. The protection bits don't map in a linear - * fashion ... and we would rather protect the bottom - * of the device since it contains the config data and - * leave the top unprotected for app use. But unfortunately - * protection works from top-to-bottom so it does - * really help very much from a software app point-of-view. - */ - if (argc < 3) { - printf ("USAGE: epcs protect on | off\n"); - return; - } - if (!dev) - return; - - /* Protection on/off is just a matter of setting/clearing - * all protection bits in the status register. - */ - stat = epcs_status_rd (); - if (strcmp ("on", argv[2]) == 0) { - stat |= dev->prot_mask; - } else if (strcmp ("off", argv[2]) == 0 ) { - stat &= ~dev->prot_mask; - } else { - printf ("epcs: unknown protection: %s\n", argv[2]); - return; - } - epcs_status_wr (stat); - return; -} - -static -void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - - if (argc < 5) { - printf ("USAGE: epcs read addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n", - addr, off, cnt); - epcs_read (addr, off, cnt); - - return; -} - -static -void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: epcs write addr offset count\n"); - return; - } - if ((epcs_status_rd() & dev->prot_mask) != 0) { - printf ( "epcs: device protected.\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - epcs_write (addr, off, cnt); - if (epcs_verify (addr, off, cnt, &err) != 0) - printf ("epcs: write error at offset %06lx\n", err); - - return; -} - -static -void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: epcs verify addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - if (epcs_verify (addr, off, cnt, &err) != 0) - printf ("epcs: verify error at offset %06lx\n", err); - - return; -} - -/*-----------------------------------------------------------------------*/ -int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int len; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) { - printf ("epcs: device not found.\n"); - return (-1); - } - - if (argc < 2) { - do_epcs_info (dev, argc, argv); - return (0); - } - - len = strlen (argv[1]); - if (strncmp ("info", argv[1], len) == 0) { - do_epcs_info (dev, argc, argv); - } else if (strncmp ("erase", argv[1], len) == 0) { - do_epcs_erase (dev, argc, argv); - } else if (strncmp ("protect", argv[1], len) == 0) { - do_epcs_protect (dev, argc, argv); - } else if (strncmp ("read", argv[1], len) == 0) { - do_epcs_read (dev, argc, argv); - } else if (strncmp ("write", argv[1], len) == 0) { - do_epcs_write (dev, argc, argv); - } else if (strncmp ("verify", argv[1], len) == 0) { - do_epcs_verify (dev, argc, argv); - } else { - printf ("epcs: unknown operation: %s\n", argv[1]); - } - - return (0); -} - -/*-----------------------------------------------------------------------*/ - - -U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP ); - -#endif /* CONFIG_NIOS_EPCS */ diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c deleted file mode 100644 index 1c3566ebf9..0000000000 --- a/cpu/nios2/interrupts.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif - -#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ) -#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation) -#endif - -/****************************************************************************/ - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct irq_action vecs[32]; - -/*************************************************************************/ -volatile ulong timestamp = 0; - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - WATCHDOG_RESET (); - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} - - -/* The board must handle this interrupt if a timer is not - * provided. - */ -#if defined(CONFIG_SYS_NIOS_TMRBASE) -void tmr_isr (void *arg) -{ - nios_timer_t *tmr = (nios_timer_t *)arg; - /* Interrupt is cleared by writing anything to the - * status register. - */ - writel (&tmr->status, 0); - timestamp += CONFIG_SYS_NIOS_TMRMS; -#ifdef CONFIG_STATUS_LED - status_led_tick(timestamp); -#endif -} - -static void tmr_init (void) -{ - nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; - - writel (&tmr->status, 0); - writel (&tmr->control, 0); - writel (&tmr->control, NIOS_TIMER_STOP); - -#if defined(CONFIG_SYS_NIOS_TMRCNT) - writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff); - writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff); -#endif - writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT | - NIOS_TIMER_START ); - irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr); -} - -#endif /* CONFIG_SYS_NIOS_TMRBASE */ - -/*************************************************************************/ -int disable_interrupts (void) -{ - int val = rdctl (CTL_STATUS); - wrctl (CTL_STATUS, val & ~STATUS_IE); - return (val & STATUS_IE); -} - -void enable_interrupts( void ) -{ - int val = rdctl (CTL_STATUS); - wrctl (CTL_STATUS, val | STATUS_IE); -} - -void external_interrupt (struct pt_regs *regs) -{ - unsigned irqs; - struct irq_action *act; - - /* Evaluate only irqs that are both enabled AND pending */ - irqs = rdctl (CTL_IENABLE) & rdctl (CTL_IPENDING); - act = vecs; - - /* Assume (as does the Nios2 HAL) that bit 0 is highest - * priority. NOTE: There is ALWAYS a handler assigned - * (the default if no other). - */ - while (irqs) { - if (irqs & 1) { - act->handler (act->arg); - act->count++; - } - irqs >>=1; - act++; - } -} - -static void def_hdlr (void *arg) -{ - unsigned irqs = rdctl (CTL_IENABLE); - - /* Disable the individual interrupt -- with gratuitous - * warning. - */ - irqs &= ~(1 << (int)arg); - wrctl (CTL_IENABLE, irqs); - printf ("WARNING: Disabling unhandled interrupt: %d\n", - (int)arg); -} - -/*************************************************************************/ -void irq_install_handler (int irq, interrupt_handler_t *hdlr, void *arg) -{ - - int flag; - struct irq_action *act; - unsigned ena = rdctl (CTL_IENABLE); - - if ((irq < 0) || (irq > 31)) - return; - act = &vecs[irq]; - - flag = disable_interrupts (); - if (hdlr) { - act->handler = hdlr; - act->arg = arg; - ena |= (1 << irq); /* enable */ - } else { - act->handler = def_hdlr; - act->arg = (void *)irq; - ena &= ~(1 << irq); /* disable */ - } - wrctl (CTL_IENABLE, ena); - if (flag) enable_interrupts (); -} - - -int interrupt_init (void) -{ - int i; - - /* Assign the default handler to all */ - for (i = 0; i < 32; i++) { - vecs[i].handler = def_hdlr; - vecs[i].arg = (void *)i; - vecs[i].count = 0; - } - -#if defined(CONFIG_SYS_NIOS_TMRBASE) - tmr_init (); -#endif - - enable_interrupts (); - return (0); -} - - -/*************************************************************************/ -#if defined(CONFIG_CMD_IRQ) -int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - struct irq_action *act = vecs; - - printf ("\nInterrupt-Information:\n\n"); - printf ("Nr Routine Arg Count\n"); - printf ("-----------------------------\n"); - - for (i=0; i<32; i++) { - if (act->handler != def_hdlr) { - printf ("%02d %08lx %08lx %d\n", - i, - (ulong)act->handler, - (ulong)act->arg, - act->count); - } - act++; - } - printf ("\n"); - - return (0); -} -#endif diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c deleted file mode 100644 index 6c835af4b1..0000000000 --- a/cpu/nios2/serial.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * YANU Support: - * Copyright 2010, Renato Andreola - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/*------------------------------------------------------------------ - * JTAG acts as the serial port - *-----------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) - -static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE; - -void serial_setbrg( void ){ return; } -int serial_init( void ) { return(0);} - -void serial_putc (char c) -{ - unsigned val; - - while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0) - WATCHDOG_RESET (); - writel (&jtag->data, (unsigned char)c); -} - -void serial_puts (const char *s) -{ - while (*s != 0) - serial_putc (*s++); -} - -int serial_tstc (void) -{ - return ( readl (&jtag->control) & NIOS_JTAG_RRDY); -} - -int serial_getc (void) -{ - int c; - unsigned val; - - while (1) { - WATCHDOG_RESET (); - val = readl (&jtag->data); - if (val & NIOS_JTAG_RVALID) - break; - } - c = val & 0x0ff; - return (c); -} - -#elif defined(CONFIG_CONSOLE_YANU) -/*-----------------------------------------------------------------*/ -/* YANU Imagos serial port */ -/*-----------------------------------------------------------------*/ - -static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; - -#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF assignment*/ - -void serial_setbrg (void) -{ - int n, k; - const unsigned max_uns = 0xFFFFFFFF; - unsigned best_n, best_m, baud; - - /* compute best N and M couple */ - best_n = YANU_MAX_PRESCALER_N; - for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { - if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - (unsigned)CONFIG_BAUDRATE) { - best_n = n; - break; - } - } - for (k = 0;; k++) { - if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k))) - break; - } - best_m = - ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) / - ((unsigned)CONFIG_SYS_CLK_FREQ >> k); - - baud = best_m + best_n * YANU_BAUDE; - writel(&uart->baud, baud); - - return; -} - -#else - -void serial_setbrg (void) -{ - int n, k; - const unsigned max_uns = 0xFFFFFFFF; - unsigned best_n, best_m, baud; - - /* compute best N and M couple */ - best_n = YANU_MAX_PRESCALER_N; - for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { - if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - gd->baudrate) { - best_n = n; - break; - } - } - for (k = 0;; k++) { - if (gd->baudrate <= (max_uns >> (15+n-k))) - break; - } - best_m = - (gd->baudrate * (1 << (15 + n - k))) / - ((unsigned)CONFIG_SYS_CLK_FREQ >> k); - - baud = best_m + best_n * YANU_BAUDE; - writel(&uart->baud, baud); - - return; -} - - -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - -int serial_init (void) -{ - unsigned action,control; - - /* status register cleanup */ - action = YANU_ACTION_RRRDY | - YANU_ACTION_RTRDY | - YANU_ACTION_ROE | - YANU_ACTION_RBRK | - YANU_ACTION_RFE | - YANU_ACTION_RPE | - YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; - - writel(&uart->action, action); - - /* control register cleanup */ - /* no interrupts enabled */ - /* one stop bit */ - /* hardware flow control disabled */ - /* 8 bits */ - control = (0x7 << YANU_CONTROL_BITS_POS); - /* enven parity just to be clean */ - control |= YANU_CONTROL_PAREVEN; - /* we set threshold for fifo */ - control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY; - control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR; - - writel(&uart->control, control); - - /* to set baud rate */ - serial_setbrg(); - - return (0); -} - - -/*----------------------------------------------------------------------- - * YANU CONSOLE - *---------------------------------------------------------------------*/ -void serial_putc (char c) -{ - int tx_chars; - unsigned status; - - if (c == '\n') - serial_putc ('\r'); - - while (1) { - status = readl(&uart->status); - tx_chars = (status>>YANU_TFIFO_CHARS_POS) - & ((1<data, (unsigned char)c); -} - -void serial_puts (const char *s) -{ - while (*s != 0) { - serial_putc (*s++); - } -} - - -int serial_tstc(void) -{ - unsigned status ; - - status = readl(&uart->status); - return (((status >> YANU_RFIFO_CHARS_POS) & - ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); -} - -int serial_getc (void) -{ - while (serial_tstc() == 0) - WATCHDOG_RESET (); - - /* first we pull the char */ - writel(&uart->action, YANU_ACTION_RFIFO_PULL); - - return(readl(&uart->data) & YANU_DATA_CHAR_MASK); -} - -#else /*CONFIG_CONSOLE_YANU*/ - -/*------------------------------------------------------------------ - * UART the serial port - *-----------------------------------------------------------------*/ - -static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; - -#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF - * assignment - */ -void serial_setbrg (void){ return; } -int serial_init (void) { return (0);} - -#else - -void serial_setbrg (void) -{ - unsigned div; - - div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; - writel (&uart->divisor,div); - return; -} - -int serial_init (void) -{ - serial_setbrg (); - return (0); -} - -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - - -/*----------------------------------------------------------------------- - * UART CONSOLE - *---------------------------------------------------------------------*/ -void serial_putc (char c) -{ - if (c == '\n') - serial_putc ('\r'); - while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) - WATCHDOG_RESET (); - writel (&uart->txdata,(unsigned char)c); -} - -void serial_puts (const char *s) -{ - while (*s != 0) { - serial_putc (*s++); - } -} - -int serial_tstc (void) -{ - return (readl (&uart->status) & NIOS_UART_RRDY); -} - -int serial_getc (void) -{ - while (serial_tstc () == 0) - WATCHDOG_RESET (); - return (readl (&uart->rxdata) & 0x00ff ); -} - -#endif /* CONFIG_JTAG_CONSOLE */ diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c deleted file mode 100644 index 5e6dbe3331..0000000000 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * cpu/ppc4xx/40x_spd_sdram.c - * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a - * SDRAM controller. Those are all current 405 PPC's. - * - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com - * - * Based on code by: - * - * Kenneth Johansson ,Ericsson AB. - * kenneth.johansson@etx.ericsson.se - * - * hacked up by bill hunter. fixed so we could run before - * serial_init and console_init. previous version avoided this by - * running out of cache memory during serial/console init, then running - * this code later. - * - * (C) Copyright 2002 - * Jun Gu, Artesyn Technology, jung@artesyncp.com - * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440) - -/* - * Set default values - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif - -#define ONE_BILLION 1000000000 - -#define SDRAM0_CFG_DCE 0x80000000 -#define SDRAM0_CFG_SRE 0x40000000 -#define SDRAM0_CFG_PME 0x20000000 -#define SDRAM0_CFG_MEMCHK 0x10000000 -#define SDRAM0_CFG_REGEN 0x08000000 -#define SDRAM0_CFG_ECCDD 0x00400000 -#define SDRAM0_CFG_EMDULR 0x00200000 -#define SDRAM0_CFG_DRW_SHIFT (31-6) -#define SDRAM0_CFG_BRPF_SHIFT (31-8) - -#define SDRAM0_TR_CASL_SHIFT (31-8) -#define SDRAM0_TR_PTA_SHIFT (31-13) -#define SDRAM0_TR_CTP_SHIFT (31-15) -#define SDRAM0_TR_LDF_SHIFT (31-17) -#define SDRAM0_TR_RFTA_SHIFT (31-29) -#define SDRAM0_TR_RCD_SHIFT (31-31) - -#define SDRAM0_RTR_SHIFT (31-15) -#define SDRAM0_ECCCFG_SHIFT (31-11) - -/* SDRAM0_CFG enable macro */ -#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT ) - -#define SDRAM0_BXCR_SZ_MASK 0x000e0000 -#define SDRAM0_BXCR_AM_MASK 0x0000e000 - -#define SDRAM0_BXCR_SZ_SHIFT (31-14) -#define SDRAM0_BXCR_AM_SHIFT (31-18) - -#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) -#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) - -#ifdef CONFIG_SPDDRAM_SILENT -# define SPD_ERR(x) do { return 0; } while (0) -#else -# define SPD_ERR(x) do { printf(x); return(0); } while (0) -#endif - -#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) - -/* function prototypes */ -int spd_read(uint addr); - - -/* - * This function is reading data from the DIMM module EEPROM over the SPD bus - * and uses that to program the sdram controller. - * - * This works on boards that has the same schematics that the AMCC walnut has. - * - * Input: null for default I2C spd functions or a pointer to a custom function - * returning spd_data. - */ - -long int spd_sdram(int(read_spd)(uint addr)) -{ - int tmp,row,col; - int total_size,bank_size,bank_code; - int ecc_on; - int mode; - int bank_cnt; - - int sdram0_pmit=0x07c00000; -#ifndef CONFIG_405EP /* not on PPC405EP */ - int sdram0_besr0 = -1; - int sdram0_besr1 = -1; - int sdram0_eccesr = -1; -#endif - int sdram0_ecccfg; - - int sdram0_rtr=0; - int sdram0_tr=0; - - int sdram0_b0cr; - int sdram0_b1cr; - int sdram0_b2cr; - int sdram0_b3cr; - - int sdram0_cfg=0; - - int t_rp; - int t_rcd; - int t_ras; - int t_rc; - int min_cas; - - PPC4xx_SYS_INFO sys_info; - unsigned long bus_period_x_10; - - /* - * get the board info - */ - get_sys_info(&sys_info); - bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); - - if (read_spd == 0){ - read_spd=spd_read; - /* - * Make sure I2C controller is initialized - * before continuing. - */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - } - - /* Make shure we are using SDRAM */ - if (read_spd(2) != 0x04) { - SPD_ERR("SDRAM - non SDRAM memory module found\n"); - } - - /* ------------------------------------------------------------------ - * configure memory timing register - * - * data from DIMM: - * 27 IN Row Precharge Time ( t RP) - * 29 MIN RAS to CAS Delay ( t RCD) - * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS - * -------------------------------------------------------------------*/ - - /* - * first figure out which cas latency mode to use - * use the min supported mode - */ - - tmp = read_spd(127) & 0x6; - if (tmp == 0x02) { /* only cas = 2 supported */ - min_cas = 2; -/* t_ck = read_spd(9); */ -/* t_ac = read_spd(10); */ - } else if (tmp == 0x04) { /* only cas = 3 supported */ - min_cas = 3; -/* t_ck = read_spd(9); */ -/* t_ac = read_spd(10); */ - } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ - min_cas = 2; -/* t_ck = read_spd(23); */ -/* t_ac = read_spd(24); */ - } else { - SPD_ERR("SDRAM - unsupported CAS latency \n"); - } - - /* get some timing values, t_rp,t_rcd,t_ras,t_rc - */ - t_rp = read_spd(27); - t_rcd = read_spd(29); - t_ras = read_spd(30); - t_rc = t_ras + t_rp; - - /* The following timing calcs subtract 1 before deviding. - * this has effect of using ceiling instead of floor rounding, - * and also subtracting 1 to convert number to reg value - */ - /* set up CASL */ - sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT; - /* set up PTA */ - sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT; - /* set up CTP */ - tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3; - if (tmp < 1) - tmp = 1; - sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT; - /* set LDF = 2 cycles, reg value = 1 */ - sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT; - /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */ - tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3; - if (tmp < 0) - tmp = 0; - if (tmp > 6) - tmp = 6; - sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT; - /* set RCD = t_rcd/bus_period*/ - sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ; - - - /*------------------------------------------------------------------ - * configure RTR register - * -------------------------------------------------------------------*/ - row = read_spd(3); - col = read_spd(4); - tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */ - switch (tmp) { - case 0x00: - tmp = 15625; - break; - case 0x01: - tmp = 15625 / 4; - break; - case 0x02: - tmp = 15625 / 2; - break; - case 0x03: - tmp = 15625 * 2; - break; - case 0x04: - tmp = 15625 * 4; - break; - case 0x05: - tmp = 15625 * 8; - break; - default: - SPD_ERR("SDRAM - Bad refresh period \n"); - } - /* convert from nsec to bus cycles */ - tmp = (tmp * 10) / bus_period_x_10; - sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; - - /*------------------------------------------------------------------ - * determine the number of banks used - * -------------------------------------------------------------------*/ - /* byte 7:6 is module data width */ - if (read_spd(7) != 0) - SPD_ERR("SDRAM - unsupported module width\n"); - tmp = read_spd(6); - if (tmp < 32) - SPD_ERR("SDRAM - unsupported module width\n"); - else if (tmp < 64) - bank_cnt = 1; /* one bank per sdram side */ - else if (tmp < 73) - bank_cnt = 2; /* need two banks per side */ - else if (tmp < 161) - bank_cnt = 4; /* need four banks per side */ - else - SPD_ERR("SDRAM - unsupported module width\n"); - - /* byte 5 is the module row count (refered to as dimm "sides") */ - tmp = read_spd(5); - if (tmp == 1) - ; - else if (tmp==2) - bank_cnt *= 2; - else if (tmp==4) - bank_cnt *= 4; - else - bank_cnt = 8; /* 8 is an error code */ - - if (bank_cnt > 4) /* we only have 4 banks to work with */ - SPD_ERR("SDRAM - unsupported module rows for this width\n"); - - /* now check for ECC ability of module. We only support ECC - * on 32 bit wide devices with 8 bit ECC. - */ - if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { - sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; - ecc_on = 1; - } else { - sdram0_ecccfg = 0; - ecc_on = 0; - } - - /*------------------------------------------------------------------ - * calculate total size - * -------------------------------------------------------------------*/ - /* calculate total size and do sanity check */ - tmp = read_spd(31); - total_size = 1 << 22; /* total_size = 4MB */ - /* now multiply 4M by the smallest device row density */ - /* note that we don't support asymetric rows */ - while (((tmp & 0x0001) == 0) && (tmp != 0)) { - total_size = total_size << 1; - tmp = tmp >> 1; - } - total_size *= read_spd(5); /* mult by module rows (dimm sides) */ - - /*------------------------------------------------------------------ - * map rows * cols * banks to a mode - * -------------------------------------------------------------------*/ - - switch (row) { - case 11: - switch (col) { - case 8: - mode=4; /* mode 5 */ - break; - case 9: - case 10: - mode=0; /* mode 1 */ - break; - default: - SPD_ERR("SDRAM - unsupported mode\n"); - } - break; - case 12: - switch (col) { - case 8: - mode=3; /* mode 4 */ - break; - case 9: - case 10: - mode=1; /* mode 2 */ - break; - default: - SPD_ERR("SDRAM - unsupported mode\n"); - } - break; - case 13: - switch (col) { - case 8: - mode=5; /* mode 6 */ - break; - case 9: - case 10: - if (read_spd(17) == 2) - mode = 6; /* mode 7 */ - else - mode = 2; /* mode 3 */ - break; - case 11: - mode = 2; /* mode 3 */ - break; - default: - SPD_ERR("SDRAM - unsupported mode\n"); - } - break; - default: - SPD_ERR("SDRAM - unsupported mode\n"); - } - - /*------------------------------------------------------------------ - * using the calculated values, compute the bank - * config register values. - * -------------------------------------------------------------------*/ - sdram0_b1cr = 0; - sdram0_b2cr = 0; - sdram0_b3cr = 0; - - /* compute the size of each bank */ - bank_size = total_size / bank_cnt; - /* convert bank size to bank size code for ppc4xx - by takeing log2(bank_size) - 22 */ - tmp = bank_size; /* start with tmp = bank_size */ - bank_code = 0; /* and bank_code = 0 */ - while (tmp > 1) { /* this takes log2 of tmp */ - bank_code++; /* and stores result in bank_code */ - tmp = tmp >> 1; - } /* bank_code is now log2(bank_size) */ - bank_code -= 22; /* subtract 22 to get the code */ - - tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; - sdram0_b0cr = (bank_size * 0) | tmp; -#ifndef CONFIG_405EP /* not on PPC405EP */ - if (bank_cnt > 1) - sdram0_b2cr = (bank_size * 1) | tmp; - if (bank_cnt > 2) - sdram0_b1cr = (bank_size * 2) | tmp; - if (bank_cnt > 3) - sdram0_b3cr = (bank_size * 3) | tmp; -#else - /* PPC405EP chip only supports two SDRAM banks */ - if (bank_cnt > 1) - sdram0_b1cr = (bank_size * 1) | tmp; - if (bank_cnt > 2) - total_size = 2 * bank_size; -#endif - - /* - * enable sdram controller DCE=1 - * enable burst read prefetch to 32 bytes BRPF=2 - * leave other functions off - */ - - /*------------------------------------------------------------------ - * now that we've done our calculations, we are ready to - * program all the registers. - * -------------------------------------------------------------------*/ - - /* disable memcontroller so updates work */ - mtsdram(SDRAM0_CFG, 0); - -#ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram(SDRAM0_BESR0, sdram0_besr0); - mtsdram(SDRAM0_BESR1, sdram0_besr1); - mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg); - mtsdram(SDRAM0_ECCESR, sdram0_eccesr); -#endif - mtsdram(SDRAM0_RTR, sdram0_rtr); - mtsdram(SDRAM0_PMIT, sdram0_pmit); - mtsdram(SDRAM0_B0CR, sdram0_b0cr); - mtsdram(SDRAM0_B1CR, sdram0_b1cr); -#ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram(SDRAM0_B2CR, sdram0_b2cr); - mtsdram(SDRAM0_B3CR, sdram0_b3cr); -#endif - mtsdram(SDRAM0_TR, sdram0_tr); - - /* SDRAM have a power on delay, 500 micro should do */ - udelay(500); - sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; - if (ecc_on) - sdram0_cfg |= SDRAM0_CFG_MEMCHK; - mtsdram(SDRAM0_CFG, sdram0_cfg); - - return (total_size); -} - -int spd_read(uint addr) -{ - uchar data[2]; - - if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0) - return (int)data[0]; - else - return 0; -} - -#endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c deleted file mode 100644 index 6176eabfbf..0000000000 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ /dev/null @@ -1,1248 +0,0 @@ -/* - * cpu/ppc4xx/44x_spd_ddr.c - * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a - * DDR controller. Those are 440GP/GX/EP/GR. - * - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com - * - * Based on code by: - * - * Kenneth Johansson ,Ericsson AB. - * kenneth.johansson@etx.ericsson.se - * - * hacked up by bill hunter. fixed so we could run before - * serial_init and console_init. previous version avoided this by - * running out of cache memory during serial/console init, then running - * this code later. - * - * (C) Copyright 2002 - * Jun Gu, Artesyn Technology, jung@artesyncp.com - * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. - * - * (C) Copyright 2005-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include -#include -#include -#include -#include - -#include "ecc.h" - -#if defined(CONFIG_SPD_EEPROM) && \ - (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR)) - -/* - * Set default values - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif - -#define ONE_BILLION 1000000000 - -/* - * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed - */ -void __spd_ddr_init_hang (void) -{ - hang (); -} -void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); - -/*-----------------------------------------------------------------------------+ - | General Definition - +-----------------------------------------------------------------------------*/ -#define DEFAULT_SPD_ADDR1 0x53 -#define DEFAULT_SPD_ADDR2 0x52 -#define MAXBANKS 4 /* at most 4 dimm banks */ -#define MAX_SPD_BYTES 256 -#define NUMHALFCYCLES 4 -#define NUMMEMTESTS 8 -#define NUMMEMWORDS 8 -#define MAXBXCR 4 -#define TRUE 1 -#define FALSE 0 - -/* - * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory - * region. Right now the cache should still be disabled in U-Boot because of the - * EMAC driver, that need it's buffer descriptor to be located in non cached - * memory. - * - * If at some time this restriction doesn't apply anymore, just define - * CONFIG_4xx_DCACHE in the board config file and this code should setup - * everything correctly. - */ -#ifdef CONFIG_4xx_DCACHE -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ -#else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ -#endif - -/* bank_parms is used to sort the bank sizes by descending order */ -struct bank_param { - unsigned long cr; - unsigned long bank_size_bytes; -}; - -typedef struct bank_param BANKPARMS; - -#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM -extern const unsigned char cfg_simulate_spd_eeprom[128]; -#endif - -static unsigned char spd_read(uchar chip, uint addr); -static void get_spd_info(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void check_mem_type(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void check_volt_type(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_cfg0(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_cfg1(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_rtr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_tr0(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_tr1(void); - -static unsigned long program_bxcr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); - -/* - * This function is reading data from the DIMM module EEPROM over the SPD bus - * and uses that to program the sdram controller. - * - * This works on boards that has the same schematics that the AMCC walnut has. - * - * BUG: Don't handle ECC memory - * BUG: A few values in the TR register is currently hardcoded - */ -long int spd_sdram(void) { - unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; - unsigned long dimm_populated[sizeof(iic0_dimm_addr)]; - unsigned long total_size; - unsigned long cfg0; - unsigned long mcsts; - unsigned long num_dimm_banks; /* on board dimm banks */ - - num_dimm_banks = sizeof(iic0_dimm_addr); - - /* - * Make sure I2C controller is initialized - * before continuing. - */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* - * Read the SPD information using I2C interface. Check to see if the - * DIMM slots are populated. - */ - get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * Check the memory type for the dimms plugged. - */ - check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * Check the voltage type for the dimms plugged. - */ - check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); - -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - /* - * Soft-reset SDRAM controller. - */ - mtsdr(SDR0_SRST, SDR0_SRST_DMC); - mtsdr(SDR0_SRST, 0x00000000); -#endif - - /* - * program 440GP SDRAM controller options (SDRAM0_CFG0) - */ - program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * program 440GP SDRAM controller options (SDRAM0_CFG1) - */ - program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * program SDRAM refresh register (SDRAM0_RTR) - */ - program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * program SDRAM Timing Register 0 (SDRAM0_TR0) - */ - program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * program the BxCR registers to find out total sdram installed - */ - total_size = program_bxcr(dimm_populated, iic0_dimm_addr, - num_dimm_banks); - -#ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */ - /* and program tlb entries for this size (dynamic) */ - program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE); -#endif - - /* - * program SDRAM Clock Timing Register (SDRAM0_CLKTR) - */ - mtsdram(SDRAM0_CLKTR, 0x40000000); - - /* - * delay to ensure 200 usec has elapsed - */ - udelay(400); - - /* - * enable the memory controller - */ - mfsdram(SDRAM0_CFG0, cfg0); - mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN); - - /* - * wait for SDRAM_CFG0_DC_EN to complete - */ - while (1) { - mfsdram(SDRAM0_MCSTS, mcsts); - if ((mcsts & SDRAM_MCSTS_MRSC) != 0) - break; - } - - /* - * program SDRAM Timing Register 1, adding some delays - */ - program_tr1(); - -#ifdef CONFIG_DDR_ECC - /* - * If ecc is enabled, initialize the parity bits. - */ - ecc_init(CONFIG_SYS_SDRAM_BASE, total_size); -#endif - - return total_size; -} - -static unsigned char spd_read(uchar chip, uint addr) -{ - unsigned char data[2]; - -#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM - if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) { - /* - * Onboard spd eeprom requested -> simulate values - */ - return cfg_simulate_spd_eeprom[addr]; - } -#endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */ - - if (i2c_probe(chip) == 0) { - if (i2c_read(chip, addr, 1, data, 1) == 0) { - return data[0]; - } - } - - return 0; -} - -static void get_spd_info(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long dimm_found; - unsigned char num_of_bytes; - unsigned char total_size; - - dimm_found = FALSE; - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - num_of_bytes = 0; - total_size = 0; - - num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); - total_size = spd_read(iic0_dimm_addr[dimm_num], 1); - - if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; - debug("DIMM slot %lu: populated\n", dimm_num); - } else { - dimm_populated[dimm_num] = FALSE; - debug("DIMM slot %lu: Not populated\n", dimm_num); - } - } - - if (dimm_found == FALSE) { - printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); - spd_ddr_init_hang (); - } -} - -static void check_mem_type(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned char dimm_type; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); - switch (dimm_type) { - case 7: - debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); - break; - default: - printf("ERROR: Unsupported DIMM detected in slot %lu.\n", - dimm_num); - printf("Only DDR SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - } - } - } -} - -static void check_volt_type(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long voltage_type; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); - if (voltage_type != 0x04) { - printf("ERROR: DIMM %lu with unsupported voltage level.\n", - dimm_num); - spd_ddr_init_hang (); - } else { - debug("DIMM %lu voltage level supported.\n", dimm_num); - } - break; - } - } -} - -static void program_cfg0(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long cfg0; - unsigned long ecc_enabled; - unsigned char ecc; - unsigned char attributes; - unsigned long data_width; - unsigned long dimm_32bit; - unsigned long dimm_64bit; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(SDRAM0_CFG0, cfg0); - - /* - * clear bits - */ - cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK | - SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD | - SDRAM_CFG0_DMWD_MASK | - SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP); - - - /* - * FIXME: assume the DDR SDRAMs in both banks are the same - */ - ecc_enabled = TRUE; - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - ecc = spd_read(iic0_dimm_addr[dimm_num], 11); - if (ecc != 0x02) { - ecc_enabled = FALSE; - } - - /* - * program Registered DIMM Enable - */ - attributes = spd_read(iic0_dimm_addr[dimm_num], 21); - if ((attributes & 0x02) != 0x00) { - cfg0 |= SDRAM_CFG0_RDEN; - } - - /* - * program DDR SDRAM Data Width - */ - data_width = - (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) + - (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8); - if (data_width == 64 || data_width == 72) { - dimm_64bit = TRUE; - cfg0 |= SDRAM_CFG0_DMWD_64; - } else if (data_width == 32 || data_width == 40) { - dimm_32bit = TRUE; - cfg0 |= SDRAM_CFG0_DMWD_32; - } else { - printf("WARNING: DIMM with datawidth of %lu bits.\n", - data_width); - printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); - spd_ddr_init_hang (); - } - break; - } - } - - /* - * program Memory Data Error Checking - */ - if (ecc_enabled == TRUE) { - cfg0 |= SDRAM_CFG0_MCHK_GEN; - } else { - cfg0 |= SDRAM_CFG0_MCHK_NON; - } - - /* - * program Page Management Unit (0 == enabled) - */ - cfg0 &= ~SDRAM_CFG0_PMUD; - - /* - * program Memory Controller Options 0 - * Note: DCEN must be enabled after all DDR SDRAM controller - * configuration registers get initialized. - */ - mtsdram(SDRAM0_CFG0, cfg0); -} - -static void program_cfg1(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long cfg1; - mfsdram(SDRAM0_CFG1, cfg1); - - /* - * Self-refresh exit, disable PM - */ - cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN); - - /* - * program Memory Controller Options 1 - */ - mtsdram(SDRAM0_CFG1, cfg1); -} - -static void program_rtr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long bus_period_x_10; - unsigned long refresh_rate = 0; - unsigned char refresh_rate_type; - unsigned long refresh_interval; - unsigned long sdram_rtr; - PPC4xx_SYS_INFO sys_info; - - /* - * get the board info - */ - get_sys_info(&sys_info); - bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); - switch (refresh_rate_type) { - case 0x00: - refresh_rate = 15625; - break; - case 0x01: - refresh_rate = 15625/4; - break; - case 0x02: - refresh_rate = 15625/2; - break; - case 0x03: - refresh_rate = 15626*2; - break; - case 0x04: - refresh_rate = 15625*4; - break; - case 0x05: - refresh_rate = 15625*8; - break; - default: - printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n", - dimm_num); - printf("Replace the DIMM module with a supported DIMM.\n"); - break; - } - - break; - } - } - - refresh_interval = refresh_rate * 10 / bus_period_x_10; - sdram_rtr = (refresh_interval & 0x3ff8) << 16; - - /* - * program Refresh Timer Register (SDRAM0_RTR) - */ - mtsdram(SDRAM0_RTR, sdram_rtr); -} - -static void program_tr0(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long tr0; - unsigned char wcsbc; - unsigned char t_rp_ns; - unsigned char t_rcd_ns; - unsigned char t_ras_ns; - unsigned long t_rp_clk; - unsigned long t_ras_rcd_clk; - unsigned long t_rcd_clk; - unsigned long t_rfc_clk; - unsigned long plb_check; - unsigned char cas_bit; - unsigned long cas_index; - unsigned char cas_2_0_available; - unsigned char cas_2_5_available; - unsigned char cas_3_0_available; - unsigned long cycle_time_ns_x_10[3]; - unsigned long tcyc_3_0_ns_x_10; - unsigned long tcyc_2_5_ns_x_10; - unsigned long tcyc_2_0_ns_x_10; - unsigned long tcyc_reg; - unsigned long bus_period_x_10; - PPC4xx_SYS_INFO sys_info; - unsigned long residue; - - /* - * get the board info - */ - get_sys_info(&sys_info); - bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); - - /* - * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits - */ - mfsdram(SDRAM0_TR0, tr0); - tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | - SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | - SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | - SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK); - - /* - * initialization - */ - wcsbc = 0; - t_rp_ns = 0; - t_rcd_ns = 0; - t_ras_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; - tcyc_2_0_ns_x_10 = 0; - tcyc_2_5_ns_x_10 = 0; - tcyc_3_0_ns_x_10 = 0; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); - t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; - t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; - t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30); - cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); - - for (cas_index = 0; cas_index < 3; cas_index++) { - switch (cas_index) { - case 0: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); - break; - case 1: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); - break; - default: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); - break; - } - - if ((tcyc_reg & 0x0F) >= 10) { - printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", - dimm_num); - spd_ddr_init_hang (); - } - - cycle_time_ns_x_10[cas_index] = - (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F); - } - - cas_index = 0; - - if ((cas_bit & 0x80) != 0) { - cas_index += 3; - } else if ((cas_bit & 0x40) != 0) { - cas_index += 2; - } else if ((cas_bit & 0x20) != 0) { - cas_index += 1; - } - - if (((cas_bit & 0x10) != 0) && (cas_index < 3)) { - tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; - cas_index++; - } else { - if (cas_index != 0) { - cas_index++; - } - cas_3_0_available = FALSE; - } - - if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { - tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index]; - cas_index++; - } else { - if (cas_index != 0) { - cas_index++; - } - cas_2_5_available = FALSE; - } - - if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { - tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; - cas_index++; - } else { - if (cas_index != 0) { - cas_index++; - } - cas_2_0_available = FALSE; - } - - break; - } - } - - /* - * Program SD_WR and SD_WCSBC fields - */ - tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ - switch (wcsbc) { - case 0: - tr0 |= SDRAM_TR0_SDWD_0_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDWD_1_CLK; - break; - } - - /* - * Program SD_CASL field - */ - if ((cas_2_0_available == TRUE) && - (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { - tr0 |= SDRAM_TR0_SDCL_2_0_CLK; - } else if ((cas_2_5_available == TRUE) && - (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { - tr0 |= SDRAM_TR0_SDCL_2_5_CLK; - } else if ((cas_3_0_available == TRUE) && - (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { - tr0 |= SDRAM_TR0_SDCL_3_0_CLK; - } else { - printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); - printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); - printf("Make sure the PLB speed is within the supported range.\n"); - spd_ddr_init_hang (); - } - - /* - * Calculate Trp in clock cycles and round up if necessary - * Program SD_PTA field - */ - t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION; - plb_check = ONE_BILLION * t_rp_clk / t_rp_ns; - if (sys_info.freqPLB != plb_check) { - t_rp_clk++; - } - switch ((unsigned long)t_rp_clk) { - case 0: - case 1: - case 2: - tr0 |= SDRAM_TR0_SDPA_2_CLK; - break; - case 3: - tr0 |= SDRAM_TR0_SDPA_3_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDPA_4_CLK; - break; - } - - /* - * Program SD_CTP field - */ - t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION; - plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns); - if (sys_info.freqPLB != plb_check) { - t_ras_rcd_clk++; - } - switch (t_ras_rcd_clk) { - case 0: - case 1: - case 2: - tr0 |= SDRAM_TR0_SDCP_2_CLK; - break; - case 3: - tr0 |= SDRAM_TR0_SDCP_3_CLK; - break; - case 4: - tr0 |= SDRAM_TR0_SDCP_4_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDCP_5_CLK; - break; - } - - /* - * Program SD_LDF field - */ - tr0 |= SDRAM_TR0_SDLD_2_CLK; - - /* - * Program SD_RFTA field - * FIXME tRFC hardcoded as 75 nanoseconds - */ - t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75); - residue = sys_info.freqPLB % (ONE_BILLION / 75); - if (residue >= (ONE_BILLION / 150)) { - t_rfc_clk++; - } - switch (t_rfc_clk) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - tr0 |= SDRAM_TR0_SDRA_6_CLK; - break; - case 7: - tr0 |= SDRAM_TR0_SDRA_7_CLK; - break; - case 8: - tr0 |= SDRAM_TR0_SDRA_8_CLK; - break; - case 9: - tr0 |= SDRAM_TR0_SDRA_9_CLK; - break; - case 10: - tr0 |= SDRAM_TR0_SDRA_10_CLK; - break; - case 11: - tr0 |= SDRAM_TR0_SDRA_11_CLK; - break; - case 12: - tr0 |= SDRAM_TR0_SDRA_12_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDRA_13_CLK; - break; - } - - /* - * Program SD_RCD field - */ - t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION; - plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns; - if (sys_info.freqPLB != plb_check) { - t_rcd_clk++; - } - switch (t_rcd_clk) { - case 0: - case 1: - case 2: - tr0 |= SDRAM_TR0_SDRD_2_CLK; - break; - case 3: - tr0 |= SDRAM_TR0_SDRD_3_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDRD_4_CLK; - break; - } - - debug("tr0: %x\n", tr0); - mtsdram(SDRAM0_TR0, tr0); -} - -static int short_mem_test(void) -{ - unsigned long i, j; - unsigned long bxcr_num; - unsigned long *membase; - const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { - {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, - {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, - {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, - {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, - {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, - {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, - {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, - {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; - - for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { - mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2)); - if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { - /* Bank is enabled */ - membase = (unsigned long*) - (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); - - /* - * Run the short memory test - */ - for (i = 0; i < NUMMEMTESTS; i++) { - for (j = 0; j < NUMMEMWORDS; j++) { - /* printf("bank enabled base:%x\n", &membase[j]); */ - membase[j] = test[i][j]; - ppcDcbf((unsigned long)&(membase[j])); - } - - for (j = 0; j < NUMMEMWORDS; j++) { - if (membase[j] != test[i][j]) { - ppcDcbf((unsigned long)&(membase[j])); - return 0; - } - ppcDcbf((unsigned long)&(membase[j])); - } - - if (j < NUMMEMWORDS) - return 0; - } - - /* - * see if the rdclt value passed - */ - if (i < NUMMEMTESTS) - return 0; - } - } - - return 1; -} - -static void program_tr1(void) -{ - unsigned long tr0; - unsigned long tr1; - unsigned long cfg0; - unsigned long ecc_temp; - unsigned long dlycal; - unsigned long dly_val; - unsigned long k; - unsigned long max_pass_length; - unsigned long current_pass_length; - unsigned long current_fail_length; - unsigned long current_start; - unsigned long rdclt; - unsigned long rdclt_offset; - long max_start; - long max_end; - long rdclt_average; - unsigned char window_found; - unsigned char fail_found; - unsigned char pass_found; - PPC4xx_SYS_INFO sys_info; - - /* - * get the board info - */ - get_sys_info(&sys_info); - - /* - * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits - */ - mfsdram(SDRAM0_TR1, tr1); - tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | - SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); - - mfsdram(SDRAM0_TR0, tr0); - if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && - (sys_info.freqPLB > 100000000)) { - tr1 |= SDRAM_TR1_RDSS_TR2; - tr1 |= SDRAM_TR1_RDSL_STAGE3; - tr1 |= SDRAM_TR1_RDCD_RCD_1_2; - } else { - tr1 |= SDRAM_TR1_RDSS_TR1; - tr1 |= SDRAM_TR1_RDSL_STAGE2; - tr1 |= SDRAM_TR1_RDCD_RCD_0_0; - } - - /* - * save CFG0 ECC setting to a temporary variable and turn ECC off - */ - mfsdram(SDRAM0_CFG0, cfg0); - ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; - mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); - - /* - * get the delay line calibration register value - */ - mfsdram(SDRAM0_DLYCAL, dlycal); - dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; - - max_pass_length = 0; - max_start = 0; - max_end = 0; - current_pass_length = 0; - current_fail_length = 0; - current_start = 0; - rdclt_offset = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; - debug("Starting memory test "); - - for (k = 0; k < NUMHALFCYCLES; k++) { - for (rdclt = 0; rdclt < dly_val; rdclt++) { - /* - * Set the timing reg for the test. - */ - mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); - - if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; - if (current_pass_length == 0) { - current_start = rdclt_offset + rdclt; - } - - current_fail_length = 0; - current_pass_length++; - - if (current_pass_length > max_pass_length) { - max_pass_length = current_pass_length; - max_start = current_start; - max_end = rdclt_offset + rdclt; - } - } - } else { - current_pass_length = 0; - current_fail_length++; - - if (current_fail_length >= (dly_val>>2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; - break; - } - } - } - } - debug("."); - - if (window_found == TRUE) { - break; - } - - tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; - rdclt_offset += dly_val; - } - debug("\n"); - - /* - * make sure we find the window - */ - if (window_found == FALSE) { - printf("ERROR: Cannot determine a common read delay.\n"); - spd_ddr_init_hang (); - } - - /* - * restore the orignal ECC setting - */ - mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); - - /* - * set the SDRAM TR1 RDCD value - */ - tr1 &= ~SDRAM_TR1_RDCD_MASK; - if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) { - tr1 |= SDRAM_TR1_RDCD_RCD_1_2; - } else { - tr1 |= SDRAM_TR1_RDCD_RCD_0_0; - } - - /* - * set the SDRAM TR1 RDCLT value - */ - tr1 &= ~SDRAM_TR1_RDCT_MASK; - while (max_end >= (dly_val << 1)) { - max_end -= (dly_val << 1); - max_start -= (dly_val << 1); - } - - rdclt_average = ((max_start + max_end) >> 1); - - if (rdclt_average < 0) { - rdclt_average = 0; - } - - if (rdclt_average >= dly_val) { - rdclt_average -= dly_val; - tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; - } - tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average); - - debug("tr1: %x\n", tr1); - - /* - * program SDRAM Timing Register 1 TR1 - */ - mtsdram(SDRAM0_TR1, tr1); -} - -static unsigned long program_bxcr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long bank_base_addr; - unsigned long cr; - unsigned long i; - unsigned long j; - unsigned long temp; - unsigned char num_row_addr; - unsigned char num_col_addr; - unsigned char num_banks; - unsigned char bank_size_id; - unsigned long ctrl_bank_num[MAXBANKS]; - unsigned long bx_cr_num; - unsigned long largest_size_index; - unsigned long largest_size; - unsigned long current_size_index; - BANKPARMS bank_parms[MAXBXCR]; - unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */ - unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/ - - /* - * Set the BxCR regs. First, wipe out the bank config registers. - */ - for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { - mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2)); - mtdcr(SDRAM0_CFGDATA, 0x00000000); - bank_parms[bx_cr_num].bank_size_bytes = 0; - } - -#ifdef CONFIG_BAMBOO - /* - * This next section is hardware dependent and must be programmed - * to match the hardware. For bamboo, the following holds... - * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard) - * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1 - * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1 - * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3 - * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM - */ - ctrl_bank_num[0] = 0; - ctrl_bank_num[1] = 1; - ctrl_bank_num[2] = 3; -#else - /* - * Ocotea, Ebony and the other IBM/AMCC eval boards have - * 2 DIMM slots with each max 2 banks - */ - ctrl_bank_num[0] = 0; - ctrl_bank_num[1] = 2; -#endif - - /* - * reset the bank_base address - */ - bank_base_addr = CONFIG_SYS_SDRAM_BASE; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); - num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); - num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); - bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); - debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num, - num_row_addr, num_col_addr, num_banks); - - /* - * Set the SDRAM0_BxCR regs - */ - cr = 0; - switch (bank_size_id) { - case 0x02: - cr |= SDRAM_BXCR_SDSZ_8; - break; - case 0x04: - cr |= SDRAM_BXCR_SDSZ_16; - break; - case 0x08: - cr |= SDRAM_BXCR_SDSZ_32; - break; - case 0x10: - cr |= SDRAM_BXCR_SDSZ_64; - break; - case 0x20: - cr |= SDRAM_BXCR_SDSZ_128; - break; - case 0x40: - cr |= SDRAM_BXCR_SDSZ_256; - break; - case 0x80: - cr |= SDRAM_BXCR_SDSZ_512; - break; - default: - printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", - dimm_num); - printf("ERROR: Unsupported value for the banksize: %d.\n", - bank_size_id); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - } - - switch (num_col_addr) { - case 0x08: - cr |= SDRAM_BXCR_SDAM_1; - break; - case 0x09: - cr |= SDRAM_BXCR_SDAM_2; - break; - case 0x0A: - cr |= SDRAM_BXCR_SDAM_3; - break; - case 0x0B: - cr |= SDRAM_BXCR_SDAM_4; - break; - default: - printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", - dimm_num); - printf("ERROR: Unsupported value for number of " - "column addresses: %d.\n", num_col_addr); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - } - - /* - * enable the bank - */ - cr |= SDRAM_BXCR_SDBE; - - for (i = 0; i < num_banks; i++) { - bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = - (4 << 20) * bank_size_id; - bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; - debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n", - dimm_num, i, ctrl_bank_num[dimm_num]+i, - bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes); - } - } - } - - /* Initialize sort tables */ - for (i = 0; i < MAXBXCR; i++) { - sorted_bank_num[i] = i; - sorted_bank_size[i] = bank_parms[i].bank_size_bytes; - } - - for (i = 0; i < MAXBXCR-1; i++) { - largest_size = sorted_bank_size[i]; - largest_size_index = 255; - - /* Find the largest remaining value */ - for (j = i + 1; j < MAXBXCR; j++) { - if (sorted_bank_size[j] > largest_size) { - /* Save largest remaining value and its index */ - largest_size = sorted_bank_size[j]; - largest_size_index = j; - } - } - - if (largest_size_index != 255) { - /* Swap the current and largest values */ - current_size_index = sorted_bank_num[largest_size_index]; - sorted_bank_size[largest_size_index] = sorted_bank_size[i]; - sorted_bank_size[i] = largest_size; - sorted_bank_num[largest_size_index] = sorted_bank_num[i]; - sorted_bank_num[i] = current_size_index; - } - } - - /* Set the SDRAM0_BxCR regs thanks to sort tables */ - for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { - if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { - mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2)); - temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | - SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); - temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | - bank_parms[sorted_bank_num[bx_cr_num]].cr; - mtdcr(SDRAM0_CFGDATA, temp); - bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; - debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp); - } - } - - return(bank_base_addr); -} -#endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c deleted file mode 100644 index 593a286919..0000000000 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ /dev/null @@ -1,3174 +0,0 @@ -/* - * cpu/ppc4xx/44x_spd_ddr2.c - * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a - * DDR2 controller (non Denali Core). Those currently are: - * - * 405: 405EX(r) - * 440/460: 440SP/440SPe/460EX/460GT - * - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson - - * (C) Copyright 2007-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * COPYRIGHT AMCC CORPORATION 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ecc.h" - -#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) - -#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \ - do { \ - u32 data; \ - mfsdram(SDRAM_##mnemonic, data); \ - printf("%20s[%02x] = 0x%08X\n", \ - "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ - } while (0) - -#define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \ - do { \ - u32 data; \ - data = mfdcr(SDRAM_##mnemonic); \ - printf("%20s[%02x] = 0x%08X\n", \ - "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ - } while (0) - -#if defined(CONFIG_440) -/* - * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 - * memory region. Right now the cache should still be disabled in U-Boot - * because of the EMAC driver, that need its buffer descriptor to be located - * in non cached memory. - * - * If at some time this restriction doesn't apply anymore, just define - * CONFIG_4xx_DCACHE in the board config file and this code should setup - * everything correctly. - */ -#ifdef CONFIG_4xx_DCACHE -/* enable caching on SDRAM */ -#define MY_TLB_WORD2_I_ENABLE 0 -#else -/* disable caching on SDRAM */ -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE -#endif /* CONFIG_4xx_DCACHE */ - -void dcbz_area(u32 start_address, u32 num_bytes); -#endif /* CONFIG_440 */ - -#define MAXRANKS 4 -#define MAXBXCF 4 - -#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) - -#if !defined(CONFIG_NAND_SPL) -/*-----------------------------------------------------------------------------+ - * sdram_memsize - *-----------------------------------------------------------------------------*/ -phys_size_t sdram_memsize(void) -{ - phys_size_t mem_size; - unsigned long mcopt2; - unsigned long mcstat; - unsigned long mb0cf; - unsigned long sdsz; - unsigned long i; - - mem_size = 0; - - mfsdram(SDRAM_MCOPT2, mcopt2); - mfsdram(SDRAM_MCSTAT, mcstat); - - /* DDR controller must be enabled and not in self-refresh. */ - /* Otherwise memsize is zero. */ - if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) - && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) - && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) - == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { - for (i = 0; i < MAXBXCF; i++) { - mfsdram(SDRAM_MB0CF + (i << 2), mb0cf); - /* Banks enabled */ - if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { -#if defined(CONFIG_440) - sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK; -#else - sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK; -#endif - switch(sdsz) { - case SDRAM_RXBAS_SDSZ_8: - mem_size+=8; - break; - case SDRAM_RXBAS_SDSZ_16: - mem_size+=16; - break; - case SDRAM_RXBAS_SDSZ_32: - mem_size+=32; - break; - case SDRAM_RXBAS_SDSZ_64: - mem_size+=64; - break; - case SDRAM_RXBAS_SDSZ_128: - mem_size+=128; - break; - case SDRAM_RXBAS_SDSZ_256: - mem_size+=256; - break; - case SDRAM_RXBAS_SDSZ_512: - mem_size+=512; - break; - case SDRAM_RXBAS_SDSZ_1024: - mem_size+=1024; - break; - case SDRAM_RXBAS_SDSZ_2048: - mem_size+=2048; - break; - case SDRAM_RXBAS_SDSZ_4096: - mem_size+=4096; - break; - default: - printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n" - , sdsz); - mem_size=0; - break; - } - } - } - } - - return mem_size << 20; -} - -/*-----------------------------------------------------------------------------+ - * is_ecc_enabled - *-----------------------------------------------------------------------------*/ -static unsigned long is_ecc_enabled(void) -{ - unsigned long val; - - mfsdram(SDRAM_MCOPT1, val); - - return SDRAM_MCOPT1_MCHK_CHK_DECODE(val); -} - -/*-----------------------------------------------------------------------------+ - * board_add_ram_info - *-----------------------------------------------------------------------------*/ -void board_add_ram_info(int use_default) -{ - PPC4xx_SYS_INFO board_cfg; - u32 val; - - if (is_ecc_enabled()) - puts(" (ECC"); - else - puts(" (ECC not"); - - get_sys_info(&board_cfg); - -#if defined(CONFIG_405EX) - val = board_cfg.freqPLB; -#else - mfsdr(SDR0_DDR0, val); - val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1); -#endif - printf(" enabled, %d MHz", (val * 2) / 1000000); - - mfsdram(SDRAM_MMODE, val); - val = (val & SDRAM_MMODE_DCL_MASK) >> 4; - printf(", CL%d)", val); -} -#endif /* !CONFIG_NAND_SPL */ - -#if defined(CONFIG_SPD_EEPROM) - -/*-----------------------------------------------------------------------------+ - * Defines - *-----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -#define SDRAM_DDR1 1 -#define SDRAM_DDR2 2 -#define SDRAM_NONE 0 - -#define MAXDIMMS 2 -#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ - -#define ONE_BILLION 1000000000 - -#define CMD_NOP (7 << 19) -#define CMD_PRECHARGE (2 << 19) -#define CMD_REFRESH (1 << 19) -#define CMD_EMR (0 << 19) -#define CMD_READ (5 << 19) -#define CMD_WRITE (4 << 19) - -#define SELECT_MR (0 << 16) -#define SELECT_EMR (1 << 16) -#define SELECT_EMR2 (2 << 16) -#define SELECT_EMR3 (3 << 16) - -/* MR */ -#define DLL_RESET 0x00000100 - -#define WRITE_RECOV_2 (1 << 9) -#define WRITE_RECOV_3 (2 << 9) -#define WRITE_RECOV_4 (3 << 9) -#define WRITE_RECOV_5 (4 << 9) -#define WRITE_RECOV_6 (5 << 9) - -#define BURST_LEN_4 0x00000002 - -/* EMR */ -#define ODT_0_OHM 0x00000000 -#define ODT_50_OHM 0x00000044 -#define ODT_75_OHM 0x00000004 -#define ODT_150_OHM 0x00000040 - -#define ODS_FULL 0x00000000 -#define ODS_REDUCED 0x00000002 -#define OCD_CALIB_DEF 0x00000380 - -/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */ -#define ODT_EB0R (0x80000000 >> 8) -#define ODT_EB0W (0x80000000 >> 7) -#define CALC_ODT_R(n) (ODT_EB0R << (n << 1)) -#define CALC_ODT_W(n) (ODT_EB0W << (n << 1)) -#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n)) - -/* Defines for the Read Cycle Delay test */ -#define NUMMEMTESTS 8 -#define NUMMEMWORDS 8 -#define NUMLOOPS 64 /* memory test loops */ - -/* - * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. - * To support such configurations, we "only" map the first 2GB via the TLB's. We - * need some free virtual address space for the remaining peripherals like, SoC - * devices, FLASH etc. - * - * Note that ECC is currently not supported on configurations with more than 2GB - * SDRAM. This is because we only map the first 2GB on such systems, and therefore - * the ECC parity byte of the remaining area can't be written. - */ - -/* - * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed - */ -void __spd_ddr_init_hang (void) -{ - hang (); -} -void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); - -/* - * To provide an interface for board specific config values in this common - * DDR setup code, we implement he "weak" default functions here. They return - * the default value back to the caller. - * - * Please see include/configs/yucca.h for an example fora board specific - * implementation. - */ -u32 __ddr_wrdtr(u32 default_val) -{ - return default_val; -} -u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr"))); - -u32 __ddr_clktr(u32 default_val) -{ - return default_val; -} -u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr"))); - - -/* Private Structure Definitions */ - -/* enum only to ease code for cas latency setting */ -typedef enum ddr_cas_id { - DDR_CAS_2 = 20, - DDR_CAS_2_5 = 25, - DDR_CAS_3 = 30, - DDR_CAS_4 = 40, - DDR_CAS_5 = 50 -} ddr_cas_id_t; - -/*-----------------------------------------------------------------------------+ - * Prototypes - *-----------------------------------------------------------------------------*/ -static void get_spd_info(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void check_mem_type(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void check_frequency(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void check_rank_number(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void check_voltage_type(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_memory_queue(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_codt(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_mode(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks, - ddr_cas_id_t *selected_cas, - int *write_recovery); -static void program_tr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_rtr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_bxcf(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_copt1(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -static void program_initplr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks, - ddr_cas_id_t selected_cas, - int write_recovery); -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks, - unsigned long tlb_word2_i_value); -#endif -#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -static void program_DQS_calibration(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); -#ifdef HARD_CODED_DQS /* calibration test with hardvalues */ -static void test(void); -#else -static void DQS_calibration_process(void); -#endif -#endif -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -static unsigned char spd_read(uchar chip, uint addr) -{ - unsigned char data[2]; - - if (i2c_probe(chip) == 0) - if (i2c_read(chip, addr, 1, data, 1) == 0) - return data[0]; - - return 0; -} - -/*-----------------------------------------------------------------------------+ - * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller. - * Note: This routine runs from flash with a stack set up in the chip's - * sram space. It is important that the routine does not require .sbss, .bss or - * .data sections. It also cannot call routines that require these sections. - *-----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------- - * Function: initdram - * Description: Configures SDRAM memory banks for DDR operation. - * Auto Memory Configuration option reads the DDR SDRAM EEPROMs - * via the IIC bus and then configures the DDR SDRAM memory - * banks appropriately. If Auto Memory Configuration is - * not used, it is assumed that no DIMM is plugged - *-----------------------------------------------------------------------------*/ -phys_size_t initdram(int board_type) -{ - unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; - unsigned char spd0[MAX_SPD_BYTES]; - unsigned char spd1[MAX_SPD_BYTES]; - unsigned char *dimm_spd[MAXDIMMS]; - unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE}; - unsigned long num_dimm_banks; /* on board dimm banks */ - unsigned long val; - ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */ - int write_recovery; - phys_size_t dram_size = 0; - - num_dimm_banks = sizeof(iic0_dimm_addr); - - /*------------------------------------------------------------------ - * Set up an array of SPD matrixes. - *-----------------------------------------------------------------*/ - dimm_spd[0] = spd0; - dimm_spd[1] = spd1; - - /*------------------------------------------------------------------ - * Reset the DDR-SDRAM controller. - *-----------------------------------------------------------------*/ - mtsdr(SDR0_SRST, (0x80000000 >> 10)); - mtsdr(SDR0_SRST, 0x00000000); - - /* - * Make sure I2C controller is initialized - * before continuing. - */ - - /* switch to correct I2C bus */ - I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /*------------------------------------------------------------------ - * Clear out the serial presence detect buffers. - * Perform IIC reads from the dimm. Fill in the spds. - * Check to see if the dimm slots are populated - *-----------------------------------------------------------------*/ - get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Check the memory type for the dimms plugged. - *-----------------------------------------------------------------*/ - check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Check the frequency supported for the dimms plugged. - *-----------------------------------------------------------------*/ - check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Check the total rank number. - *-----------------------------------------------------------------*/ - check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Check the voltage type for the dimms plugged. - *-----------------------------------------------------------------*/ - check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Program SDRAM controller options 2 register - * Except Enabling of the memory controller. - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_MCOPT2, val); - mtsdram(SDRAM_MCOPT2, - (val & - ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK | - SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK | - SDRAM_MCOPT2_ISIE_MASK)) - | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE | - SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW | - SDRAM_MCOPT2_ISIE_ENABLE)); - - /*------------------------------------------------------------------ - * Program SDRAM controller options 1 register - * Note: Does not enable the memory controller. - *-----------------------------------------------------------------*/ - program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Set the SDRAM Controller On Die Termination Register - *-----------------------------------------------------------------*/ - program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Program SDRAM refresh register. - *-----------------------------------------------------------------*/ - program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Program SDRAM mode register. - *-----------------------------------------------------------------*/ - program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks, - &selected_cas, &write_recovery); - - /*------------------------------------------------------------------ - * Set the SDRAM Write Data/DM/DQS Clock Timing Reg - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_WRDTR, val); - mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) | - ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV)); - - /*------------------------------------------------------------------ - * Set the SDRAM Clock Timing Register - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_CLKTR, val); - mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | - ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG)); - - /*------------------------------------------------------------------ - * Program the BxCF registers. - *-----------------------------------------------------------------*/ - program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Program SDRAM timing registers. - *-----------------------------------------------------------------*/ - program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Set the Extended Mode register - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_MEMODE, val); - mtsdram(SDRAM_MEMODE, - (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK | - SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) | - (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE - | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE)); - - /*------------------------------------------------------------------ - * Program Initialization preload registers. - *-----------------------------------------------------------------*/ - program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks, - selected_cas, write_recovery); - - /*------------------------------------------------------------------ - * Delay to ensure 200usec have elapsed since reset. - *-----------------------------------------------------------------*/ - udelay(400); - - /*------------------------------------------------------------------ - * Set the memory queue core base addr. - *-----------------------------------------------------------------*/ - program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Program SDRAM controller options 2 register - * Enable the memory controller. - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_MCOPT2, val); - mtsdram(SDRAM_MCOPT2, - (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK | - SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) | - SDRAM_MCOPT2_IPTR_EXECUTE); - - /*------------------------------------------------------------------ - * Wait for IPTR_EXECUTE init sequence to complete. - *-----------------------------------------------------------------*/ - do { - mfsdram(SDRAM_MCSTAT, val); - } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP); - - /* enable the controller only after init sequence completes */ - mfsdram(SDRAM_MCOPT2, val); - mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE)); - - /* Make sure delay-line calibration is done before proceeding */ - do { - mfsdram(SDRAM_DLCR, val); - } while (!(val & SDRAM_DLCR_DLCS_COMPLETE)); - - /* get installed memory size */ - dram_size = sdram_memsize(); - - /* - * Limit size to 2GB - */ - if (dram_size > CONFIG_MAX_MEM_MAPPED) - dram_size = CONFIG_MAX_MEM_MAPPED; - - /* and program tlb entries for this size (dynamic) */ - - /* - * Program TLB entries with caches enabled, for best performace - * while auto-calibrating and ECC generation - */ - program_tlb(0, 0, dram_size, 0); - - /*------------------------------------------------------------------ - * DQS calibration. - *-----------------------------------------------------------------*/ -#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) - DQS_autocalibration(); -#else - program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks); -#endif - -#ifdef CONFIG_DDR_ECC - /*------------------------------------------------------------------ - * If ecc is enabled, initialize the parity bits. - *-----------------------------------------------------------------*/ - program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0); -#endif - - /* - * Now after initialization (auto-calibration and ECC generation) - * remove the TLB entries with caches enabled and program again with - * desired cache functionality - */ - remove_tlb(0, dram_size); - program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); - - ppc4xx_ibm_ddr2_register_dump(); - - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return sdram_memsize(); -} - -static void get_spd_info(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long dimm_found; - unsigned char num_of_bytes; - unsigned char total_size; - - dimm_found = FALSE; - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - num_of_bytes = 0; - total_size = 0; - - num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); - debug("\nspd_read(0x%x) returned %d\n", - iic0_dimm_addr[dimm_num], num_of_bytes); - total_size = spd_read(iic0_dimm_addr[dimm_num], 1); - debug("spd_read(0x%x) returned %d\n", - iic0_dimm_addr[dimm_num], total_size); - - if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; - debug("DIMM slot %lu: populated\n", dimm_num); - } else { - dimm_populated[dimm_num] = FALSE; - debug("DIMM slot %lu: Not populated\n", dimm_num); - } - } - - if (dimm_found == FALSE) { - printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); - spd_ddr_init_hang (); - } -} - - -/*------------------------------------------------------------------ - * For the memory DIMMs installed, this routine verifies that they - * really are DDR specific DIMMs. - *-----------------------------------------------------------------*/ -static void check_mem_type(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long dimm_type; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); - switch (dimm_type) { - case 1: - printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in " - "slot %d.\n", (unsigned int)dimm_num); - printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - case 2: - printf("ERROR: EDO DIMM detected in slot %d.\n", - (unsigned int)dimm_num); - printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - case 3: - printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n", - (unsigned int)dimm_num); - printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - case 4: - printf("ERROR: SDRAM DIMM detected in slot %d.\n", - (unsigned int)dimm_num); - printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - case 5: - printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n", - (unsigned int)dimm_num); - printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - case 6: - printf("ERROR: SGRAM DIMM detected in slot %d.\n", - (unsigned int)dimm_num); - printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - case 7: - debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num); - dimm_populated[dimm_num] = SDRAM_DDR1; - break; - case 8: - debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num); - dimm_populated[dimm_num] = SDRAM_DDR2; - break; - default: - printf("ERROR: Unknown DIMM detected in slot %d.\n", - (unsigned int)dimm_num); - printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - } - } - } - for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) { - if ((dimm_populated[dimm_num-1] != SDRAM_NONE) - && (dimm_populated[dimm_num] != SDRAM_NONE) - && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) { - printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n"); - spd_ddr_init_hang (); - } - } -} - -/*------------------------------------------------------------------ - * For the memory DIMMs installed, this routine verifies that - * frequency previously calculated is supported. - *-----------------------------------------------------------------*/ -static void check_frequency(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long tcyc_reg; - unsigned long cycle_time; - unsigned long calc_cycle_time; - unsigned long sdram_freq; - unsigned long sdr_ddrpll; - PPC4xx_SYS_INFO board_cfg; - - /*------------------------------------------------------------------ - * Get the board configuration info. - *-----------------------------------------------------------------*/ - get_sys_info(&board_cfg); - - mfsdr(SDR0_DDR0, sdr_ddrpll); - sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); - - /* - * calc_cycle_time is calculated from DDR frequency set by board/chip - * and is expressed in multiple of 10 picoseconds - * to match the way DIMM cycle time is calculated below. - */ - calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq); - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] != SDRAM_NONE) { - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); - /* - * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles: - * the higher order nibble (bits 4-7) designates the cycle time - * to a granularity of 1ns; - * the value presented by the lower order nibble (bits 0-3) - * has a granularity of .1ns and is added to the value designated - * by the higher nibble. In addition, four lines of the lower order - * nibble are assigned to support +.25,+.33, +.66 and +.75. - */ - /* Convert from hex to decimal */ - if ((tcyc_reg & 0x0F) == 0x0D) - cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75; - else if ((tcyc_reg & 0x0F) == 0x0C) - cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66; - else if ((tcyc_reg & 0x0F) == 0x0B) - cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33; - else if ((tcyc_reg & 0x0F) == 0x0A) - cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25; - else - cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + - ((tcyc_reg & 0x0F)*10); - debug("cycle_time=%lu [10 picoseconds]\n", cycle_time); - - if (cycle_time > (calc_cycle_time + 10)) { - /* - * the provided sdram cycle_time is too small - * for the available DIMM cycle_time. - * The additionnal 100ps is here to accept a small incertainty. - */ - printf("ERROR: DRAM DIMM detected with cycle_time %d ps in " - "slot %d \n while calculated cycle time is %d ps.\n", - (unsigned int)(cycle_time*10), - (unsigned int)dimm_num, - (unsigned int)(calc_cycle_time*10)); - printf("Replace the DIMM, or change DDR frequency via " - "strapping bits.\n\n"); - spd_ddr_init_hang (); - } - } - } -} - -/*------------------------------------------------------------------ - * For the memory DIMMs installed, this routine verifies two - * ranks/banks maximum are availables. - *-----------------------------------------------------------------*/ -static void check_rank_number(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long dimm_rank; - unsigned long total_rank = 0; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] != SDRAM_NONE) { - dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5); - if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) - dimm_rank = (dimm_rank & 0x0F) +1; - else - dimm_rank = dimm_rank & 0x0F; - - - if (dimm_rank > MAXRANKS) { - printf("ERROR: DRAM DIMM detected with %lu ranks in " - "slot %lu is not supported.\n", dimm_rank, dimm_num); - printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - } else - total_rank += dimm_rank; - } - if (total_rank > MAXRANKS) { - printf("ERROR: DRAM DIMM detected with a total of %d ranks " - "for all slots.\n", (unsigned int)total_rank); - printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); - printf("Remove one of the DIMM modules.\n\n"); - spd_ddr_init_hang (); - } - } -} - -/*------------------------------------------------------------------ - * only support 2.5V modules. - * This routine verifies this. - *-----------------------------------------------------------------*/ -static void check_voltage_type(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long voltage_type; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] != SDRAM_NONE) { - voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); - switch (voltage_type) { - case 0x00: - printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); - printf("This DIMM is 5.0 Volt/TTL.\n"); - printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", - (unsigned int)dimm_num); - spd_ddr_init_hang (); - break; - case 0x01: - printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); - printf("This DIMM is LVTTL.\n"); - printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", - (unsigned int)dimm_num); - spd_ddr_init_hang (); - break; - case 0x02: - printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); - printf("This DIMM is 1.5 Volt.\n"); - printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", - (unsigned int)dimm_num); - spd_ddr_init_hang (); - break; - case 0x03: - printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); - printf("This DIMM is 3.3 Volt/TTL.\n"); - printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", - (unsigned int)dimm_num); - spd_ddr_init_hang (); - break; - case 0x04: - /* 2.5 Voltage only for DDR1 */ - break; - case 0x05: - /* 1.8 Voltage only for DDR2 */ - break; - default: - printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); - printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", - (unsigned int)dimm_num); - spd_ddr_init_hang (); - break; - } - } - } -} - -/*-----------------------------------------------------------------------------+ - * program_copt1. - *-----------------------------------------------------------------------------*/ -static void program_copt1(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long mcopt1; - unsigned long ecc_enabled; - unsigned long ecc = 0; - unsigned long data_width = 0; - unsigned long dimm_32bit; - unsigned long dimm_64bit; - unsigned long registered = 0; - unsigned long attribute = 0; - unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */ - unsigned long bankcount; - unsigned long ddrtype; - unsigned long val; - -#ifdef CONFIG_DDR_ECC - ecc_enabled = TRUE; -#else - ecc_enabled = FALSE; -#endif - dimm_32bit = FALSE; - dimm_64bit = FALSE; - buf0 = FALSE; - buf1 = FALSE; - - /*------------------------------------------------------------------ - * Set memory controller options reg 1, SDRAM_MCOPT1. - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_MCOPT1, val); - mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK | - SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK | - SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK | - SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK | - SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK | - SDRAM_MCOPT1_DREF_MASK); - - mcopt1 |= SDRAM_MCOPT1_QDEP; - mcopt1 |= SDRAM_MCOPT1_PMU_OPEN; - mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED; - mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED; - mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED; - mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] != SDRAM_NONE) { - /* test ecc support */ - ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11); - if (ecc != 0x02) /* ecc not supported */ - ecc_enabled = FALSE; - - /* test bank count */ - bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17); - if (bankcount == 0x04) /* bank count = 4 */ - mcopt1 |= SDRAM_MCOPT1_4_BANKS; - else /* bank count = 8 */ - mcopt1 |= SDRAM_MCOPT1_8_BANKS; - - /* test DDR type */ - ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2); - /* test for buffered/unbuffered, registered, differential clocks */ - registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20); - attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21); - - /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */ - if (dimm_num == 0) { - if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */ - mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE; - if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */ - mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE; - if (registered == 1) { /* DDR2 always buffered */ - /* TODO: what about above comments ? */ - mcopt1 |= SDRAM_MCOPT1_RDEN; - buf0 = TRUE; - } else { - /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */ - if ((attribute & 0x02) == 0x00) { - /* buffered not supported */ - buf0 = FALSE; - } else { - mcopt1 |= SDRAM_MCOPT1_RDEN; - buf0 = TRUE; - } - } - } - else if (dimm_num == 1) { - if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */ - mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE; - if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */ - mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE; - if (registered == 1) { - /* DDR2 always buffered */ - mcopt1 |= SDRAM_MCOPT1_RDEN; - buf1 = TRUE; - } else { - if ((attribute & 0x02) == 0x00) { - /* buffered not supported */ - buf1 = FALSE; - } else { - mcopt1 |= SDRAM_MCOPT1_RDEN; - buf1 = TRUE; - } - } - } - - /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */ - data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) + - (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8); - - switch (data_width) { - case 72: - case 64: - dimm_64bit = TRUE; - break; - case 40: - case 32: - dimm_32bit = TRUE; - break; - default: - printf("WARNING: Detected a DIMM with a data width of %lu bits.\n", - data_width); - printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n"); - break; - } - } - } - - /* verify matching properties */ - if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) { - if (buf0 != buf1) { - printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n"); - spd_ddr_init_hang (); - } - } - - if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) { - printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n"); - spd_ddr_init_hang (); - } - else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) { - mcopt1 |= SDRAM_MCOPT1_DMWD_64; - } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) { - mcopt1 |= SDRAM_MCOPT1_DMWD_32; - } else { - printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n"); - spd_ddr_init_hang (); - } - - if (ecc_enabled == TRUE) - mcopt1 |= SDRAM_MCOPT1_MCHK_GEN; - else - mcopt1 |= SDRAM_MCOPT1_MCHK_NON; - - mtsdram(SDRAM_MCOPT1, mcopt1); -} - -/*-----------------------------------------------------------------------------+ - * program_codt. - *-----------------------------------------------------------------------------*/ -static void program_codt(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long codt; - unsigned long modt0 = 0; - unsigned long modt1 = 0; - unsigned long modt2 = 0; - unsigned long modt3 = 0; - unsigned char dimm_num; - unsigned char dimm_rank; - unsigned char total_rank = 0; - unsigned char total_dimm = 0; - unsigned char dimm_type = 0; - unsigned char firstSlot = 0; - - /*------------------------------------------------------------------ - * Set the SDRAM Controller On Die Termination Register - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_CODT, codt); - codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END); - codt |= SDRAM_CODT_IO_NMODE; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] != SDRAM_NONE) { - dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5); - if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) { - dimm_rank = (dimm_rank & 0x0F) + 1; - dimm_type = SDRAM_DDR2; - } else { - dimm_rank = dimm_rank & 0x0F; - dimm_type = SDRAM_DDR1; - } - - total_rank += dimm_rank; - total_dimm++; - if ((dimm_num == 0) && (total_dimm == 1)) - firstSlot = TRUE; - else - firstSlot = FALSE; - } - } - if (dimm_type == SDRAM_DDR2) { - codt |= SDRAM_CODT_DQS_1_8_V_DDR2; - if ((total_dimm == 1) && (firstSlot == TRUE)) { - if (total_rank == 1) { /* PUUU */ - codt |= CALC_ODT_R(0); - modt0 = CALC_ODT_W(0); - modt1 = 0x00000000; - modt2 = 0x00000000; - modt3 = 0x00000000; - } - if (total_rank == 2) { /* PPUU */ - codt |= CALC_ODT_R(0) | CALC_ODT_R(1); - modt0 = CALC_ODT_W(0) | CALC_ODT_W(1); - modt1 = 0x00000000; - modt2 = 0x00000000; - modt3 = 0x00000000; - } - } else if ((total_dimm == 1) && (firstSlot != TRUE)) { - if (total_rank == 1) { /* UUPU */ - codt |= CALC_ODT_R(2); - modt0 = 0x00000000; - modt1 = 0x00000000; - modt2 = CALC_ODT_W(2); - modt3 = 0x00000000; - } - if (total_rank == 2) { /* UUPP */ - codt |= CALC_ODT_R(2) | CALC_ODT_R(3); - modt0 = 0x00000000; - modt1 = 0x00000000; - modt2 = CALC_ODT_W(2) | CALC_ODT_W(3); - modt3 = 0x00000000; - } - } - if (total_dimm == 2) { - if (total_rank == 2) { /* PUPU */ - codt |= CALC_ODT_R(0) | CALC_ODT_R(2); - modt0 = CALC_ODT_RW(2); - modt1 = 0x00000000; - modt2 = CALC_ODT_RW(0); - modt3 = 0x00000000; - } - if (total_rank == 4) { /* PPPP */ - codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | - CALC_ODT_R(2) | CALC_ODT_R(3); - modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3); - modt1 = 0x00000000; - modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1); - modt3 = 0x00000000; - } - } - } else { - codt |= SDRAM_CODT_DQS_2_5_V_DDR1; - modt0 = 0x00000000; - modt1 = 0x00000000; - modt2 = 0x00000000; - modt3 = 0x00000000; - - if (total_dimm == 1) { - if (total_rank == 1) - codt |= 0x00800000; - if (total_rank == 2) - codt |= 0x02800000; - } - if (total_dimm == 2) { - if (total_rank == 2) - codt |= 0x08800000; - if (total_rank == 4) - codt |= 0x2a800000; - } - } - - debug("nb of dimm %d\n", total_dimm); - debug("nb of rank %d\n", total_rank); - if (total_dimm == 1) - debug("dimm in slot %d\n", firstSlot); - - mtsdram(SDRAM_CODT, codt); - mtsdram(SDRAM_MODT0, modt0); - mtsdram(SDRAM_MODT1, modt1); - mtsdram(SDRAM_MODT2, modt2); - mtsdram(SDRAM_MODT3, modt3); -} - -/*-----------------------------------------------------------------------------+ - * program_initplr. - *-----------------------------------------------------------------------------*/ -static void program_initplr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks, - ddr_cas_id_t selected_cas, - int write_recovery) -{ - u32 cas = 0; - u32 odt = 0; - u32 ods = 0; - u32 mr; - u32 wr; - u32 emr; - u32 emr2; - u32 emr3; - int dimm_num; - int total_dimm = 0; - - /****************************************************** - ** Assumption: if more than one DIMM, all DIMMs are the same - ** as already checked in check_memory_type - ******************************************************/ - - if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) { - mtsdram(SDRAM_INITPLR0, 0x81B80000); - mtsdram(SDRAM_INITPLR1, 0x81900400); - mtsdram(SDRAM_INITPLR2, 0x81810000); - mtsdram(SDRAM_INITPLR3, 0xff800162); - mtsdram(SDRAM_INITPLR4, 0x81900400); - mtsdram(SDRAM_INITPLR5, 0x86080000); - mtsdram(SDRAM_INITPLR6, 0x86080000); - mtsdram(SDRAM_INITPLR7, 0x81000062); - } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) { - switch (selected_cas) { - case DDR_CAS_3: - cas = 3 << 4; - break; - case DDR_CAS_4: - cas = 4 << 4; - break; - case DDR_CAS_5: - cas = 5 << 4; - break; - default: - printf("ERROR: ucode error on selected_cas value %d", selected_cas); - spd_ddr_init_hang (); - break; - } - -#if 0 - /* - * ToDo - Still a problem with the write recovery: - * On the Corsair CM2X512-5400C4 module, setting write recovery - * in the INITPLR reg to the value calculated in program_mode() - * results in not correctly working DDR2 memory (crash after - * relocation). - * - * So for now, set the write recovery to 3. This seems to work - * on the Corair module too. - * - * 2007-03-01, sr - */ - switch (write_recovery) { - case 3: - wr = WRITE_RECOV_3; - break; - case 4: - wr = WRITE_RECOV_4; - break; - case 5: - wr = WRITE_RECOV_5; - break; - case 6: - wr = WRITE_RECOV_6; - break; - default: - printf("ERROR: write recovery not support (%d)", write_recovery); - spd_ddr_init_hang (); - break; - } -#else - wr = WRITE_RECOV_3; /* test-only, see description above */ -#endif - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) - if (dimm_populated[dimm_num] != SDRAM_NONE) - total_dimm++; - if (total_dimm == 1) { - odt = ODT_150_OHM; - ods = ODS_FULL; - } else if (total_dimm == 2) { - odt = ODT_75_OHM; - ods = ODS_REDUCED; - } else { - printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm); - spd_ddr_init_hang (); - } - - mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas; - emr = CMD_EMR | SELECT_EMR | odt | ods; - emr2 = CMD_EMR | SELECT_EMR2; - emr3 = CMD_EMR | SELECT_EMR3; - /* NOP - Wait 106 MemClk cycles */ - mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP | - SDRAM_INITPLR_IMWT_ENCODE(106)); - udelay(1000); - /* precharge 4 MemClk cycles */ - mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE | - SDRAM_INITPLR_IMWT_ENCODE(4)); - /* EMR2 - Wait tMRD (2 MemClk cycles) */ - mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 | - SDRAM_INITPLR_IMWT_ENCODE(2)); - /* EMR3 - Wait tMRD (2 MemClk cycles) */ - mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 | - SDRAM_INITPLR_IMWT_ENCODE(2)); - /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */ - mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr | - SDRAM_INITPLR_IMWT_ENCODE(2)); - /* MR w/ DLL reset - 200 cycle wait for DLL reset */ - mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET | - SDRAM_INITPLR_IMWT_ENCODE(200)); - udelay(1000); - /* precharge 4 MemClk cycles */ - mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE | - SDRAM_INITPLR_IMWT_ENCODE(4)); - /* Refresh 25 MemClk cycles */ - mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH | - SDRAM_INITPLR_IMWT_ENCODE(25)); - /* Refresh 25 MemClk cycles */ - mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH | - SDRAM_INITPLR_IMWT_ENCODE(25)); - /* Refresh 25 MemClk cycles */ - mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH | - SDRAM_INITPLR_IMWT_ENCODE(25)); - /* Refresh 25 MemClk cycles */ - mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH | - SDRAM_INITPLR_IMWT_ENCODE(25)); - /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */ - mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr | - SDRAM_INITPLR_IMWT_ENCODE(2)); - /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */ - mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF | - SDRAM_INITPLR_IMWT_ENCODE(2) | emr); - /* EMR OCD Exit */ - mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr | - SDRAM_INITPLR_IMWT_ENCODE(2)); - } else { - printf("ERROR: ucode error as unknown DDR type in program_initplr"); - spd_ddr_init_hang (); - } -} - -/*------------------------------------------------------------------ - * This routine programs the SDRAM_MMODE register. - * the selected_cas is an output parameter, that will be passed - * by caller to call the above program_initplr( ) - *-----------------------------------------------------------------*/ -static void program_mode(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks, - ddr_cas_id_t *selected_cas, - int *write_recovery) -{ - unsigned long dimm_num; - unsigned long sdram_ddr1; - unsigned long t_wr_ns; - unsigned long t_wr_clk; - unsigned long cas_bit; - unsigned long cas_index; - unsigned long sdram_freq; - unsigned long ddr_check; - unsigned long mmode; - unsigned long tcyc_reg; - unsigned long cycle_2_0_clk; - unsigned long cycle_2_5_clk; - unsigned long cycle_3_0_clk; - unsigned long cycle_4_0_clk; - unsigned long cycle_5_0_clk; - unsigned long max_2_0_tcyc_ns_x_100; - unsigned long max_2_5_tcyc_ns_x_100; - unsigned long max_3_0_tcyc_ns_x_100; - unsigned long max_4_0_tcyc_ns_x_100; - unsigned long max_5_0_tcyc_ns_x_100; - unsigned long cycle_time_ns_x_100[3]; - PPC4xx_SYS_INFO board_cfg; - unsigned char cas_2_0_available; - unsigned char cas_2_5_available; - unsigned char cas_3_0_available; - unsigned char cas_4_0_available; - unsigned char cas_5_0_available; - unsigned long sdr_ddrpll; - - /*------------------------------------------------------------------ - * Get the board configuration info. - *-----------------------------------------------------------------*/ - get_sys_info(&board_cfg); - - mfsdr(SDR0_DDR0, sdr_ddrpll); - sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1); - debug("sdram_freq=%lu\n", sdram_freq); - - /*------------------------------------------------------------------ - * Handle the timing. We need to find the worst case timing of all - * the dimm modules installed. - *-----------------------------------------------------------------*/ - t_wr_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; - cas_4_0_available = TRUE; - cas_5_0_available = TRUE; - max_2_0_tcyc_ns_x_100 = 10; - max_2_5_tcyc_ns_x_100 = 10; - max_3_0_tcyc_ns_x_100 = 10; - max_4_0_tcyc_ns_x_100 = 10; - max_5_0_tcyc_ns_x_100 = 10; - sdram_ddr1 = TRUE; - - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_populated[dimm_num] != SDRAM_NONE) { - if (dimm_populated[dimm_num] == SDRAM_DDR1) - sdram_ddr1 = TRUE; - else - sdram_ddr1 = FALSE; - - /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */ - cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); - debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit); - - /* For a particular DIMM, grab the three CAS values it supports */ - for (cas_index = 0; cas_index < 3; cas_index++) { - switch (cas_index) { - case 0: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); - break; - case 1: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); - break; - default: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); - break; - } - - if ((tcyc_reg & 0x0F) >= 10) { - if ((tcyc_reg & 0x0F) == 0x0D) { - /* Convert from hex to decimal */ - cycle_time_ns_x_100[cas_index] = - (((tcyc_reg & 0xF0) >> 4) * 100) + 75; - } else { - printf("ERROR: SPD reported Tcyc is incorrect for DIMM " - "in slot %d\n", (unsigned int)dimm_num); - spd_ddr_init_hang (); - } - } else { - /* Convert from hex to decimal */ - cycle_time_ns_x_100[cas_index] = - (((tcyc_reg & 0xF0) >> 4) * 100) + - ((tcyc_reg & 0x0F)*10); - } - debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index, - cycle_time_ns_x_100[cas_index]); - } - - /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */ - /* supported for a particular DIMM. */ - cas_index = 0; - - if (sdram_ddr1) { - /* - * DDR devices use the following bitmask for CAS latency: - * Bit 7 6 5 4 3 2 1 0 - * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0 - */ - if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) && - (cycle_time_ns_x_100[cas_index] != 0)) { - max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, - cycle_time_ns_x_100[cas_index]); - cas_index++; - } else { - if (cas_index != 0) - cas_index++; - cas_4_0_available = FALSE; - } - - if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && - (cycle_time_ns_x_100[cas_index] != 0)) { - max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, - cycle_time_ns_x_100[cas_index]); - cas_index++; - } else { - if (cas_index != 0) - cas_index++; - cas_3_0_available = FALSE; - } - - if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && - (cycle_time_ns_x_100[cas_index] != 0)) { - max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100, - cycle_time_ns_x_100[cas_index]); - cas_index++; - } else { - if (cas_index != 0) - cas_index++; - cas_2_5_available = FALSE; - } - - if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && - (cycle_time_ns_x_100[cas_index] != 0)) { - max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100, - cycle_time_ns_x_100[cas_index]); - cas_index++; - } else { - if (cas_index != 0) - cas_index++; - cas_2_0_available = FALSE; - } - } else { - /* - * DDR2 devices use the following bitmask for CAS latency: - * Bit 7 6 5 4 3 2 1 0 - * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD - */ - if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) && - (cycle_time_ns_x_100[cas_index] != 0)) { - max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100, - cycle_time_ns_x_100[cas_index]); - cas_index++; - } else { - if (cas_index != 0) - cas_index++; - cas_5_0_available = FALSE; - } - - if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && - (cycle_time_ns_x_100[cas_index] != 0)) { - max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, - cycle_time_ns_x_100[cas_index]); - cas_index++; - } else { - if (cas_index != 0) - cas_index++; - cas_4_0_available = FALSE; - } - - if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && - (cycle_time_ns_x_100[cas_index] != 0)) { - max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, - cycle_time_ns_x_100[cas_index]); - cas_index++; - } else { - if (cas_index != 0) - cas_index++; - cas_3_0_available = FALSE; - } - } - } - } - - /*------------------------------------------------------------------ - * Set the SDRAM mode, SDRAM_MMODE - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_MMODE, mmode); - mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK); - - /* add 10 here because of rounding problems */ - cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10; - cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10; - cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10; - cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10; - cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10; - debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk); - debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk); - debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk); - - if (sdram_ddr1 == TRUE) { /* DDR1 */ - if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) { - mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK; - *selected_cas = DDR_CAS_2; - } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) { - mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK; - *selected_cas = DDR_CAS_2_5; - } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { - mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK; - *selected_cas = DDR_CAS_3; - } else { - printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n"); - printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); - printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n"); - spd_ddr_init_hang (); - } - } else { /* DDR2 */ - debug("cas_3_0_available=%d\n", cas_3_0_available); - debug("cas_4_0_available=%d\n", cas_4_0_available); - debug("cas_5_0_available=%d\n", cas_5_0_available); - if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { - mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK; - *selected_cas = DDR_CAS_3; - } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) { - mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK; - *selected_cas = DDR_CAS_4; - } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) { - mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK; - *selected_cas = DDR_CAS_5; - } else { - printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n"); - printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n"); - printf("Make sure the PLB speed is within the supported range of the DIMMs.\n"); - printf("cas3=%d cas4=%d cas5=%d\n", - cas_3_0_available, cas_4_0_available, cas_5_0_available); - printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n", - sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); - spd_ddr_init_hang (); - } - } - - if (sdram_ddr1 == TRUE) - mmode |= SDRAM_MMODE_WR_DDR1; - else { - - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_populated[dimm_num] != SDRAM_NONE) - t_wr_ns = max(t_wr_ns, - spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); - } - - /* - * convert from nanoseconds to ddr clocks - * round up if necessary - */ - t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns); - if (sdram_freq != ddr_check) - t_wr_clk++; - - switch (t_wr_clk) { - case 0: - case 1: - case 2: - case 3: - mmode |= SDRAM_MMODE_WR_DDR2_3_CYC; - break; - case 4: - mmode |= SDRAM_MMODE_WR_DDR2_4_CYC; - break; - case 5: - mmode |= SDRAM_MMODE_WR_DDR2_5_CYC; - break; - default: - mmode |= SDRAM_MMODE_WR_DDR2_6_CYC; - break; - } - *write_recovery = t_wr_clk; - } - - debug("CAS latency = %d\n", *selected_cas); - debug("Write recovery = %d\n", *write_recovery); - - mtsdram(SDRAM_MMODE, mmode); -} - -/*-----------------------------------------------------------------------------+ - * program_rtr. - *-----------------------------------------------------------------------------*/ -static void program_rtr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - PPC4xx_SYS_INFO board_cfg; - unsigned long max_refresh_rate; - unsigned long dimm_num; - unsigned long refresh_rate_type; - unsigned long refresh_rate; - unsigned long rint; - unsigned long sdram_freq; - unsigned long sdr_ddrpll; - unsigned long val; - - /*------------------------------------------------------------------ - * Get the board configuration info. - *-----------------------------------------------------------------*/ - get_sys_info(&board_cfg); - - /*------------------------------------------------------------------ - * Set the SDRAM Refresh Timing Register, SDRAM_RTR - *-----------------------------------------------------------------*/ - mfsdr(SDR0_DDR0, sdr_ddrpll); - sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); - - max_refresh_rate = 0; - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] != SDRAM_NONE) { - - refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12); - refresh_rate_type &= 0x7F; - switch (refresh_rate_type) { - case 0: - refresh_rate = 15625; - break; - case 1: - refresh_rate = 3906; - break; - case 2: - refresh_rate = 7812; - break; - case 3: - refresh_rate = 31250; - break; - case 4: - refresh_rate = 62500; - break; - case 5: - refresh_rate = 125000; - break; - default: - refresh_rate = 0; - printf("ERROR: DIMM %d unsupported refresh rate/type.\n", - (unsigned int)dimm_num); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - break; - } - - max_refresh_rate = max(max_refresh_rate, refresh_rate); - } - } - - rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION); - mfsdram(SDRAM_RTR, val); - mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) | - (SDRAM_RTR_RINT_ENCODE(rint))); -} - -/*------------------------------------------------------------------ - * This routine programs the SDRAM_TRx registers. - *-----------------------------------------------------------------*/ -static void program_tr(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long sdram_ddr1; - unsigned long t_rp_ns; - unsigned long t_rcd_ns; - unsigned long t_rrd_ns; - unsigned long t_ras_ns; - unsigned long t_rc_ns; - unsigned long t_rfc_ns; - unsigned long t_wpc_ns; - unsigned long t_wtr_ns; - unsigned long t_rpc_ns; - unsigned long t_rp_clk; - unsigned long t_rcd_clk; - unsigned long t_rrd_clk; - unsigned long t_ras_clk; - unsigned long t_rc_clk; - unsigned long t_rfc_clk; - unsigned long t_wpc_clk; - unsigned long t_wtr_clk; - unsigned long t_rpc_clk; - unsigned long sdtr1, sdtr2, sdtr3; - unsigned long ddr_check; - unsigned long sdram_freq; - unsigned long sdr_ddrpll; - - PPC4xx_SYS_INFO board_cfg; - - /*------------------------------------------------------------------ - * Get the board configuration info. - *-----------------------------------------------------------------*/ - get_sys_info(&board_cfg); - - mfsdr(SDR0_DDR0, sdr_ddrpll); - sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); - - /*------------------------------------------------------------------ - * Handle the timing. We need to find the worst case timing of all - * the dimm modules installed. - *-----------------------------------------------------------------*/ - t_rp_ns = 0; - t_rrd_ns = 0; - t_rcd_ns = 0; - t_ras_ns = 0; - t_rc_ns = 0; - t_rfc_ns = 0; - t_wpc_ns = 0; - t_wtr_ns = 0; - t_rpc_ns = 0; - sdram_ddr1 = TRUE; - - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_populated[dimm_num] != SDRAM_NONE) { - if (dimm_populated[dimm_num] == SDRAM_DDR2) - sdram_ddr1 = TRUE; - else - sdram_ddr1 = FALSE; - - t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); - t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); - t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2); - t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30)); - t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41)); - t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42)); - } - } - - /*------------------------------------------------------------------ - * Set the SDRAM Timing Reg 1, SDRAM_TR1 - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_SDTR1, sdtr1); - sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK | - SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK); - - /* default values */ - sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK; - sdtr1 |= SDRAM_SDTR1_RTW_2_CLK; - - /* normal operations */ - sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK; - sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK; - - mtsdram(SDRAM_SDTR1, sdtr1); - - /*------------------------------------------------------------------ - * Set the SDRAM Timing Reg 2, SDRAM_TR2 - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_SDTR2, sdtr2); - sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK | - SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK | - SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK | - SDRAM_SDTR2_RRD_MASK); - - /* - * convert t_rcd from nanoseconds to ddr clocks - * round up if necessary - */ - t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns); - if (sdram_freq != ddr_check) - t_rcd_clk++; - - switch (t_rcd_clk) { - case 0: - case 1: - sdtr2 |= SDRAM_SDTR2_RCD_1_CLK; - break; - case 2: - sdtr2 |= SDRAM_SDTR2_RCD_2_CLK; - break; - case 3: - sdtr2 |= SDRAM_SDTR2_RCD_3_CLK; - break; - case 4: - sdtr2 |= SDRAM_SDTR2_RCD_4_CLK; - break; - default: - sdtr2 |= SDRAM_SDTR2_RCD_5_CLK; - break; - } - - if (sdram_ddr1 == TRUE) { /* DDR1 */ - if (sdram_freq < 200000000) { - sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; - sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; - sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; - } else { - sdtr2 |= SDRAM_SDTR2_WTR_2_CLK; - sdtr2 |= SDRAM_SDTR2_WPC_3_CLK; - sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; - } - } else { /* DDR2 */ - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_populated[dimm_num] != SDRAM_NONE) { - t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); - t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2); - t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2); - } - } - - /* - * convert from nanoseconds to ddr clocks - * round up if necessary - */ - t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns); - if (sdram_freq != ddr_check) - t_wpc_clk++; - - switch (t_wpc_clk) { - case 0: - case 1: - case 2: - sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; - break; - case 3: - sdtr2 |= SDRAM_SDTR2_WPC_3_CLK; - break; - case 4: - sdtr2 |= SDRAM_SDTR2_WPC_4_CLK; - break; - case 5: - sdtr2 |= SDRAM_SDTR2_WPC_5_CLK; - break; - default: - sdtr2 |= SDRAM_SDTR2_WPC_6_CLK; - break; - } - - /* - * convert from nanoseconds to ddr clocks - * round up if necessary - */ - t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns); - if (sdram_freq != ddr_check) - t_wtr_clk++; - - switch (t_wtr_clk) { - case 0: - case 1: - sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; - break; - case 2: - sdtr2 |= SDRAM_SDTR2_WTR_2_CLK; - break; - case 3: - sdtr2 |= SDRAM_SDTR2_WTR_3_CLK; - break; - default: - sdtr2 |= SDRAM_SDTR2_WTR_4_CLK; - break; - } - - /* - * convert from nanoseconds to ddr clocks - * round up if necessary - */ - t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns); - if (sdram_freq != ddr_check) - t_rpc_clk++; - - switch (t_rpc_clk) { - case 0: - case 1: - case 2: - sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; - break; - case 3: - sdtr2 |= SDRAM_SDTR2_RPC_3_CLK; - break; - default: - sdtr2 |= SDRAM_SDTR2_RPC_4_CLK; - break; - } - } - - /* default value */ - sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK; - - /* - * convert t_rrd from nanoseconds to ddr clocks - * round up if necessary - */ - t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns); - if (sdram_freq != ddr_check) - t_rrd_clk++; - - if (t_rrd_clk == 3) - sdtr2 |= SDRAM_SDTR2_RRD_3_CLK; - else - sdtr2 |= SDRAM_SDTR2_RRD_2_CLK; - - /* - * convert t_rp from nanoseconds to ddr clocks - * round up if necessary - */ - t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns); - if (sdram_freq != ddr_check) - t_rp_clk++; - - switch (t_rp_clk) { - case 0: - case 1: - case 2: - case 3: - sdtr2 |= SDRAM_SDTR2_RP_3_CLK; - break; - case 4: - sdtr2 |= SDRAM_SDTR2_RP_4_CLK; - break; - case 5: - sdtr2 |= SDRAM_SDTR2_RP_5_CLK; - break; - case 6: - sdtr2 |= SDRAM_SDTR2_RP_6_CLK; - break; - default: - sdtr2 |= SDRAM_SDTR2_RP_7_CLK; - break; - } - - mtsdram(SDRAM_SDTR2, sdtr2); - - /*------------------------------------------------------------------ - * Set the SDRAM Timing Reg 3, SDRAM_TR3 - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_SDTR3, sdtr3); - sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK | - SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK); - - /* - * convert t_ras from nanoseconds to ddr clocks - * round up if necessary - */ - t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns); - if (sdram_freq != ddr_check) - t_ras_clk++; - - sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk); - - /* - * convert t_rc from nanoseconds to ddr clocks - * round up if necessary - */ - t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns); - if (sdram_freq != ddr_check) - t_rc_clk++; - - sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk); - - /* default xcs value */ - sdtr3 |= SDRAM_SDTR3_XCS; - - /* - * convert t_rfc from nanoseconds to ddr clocks - * round up if necessary - */ - t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION); - ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns); - if (sdram_freq != ddr_check) - t_rfc_clk++; - - sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk); - - mtsdram(SDRAM_SDTR3, sdtr3); -} - -/*-----------------------------------------------------------------------------+ - * program_bxcf. - *-----------------------------------------------------------------------------*/ -static void program_bxcf(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long num_col_addr; - unsigned long num_ranks; - unsigned long num_banks; - unsigned long mode; - unsigned long ind_rank; - unsigned long ind; - unsigned long ind_bank; - unsigned long bank_0_populated; - - /*------------------------------------------------------------------ - * Set the BxCF regs. First, wipe out the bank config registers. - *-----------------------------------------------------------------*/ - mtsdram(SDRAM_MB0CF, 0x00000000); - mtsdram(SDRAM_MB1CF, 0x00000000); - mtsdram(SDRAM_MB2CF, 0x00000000); - mtsdram(SDRAM_MB3CF, 0x00000000); - - mode = SDRAM_BXCF_M_BE_ENABLE; - - bank_0_populated = 0; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] != SDRAM_NONE) { - num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); - num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5); - if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) - num_ranks = (num_ranks & 0x0F) +1; - else - num_ranks = num_ranks & 0x0F; - - num_banks = spd_read(iic0_dimm_addr[dimm_num], 17); - - for (ind_bank = 0; ind_bank < 2; ind_bank++) { - if (num_banks == 4) - ind = 0; - else - ind = 5 << 8; - switch (num_col_addr) { - case 0x08: - mode |= (SDRAM_BXCF_M_AM_0 + ind); - break; - case 0x09: - mode |= (SDRAM_BXCF_M_AM_1 + ind); - break; - case 0x0A: - mode |= (SDRAM_BXCF_M_AM_2 + ind); - break; - case 0x0B: - mode |= (SDRAM_BXCF_M_AM_3 + ind); - break; - case 0x0C: - mode |= (SDRAM_BXCF_M_AM_4 + ind); - break; - default: - printf("DDR-SDRAM: DIMM %d BxCF configuration.\n", - (unsigned int)dimm_num); - printf("ERROR: Unsupported value for number of " - "column addresses: %d.\n", (unsigned int)num_col_addr); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - } - } - - if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1)) - bank_0_populated = 1; - - for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) { - mtsdram(SDRAM_MB0CF + - ((dimm_num + bank_0_populated + ind_rank) << 2), - mode); - } - } - } -} - -/*------------------------------------------------------------------ - * program memory queue. - *-----------------------------------------------------------------*/ -static void program_memory_queue(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - phys_size_t rank_base_addr; - unsigned long rank_reg; - phys_size_t rank_size_bytes; - unsigned long rank_size_id; - unsigned long num_ranks; - unsigned long baseadd_size; - unsigned long i; - unsigned long bank_0_populated = 0; - phys_size_t total_size = 0; - - /*------------------------------------------------------------------ - * Reset the rank_base_address. - *-----------------------------------------------------------------*/ - rank_reg = SDRAM_R0BAS; - - rank_base_addr = 0x00000000; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] != SDRAM_NONE) { - num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5); - if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) - num_ranks = (num_ranks & 0x0F) + 1; - else - num_ranks = num_ranks & 0x0F; - - rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); - - /*------------------------------------------------------------------ - * Set the sizes - *-----------------------------------------------------------------*/ - baseadd_size = 0; - switch (rank_size_id) { - case 0x01: - baseadd_size |= SDRAM_RXBAS_SDSZ_1024; - total_size = 1024; - break; - case 0x02: - baseadd_size |= SDRAM_RXBAS_SDSZ_2048; - total_size = 2048; - break; - case 0x04: - baseadd_size |= SDRAM_RXBAS_SDSZ_4096; - total_size = 4096; - break; - case 0x08: - baseadd_size |= SDRAM_RXBAS_SDSZ_32; - total_size = 32; - break; - case 0x10: - baseadd_size |= SDRAM_RXBAS_SDSZ_64; - total_size = 64; - break; - case 0x20: - baseadd_size |= SDRAM_RXBAS_SDSZ_128; - total_size = 128; - break; - case 0x40: - baseadd_size |= SDRAM_RXBAS_SDSZ_256; - total_size = 256; - break; - case 0x80: - baseadd_size |= SDRAM_RXBAS_SDSZ_512; - total_size = 512; - break; - default: - printf("DDR-SDRAM: DIMM %d memory queue configuration.\n", - (unsigned int)dimm_num); - printf("ERROR: Unsupported value for the banksize: %d.\n", - (unsigned int)rank_size_id); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - spd_ddr_init_hang (); - } - rank_size_bytes = total_size << 20; - - if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1)) - bank_0_populated = 1; - - for (i = 0; i < num_ranks; i++) { - mtdcr_any(rank_reg+i+dimm_num+bank_0_populated, - (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) | - baseadd_size)); - rank_base_addr += rank_size_bytes; - } - } - } - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) - /* - * Enable high bandwidth access - * This is currently not used, but with this setup - * it is possible to use it later on in e.g. the Linux - * EMAC driver for performance gain. - */ - mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */ - mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */ - - /* - * Set optimal value for Memory Queue HB/LL Configuration registers - */ - mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) | - SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE | - SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL); - mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) | - SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE | - SDRAM_CONF1LL_RPLM); - mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); -#endif -} - -#ifdef CONFIG_DDR_ECC -/*-----------------------------------------------------------------------------+ - * program_ecc. - *-----------------------------------------------------------------------------*/ -static void program_ecc(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks, - unsigned long tlb_word2_i_value) -{ - unsigned long dimm_num; - unsigned long ecc; - - ecc = 0; - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_populated[dimm_num] != SDRAM_NONE) - ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11)); - } - if (ecc == 0) - return; - - do_program_ecc(tlb_word2_i_value); -} -#endif - -#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -/*-----------------------------------------------------------------------------+ - * program_DQS_calibration. - *-----------------------------------------------------------------------------*/ -static void program_DQS_calibration(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long val; - -#ifdef HARD_CODED_DQS /* calibration test with hardvalues */ - mtsdram(SDRAM_RQDC, 0x80000037); - mtsdram(SDRAM_RDCC, 0x40000000); - mtsdram(SDRAM_RFDC, 0x000001DF); - - test(); -#else - /*------------------------------------------------------------------ - * Program RDCC register - * Read sample cycle auto-update enable - *-----------------------------------------------------------------*/ - - mfsdram(SDRAM_RDCC, val); - mtsdram(SDRAM_RDCC, - (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK)) - | SDRAM_RDCC_RSAE_ENABLE); - - /*------------------------------------------------------------------ - * Program RQDC register - * Internal DQS delay mechanism enable - *-----------------------------------------------------------------*/ - mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38))); - - /*------------------------------------------------------------------ - * Program RFDC register - * Set Feedback Fractional Oversample - * Auto-detect read sample cycle enable - * Set RFOS to 1/4 of memclk cycle (0x3f) - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_RFDC, val); - mtsdram(SDRAM_RFDC, - (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK | - SDRAM_RFDC_RFFD_MASK)) - | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) | - SDRAM_RFDC_RFFD_ENCODE(0))); - - DQS_calibration_process(); -#endif -} - -static int short_mem_test(void) -{ - u32 *membase; - u32 bxcr_num; - u32 bxcf; - int i; - int j; - phys_size_t base_addr; - u32 test[NUMMEMTESTS][NUMMEMWORDS] = { - {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, - {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, - {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, - {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, - {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, - {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, - {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, - {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} }; - int l; - - for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { - mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf); - - /* Banks enabled */ - if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { - /* Bank is enabled */ - - /* - * Only run test on accessable memory (below 2GB) - */ - base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)); - if (base_addr >= CONFIG_MAX_MEM_MAPPED) - continue; - - /*------------------------------------------------------------------ - * Run the short memory test. - *-----------------------------------------------------------------*/ - membase = (u32 *)(u32)base_addr; - - for (i = 0; i < NUMMEMTESTS; i++) { - for (j = 0; j < NUMMEMWORDS; j++) { - membase[j] = test[i][j]; - ppcDcbf((u32)&(membase[j])); - } - sync(); - for (l=0; l max_pass_length) { - max_pass_length = current_pass_length; - max_start = current_start; - max_end = rffd; - } - } - } else { - current_pass_length = 0; - current_fail_length++; - - if (current_fail_length >= (dly_val >> 2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; - break; - } - } - } - } /* for rffd */ - - /*------------------------------------------------------------------ - * Set the average RFFD value - *-----------------------------------------------------------------*/ - rffd_average = ((max_start + max_end) >> 1); - - if (rffd_average < 0) - rffd_average = 0; - - if (rffd_average > SDRAM_RFDC_RFFD_MAX) - rffd_average = SDRAM_RFDC_RFFD_MAX; - /* now fix RFDC[RFFD] found and find RQDC[RQFD] */ - mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); - -#if !defined(CONFIG_DDR_RQDC_FIXED) - max_pass_length = 0; - max_start = 0; - max_end = 0; - current_pass_length = 0; - current_fail_length = 0; - current_start = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; - - for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { - mfsdram(SDRAM_RQDC, rqdc_reg); - rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); - - /*------------------------------------------------------------------ - * Set the timing reg for the test. - *-----------------------------------------------------------------*/ - mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd)); - - /*------------------------------------------------------------------ - * See if the rffd value passed. - *-----------------------------------------------------------------*/ - if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; - if (current_pass_length == 0) - current_start = rqfd; - - current_fail_length = 0; - current_pass_length++; - - if (current_pass_length > max_pass_length) { - max_pass_length = current_pass_length; - max_start = current_start; - max_end = rqfd; - } - } - } else { - current_pass_length = 0; - current_fail_length++; - - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; - break; - } - } - } - - rqfd_average = ((max_start + max_end) >> 1); - - /*------------------------------------------------------------------ - * Make sure we found the valid read passing window. Halt if not - *-----------------------------------------------------------------*/ - if (window_found == FALSE) { - if (rqfd_start < SDRAM_RQDC_RQFD_MAX) { - putc('\b'); - putc(slash[loopi++ % 8]); - - /* try again from with a different RQFD start value */ - rqfd_start++; - goto calibration_loop; - } - - printf("\nERROR: Cannot determine a common read delay for the " - "DIMM(s) installed.\n"); - debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__); - ppc4xx_ibm_ddr2_register_dump(); - spd_ddr_init_hang (); - } - - if (rqfd_average < 0) - rqfd_average = 0; - - if (rqfd_average > SDRAM_RQDC_RQFD_MAX) - rqfd_average = SDRAM_RQDC_RQFD_MAX; - - mtsdram(SDRAM_RQDC, - (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | - SDRAM_RQDC_RQFD_ENCODE(rqfd_average)); - - blank_string(strlen(str)); -#endif /* CONFIG_DDR_RQDC_FIXED */ - - /* - * Now complete RDSS configuration as mentioned on page 7 of the AMCC - * PowerPC440SP/SPe DDR2 application note: - * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" - */ - mfsdram(SDRAM_RTSR, val); - if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) { - mfsdram(SDRAM_RDCC, val); - if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) { - val += 0x40000000; - mtsdram(SDRAM_RDCC, val); - } - } - - mfsdram(SDRAM_DLCR, val); - debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val); - mfsdram(SDRAM_RQDC, val); - debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val); - mfsdram(SDRAM_RFDC, val); - debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val); - mfsdram(SDRAM_RDCC, val); - debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val); -} -#else /* calibration test with hardvalues */ -/*-----------------------------------------------------------------------------+ - * DQS_calibration_process. - *-----------------------------------------------------------------------------*/ -static void test(void) -{ - unsigned long dimm_num; - unsigned long ecc_temp; - unsigned long i, j; - unsigned long *membase; - unsigned long bxcf[MAXRANKS]; - unsigned long val; - char window_found; - char begin_found[MAXDIMMS]; - char end_found[MAXDIMMS]; - char search_end[MAXDIMMS]; - unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { - {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, - {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, - {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, - {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, - {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, - {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, - {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, - {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} }; - - /*------------------------------------------------------------------ - * Test to determine the best read clock delay tuning bits. - * - * Before the DDR controller can be used, the read clock delay needs to be - * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD]. - * This value cannot be hardcoded into the program because it changes - * depending on the board's setup and environment. - * To do this, all delay values are tested to see if they - * work or not. By doing this, you get groups of fails with groups of - * passing values. The idea is to find the start and end of a passing - * window and take the center of it to use as the read clock delay. - * - * A failure has to be seen first so that when we hit a pass, we know - * that it is truely the start of the window. If we get passing values - * to start off with, we don't know if we are at the start of the window. - * - * The code assumes that a failure will always be found. - * If a failure is not found, there is no easy way to get the middle - * of the passing window. I guess we can pretty much pick any value - * but some values will be better than others. Since the lowest speed - * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed), - * from experimentation it is safe to say you will always have a failure. - *-----------------------------------------------------------------*/ - mfsdram(SDRAM_MCOPT1, ecc_temp); - ecc_temp &= SDRAM_MCOPT1_MCHK_MASK; - mfsdram(SDRAM_MCOPT1, val); - mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | - SDRAM_MCOPT1_MCHK_NON); - - window_found = FALSE; - begin_found[0] = FALSE; - end_found[0] = FALSE; - search_end[0] = FALSE; - begin_found[1] = FALSE; - end_found[1] = FALSE; - search_end[1] = FALSE; - - for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { - mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]); - - /* Banks enabled */ - if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { - - /* Bank is enabled */ - membase = - (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num))); - - /*------------------------------------------------------------------ - * Run the short memory test. - *-----------------------------------------------------------------*/ - for (i = 0; i < NUMMEMTESTS; i++) { - for (j = 0; j < NUMMEMWORDS; j++) { - membase[j] = test[i][j]; - ppcDcbf((u32)&(membase[j])); - } - sync(); - for (j = 0; j < NUMMEMWORDS; j++) { - if (membase[j] != test[i][j]) { - ppcDcbf((u32)&(membase[j])); - break; - } - ppcDcbf((u32)&(membase[j])); - } - sync(); - if (j < NUMMEMWORDS) - break; - } - - /*------------------------------------------------------------------ - * See if the rffd value passed. - *-----------------------------------------------------------------*/ - if (i < NUMMEMTESTS) { - if ((end_found[dimm_num] == FALSE) && - (search_end[dimm_num] == TRUE)) { - end_found[dimm_num] = TRUE; - } - if ((end_found[0] == TRUE) && - (end_found[1] == TRUE)) - break; - } else { - if (begin_found[dimm_num] == FALSE) { - begin_found[dimm_num] = TRUE; - search_end[dimm_num] = TRUE; - } - } - } else { - begin_found[dimm_num] = TRUE; - end_found[dimm_num] = TRUE; - } - } - - if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE)) - window_found = TRUE; - - /*------------------------------------------------------------------ - * Make sure we found the valid read passing window. Halt if not - *-----------------------------------------------------------------*/ - if (window_found == FALSE) { - printf("ERROR: Cannot determine a common read delay for the " - "DIMM(s) installed.\n"); - spd_ddr_init_hang (); - } - - /*------------------------------------------------------------------ - * Restore the ECC variable to what it originally was - *-----------------------------------------------------------------*/ - mtsdram(SDRAM_MCOPT1, - (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK) - | ecc_temp); -} -#endif /* !HARD_CODED_DQS */ -#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */ - -#else /* CONFIG_SPD_EEPROM */ - -/*----------------------------------------------------------------------------- - * Function: initdram - * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller. - * The configuration is performed using static, compile- - * time parameters. - * Configures the PPC405EX(r) and PPC460EX/GT - *---------------------------------------------------------------------------*/ -phys_size_t initdram(int board_type) -{ - /* - * Only run this SDRAM init code once. For NAND booting - * targets like Kilauea, we call initdram() early from the - * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). - * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) - * which calls initdram() again. This time the controller - * mustn't be reconfigured again since we're already running - * from SDRAM. - */ -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - unsigned long val; - -#if defined(CONFIG_440) - mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS); - mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS); - mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS); - mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS); - mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */ - mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */ - mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL); - mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB); - mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB); -#endif - - /* Set Memory Bank Configuration Registers */ - - mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF); - mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF); - mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF); - mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF); - - /* Set Memory Clock Timing Register */ - - mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR); - - /* Set Refresh Time Register */ - - mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR); - - /* Set SDRAM Timing Registers */ - - mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1); - mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2); - mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3); - - /* Set Mode and Extended Mode Registers */ - - mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE); - mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE); - - /* Set Memory Controller Options 1 Register */ - - mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1); - - /* Set Manual Initialization Control Registers */ - - mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0); - mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1); - mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2); - mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3); - mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4); - mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5); - mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6); - mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7); - mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8); - mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9); - mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10); - mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11); - mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12); - mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13); - mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14); - mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15); - - /* Set On-Die Termination Registers */ - - mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT); - mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0); - mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1); - - /* Set Write Timing Register */ - - mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR); - - /* - * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and - * SDRAM0_MCOPT2[IPTR] = 1 - */ - - mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT | - SDRAM_MCOPT2_IPTR_EXECUTE)); - - /* - * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the - * completion of initialization. - */ - - do { - mfsdram(SDRAM_MCSTAT, val); - } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); - - /* Set Delay Control Registers */ - - mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR); - -#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) - mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC); - mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC); - mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC); -#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ - - /* - * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: - */ - - mfsdram(SDRAM_MCOPT2, val); - mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); - -#if defined(CONFIG_440) - /* - * Program TLB entries with caches enabled, for best performace - * while auto-calibrating and ECC generation - */ - program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0); -#endif - -#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /*------------------------------------------------------------------ - | DQS calibration. - +-----------------------------------------------------------------*/ - DQS_autocalibration(); -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ -#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ - -#if defined(CONFIG_DDR_ECC) - do_program_ecc(0); -#endif /* defined(CONFIG_DDR_ECC) */ - -#if defined(CONFIG_440) - /* - * Now after initialization (auto-calibration and ECC generation) - * remove the TLB entries with caches enabled and program again with - * desired cache functionality - */ - remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20)); - program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE); -#endif - - ppc4xx_ibm_ddr2_register_dump(); - -#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); -#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ - -#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ - - return (CONFIG_SYS_MBYTES_SDRAM << 20); -} -#endif /* CONFIG_SPD_EEPROM */ - -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#if defined(CONFIG_440) -u32 mfdcr_any(u32 dcr) -{ - u32 val; - - switch (dcr) { - case SDRAM_R0BAS + 0: - val = mfdcr(SDRAM_R0BAS + 0); - break; - case SDRAM_R0BAS + 1: - val = mfdcr(SDRAM_R0BAS + 1); - break; - case SDRAM_R0BAS + 2: - val = mfdcr(SDRAM_R0BAS + 2); - break; - case SDRAM_R0BAS + 3: - val = mfdcr(SDRAM_R0BAS + 3); - break; - default: - printf("DCR %d not defined in case statement!!!\n", dcr); - val = 0; /* just to satisfy the compiler */ - } - - return val; -} - -void mtdcr_any(u32 dcr, u32 val) -{ - switch (dcr) { - case SDRAM_R0BAS + 0: - mtdcr(SDRAM_R0BAS + 0, val); - break; - case SDRAM_R0BAS + 1: - mtdcr(SDRAM_R0BAS + 1, val); - break; - case SDRAM_R0BAS + 2: - mtdcr(SDRAM_R0BAS + 2, val); - break; - case SDRAM_R0BAS + 3: - mtdcr(SDRAM_R0BAS + 3, val); - break; - default: - printf("DCR %d not defined in case statement!!!\n", dcr); - } -} -#endif /* defined(CONFIG_440) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ - -inline void ppc4xx_ibm_ddr2_register_dump(void) -{ -#if defined(DEBUG) - printf("\nPPC4xx IBM DDR2 Register Dump:\n"); - -#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT)) - PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS); - PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS); - PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS); - PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS); -#endif /* (defined(CONFIG_440SP) || ... */ -#if defined(CONFIG_405EX) - PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR); - PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL); - PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH); - PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ); - PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT); - PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA); -#endif /* defined(CONFIG_405EX) */ - PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3); - PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT); -#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT)) - PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR); - PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS); - /* - * OPART is only used as a trigger register. - * - * No data is contained in this register, and reading or writing - * to is can cause bad things to happen (hangs). Just skip it and - * report "N/A". - */ - printf("%20s = N/A\n", "SDRAM_OPART"); -#endif /* defined(CONFIG_440SP) || ... */ - PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14); - PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15); - PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC); - PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC); - PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC); - PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR); - PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR); - PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR); - PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1); - PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2); - PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE); - PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE); - PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES); -#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT)) - PPC4xx_IBM_DDR2_DUMP_REGISTER(CID); -#endif /* defined(CONFIG_440SP) || ... */ - PPC4xx_IBM_DDR2_DUMP_REGISTER(RID); - PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR); - PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR); -#endif /* defined(DEBUG) */ -} - -#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */ diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c deleted file mode 100644 index 0283c91d84..0000000000 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ /dev/null @@ -1,1251 +0,0 @@ -/* - * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c - * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a - * DDR2 controller (non Denali Core). Those currently are: - * - * 405: 405EX - * 440/460: 440SP/440SPe/460EX/460GT/460SX - * - * (C) Copyright 2008 Applied Micro Circuits Corporation - * Adam Graham - * - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * COPYRIGHT AMCC CORPORATION 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#undef DEBUG - -#include -#include -#include -#include - -#include "ecc.h" - -#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) - -/* - * Only compile the DDR auto-calibration code for NOR boot and - * not for NAND boot (NAND SPL and NAND U-Boot - NUB) - */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - -#define MAXBXCF 4 -#define SDRAM_RXBAS_SHIFT_1M 20 - -#if defined(CONFIG_SYS_DECREMENT_PATTERNS) -#define NUMMEMTESTS 24 -#else -#define NUMMEMTESTS 8 -#endif /* CONFIG_SYS_DECREMENT_PATTERNS */ -#define NUMLOOPS 1 /* configure as you deem approporiate */ -#define NUMMEMWORDS 16 - -#define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n)) - -/* Private Structure Definitions */ - -struct autocal_regs { - u32 rffd; - u32 rqfd; -}; - -struct ddrautocal { - u32 rffd; - u32 rffd_min; - u32 rffd_max; - u32 rffd_size; - u32 rqfd; - u32 rqfd_size; - u32 rdcc; - u32 flags; -}; - -struct sdram_timing { - u32 wrdtr; - u32 clktr; -}; - -struct sdram_timing_clks { - u32 wrdtr; - u32 clktr; - u32 rdcc; - u32 flags; -}; - -struct autocal_clks { - struct sdram_timing_clks clocks; - struct ddrautocal autocal; -}; - -/*--------------------------------------------------------------------------+ - * Prototypes - *--------------------------------------------------------------------------*/ -#if defined(CONFIG_PPC4xx_DDR_METHOD_A) -static u32 DQS_calibration_methodA(struct ddrautocal *); -static u32 program_DQS_calibration_methodA(struct ddrautocal *); -#else -static u32 DQS_calibration_methodB(struct ddrautocal *); -static u32 program_DQS_calibration_methodB(struct ddrautocal *); -#endif -static int short_mem_test(u32 *); - -/* - * To provide an interface for board specific config values in this common - * DDR setup code, we implement he "weak" default functions here. They return - * the default value back to the caller. - * - * Please see include/configs/yucca.h for an example fora board specific - * implementation. - */ - -#if !defined(CONFIG_SPD_EEPROM) -u32 __ddr_wrdtr(u32 default_val) -{ - return default_val; -} -u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr"))); - -u32 __ddr_clktr(u32 default_val) -{ - return default_val; -} -u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr"))); - -/* - * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed - */ -void __spd_ddr_init_hang(void) -{ - hang(); -} -void -spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang"))); -#endif /* defined(CONFIG_SPD_EEPROM) */ - -ulong __ddr_scan_option(ulong default_val) -{ - return default_val; -} -ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option"))); - -u32 __ddr_rdss_opt(u32 default_val) -{ - return default_val; -} -u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt"))); - - -static u32 *get_membase(int bxcr_num) -{ - ulong bxcf; - u32 *membase; - -#if defined(SDRAM_R0BAS) - /* BAS from Memory Queue rank reg. */ - membase = - (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num))); - bxcf = 0; /* just to satisfy the compiler */ -#else - /* BAS from SDRAM_MBxCF mem rank reg. */ - mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); - membase = (u32 *)((bxcf & 0xfff80000) << 3); -#endif - - return membase; -} - -static inline void ecc_clear_status_reg(void) -{ - mtsdram(SDRAM_ECCES, 0xffffffff); -#if defined(SDRAM_R0BAS) - mtdcr(SDRAM_ERRSTATLL, 0xffffffff); -#endif -} - -/* - * Reset and relock memory DLL after SDRAM_CLKTR change - */ -static inline void relock_memory_DLL(void) -{ - u32 reg; - - mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE); - - do { - mfsdram(SDRAM_MCSTAT, reg); - } while (!(reg & SDRAM_MCSTAT_MIC_COMP)); - - mfsdram(SDRAM_MCOPT2, reg); - mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE); -} - -static int ecc_check_status_reg(void) -{ - u32 ecc_status; - - /* - * Compare suceeded, now check - * if got ecc error. If got an - * ecc error, then don't count - * this as a passing value - */ - mfsdram(SDRAM_ECCES, ecc_status); - if (ecc_status != 0x00000000) { - /* clear on error */ - ecc_clear_status_reg(); - /* ecc check failure */ - return 0; - } - ecc_clear_status_reg(); - sync(); - - return 1; -} - -/* return 1 if passes, 0 if fail */ -static int short_mem_test(u32 *base_address) -{ - int i, j, l; - u32 ecc_mode = 0; - - ulong test[NUMMEMTESTS][NUMMEMWORDS] = { - /* 0 */ {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, - /* 1 */ {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, - /* 2 */ {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, - /* 3 */ {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, - /* 4 */ {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, - /* 5 */ {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, - /* 6 */ {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, - /* 7 */ {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}, - -#if defined(CONFIG_SYS_DECREMENT_PATTERNS) - /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}, - /* 9 */ {0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe, - 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe, - 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe, - 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe}, - /* 10 */{0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd, - 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd, - 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd, - 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd}, - /* 11 */{0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, - 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, - 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, - 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc}, - /* 12 */{0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb, - 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb, - 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb, - 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb}, - /* 13 */{0xfffafffa, 0xfffafffa, 0xfffffffa, 0xfffafffa, - 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa, - 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa, - 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa}, - /* 14 */{0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, - 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, - 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, - 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9}, - /* 15 */{0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, - 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, - 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, - 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8}, - /* 16 */{0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7, - 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7, - 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7, - 0xfff7ffff, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7}, - /* 17 */{0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7, - 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7, - 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7, - 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7}, - /* 18 */{0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5, - 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5, - 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5, - 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5}, - /* 19 */{0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4, - 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4, - 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4, - 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4}, - /* 20 */{0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3, - 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3, - 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3, - 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3}, - /* 21 */{0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2, - 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2, - 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2, - 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2}, - /* 22 */{0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1, - 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1, - 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1, - 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1}, - /* 23 */{0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, - 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, - 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, - 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0}, -#endif /* CONFIG_SYS_DECREMENT_PATTERNS */ - }; - - mfsdram(SDRAM_MCOPT1, ecc_mode); - if ((ecc_mode & SDRAM_MCOPT1_MCHK_CHK_REP) == - SDRAM_MCOPT1_MCHK_CHK_REP) { - ecc_clear_status_reg(); - sync(); - ecc_mode = 1; - } else { - ecc_mode = 0; - } - - /* - * Run the short memory test. - */ - for (i = 0; i < NUMMEMTESTS; i++) { - for (j = 0; j < NUMMEMWORDS; j++) { - base_address[j] = test[i][j]; - ppcDcbf((ulong)&(base_address[j])); - } - sync(); - iobarrier_rw(); - for (l = 0; l < NUMLOOPS; l++) { - for (j = 0; j < NUMMEMWORDS; j++) { - if (base_address[j] != test[i][j]) { - ppcDcbf((u32)&(base_address[j])); - return 0; - } else { - if (ecc_mode) { - if (!ecc_check_status_reg()) - return 0; - } - } - ppcDcbf((u32)&(base_address[j])); - } /* for (j = 0; j < NUMMEMWORDS; j++) */ - sync(); - iobarrier_rw(); - } /* for (l=0; lSDRAM_RDCC=0x%08x\n", __func__, temp); -#endif - - pass_result = DQS_calibration_methodA(ddrcal); - - return pass_result; -} - -/* - * DQS_calibration_methodA() - * - * Autocalibration Method A - * - * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros - * ARRAY [Entire FDBK Range] FDBK_Valid_Window; initialized to all zeros - * MEMWRITE(addr, expected_data); - * for (i = 0; i < Entire DQS Range; i++) { RQDC.RQFD - * for (j = 0; j < Entire FDBK Range; j++) { RFDC.RFFD - * MEMREAD(addr, actual_data); - * if (actual_data == expected_data) { - * DQS_Valid_Window[i] = 1; RQDC.RQFD - * FDBK_Valid_Window[i][j] = 1; RFDC.RFFD - * } - * } - * } - */ -static u32 DQS_calibration_methodA(struct ddrautocal *cal) -{ - ulong rfdc_reg; - ulong rffd; - - ulong rqdc_reg; - ulong rqfd; - - u32 *membase; - ulong bxcf; - int rqfd_average; - int bxcr_num; - int rffd_average; - int pass; - u32 passed = 0; - - int in_window; - struct autocal_regs curr_win_min; - struct autocal_regs curr_win_max; - struct autocal_regs best_win_min; - struct autocal_regs best_win_max; - struct autocal_regs loop_win_min; - struct autocal_regs loop_win_max; - -#ifdef DEBUG - ulong temp; -#endif - ulong rdcc; - - char slash[] = "\\|/-\\|/-"; - int loopi = 0; - - /* start */ - in_window = 0; - - memset(&curr_win_min, 0, sizeof(curr_win_min)); - memset(&curr_win_max, 0, sizeof(curr_win_max)); - memset(&best_win_min, 0, sizeof(best_win_min)); - memset(&best_win_max, 0, sizeof(best_win_max)); - memset(&loop_win_min, 0, sizeof(loop_win_min)); - memset(&loop_win_max, 0, sizeof(loop_win_max)); - - rdcc = 0; - - /* - * Program RDCC register - * Read sample cycle auto-update enable - */ - mtsdram(SDRAM_RDCC, - ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE); - -#ifdef DEBUG - mfsdram(SDRAM_RDCC, temp); - debug("<%s>SDRAM_RDCC=0x%x\n", __func__, temp); - mfsdram(SDRAM_RTSR, temp); - debug("<%s>SDRAM_RTSR=0x%x\n", __func__, temp); - mfsdram(SDRAM_FCSR, temp); - debug("<%s>SDRAM_FCSR=0x%x\n", __func__, temp); -#endif - - /* - * Program RQDC register - * Internal DQS delay mechanism enable - */ - mtsdram(SDRAM_RQDC, - SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x00)); - -#ifdef DEBUG - mfsdram(SDRAM_RQDC, temp); - debug("<%s>SDRAM_RQDC=0x%x\n", __func__, temp); -#endif - - /* - * Program RFDC register - * Set Feedback Fractional Oversample - * Auto-detect read sample cycle enable - */ - mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE | - SDRAM_RFDC_RFOS_ENCODE(0) | SDRAM_RFDC_RFFD_ENCODE(0)); - -#ifdef DEBUG - mfsdram(SDRAM_RFDC, temp); - debug("<%s>SDRAM_RFDC=0x%x\n", __func__, temp); -#endif - - putc(' '); - for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { - - mfsdram(SDRAM_RQDC, rqdc_reg); - rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); - mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd)); - - putc('\b'); - putc(slash[loopi++ % 8]); - - curr_win_min.rffd = 0; - curr_win_max.rffd = 0; - in_window = 0; - - for (rffd = 0, pass = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) { - mfsdram(SDRAM_RFDC, rfdc_reg); - rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); - mtsdram(SDRAM_RFDC, - rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd)); - - for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { - mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); - - /* Banks enabled */ - if (bxcf & SDRAM_BXCF_M_BE_MASK) { - /* Bank is enabled */ - membase = get_membase(bxcr_num); - pass = short_mem_test(membase); - } /* if bank enabled */ - } /* for bxcr_num */ - - /* If this value passed update RFFD windows */ - if (pass && !in_window) { /* at the start of window */ - in_window = 1; - curr_win_min.rffd = curr_win_max.rffd = rffd; - curr_win_min.rqfd = curr_win_max.rqfd = rqfd; - mfsdram(SDRAM_RDCC, rdcc); /*record this value*/ - } else if (!pass && in_window) { /* at end of window */ - in_window = 0; - } else if (pass && in_window) { /* within the window */ - curr_win_max.rffd = rffd; - curr_win_max.rqfd = rqfd; - } - /* else if (!pass && !in_window) - skip - no pass, not currently in a window */ - - if (in_window) { - if ((curr_win_max.rffd - curr_win_min.rffd) > - (best_win_max.rffd - best_win_min.rffd)) { - best_win_min.rffd = curr_win_min.rffd; - best_win_max.rffd = curr_win_max.rffd; - - best_win_min.rqfd = curr_win_min.rqfd; - best_win_max.rqfd = curr_win_max.rqfd; - cal->rdcc = rdcc; - } - passed = 1; - } - } /* RFDC.RFFD */ - - /* - * save-off the best window results of the RFDC.RFFD - * for this RQDC.RQFD setting - */ - /* - * if (just ended RFDC.RFDC loop pass window) > - * (prior RFDC.RFFD loop pass window) - */ - if ((best_win_max.rffd - best_win_min.rffd) > - (loop_win_max.rffd - loop_win_min.rffd)) { - loop_win_min.rffd = best_win_min.rffd; - loop_win_max.rffd = best_win_max.rffd; - loop_win_min.rqfd = rqfd; - loop_win_max.rqfd = rqfd; - debug("RQFD.min 0x%08x, RQFD.max 0x%08x, " - "RFFD.min 0x%08x, RFFD.max 0x%08x\n", - loop_win_min.rqfd, loop_win_max.rqfd, - loop_win_min.rffd, loop_win_max.rffd); - } - } /* RQDC.RQFD */ - - putc('\b'); - - debug("\n"); - - if ((loop_win_min.rffd == 0) && (loop_win_max.rffd == 0) && - (best_win_min.rffd == 0) && (best_win_max.rffd == 0) && - (best_win_min.rqfd == 0) && (best_win_max.rqfd == 0)) { - passed = 0; - } - - /* - * Need to program RQDC before RFDC. - */ - debug("<%s> RQFD Min: 0x%x\n", __func__, loop_win_min.rqfd); - debug("<%s> RQFD Max: 0x%x\n", __func__, loop_win_max.rqfd); - rqfd_average = loop_win_max.rqfd; - - if (rqfd_average < 0) - rqfd_average = 0; - - if (rqfd_average > SDRAM_RQDC_RQFD_MAX) - rqfd_average = SDRAM_RQDC_RQFD_MAX; - - debug("<%s> RFFD average: 0x%08x\n", __func__, rqfd_average); - mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | - SDRAM_RQDC_RQFD_ENCODE(rqfd_average)); - - debug("<%s> RFFD Min: 0x%08x\n", __func__, loop_win_min.rffd); - debug("<%s> RFFD Max: 0x%08x\n", __func__, loop_win_max.rffd); - rffd_average = ((loop_win_min.rffd + loop_win_max.rffd) / 2); - - if (rffd_average < 0) - rffd_average = 0; - - if (rffd_average > SDRAM_RFDC_RFFD_MAX) - rffd_average = SDRAM_RFDC_RFFD_MAX; - - debug("<%s> RFFD average: 0x%08x\n", __func__, rffd_average); - mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); - - /* if something passed, then return the size of the largest window */ - if (passed != 0) { - passed = loop_win_max.rffd - loop_win_min.rffd; - cal->rqfd = rqfd_average; - cal->rffd = rffd_average; - cal->rffd_min = loop_win_min.rffd; - cal->rffd_max = loop_win_max.rffd; - } - - return (u32)passed; -} - -#else /* !defined(CONFIG_PPC4xx_DDR_METHOD_A) */ - -/*-----------------------------------------------------------------------------+ -| program_DQS_calibration_methodB. -+-----------------------------------------------------------------------------*/ -static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal) -{ - u32 pass_result = 0; - -#ifdef DEBUG - ulong temp; -#endif - - /* - * Program RDCC register - * Read sample cycle auto-update enable - */ - mtsdram(SDRAM_RDCC, - ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE); - -#ifdef DEBUG - mfsdram(SDRAM_RDCC, temp); - debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp); -#endif - - /* - * Program RQDC register - * Internal DQS delay mechanism enable - */ - mtsdram(SDRAM_RQDC, -#if defined(CONFIG_DDR_RQDC_START_VAL) - SDRAM_RQDC_RQDE_ENABLE | - SDRAM_RQDC_RQFD_ENCODE(CONFIG_DDR_RQDC_START_VAL)); -#else - SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x38)); -#endif - -#ifdef DEBUG - mfsdram(SDRAM_RQDC, temp); - debug("<%s>SDRAM_RQDC=0x%08x\n", __func__, temp); -#endif - - /* - * Program RFDC register - * Set Feedback Fractional Oversample - * Auto-detect read sample cycle enable - */ - mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE | - SDRAM_RFDC_RFOS_ENCODE(0) | - SDRAM_RFDC_RFFD_ENCODE(0)); - -#ifdef DEBUG - mfsdram(SDRAM_RFDC, temp); - debug("<%s>SDRAM_RFDC=0x%08x\n", __func__, temp); -#endif - - pass_result = DQS_calibration_methodB(ddrcal); - - return pass_result; -} - -/* - * DQS_calibration_methodB() - * - * Autocalibration Method B - * - * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros - * ARRAY [Entire Feedback Range] FDBK_Valid_Window; initialized to all zeros - * MEMWRITE(addr, expected_data); - * Initialialize the DQS delay to 80 degrees (MCIF0_RRQDC[RQFD]=0x38). - * - * for (j = 0; j < Entire Feedback Range; j++) { - * MEMREAD(addr, actual_data); - * if (actual_data == expected_data) { - * FDBK_Valid_Window[j] = 1; - * } - * } - * - * Set MCIF0_RFDC[RFFD] to the middle of the FDBK_Valid_Window. - * - * for (i = 0; i < Entire DQS Range; i++) { - * MEMREAD(addr, actual_data); - * if (actual_data == expected_data) { - * DQS_Valid_Window[i] = 1; - * } - * } - * - * Set MCIF0_RRQDC[RQFD] to the middle of the DQS_Valid_Window. - */ -/*-----------------------------------------------------------------------------+ -| DQS_calibration_methodB. -+-----------------------------------------------------------------------------*/ -static u32 DQS_calibration_methodB(struct ddrautocal *cal) -{ - ulong rfdc_reg; - ulong rffd; - - ulong rqdc_reg; - ulong rqfd; - - ulong rdcc; - - u32 *membase; - ulong bxcf; - int rqfd_average; - int bxcr_num; - int rffd_average; - int pass; - uint passed = 0; - - int in_window; - u32 curr_win_min, curr_win_max; - u32 best_win_min, best_win_max; - u32 size = 0; - - /*------------------------------------------------------------------ - | Test to determine the best read clock delay tuning bits. - | - | Before the DDR controller can be used, the read clock delay needs to - | be set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD]. - | This value cannot be hardcoded into the program because it changes - | depending on the board's setup and environment. - | To do this, all delay values are tested to see if they - | work or not. By doing this, you get groups of fails with groups of - | passing values. The idea is to find the start and end of a passing - | window and take the center of it to use as the read clock delay. - | - | A failure has to be seen first so that when we hit a pass, we know - | that it is truely the start of the window. If we get passing values - | to start off with, we don't know if we are at the start of the window - | - | The code assumes that a failure will always be found. - | If a failure is not found, there is no easy way to get the middle - | of the passing window. I guess we can pretty much pick any value - | but some values will be better than others. Since the lowest speed - | we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed), - | from experimentation it is safe to say you will always have a failure - +-----------------------------------------------------------------*/ - - debug("\n\n"); - - in_window = 0; - rdcc = 0; - - curr_win_min = curr_win_max = 0; - best_win_min = best_win_max = 0; - for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) { - mfsdram(SDRAM_RFDC, rfdc_reg); - rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); - mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd)); - - pass = 1; - for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { - mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); - - /* Banks enabled */ - if (bxcf & SDRAM_BXCF_M_BE_MASK) { - /* Bank is enabled */ - membase = get_membase(bxcr_num); - pass &= short_mem_test(membase); - } /* if bank enabled */ - } /* for bxcf_num */ - - /* If this value passed */ - if (pass && !in_window) { /* start of passing window */ - in_window = 1; - curr_win_min = curr_win_max = rffd; - mfsdram(SDRAM_RDCC, rdcc); /* record this value */ - } else if (!pass && in_window) { /* end passing window */ - in_window = 0; - } else if (pass && in_window) { /* within the passing window */ - curr_win_max = rffd; - } - - if (in_window) { - if ((curr_win_max - curr_win_min) > - (best_win_max - best_win_min)) { - best_win_min = curr_win_min; - best_win_max = curr_win_max; - cal->rdcc = rdcc; - } - passed = 1; - } - } /* for rffd */ - - if ((best_win_min == 0) && (best_win_max == 0)) - passed = 0; - else - size = best_win_max - best_win_min; - - debug("RFFD Min: 0x%x\n", best_win_min); - debug("RFFD Max: 0x%x\n", best_win_max); - rffd_average = ((best_win_min + best_win_max) / 2); - - cal->rffd_min = best_win_min; - cal->rffd_max = best_win_max; - - if (rffd_average < 0) - rffd_average = 0; - - if (rffd_average > SDRAM_RFDC_RFFD_MAX) - rffd_average = SDRAM_RFDC_RFFD_MAX; - - mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); - - rffd = rffd_average; - in_window = 0; - - curr_win_min = curr_win_max = 0; - best_win_min = best_win_max = 0; - for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { - mfsdram(SDRAM_RQDC, rqdc_reg); - rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); - mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd)); - - pass = 1; - for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { - - mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf); - - /* Banks enabled */ - if (bxcf & SDRAM_BXCF_M_BE_MASK) { - /* Bank is enabled */ - membase = get_membase(bxcr_num); - pass &= short_mem_test(membase); - } /* if bank enabled */ - } /* for bxcf_num */ - - /* If this value passed */ - if (pass && !in_window) { - in_window = 1; - curr_win_min = curr_win_max = rqfd; - } else if (!pass && in_window) { - in_window = 0; - } else if (pass && in_window) { - curr_win_max = rqfd; - } - - if (in_window) { - if ((curr_win_max - curr_win_min) > - (best_win_max - best_win_min)) { - best_win_min = curr_win_min; - best_win_max = curr_win_max; - } - passed = 1; - } - } /* for rqfd */ - - if ((best_win_min == 0) && (best_win_max == 0)) - passed = 0; - - debug("RQFD Min: 0x%x\n", best_win_min); - debug("RQFD Max: 0x%x\n", best_win_max); - rqfd_average = ((best_win_min + best_win_max) / 2); - - if (rqfd_average < 0) - rqfd_average = 0; - - if (rqfd_average > SDRAM_RQDC_RQFD_MAX) - rqfd_average = SDRAM_RQDC_RQFD_MAX; - - mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | - SDRAM_RQDC_RQFD_ENCODE(rqfd_average)); - - mfsdram(SDRAM_RQDC, rqdc_reg); - mfsdram(SDRAM_RFDC, rfdc_reg); - - /* - * Need to program RQDC before RFDC. The value is read above. - * That is the reason why auto cal not work. - * See, comments below. - */ - mtsdram(SDRAM_RQDC, rqdc_reg); - mtsdram(SDRAM_RFDC, rfdc_reg); - - debug("RQDC: 0x%08X\n", rqdc_reg); - debug("RFDC: 0x%08X\n", rfdc_reg); - - /* if something passed, then return the size of the largest window */ - if (passed != 0) { - passed = size; - cal->rqfd = rqfd_average; - cal->rffd = rffd_average; - } - - return (uint)passed; -} -#endif /* defined(CONFIG_PPC4xx_DDR_METHOD_A) */ - -/* - * Default table for DDR auto-calibration of all - * possible WRDTR and CLKTR values. - * Table format is: - * {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} - * - * Table is terminated with {-1, -1} value pair. - * - * Board vendors can specify their own board specific subset of - * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value - * pairs via a board defined ddr_scan_option() function. - */ -struct sdram_timing full_scan_options[] = { - {0, 0}, {0, 1}, {0, 2}, {0, 3}, - {1, 0}, {1, 1}, {1, 2}, {1, 3}, - {2, 0}, {2, 1}, {2, 2}, {2, 3}, - {3, 0}, {3, 1}, {3, 2}, {3, 3}, - {4, 0}, {4, 1}, {4, 2}, {4, 3}, - {5, 0}, {5, 1}, {5, 2}, {5, 3}, - {6, 0}, {6, 1}, {6, 2}, {6, 3}, - {-1, -1} -}; - -/*---------------------------------------------------------------------------+ -| DQS_calibration. -+----------------------------------------------------------------------------*/ -u32 DQS_autocalibration(void) -{ - u32 wdtr; - u32 clkp; - u32 result = 0; - u32 best_result = 0; - u32 best_rdcc; - struct ddrautocal ddrcal; - struct autocal_clks tcal; - ulong rfdc_reg; - ulong rqdc_reg; - u32 val; - int verbose_lvl = 0; - char *str; - char slash[] = "\\|/-\\|/-"; - int loopi = 0; - struct sdram_timing *scan_list; - -#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION) - int i; - char tmp[64]; /* long enough for environment variables */ -#endif - - memset(&tcal, 0, sizeof(tcal)); - - ddr_scan_option((ulong)full_scan_options); - - scan_list = - (struct sdram_timing *)ddr_scan_option((ulong)full_scan_options); - - mfsdram(SDRAM_MCOPT1, val); - if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP) - str = "ECC Auto calibration -"; - else - str = "Auto calibration -"; - - puts(str); - -#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION) - i = getenv_r("autocalib", tmp, sizeof(tmp)); - if (i < 0) - strcpy(tmp, CONFIG_AUTOCALIB); - - if (strcmp(tmp, "final") == 0) { - /* display the final autocalibration results only */ - verbose_lvl = 1; - } else if (strcmp(tmp, "loop") == 0) { - /* display summary autocalibration info per iteration */ - verbose_lvl = 2; - } else if (strcmp(tmp, "display") == 0) { - /* display full debug autocalibration window info. */ - verbose_lvl = 3; - } -#endif /* (DEBUG_PPC4xx_DDR_AUTOCALIBRATION) */ - - best_rdcc = (SDRAM_RDCC_RDSS_T4 >> 30); - - while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) { - wdtr = scan_list->wrdtr; - clkp = scan_list->clktr; - - mfsdram(SDRAM_WRDTR, val); - val &= ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK); - mtsdram(SDRAM_WRDTR, (val | - ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | (wdtr << 25)))); - - mtsdram(SDRAM_CLKTR, clkp << 30); - - relock_memory_DLL(); - - putc('\b'); - putc(slash[loopi++ % 8]); - -#ifdef DEBUG - debug("\n"); - debug("*** --------------\n"); - mfsdram(SDRAM_WRDTR, val); - debug("*** SDRAM_WRDTR set to 0x%08x\n", val); - mfsdram(SDRAM_CLKTR, val); - debug("*** SDRAM_CLKTR set to 0x%08x\n", val); -#endif - - debug("\n"); - if (verbose_lvl > 2) { - printf("*** SDRAM_WRDTR (wdtr) set to %d\n", wdtr); - printf("*** SDRAM_CLKTR (clkp) set to %d\n", clkp); - } - - memset(&ddrcal, 0, sizeof(ddrcal)); - - /* - * DQS calibration. - */ - /* - * program_DQS_calibration_method[A|B]() returns 0 if no - * passing RFDC.[RFFD] window is found or returns the size - * of the best passing window; in the case of a found passing - * window, the ddrcal will contain the values of the best - * window RQDC.[RQFD] and RFDC.[RFFD]. - */ - - /* - * Call PPC4xx SDRAM DDR autocalibration methodA or methodB. - * Default is methodB. - * Defined the autocalibration method in the board specific - * header file. - * Please see include/configs/kilauea.h for an example for - * a board specific implementation. - */ -#if defined(CONFIG_PPC4xx_DDR_METHOD_A) - result = program_DQS_calibration_methodA(&ddrcal); -#else - result = program_DQS_calibration_methodB(&ddrcal); -#endif - - sync(); - - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - val = ddrcal.rdcc; /* RDCC from the best passing window */ - - udelay(100); - - if (verbose_lvl > 1) { - char *tstr; - switch ((val >> 30)) { - case 0: - if (result != 0) - tstr = "T1"; - else - tstr = "N/A"; - break; - case 1: - tstr = "T2"; - break; - case 2: - tstr = "T3"; - break; - case 3: - tstr = "T4"; - break; - default: - tstr = "unknown"; - break; - } - printf("** WRDTR(%d) CLKTR(%d), Wind (%d), best (%d), " - "max-min(0x%04x)(0x%04x), RDCC: %s\n", - wdtr, clkp, result, best_result, - ddrcal.rffd_min, ddrcal.rffd_max, tstr); - } - - /* - * The DQS calibration "result" is either "0" - * if no passing window was found, or is the - * size of the RFFD passing window. - */ - /* - * want the lowest Read Sample Cycle Select - */ - val = SDRAM_RDCC_RDSS_DECODE(val); - debug("*** (%d) (%d) current_rdcc, best_rdcc\n", - val, best_rdcc); - - if ((result != 0) && - (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) { - if (((result == best_result) && (val < best_rdcc)) || - ((result > best_result) && (val <= best_rdcc))) { - tcal.autocal.flags = 1; - debug("*** (%d)(%d) result passed window " - "size: 0x%08x, rqfd = 0x%08x, " - "rffd = 0x%08x, rdcc = 0x%08x\n", - wdtr, clkp, result, ddrcal.rqfd, - ddrcal.rffd, ddrcal.rdcc); - - /* - * Save the SDRAM_WRDTR and SDRAM_CLKTR - * settings for the largest returned - * RFFD passing window size. - */ - best_rdcc = val; - tcal.clocks.wrdtr = wdtr; - tcal.clocks.clktr = clkp; - tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val); - tcal.autocal.rqfd = ddrcal.rqfd; - tcal.autocal.rffd = ddrcal.rffd; - best_result = result; - - if (verbose_lvl > 2) { - printf("** (%d)(%d) " - "best result: 0x%04x\n", - wdtr, clkp, - best_result); - printf("** (%d)(%d) " - "best WRDTR: 0x%04x\n", - wdtr, clkp, - tcal.clocks.wrdtr); - printf("** (%d)(%d) " - "best CLKTR: 0x%04x\n", - wdtr, clkp, - tcal.clocks.clktr); - printf("** (%d)(%d) " - "best RQDC: 0x%04x\n", - wdtr, clkp, - tcal.autocal.rqfd); - printf("** (%d)(%d) " - "best RFDC: 0x%04x\n", - wdtr, clkp, - tcal.autocal.rffd); - printf("** (%d)(%d) " - "best RDCC: 0x%08x\n", - wdtr, clkp, - (u32)tcal.clocks.rdcc); - mfsdram(SDRAM_RTSR, val); - printf("** (%d)(%d) best " - "loop RTSR: 0x%08x\n", - wdtr, clkp, val); - mfsdram(SDRAM_FCSR, val); - printf("** (%d)(%d) best " - "loop FCSR: 0x%08x\n", - wdtr, clkp, val); - } - } - } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */ - scan_list++; - } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */ - - if (tcal.autocal.flags == 1) { - if (verbose_lvl > 0) { - printf("*** --------------\n"); - printf("*** best_result window size: %d\n", - best_result); - printf("*** best_result WRDTR: 0x%04x\n", - tcal.clocks.wrdtr); - printf("*** best_result CLKTR: 0x%04x\n", - tcal.clocks.clktr); - printf("*** best_result RQFD: 0x%04x\n", - tcal.autocal.rqfd); - printf("*** best_result RFFD: 0x%04x\n", - tcal.autocal.rffd); - printf("*** best_result RDCC: 0x%04x\n", - tcal.clocks.rdcc); - printf("*** --------------\n"); - printf("\n"); - } - - /* - * if got best passing result window, then lock in the - * best CLKTR, WRDTR, RQFD, and RFFD values - */ - mfsdram(SDRAM_WRDTR, val); - mtsdram(SDRAM_WRDTR, (val & - ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) | - ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | - (tcal.clocks.wrdtr << 25))); - - mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30); - - relock_memory_DLL(); - - mfsdram(SDRAM_RQDC, rqdc_reg); - rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); - mtsdram(SDRAM_RQDC, rqdc_reg | - SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd)); - - mfsdram(SDRAM_RQDC, rqdc_reg); - debug("*** best_result: read value SDRAM_RQDC 0x%08x\n", - rqdc_reg); - - mfsdram(SDRAM_RFDC, rfdc_reg); - rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); - mtsdram(SDRAM_RFDC, rfdc_reg | - SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd)); - - mfsdram(SDRAM_RFDC, rfdc_reg); - debug("*** best_result: read value SDRAM_RFDC 0x%08x\n", - rfdc_reg); - mfsdram(SDRAM_RDCC, val); - debug("*** SDRAM_RDCC 0x%08x\n", val); - } else { - /* - * no valid windows were found - */ - printf("DQS memory calibration window can not be determined, " - "terminating u-boot.\n"); - ppc4xx_ibm_ddr2_register_dump(); - spd_ddr_init_hang(); - } - - blank_string(strlen(str)); - - return 0; -} -#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ -u32 DQS_autocalibration(void) -{ - return 0; -} -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ -#endif /* defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */ diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c deleted file mode 100644 index f3b921477b..0000000000 --- a/cpu/ppc4xx/4xx_pcie.c +++ /dev/null @@ -1,1298 +0,0 @@ -/* - * (C) Copyright 2006 - 2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * Roland Dreier - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include -#include -#include -#include -#include -#include - -#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ - defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE) - -#include - -enum { - PTYPE_ENDPOINT = 0x0, - PTYPE_LEGACY_ENDPOINT = 0x1, - PTYPE_ROOT_PORT = 0x4, - - LNKW_X1 = 0x1, - LNKW_X4 = 0x4, - LNKW_X8 = 0x8 -}; - -static struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS]; - -/* - * Per default, all cards are present, so we need to check if the - * link comes up. - */ -int __board_pcie_card_present(int port) -{ - return 1; -} -int board_pcie_card_present(int port) - __attribute__((weak, alias("__board_pcie_card_present"))); - -/* - * Some boards have runtime detection of the first and last PCIe - * slot used, so let's provide weak default functions for the - * common version. - */ -int __board_pcie_first(void) -{ - return 0; -} -int board_pcie_first(void) - __attribute__((weak, alias("__board_pcie_first"))); - -int __board_pcie_last(void) -{ - return CONFIG_SYS_PCIE_NR_PORTS - 1; -} -int board_pcie_last(void) - __attribute__((weak, alias("__board_pcie_last"))); - -void __board_pcie_setup_port(int port, int rootpoint) -{ - /* noting in this weak default implementation */ -} -void board_pcie_setup_port(int port, int rootpoint) - __attribute__((weak, alias("__board_pcie_setup_port"))); - -void pcie_setup_hoses(int busno) -{ - struct pci_controller *hose; - int i, bus; - int ret = 0; - char *env; - unsigned int delay; - int first = board_pcie_first(); - int last = board_pcie_last(); - - /* - * Assume we're called after the PCI(X) hose(s) are initialized, - * which takes bus ID 0... and therefore start numbering PCIe's - * from the next number. - */ - bus = busno; - - for (i = first; i <= last; i++) { - /* - * Some boards (e.g. Katmai) can detects via hardware - * if a PCIe card is plugged, so let's check this. - */ - if (!board_pcie_card_present(i)) - continue; - - if (is_end_point(i)) { - board_pcie_setup_port(i, 0); - ret = ppc4xx_init_pcie_endport(i); - } else { - board_pcie_setup_port(i, 1); - ret = ppc4xx_init_pcie_rootport(i); - } - if (ret == -ENODEV) - continue; - if (ret) { - printf("PCIE%d: initialization as %s failed\n", i, - is_end_point(i) ? "endpoint" : "root-complex"); - continue; - } - - hose = &pcie_hose[i]; - hose->first_busno = bus; - hose->last_busno = bus; - hose->current_busno = bus; - - /* setup mem resource */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, - CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, - CONFIG_SYS_PCIE_MEMSIZE, - PCI_REGION_MEM); - hose->region_count = 1; - pci_register_hose(hose); - - if (is_end_point(i)) { - ppc4xx_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ - } else { - ppc4xx_setup_pcie_rootpoint(hose, i); - env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul(env, NULL, 10); - if (delay > 5) - printf("Warning, expect noticable delay before " - "PCIe scan due to 'pciscandelay' value!\n"); - mdelay(delay * 1000); - } - - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; - } - } -} - -static int validate_endpoint(struct pci_controller *hose) -{ - if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE) - return (is_end_point(0)); - else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE) - return (is_end_point(1)); -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE) - return (is_end_point(2)); -#endif - - return 0; -} - -static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) -{ - u8 *base = (u8*)hose->cfg_data; - - /* use local configuration space for the first bus */ - if (PCI_BUS(devfn) == 0) { - if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE) - base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE; - if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE) - base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE; -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE) - base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE; -#endif - } - - return base; -} - -static void pcie_dmer_disable(void) -{ - mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); - mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); -#endif -} - -static void pcie_dmer_enable(void) -{ - mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); - mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), - mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); -#endif -} - -static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, - int offset, int len, u32 *val) { - - u8 *address; - *val = 0; - - if (validate_endpoint(hose)) - return 0; /* No upstream config access */ - - /* - * Bus numbers are relative to hose->first_busno - */ - devfn -= PCI_BDF(hose->first_busno, 0, 0); - - /* - * NOTICE: configuration space ranges are currenlty mapped only for - * the first 16 buses, so such limit must be imposed. In case more - * buses are required the TLB settings in board/amcc//init.S - * need to be altered accordingly (one bus takes 1 MB of memory space). - */ - if (PCI_BUS(devfn) >= 16) - return 0; - - /* - * Only single device/single function is supported for the primary and - * secondary buses of the 440SPe host bridge. - */ - if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && - ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) - return 0; - - address = pcie_get_base(hose, devfn); - offset += devfn << 4; - - /* - * Reading from configuration space of non-existing device can - * generate transaction errors. For the read duration we suppress - * assertion of machine check exceptions to avoid those. - */ - pcie_dmer_disable (); - - debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset); - switch (len) { - case 1: - *val = in_8(hose->cfg_data + offset); - break; - case 2: - *val = in_le16((u16 *)(hose->cfg_data + offset)); - break; - default: - *val = in_le32((u32*)(hose->cfg_data + offset)); - break; - } - - pcie_dmer_enable (); - - return 0; -} - -static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, - int offset, int len, u32 val) { - - u8 *address; - - if (validate_endpoint(hose)) - return 0; /* No upstream config access */ - - /* - * Bus numbers are relative to hose->first_busno - */ - devfn -= PCI_BDF(hose->first_busno, 0, 0); - - /* - * Same constraints as in pcie_read_config(). - */ - if (PCI_BUS(devfn) >= 16) - return 0; - - if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && - ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) - return 0; - - address = pcie_get_base(hose, devfn); - offset += devfn << 4; - - /* - * Suppress MCK exceptions, similar to pcie_read_config() - */ - pcie_dmer_disable (); - - switch (len) { - case 1: - out_8(hose->cfg_data + offset, val); - break; - case 2: - out_le16((u16 *)(hose->cfg_data + offset), val); - break; - default: - out_le32((u32 *)(hose->cfg_data + offset), val); - break; - } - - pcie_dmer_enable (); - - return 0; -} - -int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) -{ - u32 v; - int rv; - - rv = pcie_read_config(hose, dev, offset, 1, &v); - *val = (u8)v; - return rv; -} - -int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) -{ - u32 v; - int rv; - - rv = pcie_read_config(hose, dev, offset, 2, &v); - *val = (u16)v; - return rv; -} - -int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) -{ - u32 v; - int rv; - - rv = pcie_read_config(hose, dev, offset, 3, &v); - *val = (u32)v; - return rv; -} - -int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) -{ - return pcie_write_config(hose,(u32)dev,offset,1,val); -} - -int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) -{ - return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); -} - -int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) -{ - return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); -} - -#if defined(CONFIG_440SPE) -static void ppc4xx_setup_utl(u32 port) { - - volatile void *utl_base = NULL; - - /* - * Map UTL registers - */ - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); - break; - - case 1: - mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); - break; - - case 2: - mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); - mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); - break; - } - utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); - - /* - * Set buffer allocations and then assert VRB and TXE. - */ - out_be32(utl_base + PEUTL_OUTTR, 0x08000000); - out_be32(utl_base + PEUTL_INTR, 0x02000000); - out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); - out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); - out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); - out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); - out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); - out_be32(utl_base + PEUTL_PCTL, 0x80800066); -} - -static int check_error(void) -{ - u32 valPE0, valPE1, valPE2; - int err = 0; - - /* SDR0_PEGPLLLCT1 reset */ - if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) - printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); - - valPE0 = SDR_READ(PESDR0_RCSSET); - valPE1 = SDR_READ(PESDR1_RCSSET); - valPE2 = SDR_READ(PESDR2_RCSSET); - - /* SDR0_PExRCSSET rstgu */ - if (!(valPE0 & 0x01000000) || - !(valPE1 & 0x01000000) || - !(valPE2 & 0x01000000)) { - printf("PCIE: SDR0_PExRCSSET rstgu error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rstdl */ - if (!(valPE0 & 0x00010000) || - !(valPE1 & 0x00010000) || - !(valPE2 & 0x00010000)) { - printf("PCIE: SDR0_PExRCSSET rstdl error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rstpyn */ - if ((valPE0 & 0x00001000) || - (valPE1 & 0x00001000) || - (valPE2 & 0x00001000)) { - printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); - err = -1; - } - - /* SDR0_PExRCSSET hldplb */ - if ((valPE0 & 0x10000000) || - (valPE1 & 0x10000000) || - (valPE2 & 0x10000000)) { - printf("PCIE: SDR0_PExRCSSET hldplb error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rdy */ - if ((valPE0 & 0x00100000) || - (valPE1 & 0x00100000) || - (valPE2 & 0x00100000)) { - printf("PCIE: SDR0_PExRCSSET rdy error\n"); - err = -1; - } - - /* SDR0_PExRCSSET shutdown */ - if ((valPE0 & 0x00000100) || - (valPE1 & 0x00000100) || - (valPE2 & 0x00000100)) { - printf("PCIE: SDR0_PExRCSSET shutdown error\n"); - err = -1; - } - return err; -} - -/* - * Initialize PCI Express core - */ -int ppc4xx_init_pcie(void) -{ - int time_out = 20; - - /* Set PLL clock receiver to LVPECL */ - SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); - - if (check_error()) { - printf("ERROR: failed to set PCIe reference clock receiver --" - "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1)); - - return -1; - } - - /* Did resistance calibration work? */ - if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) { - printf("ERROR: PCIe resistance calibration failed --" - "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2)); - - return -1; - } - /* De-assert reset of PCIe PLL, wait for lock */ - SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); - udelay(300); /* 300 uS is maximum time lock should take */ - - while (time_out) { - if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { - time_out--; - udelay(20); /* Wait 20 uS more if needed */ - } else - break; - } - if (!time_out) { - printf("ERROR: PCIe PLL VCO output not locked to ref clock --" - "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3)); - - return -1; - } - return 0; -} -#endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -static void ppc4xx_setup_utl(u32 port) -{ - volatile void *utl_base = NULL; - - /* - * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK - */ - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); - mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)); - mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */ - mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); - break; - - case 1: - mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); - mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE) - + 0x1000); - mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */ - mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); - break; - } - utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); - - /* - * Set buffer allocations and then assert VRB and TXE. - */ - out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */ - out_be32(utl_base + PEUTL_OUTTR, 0x08000000); - out_be32(utl_base + PEUTL_INTR, 0x02000000); - out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */ - out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */ - out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000); - out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */ - out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); - out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */ -} - -/* - * TODO: double check PCI express SDR based on the latest user manual - * Some registers specified here no longer exist.. has to be - * updated based on the final EAS spec. - */ -static int check_error(void) -{ - u32 valPE0, valPE1; - int err = 0; - - valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0)); - valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1)); - - /* SDR0_PExRCSSET rstgu */ - if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) { - printf("PCIE: SDR0_PExRCSSET rstgu error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rstdl */ - if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) { - printf("PCIE: SDR0_PExRCSSET rstdl error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rstpyn */ - if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) { - printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); - err = -1; - } - - /* SDR0_PExRCSSET hldplb */ - if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) { - printf("PCIE: SDR0_PExRCSSET hldplb error\n"); - err = -1; - } - - /* SDR0_PExRCSSET rdy */ - if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) { - printf("PCIE: SDR0_PExRCSSET rdy error\n"); - err = -1; - } - - return err; -} - -/* - * Initialize PCI Express core as described in User Manual - * TODO: double check PE SDR PLL Register with the updated user manual. - */ -int ppc4xx_init_pcie(void) -{ - if (check_error()) - return -1; - - return 0; -} -#endif /* CONFIG_460EX */ - -#if defined(CONFIG_405EX) -static void ppc4xx_setup_utl(u32 port) -{ - u32 utl_base; - - /* - * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK - */ - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); - mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE); - mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */ - mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); - break; - - case 1: - mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); - mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE); - mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */ - mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); - - break; - } - utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE; - - /* - * Set buffer allocations and then assert VRB and TXE. - */ - out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000); - out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000); - out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000); - out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000); - out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000); - out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000); - out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000); - out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066); - - out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c); - out_be32((u32 *)(utl_base + PEUTL_RCSTA), - in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000); -} - -int ppc4xx_init_pcie(void) -{ - /* - * Nothing to do on 405EX - */ - return 0; -} -#endif /* CONFIG_405EX */ - -/* - * Board-specific pcie initialization - * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed - */ - -/* - * Initialize various parts of the PCI Express core for our port: - * - * - Set as a root port and enable max width - * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). - * - Set up UTL configuration. - * - Increase SERDES drive strength to levels suggested by AMCC. - * - De-assert RSTPYN, RSTDL and RSTGU. - * - * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it - * with default setting 0x11310000. The register has new fields, - * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core - * hang. - */ -#if defined(CONFIG_440SPE) -int __ppc4xx_init_pcie_port_hw(int port, int rootport) -{ - u32 val = 1 << 24; - u32 utlset1; - - if (rootport) { - val = PTYPE_ROOT_PORT << 20; - utlset1 = 0x21222222; - } else { - val = PTYPE_LEGACY_ENDPOINT << 20; - utlset1 = 0x20222222; - } - - if (port == 0) - val |= LNKW_X8 << 12; - else - val |= LNKW_X4 << 12; - - SDR_WRITE(SDRN_PESDR_DLPSET(port), val); - SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); - if (!ppc440spe_revB()) - SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000); - SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000); - SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000); - SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000); - SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000); - if (port == 0) { - SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); - } - SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) & - ~(1 << 24 | 1 << 16)) | 1 << 12); - - return 0; -} -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -int __ppc4xx_init_pcie_port_hw(int port, int rootport) -{ - u32 val; - u32 utlset1; - - if (rootport) - val = PTYPE_ROOT_PORT << 20; - else - val = PTYPE_LEGACY_ENDPOINT << 20; - - if (port == 0) { - val |= LNKW_X1 << 12; - utlset1 = 0x20000000; - } else { - val |= LNKW_X4 << 12; - utlset1 = 0x20101101; - } - - SDR_WRITE(SDRN_PESDR_DLPSET(port), val); - SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); - SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000); - - switch (port) { - case 0: - SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230); - SDR_WRITE(PESDR0_L0DRV, 0x00000130); - SDR_WRITE(PESDR0_L0CLK, 0x00000006); - - SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000); - break; - - case 1: - SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230); - SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230); - SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230); - SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230); - SDR_WRITE(PESDR1_L0DRV, 0x00000130); - SDR_WRITE(PESDR1_L1DRV, 0x00000130); - SDR_WRITE(PESDR1_L2DRV, 0x00000130); - SDR_WRITE(PESDR1_L3DRV, 0x00000130); - SDR_WRITE(PESDR1_L0CLK, 0x00000006); - SDR_WRITE(PESDR1_L1CLK, 0x00000006); - SDR_WRITE(PESDR1_L2CLK, 0x00000006); - SDR_WRITE(PESDR1_L3CLK, 0x00000006); - - SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000); - break; - } - - SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) | - (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); - - /* Poll for PHY reset */ - switch (port) { - case 0: - while (!(SDR_READ(PESDR0_RSTSTA) & 0x1)) - udelay(10); - break; - case 1: - while (!(SDR_READ(PESDR1_RSTSTA) & 0x1)) - udelay(10); - break; - } - - SDR_WRITE(SDRN_PESDR_RCSSET(port), - (SDR_READ(SDRN_PESDR_RCSSET(port)) & - ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | - PESDRx_RCSSET_RSTPYN); - - return 0; -} -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_405EX) -int __ppc4xx_init_pcie_port_hw(int port, int rootport) -{ - u32 val; - - if (rootport) - val = 0x00401000; - else - val = 0x00101000; - - SDR_WRITE(SDRN_PESDR_DLPSET(port), val); - SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000); - SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000); - SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); - SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); - - /* Assert the PE0_PHY reset */ - SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000); - udelay(1000); - - /* deassert the PE0_hotreset */ - if (is_end_point(port)) - SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000); - else - SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); - - /* poll for phy !reset */ - while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) - ; - - /* deassert the PE0_gpl_utl_reset */ - SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000); - - if (port == 0) - mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */ - else - mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */ - - return 0; -} -#endif /* CONFIG_405EX */ - -int ppc4xx_init_pcie_port_hw(int port, int rootport) -__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); - -/* - * We map PCI Express configuration access into the 512MB regions - * - * NOTICE: revB is very strict about PLB real addressess and ranges to - * be mapped for config space; it seems to only work with d_nnnn_nnnn - * range (hangs the core upon config transaction attempts when set - * otherwise) while revA uses c_nnnn_nnnn. - * - * For 440SPe revA: - * PCIE0: 0xc_4000_0000 - * PCIE1: 0xc_8000_0000 - * PCIE2: 0xc_c000_0000 - * - * For 440SPe revB: - * PCIE0: 0xd_0000_0000 - * PCIE1: 0xd_2000_0000 - * PCIE2: 0xd_4000_0000 - * - * For 405EX: - * PCIE0: 0xa000_0000 - * PCIE1: 0xc000_0000 - * - * For 460EX/GT: - * PCIE0: 0xd_0000_0000 - * PCIE1: 0xd_2000_0000 - */ -static inline u64 ppc4xx_get_cfgaddr(int port) -{ -#if defined(CONFIG_405EX) - if (port == 0) - return (u64)CONFIG_SYS_PCIE0_CFGBASE; - else - return (u64)CONFIG_SYS_PCIE1_CFGBASE; -#endif -#if defined(CONFIG_440SPE) - if (ppc440spe_revB()) { - switch (port) { - default: /* to satisfy compiler */ - case 0: - return 0x0000000d00000000ULL; - case 1: - return 0x0000000d20000000ULL; - case 2: - return 0x0000000d40000000ULL; - } - } else { - switch (port) { - default: /* to satisfy compiler */ - case 0: - return 0x0000000c40000000ULL; - case 1: - return 0x0000000c80000000ULL; - case 2: - return 0x0000000cc0000000ULL; - } - } -#endif -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - if (port == 0) - return 0x0000000d00000000ULL; - else - return 0x0000000d20000000ULL; -#endif -} - -/* - * 4xx boards as endpoint and root point setup - * and - * testing inbound and out bound windows - * - * 4xx boards can be plugged into another 4xx boards or you can get PCI-E - * cable which can be used to setup loop back from one port to another port. - * Please rememeber that unless there is a endpoint plugged in to root port it - * will not initialize. It is the same in case of endpoint , unless there is - * root port attached it will not initialize. - * - * In this release of software all the PCI-E ports are configured as either - * endpoint or rootpoint.In future we will have support for selective ports - * setup as endpoint and root point in single board. - * - * Once your board came up as root point , you can verify by reading - * /proc/bus/pci/devices. Where you can see the configuration registers - * of endpoint device attached to the port. - * - * Enpoint cofiguration can be verified by connecting 4xx board to any - * host or another 4xx board. Then try to scan the device. In case of - * linux use "lspci" or appripriate os command. - * - * How do I verify the inbound and out bound windows ? (4xx to 4xx) - * in this configuration inbound and outbound windows are setup to access - * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address - * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, - * This is waere your POM(PLB out bound memory window) mapped. then - * read the data from other 4xx board's u-boot prompt at address - * 0x9000 0000(SRAM). Data should match. - * In case of inbound , write data to u-boot command prompt at 0xb000 0000 - * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check - * data at 0x9000 0000(SRAM).Data should match. - */ -int ppc4xx_init_pcie_port(int port, int rootport) -{ - static int core_init; - volatile u32 val = 0; - int attempts; - u64 addr; - u32 low, high; - - if (!core_init) { - if (ppc4xx_init_pcie()) - return -1; - ++core_init; - } - - /* - * Initialize various parts of the PCI Express core for our port - */ - ppc4xx_init_pcie_port_hw(port, rootport); - - /* - * Notice: the following delay has critical impact on device - * initialization - if too short (<50ms) the link doesn't get up. - */ - mdelay(100); - - val = SDR_READ(SDRN_PESDR_RCSSTS(port)); - if (val & (1 << 20)) { - printf("PCIE%d: PGRST failed %08x\n", port, val); - return -1; - } - - /* - * Verify link is up - */ - val = SDR_READ(SDRN_PESDR_LOOP(port)); - if (!(val & 0x00001000)) { - printf("PCIE%d: link is not up.\n", port); - return -ENODEV; - } - - /* - * Setup UTL registers - but only on revA! - * We use default settings for revB chip. - */ - if (!ppc440spe_revB()) - ppc4xx_setup_utl(port); - - /* - * We map PCI Express configuration access into the 512MB regions - */ - addr = ppc4xx_get_cfgaddr(port); - low = U64_TO_U32_LOW(addr); - high = U64_TO_U32_HIGH(addr); - - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low); - mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ - break; - case 1: - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); - mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ - break; -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - case 2: - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); - mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ - break; -#endif - } - - /* - * Check for VC0 active and assert RDY. - */ - attempts = 10; - while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE%d: VC0 not active\n", port); - return -1; - } - mdelay(1000); - } - SDR_WRITE(SDRN_PESDR_RCSSET(port), - SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20); - mdelay(100); - - return 0; -} - -int ppc4xx_init_pcie_rootport(int port) -{ - return ppc4xx_init_pcie_port(port, 1); -} - -int ppc4xx_init_pcie_endport(int port) -{ - return ppc4xx_init_pcie_port(port, 0); -} - -void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) -{ - volatile void *mbase = NULL; - volatile void *rmbase = NULL; - - pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); - - switch (port) { - case 0: - mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE; - hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; - break; - case 1: - mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE; - hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; - break; -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - case 2: - mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE; - hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; - break; -#endif - } - - /* - * Set bus numbers on our root port - */ - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); - - /* - * Set up outbound translation to hose->mem_space from PLB - * addresses at an offset of 0xd_0000_0000. We set the low - * bits of the mask to 11 to turn off splitting into 8 - * subregions and to enable the outbound translation. - */ - out_le32(mbase + PECFG_POM0LAH, 0x00000000); - out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE + - port * CONFIG_SYS_PCIE_MEMSIZE); - debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH), - in_le32(mbase + PECFG_POM0LAL)); - - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + - port * CONFIG_SYS_PCIE_MEMSIZE); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); - debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", - mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)), - mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)), - mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)), - mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); - break; - case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + - port * CONFIG_SYS_PCIE_MEMSIZE); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); - debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", - mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)), - mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)), - mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), - mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); - break; -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + - port * CONFIG_SYS_PCIE_MEMSIZE); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); - debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", - mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)), - mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)), - mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)), - mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2))); - break; -#endif - } - - /* Set up 4GB inbound memory window at 0 */ - out_le32(mbase + PCI_BASE_ADDRESS_0, 0); - out_le32(mbase + PCI_BASE_ADDRESS_1, 0); - out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff); - out_le32(mbase + PECFG_BAR0LMPA, 0); - - out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); - out_le32(mbase + PECFG_PIM01SAL, 0x00000000); - out_le32(mbase + PECFG_PIM0LAL, 0); - out_le32(mbase + PECFG_PIM0LAH, 0); - out_le32(mbase + PECFG_PIM1LAL, 0x00000000); - out_le32(mbase + PECFG_PIM1LAH, 0x00000004); - out_le32(mbase + PECFG_PIMEN, 0x1); - - /* Enable I/O, Mem, and Busmaster cycles */ - out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Set Device and Vendor Id */ - out_le16(mbase + 0x200, 0xaaa0 + port); - out_le16(mbase + 0x202, 0xbed0 + port); - - /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ - out_le32(mbase + 0x208, 0x06040001); - - printf("PCIE%d: successfully set as root-complex\n", port); -} - -int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) -{ - volatile void *mbase = NULL; - int attempts = 0; - - pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); - - switch (port) { - case 0: - mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; - hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; - break; - case 1: - mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; - hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; - break; -#if defined(CONFIG_SYS_PCIE2_CFGBASE) - case 2: - mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; - hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; - break; -#endif - } - - /* - * Set up outbound translation to hose->mem_space from PLB - * addresses at an offset of 0xd_0000_0000. We set the low - * bits of the mask to 11 to turn off splitting into 8 - * subregions and to enable the outbound translation. - */ - out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); - out_le32(mbase + PECFG_POM0LAL, 0x00001000); - - switch (port) { - case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + - port * CONFIG_SYS_PCIE_MEMSIZE); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); - break; - case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + - port * CONFIG_SYS_PCIE_MEMSIZE); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); - break; -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + - port * CONFIG_SYS_PCIE_MEMSIZE); - mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); - mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); - break; -#endif - } - - /* Set up 64MB inbound memory window at 0 */ - out_le32(mbase + PCI_BASE_ADDRESS_0, 0); - out_le32(mbase + PCI_BASE_ADDRESS_1, 0); - - out_le32(mbase + PECFG_PIM01SAH, 0xffffffff); - out_le32(mbase + PECFG_PIM01SAL, 0xfc000000); - - /* Setup BAR0 */ - out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff); - out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64); - - /* Disable BAR1 & BAR2 */ - out_le32(mbase + PECFG_BAR1MPA, 0); - out_le32(mbase + PECFG_BAR2HMPA, 0); - out_le32(mbase + PECFG_BAR2LMPA, 0); - - out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE)); - out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE)); - out_le32(mbase + PECFG_PIMEN, 0x1); - - /* Enable I/O, Mem, and Busmaster cycles */ - out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */ - out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */ - - /* Set Class Code to Processor/PPC */ - out_le32(mbase + 0x208, 0x0b200001); - - attempts = 10; - while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE%d: BME not active\n", port); - return -1; - } - mdelay(1000); - } - - printf("PCIE%d: successfully set as endpoint\n", port); - - return 0; -} -#endif /* CONFIG_440SPE && CONFIG_PCI */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile deleted file mode 100644 index 365f966fed..0000000000 --- a/cpu/ppc4xx/Makefile +++ /dev/null @@ -1,93 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).a - -START := resetvec.o -START += start.o - -SOBJS := cache.o -SOBJS += dcr.o -SOBJS += kgdb.o - -COBJS := 40x_spd_sdram.o - -COBJS += 44x_spd_ddr.o -COBJS += 44x_spd_ddr2.o -ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION -COBJS += 4xx_ibm_ddr2_autocalib.o -endif -COBJS += 4xx_pci.o -COBJS += 4xx_pcie.o -COBJS += bedbug_405.o -ifdef CONFIG_CMD_CHIP_CONFIG -COBJS += cmd_chip_config.o -endif -COBJS += commproc.o -COBJS += cpu.o -COBJS += cpu_init.o -COBJS += denali_data_eye.o -COBJS += denali_spd_ddr2.o -COBJS += ecc.o -COBJS += fdt.o -COBJS += i2c.o -COBJS += interrupts.o -COBJS += iop480_uart.o -ifdef CONFIG_CMD_REGINFO -COBJS += reginfo.o -endif -COBJS += sdram.o -COBJS += speed.o -COBJS += tlb.o -COBJS += traps.o -COBJS += usb.o -COBJS += usb_ohci.o -COBJS += usbdev.o -ifndef CONFIG_XILINX_440 -COBJS += 4xx_uart.o -COBJS += gpio.o -COBJS += miiphy.o -COBJS += uic.o -else -COBJS += xilinx_irq.o -endif - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk deleted file mode 100644 index c1de1e97e6..0000000000 --- a/cpu/ppc4xx/config.mk +++ /dev/null @@ -1,37 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -meabi -PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float - -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is440:=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) - -ifneq (,$(findstring CONFIG_440,$(is440))) -PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 -else -PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405 -endif - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/ppc4xx/u-boot.lds diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c deleted file mode 100644 index ccd9993677..0000000000 --- a/cpu/ppc4xx/cpu_init.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2000-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) -DECLARE_GLOBAL_DATA_PTR; -#endif - -#ifndef CONFIG_SYS_PLL_RECONFIG -#define CONFIG_SYS_PLL_RECONFIG 0 -#endif - -void reconfigure_pll(u32 new_cpu_freq) -{ -#if defined(CONFIG_440EPX) - int reset_needed = 0; - u32 reg, temp; - u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */ - fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */ - fbdv, target_fbdv, lfbdv, target_lfbdv, - perdv0, target_perdv0, /* CLK_PERD */ - spcid0, target_spcid0; /* CLK_SPCID */ - - /* Reconfigure clocks if necessary. - * See PPC440EPx User's Manual, sections 8.2 and 14 */ - if (new_cpu_freq == 667) { - target_prbdv0 = 2; - target_fwdva = 2; - target_fwdvb = 4; - target_fbdv = 20; - target_lfbdv = 1; - target_perdv0 = 4; - target_spcid0 = 4; - - mfcpr(CPR0_PRIMBD0, reg); - temp = (reg & PRBDV_MASK) >> 24; - prbdv0 = temp ? temp : 8; - if (prbdv0 != target_prbdv0) { - reg &= ~PRBDV_MASK; - reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); - mtcpr(CPR0_PRIMBD0, reg); - reset_needed = 1; - } - - mfcpr(CPR0_PLLD, reg); - - temp = (reg & PLLD_FWDVA_MASK) >> 16; - fwdva = temp ? temp : 16; - - temp = (reg & PLLD_FWDVB_MASK) >> 8; - fwdvb = temp ? temp : 8; - - temp = (reg & PLLD_FBDV_MASK) >> 24; - fbdv = temp ? temp : 32; - - temp = (reg & PLLD_LFBDV_MASK); - lfbdv = temp ? temp : 64; - - if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) { - reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | - PLLD_FBDV_MASK | PLLD_LFBDV_MASK); - reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) | - ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | - ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | - (target_lfbdv == 64 ? 0 : target_lfbdv); - mtcpr(CPR0_PLLD, reg); - reset_needed = 1; - } - - mfcpr(CPR0_PERD, reg); - perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; - if (perdv0 != target_perdv0) { - reg &= ~CPR0_PERD_PERDV0_MASK; - reg |= (target_perdv0 << 24); - mtcpr(CPR0_PERD, reg); - reset_needed = 1; - } - - mfcpr(CPR0_SPCID, reg); - temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; - spcid0 = temp ? temp : 4; - if (spcid0 != target_spcid0) { - reg &= ~CPR0_SPCID_SPCIDV0_MASK; - reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); - mtcpr(CPR0_SPCID, reg); - reset_needed = 1; - } - - /* Set reload inhibit so configuration will persist across - * processor resets */ - mfcpr(CPR0_ICFG, reg); - reg &= ~CPR0_ICFG_RLI_MASK; - reg |= 1 << 31; - mtcpr(CPR0_ICFG, reg); - } - - /* Reset processor if configuration changed */ - if (reset_needed) { - __asm__ __volatile__ ("sync; isync"); - mtspr(SPRN_DBCR0, 0x20000000); - } -#endif -} - -/* - * Breath some life into the CPU... - * - * Reconfigure PLL if necessary, - * set up the memory map, - * initialize a bunch of registers - */ -void -cpu_init_f (void) -{ -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) - u32 val; -#endif - - reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); - -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) - /* - * GPIO0 setup (select GPIO or alternate function) - */ -#if defined(CONFIG_SYS_GPIO0_OR) - out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */ -#endif -#if defined(CONFIG_SYS_GPIO0_ODR) - out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */ -#endif - out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ - out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); - out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ - out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); - out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); -#if defined(CONFIG_SYS_GPIO0_ISR2H) - out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H); - out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L); -#endif -#if defined (CONFIG_SYS_GPIO0_TCR) - out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ -#endif -#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */ - -#if defined (CONFIG_405EP) - /* - * Set EMAC noise filter bits - */ - mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); -#endif /* CONFIG_405EP */ - -#if defined(CONFIG_SYS_4xx_GPIO_TABLE) - gpio_set_chip_configuration(); -#endif /* CONFIG_SYS_4xx_GPIO_TABLE */ - - /* - * External Bus Controller (EBC) Setup - */ -#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) -#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || defined(CONFIG_405)) - /* - * Move the next instructions into icache, since these modify the flash - * we are running from! - */ - asm volatile(" bl 0f" ::: "lr"); - asm volatile("0: mflr 3" ::: "r3"); - asm volatile(" addi 4, 0, 14" ::: "r4"); - asm volatile(" mtctr 4" ::: "ctr"); - asm volatile("1: icbt 0, 3"); - asm volatile(" addi 3, 3, 32" ::: "r3"); - asm volatile(" bdnz 1b" ::: "ctr", "cr0"); - asm volatile(" addis 3, 0, 0x0" ::: "r3"); - asm volatile(" ori 3, 3, 0xA000" ::: "r3"); - asm volatile(" mtctr 3" ::: "ctr"); - asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); -#endif - - mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); - mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); -#endif - -#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) - mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP); - mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR); -#endif - -#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) - mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP); - mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR); -#endif - -#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) - mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); - mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); -#endif - -#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) - mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP); - mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR); -#endif - -#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) - mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP); - mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR); -#endif - -#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) - mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP); - mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR); -#endif - -#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) - mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP); - mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR); -#endif - -#if defined (CONFIG_SYS_EBC_CFG) - mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG); -#endif - -#if defined(CONFIG_WATCHDOG) - val = mfspr(tcr); -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) - val |= 0xb8000000; /* generate system reset after 1.34 seconds */ -#elif defined(CONFIG_440EPX) - val |= 0xb0000000; /* generate system reset after 1.34 seconds */ -#else - val |= 0xf0000000; /* generate system reset after 2.684 seconds */ -#endif -#if defined(CONFIG_SYS_4xx_RESET_TYPE) - val &= ~0x30000000; /* clear WRC bits */ - val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */ -#endif - mtspr(tcr, val); - - val = mfspr(tsr); - val |= 0x80000000; /* enable watchdog timer */ - mtspr(tsr, val); - - reset_4xx_watchdog(); -#endif /* CONFIG_WATCHDOG */ - -#if defined(CONFIG_440GX) - /* Take the GX out of compatibility mode - * Travis Sawyer, 9 Mar 2004 - * NOTE: 440gx user manual inconsistency here - * Compatibility mode and Ethernet Clock select are not - * correct in the manual - */ - mfsdr(SDR0_MFR, val); - val &= ~0x10000000; - mtsdr(SDR0_MFR,val); -#endif /* CONFIG_440GX */ - -#if defined(CONFIG_460EX) - /* - * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and - * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata - * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA - */ - mfsdr(SDR0_AHB_CFG, val); - val |= 0x80; - val &= ~0x40; - mtsdr(SDR0_AHB_CFG, val); - mfsdr(SDR0_USB2HOST_CFG, val); - val &= ~0xf00; - val |= 0x400; - mtsdr(SDR0_USB2HOST_CFG, val); -#endif /* CONFIG_460EX */ - -#if defined(CONFIG_405EX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) - /* - * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read - */ - mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) | - PLB0_ACR_RDP_4DEEP); - mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) | - PLB1_ACR_RDP_4DEEP); -#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ -#if defined(CONFIG_405GP) - uint pvr = get_pvr(); - - /* - * Set edge conditioning circuitry on PPC405GPr - * for compatibility to existing PPC405GP designs. - */ - if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { - mtdcr(CPC0_ECR, 0x60606000); - } -#endif /* defined(CONFIG_405GP) */ - - return 0; -} - -#if defined(CONFIG_PCI) && \ - (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRX)) -/* - * 440EP(x)/GR(x) PCI async/sync clocking restriction: - * - * In asynchronous PCI mode, the synchronous PCI clock must meet - * certain requirements. The following equation describes the - * relationship that must be maintained between the asynchronous PCI - * clock and synchronous PCI clock. Select an appropriate PCI:PLB - * ratio to maintain the relationship: - * - * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz - */ -static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async) -{ - if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000))) - return 0; - else - return 1; -} - -int ppc4xx_pci_sync_clock_config(u32 async) -{ - sys_info_t sys_info; - u32 sync; - int div; - u32 reg; - u32 spcid_val[] = { - CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2, - CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 }; - - get_sys_info(&sys_info); - sync = sys_info.freqPCI; - - /* - * First check if the equation above is met - */ - if (!ppc4xx_pci_sync_clock_ok(sync, async)) { - /* - * Reconfigure PCI sync clock to meet the equation. - * Start with highest possible PCI sync frequency - * (divider 1). - */ - for (div = 1; div <= 4; div++) { - sync = sys_info.freqPLB / div; - if (ppc4xx_pci_sync_clock_ok(sync, async)) - break; - } - - if (div <= 4) { - mtcpr(CPR0_SPCID, spcid_val[div]); - - mfcpr(CPR0_ICFG, reg); - reg |= CPR0_ICFG_RLI_MASK; - mtcpr(CPR0_ICFG, reg); - - /* do chip reset */ - mtspr(SPRN_DBCR0, 0x20000000); - } else { - /* Impossible to configure the PCI sync clock */ - return -1; - } - } - - return 0; -} -#endif diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c deleted file mode 100644 index ffc3817449..0000000000 --- a/cpu/ppc4xx/denali_data_eye.c +++ /dev/null @@ -1,389 +0,0 @@ -/* - * cpu/ppc4xx/denali_data_eye.c - * Extracted from board/amcc/sequoia/sdram.c by Larry Johnson . - * - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include -#include -#include -#include - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/*-----------------------------------------------------------------------------+ - * denali_wait_for_dlllock. - +----------------------------------------------------------------------------*/ -int denali_wait_for_dlllock(void) -{ - u32 val; - int wait; - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - for (wait = 0; wait != 0xffff; ++wait) { - mfsdram(DDR0_17, val); - if (DDR0_17_DLLLOCKREG_DECODE(val)) { - /* dlllockreg bit on */ - return 0; - } - } - debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); - debug("Waiting for dlllockreg bit to raise\n"); - return -1; -} - -#if defined(CONFIG_DDR_DATA_EYE) -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -/*-----------------------------------------------------------------------------+ - * wait_for_dram_init_complete. - +----------------------------------------------------------------------------*/ -static int wait_for_dram_init_complete(void) -{ - unsigned long val; - int wait = 0; - - /* --------------------------------------------------------------+ - * Wait for 'DRAM initialization complete' bit in status register - * -------------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_00); - - while (wait != 0xffff) { - val = mfdcr(ddrcfgd); - if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) - /* 'DRAM initialization complete' bit */ - return 0; - else - wait++; - } - debug("DRAM initialization complete bit in status register did not " - "rise\n"); - return -1; -} - -#define NUM_TRIES 64 -#define NUM_READS 10 - -/*-----------------------------------------------------------------------------+ - * denali_core_search_data_eye. - +----------------------------------------------------------------------------*/ -void denali_core_search_data_eye(void) -{ - int k, j; - u32 val; - u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; - u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; - u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; - u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; - volatile u32 *ram_pointer; - u32 test[NUM_TRIES] = { - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 - }; - - ram_pointer = (volatile u32 *)(CONFIG_SYS_SDRAM_BASE); - - for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { - /* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */ - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | - DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'wr_dqs_shift' - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_09); - val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | - DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'dqs_out_shift' = wr_dqs_shift + 32 - * ----------------------------------------------------------*/ - dqs_out_shift = wr_dqs_shift + 32; - mtdcr(ddrcfga, DDR0_22); - val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | - DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); - mtdcr(ddrcfgd, val); - - passing_cases = 0; - - for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; - dll_dqs_delay_X++) { - /* for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; - dll_dqs_delay_X++) { */ - /* -----------------------------------------------------------+ - * Set 'dll_dqs_delay_X'. - * ----------------------------------------------------------*/ - /* dll_dqs_delay_0 */ - mtdcr(ddrcfga, DDR0_17); - val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) - | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* dll_dqs_delay_1 to dll_dqs_delay_4 */ - mtdcr(ddrcfga, DDR0_18); - val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) - | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* dll_dqs_delay_5 to dll_dqs_delay_8 */ - mtdcr(ddrcfga, DDR0_19); - val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) - | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - /* clear any ECC errors */ - mtdcr(ddrcfga, DDR0_00); - mtdcr(ddrcfgd, - mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); - - sync(); - eieio(); - - /* -----------------------------------------------------------+ - * Assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | - DDR0_02_START_ON; - mtdcr(ddrcfgd, val); - - sync(); - eieio(); - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - if (denali_wait_for_dlllock() != 0) { - printf("dll lock did not occur !!!\n"); - printf("denali_core_search_data_eye!!!\n"); - printf("wr_dqs_shift = %d - dll_dqs_delay_X = " - "%d\n", wr_dqs_shift, dll_dqs_delay_X); - hang(); - } - sync(); - eieio(); - - if (wait_for_dram_init_complete() != 0) { - printf("dram init complete did not occur!!!\n"); - printf("denali_core_search_data_eye!!!\n"); - printf("wr_dqs_shift = %d - dll_dqs_delay_X = " - "%d\n", wr_dqs_shift, dll_dqs_delay_X); - hang(); - } - udelay(100); /* wait 100us to ensure init is really completed !!! */ - - /* write values */ - for (j = 0; j < NUM_TRIES; j++) { - ram_pointer[j] = test[j]; - - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r"(&ram_pointer[j])); - } - - /* read values back */ - for (j = 0; j < NUM_TRIES; j++) { - for (k = 0; k < NUM_READS; k++) { - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r"(&ram_pointer - [j])); - - if (ram_pointer[j] != test[j]) - break; - } - - /* read error */ - if (k != NUM_READS) - break; - } - - /* See if the dll_dqs_delay_X value passed. */ - mtdcr(ddrcfga, DDR0_00); - if (j < NUM_TRIES - || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & - 0x3F)) { - /* Failed */ - passing_cases = 0; - /* break; */ - } else { - /* Passed */ - if (passing_cases == 0) - dll_dqs_delay_X_sw_val = - dll_dqs_delay_X; - passing_cases++; - if (passing_cases >= max_passing_cases) { - max_passing_cases = passing_cases; - wr_dqs_shift_with_max_passing_cases = - wr_dqs_shift; - dll_dqs_delay_X_start_window = - dll_dqs_delay_X_sw_val; - dll_dqs_delay_X_end_window = - dll_dqs_delay_X; - } - } - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | - DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ - } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ - - /* -----------------------------------------------------------+ - * Largest passing window is now detected. - * ----------------------------------------------------------*/ - - /* Compute dll_dqs_delay_X value */ - dll_dqs_delay_X = (dll_dqs_delay_X_end_window + - dll_dqs_delay_X_start_window) / 2; - wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; - - debug("DQS calibration - Window detected:\n"); - debug("max_passing_cases = %d\n", max_passing_cases); - debug("wr_dqs_shift = %d\n", wr_dqs_shift); - debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); - debug("dll_dqs_delay_X window = %d - %d\n", - dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); - - /* -----------------------------------------------------------+ - * De-assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; - mtdcr(ddrcfgd, val); - - /* -----------------------------------------------------------+ - * Set 'wr_dqs_shift' - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_09); - val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) - | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); - mtdcr(ddrcfgd, val); - debug("DDR0_09=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Set 'dqs_out_shift' = wr_dqs_shift + 32 - * ----------------------------------------------------------*/ - dqs_out_shift = wr_dqs_shift + 32; - mtdcr(ddrcfga, DDR0_22); - val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) - | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); - mtdcr(ddrcfgd, val); - debug("DDR0_22=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Set 'dll_dqs_delay_X'. - * ----------------------------------------------------------*/ - /* dll_dqs_delay_0 */ - mtdcr(ddrcfga, DDR0_17); - val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) - | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_17=0x%08lx\n", val); - - /* dll_dqs_delay_1 to dll_dqs_delay_4 */ - mtdcr(ddrcfga, DDR0_18); - val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) - | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) - | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_18=0x%08lx\n", val); - - /* dll_dqs_delay_5 to dll_dqs_delay_8 */ - mtdcr(ddrcfga, DDR0_19); - val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) - | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) - | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); - mtdcr(ddrcfgd, val); - debug("DDR0_19=0x%08lx\n", val); - - /* -----------------------------------------------------------+ - * Assert 'start' parameter. - * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_02); - val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; - mtdcr(ddrcfgd, val); - - sync(); - eieio(); - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - if (denali_wait_for_dlllock() != 0) { - printf("dll lock did not occur !!!\n"); - hang(); - } - sync(); - eieio(); - - if (wait_for_dram_init_complete() != 0) { - printf("dram init complete did not occur !!!\n"); - hang(); - } - udelay(100); /* wait 100us to ensure init is really completed !!! */ -} -#endif /* defined(CONFIG_DDR_DATA_EYE) */ -#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c deleted file mode 100644 index 5858cb36a5..0000000000 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ /dev/null @@ -1,1256 +0,0 @@ -/* - * cpu/ppc4xx/denali_spd_ddr2.c - * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core - * DDR2 controller, specifically the 440EPx/GRx. - * - * (C) Copyright 2007-2008 - * Larry Johnson, lrj@acm.org. - * - * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... - * - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * COPYRIGHT AMCC CORPORATION 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SPD_EEPROM) && \ - (defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) - -/*-----------------------------------------------------------------------------+ - * Defines - *-----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -#define MAXDIMMS 2 -#define MAXRANKS 2 - -#define ONE_BILLION 1000000000 - -#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) - -#define DLL_DQS_DELAY 0x19 -#define DLL_DQS_BYPASS 0x0B -#define DQS_OUT_SHIFT 0x7F - -/* - * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory - * region. Right now the cache should still be disabled in U-Boot because of the - * EMAC driver, that need it's buffer descriptor to be located in non cached - * memory. - * - * If at some time this restriction doesn't apply anymore, just define - * CONFIG_4xx_DCACHE in the board config file and this code should setup - * everything correctly. - */ -#if defined(CONFIG_4xx_DCACHE) -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ -#else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ -#endif - -/*-----------------------------------------------------------------------------+ - * Prototypes - *-----------------------------------------------------------------------------*/ -extern int denali_wait_for_dlllock(void); -extern void denali_core_search_data_eye(void); -extern void dcbz_area(u32 start_address, u32 num_bytes); - -/* - * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed - */ -void __spd_ddr_init_hang(void) -{ - hang(); -} -void spd_ddr_init_hang(void) - __attribute__ ((weak, alias("__spd_ddr_init_hang"))); - -#if defined(DEBUG) -static void print_mcsr(void) -{ - printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR)); -} - -static void denali_sdram_register_dump(void) -{ - unsigned int sdram_data; - - printf("\n Register Dump:\n"); - mfsdram(DDR0_00, sdram_data); - printf(" DDR0_00 = 0x%08X", sdram_data); - mfsdram(DDR0_01, sdram_data); - printf(" DDR0_01 = 0x%08X\n", sdram_data); - mfsdram(DDR0_02, sdram_data); - printf(" DDR0_02 = 0x%08X", sdram_data); - mfsdram(DDR0_03, sdram_data); - printf(" DDR0_03 = 0x%08X\n", sdram_data); - mfsdram(DDR0_04, sdram_data); - printf(" DDR0_04 = 0x%08X", sdram_data); - mfsdram(DDR0_05, sdram_data); - printf(" DDR0_05 = 0x%08X\n", sdram_data); - mfsdram(DDR0_06, sdram_data); - printf(" DDR0_06 = 0x%08X", sdram_data); - mfsdram(DDR0_07, sdram_data); - printf(" DDR0_07 = 0x%08X\n", sdram_data); - mfsdram(DDR0_08, sdram_data); - printf(" DDR0_08 = 0x%08X", sdram_data); - mfsdram(DDR0_09, sdram_data); - printf(" DDR0_09 = 0x%08X\n", sdram_data); - mfsdram(DDR0_10, sdram_data); - printf(" DDR0_10 = 0x%08X", sdram_data); - mfsdram(DDR0_11, sdram_data); - printf(" DDR0_11 = 0x%08X\n", sdram_data); - mfsdram(DDR0_12, sdram_data); - printf(" DDR0_12 = 0x%08X", sdram_data); - mfsdram(DDR0_14, sdram_data); - printf(" DDR0_14 = 0x%08X\n", sdram_data); - mfsdram(DDR0_17, sdram_data); - printf(" DDR0_17 = 0x%08X", sdram_data); - mfsdram(DDR0_18, sdram_data); - printf(" DDR0_18 = 0x%08X\n", sdram_data); - mfsdram(DDR0_19, sdram_data); - printf(" DDR0_19 = 0x%08X", sdram_data); - mfsdram(DDR0_20, sdram_data); - printf(" DDR0_20 = 0x%08X\n", sdram_data); - mfsdram(DDR0_21, sdram_data); - printf(" DDR0_21 = 0x%08X", sdram_data); - mfsdram(DDR0_22, sdram_data); - printf(" DDR0_22 = 0x%08X\n", sdram_data); - mfsdram(DDR0_23, sdram_data); - printf(" DDR0_23 = 0x%08X", sdram_data); - mfsdram(DDR0_24, sdram_data); - printf(" DDR0_24 = 0x%08X\n", sdram_data); - mfsdram(DDR0_25, sdram_data); - printf(" DDR0_25 = 0x%08X", sdram_data); - mfsdram(DDR0_26, sdram_data); - printf(" DDR0_26 = 0x%08X\n", sdram_data); - mfsdram(DDR0_27, sdram_data); - printf(" DDR0_27 = 0x%08X", sdram_data); - mfsdram(DDR0_28, sdram_data); - printf(" DDR0_28 = 0x%08X\n", sdram_data); - mfsdram(DDR0_31, sdram_data); - printf(" DDR0_31 = 0x%08X", sdram_data); - mfsdram(DDR0_32, sdram_data); - printf(" DDR0_32 = 0x%08X\n", sdram_data); - mfsdram(DDR0_33, sdram_data); - printf(" DDR0_33 = 0x%08X", sdram_data); - mfsdram(DDR0_34, sdram_data); - printf(" DDR0_34 = 0x%08X\n", sdram_data); - mfsdram(DDR0_35, sdram_data); - printf(" DDR0_35 = 0x%08X", sdram_data); - mfsdram(DDR0_36, sdram_data); - printf(" DDR0_36 = 0x%08X\n", sdram_data); - mfsdram(DDR0_37, sdram_data); - printf(" DDR0_37 = 0x%08X", sdram_data); - mfsdram(DDR0_38, sdram_data); - printf(" DDR0_38 = 0x%08X\n", sdram_data); - mfsdram(DDR0_39, sdram_data); - printf(" DDR0_39 = 0x%08X", sdram_data); - mfsdram(DDR0_40, sdram_data); - printf(" DDR0_40 = 0x%08X\n", sdram_data); - mfsdram(DDR0_41, sdram_data); - printf(" DDR0_41 = 0x%08X", sdram_data); - mfsdram(DDR0_42, sdram_data); - printf(" DDR0_42 = 0x%08X\n", sdram_data); - mfsdram(DDR0_43, sdram_data); - printf(" DDR0_43 = 0x%08X", sdram_data); - mfsdram(DDR0_44, sdram_data); - printf(" DDR0_44 = 0x%08X\n", sdram_data); -} -#else -static inline void denali_sdram_register_dump(void) -{ -} - -inline static void print_mcsr(void) -{ -} -#endif /* defined(DEBUG) */ - -static int is_ecc_enabled(void) -{ - u32 val; - - mfsdram(DDR0_22, val); - return 0x3 == DDR0_22_CTRL_RAW_DECODE(val); -} - -static unsigned char spd_read(u8 chip, unsigned int addr) -{ - u8 data[2]; - - if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) { - debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr); - return 0; - } - debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n", - chip, addr, data[0]); - return data[0]; -} - -static unsigned long get_tcyc(unsigned char reg) -{ - /* - * Byte 9, et al: Cycle time for CAS Latency=X, is split into two - * nibbles: the higher order nibble (bits 4-7) designates the cycle time - * to a granularity of 1ns; the value presented by the lower order - * nibble (bits 0-3) has a granularity of .1ns and is added to the value - * designated by the higher nibble. In addition, four lines of the lower - * order nibble are assigned to support +.25, +.33, +.66, and +.75. - */ - - unsigned char subfield_b = reg & 0x0F; - - switch (subfield_b & 0x0F) { - case 0x0: - case 0x1: - case 0x2: - case 0x3: - case 0x4: - case 0x5: - case 0x6: - case 0x7: - case 0x8: - case 0x9: - return 1000 * (reg >> 4) + 100 * subfield_b; - case 0xA: - return 1000 * (reg >> 4) + 250; - case 0xB: - return 1000 * (reg >> 4) + 333; - case 0xC: - return 1000 * (reg >> 4) + 667; - case 0xD: - return 1000 * (reg >> 4) + 750; - } - return 0; -} - -/*------------------------------------------------------------------ - * Find the installed DIMMs, make sure that the are DDR2, and fill - * in the dimm_ranks array. Then dimm_ranks[dimm_num] > 0 iff the - * DIMM and dimm_num is present. - * Note: Because there are only two chip-select lines, it is assumed - * that a board with a single socket can support two ranks on that - * socket, while a board with two sockets can support only one rank - * on each socket. - *-----------------------------------------------------------------*/ -static void get_spd_info(unsigned long dimm_ranks[], - unsigned long *ranks, - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long dimm_found = FALSE; - unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1; - unsigned char num_of_bytes; - unsigned char total_size; - - *ranks = 0; - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - num_of_bytes = 0; - total_size = 0; - - num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); - total_size = spd_read(iic0_dimm_addr[dimm_num], 1); - if ((num_of_bytes != 0) && (total_size != 0)) { - unsigned char const dimm_type = - spd_read(iic0_dimm_addr[dimm_num], 2); - - unsigned long ranks_on_dimm = - (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1; - - if (8 != dimm_type) { - switch (dimm_type) { - case 1: - printf("ERROR: Standard Fast Page Mode " - "DRAM DIMM"); - break; - case 2: - printf("ERROR: EDO DIMM"); - break; - case 3: - printf("ERROR: Pipelined Nibble DIMM"); - break; - case 4: - printf("ERROR: SDRAM DIMM"); - break; - case 5: - printf("ERROR: Multiplexed ROM DIMM"); - break; - case 6: - printf("ERROR: SGRAM DIMM"); - break; - case 7: - printf("ERROR: DDR1 DIMM"); - break; - default: - printf("ERROR: Unknown DIMM (type %d)", - (unsigned int)dimm_type); - break; - } - printf(" detected in slot %lu.\n", dimm_num); - printf("Only DDR2 SDRAM DIMMs are supported." - "\n"); - printf("Replace the module with a DDR2 DIMM." - "\n\n"); - spd_ddr_init_hang(); - } - dimm_found = TRUE; - debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM" - "\n", dimm_num, ranks_on_dimm); - if (ranks_on_dimm > max_ranks_per_dimm) { - printf("WARNING: DRAM DIMM in slot %lu has %lu " - "ranks.\n", dimm_num, ranks_on_dimm); - if (1 == max_ranks_per_dimm) { - printf("Only one rank will be used.\n"); - } else { - printf - ("Only two ranks will be used.\n"); - } - ranks_on_dimm = max_ranks_per_dimm; - } - dimm_ranks[dimm_num] = ranks_on_dimm; - *ranks += ranks_on_dimm; - } else { - dimm_ranks[dimm_num] = 0; - debug("DIMM slot %lu: Not populated\n", dimm_num); - } - } - if (dimm_found == FALSE) { - printf("ERROR: No memory installed.\n"); - printf("Install at least one DDR2 DIMM.\n\n"); - spd_ddr_init_hang(); - } - debug("Total number of ranks = %d\n", *ranks); -} - -/*------------------------------------------------------------------ - * For the memory DIMMs installed, this routine verifies that - * frequency previously calculated is supported. - *-----------------------------------------------------------------*/ -static void check_frequency(unsigned long *dimm_ranks, - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, - unsigned long sdram_freq) -{ - unsigned long dimm_num; - unsigned long cycle_time; - unsigned long calc_cycle_time; - - /* - * calc_cycle_time is calculated from DDR frequency set by board/chip - * and is expressed in picoseconds to match the way DIMM cycle time is - * calculated below. - */ - calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq); - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_ranks[dimm_num]) { - cycle_time = - get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9)); - debug("cycle_time=%d ps\n", cycle_time); - - if (cycle_time > (calc_cycle_time + 10)) { - /* - * the provided sdram cycle_time is too small - * for the available DIMM cycle_time. The - * additionnal 10ps is here to accept a small - * incertainty. - */ - printf - ("ERROR: DRAM DIMM detected with cycle_time %d ps in " - "slot %d \n while calculated cycle time is %d ps.\n", - (unsigned int)cycle_time, - (unsigned int)dimm_num, - (unsigned int)calc_cycle_time); - printf - ("Replace the DIMM, or change DDR frequency via " - "strapping bits.\n\n"); - spd_ddr_init_hang(); - } - } - } -} - -/*------------------------------------------------------------------ - * This routine gets size information for the installed memory - * DIMMs. - *-----------------------------------------------------------------*/ -static void get_dimm_size(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, - unsigned long *const rows, - unsigned long *const banks, - unsigned long *const cols, unsigned long *const width) -{ - unsigned long dimm_num; - - *rows = 0; - *banks = 0; - *cols = 0; - *width = 0; - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_ranks[dimm_num]) { - unsigned long t; - - /* Rows */ - t = spd_read(iic0_dimm_addr[dimm_num], 3); - if (0 == *rows) { - *rows = t; - } else if (t != *rows) { - printf("ERROR: DRAM DIMM modules do not all " - "have the same number of rows.\n\n"); - spd_ddr_init_hang(); - } - /* Banks */ - t = spd_read(iic0_dimm_addr[dimm_num], 17); - if (0 == *banks) { - *banks = t; - } else if (t != *banks) { - printf("ERROR: DRAM DIMM modules do not all " - "have the same number of banks.\n\n"); - spd_ddr_init_hang(); - } - /* Columns */ - t = spd_read(iic0_dimm_addr[dimm_num], 4); - if (0 == *cols) { - *cols = t; - } else if (t != *cols) { - printf("ERROR: DRAM DIMM modules do not all " - "have the same number of columns.\n\n"); - spd_ddr_init_hang(); - } - /* Data width */ - t = spd_read(iic0_dimm_addr[dimm_num], 6); - if (0 == *width) { - *width = t; - } else if (t != *width) { - printf("ERROR: DRAM DIMM modules do not all " - "have the same data width.\n\n"); - spd_ddr_init_hang(); - } - } - } - debug("Number of rows = %d\n", *rows); - debug("Number of columns = %d\n", *cols); - debug("Number of banks = %d\n", *banks); - debug("Data width = %d\n", *width); - if (*rows > 14) { - printf("ERROR: DRAM DIMM modules have %lu address rows.\n", - *rows); - printf("Only modules with 14 or fewer rows are supported.\n\n"); - spd_ddr_init_hang(); - } - if (4 != *banks && 8 != *banks) { - printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks); - printf("Only modules with 4 or 8 banks are supported.\n\n"); - spd_ddr_init_hang(); - } - if (*cols > 12) { - printf("ERROR: DRAM DIMM modules have %lu address columns.\n", - *cols); - printf("Only modules with 12 or fewer columns are " - "supported.\n\n"); - spd_ddr_init_hang(); - } - if (32 != *width && 40 != *width && 64 != *width && 72 != *width) { - printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n", - *width); - printf("Only modules with widths of 32, 40, 64, and 72 bits " - "are supported.\n\n"); - spd_ddr_init_hang(); - } -} - -/*------------------------------------------------------------------ - * Only 1.8V modules are supported. This routine verifies this. - *-----------------------------------------------------------------*/ -static void check_voltage_type(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long voltage_type; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_ranks[dimm_num]) { - voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); - if (0x05 != voltage_type) { /* 1.8V for DDR2 */ - printf("ERROR: Slot %lu provides 1.8V for DDR2 " - "DIMMs.\n", dimm_num); - switch (voltage_type) { - case 0x00: - printf("This DIMM is 5.0 Volt/TTL.\n"); - break; - case 0x01: - printf("This DIMM is LVTTL.\n"); - break; - case 0x02: - printf("This DIMM is 1.5 Volt.\n"); - break; - case 0x03: - printf("This DIMM is 3.3 Volt/TTL.\n"); - break; - case 0x04: - printf("This DIMM is 2.5 Volt.\n"); - break; - default: - printf("This DIMM is an unknown " - "voltage.\n"); - break; - } - printf("Replace it with a 1.8V DDR2 DIMM.\n\n"); - spd_ddr_init_hang(); - } - } - } -} - -static void program_ddr0_03(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, - unsigned long sdram_freq, - unsigned long rows, unsigned long *cas_latency) -{ - unsigned long dimm_num; - unsigned long cas_index; - unsigned long cycle_2_0_clk; - unsigned long cycle_3_0_clk; - unsigned long cycle_4_0_clk; - unsigned long cycle_5_0_clk; - unsigned long max_2_0_tcyc_ps = 100; - unsigned long max_3_0_tcyc_ps = 100; - unsigned long max_4_0_tcyc_ps = 100; - unsigned long max_5_0_tcyc_ps = 100; - unsigned char cas_available = 0x3C; /* value for DDR2 */ - u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2); - unsigned int const tcyc_addr[3] = { 9, 23, 25 }; - - /*------------------------------------------------------------------ - * Get the board configuration info. - *-----------------------------------------------------------------*/ - debug("sdram_freq = %d\n", sdram_freq); - - /*------------------------------------------------------------------ - * Handle the timing. We need to find the worst case timing of all - * the dimm modules installed. - *-----------------------------------------------------------------*/ - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_ranks[dimm_num]) { - unsigned char const cas_bit = - spd_read(iic0_dimm_addr[dimm_num], 18); - unsigned char cas_mask; - - cas_available &= cas_bit; - for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) { - if (cas_bit & cas_mask) - break; - } - debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n", - cas_bit, cas_mask); - - for (cas_index = 0; cas_index < 3; - cas_mask >>= 1, cas_index++) { - unsigned long cycle_time_ps; - - if (!(cas_available & cas_mask)) { - continue; - } - cycle_time_ps = - get_tcyc(spd_read(iic0_dimm_addr[dimm_num], - tcyc_addr[cas_index])); - - debug("cas_index = %d: cycle_time_ps = %d\n", - cas_index, cycle_time_ps); - /* - * DDR2 devices use the following bitmask for CAS latency: - * Bit 7 6 5 4 3 2 1 0 - * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD - */ - switch (cas_mask) { - case 0x20: - max_5_0_tcyc_ps = - max(max_5_0_tcyc_ps, cycle_time_ps); - break; - case 0x10: - max_4_0_tcyc_ps = - max(max_4_0_tcyc_ps, cycle_time_ps); - break; - case 0x08: - max_3_0_tcyc_ps = - max(max_3_0_tcyc_ps, cycle_time_ps); - break; - case 0x04: - max_2_0_tcyc_ps = - max(max_2_0_tcyc_ps, cycle_time_ps); - break; - } - } - } - } - debug("cas_available (bit map) = 0x%02X\n", cas_available); - - /*------------------------------------------------------------------ - * Set the SDRAM mode, SDRAM_MMODE - *-----------------------------------------------------------------*/ - - /* add 10 here because of rounding problems */ - cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10; - cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10; - cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10; - cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10; - debug("cycle_2_0_clk = %d\n", cycle_2_0_clk); - debug("cycle_3_0_clk = %d\n", cycle_3_0_clk); - debug("cycle_4_0_clk = %d\n", cycle_4_0_clk); - debug("cycle_5_0_clk = %d\n", cycle_5_0_clk); - - if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) { - *cas_latency = 2; - ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) | - DDR0_03_CASLAT_LIN_ENCODE(0x4); - } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) { - *cas_latency = 3; - ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) | - DDR0_03_CASLAT_LIN_ENCODE(0x6); - } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) { - *cas_latency = 4; - ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) | - DDR0_03_CASLAT_LIN_ENCODE(0x8); - } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) { - *cas_latency = 5; - ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) | - DDR0_03_CASLAT_LIN_ENCODE(0xA); - } else { - printf("ERROR: Cannot find a supported CAS latency with the " - "installed DIMMs.\n"); - printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, " - "and 5.0 are supported.\n"); - printf("Make sure the PLB speed is within the supported range " - "of the DIMMs.\n"); - printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld " - "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk, - cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); - spd_ddr_init_hang(); - } - debug("CAS latency = %d\n", *cas_latency); - mtsdram(DDR0_03, ddr0_03); -} - -static void program_ddr0_04(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, - unsigned long sdram_freq) -{ - unsigned long dimm_num; - unsigned long t_rc_ps = 0; - unsigned long t_rrd_ps = 0; - unsigned long t_rtp_ps = 0; - unsigned long t_rc_clk; - unsigned long t_rrd_clk; - unsigned long t_rtp_clk; - - /*------------------------------------------------------------------ - * Handle the timing. We need to find the worst case timing of all - * the dimm modules installed. - *-----------------------------------------------------------------*/ - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_ranks[dimm_num]) { - unsigned long ps; - - /* tRC */ - ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41); - switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) { - case 0x1: - ps += 250; - break; - case 0x2: - ps += 333; - break; - case 0x3: - ps += 500; - break; - case 0x4: - ps += 667; - break; - case 0x5: - ps += 750; - break; - } - t_rc_ps = max(t_rc_ps, ps); - /* tRRD */ - ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28); - t_rrd_ps = max(t_rrd_ps, ps); - /* tRTP */ - ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38); - t_rtp_ps = max(t_rtp_ps, ps); - } - } - debug("t_rc_ps = %d\n", t_rc_ps); - t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000; - debug("t_rrd_ps = %d\n", t_rrd_ps); - t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000; - debug("t_rtp_ps = %d\n", t_rtp_ps); - t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000; - mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) | - DDR0_04_TRRD_ENCODE(t_rrd_clk) | - DDR0_04_TRTP_ENCODE(t_rtp_clk)); -} - -static void program_ddr0_05(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, - unsigned long sdram_freq) -{ - unsigned long dimm_num; - unsigned long t_rp_ps = 0; - unsigned long t_ras_ps = 0; - unsigned long t_rp_clk; - unsigned long t_ras_clk; - u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2); - - /*------------------------------------------------------------------ - * Handle the timing. We need to find the worst case timing of all - * the dimm modules installed. - *-----------------------------------------------------------------*/ - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_ranks[dimm_num]) { - unsigned long ps; - - /* tRP */ - ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27); - t_rp_ps = max(t_rp_ps, ps); - /* tRAS */ - ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30); - t_ras_ps = max(t_ras_ps, ps); - } - } - debug("t_rp_ps = %d\n", t_rp_ps); - t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000; - debug("t_ras_ps = %d\n", t_ras_ps); - t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000; - mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) | - DDR0_05_TRAS_MIN_ENCODE(t_ras_clk)); -} - -static void program_ddr0_06(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, - unsigned long sdram_freq) -{ - unsigned long dimm_num; - unsigned char spd_40; - unsigned long t_wtr_ps = 0; - unsigned long t_rfc_ps = 0; - unsigned long t_wtr_clk; - unsigned long t_rfc_clk; - u32 ddr0_06 = - DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200); - - /*------------------------------------------------------------------ - * Handle the timing. We need to find the worst case timing of all - * the dimm modules installed. - *-----------------------------------------------------------------*/ - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_ranks[dimm_num]) { - unsigned long ps; - - /* tWTR */ - ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37); - t_wtr_ps = max(t_wtr_ps, ps); - /* tRFC */ - ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42); - spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40); - ps += 256000 * (spd_40 & 0x01); - switch ((spd_40 & 0x0E) >> 1) { - case 0x1: - ps += 250; - break; - case 0x2: - ps += 333; - break; - case 0x3: - ps += 500; - break; - case 0x4: - ps += 667; - break; - case 0x5: - ps += 750; - break; - } - t_rfc_ps = max(t_rfc_ps, ps); - } - } - debug("t_wtr_ps = %d\n", t_wtr_ps); - t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000; - debug("t_rfc_ps = %d\n", t_rfc_ps); - t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000; - mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) | - DDR0_06_TRFC_ENCODE(t_rfc_clk)); -} - -static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks) -{ - unsigned long csmap; - - if (2 == ranks) { - /* Both chip selects in use */ - csmap = 0x03; - } else { - /* One chip select in use */ - csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2; - } - mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) | - DDR0_10_CS_MAP_ENCODE(csmap) | - DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0)); -} - -static void program_ddr0_11(unsigned long sdram_freq) -{ - unsigned long const t_xsnr_ps = 200000; /* 200 ns */ - unsigned long t_xsnr_clk; - - debug("t_xsnr_ps = %d\n", t_xsnr_ps); - t_xsnr_clk = - (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000; - mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) | - DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200)); -} - -static void program_ddr0_22(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, unsigned long width) -{ -#if defined(CONFIG_DDR_ECC) - unsigned long dimm_num; - unsigned long ecc_available = width >= 64; - u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | - DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | - DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS); - - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_ranks[dimm_num]) { - /* Check for ECC */ - if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) & - 0x02)) { - ecc_available = FALSE; - } - } - } - if (ecc_available) { - debug("ECC found on all DIMMs present\n"); - mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3)); - } else { - debug("ECC not found on some or all DIMMs present\n"); - mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0)); - } -#else - mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) | - DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) | - DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) | - DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS)); -#endif /* defined(CONFIG_DDR_ECC) */ -} - -static void program_ddr0_24(unsigned long ranks) -{ - u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */ - DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0); - - if (2 == ranks) { - /* Both chip selects in use */ - ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) | - DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2); - } else { - /* One chip select in use */ - /* One of the two fields added to ddr0_24 is a "don't care" */ - ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) | - DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1); - } - mtsdram(DDR0_24, ddr0_24); -} - -static void program_ddr0_26(unsigned long sdram_freq) -{ - unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */ - /* TODO: check definition of tRAS_MAX */ - unsigned long const t_ras_max_ps = 9 * t_ref_ps; - unsigned long t_ras_max_clk; - unsigned long t_ref_clk; - - /* Round down t_ras_max_clk and t_ref_clk */ - debug("t_ras_max_ps = %d\n", t_ras_max_ps); - t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000; - debug("t_ref_ps = %d\n", t_ref_ps); - t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000; - mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) | - DDR0_26_TREF_ENCODE(t_ref_clk)); -} - -static void program_ddr0_27(unsigned long sdram_freq) -{ - unsigned long const t_init_ps = 200000000; /* 200 us. init */ - unsigned long t_init_clk; - - debug("t_init_ps = %d\n", t_init_ps); - t_init_clk = - (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000; - mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) | - DDR0_27_TINIT_ENCODE(t_init_clk)); -} - -static void program_ddr0_43(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, - unsigned long sdram_freq, - unsigned long cols, unsigned long banks) -{ - unsigned long dimm_num; - unsigned long t_wr_ps = 0; - unsigned long t_wr_clk; - u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) | - DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) | - DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0); - - /*------------------------------------------------------------------ - * Handle the timing. We need to find the worst case timing of all - * the dimm modules installed. - *-----------------------------------------------------------------*/ - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_ranks[dimm_num]) { - unsigned long ps; - - ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36); - t_wr_ps = max(t_wr_ps, ps); - } - } - debug("t_wr_ps = %d\n", t_wr_ps); - t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000; - mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk)); -} - -static void program_ddr0_44(unsigned long dimm_ranks[], - unsigned char const iic0_dimm_addr[], - unsigned long num_dimm_banks, - unsigned long sdram_freq) -{ - unsigned long dimm_num; - unsigned long t_rcd_ps = 0; - unsigned long t_rcd_clk; - - /*------------------------------------------------------------------ - * Handle the timing. We need to find the worst case timing of all - * the dimm modules installed. - *-----------------------------------------------------------------*/ - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - /* If a dimm is installed in a particular slot ... */ - if (dimm_ranks[dimm_num]) { - unsigned long ps; - - ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29); - t_rcd_ps = max(t_rcd_ps, ps); - } - } - debug("t_rcd_ps = %d\n", t_rcd_ps); - t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000; - mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk)); -} - -/*-----------------------------------------------------------------------------+ - * initdram. Initializes the 440EPx/GPx DDR SDRAM controller. - * Note: This routine runs from flash with a stack set up in the chip's - * sram space. It is important that the routine does not require .sbss, .bss or - * .data sections. It also cannot call routines that require these sections. - *-----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------- - * Function: initdram - * Description: Configures SDRAM memory banks for DDR operation. - * Auto Memory Configuration option reads the DDR SDRAM EEPROMs - * via the IIC bus and then configures the DDR SDRAM memory - * banks appropriately. If Auto Memory Configuration is - * not used, it is assumed that no DIMM is plugged - *-----------------------------------------------------------------------------*/ -phys_size_t initdram(int board_type) -{ - unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; - unsigned long dimm_ranks[MAXDIMMS]; - unsigned long ranks; - unsigned long rows; - unsigned long banks; - unsigned long cols; - unsigned long width; - unsigned long const sdram_freq = get_bus_freq(0); - unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */ - unsigned long cas_latency = 0; /* to quiet initialization warning */ - unsigned long dram_size; - - debug("\nEntering initdram()\n"); - - /*------------------------------------------------------------------ - * Stop the DDR-SDRAM controller. - *-----------------------------------------------------------------*/ - mtsdram(DDR0_02, DDR0_02_START_ENCODE(0)); - - /* - * Make sure I2C controller is initialized - * before continuing. - */ - /* switch to correct I2C bus */ - I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /*------------------------------------------------------------------ - * Clear out the serial presence detect buffers. - * Perform IIC reads from the dimm. Fill in the spds. - * Check to see if the dimm slots are populated - *-----------------------------------------------------------------*/ - get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Check the frequency supported for the dimms plugged. - *-----------------------------------------------------------------*/ - check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); - - /*------------------------------------------------------------------ - * Check and get size information. - *-----------------------------------------------------------------*/ - get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks, - &cols, &width); - - /*------------------------------------------------------------------ - * Check the voltage type for the dimms plugged. - *-----------------------------------------------------------------*/ - check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks); - - /*------------------------------------------------------------------ - * Program registers for SDRAM controller. - *-----------------------------------------------------------------*/ - mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | - DDR0_00_DLL_START_POINT_DECODE(0x0A)); - - mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) | - DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) | - DDR0_01_INT_MASK_ENCODE(0xFF)); - - program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, - rows, &cas_latency); - - program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); - - program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); - - program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); - - /* - * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia - * board SDRAM, but may be overly conservative. - */ - mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | - DDR0_07_TFAW_ENCODE(13) | - DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | - DDR0_07_AREFRESH_ENCODE(0)); - - mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) | - DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) | - DDR0_08_DDRII_ENCODE(1)); - - mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) | - DDR0_09_RTT_0_ENCODE(0x1) | - DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) | - DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20)); - - program_ddr0_10(dimm_ranks, ranks); - - program_ddr0_11(sdram_freq); - - mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3)); - - mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) | - DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) | - DDR0_14_REG_DIMM_ENABLE_ENCODE(0)); - - mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY)); - - mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) | - DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) | - DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) | - DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY)); - - mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) | - DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) | - DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) | - DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY)); - - mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) | - DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) | - DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) | - DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS)); - - mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) | - DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) | - DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) | - DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS)); - - program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width); - - mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) | - DDR0_23_FWC_ENCODE(0)); - - program_ddr0_24(ranks); - - program_ddr0_26(sdram_freq); - - program_ddr0_27(sdram_freq); - - mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) | - DDR0_28_EMRS2_DATA_ENCODE(0x0000)); - - mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); - - mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) | - DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); - - program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, - cols, banks); - - program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); - - denali_sdram_register_dump(); - - dram_size = (width >= 64) ? 8 : 4; - dram_size *= 1 << cols; - dram_size *= banks; - dram_size *= 1 << rows; - dram_size *= ranks; - debug("dram_size = %lu\n", dram_size); - - /* Start the SDRAM controler */ - mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); - denali_wait_for_dlllock(); - -#if defined(CONFIG_DDR_DATA_EYE) - /* - * Map the first 1 MiB of memory in the TLB, and perform the data eye - * search. - */ - program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); - denali_core_search_data_eye(); - denali_sdram_register_dump(); - remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE); -#endif - -#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) - program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0); - sync(); - /* Zero the memory */ - debug("Zeroing SDRAM..."); -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE); -#else -#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file -#endif - /* Write modified dcache lines back to memory */ - clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE); - debug("Completed\n"); - sync(); - remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size); - -#if defined(CONFIG_DDR_ECC) - /* - * If ECC is enabled, clear and enable interrupts - */ - if (is_ecc_enabled()) { - u32 val; - - sync(); - /* Clear error status */ - mfsdram(DDR0_00, val); - mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); - /* Set 'int_mask' parameter to functionnal value */ - mfsdram(DDR0_01, val); - mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) | - DDR0_01_INT_MASK_ALL_OFF); -#if defined(CONFIG_DDR_DATA_EYE) - /* - * Running denali_core_search_data_eye() when ECC is enabled - * causes non-ECC machine checks. This clears them. - */ - print_mcsr(); - mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); - print_mcsr(); -#endif - sync(); - } -#endif /* defined(CONFIG_DDR_ECC) */ -#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ - - program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); - return dram_size; -} - -void board_add_ram_info(int use_default) -{ - u32 val; - - printf(" (ECC"); - if (!is_ecc_enabled()) { - printf(" not"); - } - printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000); - - mfsdram(DDR0_03, val); - printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1); -} -#endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c deleted file mode 100644 index 7976e75e0b..0000000000 --- a/cpu/ppc4xx/i2c.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * (C) Copyright 2007-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * based on work by Anne Sophie Harnois - * - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include <4xx_i2c.h> -#include -#include - -#ifdef CONFIG_HARD_I2C - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_I2C_MULTI_BUS) -/* - * Initialize the bus pointer to whatever one the SPD EEPROM is on. - * Default is bus 0. This is necessary because the DDR initialization - * runs from ROM, and we can't switch buses because we can't modify - * the global variables. - */ -#ifndef CONFIG_SYS_SPD_BUS_NUM -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = - CONFIG_SYS_SPD_BUS_NUM; -#endif /* CONFIG_I2C_MULTI_BUS */ - -static void _i2c_bus_reset(void) -{ - struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; - int i; - u8 dc; - - /* Reset status register */ - /* write 1 in SCMP and IRQA to clear these fields */ - out_8(&i2c->sts, 0x0A); - - /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ - out_8(&i2c->extsts, 0x8F); - - /* Place chip in the reset state */ - out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); - - /* Check if bus is free */ - dc = in_8(&i2c->directcntl); - if (!DIRCTNL_FREE(dc)){ - /* Try to set bus free state */ - out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC); - - /* Wait until we regain bus control */ - for (i = 0; i < 100; ++i) { - dc = in_8(&i2c->directcntl); - if (DIRCTNL_FREE(dc)) - break; - - /* Toggle SCL line */ - dc ^= IIC_DIRCNTL_SCC; - out_8(&i2c->directcntl, dc); - udelay(10); - dc ^= IIC_DIRCNTL_SCC; - out_8(&i2c->directcntl, dc); - } - } - - /* Remove reset */ - out_8(&i2c->xtcntlss, 0); -} - -void i2c_init(int speed, int slaveaddr) -{ - struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; - int val, divisor; - int bus; - -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* - * Call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - */ - i2c_init_board(); -#endif - - for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) { - I2C_SET_BUS(bus); - - /* Handle possible failed I2C state */ - /* FIXME: put this into i2c_init_board()? */ - _i2c_bus_reset(); - - /* clear lo master address */ - out_8(&i2c->lmadr, 0); - - /* clear hi master address */ - out_8(&i2c->hmadr, 0); - - /* clear lo slave address */ - out_8(&i2c->lsadr, 0); - - /* clear hi slave address */ - out_8(&i2c->hsadr, 0); - - /* Clock divide Register */ - /* set divisor according to freq_opb */ - divisor = (get_OPB_freq() - 1) / 10000000; - if (divisor == 0) - divisor = 1; - out_8(&i2c->clkdiv, divisor); - - /* no interrupts */ - out_8(&i2c->intrmsk, 0); - - /* clear transfer count */ - out_8(&i2c->xfrcnt, 0); - - /* clear extended control & stat */ - /* write 1 in SRC SRS SWC SWS to clear these fields */ - out_8(&i2c->xtcntlss, 0xF0); - - /* Mode Control Register - Flush Slave/Master data buffer */ - out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); - - val = in_8(&i2c->mdcntl); - - /* Ignore General Call, slave transfers are ignored, - * disable interrupts, exit unknown bus state, enable hold - * SCL 100kHz normaly or FastMode for 400kHz and above - */ - - val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL; - if (speed >= 400000) - val |= IIC_MDCNTL_FSM; - out_8(&i2c->mdcntl, val); - - /* clear control reg */ - out_8(&i2c->cntl, 0x00); - } - - /* set to SPD bus as default bus upon powerup */ - I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); -} - -/* - * This code tries to use the features of the 405GP i2c - * controller. It will transfer up to 4 bytes in one pass - * on the loop. It only does out_8((u8 *)lbz) to the buffer when it - * is possible to do out16(lhz) transfers. - * - * cmd_type is 0 for write 1 for read. - * - * addr_len can take any value from 0-255, it is only limited - * by the char, we could make it larger if needed. If it is - * 0 we skip the address write cycle. - * - * Typical case is a Write of an addr followd by a Read. The - * IBM FAQ does not cover this. On the last byte of the write - * we don't set the creg CHT bit, and on the first bytes of the - * read we set the RPST bit. - * - * It does not support address only transfers, there must be - * a data part. If you want to write the address yourself, put - * it in the data pointer. - * - * It does not support transfer to/from address 0. - * - * It does not check XFRCNT. - */ -static int i2c_transfer(unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], - unsigned short data_len) -{ - struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; - u8 *ptr; - int reading; - int tran, cnt; - int result; - int status; - int i; - u8 creg; - - if (data == 0 || data_len == 0) { - /* Don't support data transfer of no length or to address 0 */ - printf( "i2c_transfer: bad call\n" ); - return IIC_NOK; - } - if (addr && addr_len) { - ptr = addr; - cnt = addr_len; - reading = 0; - } else { - ptr = data; - cnt = data_len; - reading = cmd_type; - } - - /* Clear Stop Complete Bit */ - out_8(&i2c->sts, IIC_STS_SCMP); - - /* Check init */ - i = 10; - do { - /* Get status */ - status = in_8(&i2c->sts); - i--; - } while ((status & IIC_STS_PT) && (i > 0)); - - if (status & IIC_STS_PT) { - result = IIC_NOK_TOUT; - return(result); - } - - /* flush the Master/Slave Databuffers */ - out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) | - IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB); - - /* need to wait 4 OPB clocks? code below should take that long */ - - /* 7-bit adressing */ - out_8(&i2c->hmadr, 0); - out_8(&i2c->lmadr, chip); - - tran = 0; - result = IIC_OK; - creg = 0; - - while (tran != cnt && (result == IIC_OK)) { - int bc,j; - - /* - * Control register = - * Normal transfer, 7-bits adressing, Transfer up to - * bc bytes, Normal start, Transfer is a sequence of transfers - */ - creg |= IIC_CNTL_PT; - - bc = (cnt - tran) > 4 ? 4 : cnt - tran; - creg |= (bc - 1) << 4; - /* if the real cmd type is write continue trans */ - if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) - creg |= IIC_CNTL_CHT; - - if (reading) { - creg |= IIC_CNTL_READ; - } else { - for(j = 0; j < bc; j++) { - /* Set buffer */ - out_8(&i2c->mdbuf, ptr[tran + j]); - } - } - out_8(&i2c->cntl, creg); - - /* - * Transfer is in progress - * we have to wait for upto 5 bytes of data - * 1 byte chip address+r/w bit then bc bytes - * of data. - * udelay(10) is 1 bit time at 100khz - * Doubled for slop. 20 is too small. - */ - i = 2 * 5 * 8; - do { - /* Get status */ - status = in_8(&i2c->sts); - udelay(10); - i--; - } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && - (i > 0)); - - if (status & IIC_STS_ERR) { - result = IIC_NOK; - status = in_8(&i2c->extsts); - /* Lost arbitration? */ - if (status & IIC_EXTSTS_LA) - result = IIC_NOK_LA; - /* Incomplete transfer? */ - if (status & IIC_EXTSTS_ICT) - result = IIC_NOK_ICT; - /* Transfer aborted? */ - if (status & IIC_EXTSTS_XFRA) - result = IIC_NOK_XFRA; - } else if ( status & IIC_STS_PT) { - result = IIC_NOK_TOUT; - } - - /* Command is reading => get buffer */ - if ((reading) && (result == IIC_OK)) { - /* Are there data in buffer */ - if (status & IIC_STS_MDBS) { - /* - * even if we have data we have to wait 4OPB - * clocks for it to hit the front of the FIFO, - * after that we can just read. We should check - * XFCNT here and if the FIFO is full there is - * no need to wait. - */ - udelay(1); - for (j = 0; j < bc; j++) - ptr[tran + j] = in_8(&i2c->mdbuf); - } else - result = IIC_NOK_DATA; - } - creg = 0; - tran += bc; - if (ptr == addr && tran == cnt) { - ptr = data; - cnt = data_len; - tran = 0; - reading = cmd_type; - if (reading) - creg = IIC_CNTL_RPST; - } - } - return result; -} - -int i2c_probe(uchar chip) -{ - uchar buf[1]; - - buf[0] = 0; - - /* - * What is needed is to send the chip address and verify that the - * address was ed (i.e. there was a chip at that address which - * drove the data line low). - */ - return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0); -} - -static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, - int len, int read) -{ - uchar xaddr[4]; - int ret; - - if (alen > 4) { - printf("I2C: addr len %d not supported\n", alen); - return 1; - } - - if (alen > 0) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } - - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if (alen > 0) - chip |= ((addr >> (alen * 8)) & - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen, - buffer, len)) != 0) { - if (gd->have_console) { - printf("I2C %s: failed %d\n", - read ? "read" : "write", ret); - } - - return 1; - } - - return 0; -} - -int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1); -} - -int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0); -} - -#if defined(CONFIG_I2C_MULTI_BUS) -/* - * Functions for multiple I2C bus handling - */ -unsigned int i2c_get_bus_num(void) -{ - return i2c_bus_num; -} - -int i2c_set_bus_num(unsigned int bus) -{ - if (bus >= CONFIG_SYS_MAX_I2C_BUS) - return -1; - - i2c_bus_num = bus; - - return 0; -} -#endif /* CONFIG_I2C_MULTI_BUS */ -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S deleted file mode 100644 index 927c88c78f..0000000000 --- a/cpu/ppc4xx/start.S +++ /dev/null @@ -1,2170 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000,2001,2002 Wolfgang Denk - * Copyright (C) 2007 Stefan Roese , DENX Software Engineering - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/*------------------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *------------------------------------------------------------------------------- - */ - -/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards - * - * - * The processor starts at 0xfffffffc and the code is executed - * from flash/rom. - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memorymap. - * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 - */ -#include -#include -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -#ifdef CONFIG_SYS_INIT_DCACHE_CS -# if (CONFIG_SYS_INIT_DCACHE_CS == 0) -# define PBxAP PB1AP -# define PBxCR PB0CR -# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) -# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP -# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR -# endif -# endif -# if (CONFIG_SYS_INIT_DCACHE_CS == 1) -# define PBxAP PB1AP -# define PBxCR PB1CR -# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) -# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP -# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR -# endif -# endif -# if (CONFIG_SYS_INIT_DCACHE_CS == 2) -# define PBxAP PB2AP -# define PBxCR PB2CR -# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) -# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP -# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR -# endif -# endif -# if (CONFIG_SYS_INIT_DCACHE_CS == 3) -# define PBxAP PB3AP -# define PBxCR PB3CR -# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) -# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP -# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR -# endif -# endif -# if (CONFIG_SYS_INIT_DCACHE_CS == 4) -# define PBxAP PB4AP -# define PBxCR PB4CR -# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) -# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP -# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR -# endif -# endif -# if (CONFIG_SYS_INIT_DCACHE_CS == 5) -# define PBxAP PB5AP -# define PBxCR PB5CR -# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) -# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP -# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR -# endif -# endif -# if (CONFIG_SYS_INIT_DCACHE_CS == 6) -# define PBxAP PB6AP -# define PBxCR PB6CR -# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) -# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP -# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR -# endif -# endif -# if (CONFIG_SYS_INIT_DCACHE_CS == 7) -# define PBxAP PB7AP -# define PBxCR PB7CR -# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) -# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP -# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR -# endif -# endif -# ifndef PBxAP_VAL -# define PBxAP_VAL 0 -# endif -# ifndef PBxCR_VAL -# define PBxCR_VAL 0 -# endif -/* - * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB - * used as temporary stack pointer for the primordial stack - */ -# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR -# define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | \ - EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(2) | \ - EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_NONDELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED) -# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ -# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR -# define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ - EBC_BXCR_BS_64MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_16BIT) -# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ -# ifndef CONFIG_SYS_INIT_RAM_PATTERN -# define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD -# endif -#endif /* CONFIG_SYS_INIT_DCACHE_CS */ - -#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10))) -#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END! -#endif - -/* - * Unless otherwise overriden, enable two 128MB cachable instruction regions - * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering - * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. - */ -#if !defined(CONFIG_SYS_FLASH_BASE) -/* If not already defined, set it to the "last" 128MByte region */ -# define CONFIG_SYS_FLASH_BASE 0xf8000000 -#endif -#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) -# define CONFIG_SYS_ICACHE_SACR_VALUE \ - (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ - PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ - PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) -#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ - -#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) -# define CONFIG_SYS_DCACHE_SACR_VALUE \ - (0x00000000) -#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ - -#define function_prolog(func_name) .text; \ - .align 2; \ - .globl func_name; \ - func_name: -#define function_epilog(func_name) .type func_name,@function; \ - .size func_name,.-func_name - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ - - - .extern ext_bus_cntlr_init -#ifdef CONFIG_NAND_U_BOOT - .extern reconfig_tlb0 -#endif - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ -#if !defined(CONFIG_NAND_SPL) - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT -#endif /* CONFIG_NAND_SPL */ - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * NAND U-Boot image is started from offset 0 - */ - .text -#if defined(CONFIG_440) - bl reconfig_tlb0 -#endif - GET_GOT - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - bl board_init_f -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - /* - * 4xx RAM-booting U-Boot image is started from offset 0 - */ - .text - bl _start_440 -#endif - -/* - * 440 Startup -- on reset only the top 4k of the effective - * address space is mapped in by an entry in the instruction - * and data shadow TLB. The .bootpg section is located in the - * top 4k & does only what's necessary to map in the the rest - * of the boot rom. Once the boot rom is mapped in we can - * proceed with normal startup. - * - * NOTE: CS0 only covers the top 2MB of the effective address - * space after reset. - */ - -#if defined(CONFIG_440) -#if !defined(CONFIG_NAND_SPL) - .section .bootpg,"ax" -#endif - .globl _start_440 - -/**************************************************************************/ -_start_440: - /*--------------------------------------------------------------------+ - | 440EPX BUP Change - Hardware team request - +--------------------------------------------------------------------*/ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - sync - nop - nop -#endif - /*----------------------------------------------------------------+ - | Core bug fix. Clear the esr - +-----------------------------------------------------------------*/ - li r0,0 - mtspr SPRN_ESR,r0 - /*----------------------------------------------------------------*/ - /* Clear and set up some registers. */ - /*----------------------------------------------------------------*/ - iccci r0,r0 /* NOTE: operands not used for 440 */ - dccci r0,r0 /* NOTE: operands not used for 440 */ - sync - li r0,0 - mtspr SPRN_SRR0,r0 - mtspr SPRN_SRR1,r0 - mtspr SPRN_CSRR0,r0 - mtspr SPRN_CSRR1,r0 - /* NOTE: 440GX adds machine check status regs */ -#if defined(CONFIG_440) && !defined(CONFIG_440GP) - mtspr SPRN_MCSRR0,r0 - mtspr SPRN_MCSRR1,r0 - mfspr r1,SPRN_MCSR - mtspr SPRN_MCSR,r1 -#endif - - /*----------------------------------------------------------------*/ - /* CCR0 init */ - /*----------------------------------------------------------------*/ - /* Disable store gathering & broadcast, guarantee inst/data - * cache block touch, force load/store alignment - * (see errata 1.12: 440_33) - */ - lis r1,0x0030 /* store gathering & broadcast disable */ - ori r1,r1,0x6000 /* cache touch */ - mtspr SPRN_CCR0,r1 - - /*----------------------------------------------------------------*/ - /* Initialize debug */ - /*----------------------------------------------------------------*/ - mfspr r1,SPRN_DBCR0 - andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ - bne skip_debug_init /* if set, don't clear debug register */ - mtspr SPRN_DBCR0,r0 - mtspr SPRN_DBCR1,r0 - mtspr SPRN_DBCR2,r0 - mtspr SPRN_IAC1,r0 - mtspr SPRN_IAC2,r0 - mtspr SPRN_IAC3,r0 - mtspr SPRN_DAC1,r0 - mtspr SPRN_DAC2,r0 - mtspr SPRN_DVC1,r0 - mtspr SPRN_DVC2,r0 - - mfspr r1,SPRN_DBSR - mtspr SPRN_DBSR,r1 /* Clear all valid bits */ -skip_debug_init: - -#if defined (CONFIG_440SPE) - /*----------------------------------------------------------------+ - | Initialize Core Configuration Reg1. - | a. ICDPEI: Record even parity. Normal operation. - | b. ICTPEI: Record even parity. Normal operation. - | c. DCTPEI: Record even parity. Normal operation. - | d. DCDPEI: Record even parity. Normal operation. - | e. DCUPEI: Record even parity. Normal operation. - | f. DCMPEI: Record even parity. Normal operation. - | g. FCOM: Normal operation - | h. MMUPEI: Record even parity. Normal operation. - | i. FFF: Flush only as much data as necessary. - | j. TCS: Timebase increments from CPU clock. - +-----------------------------------------------------------------*/ - li r0,0 - mtspr SPRN_CCR1, r0 - - /*----------------------------------------------------------------+ - | Reset the timebase. - | The previous write to CCR1 sets the timebase source. - +-----------------------------------------------------------------*/ - mtspr SPRN_TBWL, r0 - mtspr SPRN_TBWU, r0 -#endif - - /*----------------------------------------------------------------*/ - /* Setup interrupt vectors */ - /*----------------------------------------------------------------*/ - mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ - li r1,0x0100 - mtspr SPRN_IVOR0,r1 /* Critical input */ - li r1,0x0200 - mtspr SPRN_IVOR1,r1 /* Machine check */ - li r1,0x0300 - mtspr SPRN_IVOR2,r1 /* Data storage */ - li r1,0x0400 - mtspr SPRN_IVOR3,r1 /* Instruction storage */ - li r1,0x0500 - mtspr SPRN_IVOR4,r1 /* External interrupt */ - li r1,0x0600 - mtspr SPRN_IVOR5,r1 /* Alignment */ - li r1,0x0700 - mtspr SPRN_IVOR6,r1 /* Program check */ - li r1,0x0800 - mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ - li r1,0x0c00 - mtspr SPRN_IVOR8,r1 /* System call */ - li r1,0x0a00 - mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ - li r1,0x0900 - mtspr SPRN_IVOR10,r1 /* Decrementer */ - li r1,0x1300 - mtspr SPRN_IVOR13,r1 /* Data TLB error */ - li r1,0x1400 - mtspr SPRN_IVOR14,r1 /* Instr TLB error */ - li r1,0x2000 - mtspr SPRN_IVOR15,r1 /* Debug */ - - /*----------------------------------------------------------------*/ - /* Configure cache regions */ - /*----------------------------------------------------------------*/ - mtspr SPRN_INV0,r0 - mtspr SPRN_INV1,r0 - mtspr SPRN_INV2,r0 - mtspr SPRN_INV3,r0 - mtspr SPRN_DNV0,r0 - mtspr SPRN_DNV1,r0 - mtspr SPRN_DNV2,r0 - mtspr SPRN_DNV3,r0 - mtspr SPRN_ITV0,r0 - mtspr SPRN_ITV1,r0 - mtspr SPRN_ITV2,r0 - mtspr SPRN_ITV3,r0 - mtspr SPRN_DTV0,r0 - mtspr SPRN_DTV1,r0 - mtspr SPRN_DTV2,r0 - mtspr SPRN_DTV3,r0 - - /*----------------------------------------------------------------*/ - /* Cache victim limits */ - /*----------------------------------------------------------------*/ - /* floors 0, ceiling max to use the entire cache -- nothing locked - */ - lis r1,0x0001 - ori r1,r1,0xf800 - mtspr SPRN_IVLIM,r1 - mtspr SPRN_DVLIM,r1 - - /*----------------------------------------------------------------+ - |Initialize MMUCR[STID] = 0. - +-----------------------------------------------------------------*/ - mfspr r0,SPRN_MMUCR - addis r1,0,0xFFFF - ori r1,r1,0xFF00 - and r0,r0,r1 - mtspr SPRN_MMUCR,r0 - - /*----------------------------------------------------------------*/ - /* Clear all TLB entries -- TID = 0, TS = 0 */ - /*----------------------------------------------------------------*/ - addis r0,0,0x0000 -#ifdef CONFIG_SYS_RAMBOOT - li r4,0 /* Start with TLB #0 */ -#else - li r4,1 /* Start with TLB #1 */ -#endif - li r1,64 /* 64 TLB entries */ - sub r1,r1,r4 /* calculate last TLB # */ - mtctr r1 -rsttlb: -#ifdef CONFIG_SYS_RAMBOOT - tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ - rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */ - beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */ -#endif - tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/ - tlbwe r0,r4,1 - tlbwe r0,r4,2 -tlbnxt: addi r4,r4,1 /* Next TLB */ - bdnz rsttlb - - /*----------------------------------------------------------------*/ - /* TLB entry setup -- step thru tlbtab */ - /*----------------------------------------------------------------*/ -#if defined(CONFIG_440SPE) - /*----------------------------------------------------------------*/ - /* We have different TLB tables for revA and rev B of 440SPe */ - /*----------------------------------------------------------------*/ - mfspr r1, PVR - lis r0,0x5342 - ori r0,r0,0x1891 - cmpw r7,r1,r0 - bne r7,..revA - bl tlbtabB - b ..goon -..revA: - bl tlbtabA -..goon: -#else - bl tlbtab /* Get tlbtab pointer */ -#endif - mr r5,r0 - li r1,0x003f /* 64 TLB entries max */ - mtctr r1 - li r4,0 /* TLB # */ - - addi r5,r5,-4 -1: -#ifdef CONFIG_SYS_RAMBOOT - tlbre r3,r4,0 /* Read contents from TLB word #0 */ - rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */ - bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */ -#endif - lwzu r0,4(r5) - cmpwi r0,0 - beq 2f /* 0 marks end */ - lwzu r1,4(r5) - lwzu r2,4(r5) - tlbwe r0,r4,0 /* TLB Word 0 */ - tlbwe r1,r4,1 /* TLB Word 1 */ - tlbwe r2,r4,2 /* TLB Word 2 */ -tlbnx2: addi r4,r4,1 /* Next TLB */ - bdnz 1b - - /*----------------------------------------------------------------*/ - /* Continue from 'normal' start */ - /*----------------------------------------------------------------*/ -2: - bl 3f - b _start - -3: li r0,0 - mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr SPRN_SRR0,r1 - rfi -#endif /* CONFIG_440 */ - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ -#ifndef CONFIG_NAND_SPL - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start_of_vectors -_start_of_vectors: - -/* Critical input. */ - CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) - -#ifdef CONFIG_440 -/* Machine check */ - MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) -#else - CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) -#endif /* CONFIG_440 */ - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - -#ifdef CONFIG_440 - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) - STD_EXCEPTION(0xa00, APU, UnknownException) -#endif - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - -#ifdef CONFIG_440 - STD_EXCEPTION(0x1300, DataTLBError, UnknownException) - STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) -#else - STD_EXCEPTION(0x1000, PIT, DecrementerPITException) - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) -#endif - CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) - - .globl _end_of_vectors -_end_of_vectors: - . = _START_OFFSET -#endif - .globl _start -_start: - -/*****************************************************************************/ -#if defined(CONFIG_440) - - /*----------------------------------------------------------------*/ - /* Clear and set up some registers. */ - /*----------------------------------------------------------------*/ - li r0,0x0000 - lis r1,0xffff - mtspr SPRN_DEC,r0 /* prevent dec exceptions */ - mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ - mtspr SPRN_TBWU,r0 - mtspr SPRN_TSR,r1 /* clear all timer exception status */ - mtspr SPRN_TCR,r0 /* disable all */ - mtspr SPRN_ESR,r0 /* clear exception syndrome register */ - mtxer r0 /* clear integer exception register */ - - /*----------------------------------------------------------------*/ - /* Debug setup -- some (not very good) ice's need an event*/ - /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ - /* value you need in this case 0x8cff 0000 should do the trick */ - /*----------------------------------------------------------------*/ -#if defined(CONFIG_SYS_INIT_DBCR) - lis r1,0xffff - ori r1,r1,0xffff - mtspr SPRN_DBSR,r1 /* Clear all status bits */ - lis r0,CONFIG_SYS_INIT_DBCR@h - ori r0,r0,CONFIG_SYS_INIT_DBCR@l - mtspr SPRN_DBCR0,r0 - isync -#endif - - /*----------------------------------------------------------------*/ - /* Setup the internal SRAM */ - /*----------------------------------------------------------------*/ - li r0,0 - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* Clear Dcache to use as RAM */ - addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l - addis r4,r0,CONFIG_SYS_INIT_RAM_END@h - ori r4,r4,CONFIG_SYS_INIT_RAM_END@l - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ran - addi r5,r5,0x0001 -..d_ran: - mtctr r5 -..d_ag: - dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag - - /* - * Lock the init-ram/stack in d-cache, so that other regions - * may use d-cache as well - * Note, that this current implementation locks exactly 4k - * of d-cache, so please make sure that you don't define a - * bigger init-ram area. Take a look at the lwmon5 440EPx - * implementation as a reference. - */ - msync - isync - /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ - lis r1,0x0201 - ori r1,r1,0xf808 - mtspr SPRN_DVLIM,r1 - lis r1,0x0808 - ori r1,r1,0x0808 - mtspr SPRN_DNV0,r1 - mtspr SPRN_DNV1,r1 - mtspr SPRN_DNV2,r1 - mtspr SPRN_DNV3,r1 - mtspr SPRN_DTV0,r1 - mtspr SPRN_DTV1,r1 - mtspr SPRN_DTV2,r1 - mtspr SPRN_DTV3,r1 - msync - isync -#endif /* CONFIG_SYS_INIT_RAM_DCACHE */ - - /* 440EP & 440GR are only 440er PPC's without internal SRAM */ -#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) - /* not all PPC's have internal SRAM usable as L2-cache */ -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460SX) - mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - lis r1, 0x0000 - ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ - mtdcr L2_CACHE_CFG,r1 -#endif - - lis r2,0x7fff - ori r2,r2,0xffff - mfdcr r1,ISRAM0_DPC - and r1,r1,r2 /* Disable parity check */ - mtdcr ISRAM0_DPC,r1 - mfdcr r1,ISRAM0_PMEG - and r1,r1,r2 /* Disable pwr mgmt */ - mtdcr ISRAM0_PMEG,r1 - - lis r1,0x8000 /* BAS = 8000_0000 */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) - ori r1,r1,0x0980 /* first 64k */ - mtdcr ISRAM0_SB0CR,r1 - lis r1,0x8001 - ori r1,r1,0x0980 /* second 64k */ - mtdcr ISRAM0_SB1CR,r1 - lis r1, 0x8002 - ori r1,r1, 0x0980 /* third 64k */ - mtdcr ISRAM0_SB2CR,r1 - lis r1, 0x8003 - ori r1,r1, 0x0980 /* fourth 64k */ - mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) - lis r1,0x0000 /* BAS = X_0000_0000 */ - ori r1,r1,0x0984 /* first 64k */ - mtdcr ISRAM0_SB0CR,r1 - lis r1,0x0001 - ori r1,r1,0x0984 /* second 64k */ - mtdcr ISRAM0_SB1CR,r1 - lis r1, 0x0002 - ori r1,r1, 0x0984 /* third 64k */ - mtdcr ISRAM0_SB2CR,r1 - lis r1, 0x0003 - ori r1,r1, 0x0984 /* fourth 64k */ - mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - lis r2,0x7fff - ori r2,r2,0xffff - mfdcr r1,ISRAM1_DPC - and r1,r1,r2 /* Disable parity check */ - mtdcr ISRAM1_DPC,r1 - mfdcr r1,ISRAM1_PMEG - and r1,r1,r2 /* Disable pwr mgmt */ - mtdcr ISRAM1_PMEG,r1 - - lis r1,0x0004 /* BAS = 4_0004_0000 */ - ori r1,r1,0x0984 /* 64k */ - mtdcr ISRAM1_SB0CR,r1 -#endif -#elif defined(CONFIG_460SX) - lis r1,0x0000 /* BAS = 0000_0000 */ - ori r1,r1,0x0B84 /* first 128k */ - mtdcr ISRAM0_SB0CR,r1 - lis r1,0x0001 - ori r1,r1,0x0B84 /* second 128k */ - mtdcr ISRAM0_SB1CR,r1 - lis r1, 0x0002 - ori r1,r1, 0x0B84 /* third 128k */ - mtdcr ISRAM0_SB2CR,r1 - lis r1, 0x0003 - ori r1,r1, 0x0B84 /* fourth 128k */ - mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440GP) - ori r1,r1,0x0380 /* 8k rw */ - mtdcr ISRAM0_SB0CR,r1 - mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ -#endif -#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ - - /*----------------------------------------------------------------*/ - /* Setup the stack in internal SRAM */ - /*----------------------------------------------------------------*/ - lis r1,CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l - li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0, RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ - -#ifdef CONFIG_NAND_SPL - bl nand_boot_common /* will not return */ -#else - GET_GOT - - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - bl board_init_f -#endif - -#endif /* CONFIG_440 */ - -/*****************************************************************************/ -#ifdef CONFIG_IOP480 - /*----------------------------------------------------------------------- */ - /* Set up some machine state registers. */ - /*----------------------------------------------------------------------- */ - addi r0,r0,0x0000 /* initialize r0 to zero */ - mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ - mttcr r0 /* timer control register */ - mtexier r0 /* disable all interrupts */ - addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ - ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ - mtdbsr r4 /* clear/reset the dbsr */ - mtexisr r4 /* clear all pending interrupts */ - addis r4,r0,0x8000 - mtexier r4 /* enable critical exceptions */ - addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ - ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ - mtiocr r4 /* since bit not used) & DRC to latch */ - /* data bus on rising edge of CAS */ - /*----------------------------------------------------------------------- */ - /* Clear XER. */ - /*----------------------------------------------------------------------- */ - mtxer r0 - /*----------------------------------------------------------------------- */ - /* Invalidate i-cache and d-cache TAG arrays. */ - /*----------------------------------------------------------------------- */ - addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ - addi r4,0,1024 /* 1/4 of I-cache */ -..cloop: - iccci 0,r3 - iccci r4,r3 - dccci 0,r3 - addic. r3,r3,-16 /* move back one cache line */ - bne ..cloop /* loop back to do rest until r3 = 0 */ - - /* */ - /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ - /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ - /* */ - - /* first copy IOP480 register base address into r3 */ - addis r3,0,0x5000 /* IOP480 register base address hi */ -/* ori r3,r3,0x0000 / IOP480 register base address lo */ - -#ifdef CONFIG_ADCIOP - /* use r4 as the working variable */ - /* turn on CS3 (LOCCTL.7) */ - lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ - andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ - stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ -#endif - -#ifdef CONFIG_DASA_SIM - /* use r4 as the working variable */ - /* turn on MA17 (LOCCTL.7) */ - lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ - ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ - stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ -#endif - - /* turn on MA16..13 (LCS0BRD.12 = 0) */ - lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ - andi. r4,r4,0xefff /* make bit 12 = 0 */ - stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ - - /* make sure above stores all comlete before going on */ - sync - - /* last thing, set local init status done bit (DEVINIT.31) */ - lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ - oris r4,r4,0x8000 /* make bit 31 = 1 */ - stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ - - /* clear all pending interrupts and disable all interrupts */ - li r4,-1 /* set p1 to 0xffffffff */ - stw r4,0x1b0(r3) /* clear all pending interrupts */ - stw r4,0x1b8(r3) /* clear all pending interrupts */ - li r4,0 /* set r4 to 0 */ - stw r4,0x1b4(r3) /* disable all interrupts */ - stw r4,0x1bc(r3) /* disable all interrupts */ - - /* make sure above stores all comlete before going on */ - sync - - /* Set-up icache cacheability. */ - lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h - ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l - mticcr r1 - isync - - /* Set-up dcache cacheability. */ - lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h - ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l - mtdccr r1 - - addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - GET_GOT /* initialize GOT access */ - - bl board_init_f /* run first part of init code (from Flash) */ - -#endif /* CONFIG_IOP480 */ - -/*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || defined(CONFIG_405) - /*----------------------------------------------------------------------- */ - /* Clear and set up some registers. */ - /*----------------------------------------------------------------------- */ - addi r4,r0,0x0000 -#if !defined(CONFIG_405EX) - mtspr SPRN_SGR,r4 -#else - /* - * On 405EX, completely clearing the SGR leads to PPC hangup - * upon PCIe configuration access. The PCIe memory regions - * need to be guarded! - */ - lis r3,0x0000 - ori r3,r3,0x7FFC - mtspr SPRN_SGR,r3 -#endif - mtspr SPRN_DCWR,r4 - mtesr r4 /* clear Exception Syndrome Reg */ - mttcr r4 /* clear Timer Control Reg */ - mtxer r4 /* clear Fixed-Point Exception Reg */ - mtevpr r4 /* clear Exception Vector Prefix Reg */ - addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ - /* dbsr is cleared by setting bits to 1) */ - mtdbsr r4 /* clear/reset the dbsr */ - - /* Invalidate the i- and d-caches. */ - bl invalidate_icache - bl invalidate_dcache - - /* Set-up icache cacheability. */ - lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h - ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l - mticcr r4 - isync - - /* Set-up dcache cacheability. */ - lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h - ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l - mtdccr r4 - -#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ - && !defined (CONFIG_XILINX_405) - /*----------------------------------------------------------------------- */ - /* Tune the speed and size for flash CS0 */ - /*----------------------------------------------------------------------- */ - bl ext_bus_cntlr_init -#endif - -#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) - /* - * For boards that don't have OCM and can't use the data cache - * for their primordial stack, setup stack here directly after the - * SDRAM is initialized in ext_bus_cntlr_init. - */ - lis r1, CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - lis r0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ - -#if defined(CONFIG_405EP) - /*----------------------------------------------------------------------- */ - /* DMA Status, clear to come up clean */ - /*----------------------------------------------------------------------- */ - addis r3,r0, 0xFFFF /* Clear all existing DMA status */ - ori r3,r3, 0xFFFF - mtdcr DMASR, r3 - - bl ppc405ep_init /* do ppc405ep specific init */ -#endif /* CONFIG_405EP */ - -#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) -#if defined(CONFIG_405EZ) - /******************************************************************** - * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 - *******************************************************************/ - /* - * We can map the OCM on the PLB3, so map it at - * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 - */ - lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l - ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ - ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ - isync - - lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l - ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr OCM0_DSRC1, r3 /* Set Data Side */ - mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ - ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr OCM0_DSRC2, r3 /* Set Data Side */ - mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ - addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ - mtdcr OCM0_DISDPC,r3 - - isync -#else /* CONFIG_405EZ */ - /******************************************************************** - * Setup OCM - On Chip Memory - *******************************************************************/ - /* Setup OCM */ - lis r0, 0x7FFF - ori r0, r0, 0xFFFF - mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ - mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ - and r3, r3, r0 /* disable data-side IRAM */ - and r4, r4, r0 /* disable data-side IRAM */ - mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ - mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ - isync - - lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l - mtdcr OCM0_DSARC, r3 - addis r4, 0, 0xC000 /* OCM data area enabled */ - mtdcr OCM0_DSCNTL, r4 - isync -#endif /* CONFIG_405EZ */ -#endif - - /*----------------------------------------------------------------------- */ - /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ - /*----------------------------------------------------------------------- */ -#ifdef CONFIG_SYS_INIT_DCACHE_CS - li r4, PBxAP - mtdcr EBC0_CFGADDR, r4 - lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h - ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l - mtdcr EBC0_CFGDATA, r4 - - addi r4, 0, PBxCR - mtdcr EBC0_CFGADDR, r4 - lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h - ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l - mtdcr EBC0_CFGDATA, r4 - - /* - * Enable the data cache for the 128MB storage access control region - * at CONFIG_SYS_INIT_RAM_ADDR. - */ - mfdccr r4 - oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l - mtdccr r4 - - /* - * Preallocate data cache lines to be used to avoid a subsequent - * cache miss and an ensuing machine check exception when exceptions - * are enabled. - */ - li r0, 0 - - lis r3, CONFIG_SYS_INIT_RAM_ADDR@h - ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l - - lis r4, CONFIG_SYS_INIT_RAM_END@h - ori r4, r4, CONFIG_SYS_INIT_RAM_END@l - - /* - * Convert the size, in bytes, to the number of cache lines/blocks - * to preallocate. - */ - clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) - srwi r5, r4, L1_CACHE_SHIFT - beq ..load_counter - addi r5, r5, 0x0001 -..load_counter: - mtctr r5 - - /* Preallocate the computed number of cache blocks. */ -..alloc_dcache_block: - dcba r0, r3 - addi r3, r3, L1_CACHE_BYTES - bdnz ..alloc_dcache_block - sync - - /* - * Load the initial stack pointer and data area and convert the size, - * in bytes, to the number of words to initialize to a known value. - */ - lis r1, CONFIG_SYS_INIT_RAM_ADDR@h - ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l - - lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h - ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l - mtctr r4 - - lis r2, CONFIG_SYS_INIT_RAM_ADDR@h - ori r2, r2, CONFIG_SYS_INIT_RAM_END@l - - lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h - ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l - -..stackloop: - stwu r4, -4(r2) - bdnz ..stackloop - - /* - * Make room for stack frame header and clear final stack frame so - * that stack backtraces terminate cleanly. - */ - stwu r0, -4(r1) - stwu r0, -4(r1) - - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ - -#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ - (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) - /* - * Stack in OCM. - */ - - /* Set up Stack at top of OCM */ - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l - - /* Set up a zeroized stack frame so that backtrace works right */ - li r0, 0 - stwu r0, -4(r1) - stwu r0, -4(r1) - - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - lis r0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* CONFIG_SYS_INIT_DCACHE_CS */ - -#ifdef CONFIG_NAND_SPL - bl nand_boot_common /* will not return */ -#else - GET_GOT /* initialize GOT access */ - - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - /* NEVER RETURNS! */ - bl board_init_f /* run first part of init code (from Flash) */ -#endif /* CONFIG_NAND_SPL */ - -#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ - /*----------------------------------------------------------------------- */ - - -#ifndef CONFIG_NAND_SPL -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -crit_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SPRN_CSRR0,r2 - mtspr SPRN_CSRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfci - -#ifdef CONFIG_440 -mck_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SPRN_MCSRR0,r2 - mtspr SPRN_MCSRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfmci -#endif /* CONFIG_440 */ - - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,r0,r3 - blr - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = Relocated stack pointer - * r4 = Relocated global data pointer - * r5 = Relocated text pointer - */ - .globl relocate_code -relocate_code: -#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) - /* - * We need to flush the initial global data (gd_t) before the dcache - * will be invalidated. - */ - - /* Save registers */ - mr r9, r3 - mr r10, r4 - mr r11, r5 - - /* Flush initial global data range */ - mr r3, r4 - addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l - bl flush_dcache_range - -#if defined(CONFIG_SYS_INIT_DCACHE_CS) - /* - * Undo the earlier data cache set-up for the primordial stack and - * data area. First, invalidate the data cache and then disable data - * cacheability for that area. Finally, restore the EBC values, if - * any. - */ - - /* Invalidate the primordial stack and data area in cache */ - lis r3, CONFIG_SYS_INIT_RAM_ADDR@h - ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l - - lis r4, CONFIG_SYS_INIT_RAM_END@h - ori r4, r4, CONFIG_SYS_INIT_RAM_END@l - add r4, r4, r3 - - bl invalidate_dcache_range - - /* Disable cacheability for the region */ - mfdccr r3 - lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l - and r3, r3, r4 - mtdccr r3 - - /* Restore the EBC parameters */ - li r3, PBxAP - mtdcr EBC0_CFGADDR, r3 - lis r3, PBxAP_VAL@h - ori r3, r3, PBxAP_VAL@l - mtdcr EBC0_CFGDATA, r3 - - li r3, PBxCR - mtdcr EBC0_CFGADDR, r3 - lis r3, PBxCR_VAL@h - ori r3, r3, PBxCR_VAL@l - mtdcr EBC0_CFGDATA, r3 -#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ - - /* Restore registers */ - mr r3, r9 - mr r4, r10 - mr r5, r11 -#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* - * Unlock the previously locked d-cache - */ - msync - isync - /* set TFLOOR/NFLOOR to 0 again */ - lis r6,0x0001 - ori r6,r6,0xf800 - mtspr SPRN_DVLIM,r6 - lis r6,0x0000 - ori r6,r6,0x0000 - mtspr SPRN_DNV0,r6 - mtspr SPRN_DNV1,r6 - mtspr SPRN_DNV2,r6 - mtspr SPRN_DNV3,r6 - mtspr SPRN_DTV0,r6 - mtspr SPRN_DTV1,r6 - mtspr SPRN_DTV2,r6 - mtspr SPRN_DTV3,r6 - msync - isync -#endif /* CONFIG_SYS_INIT_RAM_DCACHE */ - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) - /* - * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) - * to speed up the boot process. Now this cache needs to be disabled. - */ - iccci 0,0 /* Invalidate inst cache */ - dccci 0,0 /* Invalidate data cache, now no longer our stack */ - sync - isync - - /* Clear all potential pending exceptions */ - mfspr r1,SPRN_MCSR - mtspr SPRN_MCSR,r1 -#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH - addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ -#else - addi r1,r0,0x0000 /* Default TLB entry is #0 */ -#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */ - tlbre r0,r1,0x0002 /* Read contents */ - ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ - tlbwe r0,r1,0x0002 /* Save it out */ - sync - isync -#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Init Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, L1_CACHE_BYTES /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + _START_OFFSET - mtlr r0 - blr /* NEVER RETURNS! */ - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 7f - - li r0, 0 - - andi. r5, r4, 3 - beq 6f - sub r4, r4, r5 - mtctr r5 - mr r5, r4 -5: stb r0, 0(r5) - addi r5, r5, 1 - bdnz 5b -6: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 6b - -7: - mr r3, r9 /* Init Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start_of_vectors) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + _START_OFFSET - li r8, Alignment - _start + _START_OFFSET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + _START_OFFSET - bl trap_reloc - -#ifdef CONFIG_440 - li r7, .L_FPUnavailable - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_Decrementer - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_APU - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_InstructionTLBError - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_DataTLBError - _start + _START_OFFSET - bl trap_reloc -#else /* CONFIG_440 */ - li r7, .L_PIT - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_InstructionTLBMiss - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_DataTLBMiss - _start + _START_OFFSET - bl trap_reloc -#endif /* CONFIG_440 */ - - li r7, .L_DebugBreakpoint - _start + _START_OFFSET - bl trap_reloc - -#if !defined(CONFIG_440) - addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ - oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ - mtmsr r7 /* change MSR */ -#else - bl __440_msr_set - b __440_msr_continue - -__440_msr_set: - addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ - oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ - mtspr SPRN_SRR1,r7 - mflr r7 - mtspr SPRN_SRR0,r7 - rfi -__440_msr_continue: -#endif - - mtlr r4 /* restore link register */ - blr - -#if defined(CONFIG_440) -/*----------------------------------------------------------------------------+ -| dcbz_area. -+----------------------------------------------------------------------------*/ - function_prolog(dcbz_area) - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 -..d_ra2:mtctr r5 -..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 - sync - blr - function_epilog(dcbz_area) -#endif /* CONFIG_440 */ -#endif /* CONFIG_NAND_SPL */ - -/*------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0x0000(3) - blr - -/**************************************************************************/ -/* PPC405EP specific stuff */ -/**************************************************************************/ -#ifdef CONFIG_405EP -ppc405ep_init: - -#ifdef CONFIG_BUBINGA - /* - * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate - * function) to support FPGA and NVRAM accesses below. - */ - - lis r3,GPIO0_OSRH@h /* config GPIO output select */ - ori r3,r3,GPIO0_OSRH@l - lis r4,CONFIG_SYS_GPIO0_OSRH@h - ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l - stw r4,0(r3) - lis r3,GPIO0_OSRL@h - ori r3,r3,GPIO0_OSRL@l - lis r4,CONFIG_SYS_GPIO0_OSRL@h - ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l - stw r4,0(r3) - - lis r3,GPIO0_ISR1H@h /* config GPIO input select */ - ori r3,r3,GPIO0_ISR1H@l - lis r4,CONFIG_SYS_GPIO0_ISR1H@h - ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l - stw r4,0(r3) - lis r3,GPIO0_ISR1L@h - ori r3,r3,GPIO0_ISR1L@l - lis r4,CONFIG_SYS_GPIO0_ISR1L@h - ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l - stw r4,0(r3) - - lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ - ori r3,r3,GPIO0_TSRH@l - lis r4,CONFIG_SYS_GPIO0_TSRH@h - ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l - stw r4,0(r3) - lis r3,GPIO0_TSRL@h - ori r3,r3,GPIO0_TSRL@l - lis r4,CONFIG_SYS_GPIO0_TSRL@h - ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l - stw r4,0(r3) - - lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ - ori r3,r3,GPIO0_TCR@l - lis r4,CONFIG_SYS_GPIO0_TCR@h - ori r4,r4,CONFIG_SYS_GPIO0_TCR@l - stw r4,0(r3) - - li r3,PB1AP /* program EBC bank 1 for RTC access */ - mtdcr EBC0_CFGADDR,r3 - lis r3,CONFIG_SYS_EBC_PB1AP@h - ori r3,r3,CONFIG_SYS_EBC_PB1AP@l - mtdcr EBC0_CFGDATA,r3 - li r3,PB1CR - mtdcr EBC0_CFGADDR,r3 - lis r3,CONFIG_SYS_EBC_PB1CR@h - ori r3,r3,CONFIG_SYS_EBC_PB1CR@l - mtdcr EBC0_CFGDATA,r3 - - li r3,PB1AP /* program EBC bank 1 for RTC access */ - mtdcr EBC0_CFGADDR,r3 - lis r3,CONFIG_SYS_EBC_PB1AP@h - ori r3,r3,CONFIG_SYS_EBC_PB1AP@l - mtdcr EBC0_CFGDATA,r3 - li r3,PB1CR - mtdcr EBC0_CFGADDR,r3 - lis r3,CONFIG_SYS_EBC_PB1CR@h - ori r3,r3,CONFIG_SYS_EBC_PB1CR@l - mtdcr EBC0_CFGDATA,r3 - - li r3,PB4AP /* program EBC bank 4 for FPGA access */ - mtdcr EBC0_CFGADDR,r3 - lis r3,CONFIG_SYS_EBC_PB4AP@h - ori r3,r3,CONFIG_SYS_EBC_PB4AP@l - mtdcr EBC0_CFGDATA,r3 - li r3,PB4CR - mtdcr EBC0_CFGADDR,r3 - lis r3,CONFIG_SYS_EBC_PB4CR@h - ori r3,r3,CONFIG_SYS_EBC_PB4CR@l - mtdcr EBC0_CFGDATA,r3 -#endif - - /* - !----------------------------------------------------------------------- - ! Check to see if chip is in bypass mode. - ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a - ! CPU reset Otherwise, skip this step and keep going. - ! Note: Running BIOS in bypass mode is not supported since PLB speed - ! will not be fast enough for the SDRAM (min 66MHz) - !----------------------------------------------------------------------- - */ - mfdcr r5, CPC0_PLLMR1 - rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ - cmpi cr0,0,r4,0x1 - - beq pll_done /* if SSCS =b'1' then PLL has */ - /* already been set */ - /* and CPU has been reset */ - /* so skip to next section */ - -#ifdef CONFIG_BUBINGA - /* - !----------------------------------------------------------------------- - ! Read NVRAM to get value to write in PLLMR. - ! If value has not been correctly saved, write default value - ! Default config values (assuming on-board 33MHz SYS_CLK) are above. - ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. - ! - ! WARNING: This code assumes the first three words in the nvram_t - ! structure in openbios.h. Changing the beginning of - ! the structure will break this code. - ! - !----------------------------------------------------------------------- - */ - addis r3,0,NVRAM_BASE@h - addi r3,r3,NVRAM_BASE@l - - lwz r4, 0(r3) - addis r5,0,NVRVFY1@h - addi r5,r5,NVRVFY1@l - cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ - bne ..no_pllset - addi r3,r3,4 - lwz r4, 0(r3) - addis r5,0,NVRVFY2@h - addi r5,r5,NVRVFY2@l - cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ - bne ..no_pllset - addi r3,r3,8 /* Skip over conf_size */ - lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ - lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ - rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ - cmpi cr0,0,r5,1 /* See if PLL is locked */ - beq pll_write -..no_pllset: -#endif /* CONFIG_BUBINGA */ - -#ifdef CONFIG_TAIHU - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ - addis r5,0,CPLD_REG0_ADDR@h - ori r5,r5,CPLD_REG0_ADDR@l - andi. r5, r5, 0x10 - bne _pci_66mhz -#endif /* CONFIG_TAIHU */ - -#if defined(CONFIG_ZEUS) - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ - lis r3,0x0000 - addi r3,r3,0x3030 - lis r4,0x8042 - addi r4,r4,0x223e - b 1f -strap_1: - mfdcr r3, CPC0_PLLMR0 - mfdcr r4, CPC0_PLLMR1 - b 1f -#endif - - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ - ori r3,r3,PLLMR0_DEFAULT@l /* */ - addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ - ori r4,r4,PLLMR1_DEFAULT@l /* */ - -#ifdef CONFIG_TAIHU - b 1f -_pci_66mhz: - addis r3,0,PLLMR0_DEFAULT_PCI66@h - ori r3,r3,PLLMR0_DEFAULT_PCI66@l - addis r4,0,PLLMR1_DEFAULT_PCI66@h - ori r4,r4,PLLMR1_DEFAULT_PCI66@l - b 1f -strap_1: - mfdcr r3, CPC0_PLLMR0 - mfdcr r4, CPC0_PLLMR1 -#endif /* CONFIG_TAIHU */ - -1: - b pll_write /* Write the CPC0_PLLMR with new value */ - -pll_done: - /* - !----------------------------------------------------------------------- - ! Clear Soft Reset Register - ! This is needed to enable PCI if not booting from serial EPROM - !----------------------------------------------------------------------- - */ - addi r3, 0, 0x0 - mtdcr CPC0_SRR, r3 - - addis r3,0,0x0010 - mtctr r3 -pci_wait: - bdnz pci_wait - - blr /* return to main code */ - -/* -!----------------------------------------------------------------------------- -! Function: pll_write -! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation -! That is: -! 1. Pll is first disabled (de-activated by putting in bypass mode) -! 2. PLL is reset -! 3. Clock dividers are set while PLL is held in reset and bypassed -! 4. PLL Reset is cleared -! 5. Wait 100us for PLL to lock -! 6. A core reset is performed -! Input: r3 = Value to write to CPC0_PLLMR0 -! Input: r4 = Value to write to CPC0_PLLMR1 -! Output r3 = none -!----------------------------------------------------------------------------- -*/ - .globl pll_write -pll_write: - mfdcr r5, CPC0_UCR - andis. r5,r5,0xFFFF - ori r5,r5,0x0101 /* Stop the UART clocks */ - mtdcr CPC0_UCR,r5 /* Before changing PLL */ - - mfdcr r5, CPC0_PLLMR1 - rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ - mtdcr CPC0_PLLMR1,r5 - oris r5,r5,0x4000 /* Set PLL Reset */ - mtdcr CPC0_PLLMR1,r5 - - mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ - rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ - oris r5,r5,0x4000 /* Set PLL Reset */ - mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ - rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ - mtdcr CPC0_PLLMR1,r5 - - /* - ! Wait min of 100us for PLL to lock. - ! See CMOS 27E databook for more info. - ! At 200MHz, that means waiting 20,000 instructions - */ - addi r3,0,20000 /* 2000 = 0x4e20 */ - mtctr r3 -pll_wait: - bdnz pll_wait - - oris r5,r5,0x8000 /* Enable PLL */ - mtdcr CPC0_PLLMR1,r5 /* Engage */ - - /* - * Reset CPU to guarantee timings are OK - * Not sure if this is needed... - */ - addis r3,0,0x1000 - mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ - /* execution will continue from the poweron */ - /* vector of 0xfffffffc */ -#endif /* CONFIG_405EP */ - -#if defined(CONFIG_440) -/*----------------------------------------------------------------------------+ -| mttlb3. -+----------------------------------------------------------------------------*/ - function_prolog(mttlb3) - TLBWE(4,3,2) - blr - function_epilog(mttlb3) - -/*----------------------------------------------------------------------------+ -| mftlb3. -+----------------------------------------------------------------------------*/ - function_prolog(mftlb3) - TLBRE(3,3,2) - blr - function_epilog(mftlb3) - -/*----------------------------------------------------------------------------+ -| mttlb2. -+----------------------------------------------------------------------------*/ - function_prolog(mttlb2) - TLBWE(4,3,1) - blr - function_epilog(mttlb2) - -/*----------------------------------------------------------------------------+ -| mftlb2. -+----------------------------------------------------------------------------*/ - function_prolog(mftlb2) - TLBRE(3,3,1) - blr - function_epilog(mftlb2) - -/*----------------------------------------------------------------------------+ -| mttlb1. -+----------------------------------------------------------------------------*/ - function_prolog(mttlb1) - TLBWE(4,3,0) - blr - function_epilog(mttlb1) - -/*----------------------------------------------------------------------------+ -| mftlb1. -+----------------------------------------------------------------------------*/ - function_prolog(mftlb1) - TLBRE(3,3,0) - blr - function_epilog(mftlb1) -#endif /* CONFIG_440 */ - -#if defined(CONFIG_NAND_SPL) -/* - * void nand_boot_relocate(dst, src, bytes) - * - * r3 = Destination address to copy code to (in SDRAM) - * r4 = Source address to copy code from - * r5 = size to copy in bytes - */ -nand_boot_relocate: - mr r6,r3 - mr r7,r4 - mflr r8 - - /* - * Copy SPL from icache into SDRAM - */ - subi r3,r3,4 - subi r4,r4,4 - srwi r5,r5,2 - mtctr r5 -..spl_loop: - lwzu r0,4(r4) - stwu r0,4(r3) - bdnz ..spl_loop - - /* - * Calculate "corrected" link register, so that we "continue" - * in execution in destination range - */ - sub r3,r7,r6 /* r3 = src - dst */ - sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ - mtlr r8 - blr - -nand_boot_common: - /* - * First initialize SDRAM. It has to be available *before* calling - * nand_boot(). - */ - lis r3,CONFIG_SYS_SDRAM_BASE@h - ori r3,r3,CONFIG_SYS_SDRAM_BASE@l - bl initdram - - /* - * Now copy the 4k SPL code into SDRAM and continue execution - * from there. - */ - lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h - ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l - lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h - ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l - lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h - ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l - bl nand_boot_relocate - - /* - * We're running from SDRAM now!!! - * - * It is necessary for 4xx systems to relocate from running at - * the original location (0xfffffxxx) to somewhere else (SDRAM - * preferably). This is because CS0 needs to be reconfigured for - * NAND access. And we can't reconfigure this CS when currently - * "running" from it. - */ - - /* - * Finally call nand_boot() to load main NAND U-Boot image from - * NAND and jump to it. - */ - bl nand_boot /* will not return */ -#endif /* CONFIG_NAND_SPL */ diff --git a/cpu/ppc4xx/u-boot.lds b/cpu/ppc4xx/u-boot.lds deleted file mode 100644 index 2b47934a2e..0000000000 --- a/cpu/ppc4xx/u-boot.lds +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include "config.h" /* CONFIG_BOARDDIR */ - -#ifndef RESET_VECTOR_ADDRESS -#define RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - *(.text) - *(.got1) - } :text - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - -#ifdef CONFIG_440 - .bootpg RESET_VECTOR_ADDRESS - 0xffc : - { - cpu/ppc4xx/start.o (.bootpg) - - /* - * PPC440 board need a board specific object with the - * TLB definitions. This needs to get included right after - * start.o, since the first shadow TLB only covers 4k - * of address space. - */ - CONFIG_BOARDDIR/init.o (.bootpg) - } :text = 0xffff -#endif - - .resetvec RESET_VECTOR_ADDRESS : - { - *(.resetvec) - } :text = 0xffff - - . = RESET_VECTOR_ADDRESS + 0x4; - - /* - * Make sure that the bss segment isn't linked at 0x0, otherwise its - * address won't be updated during relocation fixups. Note that - * this is a temporary fix. Code to dynamically the fixup the bss - * location will be added in the future. When the bss relocation - * fixup code is present this workaround should be removed. - */ -#if (RESET_VECTOR_ADDRESS == 0xfffffffc) - . |= 0x10; -#endif - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } :bss - - . = ALIGN(4); - _end = . ; - PROVIDE (end = .); -} diff --git a/cpu/pxa/u-boot.lds b/cpu/pxa/u-boot.lds deleted file mode 100644 index 77ab3c902b..0000000000 --- a/cpu/pxa/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/s3c44b0/u-boot.lds b/cpu/s3c44b0/u-boot.lds deleted file mode 100644 index 41ca3b4e8d..0000000000 --- a/cpu/s3c44b0/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/s3c44b0/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/sa1100/u-boot.lds b/cpu/sa1100/u-boot.lds deleted file mode 100644 index 0c02e76e7a..0000000000 --- a/cpu/sa1100/u-boot.lds +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * MontaVista Software, Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - _end = .; -} diff --git a/cpu/sh2/u-boot.lds b/cpu/sh2/u-boot.lds deleted file mode 100644 index 6db5a00913..0000000000 --- a/cpu/sh2/u-boot.lds +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh2/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} diff --git a/cpu/sh3/u-boot.lds b/cpu/sh3/u-boot.lds deleted file mode 100644 index 1e55b832f5..0000000000 --- a/cpu/sh3/u-boot.lds +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (C) 2007 - * Yoshihiro Shimoda - * - * Copyright (C) 2007 - * Nobuhiro Iwamatsu - * - * Copyright (C) 2008 - * Mark Jonas - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh3/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} diff --git a/cpu/sh4/u-boot.lds b/cpu/sh4/u-boot.lds deleted file mode 100644 index bff9f43c10..0000000000 --- a/cpu/sh4/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu - * - * Copyright (C) 2008-2009 - * Yoshihiro Shimoda - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh4/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss (NOLOAD) : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} diff --git a/doc/README-integrator b/doc/README-integrator index 4daf3413aa..5a0e934924 100644 --- a/doc/README-integrator +++ b/doc/README-integrator @@ -52,7 +52,7 @@ cpu/arm<>/start.S so that it may be used by other boards. However, to avoid duplicating code through all processor files, a generic core for ARM Integrator CMs has been added - cpu/arm_intcm + arch/arm/cpu/arm_intcm Otherwise. for example, the standard CM reset via the CM control register would need placing in each CM processor file...... diff --git a/doc/README.ARM-SoC b/doc/README.ARM-SoC index 0f2677f88b..d6bd624886 100644 --- a/doc/README.ARM-SoC +++ b/doc/README.ARM-SoC @@ -1,24 +1,24 @@ [By Steven Scholz , 16 Aug 2004] Since the cpu/ directory gets clobbered with peripheral driver code I -started cleaning up cpu/arm920t. +started cleaning up arch/arm/cpu/arm920t. I introduced the concept of Soc (system on a chip) into the ./cpu directory. That means that code that is cpu (i.e. core) specific resides in - cpu/$(CPU)/ + $(CPUDIR)/ and code that is specific to some SoC (i.e. vendor specific peripherals around the core) is moved into - cpu/$(CPU)/$(SOC)/ + $(CPUDIR)/$(SOC)/ -Thus a library/archive "cpu/$(CPU)/$(SOC)/lib$(SOC).a" will be build +Thus a library/archive "$(CPUDIR)/$(SOC)/lib$(SOC).a" will be build and linked. Examples will be - cpu/arm920t/imx/ - cpu/arm920t/s3c24x0 + arch/arm/cpu/arm920t/imx/ + arch/arm/cpu/arm920t/s3c24x0 One can select an SoC by passing the name of it to ./mkconfig just like diff --git a/doc/README.LED b/doc/README.LED index 94e552aa03..c3bcb3ac80 100644 --- a/doc/README.LED +++ b/doc/README.LED @@ -69,7 +69,7 @@ yellow_LED_off blue_LED_on blue_LED_off -These are weakly defined in lib_arm/board.c to noops. Where applicable, define +These are weakly defined in arch/arm/lib/board.c to noops. Where applicable, define these functions in the board specific source. TBD : Describe older board dependent macros similar to what is done for diff --git a/doc/README.PIP405 b/doc/README.PIP405 index d8b3f9c012..e8a654128d 100644 --- a/doc/README.PIP405 +++ b/doc/README.PIP405 @@ -17,11 +17,11 @@ Changed files: added console settings from environment - common/devices.c added ISA keyboard init - common/main.c corrected the read of bootdelay -- cpu/ppc4xx/405gp_pci.c excluded file from PIP405 -- cpu/ppc4xx/i2c.c added 16bit read write I2C support +- arch/ppc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405 +- arch/ppc/cpu/ppc4xx/i2c.c added 16bit read write I2C support added page write -- cpu/ppc4xx/speed.c added get_PCI_freq -- cpu/ppc4xx/start.S added CONFIG_IDENT_STRING +- arch/ppc/cpu/ppc4xx/speed.c added get_PCI_freq +- arch/ppc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING - disk/Makefile added part_iso for CD support - disk/part.c changed to work with block device description added ISO CD support @@ -275,7 +275,7 @@ Added the config variable CONFIG_IDENT_STRING which will be added to the "U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate and custom versions. Changed files: -- cpu/ppc4xx/start.s +- arch/ppc/cpu/ppc4xx/start.s Firmware Image: --------------- @@ -288,11 +288,11 @@ Changed files: Correct PCI Frequency for PPC405: --------------------------------- -Added function (in cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU. +Added function (in arch/ppc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU. The PCI Frequency will now be set correct in the board description in common/board.c. (was set to the busfreq before). Changed files: -- cpu/ppc4xx/speed.c +- arch/ppc/cpu/ppc4xx/speed.c - common/board.c I2C Stuff: @@ -301,7 +301,7 @@ Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c. Added 16bit read/write support for I2C (PPC405), and page write to I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE. Changed files: -- cpu/ppc4xx/i2c.c +- arch/ppc/cpu/ppc4xx/i2c.c - common/cmd_i2c.c Environment / Console: diff --git a/doc/README.POST b/doc/README.POST index a81e07926d..0d5e20e977 100644 --- a/doc/README.POST +++ b/doc/README.POST @@ -713,7 +713,7 @@ use external loopback for testing. That will need appropriate reconfiguration of the physical interface chip. The test routines for the SCC ethernet tests will be located in -cpu/mpc8xx/scc.c. +arch/ppc/cpu/mpc8xx/scc.c. 2.2.3.2. UART tests (SMC/SCC) @@ -725,7 +725,7 @@ will be transmitted. These tests may be enhanced to make to perform test will be executed manually. The test routine for the SMC/SCC UART tests will be located in -cpu/mpc8xx/serial.c. +arch/ppc/cpu/mpc8xx/serial.c. 2.2.3.3. USB test diff --git a/doc/README.RPXlite b/doc/README.RPXlite index c0238ae213..0aa4d11303 100644 --- a/doc/README.RPXlite +++ b/doc/README.RPXlite @@ -116,7 +116,7 @@ board/RPXLITE/RPXLITE.c /* DRAM-related routines */ board/RPXLITE/flash.c /* flash-related routines */ board/RPXLITE/config.mk /* set text base address */ - cpu/mpc8xx/serial.c /* board specific register setting */ + arch/ppc/cpu/mpc8xx/serial.c /* board specific register setting */ include/config_RPXLITE.h /* board specific registers */ See 'reg_config.txt' for register values in detail. diff --git a/doc/README.TQM8260 b/doc/README.TQM8260 index b93a1cb948..e64e64a3e2 100644 --- a/doc/README.TQM8260 +++ b/doc/README.TQM8260 @@ -14,10 +14,10 @@ The following common files have been modified by this project: MAKEALL - TQM8260 entry added Makefile - TQM8260_config entry added -cpu/mpc8260/Makefile - soft_i2c.o module added -cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious +arch/ppc/cpu/mpc8260/Makefile - soft_i2c.o module added +arch/ppc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious bug fixed (fcr -> scr) -cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added +arch/ppc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added include/flash.h - added definitions for the AM29LV640D Flash chip @@ -33,7 +33,7 @@ board/tqm8260/config.mk - config file board/tqm8260/flash.c - flash driver (for AM29LV640D) board/tqm8260/ppcboot.lds - linker script board/tqm8260/tqm8260.c - ioport and memory initialization -cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver +arch/ppc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver include/config_TQM8260.h - main configuration file diff --git a/doc/README.alaska8220 b/doc/README.alaska8220 index 0bd68d9628..9249cfb31e 100644 --- a/doc/README.alaska8220 +++ b/doc/README.alaska8220 @@ -22,7 +22,7 @@ Changed files: - include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk, vco_clk, pev_clk, flb_clk, and bExtUart -- lib_ppc/board.c added CONFIG_MPC8220 support +- arch/ppc/lib/board.c added CONFIG_MPC8220 support - net/eth.c added FEC support for MPC8220 @@ -37,24 +37,24 @@ Added files: - board/alaska/config.mk config make - board/alaska/u-boot.lds Linker description -- cpu/mpc8220/dma.h multi-channel dma header file -- cpu/mpc8220/dramSetup.h dram setup header file -- cpu/mpc8220/fec.h MPC8220 FEC header file -- cpu/mpc8220/cpu.c cpu specific code -- cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup -- cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup -- cpu/mpc8220/fec.c MPC8220 FEC driver -- cpu/mpc8220/i2c.c MPC8220 I2C driver -- cpu/mpc8220/interrupts.c interrupt support (not enable) -- cpu/mpc8220/loadtask.c load dma -- cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock -- cpu/mpc8220/traps.c exception -- cpu/mpc8220/uart.c MPC8220 UART driver -- cpu/mpc8220/Makefile Makefile -- cpu/mpc8220/config.mk config make -- cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program -- cpu/mpc8220/io.S io functions -- cpu/mpc8220/start.S start up +- arch/ppc/cpu/mpc8220/dma.h multi-channel dma header file +- arch/ppc/cpu/mpc8220/dramSetup.h dram setup header file +- arch/ppc/cpu/mpc8220/fec.h MPC8220 FEC header file +- arch/ppc/cpu/mpc8220/cpu.c cpu specific code +- arch/ppc/cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup +- arch/ppc/cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup +- arch/ppc/cpu/mpc8220/fec.c MPC8220 FEC driver +- arch/ppc/cpu/mpc8220/i2c.c MPC8220 I2C driver +- arch/ppc/cpu/mpc8220/interrupts.c interrupt support (not enable) +- arch/ppc/cpu/mpc8220/loadtask.c load dma +- arch/ppc/cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock +- arch/ppc/cpu/mpc8220/traps.c exception +- arch/ppc/cpu/mpc8220/uart.c MPC8220 UART driver +- arch/ppc/cpu/mpc8220/Makefile Makefile +- arch/ppc/cpu/mpc8220/config.mk config make +- arch/ppc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program +- arch/ppc/cpu/mpc8220/io.S io functions +- arch/ppc/cpu/mpc8220/start.S start up - include/mpc8220.h diff --git a/doc/README.bedbug b/doc/README.bedbug index 2616acc653..4c1e6c4d5b 100644 --- a/doc/README.bedbug +++ b/doc/README.bedbug @@ -18,15 +18,15 @@ can be easily implemented. ./common/board.c Added call to initialize debugger on startup. -./cpu/ppc4xx/Makefile +./arch/ppc/cpu/ppc4xx/Makefile Added bedbug_405.c to the Makefile. -./cpu/ppc4xx/start.S +./arch/ppc/cpu/ppc4xx/start.S Added code to handle the debug exception (0x2000) on the 405. Also added code to handle critical exceptions since the debug is treated as critical on the 405. -./cpu/ppc4xx/traps.c +./arch/ppc/cpu/ppc4xx/traps.c Added more detailed output for the program exception to tell if it is an illegal instruction, privileged instruction or a trap. Also added debug trap handler. @@ -51,7 +51,7 @@ can be easily implemented. hardware breakpoints and stepping through code. These routines are common to all PowerPC processors. -./cpu/ppc4xx/bedbug_405.c +./arch/ppc/cpu/ppc4xx/bedbug_405.c AMCC PPC405 specific debugger routines. @@ -63,16 +63,16 @@ Changes: common/cmd_bedbug.c Added call to initialize 860 debugger. - cpu/mpc8xx/Makefile + arch/ppc/cpu/mpc8xx/Makefile Added new file "bedbug_860.c" to the makefile - cpu/mpc8xx/start.S + arch/ppc/cpu/mpc8xx/start.S Added handler for InstructionBreakpoint (0xfd00) - cpu/mpc8xx/traps.c + arch/ppc/cpu/mpc8xx/traps.c Added new routine DebugException() New Files: - cpu/mpc8xx/bedbug_860.c + arch/ppc/cpu/mpc8xx/bedbug_860.c CPU-specific routines for 860 debug registers. diff --git a/doc/README.enetaddr b/doc/README.enetaddr index 1d75aa3876..94d800a02a 100644 --- a/doc/README.enetaddr +++ b/doc/README.enetaddr @@ -28,6 +28,17 @@ Here are the places where MAC addresses might be stored: purpose of passing this information to an OS kernel we are about to boot +Correct flow of setting up the MAC address (summarized): + +1. Read from hardware in initialize() function +2. Read from environment in net/eth.c after initialize() +3. Give priority to the value in the environment if a conflict +4. Program hardware in the device's init() function. + +If somebody wants to subvert the design philosophy, this can be done +in the board-specific board_eth_init() function by calling eth_init() +after all the NICs have been registered. + ------- Usage ------- diff --git a/doc/README.m52277evb b/doc/README.m52277evb index 40f9028c6f..b6e955bcad 100644 --- a/doc/README.m52277evb +++ b/doc/README.m52277evb @@ -14,13 +14,13 @@ Changed files: - board/freescale/m52277evb/config.mk config make - board/freescale/m52277evb/u-boot.lds Linker description -- cpu/mcf5227x/cpu.c cpu specific code -- cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs -- cpu/mcf5227x/interrupts.c cpu specific interrupt support -- cpu/mcf5227x/speed.c system, flexbus, and cpu clock -- cpu/mcf5227x/Makefile Makefile -- cpu/mcf5227x/config.mk config make -- cpu/mcf5227x/start.S start up assembly code +- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code +- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock +- arch/m68k/cpu/mcf5227x/Makefile Makefile +- arch/m68k/cpu/mcf5227x/config.mk config make +- arch/m68k/cpu/mcf5227x/start.S start up assembly code - doc/README.m52277evb This readme file @@ -53,12 +53,12 @@ Changed files: - include/configs/M52277EVB.h Board specific configuration file -- lib_m68k/board.c board init function -- lib_m68k/cache.c -- lib_m68k/interrupts Coldfire common interrupt functions -- lib_m68k/m68k_linux.c -- lib_m68k/time.c Timer functions (Dma timer and PIT) -- lib_m68k/traps.c Exception init code +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code 1 MCF52277 specific Options/Settings ==================================== diff --git a/doc/README.m53017evb b/doc/README.m53017evb index 60cfa95af3..42798c2000 100644 --- a/doc/README.m53017evb +++ b/doc/README.m53017evb @@ -15,13 +15,13 @@ Changed files: - board/freescale/m53017evb/config.mk config make - board/freescale/m53017evb/u-boot.lds Linker description -- cpu/mcf532x/cpu.c cpu specific code -- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs -- cpu/mcf532x/interrupts.c cpu specific interrupt support -- cpu/mcf532x/speed.c system, flexbus, and cpu clock -- cpu/mcf532x/Makefile Makefile -- cpu/mcf532x/config.mk config make -- cpu/mcf532x/start.S start up assembly code +- arch/m68k/cpu/mcf532x/cpu.c cpu specific code +- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf532x/speed.c system, flexbus, and cpu clock +- arch/m68k/cpu/mcf532x/Makefile Makefile +- arch/m68k/cpu/mcf532x/config.mk config make +- arch/m68k/cpu/mcf532x/start.S start up assembly code - doc/README.m53017evb This readme file @@ -51,12 +51,12 @@ Changed files: - include/configs/M53017EVB.h Board specific configuration file -- lib_m68k/board.c board init function -- lib_m68k/cache.c -- lib_m68k/interrupts Coldfire common interrupt functions -- lib_m68k/m68k_linux.c -- lib_m68k/time.c Timer functions (Dma timer and PIT) -- lib_m68k/traps.c Exception init code +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code 1 MCF5301x specific Options/Settings ==================================== diff --git a/doc/README.m5373evb b/doc/README.m5373evb index 5591748933..e90a320ee5 100644 --- a/doc/README.m5373evb +++ b/doc/README.m5373evb @@ -15,13 +15,13 @@ Changed files: - board/freescale/m5373evb/config.mk config make - board/freescale/m5373evb/u-boot.lds Linker description -- cpu/mcf532x/cpu.c cpu specific code -- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs -- cpu/mcf532x/interrupts.c cpu specific interrupt support -- cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock -- cpu/mcf532x/Makefile Makefile -- cpu/mcf532x/config.mk config make -- cpu/mcf532x/start.S start up assembly code +- arch/m68k/cpu/mcf532x/cpu.c cpu specific code +- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock +- arch/m68k/cpu/mcf532x/Makefile Makefile +- arch/m68k/cpu/mcf532x/config.mk config make +- arch/m68k/cpu/mcf532x/start.S start up assembly code - doc/README.m5373evb This readme file @@ -50,12 +50,12 @@ Changed files: - include/configs/M5373EVB.h Board specific configuration file -- lib_m68k/board.c board init function -- lib_m68k/cache.c -- lib_m68k/interrupts Coldfire common interrupt functions -- lib_m68k/m68k_linux.c -- lib_m68k/time.c Timer functions (Dma timer and PIT) -- lib_m68k/traps.c Exception init code +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code 1 MCF5373 specific Options/Settings ==================================== diff --git a/doc/README.m54455evb b/doc/README.m54455evb index 1888e16625..918a746eb8 100644 --- a/doc/README.m54455evb +++ b/doc/README.m54455evb @@ -18,13 +18,13 @@ Changed files: - common/cmd_bdinfo.c Clock frequencies output - common/cmd_mii.c mii support -- cpu/mcf5445x/cpu.c cpu specific code -- cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs -- cpu/mcf5445x/interrupts.c cpu specific interrupt support -- cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock -- cpu/mcf5445x/Makefile Makefile -- cpu/mcf5445x/config.mk config make -- cpu/mcf5445x/start.S start up assembly code +- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code +- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock +- arch/m68k/cpu/mcf5445x/Makefile Makefile +- arch/m68k/cpu/mcf5445x/config.mk config make +- arch/m68k/cpu/mcf5445x/start.S start up assembly code - doc/README.m54455evb This readme file @@ -52,12 +52,12 @@ Changed files: - include/configs/M54455EVB.h Board specific configuration file -- lib_m68k/board.c board init function -- lib_m68k/cache.c -- lib_m68k/interrupts Coldfire common interrupt functions -- lib_m68k/m68k_linux.c -- lib_m68k/time.c Timer functions (Dma timer and PIT) -- lib_m68k/traps.c Exception init code +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code - rtc/mcfrtc.c Realtime clock Driver diff --git a/doc/README.m5475evb b/doc/README.m5475evb index f3a1d7b28b..f5658ea486 100644 --- a/doc/README.m5475evb +++ b/doc/README.m5475evb @@ -15,14 +15,14 @@ Changed files: - board/freescale/m547xevb/config.mk config make - board/freescale/m547xevb/u-boot.lds Linker description -- cpu/mcf547x_8x/cpu.c cpu specific code -- cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs -- cpu/mcf547x_8x/interrupts.c cpu specific interrupt support -- cpu/mcf547x_8x/slicetimer.c Timer support -- cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock -- cpu/mcf547x_8x/Makefile Makefile -- cpu/mcf547x_8x/config.mk config make -- cpu/mcf547x_8x/start.S start up assembly code +- arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code +- arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support +- arch/m68k/cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock +- arch/m68k/cpu/mcf547x_8x/Makefile Makefile +- arch/m68k/cpu/mcf547x_8x/config.mk config make +- arch/m68k/cpu/mcf547x_8x/start.S start up assembly code - doc/README.m5475evb This readme file @@ -58,11 +58,11 @@ Changed files: - include/configs/M5475EVB.h Board specific configuration file -- lib_m68k/board.c board init function -- lib_m68k/cache.c -- lib_m68k/interrupts Coldfire common interrupt functions -- lib_m68k/m68k_linux.c -- lib_m68k/traps.c Exception init code +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/traps.c Exception init code 1 MCF547x specific Options/Settings ==================================== diff --git a/doc/README.m68k b/doc/README.m68k index e6c33a7d96..a00ab69b6f 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -31,12 +31,12 @@ hopefully added soon! 2.1 Motorola Coldfire MCF5272 ----------------------------- -CPU specific code is located in: cpu/mcf52x2 +CPU specific code is located in: arch/m68k/cpu/mcf52x2 2.1 Motorola Coldfire MCF5282 ----------------------------- -CPU specific code is located in: cpu/mcf52x2 +CPU specific code is located in: arch/m68k/cpu/mcf52x2 The MCF5282 Port no longer needs a preloader and can place in external or internal FLASH. diff --git a/doc/README.ml300 b/doc/README.ml300 deleted file mode 100644 index 27c5b92783..0000000000 --- a/doc/README.ml300 +++ /dev/null @@ -1,128 +0,0 @@ -Xilinx ML300 platform -===================== - -0. Introduction ---------------- - -The Xilinx ML300 board is based on the Virtex-II Pro FPGA with -integrated AMCC PowerPC 405 core. The board is normally booted from -System ACE CF. U-Boot is then run out of main memory. - -An FPGA is a configurable and thus very flexible device. To -accommodate for this flexibility this port of U-Boot includes the -required means to regenerate the drivers and configuration files if -you decide to change the hardware design. The required steps are -described below. - - -1. Requirements ---------------- - -To compile and run U-Boot on the Xilinx ML300 platform you need the -following items. - -- A Xilinx ML300 platform (see http://www.xilinx.com/ml300) -- EDK and ISE development tools (shipping with ML300) -- Parallel4 cable (shipping with ML300) -- The EDK reference design for ML300. You can get this as design #6 from - http://www.xilinx.com/ise/embedded/edk_examples.htm -- A BOOTP/TFTP server - - -2. Quick Start --------------- - -To compile and run U-Boot on ML300 follow the steps below. Make sure -to consult the documentation for U-Boot, EDK, and the EDK reference -design for ML300 if you have any questions. - -1. Implement the EDK reference design for ML300. You can use any of - the project files, for example from a xygwin shell: - $ xps -nw system_linux.xmp - XPS% run init_bram -2. Configure and compile U-Boot. Change into the root directory of - U-Boot and run: - $ export CROSS_COMPILE=powerpc-eabi- - $ make ml300_config - $ make -3. Set up the ML300, connect the Parallel4 and the serial cable. Start - a terminal on your host computer and set the communication - parameters to 9600,8N1,no handshake. -4. Set up the BOOTP/TFTP server on your host machine. U-Boot is - preconfigured to use a fixed HW MAC address of 00:0A:35:00:22:01. -5. Download the bitstream to the ML300. -6. Use XMD to download and run U-Boot on the ML300: - $ xmd - XMD% ppcconnect - XMD% dow u-boot - XMD% run - -You can now make an ACE file out of bitstream and U-Boot: - $ xmd genace.tcl -jprog -board ml300 -hw \ - implementation/download.bit -elf u-boot -ace top.ace - -Put the ACE file onto the MicroDrive, for example into xilinx/myace, -and reboot ML300. - - -3. Generating a Custom BSP for U-Boot -------------------------------------- - -If you decide to change the EDK reference design for ML300 or if you -build a new design from scratch either with the Base System Builder in -XPS or all by hand you most likely will change the base addresses for -the Uart and the Ethernet peripheral. If you do so you will have two -options: - -1. Edit boards/xilinx/ml300/xparameters.h to reflect the changes you - made to your hardware. -2. Use the MLD technology provided by Xilinx Platform Studio to make - the changes automatically. To do so go to the root directory of the - EDK reference design for ML300. Copy the Linux project file and the - Linux software configuration file: - $ cp system_linux.xmp system_uboot.xmp - $ cp system_linux.mss system_uboot.mss - - Edit system_uboot.xmp and and have it point to system_uboot.mss for - the software configuration. - - Then, copy the sw_services directory in - boards/xilinx/ml300/sw_services to the root directory of the EDK - reference design for ML300. - $ cp -R /boards/xilinx/ml300/sw_services - - Modify system_uboot.mss. Look for the Linux library definition - and change it to generate a BSP for U-Boot. An example, might look - like this: - - BEGIN LIBRARY - PARAMETER LIBRARY_NAME = uboot - PARAMETER LIBRARY_VER = 1.00.a - PARAMETER CONNECTED_PERIPHS = (opb_uart16550_0,opb_ethernet_0) - PARAMETER TARGET_DIR = - END - - Now, you are ready to generate the Xilinx ML300 BSP for U-Boot: - $ xps -nw system_uboot.xmp - XPS% run libs - - If all goes well the new configuration has been copied into the - right places within the U-Boot source tree. Recompile U-Boot and - run it on the ML300. - - -4. ToDo -------- - -- Add support for all other peripherals on ML300. -- Read the MAC address out of the IIC EEPROM. -- Store the bootargs in the IIC EEPROM. - - -5. References -------------- - -ML300: http://www.xilinx.com/ml300 -EDK: http://www.xilinx.com/edk -ISE: http://www.xilinx.com/ise -Reference Design: http://www.xilinx.com/ise/embedded/edk_examples.htm diff --git a/doc/README.modnet50 b/doc/README.modnet50 index f7bb254e16..2ac3c8fbe3 100644 --- a/doc/README.modnet50 +++ b/doc/README.modnet50 @@ -45,7 +45,7 @@ flash. Files: -cpu/arm720t/serial_netarm.c .. serial I/O for the cpu +arch/arm/cpu/arm720t/serial_netarm.c .. serial I/O for the cpu board/modnet50/lowlevel_init.S .. memory setup for ModNET50 board/modnet50/flash.c .. flash routines diff --git a/doc/README.mpc5xx b/doc/README.mpc5xx index 07be8637fa..26fb0c27dc 100644 --- a/doc/README.mpc5xx +++ b/doc/README.mpc5xx @@ -25,7 +25,7 @@ Added or Changed Files: u-boot-0.2.0/common/cmd_boot.c u-boot-0.2.0/common/cmd_reginfo.c u-boot-0.2.0/common/environment.c -u-boot-0.2.0/cpu/mpc5xx/* +u-boot-0.2.0/arch/ppc/cpu/mpc5xx/* u-boot-0.2.0/include/cmd_reginfo.h u-boot-0.2.0/include/common.h u-boot-0.2.0/include/ppc_asm.tmpl @@ -34,9 +34,9 @@ u-boot-0.2.0/include/mpc5xx.h u-boot-0.2.0/include/status_led.h u-boot-0.2.0/include/asm-ppc/u-boot.h u-boot-0.2.0/include/asm-ppc/5xx_immap.h -u-boot-0.2.0/lib_ppc/board.c -u-boot-0.2.0/lib_ppc/cache.c -u-boot-0.2.0/lib_ppc/time.c +u-boot-0.2.0/arch/ppc/lib/board.c +u-boot-0.2.0/arch/ppc/lib/cache.c +u-boot-0.2.0/arch/ppc/lib/time.c u-boot-0.2.0/Makefile u-boot-0.2.0/CREDITS u-boot-0.2.0/doc/README.mpc5xx diff --git a/doc/README.mvsmr b/doc/README.mvsmr new file mode 100644 index 0000000000..d729ea6fbe --- /dev/null +++ b/doc/README.mvsmr @@ -0,0 +1,55 @@ +Matrix Vision mvSMR +------------------- + +1. Board Description + + The mvSMR is a 75x130mm single image processing board used + in automation. Power Supply is 24VDC. + +2 System Components + +2.1 CPU + Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. + 64MB DDR-I @ 133MHz. + 8 MByte Nor Flash on local bus. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + +2.2 PCI + PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core. + +2.3 FPGA + Xilinx Spartan-3 XC3S200 with PCI DMA engine. + Connects to Matrix Vision specific CCD/CMOS sensor interface. + +2.4 I2C + EEPROM @ 0xA0 for vendor specifics. + image sensor interface (slave adresses depend on sensor) + +3 Flash layout. + + reset vector is 0x00000100, i.e. "LOWBOOT". + + FF800000 u-boot + FF806000 u-boot script image + FF808000 u-boot environment + FF840000 FPGA raw bit file + FF880000 root FS + FFF00000 kernel + +4 Booting + + On startup the bootscript @ FF806000 is executed. This script can be + exchanged easily. Default boot mode is "boot from flash", i.e. system + works stand-alone. + + This behaviour depends on some environment variables : + + "netboot" : yes ->try dhcp/bootp and boot from network. + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for + DHCP server configuration, e.g. to provide different images to + different devices. + + During netboot the system tries to get 3 image files: + 1. Kernel - name + data is given during BOOTP. + 2. Initrd - name is stored in "initrd_name" + Fallback files are the flash versions. diff --git a/doc/README.nios b/doc/README.nios index 7f34938081..5628144600 100644 --- a/doc/README.nios +++ b/doc/README.nios @@ -243,8 +243,8 @@ cover most of the individual functions to get you started. following commands, then close the console window: (gdb) directory common - (gdb) directory cpu/nios - (gdb) directory lib_nios + (gdb) directory arch/nios/cpu + (gdb) directory arch/nios/lib (gdb) directory board/altera/dk1c20 Note that the last command is for the DK1C20 board only. If you diff --git a/doc/TODO-i386 b/doc/TODO-i386 index 84113f8112..9b6c5d41ab 100644 --- a/doc/TODO-i386 +++ b/doc/TODO-i386 @@ -4,11 +4,11 @@ i386 port missing features: * setup the BIOS data area and BIOS equipment word to reflect machine config. * Make reset work (from Linux and from the boot prompt) * DMA, FDC, RTC, KBC initialization -* split of part of cpu/i386/interrupt.c to cpu/i385/entry.c? +* split of part of arch/i386/cpu/interrupt.c to cpu/i385/entry.c? * re-entry of protected mode from real mode, should be added to realmode_switch.S (and used by INT 10h and INT 16h handlers for console I/O during early linux boot...) -* missing functions in lib_i386 and cpu/i386 +* missing functions in arch/i386/lib and arch/i386/cpu * speaker beep interface diff --git a/doc/uImage.FIT/multi.its b/doc/uImage.FIT/multi.its index a120da038f..881b74952d 100644 --- a/doc/uImage.FIT/multi.its +++ b/doc/uImage.FIT/multi.its @@ -61,6 +61,8 @@ arch = "ppc"; os = "linux"; compression = "gzip"; + load = <00000000>; + entry = <00000000>; hash@1 { algo = "sha1"; }; @@ -73,6 +75,8 @@ arch = "ppc"; os = "linux"; compression = "gzip"; + load = <00000000>; + entry = <00000000>; hash@1 { algo = "crc32"; }; diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 5f9bd101d6..dbb5e8cce5 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -173,7 +173,7 @@ Maps a pointer to the BIOS image on the graphics card on the PCI bus. ****************************************************************************/ void *PCI_mapBIOSImage(pci_dev_t pcidev) { - u32 BIOSImagePhys; + u32 BIOSImageBus; int BIOSImageBAR; u8 *BIOSImage; @@ -195,16 +195,18 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev) specific programming for different cards to solve this problem. */ - if ((BIOSImagePhys = PCI_findBIOSAddr(pcidev, &BIOSImageBAR)) == 0) { + BIOSImageBus = PCI_findBIOSAddr(pcidev, &BIOSImageBAR); + if (BIOSImageBus == 0) { printf("Find bios addr error\n"); return NULL; } - BIOSImage = (u8 *) BIOSImagePhys; + BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus, + PCI_REGION_MEM, 0, MAP_NOCACHE); /*Change the PCI BAR registers to map it onto the bus.*/ pci_write_config_dword(pcidev, BIOSImageBAR, 0); - pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImagePhys | 0x1); + pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); udelay(1); @@ -315,7 +317,8 @@ int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp) BE_init(0, 65536, VGAInfo, 0); /*Post all the display controller BIOS'es*/ - PCI_postController(pcidev, VGAInfo); + if (!PCI_postController(pcidev, VGAInfo)) + return false; /*Cleanup and exit the emulator if requested. If the BIOS emulator is needed after booting the card, we will not call BE_exit and diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 0fe30410a6..7a89b5692c 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -385,34 +385,38 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) } while ((*fn->init) (cookie)); /* Load the data */ - while (bytecount < bsize) { + if(*fn->bwr) + (*fn->bwr) (data, bsize, TRUE, cookie); + else { + while (bytecount < bsize) { - /* Xilinx detects an error if INIT goes low (active) - while DONE is low (inactive) */ - if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { - puts ("** CRC error during FPGA load.\n"); - return (FPGA_FAIL); - } - val = data [bytecount ++]; - i = 8; - do { - /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); - CONFIG_FPGA_DELAY (); - /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); - CONFIG_FPGA_DELAY (); - /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); - CONFIG_FPGA_DELAY (); - val <<= 1; - i --; - } while (i > 0); + /* Xilinx detects an error if INIT goes low (active) + while DONE is low (inactive) */ + if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { + puts ("** CRC error during FPGA load.\n"); + return (FPGA_FAIL); + } + val = data [bytecount ++]; + i = 8; + do { + /* Deassert the clock */ + (*fn->clk) (FALSE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Write data */ + (*fn->wr) ((val & 0x80), TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Assert the clock */ + (*fn->clk) (TRUE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + val <<= 1; + i --; + } while (i > 0); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (bytecount % (bsize / 40) == 0) - putc ('.'); /* let them know we are alive */ + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ #endif + } } CONFIG_FPGA_DELAY (); diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 29bda85dbd..d2c251546a 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o +COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o diff --git a/drivers/i2c/ppc4xx_i2c.c b/drivers/i2c/ppc4xx_i2c.c new file mode 100644 index 0000000000..e9548f1a68 --- /dev/null +++ b/drivers/i2c/ppc4xx_i2c.c @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2007-2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * based on work by Anne Sophie Harnois + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include <4xx_i2c.h> +#include +#include + +#ifdef CONFIG_HARD_I2C + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_I2C_MULTI_BUS) +/* + * Initialize the bus pointer to whatever one the SPD EEPROM is on. + * Default is bus 0. This is necessary because the DDR initialization + * runs from ROM, and we can't switch buses because we can't modify + * the global variables. + */ +#ifndef CONFIG_SYS_SPD_BUS_NUM +#define CONFIG_SYS_SPD_BUS_NUM 0 +#endif +static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = + CONFIG_SYS_SPD_BUS_NUM; +#endif /* CONFIG_I2C_MULTI_BUS */ + +static void _i2c_bus_reset(void) +{ + struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; + int i; + u8 dc; + + /* Reset status register */ + /* write 1 in SCMP and IRQA to clear these fields */ + out_8(&i2c->sts, 0x0A); + + /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ + out_8(&i2c->extsts, 0x8F); + + /* Place chip in the reset state */ + out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); + + /* Check if bus is free */ + dc = in_8(&i2c->directcntl); + if (!DIRCTNL_FREE(dc)){ + /* Try to set bus free state */ + out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC); + + /* Wait until we regain bus control */ + for (i = 0; i < 100; ++i) { + dc = in_8(&i2c->directcntl); + if (DIRCTNL_FREE(dc)) + break; + + /* Toggle SCL line */ + dc ^= IIC_DIRCNTL_SCC; + out_8(&i2c->directcntl, dc); + udelay(10); + dc ^= IIC_DIRCNTL_SCC; + out_8(&i2c->directcntl, dc); + } + } + + /* Remove reset */ + out_8(&i2c->xtcntlss, 0); +} + +void i2c_init(int speed, int slaveaddr) +{ + struct ppc4xx_i2c *i2c; + int val, divisor; + int bus; + +#ifdef CONFIG_SYS_I2C_INIT_BOARD + /* + * Call board specific i2c bus reset routine before accessing the + * environment, which might be in a chip on that bus. For details + * about this problem see doc/I2C_Edge_Conditions. + */ + i2c_init_board(); +#endif + + for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) { + I2C_SET_BUS(bus); + + /* Set i2c pointer after calling I2C_SET_BUS() */ + i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; + + /* Handle possible failed I2C state */ + /* FIXME: put this into i2c_init_board()? */ + _i2c_bus_reset(); + + /* clear lo master address */ + out_8(&i2c->lmadr, 0); + + /* clear hi master address */ + out_8(&i2c->hmadr, 0); + + /* clear lo slave address */ + out_8(&i2c->lsadr, 0); + + /* clear hi slave address */ + out_8(&i2c->hsadr, 0); + + /* Clock divide Register */ + /* set divisor according to freq_opb */ + divisor = (get_OPB_freq() - 1) / 10000000; + if (divisor == 0) + divisor = 1; + out_8(&i2c->clkdiv, divisor); + + /* no interrupts */ + out_8(&i2c->intrmsk, 0); + + /* clear transfer count */ + out_8(&i2c->xfrcnt, 0); + + /* clear extended control & stat */ + /* write 1 in SRC SRS SWC SWS to clear these fields */ + out_8(&i2c->xtcntlss, 0xF0); + + /* Mode Control Register + Flush Slave/Master data buffer */ + out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); + + val = in_8(&i2c->mdcntl); + + /* Ignore General Call, slave transfers are ignored, + * disable interrupts, exit unknown bus state, enable hold + * SCL 100kHz normaly or FastMode for 400kHz and above + */ + + val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL; + if (speed >= 400000) + val |= IIC_MDCNTL_FSM; + out_8(&i2c->mdcntl, val); + + /* clear control reg */ + out_8(&i2c->cntl, 0x00); + } + + /* set to SPD bus as default bus upon powerup */ + I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); +} + +/* + * This code tries to use the features of the 405GP i2c + * controller. It will transfer up to 4 bytes in one pass + * on the loop. It only does out_8((u8 *)lbz) to the buffer when it + * is possible to do out16(lhz) transfers. + * + * cmd_type is 0 for write 1 for read. + * + * addr_len can take any value from 0-255, it is only limited + * by the char, we could make it larger if needed. If it is + * 0 we skip the address write cycle. + * + * Typical case is a Write of an addr followd by a Read. The + * IBM FAQ does not cover this. On the last byte of the write + * we don't set the creg CHT bit, and on the first bytes of the + * read we set the RPST bit. + * + * It does not support address only transfers, there must be + * a data part. If you want to write the address yourself, put + * it in the data pointer. + * + * It does not support transfer to/from address 0. + * + * It does not check XFRCNT. + */ +static int i2c_transfer(unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len) +{ + struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR; + u8 *ptr; + int reading; + int tran, cnt; + int result; + int status; + int i; + u8 creg; + + if (data == 0 || data_len == 0) { + /* Don't support data transfer of no length or to address 0 */ + printf( "i2c_transfer: bad call\n" ); + return IIC_NOK; + } + if (addr && addr_len) { + ptr = addr; + cnt = addr_len; + reading = 0; + } else { + ptr = data; + cnt = data_len; + reading = cmd_type; + } + + /* Clear Stop Complete Bit */ + out_8(&i2c->sts, IIC_STS_SCMP); + + /* Check init */ + i = 10; + do { + /* Get status */ + status = in_8(&i2c->sts); + i--; + } while ((status & IIC_STS_PT) && (i > 0)); + + if (status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + return(result); + } + + /* flush the Master/Slave Databuffers */ + out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) | + IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB); + + /* need to wait 4 OPB clocks? code below should take that long */ + + /* 7-bit adressing */ + out_8(&i2c->hmadr, 0); + out_8(&i2c->lmadr, chip); + + tran = 0; + result = IIC_OK; + creg = 0; + + while (tran != cnt && (result == IIC_OK)) { + int bc,j; + + /* + * Control register = + * Normal transfer, 7-bits adressing, Transfer up to + * bc bytes, Normal start, Transfer is a sequence of transfers + */ + creg |= IIC_CNTL_PT; + + bc = (cnt - tran) > 4 ? 4 : cnt - tran; + creg |= (bc - 1) << 4; + /* if the real cmd type is write continue trans */ + if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) + creg |= IIC_CNTL_CHT; + + if (reading) { + creg |= IIC_CNTL_READ; + } else { + for(j = 0; j < bc; j++) { + /* Set buffer */ + out_8(&i2c->mdbuf, ptr[tran + j]); + } + } + out_8(&i2c->cntl, creg); + + /* + * Transfer is in progress + * we have to wait for upto 5 bytes of data + * 1 byte chip address+r/w bit then bc bytes + * of data. + * udelay(10) is 1 bit time at 100khz + * Doubled for slop. 20 is too small. + */ + i = 2 * 5 * 8; + do { + /* Get status */ + status = in_8(&i2c->sts); + udelay(10); + i--; + } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && + (i > 0)); + + if (status & IIC_STS_ERR) { + result = IIC_NOK; + status = in_8(&i2c->extsts); + /* Lost arbitration? */ + if (status & IIC_EXTSTS_LA) + result = IIC_NOK_LA; + /* Incomplete transfer? */ + if (status & IIC_EXTSTS_ICT) + result = IIC_NOK_ICT; + /* Transfer aborted? */ + if (status & IIC_EXTSTS_XFRA) + result = IIC_NOK_XFRA; + } else if ( status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + } + + /* Command is reading => get buffer */ + if ((reading) && (result == IIC_OK)) { + /* Are there data in buffer */ + if (status & IIC_STS_MDBS) { + /* + * even if we have data we have to wait 4OPB + * clocks for it to hit the front of the FIFO, + * after that we can just read. We should check + * XFCNT here and if the FIFO is full there is + * no need to wait. + */ + udelay(1); + for (j = 0; j < bc; j++) + ptr[tran + j] = in_8(&i2c->mdbuf); + } else + result = IIC_NOK_DATA; + } + creg = 0; + tran += bc; + if (ptr == addr && tran == cnt) { + ptr = data; + cnt = data_len; + tran = 0; + reading = cmd_type; + if (reading) + creg = IIC_CNTL_RPST; + } + } + return result; +} + +int i2c_probe(uchar chip) +{ + uchar buf[1]; + + buf[0] = 0; + + /* + * What is needed is to send the chip address and verify that the + * address was ed (i.e. there was a chip at that address which + * drove the data line low). + */ + return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0); +} + +static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, + int len, int read) +{ + uchar xaddr[4]; + int ret; + + if (alen > 4) { + printf("I2C: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + + +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen, + buffer, len)) != 0) { + if (gd->have_console) { + printf("I2C %s: failed %d\n", + read ? "read" : "write", ret); + } + + return 1; + } + + return 0; +} + +int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1); +} + +int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0); +} + +#if defined(CONFIG_I2C_MULTI_BUS) +/* + * Functions for multiple I2C bus handling + */ +unsigned int i2c_get_bus_num(void) +{ + return i2c_bus_num; +} + +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= CONFIG_SYS_MAX_I2C_BUS) + return -1; + + i2c_bus_num = bus; + + return 0; +} +#endif /* CONFIG_I2C_MULTI_BUS */ +#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c index 1b20a76c4c..8d0b6d6042 100644 --- a/drivers/input/ps2ser.c +++ b/drivers/input/ps2ser.c @@ -36,8 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PSC_BASE MPC5XXX_PSC2 #elif CONFIG_PS2SERIAL == 3 #define PSC_BASE MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PS2SERIAL must be in 1, 2 or 3 #elif CONFIG_PS2SERIAL == 4 #define PSC_BASE MPC5XXX_PSC4 #elif CONFIG_PS2SERIAL == 5 @@ -87,23 +85,14 @@ int ps2ser_init(void) psc->command = PSC_SEL_MODE_REG_1; /* select clock sources */ -#if defined(CONFIG_MGT5100) - psc->psc_clock_select = 0xdd00; - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) psc->psc_clock_select = 0; baseclk = (gd->ipb_clk + 16) / 32; -#endif /* switch to UART mode */ psc->sicr = 0; /* configure parity, bit length and so on */ -#if defined(CONFIG_MGT5100) - psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#elif defined(CONFIG_MPC5200) psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#endif psc->mode = PSC_MODE_ONE_STOP; /* set up UART divisor */ diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 287e555900..8255175d2a 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1012) || defined(CONFIG_P1021) || \ + defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 #elif defined(CONFIG_PPC_P4080) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e665b5ebd8..0f6f8b161c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, Freescale Semiconductor, Inc + * Copyright 2007,2010 Freescale Semiconductor, Inc * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -110,8 +110,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) if (wml_value > 0x10) wml_value = 0x10; - wml_value = 0x100000 | wml_value; - + esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); esdhc_write32(®s->dsaddr, (u32)data->dest); } else { if (wml_value > 0x80) @@ -120,12 +119,12 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return TIMEOUT; } - wml_value = wml_value << 16 | 0x10; + + esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, + wml_value << 16); esdhc_write32(®s->dsaddr, (u32)data->src); } - esdhc_write32(®s->wml, wml_value); - esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); /* Calculate the timeout period for data transactions */ @@ -265,18 +264,13 @@ void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); - /* On imx the clock must be stopped before changing frequency */ - if (cfg->clk_enable) - esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); + esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); udelay(10000); - clk = SYSCTL_PEREN; - /* On imx systems the clock must be explicitely enabled */ - if (cfg->clk_enable) - clk |= SYSCTL_CKEN; + clk = SYSCTL_PEREN | SYSCTL_CKEN; esdhc_setbits32(®s->sysctl, clk); } @@ -349,6 +343,20 @@ static int esdhc_init(struct mmc *mmc) return ret; } +static void esdhc_reset(struct fsl_esdhc *regs) +{ + unsigned long timeout = 100; /* wait max 100 ms */ + + /* reset the controller */ + esdhc_write32(®s->sysctl, SYSCTL_RSTA); + + /* hardware clears the bit when it is done */ + while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) + udelay(1000); + if (!timeout) + printf("MMC/SD: Reset never completed.\n"); +} + int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) { struct fsl_esdhc *regs; @@ -363,6 +371,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) sprintf(mmc->name, "FSL_ESDHC"); regs = (struct fsl_esdhc *)cfg->esdhc_base; + /* First reset the eSDHC controller */ + esdhc_reset(regs); + mmc->priv = cfg; mmc->send_cmd = esdhc_send_cmd; mmc->set_ios = esdhc_set_ios; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index fdba297c88..3267c5de36 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -537,10 +537,14 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, ulong start; #if CONFIG_SYS_HZ != 1000 - tout *= CONFIG_SYS_HZ/1000; + if ((ulong)CONFIG_SYS_HZ > 100000) + tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ + else + tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); #endif /* Wait for command completion */ + reset_timer(); start = get_timer (0); while (flash_is_busy (info, sector)) { if (get_timer (start) > tout) { @@ -602,6 +606,64 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, return retcode; } +static int use_flash_status_poll(flash_info_t *info) +{ +#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL + if (info->vendor == CFI_CMDSET_AMD_EXTENDED || + info->vendor == CFI_CMDSET_AMD_STANDARD) + return 1; +#endif + return 0; +} + +static int flash_status_poll(flash_info_t *info, void *src, void *dst, + ulong tout, char *prompt) +{ +#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL + ulong start; + int ready; + +#if CONFIG_SYS_HZ != 1000 + if ((ulong)CONFIG_SYS_HZ > 100000) + tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ + else + tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); +#endif + + /* Wait for command completion */ + reset_timer(); + start = get_timer(0); + while (1) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + ready = flash_read8(dst) == flash_read8(src); + break; + case FLASH_CFI_16BIT: + ready = flash_read16(dst) == flash_read16(src); + break; + case FLASH_CFI_32BIT: + ready = flash_read32(dst) == flash_read32(src); + break; + case FLASH_CFI_64BIT: + ready = flash_read64(dst) == flash_read64(src); + break; + default: + ready = 0; + break; + } + if (ready) + break; + if (get_timer(start) > tout) { + printf("Flash %s timeout at address %lx data %lx\n", + prompt, (ulong)dst, (ulong)flash_read8(dst)); + return ERR_TIMOUT; + } + udelay(1); /* also triggers watchdog */ + } +#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ + return ERR_OK; +} + /*----------------------------------------------------------------------- */ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) @@ -749,7 +811,12 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, if (!sect_found) sect = find_sector (info, dest); - return flash_full_status_check (info, sect, info->write_tout, "write"); + if (use_flash_status_poll(info)) + return flash_status_poll(info, &cword, dstaddr, + info->write_tout, "write"); + else + return flash_full_status_check(info, sect, + info->write_tout, "write"); } #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE @@ -911,9 +978,15 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, } flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check (info, sector, - info->buffer_write_tout, - "buffer write"); + if (use_flash_status_poll(info)) + retcode = flash_status_poll(info, src - (1 << shift), + dst - (1 << shift), + info->buffer_write_tout, + "buffer write"); + else + retcode = flash_full_status_check(info, sector, + info->buffer_write_tout, + "buffer write"); break; default: @@ -935,6 +1008,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int rcode = 0; int prot; flash_sect_t sect; + int st; if (info->flash_id != FLASH_MAN_CFI) { puts ("Can't erase unknown flash type - aborted\n"); @@ -998,10 +1072,20 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) break; } - if (flash_full_status_check - (info, sect, info->erase_blk_tout, "erase")) { + if (use_flash_status_poll(info)) { + cfiword_t cword = (cfiword_t)0xffffffffffffffffULL; + void *dest; + dest = flash_map(info, sect, 0); + st = flash_status_poll(info, &cword, dest, + info->erase_blk_tout, "erase"); + flash_unmap(info, sect, 0, dest); + } else + st = flash_full_status_check(info, sect, + info->erase_blk_tout, + "erase"); + if (st) rcode = 1; - } else if (flash_verbose) + else if (flash_verbose) putc ('.'); } } diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 40002be417..d5eb54ad84 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -31,6 +31,209 @@ #include +#ifdef CONFIG_ATMEL_NAND_HWECC + +/* Register access macros */ +#define ecc_readl(add, reg) \ + readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg) +#define ecc_writel(add, reg, value) \ + writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg) + +#include "atmel_nand_ecc.h" /* Hardware ECC registers */ + +/* oob layout for large page size + * bad block info is on bytes 0 and 1 + * the bytes have to be consecutives to avoid + * several NAND_CMD_RNDOUT during read + */ +static struct nand_ecclayout atmel_oobinfo_large = { + .eccbytes = 4, + .eccpos = {60, 61, 62, 63}, + .oobfree = { + {2, 58} + }, +}; + +/* oob layout for small page size + * bad block info is on bytes 4 and 5 + * the bytes have to be consecutives to avoid + * several NAND_CMD_RNDOUT during read + */ +static struct nand_ecclayout atmel_oobinfo_small = { + .eccbytes = 4, + .eccpos = {0, 1, 2, 3}, + .oobfree = { + {6, 10} + }, +}; + +/* + * Calculate HW ECC + * + * function called after a write + * + * mtd: MTD block structure + * dat: raw data (unused) + * ecc_code: buffer for ECC + */ +static int atmel_nand_calculate(struct mtd_info *mtd, + const u_char *dat, unsigned char *ecc_code) +{ + struct nand_chip *nand_chip = mtd->priv; + unsigned int ecc_value; + + /* get the first 2 ECC bytes */ + ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR); + + ecc_code[0] = ecc_value & 0xFF; + ecc_code[1] = (ecc_value >> 8) & 0xFF; + + /* get the last 2 ECC bytes */ + ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY; + + ecc_code[2] = ecc_value & 0xFF; + ecc_code[3] = (ecc_value >> 8) & 0xFF; + + return 0; +} + +/* + * HW ECC read page function + * + * mtd: mtd info structure + * chip: nand chip info structure + * buf: buffer to store read data + */ +static int atmel_nand_read_page(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int page) +{ + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + uint32_t *eccpos = chip->ecc.layout->eccpos; + uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + uint8_t *ecc_pos; + int stat; + + /* read the page */ + chip->read_buf(mtd, p, eccsize); + + /* move to ECC position if needed */ + if (eccpos[0] != 0) { + /* This only works on large pages + * because the ECC controller waits for + * NAND_CMD_RNDOUTSTART after the + * NAND_CMD_RNDOUT. + * anyway, for small pages, the eccpos[0] == 0 + */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, + mtd->writesize + eccpos[0], -1); + } + + /* the ECC controller needs to read the ECC just after the data */ + ecc_pos = oob + eccpos[0]; + chip->read_buf(mtd, ecc_pos, eccbytes); + + /* check if there's an error */ + stat = chip->ecc.correct(mtd, p, oob, NULL); + + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + + /* get back to oob start (end of page) */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); + + /* read the oob */ + chip->read_buf(mtd, oob, mtd->oobsize); + + return 0; +} + +/* + * HW ECC Correction + * + * function called after a read + * + * mtd: MTD block structure + * dat: raw data read from the chip + * read_ecc: ECC from the chip (unused) + * isnull: unused + * + * Detect and correct a 1 bit error for a page + */ +static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *isnull) +{ + struct nand_chip *nand_chip = mtd->priv; + unsigned int ecc_status, ecc_parity, ecc_mode; + unsigned int ecc_word, ecc_bit; + + /* get the status from the Status Register */ + ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR); + + /* if there's no error */ + if (likely(!(ecc_status & ATMEL_ECC_RECERR))) + return 0; + + /* get error bit offset (4 bits) */ + ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR; + /* get word address (12 bits) */ + ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR; + ecc_word >>= 4; + + /* if there are multiple errors */ + if (ecc_status & ATMEL_ECC_MULERR) { + /* check if it is a freshly erased block + * (filled with 0xff) */ + if ((ecc_bit == ATMEL_ECC_BITADDR) + && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) { + /* the block has just been erased, return OK */ + return 0; + } + /* it doesn't seems to be a freshly + * erased block. + * We can't correct so many errors */ + printk(KERN_WARNING "atmel_nand : multiple errors detected." + " Unable to correct.\n"); + return -EIO; + } + + /* if there's a single bit error : we can correct it */ + if (ecc_status & ATMEL_ECC_ECCERR) { + /* there's nothing much to do here. + * the bit error is on the ECC itself. + */ + printk(KERN_WARNING "atmel_nand : one bit error on ECC code." + " Nothing to correct\n"); + return 0; + } + + printk(KERN_WARNING "atmel_nand : one bit error on data." + " (word offset in the page :" + " 0x%x bit offset : 0x%x)\n", + ecc_word, ecc_bit); + /* correct the error */ + if (nand_chip->options & NAND_BUSWIDTH_16) { + /* 16 bits words */ + ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit); + } else { + /* 8 bits words */ + dat[ecc_word] ^= (1 << ecc_bit); + } + printk(KERN_WARNING "atmel_nand : error corrected\n"); + return 1; +} + +/* + * Enable HW ECC : unused on most chips + */ +static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) +{ +} +#endif + static void at91_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { @@ -64,6 +267,11 @@ static int at91_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { +#ifdef CONFIG_ATMEL_NAND_HWECC + static int chip_nr = 0; + struct mtd_info *mtd; +#endif + nand->ecc.mode = NAND_ECC_SOFT; #ifdef CONFIG_SYS_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; @@ -74,5 +282,62 @@ int board_nand_init(struct nand_chip *nand) #endif nand->chip_delay = 20; +#ifdef CONFIG_ATMEL_NAND_HWECC + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.calculate = atmel_nand_calculate; + nand->ecc.correct = atmel_nand_correct; + nand->ecc.hwctl = atmel_nand_hwctl; + nand->ecc.read_page = atmel_nand_read_page; + nand->ecc.bytes = 4; +#endif + +#ifdef CONFIG_ATMEL_NAND_HWECC + mtd = &nand_info[chip_nr++]; + mtd->priv = nand; + + /* Detect NAND chips */ + if (nand_scan_ident(mtd, 1)) { + printk(KERN_WARNING "NAND Flash not found !\n"); + return -ENXIO; + } + + if (nand->ecc.mode == NAND_ECC_HW) { + /* ECC is calculated for the whole page (1 step) */ + nand->ecc.size = mtd->writesize; + + /* set ECC page size and oob layout */ + switch (mtd->writesize) { + case 512: + nand->ecc.layout = &atmel_oobinfo_small; + ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_528); + break; + case 1024: + nand->ecc.layout = &atmel_oobinfo_large; + ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_1056); + break; + case 2048: + nand->ecc.layout = &atmel_oobinfo_large; + ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_2112); + break; + case 4096: + nand->ecc.layout = &atmel_oobinfo_large; + ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_4224); + break; + default: + /* page size not handled by HW ECC */ + /* switching back to soft ECC */ + nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.calculate = NULL; + nand->ecc.correct = NULL; + nand->ecc.hwctl = NULL; + nand->ecc.read_page = NULL; + nand->ecc.postpad = 0; + nand->ecc.prepad = 0; + nand->ecc.bytes = 0; + break; + } + } +#endif + return 0; } diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h new file mode 100644 index 0000000000..1ee7f993db --- /dev/null +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -0,0 +1,36 @@ +/* + * Error Corrected Code Controller (ECC) - System peripherals regsters. + * Based on AT91SAM9260 datasheet revision B. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef ATMEL_NAND_ECC_H +#define ATMEL_NAND_ECC_H + +#define ATMEL_ECC_CR 0x00 /* Control register */ +#define ATMEL_ECC_RST (1 << 0) /* Reset parity */ + +#define ATMEL_ECC_MR 0x04 /* Mode register */ +#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */ +#define ATMEL_ECC_PAGESIZE_528 (0) +#define ATMEL_ECC_PAGESIZE_1056 (1) +#define ATMEL_ECC_PAGESIZE_2112 (2) +#define ATMEL_ECC_PAGESIZE_4224 (3) + +#define ATMEL_ECC_SR 0x08 /* Status register */ +#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */ +#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ +#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */ + +#define ATMEL_ECC_PR 0x0c /* Parity register */ +#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */ +#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ + +#define ATMEL_ECC_NPR 0x10 /* NParity register */ +#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */ + +#endif diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index bfc2acf59e..4ca738e451 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -57,8 +57,6 @@ #define ECC_STATE_ERR_CORR_COMP_P 0x2 #define ECC_STATE_ERR_CORR_COMP_N 0x3 -static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE; - /* * Exploit the little endianness of the ARM to do multi-byte transfers * per device read. This can perform over twice as quickly as individual @@ -93,7 +91,7 @@ static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) /* copy aligned data */ while (len >= 4) { - *(u32 *)buf = readl(nand); + *(u32 *)buf = __raw_readl(nand); buf += 4; len -= 4; } @@ -138,7 +136,7 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf, /* copy aligned data */ while (len >= 4) { - writel(*(u32 *)buf, nand); + __raw_writel(*(u32 *)buf, nand); buf += 4; len -= 4; } @@ -156,7 +154,8 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf, } } -static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) { struct nand_chip *this = mtd->priv; u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; @@ -164,9 +163,9 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c if (ctrl & NAND_CTRL_CHANGE) { IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - if ( ctrl & NAND_CLE ) + if (ctrl & NAND_CLE) IO_ADDR_W |= MASK_CLE; - if ( ctrl & NAND_ALE ) + if (ctrl & NAND_ALE) IO_ADDR_W |= MASK_ALE; this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; } @@ -181,24 +180,26 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { u_int32_t val; - (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); + (void)__raw_readl(&(davinci_emif_regs->nandfecc[ + CONFIG_SYS_NAND_CS - 2])); - val = readl(&emif_regs->NANDFCR); + val = __raw_readl(&davinci_emif_regs->nandfcr); val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); - writel(val, &emif_regs->NANDFCR); + __raw_writel(val, &davinci_emif_regs->nandfcr); } static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) { u_int32_t ecc = 0; - ecc = readl(&(emif_regs->NANDFECC[region - 1])); + ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1])); - return(ecc); + return ecc; } -static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) { u_int32_t tmp; const int region = 1; @@ -232,7 +233,8 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u return 0; } -static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) { struct nand_chip *this = mtd->priv; u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | @@ -268,7 +270,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char * return -1; } } - return(0); + return 0; } #endif /* CONFIG_SYS_NAND_HW_ECC */ @@ -315,15 +317,15 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) * Start a new ECC calculation for reading or writing 512 bytes * of data. */ - val = readl(&emif_regs->NANDFCR); + val = __raw_readl(&davinci_emif_regs->nandfcr); val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_4BIT_ECC_START; - writel(val, &emif_regs->NANDFCR); + __raw_writel(val, &davinci_emif_regs->nandfcr); break; case NAND_ECC_READSYN: - val = emif_regs->NAND4BITECC1; + val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]); break; default: break; @@ -332,10 +334,12 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4]) { - ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK; - ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK; - ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK; - ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK; + int i; + + for (i = 0; i < 4; i++) { + ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) & + NAND_4BITECC_MASK; + } return 0; } @@ -418,32 +422,36 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, */ /*Take 2 bits from 8th byte and 8 bits from 9th byte */ - writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD); + __raw_writel(((ecc16[4]) >> 6) & 0x3FF, + &davinci_emif_regs->nand4biteccload); /* Take 4 bits from 7th byte and 6 bits from 8th byte */ - writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0), - &emif_regs->NAND4BITECCLOAD); + __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0), + &davinci_emif_regs->nand4biteccload); /* Take 6 bits from 6th byte and 4 bits from 7th byte */ - writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD); + __raw_writel((ecc16[3] >> 2) & 0x3FF, + &davinci_emif_regs->nand4biteccload); /* Take 8 bits from 5th byte and 2 bits from 6th byte */ - writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300), - &emif_regs->NAND4BITECCLOAD); + __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300), + &davinci_emif_regs->nand4biteccload); /*Take 2 bits from 3rd byte and 8 bits from 4th byte */ - writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC), - &emif_regs->NAND4BITECCLOAD); + __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC), + &davinci_emif_regs->nand4biteccload); /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */ - writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD); + __raw_writel(((ecc16[1]) >> 4) & 0x3FF, + &davinci_emif_regs->nand4biteccload); /* Take 6 bits from 1st byte and 4 bits from 2nd byte */ - writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0), - &emif_regs->NAND4BITECCLOAD); + __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0), + &davinci_emif_regs->nand4biteccload); /* Take 10 bits from 0th and 1st bytes */ - writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD); + __raw_writel((ecc16[0]) & 0x3FF, + &davinci_emif_regs->nand4biteccload); /* * Perform a dummy read to the EMIF Revision Code and Status register. @@ -451,7 +459,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, * writing the ECC values in previous step. */ - val = emif_regs->NANDFSR; + val = __raw_readl(&davinci_emif_regs->nandfsr); /* * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers. @@ -467,13 +475,13 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, * Clear any previous address calculation by doing a dummy read of an * error address register. */ - val = emif_regs->NANDERRADD1; + val = __raw_readl(&davinci_emif_regs->nanderradd1); /* * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control * register to 1. */ - emif_regs->NANDFCR |= 1 << 13; + __raw_writel(1 << 13, &davinci_emif_regs->nandfcr); /* * Wait for the corr_state field (bits 8 to 11)in the @@ -481,12 +489,12 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, */ i = NAND_TIMEOUT; do { - val = emif_regs->NANDFSR; + val = __raw_readl(&davinci_emif_regs->nandfsr); val &= 0xc00; i--; } while ((i > 0) && val); - iserror = emif_regs->NANDFSR; + iserror = __raw_readl(&davinci_emif_regs->nandfsr); iserror &= EMIF_NANDFSR_ECC_STATE_MASK; iserror = iserror >> 8; @@ -501,32 +509,33 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, */ if (iserror == ECC_STATE_NO_ERR) { - val = emif_regs->NANDERRVAL1; + val = __raw_readl(&davinci_emif_regs->nanderrval1); return 0; } else if (iserror == ECC_STATE_TOO_MANY_ERRS) { - val = emif_regs->NANDERRVAL1; + val = __raw_readl(&davinci_emif_regs->nanderrval1); return -1; } - numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1; + numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16) + & 0x3) + 1; /* Read the error address, error value and correct */ for (i = 0; i < numerrors; i++) { if (i > 1) { erroraddress = - ((emif_regs->NANDERRADD2 >> + ((__raw_readl(&davinci_emif_regs->nanderradd2) >> (16 * (i & 1))) & 0x3FF); erroraddress = ((512 + 7) - erroraddress); errorvalue = - ((emif_regs->NANDERRVAL2 >> + ((__raw_readl(&davinci_emif_regs->nanderrval2) >> (16 * (i & 1))) & 0xFF); } else { erroraddress = - ((emif_regs->NANDERRADD1 >> + ((__raw_readl(&davinci_emif_regs->nanderradd1) >> (16 * (i & 1))) & 0x3FF); erroraddress = ((512 + 7) - erroraddress); errorvalue = - ((emif_regs->NANDERRVAL1 >> + ((__raw_readl(&davinci_emif_regs->nanderrval1) >> (16 * (i & 1))) & 0xFF); } /* xor the corrupt data with error value */ @@ -540,7 +549,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, static int nand_davinci_dev_ready(struct mtd_info *mtd) { - return emif_regs->NANDFSR & 0x1; + return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1; } static void nand_flash_init(void) @@ -561,21 +570,22 @@ static void nand_flash_init(void) * * *------------------------------------------------------------------*/ acfg1 = 0 - | (0 << 31 ) /* selectStrobe */ - | (0 << 30 ) /* extWait */ - | (1 << 26 ) /* writeSetup 10 ns */ - | (3 << 20 ) /* writeStrobe 40 ns */ - | (1 << 17 ) /* writeHold 10 ns */ - | (1 << 13 ) /* readSetup 10 ns */ - | (5 << 7 ) /* readStrobe 60 ns */ - | (1 << 4 ) /* readHold 10 ns */ - | (3 << 2 ) /* turnAround ?? ns */ - | (0 << 0 ) /* asyncSize 8-bit bus */ + | (0 << 31) /* selectStrobe */ + | (0 << 30) /* extWait */ + | (1 << 26) /* writeSetup 10 ns */ + | (3 << 20) /* writeStrobe 40 ns */ + | (1 << 17) /* writeHold 10 ns */ + | (1 << 13) /* readSetup 10 ns */ + | (5 << 7) /* readStrobe 60 ns */ + | (1 << 4) /* readHold 10 ns */ + | (3 << 2) /* turnAround ?? ns */ + | (0 << 0) /* asyncSize 8-bit bus */ ; - emif_regs->AB1CR = acfg1; /* CS2 */ + __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */ - emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */ + /* NAND flash on CS2 */ + __raw_writel(0x00000101, &davinci_emif_regs->nandfcr); #endif } diff --git a/drivers/mtd/spi/eeprom_m95xxx.c b/drivers/mtd/spi/eeprom_m95xxx.c index 0148d005e9..632db4e9e0 100644 --- a/drivers/mtd/spi/eeprom_m95xxx.c +++ b/drivers/mtd/spi/eeprom_m95xxx.c @@ -44,6 +44,9 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000, CONFIG_DEFAULT_SPI_MODE); + if(!slave) + return 0; + spi_claim_bus(slave); /* command */ @@ -75,6 +78,9 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000, CONFIG_DEFAULT_SPI_MODE); + if (!slave) + return 0; + spi_claim_bus(slave); buf[0] = SPI_EEPROM_WREN; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 5af9cdba2a..8c4ade5ab5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -752,7 +752,6 @@ static int fec_probe(bd_t *bd) if (fec_get_hwaddr(edev, ethaddr) == 0) { printf("got MAC address from EEPROM: %pM\n", ethaddr); memcpy(edev->enetaddr, ethaddr, 6); - fec_set_hwaddr(edev); } return 0; diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index 1876b7684b..c2b1bbdc7b 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -336,13 +336,11 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) */ fec->eth->xmit_fsm = 0x03000000; -#if defined(CONFIG_MPC5200) /* - * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't + * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't * work w/ the current receive task. */ sdma->PtdCntrl |= 0x00000001; -#endif /* * Set priority of different initiators @@ -579,9 +577,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) /********************************************************************/ static void mpc5xxx_fec_halt(struct eth_device *dev) { -#if defined(CONFIG_MPC5200) struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; -#endif mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; int counter = 0xffff; @@ -611,13 +607,11 @@ static void mpc5xxx_fec_halt(struct eth_device *dev) SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); -#if defined(CONFIG_MPC5200) /* - * Turn on COMM bus prefetch in the MGT5200 BestComm after we're + * Turn on COMM bus prefetch in the MPC5200 BestComm after we're * done. It doesn't work w/ the current receive task. */ sdma->PtdCntrl &= ~0x00000001; -#endif /* * Disable the Ethernet Controller diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index fe57926d7e..5a63fa2168 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -1,9 +1,10 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -513,10 +514,15 @@ void ft_fsl_pci_setup(void *blob, const char *pci_alias, struct pci_controller *hose) { int off = fdt_path_offset(blob, pci_alias); + u32 bus_range[2]; - if (off >= 0) { - u32 bus_range[2]; + if (off < 0) + return; + /* We assume a cfg_addr not being set means we didn't setup the controller */ + if ((hose == NULL) || (hose->cfg_addr == NULL)) { + fdt_del_node_and_alias(blob, pci_alias); + } else { bus_range[0] = 0; bus_range[1] = hose->last_busno - hose->first_busno; fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); diff --git a/drivers/pci/pci_sh4.c b/drivers/pci/pci_sh4.c index c7963ed8a8..62915b6df9 100644 --- a/drivers/pci/pci_sh4.c +++ b/drivers/pci/pci_sh4.c @@ -4,7 +4,7 @@ * (C) 2007,2008 Nobuhiro Iwamatsu * (C) 2008 Yusuke Goda * - * u-boot/cpu/sh4/pci-sh4.c + * u-boot/arch/sh/cpu/sh4/pci-sh4.c * * See file CREDITS for list of people who contributed to this * project. diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index c4214d9a0a..c1cc23bfcd 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -47,7 +47,7 @@ /*--------------------------------------------------------------------+ * Fixed PHY (PHY-less) support for Ethernet Ports. * - * Copied from cpu/ppc4xx/4xx_enet.c + * Copied from arch/ppc/cpu/ppc4xx/4xx_enet.c *--------------------------------------------------------------------*/ /* diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 71392e6847..c731bfb594 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a +COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o +COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o +COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c new file mode 100644 index 0000000000..fb28aa9eb9 --- /dev/null +++ b/drivers/serial/altera_jtag_uart.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/*------------------------------------------------------------------ + * JTAG acts as the serial port + *-----------------------------------------------------------------*/ +static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE; + +void serial_setbrg( void ){ return; } +int serial_init( void ) { return(0);} + +void serial_putc (char c) +{ + while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0) + WATCHDOG_RESET (); + writel ((unsigned char)c, &jtag->data); +} + +void serial_puts (const char *s) +{ + while (*s != 0) + serial_putc (*s++); +} + +int serial_tstc (void) +{ + return ( readl (&jtag->control) & NIOS_JTAG_RRDY); +} + +int serial_getc (void) +{ + int c; + unsigned val; + + while (1) { + WATCHDOG_RESET (); + val = readl (&jtag->data); + if (val & NIOS_JTAG_RVALID) + break; + } + c = val & 0x0ff; + return (c); +} diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c new file mode 100644 index 0000000000..045f1197a3 --- /dev/null +++ b/drivers/serial/altera_uart.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/*------------------------------------------------------------------ + * UART the serial port + *-----------------------------------------------------------------*/ + +static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; + +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + +/* Everything's already setup for fixed-baud PTF + * assignment + */ +void serial_setbrg (void){ return; } +int serial_init (void) { return (0);} + +#else + +void serial_setbrg (void) +{ + unsigned div; + + div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; + writel (div, &uart->divisor); + return; +} + +int serial_init (void) +{ + serial_setbrg (); + return (0); +} + +#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ + +/*----------------------------------------------------------------------- + * UART CONSOLE + *---------------------------------------------------------------------*/ +void serial_putc (char c) +{ + if (c == '\n') + serial_putc ('\r'); + while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) + WATCHDOG_RESET (); + writel ((unsigned char)c, &uart->txdata); +} + +void serial_puts (const char *s) +{ + while (*s != 0) { + serial_putc (*s++); + } +} + +int serial_tstc (void) +{ + return (readl (&uart->status) & NIOS_UART_RRDY); +} + +int serial_getc (void) +{ + while (serial_tstc () == 0) + WATCHDOG_RESET (); + return (readl (&uart->rxdata) & 0x00ff ); +} diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index 0b531402e4..d93b24b897 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern void uart_port_conf(void); +extern void uart_port_conf(int port); int serial_init(void) { @@ -43,7 +43,7 @@ int serial_init(void) uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE); - uart_port_conf(); + uart_port_conf(CONFIG_SYS_UART_PORT); /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ uart->ucr = UART_UCR_RESET_RX; diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c new file mode 100644 index 0000000000..f18f7f444e --- /dev/null +++ b/drivers/serial/opencores_yanu.c @@ -0,0 +1,188 @@ +/* + * Copyright 2010, Renato Andreola + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/*-----------------------------------------------------------------*/ +/* YANU Imagos serial port */ +/*-----------------------------------------------------------------*/ + +static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; + +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + +/* Everything's already setup for fixed-baud PTF assignment*/ + +void serial_setbrg (void) +{ + int n, k; + const unsigned max_uns = 0xFFFFFFFF; + unsigned best_n, best_m, baud; + + /* compute best N and M couple */ + best_n = YANU_MAX_PRESCALER_N; + for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { + if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= + (unsigned)CONFIG_BAUDRATE) { + best_n = n; + break; + } + } + for (k = 0;; k++) { + if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k))) + break; + } + best_m = + ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) / + ((unsigned)CONFIG_SYS_CLK_FREQ >> k); + + baud = best_m + best_n * YANU_BAUDE; + writel(baud, &uart->baud); + + return; +} + +#else + +void serial_setbrg (void) +{ + int n, k; + const unsigned max_uns = 0xFFFFFFFF; + unsigned best_n, best_m, baud; + + /* compute best N and M couple */ + best_n = YANU_MAX_PRESCALER_N; + for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { + if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= + gd->baudrate) { + best_n = n; + break; + } + } + for (k = 0;; k++) { + if (gd->baudrate <= (max_uns >> (15+n-k))) + break; + } + best_m = + (gd->baudrate * (1 << (15 + n - k))) / + ((unsigned)CONFIG_SYS_CLK_FREQ >> k); + + baud = best_m + best_n * YANU_BAUDE; + writel(baud, &uart->baud); + + return; +} + + +#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ + +int serial_init (void) +{ + unsigned action,control; + + /* status register cleanup */ + action = YANU_ACTION_RRRDY | + YANU_ACTION_RTRDY | + YANU_ACTION_ROE | + YANU_ACTION_RBRK | + YANU_ACTION_RFE | + YANU_ACTION_RPE | + YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; + + writel(action, &uart->action); + + /* control register cleanup */ + /* no interrupts enabled */ + /* one stop bit */ + /* hardware flow control disabled */ + /* 8 bits */ + control = (0x7 << YANU_CONTROL_BITS_POS); + /* enven parity just to be clean */ + control |= YANU_CONTROL_PAREVEN; + /* we set threshold for fifo */ + control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY; + control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR; + + writel(control, &uart->control); + + /* to set baud rate */ + serial_setbrg(); + + return (0); +} + + +/*----------------------------------------------------------------------- + * YANU CONSOLE + *---------------------------------------------------------------------*/ +void serial_putc (char c) +{ + int tx_chars; + unsigned status; + + if (c == '\n') + serial_putc ('\r'); + + while (1) { + status = readl(&uart->status); + tx_chars = (status>>YANU_TFIFO_CHARS_POS) + & ((1<data); +} + +void serial_puts (const char *s) +{ + while (*s != 0) { + serial_putc (*s++); + } +} + + +int serial_tstc(void) +{ + unsigned status ; + + status = readl(&uart->status); + return (((status >> YANU_RFIFO_CHARS_POS) & + ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); +} + +int serial_getc (void) +{ + while (serial_tstc() == 0) + WATCHDOG_RESET (); + + /* first we pull the char */ + writel(YANU_ACTION_RFIFO_PULL, &uart->action); + + return(readl(&uart->data) & YANU_DATA_CHAR_MASK); +} diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index c4b36f06c0..687ffe6ace 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc. - * With help from the common/soft_spi and cpu/mpc8260 drivers + * With help from the common/soft_spi and arch/ppc/cpu/mpc8260 drivers * * See file CREDITS for list of people who contributed to this * project. diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 9ebeb4f23d..7784d92b6f 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -55,14 +55,14 @@ static struct descriptor { { 0x12, /* bLength */ 1, /* bDescriptorType: UDESC_DEVICE */ - 0x0002, /* bcdUSB: v2.0 */ + cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 9, /* bDeviceClass: UDCLASS_HUB */ 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 64, /* bMaxPacketSize: 64 bytes */ 0x0000, /* idVendor */ 0x0000, /* idProduct */ - 0x0001, /* bcdDevice */ + cpu_to_le16(0x0100), /* bcdDevice */ 1, /* iManufacturer */ 2, /* iProduct */ 0, /* iSerialNumber */ @@ -536,7 +536,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, uint32_t reg; uint32_t *status_reg; - if (le16_to_cpu(req->index) >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { + if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { printf("The request port(%d) is not configured\n", le16_to_cpu(req->index) - 1); return -1; @@ -630,19 +630,8 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, tmpbuf[0] |= USB_PORT_STAT_SUSPEND; if (reg & EHCI_PS_OCA) tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; - if (reg & EHCI_PS_PR && - (portreset & (1 << le16_to_cpu(req->index)))) { - int ret; - /* force reset to complete */ - reg = reg & ~(EHCI_PS_PR | EHCI_PS_CLEAR); - ehci_writel(status_reg, reg); - ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000); - if (!ret) - tmpbuf[0] |= USB_PORT_STAT_RESET; - else - printf("port(%d) reset error\n", - le16_to_cpu(req->index) - 1); - } + if (reg & EHCI_PS_PR) + tmpbuf[0] |= USB_PORT_STAT_RESET; if (reg & EHCI_PS_PP) tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; @@ -699,6 +688,8 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, ehci_writel(status_reg, reg); break; } else { + int ret; + reg |= EHCI_PS_PR; reg &= ~EHCI_PS_PE; ehci_writel(status_reg, reg); @@ -710,8 +701,19 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, wait_ms(50); /* terminate the reset */ ehci_writel(status_reg, reg & ~EHCI_PS_PR); - wait_ms(2); - portreset |= 1 << le16_to_cpu(req->index); + /* + * A host controller must terminate the reset + * and stabilize the state of the port within + * 2 milliseconds + */ + ret = handshake(status_reg, EHCI_PS_PR, 0, + 2 * 1000); + if (!ret) + portreset |= + 1 << le16_to_cpu(req->index); + else + printf("port(%d) reset error\n", + le16_to_cpu(req->index) - 1); } break; default: diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 441b1a2714..047902a0c1 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -28,6 +28,7 @@ #ifdef CONFIG_PCI_EHCI_DEVICE static struct pci_device_id ehci_pci_ids[] = { /* Please add supported PCI EHCI controller ids here */ + {0x1033, 0x00E0}, {0, 0} }; #endif diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c index 7aff54bce1..abdcbb4b22 100644 --- a/drivers/usb/host/isp116x-hcd.c +++ b/drivers/usb/host/isp116x-hcd.c @@ -42,7 +42,7 @@ * * [[GNU/GPL disclaimer]] * - * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c" + * and in part from AU1x00 OHCI HCD driver "u-boot/arch/mips/cpu/au1x00_usb_ohci.c" * (original copyright message follows): * * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00. diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 29f3ba186a..b2e03bc58b 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -25,11 +25,6 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -#ifndef CONFIG_AT91_LEGACY -#define CONFIG_AT91_LEGACY -#warning Please update to use C structur SoC access ! -#endif - #include #include #include @@ -37,22 +32,23 @@ int usb_cpu_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ defined(CONFIG_AT91SAM9261) /* Enable PLLB */ - at91_sys_write(AT91_CKGR_PLLBR, get_pllb_init()); - while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) + writel(get_pllb_init(), &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; #endif /* Enable USB host clock. */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP); + writel(1 << AT91_ID_UHP, &pmc->pcer); #ifdef CONFIG_AT91SAM9261 - at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0); + writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scer); #else - at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP); + writel(AT91_PMC_UHP, &pmc->scer); #endif return 0; @@ -60,19 +56,21 @@ int usb_cpu_init(void) int usb_cpu_stop(void) { + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; + /* Disable USB host clock. */ - at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP); + writel(1 << AT91_ID_UHP, &pmc->pcdr); #ifdef CONFIG_AT91SAM9261 - at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0); + writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr); #else - at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP); + writel(AT91_PMC_UHP, &pmc->scdr); #endif #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) /* Disable PLLB */ - at91_sys_write(AT91_CKGR_PLLBR, 0); - while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != 0) + writel(0, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) ; #endif diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c index 9ebb0b0c96..4a9bd07e01 100644 --- a/drivers/video/ati_radeon_fb.c +++ b/drivers/video/ati_radeon_fb.c @@ -210,7 +210,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo) * ToDo: identify these cases */ - DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n", + DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n", rinfo->video_ram / 1024, rinfo->vram_ddr ? "DDR" : "SDRAM", rinfo->vram_width); @@ -586,18 +586,21 @@ int radeon_probe(struct radeonfb_info *rinfo) rinfo->pdev.device = did; rinfo->family = get_radeon_id_family(rinfo->pdev.device); pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, - &rinfo->fb_base_phys); + &rinfo->fb_base_bus); pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, - &rinfo->mmio_base_phys); - rinfo->fb_base_phys &= 0xfffff000; - rinfo->mmio_base_phys &= ~0x04; + &rinfo->mmio_base_bus); + rinfo->fb_base_bus &= 0xfffff000; + rinfo->mmio_base_bus &= ~0x04; - rinfo->mmio_base = (void *)rinfo->mmio_base_phys; - DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base); + rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus, + PCI_REGION_MEM, 0, MAP_NOCACHE); + DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n", + rinfo->mmio_base, rinfo->mmio_base_bus); rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); /* PostBIOS with x86 emulater */ - BootVideoCardBIOS(pdev, NULL, 0); + if (!BootVideoCardBIOS(pdev, NULL, 0)) + return -1; /* * Check for errata @@ -610,14 +613,15 @@ int radeon_probe(struct radeonfb_info *rinfo) rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); - rinfo->fb_base = (void *)rinfo->fb_base_phys; - - DPRINT("Radeon: framebuffer base phy address 0x%08x," \ - "MMIO base phy address 0x%08x," \ - "framebuffer local base 0x%08x.\n ", - rinfo->fb_base_phys, rinfo->mmio_base_phys, - rinfo->fb_local_base); - + rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus, + PCI_REGION_MEM, 0, MAP_NOCACHE); + DPRINT("Radeon: framebuffer base address 0x%08x, " + "bus address 0x%08x\n" + "MMIO base address 0x%08x, bus address 0x%08x, " + "framebuffer local base 0x%08x.\n ", + (u32)rinfo->fb_base, rinfo->fb_base_bus, + (u32)rinfo->mmio_base, rinfo->mmio_base_bus, + rinfo->fb_local_base); return 0; } return -1; @@ -733,13 +737,13 @@ void *video_hw_init(void) } pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; - pGD->pciBase = rinfo->fb_base_phys; - pGD->frameAdrs = rinfo->fb_base_phys; + pGD->pciBase = (unsigned int)rinfo->fb_base; + pGD->frameAdrs = (unsigned int)rinfo->fb_base; pGD->memSize = 64 * 1024 * 1024; /* Cursor Start Address */ - pGD->dprBase = - (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys; + pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + + (unsigned int)rinfo->fb_base; if ((pGD->dprBase & 0x0fff) != 0) { /* allign it */ pGD->dprBase &= 0xfffff000; @@ -747,8 +751,8 @@ void *video_hw_init(void) } DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, PATTERN_ADR); - pGD->vprBase = rinfo->fb_base_phys; /* Dummy */ - pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ + pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */ + pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */ /* set up Hardware */ /* Clear video memory (only visible screen area) */ diff --git a/drivers/video/ati_radeon_fb.h b/drivers/video/ati_radeon_fb.h index e981f95246..065904555f 100644 --- a/drivers/video/ati_radeon_fb.h +++ b/drivers/video/ati_radeon_fb.h @@ -49,8 +49,8 @@ struct radeonfb_info { struct pci_device_id pdev; u16 family; - u32 fb_base_phys; - u32 mmio_base_phys; + u32 fb_base_bus; + u32 mmio_base_bus; void *mmio_base; void *fb_base; diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 49f0a2e040..d1f47c9157 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -802,9 +802,194 @@ static void inline fill_555rgb_pswap(uchar *fb, int x, } #endif +/* + * RLE8 bitmap support + */ + +#ifdef CONFIG_VIDEO_BMP_RLE8 +/* Pre-calculated color table entry */ +struct palette { + union { + unsigned short w; /* word */ + unsigned int dw; /* double word */ + } ce; /* color entry */ +}; + +/* + * Helper to draw encoded/unencoded run. + */ +static void draw_bitmap (uchar **fb, uchar *bm, struct palette *p, + int cnt, int enc) +{ + ulong addr = (ulong)*fb; + int *off; + int enc_off = 1; + int i; + + /* + * Setup offset of the color index in the bitmap. + * Color index of encoded run is at offset 1. + */ + off = enc ? &enc_off : &i; + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + for (i = 0; i < cnt; i++) + *(unsigned char *)addr++ = bm[*off]; + break; + case GDF_15BIT_555RGB: + case GDF_16BIT_565RGB: + /* differences handled while pre-calculating palette */ + for (i = 0; i < cnt; i++) { + *(unsigned short *)addr = p[bm[*off]].ce.w; + addr += 2; + } + break; + case GDF_32BIT_X888RGB: + for (i = 0; i < cnt; i++) { + *(unsigned long *)addr = p[bm[*off]].ce.dw; + addr += 4; + } + break; + } + *fb = (uchar *)addr; /* return modified address */ +} + +static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, + int width, int height) +{ + unsigned char *bm; + unsigned char *fbp; + unsigned int cnt, runlen; + int decode = 1; + int x, y, bpp, i, ncolors; + struct palette p[256]; + bmp_color_table_entry_t cte; + int green_shift, red_off; + + x = 0; + y = __le32_to_cpu(img->header.height) - 1; + ncolors = __le32_to_cpu(img->header.colors_used); + bpp = VIDEO_PIXEL_SIZE; + fbp = (unsigned char *)((unsigned int)video_fb_address + + (((y + yoff) * VIDEO_COLS) + xoff) * bpp); + + bm = (uchar *)img + __le32_to_cpu(img->header.data_offset); + + /* pre-calculate and setup palette */ + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + video_set_lut (i, cte.red, cte.green, cte.blue); + } + break; + case GDF_15BIT_555RGB: + case GDF_16BIT_565RGB: + if (VIDEO_DATA_FORMAT == GDF_15BIT_555RGB) { + green_shift = 3; + red_off = 10; + } else { + green_shift = 2; + red_off = 11; + } + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + p[i].ce.w = SWAP16((unsigned short) + (((cte.red >> 3) << red_off) | + ((cte.green >> green_shift) << 5) | + cte.blue >> 3)); + } + break; + case GDF_32BIT_X888RGB: + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + p[i].ce.dw = SWAP32((cte.red << 16) | (cte.green << 8) | + cte.blue); + } + break; + default: + printf("RLE Bitmap unsupported in video mode 0x%x\n", + VIDEO_DATA_FORMAT); + return -1; + } + + while (decode) { + switch (bm[0]) { + case 0: + switch (bm[1]) { + case 0: + /* scan line end marker */ + bm += 2; + x = 0; + y--; + fbp = (unsigned char *) + ((unsigned int)video_fb_address + + (((y + yoff) * VIDEO_COLS) + + xoff) * bpp); + continue; + case 1: + /* end of bitmap data marker */ + decode = 0; + break; + case 2: + /* run offset marker */ + x += bm[2]; + y -= bm[3]; + fbp = (unsigned char *) + ((unsigned int)video_fb_address + + (((y + yoff) * VIDEO_COLS) + + x + xoff) * bpp); + bm += 4; + break; + default: + /* unencoded run */ + cnt = bm[1]; + runlen = cnt; + bm += 2; + if (y < height) { + if (x >= width) { + x += runlen; + goto next_run; + } + if (x + runlen > width) + cnt = width - x; + + draw_bitmap (&fbp, bm, p, cnt, 0); + x += runlen; + } +next_run: + bm += runlen; + if (runlen & 1) + bm++; /* 0 padding if length is odd */ + } + break; + default: + /* encoded run */ + if (y < height) { /* only draw into visible area */ + cnt = bm[0]; + runlen = cnt; + if (x >= width) { + x += runlen; + bm += 2; + continue; + } + if (x + runlen > width) + cnt = width - x; + + draw_bitmap (&fbp, bm, p, cnt, 1); + x += runlen; + } + bm += 2; + break; + } + } + return 0; +} +#endif + /* * Display the BMP file located at address bmp_image. - * Only uncompressed */ int video_display_bitmap (ulong bmp_image, int x, int y) { @@ -872,7 +1057,11 @@ int video_display_bitmap (ulong bmp_image, int x, int y) debug ("Display-bmp: %d x %d with %d colors\n", width, height, colors); - if (compression != BMP_BI_RGB) { + if (compression != BMP_BI_RGB +#ifdef CONFIG_VIDEO_BMP_RLE8 + && compression != BMP_BI_RLE8 +#endif + ) { printf ("Error: compression type %ld not supported\n", compression); #ifdef CONFIG_VIDEO_BMP_GZIP @@ -906,6 +1095,13 @@ int video_display_bitmap (ulong bmp_image, int x, int y) ((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE); +#ifdef CONFIG_VIDEO_BMP_RLE8 + if (compression == BMP_BI_RLE8) { + return display_rle8_bitmap(bmp, + x, y, width, height); + } +#endif + /* We handle only 8bpp or 24 bpp bitmap */ switch (le16_to_cpu (bmp->header.bit_count)) { case 8: diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 5bb8b77afc..25afae748d 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -42,11 +42,10 @@ static int at91_wdt_settimeout(unsigned int timeout) { unsigned int reg; - unsigned int mr; + at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE; /* Check if disabled */ - mr = at91_sys_read(AT91_WDT_MR); - if (mr & AT91_WDT_WDDIS) { + if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { printf("sorry, watchdog is disabled\n"); return -1; } @@ -57,19 +56,21 @@ static int at91_wdt_settimeout(unsigned int timeout) * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ - reg = AT91_WDT_WDRSTEN /* causes watchdog reset */ - /* | AT91_WDT_WDRPROC causes processor reset only */ - | AT91_WDT_WDDBGHLT /* disabled in debug mode */ - | AT91_WDT_WDD /* restart at any time */ - | (timeout & AT91_WDT_WDV); /* timer value */ - at91_sys_write(AT91_WDT_MR, reg); + + reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ + | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ + | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ + | AT91_WDT_MR_WDV(timeout); /* timer value */ + + writel(reg, &wd->mr); return 0; } void hw_watchdog_reset(void) { - at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); + at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE; + writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); } void hw_watchdog_init(void) diff --git a/examples/api/Makefile b/examples/api/Makefile index d4c5ca2559..bed16f1555 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -40,14 +40,14 @@ COBJ_FILES-$(CONFIG_API) += glue.o COBJ_FILES-$(CONFIG_API) += libgenwrap.o # Source files which exist outside the examples/api directory -EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/crc32.o -EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/ctype.o -EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/div64.o -EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/string.o -EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/time.o -EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/vsprintf.o +EXT_COBJ_FILES-$(CONFIG_API) += lib/crc32.o +EXT_COBJ_FILES-$(CONFIG_API) += lib/ctype.o +EXT_COBJ_FILES-$(CONFIG_API) += lib/div64.o +EXT_COBJ_FILES-$(CONFIG_API) += lib/string.o +EXT_COBJ_FILES-$(CONFIG_API) += lib/time.o +EXT_COBJ_FILES-$(CONFIG_API) += lib/vsprintf.o ifeq ($(ARCH),ppc) -EXT_SOBJ_FILES-$(CONFIG_API) += lib_ppc/ppcstring.o +EXT_SOBJ_FILES-$(CONFIG_API) += arch/ppc/lib/ppcstring.o endif # Create a list of source files so their dependencies can be auto-generated @@ -75,11 +75,11 @@ $(OUTPUT): $(OBJS) $(OBJCOPY) -O binary $@ $(OUTPUT).bin 2>/dev/null # Rule to build generic library C files -$(obj)%.o: $(SRCTREE)/lib_generic/%.c +$(obj)%.o: $(SRCTREE)/lib/%.c $(CC) -g $(CFLAGS) -c -o $@ $< # Rule to build architecture-specific library assembly files -$(obj)%.o: $(SRCTREE)/lib_$(ARCH)/%.S +$(obj)%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S $(CC) -g $(CFLAGS) -c -o $@ $< ######################################################################### diff --git a/examples/api/libgenwrap.c b/examples/api/libgenwrap.c index 2b107d9797..b435ddecba 100644 --- a/examples/api/libgenwrap.c +++ b/examples/api/libgenwrap.c @@ -23,7 +23,7 @@ * * * This is is a set of wrappers/stubs that allow to use certain routines from - * U-Boot's lib_generic in the standalone app. This way way we can re-use + * U-Boot's lib in the standalone app. This way way we can re-use * existing code e.g. operations on strings and similar. * */ diff --git a/examples/standalone/mem_to_mem_idma2intr.c b/examples/standalone/mem_to_mem_idma2intr.c index 15779d0a16..eeff5f5f2d 100644 --- a/examples/standalone/mem_to_mem_idma2intr.c +++ b/examples/standalone/mem_to_mem_idma2intr.c @@ -1,5 +1,5 @@ /* The dpalloc function used and implemented in this file was derieved - * from PPCBoot/U-Boot file "cpu/mpc8260/commproc.c". + * from PPCBoot/U-Boot file "arch/ppc/cpu/mpc8260/commproc.c". */ /* Author: Arun Dharankar diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 93651f53e9..c4f7445221 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -398,23 +398,26 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf) { struct mtdids *id = current_part->dev->id; + switch(id->type) { #if defined(CONFIG_CMD_FLASH) - if (id->type == MTD_DEV_TYPE_NOR) { + case MTD_DEV_TYPE_NOR: return get_fl_mem_nor(off, size, ext_buf); - } + break; #endif - #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND) - if (id->type == MTD_DEV_TYPE_NAND) + case MTD_DEV_TYPE_NAND: return get_fl_mem_nand(off, size, ext_buf); + break; #endif - #if defined(CONFIG_CMD_ONENAND) - if (id->type == MTD_DEV_TYPE_ONENAND) + case MTD_DEV_TYPE_ONENAND: return get_fl_mem_onenand(off, size, ext_buf); + break; #endif - - printf("get_fl_mem: unknown device type, using raw offset!\n"); + default: + printf("get_fl_mem: unknown device type, " \ + "using raw offset!\n"); + } return (void*)off; } @@ -422,23 +425,27 @@ static inline void *get_node_mem(u32 off, void *ext_buf) { struct mtdids *id = current_part->dev->id; + switch(id->type) { #if defined(CONFIG_CMD_FLASH) - if (id->type == MTD_DEV_TYPE_NOR) + case MTD_DEV_TYPE_NOR: return get_node_mem_nor(off, ext_buf); + break; #endif - #if defined(CONFIG_JFFS2_NAND) && \ defined(CONFIG_CMD_NAND) - if (id->type == MTD_DEV_TYPE_NAND) + case MTD_DEV_TYPE_NAND: return get_node_mem_nand(off, ext_buf); + break; #endif - #if defined(CONFIG_CMD_ONENAND) - if (id->type == MTD_DEV_TYPE_ONENAND) + case MTD_DEV_TYPE_ONENAND: return get_node_mem_onenand(off, ext_buf); + break; #endif - - printf("get_node_mem: unknown device type, using raw offset!\n"); + default: + printf("get_fl_mem: unknown device type, " \ + "using raw offset!\n"); + } return (void*)off; } diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h deleted file mode 100644 index ec053c9912..0000000000 --- a/include/asm-arm/arch-arm720t/hardware.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef __ARM7_HW_H -#define __ARM7_HW_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if defined(CONFIG_NETARM) -#include -#elif defined(CONFIG_IMPA7) -/* include IMPA7 specific hardware file if there was one */ -#elif defined(CONFIG_EP7312) -/* include EP7312 specific hardware file if there was one */ -#elif defined(CONFIG_ARMADILLO) -/* include armadillo specific hardware file if there was one */ -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) -/* include IntegratorCP/CM720T specific hardware file if there was one */ -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ARM7_HW_H */ diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h deleted file mode 100644 index 680fe33270..0000000000 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#define AT91_ASM_PMC_MOR (AT91_PMC_BASE + 0x20) -#define AT91_ASM_PMC_PLLAR (AT91_PMC_BASE + 0x28) -#define AT91_ASM_PMC_PLLBR (AT91_PMC_BASE + 0x2c) -#define AT91_ASM_PMC_MCKR (AT91_PMC_BASE + 0x30) -#define AT91_ASM_PMC_SR (AT91_PMC_BASE + 0x68) - -#ifndef __ASSEMBLY__ - -#include - -typedef struct at91_pmc { - u32 scer; /* 0x00 System Clock Enable Register */ - u32 scdr; /* 0x04 System Clock Disable Register */ - u32 scsr; /* 0x08 System Clock Status Register */ - u32 reserved0; - u32 pcer; /* 0x10 Peripheral Clock Enable Register */ - u32 pcdr; /* 0x14 Peripheral Clock Disable Register */ - u32 pcsr; /* 0x18 Peripheral Clock Status Register */ - u32 reserved1; - u32 mor; /* 0x20 Main Oscilator Register */ - u32 mcfr; /* 0x24 Main Clock Frequency Register */ - u32 pllar; /* 0x28 PLL A Register */ - u32 pllbr; /* 0x2C PLL B Register */ - u32 mckr; /* 0x30 Master Clock Register */ - u32 reserved2[3]; - u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */ - u32 reserved3[4]; - u32 ier; /* 0x60 Interrupt Enable Register */ - u32 idr; /* 0x64 Interrupt Disable Register */ - u32 sr; /* 0x68 Status Register */ - u32 imr; /* 0x6C Interrupt Mask Register */ - u32 reserved4[4]; - u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */ - u32 reserved5[21]; - u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ - u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ - u32 reserved8[5]; -} at91_pmc_t; - -#endif /* end not assembly */ - -#define AT91_PMC_MOR_MOSCEN 0x01 -#define AT91_PMC_MOR_OSCBYPASS 0x02 -#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) - -#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) -#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) -#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) -#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) -#define AT91_PMC_PLLAR_29 0x20000000 -#define AT91_PMC_PLLBR_USBDIV_1 0x00000000 -#define AT91_PMC_PLLBR_USBDIV_2 0x10000000 -#define AT91_PMC_PLLBR_USBDIV_4 0x20000000 - -#define AT91_PMC_MCFR_MAINRDY 0x00010000 -#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF - -#define AT91_PMC_MCKR_CSS_SLOW 0x00000000 -#define AT91_PMC_MCKR_CSS_MAIN 0x00000001 -#define AT91_PMC_MCKR_CSS_PLLA 0x00000002 -#define AT91_PMC_MCKR_CSS_PLLB 0x00000003 -#define AT91_PMC_MCKR_CSS_MASK 0x00000003 - -#define AT91_PMC_MCKR_PRES_1 0x00000000 -#define AT91_PMC_MCKR_PRES_2 0x00000004 -#define AT91_PMC_MCKR_PRES_4 0x00000008 -#define AT91_PMC_MCKR_PRES_8 0x0000000C -#define AT91_PMC_MCKR_PRES_16 0x00000010 -#define AT91_PMC_MCKR_PRES_32 0x00000014 -#define AT91_PMC_MCKR_PRES_64 0x00000018 -#define AT91_PMC_MCKR_PRES_MASK 0x0000001C - -#define AT91_PMC_MCKR_MDIV_1 0x00000000 -#define AT91_PMC_MCKR_MDIV_2 0x00000100 -#define AT91_PMC_MCKR_MDIV_4 0x00000200 -#define AT91_PMC_MCKR_MDIV_MASK 0x00000300 - -#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 -#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 - -#define AT91_PMC_IXR_MOSCS 0x00000001 -#define AT91_PMC_IXR_LOCKA 0x00000002 -#define AT91_PMC_IXR_LOCKB 0x00000004 -#define AT91_PMC_IXR_MCKRDY 0x00000008 -#define AT91_PMC_IXR_LOCKU 0x00000040 -#define AT91_PMC_IXR_PCKRDY0 0x00000100 -#define AT91_PMC_IXR_PCKRDY1 0x00000200 -#define AT91_PMC_IXR_PCKRDY2 0x00000400 -#define AT91_PMC_IXR_PCKRDY3 0x00000800 - -#ifdef CONFIG_AT91_LEGACY - -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ - -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ - -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ - -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ -#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ - -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << 2) -#define AT91_PMC_PRES_2 (1 << 2) -#define AT91_PMC_PRES_4 (2 << 2) -#define AT91_PMC_PRES_8 (3 << 2) -#define AT91_PMC_PRES_16 (4 << 2) -#define AT91_PMC_PRES_32 (5 << 2) -#define AT91_PMC_PRES_64 (6 << 2) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_6 (3 << 8) -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) - -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ - -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ -#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ - -#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ -#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ - -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ - -#endif /* CONFIG_AT91_LEGACY */ -#endif diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h deleted file mode 100644 index a60a0811c0..0000000000 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] - * - * (C) 2006 Andrew Victor - * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -#define AT91_EMAC_BASE 0xfffc4000 -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9260_BASE_US0 -#define AT91_USART1 AT91SAM9260_BASE_US1 -#define AT91_USART2 AT91SAM9260_BASE_US2 -#define AT91_USART3 AT91SAM9260_BASE_US3 -#define AT91_USART4 AT91SAM9260_BASE_US4 -#define AT91_USART5 AT91SAM9260_BASE_US5 - -#endif /* CONFIG_AT91_LEGACY */ - -/* - * Internal Memory. - */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ - -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ - -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ - -/* - * Cpu Name - */ -#if defined(CONFIG_AT91SAM9260) -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" -#elif defined(CONFIG_AT91SAM9G20) -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" -#endif - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h deleted file mode 100644 index 2952292c5d..0000000000 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] - * - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_H -#define AT91SAM9261_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 -#define AT91_BASE_SYS 0xffffea00 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9261_BASE_US0 -#define AT91_USART1 AT91SAM9261_BASE_US1 -#define AT91_USART2 AT91SAM9261_BASE_US2 - -#endif /* CONFIG_AT91_LEGACY */ - -/* - * Internal Memory. - */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ - -/* - * Cpu Name - */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h deleted file mode 100644 index c177bd059e..0000000000 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] - * - * (C) 2007 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_H -#define AT91SAM9263_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - -#define AT91_EMAC_BASE 0xfffbc000 -#define AT91_ECC0_BASE 0xffffe000 -#define AT91_SDRAMC0_BASE 0xffffe200 -#define AT91_SMC0_BASE 0xffffe400 -#define AT91_ECC1_BASE 0xffffe600 -#define AT91_SDRAMC1_BASE 0xffffe800 -#define AT91_SMC1_BASE 0xffffea00 -#define AT91_MATRIX_BASE 0xffffec00 -#define AT91_CCFG_BASE 0xffffed10 -#define AT91_DBGU_BASE 0xffffee00 -#define AT91_AIC_BASE 0xfffff000 -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 -#define AT91_BASE_SYS 0xffffe000 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) -#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) -#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9263_BASE_US0 -#define AT91_USART1 AT91SAM9263_BASE_US1 -#define AT91_USART2 AT91SAM9263_BASE_US2 - -#define AT91_SMC AT91_SMC0 -#define AT91_SDRAMC AT91_SDRAMC0 - -#endif /* CONFIG_AT91_LEGACY */ - -/* - * Internal Memory. - */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ - -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ - -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ - -/* - * Cpu Name - */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" - -#endif diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h deleted file mode 100644 index aa57703c68..0000000000 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include - -typedef struct davinci_emif_regs { - dv_reg ERCSR; - dv_reg AWCCR; - dv_reg SDBCR; - dv_reg SDRCR; - dv_reg AB1CR; - dv_reg AB2CR; - dv_reg AB3CR; - dv_reg AB4CR; - dv_reg SDTIMR; - dv_reg DDRSR; - dv_reg DDRPHYCR; - dv_reg DDRPHYSR; - dv_reg TOTAR; - dv_reg TOTACTR; - dv_reg DDRPHYID_REV; - dv_reg SDSRETR; - dv_reg EIRR; - dv_reg EIMR; - dv_reg EIMSR; - dv_reg EIMCR; - dv_reg IOCTRLR; - dv_reg IOSTATR; - u_int8_t RSVD0[8]; - dv_reg NANDFCR; - dv_reg NANDFSR; - u_int8_t RSVD1[8]; - dv_reg NANDFECC[4]; - u_int8_t RSVD2[60]; - dv_reg NAND4BITECCLOAD; - dv_reg NAND4BITECC1; - dv_reg NAND4BITECC2; - dv_reg NAND4BITECC3; - dv_reg NAND4BITECC4; - dv_reg NANDERRADD1; - dv_reg NANDERRADD2; - dv_reg NANDERRVAL1; - dv_reg NANDERRVAL2; -} emif_registers; - -typedef emif_registers *emifregs; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) (n << 26) -#define DAVINCI_ABCR_WSTROBE(n) (n << 20) -#define DAVINCI_ABCR_WHOLD(n) (n << 17) -#define DAVINCI_ABCR_RSETUP(n) (n << 13) -#define DAVINCI_ABCR_RSTROBE(n) (n << 7) -#define DAVINCI_ABCR_RHOLD(n) (n << 4) -#define DAVINCI_ABCR_TA(n) (n << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/include/asm-arm/arch-lpc2292/hardware.h b/include/asm-arm/arch-lpc2292/hardware.h deleted file mode 100644 index fd2b464e37..0000000000 --- a/include/asm-arm/arch-lpc2292/hardware.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if defined(CONFIG_LPC2292) -#include -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-mx27/imx-regs.h b/include/asm-arm/arch-mx27/imx-regs.h deleted file mode 100644 index d36a6da96d..0000000000 --- a/include/asm-arm/arch-mx27/imx-regs.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * (c) 2007 Pengutronix, Sascha Hauer - * (c) 2009 Ilya Yanok, Emcraft Systems - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#ifndef __ASSEMBLY__ - -extern void imx_gpio_mode (int gpio_mode); - -#ifdef CONFIG_MXC_UART -extern void mx27_uart_init_pins(void); -#endif /* CONFIG_MXC_UART */ - -#ifdef CONFIG_FEC_MXC -extern void mx27_fec_init_pins(void); -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_MXC_MMC -extern void mx27_sd2_init_pins(void); -#endif /* CONFIG_MXC_MMC */ - -/* AIPI */ -struct aipi_regs { - u32 psr0; - u32 psr1; -}; - -/* System Control */ -struct system_control_regs { - u32 res[5]; - u32 fmcr; - u32 gpcr; - u32 wbcr; - u32 dscr1; - u32 dscr2; - u32 dscr3; - u32 dscr4; - u32 dscr5; - u32 dscr6; - u32 dscr7; - u32 dscr8; - u32 dscr9; - u32 dscr10; - u32 dscr11; - u32 dscr12; - u32 dscr13; - u32 pscr; - u32 pmcr; - u32 res1; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; -}; - -/* Chip Select Registers */ -struct weim_regs { - u32 cs0u; /* Chip Select 0 Upper Register */ - u32 cs0l; /* Chip Select 0 Lower Register */ - u32 cs0a; /* Chip Select 0 Addition Register */ - u32 pad0; - u32 cs1u; /* Chip Select 1 Upper Register */ - u32 cs1l; /* Chip Select 1 Lower Register */ - u32 cs1a; /* Chip Select 1 Addition Register */ - u32 pad1; - u32 cs2u; /* Chip Select 2 Upper Register */ - u32 cs2l; /* Chip Select 2 Lower Register */ - u32 cs2a; /* Chip Select 2 Addition Register */ - u32 pad2; - u32 cs3u; /* Chip Select 3 Upper Register */ - u32 cs3l; /* Chip Select 3 Lower Register */ - u32 cs3a; /* Chip Select 3 Addition Register */ - u32 pad3; - u32 cs4u; /* Chip Select 4 Upper Register */ - u32 cs4l; /* Chip Select 4 Lower Register */ - u32 cs4a; /* Chip Select 4 Addition Register */ - u32 pad4; - u32 cs5u; /* Chip Select 5 Upper Register */ - u32 cs5l; /* Chip Select 5 Lower Register */ - u32 cs5a; /* Chip Select 5 Addition Register */ - u32 pad5; - u32 eim; /* WEIM Configuration Register */ -}; - -/* SDRAM Controller registers */ -struct esdramc_regs { -/* Enhanced SDRAM Control Register 0 */ - u32 esdctl0; -/* Enhanced SDRAM Configuration Register 0 */ - u32 esdcfg0; -/* Enhanced SDRAM Control Register 1 */ - u32 esdctl1; -/* Enhanced SDRAM Configuration Register 1 */ - u32 esdcfg1; -/* Enhanced SDRAM Miscellanious Register */ - u32 esdmisc; -}; - -/* Watchdog Registers*/ -struct wdog_regs { - u32 wcr; - u32 wsr; - u32 wstr; -}; - -/* PLL registers */ -struct pll_regs { - u32 cscr; /* Clock Source Control Register */ - u32 mpctl0; /* MCU PLL Control Register 0 */ - u32 mpctl1; /* MCU PLL Control Register 1 */ - u32 spctl0; /* System PLL Control Register 0 */ - u32 spctl1; /* System PLL Control Register 1 */ - u32 osc26mctl; /* Oscillator 26M Register */ - u32 pcdr0; /* Peripheral Clock Divider Register 0 */ - u32 pcdr1; /* Peripheral Clock Divider Register 1 */ - u32 pccr0; /* Peripheral Clock Control Register 0 */ - u32 pccr1; /* Peripheral Clock Control Register 1 */ - u32 ccsr; /* Clock Control Status Register */ -}; - -/* - * Definitions for the clocksource registers - */ -struct gpt_regs { - u32 gpt_tctl; - u32 gpt_tprer; - u32 gpt_tcmp; - u32 gpt_tcr; - u32 gpt_tcn; - u32 gpt_tstat; -}; - -/* - * GPIO Module and I/O Multiplexer - */ -#define PORTA 0 -#define PORTB 1 -#define PORTC 2 -#define PORTD 3 -#define PORTE 4 -#define PORTF 5 - -struct gpio_regs { - struct { - u32 ddir; - u32 ocr1; - u32 ocr2; - u32 iconfa1; - u32 iconfa2; - u32 iconfb1; - u32 iconfb2; - u32 dr; - u32 gius; - u32 ssr; - u32 icr1; - u32 icr2; - u32 imr; - u32 isr; - u32 gpr; - u32 swr; - u32 puen; - u32 res[0x2f]; - } port[6]; -}; - -/* IIM Control Registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prog_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res[0x1F0]; - u32 iim_bank_area0[0x100]; -}; -#endif - -#define IMX_IO_BASE 0x10000000 - -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) -#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) -#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) -#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) -#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) -#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) -#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE) -#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) -#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) -#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) -#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) - -#define IMX_ESD_BASE (0xD8001000) -#define IMX_WEIM_BASE (0xD8002000) - -/* FMCR System Control bit definition*/ -#define UART4_RXD_CTL (1 << 25) -#define UART4_RTS_CTL (1 << 24) -#define KP_COL6_CTL (1 << 18) -#define KP_ROW7_CTL (1 << 17) -#define KP_ROW6_CTL (1 << 16) -#define PC_WAIT_B_CTL (1 << 14) -#define PC_READY_CTL (1 << 13) -#define PC_VS1_CTL (1 << 12) -#define PC_VS2_CTL (1 << 11) -#define PC_BVD1_CTL (1 << 10) -#define PC_BVD2_CTL (1 << 9) -#define IOS16_CTL (1 << 8) -#define NF_FMS (1 << 5) -#define NF_16BIT_SEL (1 << 4) -#define SLCDC_SEL (1 << 2) -#define SDCS1_SEL (1 << 1) -#define SDCS0_SEL (1 << 0) - - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) -#define CSCR_AHB_DIV -#define CSCR_ARM_DIV -#define CSCR_ARM_SRC_MPLL (1 << 15) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_MPLL_RESTART (1 << 18) -#define CSCR_SPLL_RESTART (1 << 19) -#define CSCR_MSHC_SEL (1 << 20) -#define CSCR_H264_SEL (1 << 21) -#define CSCR_SSI1_SEL (1 << 22) -#define CSCR_SSI2_SEL (1 << 23) -#define CSCR_SD_CNT -#define CSCR_USB_DIV -#define CSCR_UPDATE_DIS (1 << 31) - -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) - -#define PCCR0_SSI2_EN (1 << 0) -#define PCCR0_SSI1_EN (1 << 1) -#define PCCR0_SLCDC_EN (1 << 2) -#define PCCR0_SDHC3_EN (1 << 3) -#define PCCR0_SDHC2_EN (1 << 4) -#define PCCR0_SDHC1_EN (1 << 5) -#define PCCR0_SDC_EN (1 << 6) -#define PCCR0_SAHARA_EN (1 << 7) -#define PCCR0_RTIC_EN (1 << 8) -#define PCCR0_RTC_EN (1 << 9) -#define PCCR0_PWM_EN (1 << 11) -#define PCCR0_OWIRE_EN (1 << 12) -#define PCCR0_MSHC_EN (1 << 13) -#define PCCR0_LCDC_EN (1 << 14) -#define PCCR0_KPP_EN (1 << 15) -#define PCCR0_IIM_EN (1 << 16) -#define PCCR0_I2C2_EN (1 << 17) -#define PCCR0_I2C1_EN (1 << 18) -#define PCCR0_GPT6_EN (1 << 19) -#define PCCR0_GPT5_EN (1 << 20) -#define PCCR0_GPT4_EN (1 << 21) -#define PCCR0_GPT3_EN (1 << 22) -#define PCCR0_GPT2_EN (1 << 23) -#define PCCR0_GPT1_EN (1 << 24) -#define PCCR0_GPIO_EN (1 << 25) -#define PCCR0_FEC_EN (1 << 26) -#define PCCR0_EMMA_EN (1 << 27) -#define PCCR0_DMA_EN (1 << 28) -#define PCCR0_CSPI3_EN (1 << 29) -#define PCCR0_CSPI2_EN (1 << 30) -#define PCCR0_CSPI1_EN (1 << 31) - -#define PCCR1_MSHC_BAUDEN (1 << 2) -#define PCCR1_NFC_BAUDEN (1 << 3) -#define PCCR1_SSI2_BAUDEN (1 << 4) -#define PCCR1_SSI1_BAUDEN (1 << 5) -#define PCCR1_H264_BAUDEN (1 << 6) -#define PCCR1_PERCLK4_EN (1 << 7) -#define PCCR1_PERCLK3_EN (1 << 8) -#define PCCR1_PERCLK2_EN (1 << 9) -#define PCCR1_PERCLK1_EN (1 << 10) -#define PCCR1_HCLK_USB (1 << 11) -#define PCCR1_HCLK_SLCDC (1 << 12) -#define PCCR1_HCLK_SAHARA (1 << 13) -#define PCCR1_HCLK_RTIC (1 << 14) -#define PCCR1_HCLK_LCDC (1 << 15) -#define PCCR1_HCLK_H264 (1 << 16) -#define PCCR1_HCLK_FEC (1 << 17) -#define PCCR1_HCLK_EMMA (1 << 18) -#define PCCR1_HCLK_EMI (1 << 19) -#define PCCR1_HCLK_DMA (1 << 20) -#define PCCR1_HCLK_CSI (1 << 21) -#define PCCR1_HCLK_BROM (1 << 22) -#define PCCR1_HCLK_ATA (1 << 23) -#define PCCR1_WDT_EN (1 << 24) -#define PCCR1_USB_EN (1 << 25) -#define PCCR1_UART6_EN (1 << 26) -#define PCCR1_UART5_EN (1 << 27) -#define PCCR1_UART4_EN (1 << 28) -#define PCCR1_UART3_EN (1 << 29) -#define PCCR1_UART2_EN (1 << 30) -#define PCCR1_UART1_EN (1 << 31) - -/* SDRAM Controller registers bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) -#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) - -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) -#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) - -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) - -/* Clocksource Bitfields */ -#define TCTL_SWR (1 << 15) /* Software reset */ -#define TCTL_FRR (1 << 8) /* Freerun / restart */ -#define TCTL_CAP (3 << 6) /* Capture Edge */ -#define TCTL_OM (1 << 5) /* output mode */ -#define TCTL_IRQEN (1 << 4) /* interrupt enable */ -#define TCTL_CLKSOURCE 1 /* Clock source bit position */ -#define TCTL_TEN 1 /* Timer enable */ -#define TPRER_PRES 0xff /* Prescale */ -#define TSTAT_CAPT (1 << 1) /* Capture event */ -#define TSTAT_COMP 1 /* Compare event */ - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) -#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) -#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) -#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) -#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) -#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -#define IIM_STAT_BUSY (1 << 7) -#define IIM_STAT_PRGD (1 << 1) -#define IIM_STAT_SNSD (1 << 0) -#define IIM_ERR_PRGE (1 << 7) -#define IIM_ERR_WPE (1 << 6) -#define IIM_ERR_OPE (1 << 5) -#define IIM_ERR_RPE (1 << 4) -#define IIM_ERR_WLRE (1 << 3) -#define IIM_ERR_SNSE (1 << 2) -#define IIM_ERR_PARITYE (1 << 1) - -/* Definitions for i.MX27 TO2 */ -#define IIM0_MAC 5 -#define IIM0_SCC_KEY 11 -#define IIM1_SUID 1 - -#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-mx51/asm-offsets.h b/include/asm-arm/arch-mx51/asm-offsets.h deleted file mode 100644 index 3a83fa07a1..0000000000 --- a/include/asm-arm/arch-mx51/asm-offsets.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * needed for cpu/arm_cortexa8/mx51/lowlevel_init.S - * - * These should be auto-generated - */ -/* CCM */ -#define CLKCTL_CCR 0x00 -#define CLKCTL_CCDR 0x04 -#define CLKCTL_CSR 0x08 -#define CLKCTL_CCSR 0x0C -#define CLKCTL_CACRR 0x10 -#define CLKCTL_CBCDR 0x14 -#define CLKCTL_CBCMR 0x18 -#define CLKCTL_CSCMR1 0x1C -#define CLKCTL_CSCMR2 0x20 -#define CLKCTL_CSCDR1 0x24 -#define CLKCTL_CS1CDR 0x28 -#define CLKCTL_CS2CDR 0x2C -#define CLKCTL_CDCDR 0x30 -#define CLKCTL_CHSCCDR 0x34 -#define CLKCTL_CSCDR2 0x38 -#define CLKCTL_CSCDR3 0x3C -#define CLKCTL_CSCDR4 0x40 -#define CLKCTL_CWDR 0x44 -#define CLKCTL_CDHIPR 0x48 -#define CLKCTL_CDCR 0x4C -#define CLKCTL_CTOR 0x50 -#define CLKCTL_CLPCR 0x54 -#define CLKCTL_CISR 0x58 -#define CLKCTL_CIMR 0x5C -#define CLKCTL_CCOSR 0x60 -#define CLKCTL_CGPR 0x64 -#define CLKCTL_CCGR0 0x68 -#define CLKCTL_CCGR1 0x6C -#define CLKCTL_CCGR2 0x70 -#define CLKCTL_CCGR3 0x74 -#define CLKCTL_CCGR4 0x78 -#define CLKCTL_CCGR5 0x7C -#define CLKCTL_CCGR6 0x80 -#define CLKCTL_CMEOR 0x84 - -/* DPLL */ -#define PLL_DP_CTL 0x00 -#define PLL_DP_CONFIG 0x04 -#define PLL_DP_OP 0x08 -#define PLL_DP_MFD 0x0C -#define PLL_DP_MFN 0x10 -#define PLL_DP_HFS_OP 0x1C -#define PLL_DP_HFS_MFD 0x20 -#define PLL_DP_HFS_MFN 0x24 diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h deleted file mode 100644 index 4622557b57..0000000000 --- a/include/asm-arm/mach-types.h +++ /dev/null @@ -1,34955 +0,0 @@ -/* - * This was automagically generated from arch/arm/tools/mach-types! - * Do NOT edit - */ - -#ifndef __ASM_ARM_MACH_TYPE_H -#define __ASM_ARM_MACH_TYPE_H - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -/* see arch/arm/kernel/arch.c for a description of these */ -#define MACH_TYPE_EBSA110 0 -#define MACH_TYPE_RISCPC 1 -#define MACH_TYPE_NEXUSPCI 3 -#define MACH_TYPE_EBSA285 4 -#define MACH_TYPE_NETWINDER 5 -#define MACH_TYPE_CATS 6 -#define MACH_TYPE_TBOX 7 -#define MACH_TYPE_CO285 8 -#define MACH_TYPE_CLPS7110 9 -#define MACH_TYPE_ARCHIMEDES 10 -#define MACH_TYPE_A5K 11 -#define MACH_TYPE_ETOILE 12 -#define MACH_TYPE_LACIE_NAS 13 -#define MACH_TYPE_CLPS7500 14 -#define MACH_TYPE_SHARK 15 -#define MACH_TYPE_BRUTUS 16 -#define MACH_TYPE_PERSONAL_SERVER 17 -#define MACH_TYPE_ITSY 18 -#define MACH_TYPE_L7200 19 -#define MACH_TYPE_PLEB 20 -#define MACH_TYPE_INTEGRATOR 21 -#define MACH_TYPE_H3600 22 -#define MACH_TYPE_IXP1200 23 -#define MACH_TYPE_P720T 24 -#define MACH_TYPE_ASSABET 25 -#define MACH_TYPE_VICTOR 26 -#define MACH_TYPE_LART 27 -#define MACH_TYPE_RANGER 28 -#define MACH_TYPE_GRAPHICSCLIENT 29 -#define MACH_TYPE_XP860 30 -#define MACH_TYPE_CERF 31 -#define MACH_TYPE_NANOENGINE 32 -#define MACH_TYPE_FPIC 33 -#define MACH_TYPE_EXTENEX1 34 -#define MACH_TYPE_SHERMAN 35 -#define MACH_TYPE_ACCELENT_SA 36 -#define MACH_TYPE_ACCELENT_L7200 37 -#define MACH_TYPE_NETPORT 38 -#define MACH_TYPE_PANGOLIN 39 -#define MACH_TYPE_YOPY 40 -#define MACH_TYPE_COOLIDGE 41 -#define MACH_TYPE_HUW_WEBPANEL 42 -#define MACH_TYPE_SPOTME 43 -#define MACH_TYPE_FREEBIRD 44 -#define MACH_TYPE_TI925 45 -#define MACH_TYPE_RISCSTATION 46 -#define MACH_TYPE_CAVY 47 -#define MACH_TYPE_JORNADA720 48 -#define MACH_TYPE_OMNIMETER 49 -#define MACH_TYPE_EDB7211 50 -#define MACH_TYPE_CITYGO 51 -#define MACH_TYPE_PFS168 52 -#define MACH_TYPE_SPOT 53 -#define MACH_TYPE_FLEXANET 54 -#define MACH_TYPE_WEBPAL 55 -#define MACH_TYPE_LINPDA 56 -#define MACH_TYPE_ANAKIN 57 -#define MACH_TYPE_MVI 58 -#define MACH_TYPE_JUPITER 59 -#define MACH_TYPE_PSIONW 60 -#define MACH_TYPE_ALN 61 -#define MACH_TYPE_CAMELOT 62 -#define MACH_TYPE_GDS2200 63 -#define MACH_TYPE_PSION_SERIES7 64 -#define MACH_TYPE_XFILE 65 -#define MACH_TYPE_ACCELENT_EP9312 66 -#define MACH_TYPE_IC200 67 -#define MACH_TYPE_CREDITLART 68 -#define MACH_TYPE_HTM 69 -#define MACH_TYPE_IQ80310 70 -#define MACH_TYPE_FREEBOT 71 -#define MACH_TYPE_ENTEL 72 -#define MACH_TYPE_ENP3510 73 -#define MACH_TYPE_TRIZEPS 74 -#define MACH_TYPE_NESA 75 -#define MACH_TYPE_VENUS 76 -#define MACH_TYPE_TARDIS 77 -#define MACH_TYPE_MERCURY 78 -#define MACH_TYPE_EMPEG 79 -#define MACH_TYPE_I80200FCC 80 -#define MACH_TYPE_ITT_CPB 81 -#define MACH_TYPE_SVC 82 -#define MACH_TYPE_ALPHA2 84 -#define MACH_TYPE_ALPHA1 85 -#define MACH_TYPE_NETARM 86 -#define MACH_TYPE_SIMPAD 87 -#define MACH_TYPE_PDA1 88 -#define MACH_TYPE_LUBBOCK 89 -#define MACH_TYPE_ANIKO 90 -#define MACH_TYPE_CLEP7212 91 -#define MACH_TYPE_CS89712 92 -#define MACH_TYPE_WEARARM 93 -#define MACH_TYPE_POSSIO_PX 94 -#define MACH_TYPE_SIDEARM 95 -#define MACH_TYPE_STORK 96 -#define MACH_TYPE_SHANNON 97 -#define MACH_TYPE_ACE 98 -#define MACH_TYPE_BALLYARM 99 -#define MACH_TYPE_SIMPUTER 100 -#define MACH_TYPE_NEXTERM 101 -#define MACH_TYPE_SA1100_ELF 102 -#define MACH_TYPE_GATOR 103 -#define MACH_TYPE_GRANITE 104 -#define MACH_TYPE_CONSUS 105 -#define MACH_TYPE_AAED2000 106 -#define MACH_TYPE_CDB89712 107 -#define MACH_TYPE_GRAPHICSMASTER 108 -#define MACH_TYPE_ADSBITSY 109 -#define MACH_TYPE_PXA_IDP 110 -#define MACH_TYPE_PLCE 111 -#define MACH_TYPE_PT_SYSTEM3 112 -#define MACH_TYPE_MEDALB 113 -#define MACH_TYPE_EAGLE 114 -#define MACH_TYPE_DSC21 115 -#define MACH_TYPE_DSC24 116 -#define MACH_TYPE_TI5472 117 -#define MACH_TYPE_AUTCPU12 118 -#define MACH_TYPE_UENGINE 119 -#define MACH_TYPE_BLUESTEM 120 -#define MACH_TYPE_XINGU8 121 -#define MACH_TYPE_BUSHSTB 122 -#define MACH_TYPE_EPSILON1 123 -#define MACH_TYPE_BALLOON 124 -#define MACH_TYPE_PUPPY 125 -#define MACH_TYPE_ELROY 126 -#define MACH_TYPE_GMS720 127 -#define MACH_TYPE_S24X 128 -#define MACH_TYPE_JTEL_CLEP7312 129 -#define MACH_TYPE_CX821XX 130 -#define MACH_TYPE_EDB7312 131 -#define MACH_TYPE_BSA1110 132 -#define MACH_TYPE_POWERPIN 133 -#define MACH_TYPE_OPENARM 134 -#define MACH_TYPE_WHITECHAPEL 135 -#define MACH_TYPE_H3100 136 -#define MACH_TYPE_H3800 137 -#define MACH_TYPE_BLUE_V1 138 -#define MACH_TYPE_PXA_CERF 139 -#define MACH_TYPE_ARM7TEVB 140 -#define MACH_TYPE_D7400 141 -#define MACH_TYPE_PIRANHA 142 -#define MACH_TYPE_SBCAMELOT 143 -#define MACH_TYPE_KINGS 144 -#define MACH_TYPE_SMDK2400 145 -#define MACH_TYPE_COLLIE 146 -#define MACH_TYPE_IDR 147 -#define MACH_TYPE_BADGE4 148 -#define MACH_TYPE_WEBNET 149 -#define MACH_TYPE_D7300 150 -#define MACH_TYPE_CEP 151 -#define MACH_TYPE_FORTUNET 152 -#define MACH_TYPE_VC547X 153 -#define MACH_TYPE_FILEWALKER 154 -#define MACH_TYPE_NETGATEWAY 155 -#define MACH_TYPE_SYMBOL2800 156 -#define MACH_TYPE_SUNS 157 -#define MACH_TYPE_FRODO 158 -#define MACH_TYPE_MACH_TYTE_MS301 159 -#define MACH_TYPE_MX1ADS 160 -#define MACH_TYPE_H7201 161 -#define MACH_TYPE_H7202 162 -#define MACH_TYPE_AMICO 163 -#define MACH_TYPE_IAM 164 -#define MACH_TYPE_TT530 165 -#define MACH_TYPE_SAM2400 166 -#define MACH_TYPE_JORNADA56X 167 -#define MACH_TYPE_ACTIVE 168 -#define MACH_TYPE_IQ80321 169 -#define MACH_TYPE_WID 170 -#define MACH_TYPE_SABINAL 171 -#define MACH_TYPE_IXP425_MATACUMBE 172 -#define MACH_TYPE_MINIPRINT 173 -#define MACH_TYPE_ADM510X 174 -#define MACH_TYPE_SVS200 175 -#define MACH_TYPE_ATG_TCU 176 -#define MACH_TYPE_JORNADA820 177 -#define MACH_TYPE_S3C44B0 178 -#define MACH_TYPE_MARGIS2 179 -#define MACH_TYPE_KS8695 180 -#define MACH_TYPE_BRH 181 -#define MACH_TYPE_S3C2410 182 -#define MACH_TYPE_POSSIO_PX30 183 -#define MACH_TYPE_S3C2800 184 -#define MACH_TYPE_FLEETWOOD 185 -#define MACH_TYPE_OMAHA 186 -#define MACH_TYPE_TA7 187 -#define MACH_TYPE_NOVA 188 -#define MACH_TYPE_HMK 189 -#define MACH_TYPE_KARO 190 -#define MACH_TYPE_FESTER 191 -#define MACH_TYPE_GPI 192 -#define MACH_TYPE_SMDK2410 193 -#define MACH_TYPE_I519 194 -#define MACH_TYPE_NEXIO 195 -#define MACH_TYPE_BITBOX 196 -#define MACH_TYPE_G200 197 -#define MACH_TYPE_GILL 198 -#define MACH_TYPE_PXA_MERCURY 199 -#define MACH_TYPE_CEIVA 200 -#define MACH_TYPE_FRET 201 -#define MACH_TYPE_EMAILPHONE 202 -#define MACH_TYPE_H3900 203 -#define MACH_TYPE_PXA1 204 -#define MACH_TYPE_KOAN369 205 -#define MACH_TYPE_COGENT 206 -#define MACH_TYPE_ESL_SIMPUTER 207 -#define MACH_TYPE_ESL_SIMPUTER_CLR 208 -#define MACH_TYPE_ESL_SIMPUTER_BW 209 -#define MACH_TYPE_HHP_CRADLE 210 -#define MACH_TYPE_HE500 211 -#define MACH_TYPE_INHANDELF2 212 -#define MACH_TYPE_INHANDFTIP 213 -#define MACH_TYPE_DNP1110 214 -#define MACH_TYPE_PNP1110 215 -#define MACH_TYPE_CSB226 216 -#define MACH_TYPE_ARNOLD 217 -#define MACH_TYPE_VOICEBLUE 218 -#define MACH_TYPE_JZ8028 219 -#define MACH_TYPE_H5400 220 -#define MACH_TYPE_FORTE 221 -#define MACH_TYPE_ACAM 222 -#define MACH_TYPE_ABOX 223 -#define MACH_TYPE_ATMEL 224 -#define MACH_TYPE_SITSANG 225 -#define MACH_TYPE_CPU1110LCDNET 226 -#define MACH_TYPE_MPL_VCMA9 227 -#define MACH_TYPE_OPUS_A1 228 -#define MACH_TYPE_DAYTONA 229 -#define MACH_TYPE_KILLBEAR 230 -#define MACH_TYPE_YOHO 231 -#define MACH_TYPE_JASPER 232 -#define MACH_TYPE_DSC25 233 -#define MACH_TYPE_OMAP_INNOVATOR 234 -#define MACH_TYPE_RAMSES 235 -#define MACH_TYPE_S28X 236 -#define MACH_TYPE_MPORT3 237 -#define MACH_TYPE_PXA_EAGLE250 238 -#define MACH_TYPE_PDB 239 -#define MACH_TYPE_BLUE_2G 240 -#define MACH_TYPE_BLUEARCH 241 -#define MACH_TYPE_IXDP2400 242 -#define MACH_TYPE_IXDP2800 243 -#define MACH_TYPE_EXPLORER 244 -#define MACH_TYPE_IXDP425 245 -#define MACH_TYPE_CHIMP 246 -#define MACH_TYPE_STORK_NEST 247 -#define MACH_TYPE_STORK_EGG 248 -#define MACH_TYPE_WISMO 249 -#define MACH_TYPE_EZLINX 250 -#define MACH_TYPE_AT91RM9200 251 -#define MACH_TYPE_ADTECH_ORION 252 -#define MACH_TYPE_NEPTUNE 253 -#define MACH_TYPE_HACKKIT 254 -#define MACH_TYPE_PXA_WINS30 255 -#define MACH_TYPE_LAVINNA 256 -#define MACH_TYPE_PXA_UENGINE 257 -#define MACH_TYPE_INNOKOM 258 -#define MACH_TYPE_BMS 259 -#define MACH_TYPE_IXCDP1100 260 -#define MACH_TYPE_PRPMC1100 261 -#define MACH_TYPE_AT91RM9200DK 262 -#define MACH_TYPE_ARMSTICK 263 -#define MACH_TYPE_ARMONIE 264 -#define MACH_TYPE_MPORT1 265 -#define MACH_TYPE_S3C5410 266 -#define MACH_TYPE_ZCP320A 267 -#define MACH_TYPE_I_BOX 268 -#define MACH_TYPE_STLC1502 269 -#define MACH_TYPE_SIREN 270 -#define MACH_TYPE_GREENLAKE 271 -#define MACH_TYPE_ARGUS 272 -#define MACH_TYPE_COMBADGE 273 -#define MACH_TYPE_ROKEPXA 274 -#define MACH_TYPE_CINTEGRATOR 275 -#define MACH_TYPE_GUIDEA07 276 -#define MACH_TYPE_TAT257 277 -#define MACH_TYPE_IGP2425 278 -#define MACH_TYPE_BLUEGRAMMA 279 -#define MACH_TYPE_IPOD 280 -#define MACH_TYPE_ADSBITSYX 281 -#define MACH_TYPE_TRIZEPS2 282 -#define MACH_TYPE_VIPER 283 -#define MACH_TYPE_ADSBITSYPLUS 284 -#define MACH_TYPE_ADSAGC 285 -#define MACH_TYPE_STP7312 286 -#define MACH_TYPE_NX_PHNX 287 -#define MACH_TYPE_WEP_EP250 288 -#define MACH_TYPE_INHANDELF3 289 -#define MACH_TYPE_ADI_COYOTE 290 -#define MACH_TYPE_IYONIX 291 -#define MACH_TYPE_DAMICAM_SA1110 292 -#define MACH_TYPE_MEG03 293 -#define MACH_TYPE_PXA_WHITECHAPEL 294 -#define MACH_TYPE_NWSC 295 -#define MACH_TYPE_NWLARM 296 -#define MACH_TYPE_IXP425_MGUARD 297 -#define MACH_TYPE_PXA_NETDCU4 298 -#define MACH_TYPE_IXDP2401 299 -#define MACH_TYPE_IXDP2801 300 -#define MACH_TYPE_ZODIAC 301 -#define MACH_TYPE_ARMMODUL 302 -#define MACH_TYPE_KETOP 303 -#define MACH_TYPE_AV7200 304 -#define MACH_TYPE_ARCH_TI925 305 -#define MACH_TYPE_ACQ200 306 -#define MACH_TYPE_PT_DAFIT 307 -#define MACH_TYPE_IHBA 308 -#define MACH_TYPE_QUINQUE 309 -#define MACH_TYPE_NIMBRAONE 310 -#define MACH_TYPE_NIMBRA29X 311 -#define MACH_TYPE_NIMBRA210 312 -#define MACH_TYPE_HHP_D95XX 313 -#define MACH_TYPE_LABARM 314 -#define MACH_TYPE_M825XX 315 -#define MACH_TYPE_M7100 316 -#define MACH_TYPE_NIPC2 317 -#define MACH_TYPE_FU7202 318 -#define MACH_TYPE_ADSAGX 319 -#define MACH_TYPE_PXA_POOH 320 -#define MACH_TYPE_BANDON 321 -#define MACH_TYPE_PCM7210 322 -#define MACH_TYPE_NMS9200 323 -#define MACH_TYPE_LOGODL 324 -#define MACH_TYPE_M7140 325 -#define MACH_TYPE_KOREBOT 326 -#define MACH_TYPE_IQ31244 327 -#define MACH_TYPE_KOAN393 328 -#define MACH_TYPE_INHANDFTIP3 329 -#define MACH_TYPE_GONZO 330 -#define MACH_TYPE_BAST 331 -#define MACH_TYPE_SCANPASS 332 -#define MACH_TYPE_EP7312_POOH 333 -#define MACH_TYPE_TA7S 334 -#define MACH_TYPE_TA7V 335 -#define MACH_TYPE_ICARUS 336 -#define MACH_TYPE_H1900 337 -#define MACH_TYPE_GEMINI 338 -#define MACH_TYPE_AXIM 339 -#define MACH_TYPE_AUDIOTRON 340 -#define MACH_TYPE_H2200 341 -#define MACH_TYPE_LOOX600 342 -#define MACH_TYPE_NIOP 343 -#define MACH_TYPE_DM310 344 -#define MACH_TYPE_SEEDPXA_C2 345 -#define MACH_TYPE_IXP4XX_MGUARD_PCI 346 -#define MACH_TYPE_H1940 347 -#define MACH_TYPE_SCORPIO 348 -#define MACH_TYPE_VIVA 349 -#define MACH_TYPE_PXA_XCARD 350 -#define MACH_TYPE_CSB335 351 -#define MACH_TYPE_IXRD425 352 -#define MACH_TYPE_IQ80315 353 -#define MACH_TYPE_NMP7312 354 -#define MACH_TYPE_CX861XX 355 -#define MACH_TYPE_ENP2611 356 -#define MACH_TYPE_XDA 357 -#define MACH_TYPE_CSIR_IMS 358 -#define MACH_TYPE_IXP421_DNAEETH 359 -#define MACH_TYPE_POCKETSERV9200 360 -#define MACH_TYPE_TOTO 361 -#define MACH_TYPE_S3C2440 362 -#define MACH_TYPE_KS8695P 363 -#define MACH_TYPE_SE4000 364 -#define MACH_TYPE_QUADRICEPS 365 -#define MACH_TYPE_BRONCO 366 -#define MACH_TYPE_ESL_WIRELESS_TAB 367 -#define MACH_TYPE_ESL_SOFCOMP 368 -#define MACH_TYPE_S5C7375 369 -#define MACH_TYPE_SPEARHEAD 370 -#define MACH_TYPE_PANTERA 371 -#define MACH_TYPE_PRAYOGLITE 372 -#define MACH_TYPE_GUMSTIX 373 -#define MACH_TYPE_RCUBE 374 -#define MACH_TYPE_REA_OLV 375 -#define MACH_TYPE_PXA_IPHONE 376 -#define MACH_TYPE_S3C3410 377 -#define MACH_TYPE_ESPD_4510B 378 -#define MACH_TYPE_MP1X 379 -#define MACH_TYPE_AT91RM9200TB 380 -#define MACH_TYPE_ADSVGX 381 -#define MACH_TYPE_OMAP_H2 382 -#define MACH_TYPE_PELEE 383 -#define MACH_TYPE_E740 384 -#define MACH_TYPE_IQ80331 385 -#define MACH_TYPE_VERSATILE_PB 387 -#define MACH_TYPE_KEV7A400 388 -#define MACH_TYPE_LPD7A400 389 -#define MACH_TYPE_LPD7A404 390 -#define MACH_TYPE_FUJITSU_CAMELOT 391 -#define MACH_TYPE_JANUS2M 392 -#define MACH_TYPE_EMBTF 393 -#define MACH_TYPE_HPM 394 -#define MACH_TYPE_SMDK2410TK 395 -#define MACH_TYPE_SMDK2410AJ 396 -#define MACH_TYPE_STREETRACER 397 -#define MACH_TYPE_EFRAME 398 -#define MACH_TYPE_CSB337 399 -#define MACH_TYPE_PXA_LARK 400 -#define MACH_TYPE_PNP2110 401 -#define MACH_TYPE_TCC72X 402 -#define MACH_TYPE_ALTAIR 403 -#define MACH_TYPE_KC3 404 -#define MACH_TYPE_SINTEFTD 405 -#define MACH_TYPE_MAINSTONE 406 -#define MACH_TYPE_ADAY4X 407 -#define MACH_TYPE_LITE300 408 -#define MACH_TYPE_S5C7376 409 -#define MACH_TYPE_MT02 410 -#define MACH_TYPE_MPORT3S 411 -#define MACH_TYPE_RA_ALPHA 412 -#define MACH_TYPE_XCEP 413 -#define MACH_TYPE_ARCOM_VULCAN 414 -#define MACH_TYPE_STARGATE 415 -#define MACH_TYPE_ARMADILLOJ 416 -#define MACH_TYPE_ELROY_JACK 417 -#define MACH_TYPE_BACKEND 418 -#define MACH_TYPE_S5LINBOX 419 -#define MACH_TYPE_NOMADIK 420 -#define MACH_TYPE_IA_CPU_9200 421 -#define MACH_TYPE_AT91_BJA1 422 -#define MACH_TYPE_CORGI 423 -#define MACH_TYPE_POODLE 424 -#define MACH_TYPE_TEN 425 -#define MACH_TYPE_ROVERP5P 426 -#define MACH_TYPE_SC2700 427 -#define MACH_TYPE_EX_EAGLE 428 -#define MACH_TYPE_NX_PXA12 429 -#define MACH_TYPE_NX_PXA5 430 -#define MACH_TYPE_BLACKBOARD2 431 -#define MACH_TYPE_I819 432 -#define MACH_TYPE_IXMB995E 433 -#define MACH_TYPE_SKYRIDER 434 -#define MACH_TYPE_SKYHAWK 435 -#define MACH_TYPE_ENTERPRISE 436 -#define MACH_TYPE_DEP2410 437 -#define MACH_TYPE_ARMCORE 438 -#define MACH_TYPE_HOBBIT 439 -#define MACH_TYPE_H7210 440 -#define MACH_TYPE_PXA_NETDCU5 441 -#define MACH_TYPE_ACC 442 -#define MACH_TYPE_ESL_SARVA 443 -#define MACH_TYPE_XM250 444 -#define MACH_TYPE_T6TC1XB 445 -#define MACH_TYPE_ESS710 446 -#define MACH_TYPE_MX31ADS 447 -#define MACH_TYPE_HIMALAYA 448 -#define MACH_TYPE_BOLFENK 449 -#define MACH_TYPE_AT91RM9200KR 450 -#define MACH_TYPE_EDB9312 451 -#define MACH_TYPE_OMAP_GENERIC 452 -#define MACH_TYPE_AXIMX3 453 -#define MACH_TYPE_EB67XDIP 454 -#define MACH_TYPE_WEBTXS 455 -#define MACH_TYPE_HAWK 456 -#define MACH_TYPE_CCAT91SBC001 457 -#define MACH_TYPE_EXPRESSO 458 -#define MACH_TYPE_H4000 459 -#define MACH_TYPE_DINO 460 -#define MACH_TYPE_ML675K 461 -#define MACH_TYPE_EDB9301 462 -#define MACH_TYPE_EDB9315 463 -#define MACH_TYPE_RECIVA_TT 464 -#define MACH_TYPE_CSTCB01 465 -#define MACH_TYPE_CSTCB1 466 -#define MACH_TYPE_SHADWELL 467 -#define MACH_TYPE_GOEPEL263 468 -#define MACH_TYPE_ACQ100 469 -#define MACH_TYPE_MX1FS2 470 -#define MACH_TYPE_HIPTOP_G1 471 -#define MACH_TYPE_SPARKY 472 -#define MACH_TYPE_NS9750 473 -#define MACH_TYPE_PHOENIX 474 -#define MACH_TYPE_VR1000 475 -#define MACH_TYPE_DEISTERPXA 476 -#define MACH_TYPE_BCM1160 477 -#define MACH_TYPE_PCM022 478 -#define MACH_TYPE_ADSGCX 479 -#define MACH_TYPE_DREADNAUGHT 480 -#define MACH_TYPE_DM320 481 -#define MACH_TYPE_MARKOV 482 -#define MACH_TYPE_COS7A400 483 -#define MACH_TYPE_MILANO 484 -#define MACH_TYPE_UE9328 485 -#define MACH_TYPE_UEX255 486 -#define MACH_TYPE_UE2410 487 -#define MACH_TYPE_A620 488 -#define MACH_TYPE_OCELOT 489 -#define MACH_TYPE_CHEETAH 490 -#define MACH_TYPE_OMAP_PERSEUS2 491 -#define MACH_TYPE_ZVUE 492 -#define MACH_TYPE_ROVERP1 493 -#define MACH_TYPE_ASIDIAL2 494 -#define MACH_TYPE_S3C24A0 495 -#define MACH_TYPE_E800 496 -#define MACH_TYPE_E750 497 -#define MACH_TYPE_S3C5500 498 -#define MACH_TYPE_SMDK5500 499 -#define MACH_TYPE_SIGNALSYNC 500 -#define MACH_TYPE_NBC 501 -#define MACH_TYPE_KODIAK 502 -#define MACH_TYPE_NETBOOKPRO 503 -#define MACH_TYPE_HW90200 504 -#define MACH_TYPE_CONDOR 505 -#define MACH_TYPE_CUP 506 -#define MACH_TYPE_KITE 507 -#define MACH_TYPE_SCB9328 508 -#define MACH_TYPE_OMAP_H3 509 -#define MACH_TYPE_OMAP_H4 510 -#define MACH_TYPE_N10 511 -#define MACH_TYPE_MONTAJADE 512 -#define MACH_TYPE_SG560 513 -#define MACH_TYPE_DP1000 514 -#define MACH_TYPE_OMAP_OSK 515 -#define MACH_TYPE_RG100V3 516 -#define MACH_TYPE_MX2ADS 517 -#define MACH_TYPE_PXA_KILO 518 -#define MACH_TYPE_IXP4XX_EAGLE 519 -#define MACH_TYPE_TOSA 520 -#define MACH_TYPE_MB2520F 521 -#define MACH_TYPE_EMC1000 522 -#define MACH_TYPE_TIDSC25 523 -#define MACH_TYPE_AKCPMXL 524 -#define MACH_TYPE_AV3XX 525 -#define MACH_TYPE_AVILA 526 -#define MACH_TYPE_PXA_MPM10 527 -#define MACH_TYPE_PXA_KYANITE 528 -#define MACH_TYPE_SGOLD 529 -#define MACH_TYPE_OSCAR 530 -#define MACH_TYPE_EPXA4USB2 531 -#define MACH_TYPE_XSENGINE 532 -#define MACH_TYPE_IP600 533 -#define MACH_TYPE_MCAN2 534 -#define MACH_TYPE_DDI_BLUERIDGE 535 -#define MACH_TYPE_SKYMINDER 536 -#define MACH_TYPE_LPD79520 537 -#define MACH_TYPE_EDB9302 538 -#define MACH_TYPE_HW90340 539 -#define MACH_TYPE_CIP_BOX 540 -#define MACH_TYPE_IVPN 541 -#define MACH_TYPE_RSOC2 542 -#define MACH_TYPE_HUSKY 543 -#define MACH_TYPE_BOXER 544 -#define MACH_TYPE_SHEPHERD 545 -#define MACH_TYPE_AML42800AA 546 -#define MACH_TYPE_LPC2294 548 -#define MACH_TYPE_SWITCHGRASS 549 -#define MACH_TYPE_ENS_CMU 550 -#define MACH_TYPE_MM6_SDB 551 -#define MACH_TYPE_SATURN 552 -#define MACH_TYPE_I30030EVB 553 -#define MACH_TYPE_MXC27530EVB 554 -#define MACH_TYPE_SMDK2800 555 -#define MACH_TYPE_MTWILSON 556 -#define MACH_TYPE_ZITI 557 -#define MACH_TYPE_GRANDFATHER 558 -#define MACH_TYPE_TENGINE 559 -#define MACH_TYPE_S3C2460 560 -#define MACH_TYPE_PDM 561 -#define MACH_TYPE_H4700 562 -#define MACH_TYPE_H6300 563 -#define MACH_TYPE_RZ1700 564 -#define MACH_TYPE_A716 565 -#define MACH_TYPE_ESTK2440A 566 -#define MACH_TYPE_ATWIXP425 567 -#define MACH_TYPE_CSB336 568 -#define MACH_TYPE_RIRM2 569 -#define MACH_TYPE_CX23518 570 -#define MACH_TYPE_CX2351X 571 -#define MACH_TYPE_COMPUTIME 572 -#define MACH_TYPE_IZARUS 573 -#define MACH_TYPE_RTS 574 -#define MACH_TYPE_SE5100 575 -#define MACH_TYPE_S3C2510 576 -#define MACH_TYPE_CSB437TL 577 -#define MACH_TYPE_SLAUSON 578 -#define MACH_TYPE_PEARLRIVER 579 -#define MACH_TYPE_TDC_P210 580 -#define MACH_TYPE_SG580 581 -#define MACH_TYPE_WRSBCARM7 582 -#define MACH_TYPE_IPD 583 -#define MACH_TYPE_PXA_DNP2110 584 -#define MACH_TYPE_XAENIAX 585 -#define MACH_TYPE_SOMN4250 586 -#define MACH_TYPE_PLEB2 587 -#define MACH_TYPE_CORNWALLIS 588 -#define MACH_TYPE_GURNEY_DRV 589 -#define MACH_TYPE_CHAFFEE 590 -#define MACH_TYPE_RMS101 591 -#define MACH_TYPE_RX3715 592 -#define MACH_TYPE_SWIFT 593 -#define MACH_TYPE_ROVERP7 594 -#define MACH_TYPE_PR818S 595 -#define MACH_TYPE_TRXPRO 596 -#define MACH_TYPE_NSLU2 597 -#define MACH_TYPE_E400 598 -#define MACH_TYPE_TRAB 599 -#define MACH_TYPE_CMC_PU2 600 -#define MACH_TYPE_FULCRUM 601 -#define MACH_TYPE_NETGATE42X 602 -#define MACH_TYPE_STR710 603 -#define MACH_TYPE_IXDPG425 604 -#define MACH_TYPE_TOMTOMGO 605 -#define MACH_TYPE_VERSATILE_AB 606 -#define MACH_TYPE_EDB9307 607 -#define MACH_TYPE_SG565 608 -#define MACH_TYPE_LPD79524 609 -#define MACH_TYPE_LPD79525 610 -#define MACH_TYPE_RMS100 611 -#define MACH_TYPE_KB9200 612 -#define MACH_TYPE_SX1 613 -#define MACH_TYPE_HMS39C7092 614 -#define MACH_TYPE_ARMADILLO 615 -#define MACH_TYPE_IPCU 616 -#define MACH_TYPE_LOOX720 617 -#define MACH_TYPE_IXDP465 618 -#define MACH_TYPE_IXDP2351 619 -#define MACH_TYPE_ADSVIX 620 -#define MACH_TYPE_DM270 621 -#define MACH_TYPE_SOCLTPLUS 622 -#define MACH_TYPE_ECIA 623 -#define MACH_TYPE_CM4008 624 -#define MACH_TYPE_P2001 625 -#define MACH_TYPE_TWISTER 626 -#define MACH_TYPE_MUDSHARK 627 -#define MACH_TYPE_HB2 628 -#define MACH_TYPE_IQ80332 629 -#define MACH_TYPE_SENDT 630 -#define MACH_TYPE_MX2JAZZ 631 -#define MACH_TYPE_MULTIIO 632 -#define MACH_TYPE_HRDISPLAY 633 -#define MACH_TYPE_MXC27530ADS 634 -#define MACH_TYPE_TRIZEPS3 635 -#define MACH_TYPE_ZEFEERDZA 636 -#define MACH_TYPE_ZEFEERDZB 637 -#define MACH_TYPE_ZEFEERDZG 638 -#define MACH_TYPE_ZEFEERDZN 639 -#define MACH_TYPE_ZEFEERDZQ 640 -#define MACH_TYPE_GTWX5715 641 -#define MACH_TYPE_ASTRO_JACK 643 -#define MACH_TYPE_TIP03 644 -#define MACH_TYPE_A9200EC 645 -#define MACH_TYPE_PNX0105 646 -#define MACH_TYPE_ADCPOECPU 647 -#define MACH_TYPE_CSB637 648 -#define MACH_TYPE_MB9200 650 -#define MACH_TYPE_KULUN 651 -#define MACH_TYPE_SNAPPER 652 -#define MACH_TYPE_OPTIMA 653 -#define MACH_TYPE_DLHSBC 654 -#define MACH_TYPE_X30 655 -#define MACH_TYPE_N30 656 -#define MACH_TYPE_MANGA_KS8695 657 -#define MACH_TYPE_AJAX 658 -#define MACH_TYPE_NEC_MP900 659 -#define MACH_TYPE_VVTK1000 661 -#define MACH_TYPE_KAFA 662 -#define MACH_TYPE_VVTK3000 663 -#define MACH_TYPE_PIMX1 664 -#define MACH_TYPE_OLLIE 665 -#define MACH_TYPE_SKYMAX 666 -#define MACH_TYPE_JAZZ 667 -#define MACH_TYPE_TEL_T3 668 -#define MACH_TYPE_AISINO_FCR255 669 -#define MACH_TYPE_BTWEB 670 -#define MACH_TYPE_DBG_LH79520 671 -#define MACH_TYPE_CM41XX 672 -#define MACH_TYPE_TS72XX 673 -#define MACH_TYPE_NGGPXA 674 -#define MACH_TYPE_CSB535 675 -#define MACH_TYPE_CSB536 676 -#define MACH_TYPE_PXA_TRAKPOD 677 -#define MACH_TYPE_PRAXIS 678 -#define MACH_TYPE_LH75411 679 -#define MACH_TYPE_OTOM 680 -#define MACH_TYPE_NEXCODER_2440 681 -#define MACH_TYPE_LOOX410 682 -#define MACH_TYPE_WESTLAKE 683 -#define MACH_TYPE_NSB 684 -#define MACH_TYPE_ESL_SARVA_STN 685 -#define MACH_TYPE_ESL_SARVA_TFT 686 -#define MACH_TYPE_ESL_SARVA_IAD 687 -#define MACH_TYPE_ESL_SARVA_ACC 688 -#define MACH_TYPE_TYPHOON 689 -#define MACH_TYPE_CNAV 690 -#define MACH_TYPE_A730 691 -#define MACH_TYPE_NETSTAR 692 -#define MACH_TYPE_PHASEFALE_SUPERCON 693 -#define MACH_TYPE_SHIVA1100 694 -#define MACH_TYPE_ETEXSC 695 -#define MACH_TYPE_IXDPG465 696 -#define MACH_TYPE_A9M2410 697 -#define MACH_TYPE_A9M2440 698 -#define MACH_TYPE_A9M9750 699 -#define MACH_TYPE_A9M9360 700 -#define MACH_TYPE_UNC90 701 -#define MACH_TYPE_ECO920 702 -#define MACH_TYPE_SATVIEW 703 -#define MACH_TYPE_ROADRUNNER 704 -#define MACH_TYPE_AT91RM9200EK 705 -#define MACH_TYPE_GP32 706 -#define MACH_TYPE_GEM 707 -#define MACH_TYPE_I858 708 -#define MACH_TYPE_HX2750 709 -#define MACH_TYPE_MXC91131EVB 710 -#define MACH_TYPE_P700 711 -#define MACH_TYPE_CPE 712 -#define MACH_TYPE_SPITZ 713 -#define MACH_TYPE_NIMBRA340 714 -#define MACH_TYPE_LPC22XX 715 -#define MACH_TYPE_COMET3 716 -#define MACH_TYPE_COMET4 717 -#define MACH_TYPE_CSB625 718 -#define MACH_TYPE_FORTUNET2 719 -#define MACH_TYPE_S5H2200 720 -#define MACH_TYPE_OPTORM920 721 -#define MACH_TYPE_ADSBITSYXB 722 -#define MACH_TYPE_ADSSPHERE 723 -#define MACH_TYPE_ADSPORTAL 724 -#define MACH_TYPE_LN2410SBC 725 -#define MACH_TYPE_CB3RUFC 726 -#define MACH_TYPE_MP2USB 727 -#define MACH_TYPE_NTNP425C 728 -#define MACH_TYPE_COLIBRI 729 -#define MACH_TYPE_PCM7220 730 -#define MACH_TYPE_GATEWAY7001 731 -#define MACH_TYPE_PCM027 732 -#define MACH_TYPE_CMPXA 733 -#define MACH_TYPE_ANUBIS 734 -#define MACH_TYPE_ITE8152 735 -#define MACH_TYPE_LPC3XXX 736 -#define MACH_TYPE_PUPPETEER 737 -#define MACH_TYPE_E570 739 -#define MACH_TYPE_X50 740 -#define MACH_TYPE_RECON 741 -#define MACH_TYPE_XBOARDGP8 742 -#define MACH_TYPE_FPIC2 743 -#define MACH_TYPE_AKITA 744 -#define MACH_TYPE_A81 745 -#define MACH_TYPE_SVM_SC25X 746 -#define MACH_TYPE_VADATECH020 747 -#define MACH_TYPE_TLI 748 -#define MACH_TYPE_EDB9315LC 749 -#define MACH_TYPE_PASSEC 750 -#define MACH_TYPE_DS_TIGER 751 -#define MACH_TYPE_E310 752 -#define MACH_TYPE_E330 753 -#define MACH_TYPE_RT3000 754 -#define MACH_TYPE_NOKIA770 755 -#define MACH_TYPE_PNX0106 756 -#define MACH_TYPE_HX21XX 757 -#define MACH_TYPE_FARADAY 758 -#define MACH_TYPE_SBC9312 759 -#define MACH_TYPE_BATMAN 760 -#define MACH_TYPE_JPD201 761 -#define MACH_TYPE_MIPSA 762 -#define MACH_TYPE_KACOM 763 -#define MACH_TYPE_SWARCOCPU 764 -#define MACH_TYPE_SWARCODSL 765 -#define MACH_TYPE_BLUEANGEL 766 -#define MACH_TYPE_HAIRYGRAMA 767 -#define MACH_TYPE_BANFF 768 -#define MACH_TYPE_CARMEVA 769 -#define MACH_TYPE_SAM255 770 -#define MACH_TYPE_PPM10 771 -#define MACH_TYPE_EDB9315A 772 -#define MACH_TYPE_SUNSET 773 -#define MACH_TYPE_STARGATE2 774 -#define MACH_TYPE_INTELMOTE2 775 -#define MACH_TYPE_TRIZEPS4 776 -#define MACH_TYPE_MAINSTONE2 777 -#define MACH_TYPE_EZ_IXP42X 778 -#define MACH_TYPE_TAPWAVE_ZODIAC 779 -#define MACH_TYPE_UNIVERSALMETER 780 -#define MACH_TYPE_HICOARM9 781 -#define MACH_TYPE_PNX4008 782 -#define MACH_TYPE_KWS6000 783 -#define MACH_TYPE_PORTUX920T 784 -#define MACH_TYPE_EZ_X5 785 -#define MACH_TYPE_OMAP_RUDOLPH 786 -#define MACH_TYPE_CPUAT91 787 -#define MACH_TYPE_REA9200 788 -#define MACH_TYPE_ACTS_PUNE_SA1110 789 -#define MACH_TYPE_IXP425 790 -#define MACH_TYPE_I30030ADS 791 -#define MACH_TYPE_PERCH 792 -#define MACH_TYPE_EIS05R1 793 -#define MACH_TYPE_PEPPERPAD 794 -#define MACH_TYPE_SB3010 795 -#define MACH_TYPE_RM9200 796 -#define MACH_TYPE_DMA03 797 -#define MACH_TYPE_ROAD_S101 798 -#define MACH_TYPE_IQ81340SC 799 -#define MACH_TYPE_IQ_NEXTGEN_B 800 -#define MACH_TYPE_IQ81340MC 801 -#define MACH_TYPE_IQ_NEXTGEN_D 802 -#define MACH_TYPE_IQ_NEXTGEN_E 803 -#define MACH_TYPE_MALLOW_AT91 804 -#define MACH_TYPE_CYBERTRACKER_I 805 -#define MACH_TYPE_GESBC931X 806 -#define MACH_TYPE_CENTIPAD 807 -#define MACH_TYPE_ARMSOC 808 -#define MACH_TYPE_SE4200 809 -#define MACH_TYPE_EMS197A 810 -#define MACH_TYPE_MICRO9 811 -#define MACH_TYPE_MICRO9L 812 -#define MACH_TYPE_UC5471DSP 813 -#define MACH_TYPE_SJ5471ENG 814 -#define MACH_TYPE_CMPXA26X 815 -#define MACH_TYPE_NC 816 -#define MACH_TYPE_OMAP_PALMTE 817 -#define MACH_TYPE_AJAX52X 818 -#define MACH_TYPE_SIRIUSTAR 819 -#define MACH_TYPE_IODATA_HDLG 820 -#define MACH_TYPE_AT91RM9200UTL 821 -#define MACH_TYPE_BIOSAFE 822 -#define MACH_TYPE_MP1000 823 -#define MACH_TYPE_PARSY 824 -#define MACH_TYPE_CCXP 825 -#define MACH_TYPE_OMAP_GSAMPLE 826 -#define MACH_TYPE_REALVIEW_EB 827 -#define MACH_TYPE_SAMOA 828 -#define MACH_TYPE_PALMT3 829 -#define MACH_TYPE_I878 830 -#define MACH_TYPE_BORZOI 831 -#define MACH_TYPE_GECKO 832 -#define MACH_TYPE_DS101 833 -#define MACH_TYPE_OMAP_PALMTT2 834 -#define MACH_TYPE_PALMLD 835 -#define MACH_TYPE_CC9C 836 -#define MACH_TYPE_SBC1670 837 -#define MACH_TYPE_IXDP28X5 838 -#define MACH_TYPE_OMAP_PALMTT 839 -#define MACH_TYPE_ML696K 840 -#define MACH_TYPE_ARCOM_ZEUS 841 -#define MACH_TYPE_OSIRIS 842 -#define MACH_TYPE_MAESTRO 843 -#define MACH_TYPE_PALMTE2 844 -#define MACH_TYPE_IXBBM 845 -#define MACH_TYPE_MX27ADS 846 -#define MACH_TYPE_AX8004 847 -#define MACH_TYPE_AT91SAM9261EK 848 -#define MACH_TYPE_LOFT 849 -#define MACH_TYPE_MAGPIE 850 -#define MACH_TYPE_MX21ADS 851 -#define MACH_TYPE_MB87M3400 852 -#define MACH_TYPE_MGUARD_DELTA 853 -#define MACH_TYPE_DAVINCI_DVDP 854 -#define MACH_TYPE_HTCUNIVERSAL 855 -#define MACH_TYPE_TPAD 856 -#define MACH_TYPE_ROVERP3 857 -#define MACH_TYPE_JORNADA928 858 -#define MACH_TYPE_MV88FXX81 859 -#define MACH_TYPE_STMP36XX 860 -#define MACH_TYPE_SXNI79524 861 -#define MACH_TYPE_AMS_DELTA 862 -#define MACH_TYPE_URANIUM 863 -#define MACH_TYPE_UCON 864 -#define MACH_TYPE_NAS100D 865 -#define MACH_TYPE_L083_1000 866 -#define MACH_TYPE_EZX 867 -#define MACH_TYPE_PNX5220 868 -#define MACH_TYPE_BUTTE 869 -#define MACH_TYPE_SRM2 870 -#define MACH_TYPE_DSBR 871 -#define MACH_TYPE_CRYSTALBALL 872 -#define MACH_TYPE_TINYPXA27X 873 -#define MACH_TYPE_HERBIE 874 -#define MACH_TYPE_MAGICIAN 875 -#define MACH_TYPE_CM4002 876 -#define MACH_TYPE_B4 877 -#define MACH_TYPE_MAUI 878 -#define MACH_TYPE_CYBERTRACKER_G 879 -#define MACH_TYPE_NXDKN 880 -#define MACH_TYPE_MIO8390 881 -#define MACH_TYPE_OMI_BOARD 882 -#define MACH_TYPE_MX21CIV 883 -#define MACH_TYPE_MAHI_CDAC 884 -#define MACH_TYPE_PALMTX 885 -#define MACH_TYPE_S3C2413 887 -#define MACH_TYPE_SAMSYS_EP0 888 -#define MACH_TYPE_WG302V1 889 -#define MACH_TYPE_WG302V2 890 -#define MACH_TYPE_EB42X 891 -#define MACH_TYPE_IQ331ES 892 -#define MACH_TYPE_COSYDSP 893 -#define MACH_TYPE_UPLAT7D 894 -#define MACH_TYPE_PTDAVINCI 895 -#define MACH_TYPE_MBUS 896 -#define MACH_TYPE_NADIA2VB 897 -#define MACH_TYPE_R1000 898 -#define MACH_TYPE_HW90250 899 -#define MACH_TYPE_OMAP_2430SDP 900 -#define MACH_TYPE_DAVINCI_EVM 901 -#define MACH_TYPE_OMAP_TORNADO 902 -#define MACH_TYPE_OLOCREEK 903 -#define MACH_TYPE_PALMZ72 904 -#define MACH_TYPE_NXDB500 905 -#define MACH_TYPE_APF9328 906 -#define MACH_TYPE_OMAP_WIPOQ 907 -#define MACH_TYPE_OMAP_TWIP 908 -#define MACH_TYPE_TREO650 909 -#define MACH_TYPE_ACUMEN 910 -#define MACH_TYPE_XP100 911 -#define MACH_TYPE_FS2410 912 -#define MACH_TYPE_PXA270_CERF 913 -#define MACH_TYPE_SQ2FTLPALM 914 -#define MACH_TYPE_BSEMSERVER 915 -#define MACH_TYPE_NETCLIENT 916 -#define MACH_TYPE_PALMT5 917 -#define MACH_TYPE_PALMTC 918 -#define MACH_TYPE_OMAP_APOLLON 919 -#define MACH_TYPE_MXC30030EVB 920 -#define MACH_TYPE_REA_2D 921 -#define MACH_TYPE_TI3E524 922 -#define MACH_TYPE_ATEB9200 923 -#define MACH_TYPE_AUCKLAND 924 -#define MACH_TYPE_AK3320M 925 -#define MACH_TYPE_DURAMAX 926 -#define MACH_TYPE_N35 927 -#define MACH_TYPE_PRONGHORN 928 -#define MACH_TYPE_FUNDY 929 -#define MACH_TYPE_LOGICPD_PXA270 930 -#define MACH_TYPE_CPU777 931 -#define MACH_TYPE_SIMICON9201 932 -#define MACH_TYPE_LEAP2_HPM 933 -#define MACH_TYPE_CM922TXA10 934 -#define MACH_TYPE_PXA 935 -#define MACH_TYPE_SANDGATE2 936 -#define MACH_TYPE_SANDGATE2G 937 -#define MACH_TYPE_SANDGATE2P 938 -#define MACH_TYPE_FRED_JACK 939 -#define MACH_TYPE_TTG_COLOR1 940 -#define MACH_TYPE_NXEB500HMI 941 -#define MACH_TYPE_NETDCU8 942 -#define MACH_TYPE_NG_FVX538 944 -#define MACH_TYPE_NG_FVS338 945 -#define MACH_TYPE_PNX4103 946 -#define MACH_TYPE_HESDB 947 -#define MACH_TYPE_XSILO 948 -#define MACH_TYPE_ESPRESSO 949 -#define MACH_TYPE_EMLC 950 -#define MACH_TYPE_SISTERON 951 -#define MACH_TYPE_RX1950 952 -#define MACH_TYPE_TSC_VENUS 953 -#define MACH_TYPE_DS101J 954 -#define MACH_TYPE_MXC30030ADS 955 -#define MACH_TYPE_FUJITSU_WIMAXSOC 956 -#define MACH_TYPE_DUALPCMODEM 957 -#define MACH_TYPE_GESBC9312 958 -#define MACH_TYPE_HTCAPACHE 959 -#define MACH_TYPE_IXDP435 960 -#define MACH_TYPE_CATPROVT100 961 -#define MACH_TYPE_PICOTUX1XX 962 -#define MACH_TYPE_PICOTUX2XX 963 -#define MACH_TYPE_DSMG600 964 -#define MACH_TYPE_EMPC2 965 -#define MACH_TYPE_VENTURA 966 -#define MACH_TYPE_PHIDGET_SBC 967 -#define MACH_TYPE_IJ3K 968 -#define MACH_TYPE_PISGAH 969 -#define MACH_TYPE_OMAP_FSAMPLE 970 -#define MACH_TYPE_SG720 971 -#define MACH_TYPE_REDFOX 972 -#define MACH_TYPE_MYSH_EP9315_1 973 -#define MACH_TYPE_TPF106 974 -#define MACH_TYPE_AT91RM9200KG 975 -#define MACH_TYPE_SLEDB 976 -#define MACH_TYPE_ONTRACK 977 -#define MACH_TYPE_PM1200 978 -#define MACH_TYPE_ESS24XXX 979 -#define MACH_TYPE_COREMP7 980 -#define MACH_TYPE_NEXCODER_6446 981 -#define MACH_TYPE_STVC8380 982 -#define MACH_TYPE_TEKLYNX 983 -#define MACH_TYPE_CARBONADO 984 -#define MACH_TYPE_SYSMOS_MP730 985 -#define MACH_TYPE_SNAPPER_CL15 986 -#define MACH_TYPE_PGIGIM 987 -#define MACH_TYPE_PTX9160P2 988 -#define MACH_TYPE_DCORE1 989 -#define MACH_TYPE_VICTORPXA 990 -#define MACH_TYPE_MX2DTB 991 -#define MACH_TYPE_PXA_IREX_ER0100 992 -#define MACH_TYPE_OMAP_PALMZ71 993 -#define MACH_TYPE_BARTEC_DEG 994 -#define MACH_TYPE_HW50251 995 -#define MACH_TYPE_IBOX 996 -#define MACH_TYPE_ATLASLH7A404 997 -#define MACH_TYPE_PT2026 998 -#define MACH_TYPE_HTCALPINE 999 -#define MACH_TYPE_BARTEC_VTU 1000 -#define MACH_TYPE_VCOREII 1001 -#define MACH_TYPE_PDNB3 1002 -#define MACH_TYPE_HTCBEETLES 1003 -#define MACH_TYPE_S3C6400 1004 -#define MACH_TYPE_S3C2443 1005 -#define MACH_TYPE_OMAP_LDK 1006 -#define MACH_TYPE_SMDK2460 1007 -#define MACH_TYPE_SMDK2440 1008 -#define MACH_TYPE_SMDK2412 1009 -#define MACH_TYPE_WEBBOX 1010 -#define MACH_TYPE_CWWNDP 1011 -#define MACH_TYPE_DRAGON 1012 -#define MACH_TYPE_OPENDO_CPU_BOARD 1013 -#define MACH_TYPE_CCM2200 1014 -#define MACH_TYPE_ETWARM 1015 -#define MACH_TYPE_M93030 1016 -#define MACH_TYPE_CC7U 1017 -#define MACH_TYPE_MTT_RANGER 1018 -#define MACH_TYPE_NEXUS 1019 -#define MACH_TYPE_DESMAN 1020 -#define MACH_TYPE_BKDE303 1021 -#define MACH_TYPE_SMDK2413 1022 -#define MACH_TYPE_AML_M7200 1023 -#define MACH_TYPE_AML_M5900 1024 -#define MACH_TYPE_SG640 1025 -#define MACH_TYPE_EDG79524 1026 -#define MACH_TYPE_AI2410 1027 -#define MACH_TYPE_IXP465 1028 -#define MACH_TYPE_BALLOON3 1029 -#define MACH_TYPE_HEINS 1030 -#define MACH_TYPE_MPLUSEVA 1031 -#define MACH_TYPE_RT042 1032 -#define MACH_TYPE_CWIEM 1033 -#define MACH_TYPE_CM_X270 1034 -#define MACH_TYPE_CM_X255 1035 -#define MACH_TYPE_ESH_AT91 1036 -#define MACH_TYPE_SANDGATE3 1037 -#define MACH_TYPE_PRIMO 1038 -#define MACH_TYPE_GEMSTONE 1039 -#define MACH_TYPE_PRONGHORNMETRO 1040 -#define MACH_TYPE_SIDEWINDER 1041 -#define MACH_TYPE_PICOMOD1 1042 -#define MACH_TYPE_SG590 1043 -#define MACH_TYPE_AKAI9307 1044 -#define MACH_TYPE_FONTAINE 1045 -#define MACH_TYPE_WOMBAT 1046 -#define MACH_TYPE_ACQ300 1047 -#define MACH_TYPE_MOD_270 1048 -#define MACH_TYPE_VC0820 1049 -#define MACH_TYPE_ANI_AIM 1050 -#define MACH_TYPE_JELLYFISH 1051 -#define MACH_TYPE_AMANITA 1052 -#define MACH_TYPE_VLINK 1053 -#define MACH_TYPE_DEXFLEX 1054 -#define MACH_TYPE_EIGEN_TTQ 1055 -#define MACH_TYPE_ARCOM_TITAN 1056 -#define MACH_TYPE_TABLA 1057 -#define MACH_TYPE_MDIRAC3 1058 -#define MACH_TYPE_MRHFBP2 1059 -#define MACH_TYPE_AT91RM9200RB 1060 -#define MACH_TYPE_ANI_APM 1061 -#define MACH_TYPE_ELLA1 1062 -#define MACH_TYPE_INHAND_PXA27X 1063 -#define MACH_TYPE_INHAND_PXA25X 1064 -#define MACH_TYPE_EMPOS_XM 1065 -#define MACH_TYPE_EMPOS 1066 -#define MACH_TYPE_EMPOS_TINY 1067 -#define MACH_TYPE_EMPOS_SM 1068 -#define MACH_TYPE_EGRET 1069 -#define MACH_TYPE_OSTRICH 1070 -#define MACH_TYPE_N50 1071 -#define MACH_TYPE_ECBAT91 1072 -#define MACH_TYPE_STAREAST 1073 -#define MACH_TYPE_DSPG_DW 1074 -#define MACH_TYPE_ONEARM 1075 -#define MACH_TYPE_MRG110_6 1076 -#define MACH_TYPE_WRT300NV2 1077 -#define MACH_TYPE_XM_BULVERDE 1078 -#define MACH_TYPE_MSM6100 1079 -#define MACH_TYPE_ETI_B1 1080 -#define MACH_TYPE_ZILOG_ZA9L 1081 -#define MACH_TYPE_BIT2440 1082 -#define MACH_TYPE_NBI 1083 -#define MACH_TYPE_SMDK2443 1084 -#define MACH_TYPE_VDAVINCI 1085 -#define MACH_TYPE_ATC6 1086 -#define MACH_TYPE_MULTMDW 1087 -#define MACH_TYPE_MBA2440 1088 -#define MACH_TYPE_ECSD 1089 -#define MACH_TYPE_PALMZ31 1090 -#define MACH_TYPE_FSG 1091 -#define MACH_TYPE_RAZOR101 1092 -#define MACH_TYPE_OPERA_TDM 1093 -#define MACH_TYPE_COMCERTO 1094 -#define MACH_TYPE_TB0319 1095 -#define MACH_TYPE_KWS8000 1096 -#define MACH_TYPE_B2 1097 -#define MACH_TYPE_LCL54 1098 -#define MACH_TYPE_AT91SAM9260EK 1099 -#define MACH_TYPE_GLANTANK 1100 -#define MACH_TYPE_N2100 1101 -#define MACH_TYPE_N4100 1102 -#define MACH_TYPE_VERTICAL_RSC4 1103 -#define MACH_TYPE_SG8100 1104 -#define MACH_TYPE_IM42XX 1105 -#define MACH_TYPE_FTXX 1106 -#define MACH_TYPE_LWFUSION 1107 -#define MACH_TYPE_QT2410 1108 -#define MACH_TYPE_KIXRP435 1109 -#define MACH_TYPE_CCW9C 1110 -#define MACH_TYPE_DABHS 1111 -#define MACH_TYPE_GZMX 1112 -#define MACH_TYPE_IPNW100AP 1113 -#define MACH_TYPE_CC9P9360DEV 1114 -#define MACH_TYPE_CC9P9750DEV 1115 -#define MACH_TYPE_CC9P9360VAL 1116 -#define MACH_TYPE_CC9P9750VAL 1117 -#define MACH_TYPE_NX70V 1118 -#define MACH_TYPE_AT91RM9200DF 1119 -#define MACH_TYPE_SE_PILOT2 1120 -#define MACH_TYPE_MTCN_T800 1121 -#define MACH_TYPE_VCMX212 1122 -#define MACH_TYPE_LYNX 1123 -#define MACH_TYPE_AT91SAM9260ID 1124 -#define MACH_TYPE_HW86052 1125 -#define MACH_TYPE_PILZ_PMI3 1126 -#define MACH_TYPE_EDB9302A 1127 -#define MACH_TYPE_EDB9307A 1128 -#define MACH_TYPE_CT_DFS 1129 -#define MACH_TYPE_PILZ_PMI4 1130 -#define MACH_TYPE_XCEEDNP_IXP 1131 -#define MACH_TYPE_SMDK2442B 1132 -#define MACH_TYPE_XNODE 1133 -#define MACH_TYPE_AIDX270 1134 -#define MACH_TYPE_REMA 1135 -#define MACH_TYPE_BPS1000 1136 -#define MACH_TYPE_HW90350 1137 -#define MACH_TYPE_OMAP_3430SDP 1138 -#define MACH_TYPE_BLUETOUCH 1139 -#define MACH_TYPE_VSTMS 1140 -#define MACH_TYPE_XSBASE270 1141 -#define MACH_TYPE_AT91SAM9260EK_CN 1142 -#define MACH_TYPE_ADSTURBOXB 1143 -#define MACH_TYPE_OTI4110 1144 -#define MACH_TYPE_HME_PXA 1145 -#define MACH_TYPE_DEISTERDCA 1146 -#define MACH_TYPE_CES_SSEM2 1147 -#define MACH_TYPE_CES_MTR 1148 -#define MACH_TYPE_TDS_AVNG_SBC 1149 -#define MACH_TYPE_EVEREST 1150 -#define MACH_TYPE_PNX4010 1151 -#define MACH_TYPE_OXNAS 1152 -#define MACH_TYPE_FIORI 1153 -#define MACH_TYPE_ML1200 1154 -#define MACH_TYPE_PECOS 1155 -#define MACH_TYPE_NB2XXX 1156 -#define MACH_TYPE_HW6900 1157 -#define MACH_TYPE_CDCS_QUOLL 1158 -#define MACH_TYPE_QUICKSILVER 1159 -#define MACH_TYPE_UPLAT926 1160 -#define MACH_TYPE_DEP2410_THOMAS 1161 -#define MACH_TYPE_DTK2410 1162 -#define MACH_TYPE_CHILI 1163 -#define MACH_TYPE_DEMETER 1164 -#define MACH_TYPE_DIONYSUS 1165 -#define MACH_TYPE_AS352X 1166 -#define MACH_TYPE_SERVICE 1167 -#define MACH_TYPE_CS_E9301 1168 -#define MACH_TYPE_MICRO9M 1169 -#define MACH_TYPE_IA_MOSPCK 1170 -#define MACH_TYPE_QL201B 1171 -#define MACH_TYPE_BBM 1174 -#define MACH_TYPE_EXXX 1175 -#define MACH_TYPE_WMA11B 1176 -#define MACH_TYPE_PELCO_ATLAS 1177 -#define MACH_TYPE_G500 1178 -#define MACH_TYPE_BUG 1179 -#define MACH_TYPE_MX33ADS 1180 -#define MACH_TYPE_CHUB 1181 -#define MACH_TYPE_NEO1973_GTA01 1182 -#define MACH_TYPE_W90N740 1183 -#define MACH_TYPE_MEDALLION_SA2410 1184 -#define MACH_TYPE_IA_CPU_9200_2 1185 -#define MACH_TYPE_DIMMRM9200 1186 -#define MACH_TYPE_PM9261 1187 -#define MACH_TYPE_ML7304 1189 -#define MACH_TYPE_UCP250 1190 -#define MACH_TYPE_INTBOARD 1191 -#define MACH_TYPE_GULFSTREAM 1192 -#define MACH_TYPE_LABQUEST 1193 -#define MACH_TYPE_VCMX313 1194 -#define MACH_TYPE_URG200 1195 -#define MACH_TYPE_CPUX255LCDNET 1196 -#define MACH_TYPE_NETDCU9 1197 -#define MACH_TYPE_NETDCU10 1198 -#define MACH_TYPE_DSPG_DGA 1199 -#define MACH_TYPE_DSPG_DVW 1200 -#define MACH_TYPE_SOLOS 1201 -#define MACH_TYPE_AT91SAM9263EK 1202 -#define MACH_TYPE_OSSTBOX 1203 -#define MACH_TYPE_KBAT9261 1204 -#define MACH_TYPE_CT1100 1205 -#define MACH_TYPE_AKCPPXA 1206 -#define MACH_TYPE_OCHAYA1020 1207 -#define MACH_TYPE_HITRACK 1208 -#define MACH_TYPE_SYME1 1209 -#define MACH_TYPE_SYHL1 1210 -#define MACH_TYPE_EMPCA400 1211 -#define MACH_TYPE_EM7210 1212 -#define MACH_TYPE_HTCHERMES 1213 -#define MACH_TYPE_ETI_C1 1214 -#define MACH_TYPE_AC100 1216 -#define MACH_TYPE_SNEETCH 1217 -#define MACH_TYPE_STUDENTMATE 1218 -#define MACH_TYPE_ZIR2410 1219 -#define MACH_TYPE_ZIR2413 1220 -#define MACH_TYPE_DLONIP3 1221 -#define MACH_TYPE_INSTREAM 1222 -#define MACH_TYPE_AMBARELLA 1223 -#define MACH_TYPE_NEVIS 1224 -#define MACH_TYPE_HTC_TRINITY 1225 -#define MACH_TYPE_QL202B 1226 -#define MACH_TYPE_VPAC270 1227 -#define MACH_TYPE_RD129 1228 -#define MACH_TYPE_HTCWIZARD 1229 -#define MACH_TYPE_TREO680 1230 -#define MACH_TYPE_TECON_TMEZON 1231 -#define MACH_TYPE_ZYLONITE 1233 -#define MACH_TYPE_GENE1270 1234 -#define MACH_TYPE_ZIR2412 1235 -#define MACH_TYPE_MX31LITE 1236 -#define MACH_TYPE_T700WX 1237 -#define MACH_TYPE_VF100 1238 -#define MACH_TYPE_NSB2 1239 -#define MACH_TYPE_NXHMI_BB 1240 -#define MACH_TYPE_NXHMI_RE 1241 -#define MACH_TYPE_N4100PRO 1242 -#define MACH_TYPE_SAM9260 1243 -#define MACH_TYPE_OMAP_TREO600 1244 -#define MACH_TYPE_INDY2410 1245 -#define MACH_TYPE_NELT_A 1246 -#define MACH_TYPE_N311 1248 -#define MACH_TYPE_AT91SAM9260VGK 1249 -#define MACH_TYPE_AT91LEPPE 1250 -#define MACH_TYPE_AT91LEPCCN 1251 -#define MACH_TYPE_APC7100 1252 -#define MACH_TYPE_STARGAZER 1253 -#define MACH_TYPE_SONATA 1254 -#define MACH_TYPE_SCHMOOGIE 1255 -#define MACH_TYPE_AZTOOL 1256 -#define MACH_TYPE_MIOA701 1257 -#define MACH_TYPE_SXNI9260 1258 -#define MACH_TYPE_MXC27520EVB 1259 -#define MACH_TYPE_ARMADILLO5X0 1260 -#define MACH_TYPE_MB9260 1261 -#define MACH_TYPE_MB9263 1262 -#define MACH_TYPE_IPAC9302 1263 -#define MACH_TYPE_CC9P9360JS 1264 -#define MACH_TYPE_GALLIUM 1265 -#define MACH_TYPE_MSC2410 1266 -#define MACH_TYPE_GHI270 1267 -#define MACH_TYPE_DAVINCI_LEONARDO 1268 -#define MACH_TYPE_OIAB 1269 -#define MACH_TYPE_SMDK6400 1270 -#define MACH_TYPE_NOKIA_N800 1271 -#define MACH_TYPE_GREENPHONE 1272 -#define MACH_TYPE_COMPEXWP18 1273 -#define MACH_TYPE_XMATE 1274 -#define MACH_TYPE_ENERGIZER 1275 -#define MACH_TYPE_IME1 1276 -#define MACH_TYPE_SWEDATMS 1277 -#define MACH_TYPE_NTNP435C 1278 -#define MACH_TYPE_SPECTRO2 1279 -#define MACH_TYPE_H6039 1280 -#define MACH_TYPE_EP80219 1281 -#define MACH_TYPE_SAMOA_II 1282 -#define MACH_TYPE_CWMXL 1283 -#define MACH_TYPE_AS9200 1284 -#define MACH_TYPE_SFX1149 1285 -#define MACH_TYPE_NAVI010 1286 -#define MACH_TYPE_MULTMDP 1287 -#define MACH_TYPE_SCB9520 1288 -#define MACH_TYPE_HTCATHENA 1289 -#define MACH_TYPE_XP179 1290 -#define MACH_TYPE_H4300 1291 -#define MACH_TYPE_GORAMO_MLR 1292 -#define MACH_TYPE_MXC30020EVB 1293 -#define MACH_TYPE_ADSBITSYG5 1294 -#define MACH_TYPE_ADSPORTALPLUS 1295 -#define MACH_TYPE_MMSP2PLUS 1296 -#define MACH_TYPE_EM_X270 1297 -#define MACH_TYPE_TPP302 1298 -#define MACH_TYPE_TPM104 1299 -#define MACH_TYPE_TPM102 1300 -#define MACH_TYPE_TPM109 1301 -#define MACH_TYPE_FBXO1 1302 -#define MACH_TYPE_HXD8 1303 -#define MACH_TYPE_NEO1973_GTA02 1304 -#define MACH_TYPE_EMTEST 1305 -#define MACH_TYPE_AD6900 1306 -#define MACH_TYPE_EUROPA 1307 -#define MACH_TYPE_METROCONNECT 1308 -#define MACH_TYPE_EZ_S2410 1309 -#define MACH_TYPE_EZ_S2440 1310 -#define MACH_TYPE_EZ_EP9312 1311 -#define MACH_TYPE_EZ_EP9315 1312 -#define MACH_TYPE_EZ_X7 1313 -#define MACH_TYPE_GODOTDB 1314 -#define MACH_TYPE_MISTRAL 1315 -#define MACH_TYPE_MSM 1316 -#define MACH_TYPE_CT5910 1317 -#define MACH_TYPE_CT5912 1318 -#define MACH_TYPE_HYNET_INE 1319 -#define MACH_TYPE_HYNET_APP 1320 -#define MACH_TYPE_MSM7200 1321 -#define MACH_TYPE_MSM7600 1322 -#define MACH_TYPE_CEB255 1323 -#define MACH_TYPE_CIEL 1324 -#define MACH_TYPE_SLM5650 1325 -#define MACH_TYPE_AT91SAM9RLEK 1326 -#define MACH_TYPE_COMTECH_ROUTER 1327 -#define MACH_TYPE_SBC2410X 1328 -#define MACH_TYPE_AT4X0BD 1329 -#define MACH_TYPE_CBIFR 1330 -#define MACH_TYPE_ARCOM_QUANTUM 1331 -#define MACH_TYPE_MATRIX520 1332 -#define MACH_TYPE_MATRIX510 1333 -#define MACH_TYPE_MATRIX500 1334 -#define MACH_TYPE_M501 1335 -#define MACH_TYPE_AAEON1270 1336 -#define MACH_TYPE_MATRIX500EV 1337 -#define MACH_TYPE_PAC500 1338 -#define MACH_TYPE_PNX8181 1339 -#define MACH_TYPE_COLIBRI320 1340 -#define MACH_TYPE_AZTOOLBB 1341 -#define MACH_TYPE_AZTOOLG2 1342 -#define MACH_TYPE_DVLHOST 1343 -#define MACH_TYPE_ZIR9200 1344 -#define MACH_TYPE_ZIR9260 1345 -#define MACH_TYPE_COCOPAH 1346 -#define MACH_TYPE_NDS 1347 -#define MACH_TYPE_ROSENCRANTZ 1348 -#define MACH_TYPE_FTTX_ODSC 1349 -#define MACH_TYPE_CLASSE_R6904 1350 -#define MACH_TYPE_CAM60 1351 -#define MACH_TYPE_MXC30031ADS 1352 -#define MACH_TYPE_DATACALL 1353 -#define MACH_TYPE_AT91EB01 1354 -#define MACH_TYPE_RTY 1355 -#define MACH_TYPE_DWL2100 1356 -#define MACH_TYPE_VINSI 1357 -#define MACH_TYPE_DB88F5281 1358 -#define MACH_TYPE_CSB726 1359 -#define MACH_TYPE_TIK27 1360 -#define MACH_TYPE_MX_UC7420 1361 -#define MACH_TYPE_RIRM3 1362 -#define MACH_TYPE_PELCO_ODYSSEY 1363 -#define MACH_TYPE_ADX_ABOX 1365 -#define MACH_TYPE_ADX_TPID 1366 -#define MACH_TYPE_MINICHECK 1367 -#define MACH_TYPE_IDAM 1368 -#define MACH_TYPE_MARIO_MX 1369 -#define MACH_TYPE_VI1888 1370 -#define MACH_TYPE_ZR4230 1371 -#define MACH_TYPE_T1_IX_BLUE 1372 -#define MACH_TYPE_SYHQ2 1373 -#define MACH_TYPE_COMPUTIME_R3 1374 -#define MACH_TYPE_ORATIS 1375 -#define MACH_TYPE_MIKKO 1376 -#define MACH_TYPE_HOLON 1377 -#define MACH_TYPE_OLIP8 1378 -#define MACH_TYPE_GHI270HG 1379 -#define MACH_TYPE_DAVINCI_DM6467_EVM 1380 -#define MACH_TYPE_DAVINCI_DM355_EVM 1381 -#define MACH_TYPE_BLACKRIVER 1383 -#define MACH_TYPE_SANDGATEWP 1384 -#define MACH_TYPE_CDOTBWSG 1385 -#define MACH_TYPE_QUARK963 1386 -#define MACH_TYPE_CSB735 1387 -#define MACH_TYPE_LITTLETON 1388 -#define MACH_TYPE_MIO_P550 1389 -#define MACH_TYPE_MOTION2440 1390 -#define MACH_TYPE_IMM500 1391 -#define MACH_TYPE_HOMEMATIC 1392 -#define MACH_TYPE_ERMINE 1393 -#define MACH_TYPE_KB9202B 1394 -#define MACH_TYPE_HS1XX 1395 -#define MACH_TYPE_STUDENTMATE2440 1396 -#define MACH_TYPE_ARVOO_L1_Z1 1397 -#define MACH_TYPE_DEP2410K 1398 -#define MACH_TYPE_XXSVIDEO 1399 -#define MACH_TYPE_IM4004 1400 -#define MACH_TYPE_OCHAYA1050 1401 -#define MACH_TYPE_LEP9261 1402 -#define MACH_TYPE_SVENMEB 1403 -#define MACH_TYPE_FORTUNET2NE 1404 -#define MACH_TYPE_NXHX 1406 -#define MACH_TYPE_REALVIEW_PB11MP 1407 -#define MACH_TYPE_IDS500 1408 -#define MACH_TYPE_ORS_N725 1409 -#define MACH_TYPE_HSDARM 1410 -#define MACH_TYPE_SHA_PON003 1411 -#define MACH_TYPE_SHA_PON004 1412 -#define MACH_TYPE_SHA_PON007 1413 -#define MACH_TYPE_SHA_PON011 1414 -#define MACH_TYPE_H6042 1415 -#define MACH_TYPE_H6043 1416 -#define MACH_TYPE_LOOXC550 1417 -#define MACH_TYPE_CNTY_TITAN 1418 -#define MACH_TYPE_APP3XX 1419 -#define MACH_TYPE_SIDEOATSGRAMA 1420 -#define MACH_TYPE_TREO700P 1421 -#define MACH_TYPE_TREO700W 1422 -#define MACH_TYPE_TREO750 1423 -#define MACH_TYPE_TREO755P 1424 -#define MACH_TYPE_EZREGANUT9200 1425 -#define MACH_TYPE_SARGE 1426 -#define MACH_TYPE_A696 1427 -#define MACH_TYPE_TURTLE 1428 -#define MACH_TYPE_MX27_3DS 1430 -#define MACH_TYPE_BISHOP 1431 -#define MACH_TYPE_PXX 1432 -#define MACH_TYPE_REDWOOD 1433 -#define MACH_TYPE_OMAP_2430DLP 1436 -#define MACH_TYPE_OMAP_2430OSK 1437 -#define MACH_TYPE_SARDINE 1438 -#define MACH_TYPE_HALIBUT 1439 -#define MACH_TYPE_TROUT 1440 -#define MACH_TYPE_GOLDFISH 1441 -#define MACH_TYPE_GESBC2440 1442 -#define MACH_TYPE_NOMAD 1443 -#define MACH_TYPE_ROSALIND 1444 -#define MACH_TYPE_CC9P9215 1445 -#define MACH_TYPE_CC9P9210 1446 -#define MACH_TYPE_CC9P9215JS 1447 -#define MACH_TYPE_CC9P9210JS 1448 -#define MACH_TYPE_NASFFE 1449 -#define MACH_TYPE_TN2X0BD 1450 -#define MACH_TYPE_GWMPXA 1451 -#define MACH_TYPE_EXYPLUS 1452 -#define MACH_TYPE_JADOO21 1453 -#define MACH_TYPE_LOOXN560 1454 -#define MACH_TYPE_BONSAI 1455 -#define MACH_TYPE_ADSMILGATO 1456 -#define MACH_TYPE_GBA 1457 -#define MACH_TYPE_H6044 1458 -#define MACH_TYPE_APP 1459 -#define MACH_TYPE_TCT_HAMMER 1460 -#define MACH_TYPE_HERALD 1461 -#define MACH_TYPE_ARTEMIS 1462 -#define MACH_TYPE_HTCTITAN 1463 -#define MACH_TYPE_QRANIUM 1464 -#define MACH_TYPE_ADX_WSC2 1465 -#define MACH_TYPE_ADX_MEDCOM 1466 -#define MACH_TYPE_BBOARD 1467 -#define MACH_TYPE_CAMBRIA 1468 -#define MACH_TYPE_MT7XXX 1469 -#define MACH_TYPE_MATRIX512 1470 -#define MACH_TYPE_MATRIX522 1471 -#define MACH_TYPE_IPAC5010 1472 -#define MACH_TYPE_SAKURA 1473 -#define MACH_TYPE_GROCX 1474 -#define MACH_TYPE_PM9263 1475 -#define MACH_TYPE_SIM_ONE 1476 -#define MACH_TYPE_ACQ132 1477 -#define MACH_TYPE_DATR 1478 -#define MACH_TYPE_ACTUX1 1479 -#define MACH_TYPE_ACTUX2 1480 -#define MACH_TYPE_ACTUX3 1481 -#define MACH_TYPE_FLEXIT 1482 -#define MACH_TYPE_BH2X0BD 1483 -#define MACH_TYPE_ATB2002 1484 -#define MACH_TYPE_XENON 1485 -#define MACH_TYPE_FM607 1486 -#define MACH_TYPE_MATRIX514 1487 -#define MACH_TYPE_MATRIX524 1488 -#define MACH_TYPE_INPOD 1489 -#define MACH_TYPE_JIVE 1490 -#define MACH_TYPE_TLL_MX21 1491 -#define MACH_TYPE_SBC2800 1492 -#define MACH_TYPE_CC7UCAMRY 1493 -#define MACH_TYPE_UBISYS_P9_SC15 1494 -#define MACH_TYPE_UBISYS_P9_SSC2D10 1495 -#define MACH_TYPE_UBISYS_P9_RCU3 1496 -#define MACH_TYPE_AML_M8000 1497 -#define MACH_TYPE_SNAPPER_270 1498 -#define MACH_TYPE_OMAP_BBX 1499 -#define MACH_TYPE_UCN2410 1500 -#define MACH_TYPE_SAM9_L9260 1501 -#define MACH_TYPE_ETI_C2 1502 -#define MACH_TYPE_AVALANCHE 1503 -#define MACH_TYPE_REALVIEW_PB1176 1504 -#define MACH_TYPE_DP1500 1505 -#define MACH_TYPE_APPLE_IPHONE 1506 -#define MACH_TYPE_YL9200 1507 -#define MACH_TYPE_RD88F5182 1508 -#define MACH_TYPE_KUROBOX_PRO 1509 -#define MACH_TYPE_SE_POET 1510 -#define MACH_TYPE_MX31_3DS 1511 -#define MACH_TYPE_R270 1512 -#define MACH_TYPE_ARMOUR21 1513 -#define MACH_TYPE_DT2 1514 -#define MACH_TYPE_VT4 1515 -#define MACH_TYPE_TYCO320 1516 -#define MACH_TYPE_ADMA 1517 -#define MACH_TYPE_WP188 1518 -#define MACH_TYPE_CORSICA 1519 -#define MACH_TYPE_BIGEYE 1520 -#define MACH_TYPE_TLL5000 1522 -#define MACH_TYPE_BEBOT 1523 -#define MACH_TYPE_QONG 1524 -#define MACH_TYPE_TCOMPACT 1525 -#define MACH_TYPE_PUMA5 1526 -#define MACH_TYPE_ELARA 1527 -#define MACH_TYPE_ELLINGTON 1528 -#define MACH_TYPE_XDA_ATOM 1529 -#define MACH_TYPE_ENERGIZER2 1530 -#define MACH_TYPE_ODIN 1531 -#define MACH_TYPE_ACTUX4 1532 -#define MACH_TYPE_ESL_OMAP 1533 -#define MACH_TYPE_OMAP2EVM 1534 -#define MACH_TYPE_OMAP3EVM 1535 -#define MACH_TYPE_ADX_PCU57 1536 -#define MACH_TYPE_MONACO 1537 -#define MACH_TYPE_LEVANTE 1538 -#define MACH_TYPE_TMXIPX425 1539 -#define MACH_TYPE_LEEP 1540 -#define MACH_TYPE_RAAD 1541 -#define MACH_TYPE_DNS323 1542 -#define MACH_TYPE_AP1000 1543 -#define MACH_TYPE_A9SAM6432 1544 -#define MACH_TYPE_SHINY 1545 -#define MACH_TYPE_OMAP3_BEAGLE 1546 -#define MACH_TYPE_CSR_BDB2 1547 -#define MACH_TYPE_NOKIA_N810 1548 -#define MACH_TYPE_C270 1549 -#define MACH_TYPE_SENTRY 1550 -#define MACH_TYPE_PCM038 1551 -#define MACH_TYPE_ANC300 1552 -#define MACH_TYPE_HTCKAISER 1553 -#define MACH_TYPE_SBAT100 1554 -#define MACH_TYPE_MODUNORM 1555 -#define MACH_TYPE_PELOS_TWARM 1556 -#define MACH_TYPE_FLANK 1557 -#define MACH_TYPE_SIRLOIN 1558 -#define MACH_TYPE_BRISKET 1559 -#define MACH_TYPE_CHUCK 1560 -#define MACH_TYPE_OTTER 1561 -#define MACH_TYPE_DAVINCI_LDK 1562 -#define MACH_TYPE_PHREEDOM 1563 -#define MACH_TYPE_SG310 1564 -#define MACH_TYPE_TS209 1565 -#define MACH_TYPE_AT91CAP9ADK 1566 -#define MACH_TYPE_TION9315 1567 -#define MACH_TYPE_MAST 1568 -#define MACH_TYPE_PFW 1569 -#define MACH_TYPE_YL_P2440 1570 -#define MACH_TYPE_ZSBC32 1571 -#define MACH_TYPE_OMAP_PACE2 1572 -#define MACH_TYPE_IMX_PACE2 1573 -#define MACH_TYPE_MX31MOBOARD 1574 -#define MACH_TYPE_MX37_3DS 1575 -#define MACH_TYPE_RCC 1576 -#define MACH_TYPE_ARM9 1577 -#define MACH_TYPE_VISION_EP9307 1578 -#define MACH_TYPE_SCLY1000 1579 -#define MACH_TYPE_FONTEL_EP 1580 -#define MACH_TYPE_VOICEBLUE3G 1581 -#define MACH_TYPE_TT9200 1582 -#define MACH_TYPE_DIGI2410 1583 -#define MACH_TYPE_TERASTATION_PRO2 1584 -#define MACH_TYPE_LINKSTATION_PRO 1585 -#define MACH_TYPE_MOTOROLA_A780 1587 -#define MACH_TYPE_MOTOROLA_E6 1588 -#define MACH_TYPE_MOTOROLA_E2 1589 -#define MACH_TYPE_MOTOROLA_E680 1590 -#define MACH_TYPE_UR2410 1591 -#define MACH_TYPE_TAS9261 1592 -#define MACH_TYPE_HERMES_HD 1593 -#define MACH_TYPE_PERSEO_HD 1594 -#define MACH_TYPE_STARGAZER2 1595 -#define MACH_TYPE_E350 1596 -#define MACH_TYPE_WPCM450 1597 -#define MACH_TYPE_CARTESIO 1598 -#define MACH_TYPE_TOYBOX 1599 -#define MACH_TYPE_TX27 1600 -#define MACH_TYPE_TS409 1601 -#define MACH_TYPE_P300 1602 -#define MACH_TYPE_XDACOMET 1603 -#define MACH_TYPE_DEXFLEX2 1604 -#define MACH_TYPE_OW 1605 -#define MACH_TYPE_ARMEBS3 1606 -#define MACH_TYPE_U3 1607 -#define MACH_TYPE_SMDK2450 1608 -#define MACH_TYPE_RSI_EWS 1609 -#define MACH_TYPE_TNB 1610 -#define MACH_TYPE_TOEPATH 1611 -#define MACH_TYPE_KB9263 1612 -#define MACH_TYPE_MT7108 1613 -#define MACH_TYPE_SMTR2440 1614 -#define MACH_TYPE_MANAO 1615 -#define MACH_TYPE_CM_X300 1616 -#define MACH_TYPE_GULFSTREAM_KP 1617 -#define MACH_TYPE_LANREADYFN522 1618 -#define MACH_TYPE_ARMA37 1619 -#define MACH_TYPE_MENDEL 1620 -#define MACH_TYPE_PELCO_ILIAD 1621 -#define MACH_TYPE_UNIT2P 1622 -#define MACH_TYPE_INC20OTTER 1623 -#define MACH_TYPE_AT91SAM9G20EK 1624 -#define MACH_TYPE_STORCENTER 1625 -#define MACH_TYPE_SMDK6410 1626 -#define MACH_TYPE_U300 1627 -#define MACH_TYPE_U500 1628 -#define MACH_TYPE_DS9260 1629 -#define MACH_TYPE_RIVERROCK 1630 -#define MACH_TYPE_SCIBATH 1631 -#define MACH_TYPE_AT91SAM7SE512EK 1632 -#define MACH_TYPE_WRT350N_V2 1633 -#define MACH_TYPE_MULTIMEDIA 1634 -#define MACH_TYPE_MARVIN 1635 -#define MACH_TYPE_X500 1636 -#define MACH_TYPE_AWLUG4LCU 1637 -#define MACH_TYPE_PALERMOC 1638 -#define MACH_TYPE_OMAP_LDP 1639 -#define MACH_TYPE_IP500 1640 -#define MACH_TYPE_ASE2 1642 -#define MACH_TYPE_MX35EVB 1643 -#define MACH_TYPE_AML_M8050 1644 -#define MACH_TYPE_MX35_3DS 1645 -#define MACH_TYPE_MARS 1646 -#define MACH_TYPE_NEUROS_OSD2 1647 -#define MACH_TYPE_BADGER 1648 -#define MACH_TYPE_TRIZEPS4WL 1649 -#define MACH_TYPE_TRIZEPS5 1650 -#define MACH_TYPE_MARLIN 1651 -#define MACH_TYPE_TS78XX 1652 -#define MACH_TYPE_HPIPAQ214 1653 -#define MACH_TYPE_AT572D940DCM 1654 -#define MACH_TYPE_NE1BOARD 1655 -#define MACH_TYPE_ZANTE 1656 -#define MACH_TYPE_SFFSDR 1657 -#define MACH_TYPE_TW2662 1658 -#define MACH_TYPE_VF10XX 1659 -#define MACH_TYPE_ZORAN43XX 1660 -#define MACH_TYPE_SONIX926 1661 -#define MACH_TYPE_CELESTIALSEMI 1662 -#define MACH_TYPE_CC9M2443JS 1663 -#define MACH_TYPE_TW5334 1664 -#define MACH_TYPE_HTCARTEMIS 1665 -#define MACH_TYPE_NAL_HLITE 1666 -#define MACH_TYPE_HTCVOGUE 1667 -#define MACH_TYPE_SMARTWEB 1668 -#define MACH_TYPE_MV86XX 1669 -#define MACH_TYPE_MV87XX 1670 -#define MACH_TYPE_SONGYOUNGHO 1671 -#define MACH_TYPE_YOUNGHOTEMA 1672 -#define MACH_TYPE_PCM037 1673 -#define MACH_TYPE_MMVP 1674 -#define MACH_TYPE_MMAP 1675 -#define MACH_TYPE_PTID2410 1676 -#define MACH_TYPE_JAMES_926 1677 -#define MACH_TYPE_FM6000 1678 -#define MACH_TYPE_DB88F6281_BP 1680 -#define MACH_TYPE_RD88F6192_NAS 1681 -#define MACH_TYPE_RD88F6281 1682 -#define MACH_TYPE_DB78X00_BP 1683 -#define MACH_TYPE_SMDK2416 1685 -#define MACH_TYPE_OCE_SPIDER_SI 1686 -#define MACH_TYPE_OCE_SPIDER_SK 1687 -#define MACH_TYPE_ROVERN6 1688 -#define MACH_TYPE_PELCO_EVOLUTION 1689 -#define MACH_TYPE_WBD111 1690 -#define MACH_TYPE_ELARACPE 1691 -#define MACH_TYPE_MABV3 1692 -#define MACH_TYPE_MV2120 1693 -#define MACH_TYPE_CSB737 1695 -#define MACH_TYPE_MX51_3DS 1696 -#define MACH_TYPE_G900 1697 -#define MACH_TYPE_APF27 1698 -#define MACH_TYPE_GGUS2000 1699 -#define MACH_TYPE_OMAP_2430_MIMIC 1700 -#define MACH_TYPE_IMX27LITE 1701 -#define MACH_TYPE_ALMEX 1702 -#define MACH_TYPE_CONTROL 1703 -#define MACH_TYPE_MBA2410 1704 -#define MACH_TYPE_VOLCANO 1705 -#define MACH_TYPE_ZENITH 1706 -#define MACH_TYPE_MUCHIP 1707 -#define MACH_TYPE_MAGELLAN 1708 -#define MACH_TYPE_USB_A9260 1709 -#define MACH_TYPE_USB_A9263 1710 -#define MACH_TYPE_QIL_A9260 1711 -#define MACH_TYPE_CME9210 1712 -#define MACH_TYPE_HCZH4 1713 -#define MACH_TYPE_SPEARBASIC 1714 -#define MACH_TYPE_DEP2440 1715 -#define MACH_TYPE_HDL_GXR 1716 -#define MACH_TYPE_HDL_GT 1717 -#define MACH_TYPE_HDL_4G 1718 -#define MACH_TYPE_S3C6000 1719 -#define MACH_TYPE_MMSP2_MDK 1720 -#define MACH_TYPE_MPX220 1721 -#define MACH_TYPE_KZM_ARM11_01 1722 -#define MACH_TYPE_HTC_POLARIS 1723 -#define MACH_TYPE_HTC_KAISER 1724 -#define MACH_TYPE_LG_KS20 1725 -#define MACH_TYPE_HHGPS 1726 -#define MACH_TYPE_NOKIA_N810_WIMAX 1727 -#define MACH_TYPE_INSIGHT 1728 -#define MACH_TYPE_SAPPHIRE 1729 -#define MACH_TYPE_CSB637XO 1730 -#define MACH_TYPE_EVISIONG 1731 -#define MACH_TYPE_STMP37XX 1732 -#define MACH_TYPE_STMP378X 1733 -#define MACH_TYPE_TNT 1734 -#define MACH_TYPE_TBXT 1735 -#define MACH_TYPE_PLAYMATE 1736 -#define MACH_TYPE_PNS10 1737 -#define MACH_TYPE_EZNAVI 1738 -#define MACH_TYPE_PS4000 1739 -#define MACH_TYPE_EZX_A780 1740 -#define MACH_TYPE_EZX_E680 1741 -#define MACH_TYPE_EZX_A1200 1742 -#define MACH_TYPE_EZX_E6 1743 -#define MACH_TYPE_EZX_E2 1744 -#define MACH_TYPE_EZX_A910 1745 -#define MACH_TYPE_CWMX31 1746 -#define MACH_TYPE_SL2312 1747 -#define MACH_TYPE_BLENNY 1748 -#define MACH_TYPE_DS107 1749 -#define MACH_TYPE_DSX07 1750 -#define MACH_TYPE_PICOCOM1 1751 -#define MACH_TYPE_LYNX_WOLVERINE 1752 -#define MACH_TYPE_UBISYS_P9_SC19 1753 -#define MACH_TYPE_KRATOS_LOW 1754 -#define MACH_TYPE_M700 1755 -#define MACH_TYPE_EDMINI_V2 1756 -#define MACH_TYPE_ZIPIT2 1757 -#define MACH_TYPE_HSLFEMTOCELL 1758 -#define MACH_TYPE_DAINTREE_AT91 1759 -#define MACH_TYPE_SG560USB 1760 -#define MACH_TYPE_OMAP3_PANDORA 1761 -#define MACH_TYPE_USR8200 1762 -#define MACH_TYPE_S1S65K 1763 -#define MACH_TYPE_S2S65A 1764 -#define MACH_TYPE_ICORE 1765 -#define MACH_TYPE_MSS2 1766 -#define MACH_TYPE_BELMONT 1767 -#define MACH_TYPE_ASUSP525 1768 -#define MACH_TYPE_LB88RC8480 1769 -#define MACH_TYPE_HIPXA 1770 -#define MACH_TYPE_MX25_3DS 1771 -#define MACH_TYPE_M800 1772 -#define MACH_TYPE_OMAP3530_LV_SOM 1773 -#define MACH_TYPE_PRIMA_EVB 1774 -#define MACH_TYPE_MX31BT1 1775 -#define MACH_TYPE_ATLAS4_EVB 1776 -#define MACH_TYPE_MX31CICADA 1777 -#define MACH_TYPE_MI424WR 1778 -#define MACH_TYPE_AXS_ULTRAX 1779 -#define MACH_TYPE_AT572D940DEB 1780 -#define MACH_TYPE_DAVINCI_DA830_EVM 1781 -#define MACH_TYPE_EP9302 1782 -#define MACH_TYPE_AT572D940HFEB 1783 -#define MACH_TYPE_CYBOOK3 1784 -#define MACH_TYPE_WDG002 1785 -#define MACH_TYPE_SG560ADSL 1786 -#define MACH_TYPE_NEXTIO_N2800_ICA 1787 -#define MACH_TYPE_DOVE_DB 1788 -#define MACH_TYPE_MARVELL_NEWDB 1789 -#define MACH_TYPE_VANDIHUD 1790 -#define MACH_TYPE_MAGX_E8 1791 -#define MACH_TYPE_MAGX_Z6 1792 -#define MACH_TYPE_MAGX_V8 1793 -#define MACH_TYPE_MAGX_U9 1794 -#define MACH_TYPE_TOUGHCF08 1795 -#define MACH_TYPE_ZW4400 1796 -#define MACH_TYPE_MARAT91 1797 -#define MACH_TYPE_OVERO 1798 -#define MACH_TYPE_AT2440EVB 1799 -#define MACH_TYPE_NEOCORE926 1800 -#define MACH_TYPE_WNR854T 1801 -#define MACH_TYPE_IMX27 1802 -#define MACH_TYPE_MOOSE_DB 1803 -#define MACH_TYPE_FAB4 1804 -#define MACH_TYPE_HTCDIAMOND 1805 -#define MACH_TYPE_FIONA 1806 -#define MACH_TYPE_MXC30030_X 1807 -#define MACH_TYPE_BMP1000 1808 -#define MACH_TYPE_LOGI9200 1809 -#define MACH_TYPE_TQMA31 1810 -#define MACH_TYPE_CCW9P9215JS 1811 -#define MACH_TYPE_RD88F5181L_GE 1812 -#define MACH_TYPE_SIFMAIN 1813 -#define MACH_TYPE_SAM9_L9261 1814 -#define MACH_TYPE_CC9M2443 1815 -#define MACH_TYPE_XARIA300 1816 -#define MACH_TYPE_IT9200 1817 -#define MACH_TYPE_RD88F5181L_FXO 1818 -#define MACH_TYPE_KRISS_SENSOR 1819 -#define MACH_TYPE_PILZ_PMI5 1820 -#define MACH_TYPE_JADE 1821 -#define MACH_TYPE_KS8695_SOFTPLC 1822 -#define MACH_TYPE_GPRISC3 1823 -#define MACH_TYPE_STAMP9G20 1824 -#define MACH_TYPE_SMDK6430 1825 -#define MACH_TYPE_SMDKC100 1826 -#define MACH_TYPE_TAVOREVB 1827 -#define MACH_TYPE_SAAR 1828 -#define MACH_TYPE_DEISTER_EYECAM 1829 -#define MACH_TYPE_AT91SAM9M10G45EK 1830 -#define MACH_TYPE_LINKSTATION_PRODUO 1831 -#define MACH_TYPE_HIT_B0 1832 -#define MACH_TYPE_ADX_RMU 1833 -#define MACH_TYPE_XG_CPE_MAIN 1834 -#define MACH_TYPE_EDB9407A 1835 -#define MACH_TYPE_DTB9608 1836 -#define MACH_TYPE_EM104V1 1837 -#define MACH_TYPE_DEMO 1838 -#define MACH_TYPE_LOGI9260 1839 -#define MACH_TYPE_MX31_EXM32 1840 -#define MACH_TYPE_USB_A9G20 1841 -#define MACH_TYPE_PICPROJE2008 1842 -#define MACH_TYPE_CS_E9315 1843 -#define MACH_TYPE_QIL_A9G20 1844 -#define MACH_TYPE_SHA_PON020 1845 -#define MACH_TYPE_NAD 1846 -#define MACH_TYPE_SBC35_A9260 1847 -#define MACH_TYPE_SBC35_A9G20 1848 -#define MACH_TYPE_DAVINCI_BEGINNING 1849 -#define MACH_TYPE_UWC 1850 -#define MACH_TYPE_MXLADS 1851 -#define MACH_TYPE_HTCNIKE 1852 -#define MACH_TYPE_DEISTER_PXA270 1853 -#define MACH_TYPE_CME9210JS 1854 -#define MACH_TYPE_CC9P9360 1855 -#define MACH_TYPE_MOCHA 1856 -#define MACH_TYPE_WAPD170AG 1857 -#define MACH_TYPE_LINKSTATION_MINI 1858 -#define MACH_TYPE_AFEB9260 1859 -#define MACH_TYPE_W90X900 1860 -#define MACH_TYPE_W90X700 1861 -#define MACH_TYPE_KT300IP 1862 -#define MACH_TYPE_KT300IP_G20 1863 -#define MACH_TYPE_SRCM 1864 -#define MACH_TYPE_WLNX_9260 1865 -#define MACH_TYPE_OPENMOKO_GTA03 1866 -#define MACH_TYPE_OSPREY2 1867 -#define MACH_TYPE_KBIO9260 1868 -#define MACH_TYPE_GINZA 1869 -#define MACH_TYPE_A636N 1870 -#define MACH_TYPE_IMX27IPCAM 1871 -#define MACH_TYPE_NEMOC 1872 -#define MACH_TYPE_GENEVA 1873 -#define MACH_TYPE_HTCPHAROS 1874 -#define MACH_TYPE_NEONC 1875 -#define MACH_TYPE_NAS7100 1876 -#define MACH_TYPE_TEUPHONE 1877 -#define MACH_TYPE_ANNAX_ETH2 1878 -#define MACH_TYPE_CSB733 1879 -#define MACH_TYPE_BK3 1880 -#define MACH_TYPE_OMAP_EM32 1881 -#define MACH_TYPE_ET9261CP 1882 -#define MACH_TYPE_JASPERC 1883 -#define MACH_TYPE_ISSI_ARM9 1884 -#define MACH_TYPE_UED 1885 -#define MACH_TYPE_ESIBLADE 1886 -#define MACH_TYPE_EYE02 1887 -#define MACH_TYPE_IMX27KBD 1888 -#define MACH_TYPE_SST61VC010_FPGA 1889 -#define MACH_TYPE_KIXVP435 1890 -#define MACH_TYPE_KIXNP435 1891 -#define MACH_TYPE_AFRICA 1892 -#define MACH_TYPE_NH233 1893 -#define MACH_TYPE_RD88F6183AP_GE 1894 -#define MACH_TYPE_BCM4760 1895 -#define MACH_TYPE_EDDY_V2 1896 -#define MACH_TYPE_REALVIEW_PBA8 1897 -#define MACH_TYPE_HID_A7 1898 -#define MACH_TYPE_HERO 1899 -#define MACH_TYPE_OMAP_POSEIDON 1900 -#define MACH_TYPE_REALVIEW_PBX 1901 -#define MACH_TYPE_MICRO9S 1902 -#define MACH_TYPE_MAKO 1903 -#define MACH_TYPE_XDAFLAME 1904 -#define MACH_TYPE_PHIDGET_SBC2 1905 -#define MACH_TYPE_LIMESTONE 1906 -#define MACH_TYPE_IPROBE_C32 1907 -#define MACH_TYPE_RUT100 1908 -#define MACH_TYPE_ASUSP535 1909 -#define MACH_TYPE_HTCRAPHAEL 1910 -#define MACH_TYPE_SYGDG1 1911 -#define MACH_TYPE_SYGDG2 1912 -#define MACH_TYPE_SEOUL 1913 -#define MACH_TYPE_SALERNO 1914 -#define MACH_TYPE_UCN_S3C64XX 1915 -#define MACH_TYPE_MSM7201A 1916 -#define MACH_TYPE_LPR1 1917 -#define MACH_TYPE_ARMADILLO500FX 1918 -#define MACH_TYPE_G3EVM 1919 -#define MACH_TYPE_Z3_DM355 1920 -#define MACH_TYPE_W90P910EVB 1921 -#define MACH_TYPE_W90P920EVB 1922 -#define MACH_TYPE_W90P950EVB 1923 -#define MACH_TYPE_W90N960EVB 1924 -#define MACH_TYPE_CAMHD 1925 -#define MACH_TYPE_MVC100 1926 -#define MACH_TYPE_ELECTRUM_200 1927 -#define MACH_TYPE_HTCJADE 1928 -#define MACH_TYPE_MEMPHIS 1929 -#define MACH_TYPE_IMX27SBC 1930 -#define MACH_TYPE_LEXTAR 1931 -#define MACH_TYPE_MV88F6281GTW_GE 1932 -#define MACH_TYPE_NCP 1933 -#define MACH_TYPE_Z32AN 1934 -#define MACH_TYPE_TMQ_CAPD 1935 -#define MACH_TYPE_OMAP3_WL 1936 -#define MACH_TYPE_CHUMBY 1937 -#define MACH_TYPE_ATSARM9 1938 -#define MACH_TYPE_DAVINCI_DM365_EVM 1939 -#define MACH_TYPE_BAHAMAS 1940 -#define MACH_TYPE_DAS 1941 -#define MACH_TYPE_MINIDAS 1942 -#define MACH_TYPE_VK1000 1943 -#define MACH_TYPE_CENTRO 1944 -#define MACH_TYPE_CTERA_2BAY 1945 -#define MACH_TYPE_EDGECONNECT 1946 -#define MACH_TYPE_ND27000 1947 -#define MACH_TYPE_GEMALTO_COBRA 1948 -#define MACH_TYPE_INGELABS_COMET 1949 -#define MACH_TYPE_POLLUX_WIZ 1950 -#define MACH_TYPE_BLACKSTONE 1951 -#define MACH_TYPE_TOPAZ 1952 -#define MACH_TYPE_AIXLE 1953 -#define MACH_TYPE_MW998 1954 -#define MACH_TYPE_NOKIA_RX51 1955 -#define MACH_TYPE_VSC5605EV 1956 -#define MACH_TYPE_NT98700DK 1957 -#define MACH_TYPE_ICONTACT 1958 -#define MACH_TYPE_SWARCO_FRCPU 1959 -#define MACH_TYPE_SWARCO_SCPU 1960 -#define MACH_TYPE_BBOX_P16 1961 -#define MACH_TYPE_BSTD 1962 -#define MACH_TYPE_SBC2440II 1963 -#define MACH_TYPE_PCM034 1964 -#define MACH_TYPE_NESO 1965 -#define MACH_TYPE_WLNX_9G20 1966 -#define MACH_TYPE_OMAP_ZOOM2 1967 -#define MACH_TYPE_TOTEMNOVA 1968 -#define MACH_TYPE_C5000 1969 -#define MACH_TYPE_UNIPO_AT91SAM9263 1970 -#define MACH_TYPE_ETHERNUT5 1971 -#define MACH_TYPE_ARM11 1972 -#define MACH_TYPE_CPUAT9260 1973 -#define MACH_TYPE_CPUPXA255 1974 -#define MACH_TYPE_CPUIMX27 1975 -#define MACH_TYPE_CHEFLUX 1976 -#define MACH_TYPE_EB_CPUX9K2 1977 -#define MACH_TYPE_OPCOTEC 1978 -#define MACH_TYPE_YT 1979 -#define MACH_TYPE_MOTOQ 1980 -#define MACH_TYPE_BSB1 1981 -#define MACH_TYPE_ACS5K 1982 -#define MACH_TYPE_MILAN 1983 -#define MACH_TYPE_QUARTZV2 1984 -#define MACH_TYPE_RSVP 1985 -#define MACH_TYPE_RMP200 1986 -#define MACH_TYPE_SNAPPER_9260 1987 -#define MACH_TYPE_DSM320 1988 -#define MACH_TYPE_ADSGCM 1989 -#define MACH_TYPE_ASE2_400 1990 -#define MACH_TYPE_PIZZA 1991 -#define MACH_TYPE_SPOT_NGPL 1992 -#define MACH_TYPE_ARMATA 1993 -#define MACH_TYPE_EXEDA 1994 -#define MACH_TYPE_MX31SF005 1995 -#define MACH_TYPE_F5D8231_4_V2 1996 -#define MACH_TYPE_Q2440 1997 -#define MACH_TYPE_QQ2440 1998 -#define MACH_TYPE_MINI2440 1999 -#define MACH_TYPE_COLIBRI300 2000 -#define MACH_TYPE_JADES 2001 -#define MACH_TYPE_SPARK 2002 -#define MACH_TYPE_BENZINA 2003 -#define MACH_TYPE_BLAZE 2004 -#define MACH_TYPE_LINKSTATION_LS_HGL 2005 -#define MACH_TYPE_HTCVENUS 2006 -#define MACH_TYPE_SONY_PRS505 2007 -#define MACH_TYPE_HANLIN_V3 2008 -#define MACH_TYPE_SAPPHIRA 2009 -#define MACH_TYPE_DACK_SDA_01 2010 -#define MACH_TYPE_ARMBOX 2011 -#define MACH_TYPE_HARRIS_RVP 2012 -#define MACH_TYPE_RIBALDO 2013 -#define MACH_TYPE_AGORA 2014 -#define MACH_TYPE_OMAP3_MINI 2015 -#define MACH_TYPE_A9SAM6432_B 2016 -#define MACH_TYPE_USG2410 2017 -#define MACH_TYPE_PC72052_I10_REVB 2018 -#define MACH_TYPE_MX35_EXM32 2019 -#define MACH_TYPE_TOPAS910 2020 -#define MACH_TYPE_HYENA 2021 -#define MACH_TYPE_POSPAX 2022 -#define MACH_TYPE_HDL_GX 2023 -#define MACH_TYPE_CTERA_4BAY 2024 -#define MACH_TYPE_CTERA_PLUG_C 2025 -#define MACH_TYPE_CRWEA_PLUG_I 2026 -#define MACH_TYPE_EGAUGE2 2027 -#define MACH_TYPE_DIDJ 2028 -#define MACH_TYPE_MEISTER 2029 -#define MACH_TYPE_HTCBLACKSTONE 2030 -#define MACH_TYPE_CPUAT9G20 2031 -#define MACH_TYPE_SMDK6440 2032 -#define MACH_TYPE_OMAP_35XX_MVP 2033 -#define MACH_TYPE_CTERA_PLUG_I 2034 -#define MACH_TYPE_PVG610 2035 -#define MACH_TYPE_HPRW6815 2036 -#define MACH_TYPE_OMAP3_OSWALD 2037 -#define MACH_TYPE_NAS4220B 2038 -#define MACH_TYPE_HTCRAPHAEL_CDMA 2039 -#define MACH_TYPE_HTCDIAMOND_CDMA 2040 -#define MACH_TYPE_SCALER 2041 -#define MACH_TYPE_ZYLONITE2 2042 -#define MACH_TYPE_ASPENITE 2043 -#define MACH_TYPE_TETON 2044 -#define MACH_TYPE_TTC_DKB 2045 -#define MACH_TYPE_BISHOP2 2046 -#define MACH_TYPE_IPPV5 2047 -#define MACH_TYPE_FARM926 2048 -#define MACH_TYPE_MMCCPU 2049 -#define MACH_TYPE_SGMSFL 2050 -#define MACH_TYPE_TT8000 2051 -#define MACH_TYPE_ZRN4300LP 2052 -#define MACH_TYPE_MPTC 2053 -#define MACH_TYPE_H6051 2054 -#define MACH_TYPE_PVG610_101 2055 -#define MACH_TYPE_STAMP9261_PC_EVB 2056 -#define MACH_TYPE_PELCO_ODYSSEUS 2057 -#define MACH_TYPE_TNY_A9260 2058 -#define MACH_TYPE_TNY_A9G20 2059 -#define MACH_TYPE_AESOP_MP2530F 2060 -#define MACH_TYPE_DX900 2061 -#define MACH_TYPE_CPODC2 2062 -#define MACH_TYPE_TILT_8925 2063 -#define MACH_TYPE_DAVINCI_DM357_EVM 2064 -#define MACH_TYPE_SWORDFISH 2065 -#define MACH_TYPE_CORVUS 2066 -#define MACH_TYPE_TAURUS 2067 -#define MACH_TYPE_AXM 2068 -#define MACH_TYPE_AXC 2069 -#define MACH_TYPE_BABY 2070 -#define MACH_TYPE_MP200 2071 -#define MACH_TYPE_PCM043 2072 -#define MACH_TYPE_HANLIN_V3C 2073 -#define MACH_TYPE_KBK9G20 2074 -#define MACH_TYPE_ADSTURBOG5 2075 -#define MACH_TYPE_AVENGER_LITE1 2076 -#define MACH_TYPE_SUC 2077 -#define MACH_TYPE_AT91SAM7S256 2078 -#define MACH_TYPE_MENDOZA 2079 -#define MACH_TYPE_KIRA 2080 -#define MACH_TYPE_MX1HBM 2081 -#define MACH_TYPE_QUATRO43XX 2082 -#define MACH_TYPE_QUATRO4230 2083 -#define MACH_TYPE_NSB400 2084 -#define MACH_TYPE_DRP255 2085 -#define MACH_TYPE_THOTH 2086 -#define MACH_TYPE_FIRESTONE 2087 -#define MACH_TYPE_ASUSP750 2088 -#define MACH_TYPE_CTERA_DL 2089 -#define MACH_TYPE_SOCR 2090 -#define MACH_TYPE_HTCOXYGEN 2091 -#define MACH_TYPE_HEROC 2092 -#define MACH_TYPE_ZENO6800 2093 -#define MACH_TYPE_SC2MCS 2094 -#define MACH_TYPE_GENE100 2095 -#define MACH_TYPE_AS353X 2096 -#define MACH_TYPE_SHEEVAPLUG 2097 -#define MACH_TYPE_AT91SAM9G20 2098 -#define MACH_TYPE_MV88F6192GTW_FE 2099 -#define MACH_TYPE_CC9200 2100 -#define MACH_TYPE_SM9200 2101 -#define MACH_TYPE_TP9200 2102 -#define MACH_TYPE_SNAPPERDV 2103 -#define MACH_TYPE_AVENGERS_LITE 2104 -#define MACH_TYPE_AVENGERS_LITE1 2105 -#define MACH_TYPE_OMAP3AXON 2106 -#define MACH_TYPE_MA8XX 2107 -#define MACH_TYPE_MP201EK 2108 -#define MACH_TYPE_DAVINCI_TUX 2109 -#define MACH_TYPE_MPA1600 2110 -#define MACH_TYPE_PELCO_TROY 2111 -#define MACH_TYPE_NSB667 2112 -#define MACH_TYPE_ROVERS5_4MPIX 2113 -#define MACH_TYPE_TWOCOM 2114 -#define MACH_TYPE_UBISYS_P9_RCU3R2 2115 -#define MACH_TYPE_HERO_ESPRESSO 2116 -#define MACH_TYPE_AFEUSB 2117 -#define MACH_TYPE_T830 2118 -#define MACH_TYPE_SPD8020_CC 2119 -#define MACH_TYPE_OM_3D7K 2120 -#define MACH_TYPE_PICOCOM2 2121 -#define MACH_TYPE_UWG4MX27 2122 -#define MACH_TYPE_UWG4MX31 2123 -#define MACH_TYPE_CHERRY 2124 -#define MACH_TYPE_MX51_BABBAGE 2125 -#define MACH_TYPE_S3C2440TURKIYE 2126 -#define MACH_TYPE_TX37 2127 -#define MACH_TYPE_SBC2800_9G20 2128 -#define MACH_TYPE_BENZGLB 2129 -#define MACH_TYPE_BENZTD 2130 -#define MACH_TYPE_CARTESIO_PLUS 2131 -#define MACH_TYPE_SOLRAD_G20 2132 -#define MACH_TYPE_MX27WALLACE 2133 -#define MACH_TYPE_FMZWEBMODUL 2134 -#define MACH_TYPE_RD78X00_MASA 2135 -#define MACH_TYPE_SMALLOGGER 2136 -#define MACH_TYPE_CCW9P9215 2137 -#define MACH_TYPE_DM355_LEOPARD 2138 -#define MACH_TYPE_TS219 2139 -#define MACH_TYPE_TNY_A9263 2140 -#define MACH_TYPE_APOLLO 2141 -#define MACH_TYPE_AT91CAP9STK 2142 -#define MACH_TYPE_SPC300 2143 -#define MACH_TYPE_EKO 2144 -#define MACH_TYPE_CCW9M2443 2145 -#define MACH_TYPE_CCW9M2443JS 2146 -#define MACH_TYPE_M2M_ROUTER_DEVICE 2147 -#define MACH_TYPE_STAR9104NAS 2148 -#define MACH_TYPE_PCA100 2149 -#define MACH_TYPE_Z3_DM365_MOD_01 2150 -#define MACH_TYPE_HIPOX 2151 -#define MACH_TYPE_OMAP3_PITEDS 2152 -#define MACH_TYPE_BM150R 2153 -#define MACH_TYPE_TBONE 2154 -#define MACH_TYPE_MERLIN 2155 -#define MACH_TYPE_FALCON 2156 -#define MACH_TYPE_DAVINCI_DA850_EVM 2157 -#define MACH_TYPE_S5P6440 2158 -#define MACH_TYPE_AT91SAM9G10EK 2159 -#define MACH_TYPE_OMAP_4430SDP 2160 -#define MACH_TYPE_LPC313X 2161 -#define MACH_TYPE_MAGX_ZN5 2162 -#define MACH_TYPE_MAGX_EM30 2163 -#define MACH_TYPE_MAGX_VE66 2164 -#define MACH_TYPE_MEESC 2165 -#define MACH_TYPE_OTC570 2166 -#define MACH_TYPE_BCU2412 2167 -#define MACH_TYPE_BEACON 2168 -#define MACH_TYPE_ACTIA_TGW 2169 -#define MACH_TYPE_E4430 2170 -#define MACH_TYPE_QL300 2171 -#define MACH_TYPE_BTMAVB101 2172 -#define MACH_TYPE_BTMAWB101 2173 -#define MACH_TYPE_SQ201 2174 -#define MACH_TYPE_QUATRO45XX 2175 -#define MACH_TYPE_OPENPAD 2176 -#define MACH_TYPE_TX25 2177 -#define MACH_TYPE_OMAP3_TORPEDO 2178 -#define MACH_TYPE_HTCRAPHAEL_K 2179 -#define MACH_TYPE_LAL43 2181 -#define MACH_TYPE_HTCRAPHAEL_CDMA500 2182 -#define MACH_TYPE_ANW6410 2183 -#define MACH_TYPE_HTCPROPHET 2185 -#define MACH_TYPE_CFA_10022 2186 -#define MACH_TYPE_IMX27_VISSTRIM_M10 2187 -#define MACH_TYPE_PX2IMX27 2188 -#define MACH_TYPE_STM3210E_EVAL 2189 -#define MACH_TYPE_DVS10 2190 -#define MACH_TYPE_PORTUXG20 2191 -#define MACH_TYPE_ARM_SPV 2192 -#define MACH_TYPE_SMDKC110 2193 -#define MACH_TYPE_CABESPRESSO 2194 -#define MACH_TYPE_HMC800 2195 -#define MACH_TYPE_SHOLES 2196 -#define MACH_TYPE_BTMXC31 2197 -#define MACH_TYPE_DT501 2198 -#define MACH_TYPE_KTX 2199 -#define MACH_TYPE_OMAP3517EVM 2200 -#define MACH_TYPE_NETSPACE_V2 2201 -#define MACH_TYPE_NETSPACE_MAX_V2 2202 -#define MACH_TYPE_D2NET_V2 2203 -#define MACH_TYPE_NET2BIG_V2 2204 -#define MACH_TYPE_NET4BIG_V2 2205 -#define MACH_TYPE_NET5BIG_V2 2206 -#define MACH_TYPE_ENDB2443 2207 -#define MACH_TYPE_INETSPACE_V2 2208 -#define MACH_TYPE_TROS 2209 -#define MACH_TYPE_PELCO_HOMER 2210 -#define MACH_TYPE_OFSP8 2211 -#define MACH_TYPE_AT91SAM9G45EKES 2212 -#define MACH_TYPE_GUF_CUPID 2213 -#define MACH_TYPE_EAB1R 2214 -#define MACH_TYPE_DESIREC 2215 -#define MACH_TYPE_CORDOBA 2216 -#define MACH_TYPE_IRVINE 2217 -#define MACH_TYPE_SFF772 2218 -#define MACH_TYPE_PELCO_MILANO 2219 -#define MACH_TYPE_PC7302 2220 -#define MACH_TYPE_BIP6000 2221 -#define MACH_TYPE_SILVERMOON 2222 -#define MACH_TYPE_VC0830 2223 -#define MACH_TYPE_DT430 2224 -#define MACH_TYPE_JI42PF 2225 -#define MACH_TYPE_GNET_KSM 2226 -#define MACH_TYPE_GNET_SGM 2227 -#define MACH_TYPE_GNET_SGR 2228 -#define MACH_TYPE_OMAP3_ICETEKEVM 2229 -#define MACH_TYPE_PNP 2230 -#define MACH_TYPE_CTERA_2BAY_K 2231 -#define MACH_TYPE_CTERA_2BAY_U 2232 -#define MACH_TYPE_SAS_C 2233 -#define MACH_TYPE_VMA2315 2234 -#define MACH_TYPE_VCS 2235 -#define MACH_TYPE_SPEAR600 2236 -#define MACH_TYPE_SPEAR300 2237 -#define MACH_TYPE_SPEAR1300 2238 -#define MACH_TYPE_LILLY1131 2239 -#define MACH_TYPE_ARVOO_AX301 2240 -#define MACH_TYPE_MAPPHONE 2241 -#define MACH_TYPE_LEGEND 2242 -#define MACH_TYPE_SALSA 2243 -#define MACH_TYPE_LOUNGE 2244 -#define MACH_TYPE_VISION 2245 -#define MACH_TYPE_VMB20 2246 -#define MACH_TYPE_HY2410 2247 -#define MACH_TYPE_HY9315 2248 -#define MACH_TYPE_BULLWINKLE 2249 -#define MACH_TYPE_ARM_ULTIMATOR2 2250 -#define MACH_TYPE_VS_V210 2252 -#define MACH_TYPE_VS_V212 2253 -#define MACH_TYPE_HMT 2254 -#define MACH_TYPE_SUEN3 2255 -#define MACH_TYPE_VESPER 2256 -#define MACH_TYPE_STR9 2257 -#define MACH_TYPE_OMAP3_WL_FF 2258 -#define MACH_TYPE_SIMCOM 2259 -#define MACH_TYPE_MCWEBIO 2260 -#define MACH_TYPE_OMAP3_PHRAZER 2261 -#define MACH_TYPE_DARWIN 2262 -#define MACH_TYPE_ORATISCOMU 2263 -#define MACH_TYPE_RTSBC20 2264 -#define MACH_TYPE_I780 2265 -#define MACH_TYPE_GEMINI324 2266 -#define MACH_TYPE_ORATISLAN 2267 -#define MACH_TYPE_ORATISALOG 2268 -#define MACH_TYPE_ORATISMADI 2269 -#define MACH_TYPE_ORATISOT16 2270 -#define MACH_TYPE_ORATISDESK 2271 -#define MACH_TYPE_VEXPRESS 2272 -#define MACH_TYPE_SINTEXO 2273 -#define MACH_TYPE_CM3389 2274 -#define MACH_TYPE_OMAP3_CIO 2275 -#define MACH_TYPE_SGH_I900 2276 -#define MACH_TYPE_BST100 2277 -#define MACH_TYPE_PASSION 2278 -#define MACH_TYPE_INDESIGN_AT91SAM 2279 -#define MACH_TYPE_C4_BADGER 2280 -#define MACH_TYPE_C4_VIPER 2281 -#define MACH_TYPE_D2NET 2282 -#define MACH_TYPE_BIGDISK 2283 -#define MACH_TYPE_NOTALVISION 2284 -#define MACH_TYPE_OMAP3_KBOC 2285 -#define MACH_TYPE_CYCLONE 2286 -#define MACH_TYPE_NINJA 2287 -#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 -#define MACH_TYPE_BCMRING 2289 -#define MACH_TYPE_RESOL_DL2 2290 -#define MACH_TYPE_IFOSW 2291 -#define MACH_TYPE_HTCRHODIUM 2292 -#define MACH_TYPE_HTCTOPAZ 2293 -#define MACH_TYPE_MATRIX504 2294 -#define MACH_TYPE_MRFSA 2295 -#define MACH_TYPE_SC_P270 2296 -#define MACH_TYPE_ATLAS5_EVB 2297 -#define MACH_TYPE_PELCO_LOBOX 2298 -#define MACH_TYPE_DILAX_PCU200 2299 -#define MACH_TYPE_LEONARDO 2300 -#define MACH_TYPE_ZORAN_APPROACH7 2301 -#define MACH_TYPE_DP6XX 2302 -#define MACH_TYPE_BCM2153_VESPER 2303 -#define MACH_TYPE_MAHIMAHI 2304 -#define MACH_TYPE_CLICKC 2305 -#define MACH_TYPE_ZB_GATEWAY 2306 -#define MACH_TYPE_TAZCARD 2307 -#define MACH_TYPE_TAZDEV 2308 -#define MACH_TYPE_ANNAX_CB_ARM 2309 -#define MACH_TYPE_ANNAX_DM3 2310 -#define MACH_TYPE_CEREBRIC 2311 -#define MACH_TYPE_ORCA 2312 -#define MACH_TYPE_PC9260 2313 -#define MACH_TYPE_EMS285A 2314 -#define MACH_TYPE_GEC2410 2315 -#define MACH_TYPE_GEC2440 2316 -#define MACH_TYPE_ARCH_MW903 2317 -#define MACH_TYPE_MW2440 2318 -#define MACH_TYPE_ECAC2378 2319 -#define MACH_TYPE_TAZKIOSK 2320 -#define MACH_TYPE_WHITERABBIT_MCH 2321 -#define MACH_TYPE_SBOX9263 2322 -#define MACH_TYPE_OREO 2323 -#define MACH_TYPE_SMDK6442 2324 -#define MACH_TYPE_OPENRD_BASE 2325 -#define MACH_TYPE_INCREDIBLE 2326 -#define MACH_TYPE_INCREDIBLEC 2327 -#define MACH_TYPE_HEROCT 2328 -#define MACH_TYPE_MMNET1000 2329 -#define MACH_TYPE_DEVKIT8000 2330 -#define MACH_TYPE_DEVKIT9000 2331 -#define MACH_TYPE_MX31TXTR 2332 -#define MACH_TYPE_U380 2333 -#define MACH_TYPE_HUALU_BOARD 2334 -#define MACH_TYPE_NPCMX50 2335 -#define MACH_TYPE_MX51_LANGE51 2336 -#define MACH_TYPE_MX51_LANGE52 2337 -#define MACH_TYPE_RIOM 2338 -#define MACH_TYPE_COMCAS 2339 -#define MACH_TYPE_WSI_MX27 2340 -#define MACH_TYPE_CM_T35 2341 -#define MACH_TYPE_NET2BIG 2342 -#define MACH_TYPE_MOTOROLA_A1600 2343 -#define MACH_TYPE_IGEP0020 2344 -#define MACH_TYPE_IGEP0010 2345 -#define MACH_TYPE_MV6281GTWGE2 2346 -#define MACH_TYPE_SCAT100 2347 -#define MACH_TYPE_SANMINA 2348 -#define MACH_TYPE_MOMENTO 2349 -#define MACH_TYPE_NUC9XX 2350 -#define MACH_TYPE_NUC910EVB 2351 -#define MACH_TYPE_NUC920EVB 2352 -#define MACH_TYPE_NUC950EVB 2353 -#define MACH_TYPE_NUC945EVB 2354 -#define MACH_TYPE_NUC960EVB 2355 -#define MACH_TYPE_NUC932EVB 2356 -#define MACH_TYPE_NUC900 2357 -#define MACH_TYPE_SD1SOC 2358 -#define MACH_TYPE_LN2440BC 2359 -#define MACH_TYPE_RSBC 2360 -#define MACH_TYPE_OPENRD_CLIENT 2361 -#define MACH_TYPE_HPIPAQ11X 2362 -#define MACH_TYPE_WAYLAND 2363 -#define MACH_TYPE_ACNBSX102 2364 -#define MACH_TYPE_HWAT91 2365 -#define MACH_TYPE_AT91SAM9263CS 2366 -#define MACH_TYPE_CSB732 2367 -#define MACH_TYPE_U8500 2368 -#define MACH_TYPE_HUQIU 2369 -#define MACH_TYPE_MX51_KUNLUN 2370 -#define MACH_TYPE_PMT1G 2371 -#define MACH_TYPE_HTCELF 2372 -#define MACH_TYPE_ARMADILLO420 2373 -#define MACH_TYPE_ARMADILLO440 2374 -#define MACH_TYPE_U_CHIP_DUAL_ARM 2375 -#define MACH_TYPE_CSR_BDB3 2376 -#define MACH_TYPE_DOLBY_CAT1018 2377 -#define MACH_TYPE_HY9307 2378 -#define MACH_TYPE_A_ES 2379 -#define MACH_TYPE_DAVINCI_IRIF 2380 -#define MACH_TYPE_AGAMA9263 2381 -#define MACH_TYPE_MARVELL_JASPER 2382 -#define MACH_TYPE_FLINT 2383 -#define MACH_TYPE_TAVOREVB3 2384 -#define MACH_TYPE_SCH_M490 2386 -#define MACH_TYPE_RBL01 2387 -#define MACH_TYPE_OMNIFI 2388 -#define MACH_TYPE_OTAVALO 2389 -#define MACH_TYPE_SIENNA 2390 -#define MACH_TYPE_HTC_EXCALIBUR_S620 2391 -#define MACH_TYPE_HTC_OPAL 2392 -#define MACH_TYPE_TOUCHBOOK 2393 -#define MACH_TYPE_LATTE 2394 -#define MACH_TYPE_XA200 2395 -#define MACH_TYPE_NIMROD 2396 -#define MACH_TYPE_CC9P9215_3G 2397 -#define MACH_TYPE_CC9P9215_3GJS 2398 -#define MACH_TYPE_TK71 2399 -#define MACH_TYPE_COMHAM3525 2400 -#define MACH_TYPE_MX31EREBUS 2401 -#define MACH_TYPE_MCARDMX27 2402 -#define MACH_TYPE_PARADISE 2403 -#define MACH_TYPE_TIDE 2404 -#define MACH_TYPE_WZL2440 2405 -#define MACH_TYPE_SDRDEMO 2406 -#define MACH_TYPE_ETHERCAN2 2407 -#define MACH_TYPE_ECMIMG20 2408 -#define MACH_TYPE_OMAP_DRAGON 2409 -#define MACH_TYPE_HALO 2410 -#define MACH_TYPE_HUANGSHAN 2411 -#define MACH_TYPE_VL_MA2SC 2412 -#define MACH_TYPE_RAUMFELD_RC 2413 -#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 -#define MACH_TYPE_RAUMFELD_SPEAKER 2415 -#define MACH_TYPE_MULTIBUS_MASTER 2416 -#define MACH_TYPE_MULTIBUS_PBK 2417 -#define MACH_TYPE_TNETV107X 2418 -#define MACH_TYPE_SNAKE 2419 -#define MACH_TYPE_CWMX27 2420 -#define MACH_TYPE_SCH_M480 2421 -#define MACH_TYPE_PLATYPUS 2422 -#define MACH_TYPE_PSS2 2423 -#define MACH_TYPE_DAVINCI_APM150 2424 -#define MACH_TYPE_STR9100 2425 -#define MACH_TYPE_NET5BIG 2426 -#define MACH_TYPE_SEABED9263 2427 -#define MACH_TYPE_MX51_M2ID 2428 -#define MACH_TYPE_OCTVOCPLUS_EB 2429 -#define MACH_TYPE_KLK_FIREFOX 2430 -#define MACH_TYPE_KLK_WIRMA_MODULE 2431 -#define MACH_TYPE_KLK_WIRMA_MMI 2432 -#define MACH_TYPE_SUPERSONIC 2433 -#define MACH_TYPE_LIBERTY 2434 -#define MACH_TYPE_MH355 2435 -#define MACH_TYPE_PC7802 2436 -#define MACH_TYPE_GNET_SGC 2437 -#define MACH_TYPE_EINSTEIN15 2438 -#define MACH_TYPE_CMPD 2439 -#define MACH_TYPE_DAVINCI_HASE1 2440 -#define MACH_TYPE_LGEINCITEPHONE 2441 -#define MACH_TYPE_EA313X 2442 -#define MACH_TYPE_FWBD_39064 2443 -#define MACH_TYPE_FWBD_390128 2444 -#define MACH_TYPE_PELCO_MOE 2445 -#define MACH_TYPE_MINIMIX27 2446 -#define MACH_TYPE_OMAP3_THUNDER 2447 -#define MACH_TYPE_PASSIONC 2448 -#define MACH_TYPE_MX27AMATA 2449 -#define MACH_TYPE_BGAT1 2450 -#define MACH_TYPE_BUZZ 2451 -#define MACH_TYPE_MB9G20 2452 -#define MACH_TYPE_YUSHAN 2453 -#define MACH_TYPE_LIZARD 2454 -#define MACH_TYPE_OMAP3POLYCOM 2455 -#define MACH_TYPE_SMDKV210 2456 -#define MACH_TYPE_BRAVO 2457 -#define MACH_TYPE_SIOGENTOO1 2458 -#define MACH_TYPE_SIOGENTOO2 2459 -#define MACH_TYPE_SM3K 2460 -#define MACH_TYPE_ACER_TEMPO_F900 2461 -#define MACH_TYPE_SST61VC010_DEV 2462 -#define MACH_TYPE_GLITTERTIND 2463 -#define MACH_TYPE_OMAP_ZOOM3 2464 -#define MACH_TYPE_OMAP_3630SDP 2465 -#define MACH_TYPE_CYBOOK2440 2466 -#define MACH_TYPE_TORINO_S 2467 -#define MACH_TYPE_HAVANA 2468 -#define MACH_TYPE_BEAUMONT_11 2469 -#define MACH_TYPE_VANGUARD 2470 -#define MACH_TYPE_S5PC110_DRACO 2471 -#define MACH_TYPE_CARTESIO_TWO 2472 -#define MACH_TYPE_ASTER 2473 -#define MACH_TYPE_VOGUESV210 2474 -#define MACH_TYPE_ACM500X 2475 -#define MACH_TYPE_KM9260 2476 -#define MACH_TYPE_NIDEFLEXG1 2477 -#define MACH_TYPE_CTERA_PLUG_IO 2478 -#define MACH_TYPE_SMARTQ7 2479 -#define MACH_TYPE_AT91SAM9G10EK2 2480 -#define MACH_TYPE_ASUSP527 2481 -#define MACH_TYPE_AT91SAM9G20MPM2 2482 -#define MACH_TYPE_TOPASA900 2483 -#define MACH_TYPE_ELECTRUM_100 2484 -#define MACH_TYPE_MX51GRB 2485 -#define MACH_TYPE_XEA300 2486 -#define MACH_TYPE_HTCSTARTREK 2487 -#define MACH_TYPE_LIMA 2488 -#define MACH_TYPE_CSB740 2489 -#define MACH_TYPE_USB_S8815 2490 -#define MACH_TYPE_WATSON_EFM_PLUGIN 2491 -#define MACH_TYPE_MILKYWAY 2492 -#define MACH_TYPE_G4EVM 2493 -#define MACH_TYPE_PICOMOD6 2494 -#define MACH_TYPE_OMAPL138_HAWKBOARD 2495 -#define MACH_TYPE_IP6000 2496 -#define MACH_TYPE_IP6010 2497 -#define MACH_TYPE_UTM400 2498 -#define MACH_TYPE_OMAP3_ZYBEX 2499 -#define MACH_TYPE_WIRELESS_SPACE 2500 -#define MACH_TYPE_SX560 2501 -#define MACH_TYPE_TS41X 2502 -#define MACH_TYPE_ELPHEL10373 2503 -#define MACH_TYPE_RHOBOT 2504 -#define MACH_TYPE_MX51_REFRESH 2505 -#define MACH_TYPE_LS9260 2506 -#define MACH_TYPE_SHANK 2507 -#define MACH_TYPE_QSD8X50_ST1 2508 -#define MACH_TYPE_AT91SAM9M10EKES 2509 -#define MACH_TYPE_HIRAM 2510 -#define MACH_TYPE_PHY3250 2511 -#define MACH_TYPE_EA3250 2512 -#define MACH_TYPE_FDI3250 2513 -#define MACH_TYPE_WHITESTONE 2514 -#define MACH_TYPE_AT91SAM9263NIT 2515 -#define MACH_TYPE_CCMX51 2516 -#define MACH_TYPE_CCMX51JS 2517 -#define MACH_TYPE_CCWMX51 2518 -#define MACH_TYPE_CCWMX51JS 2519 -#define MACH_TYPE_MINI6410 2520 -#define MACH_TYPE_TINY6410 2521 -#define MACH_TYPE_NANO6410 2522 -#define MACH_TYPE_AT572D940HFNLDB 2523 -#define MACH_TYPE_HTCLEO 2524 -#define MACH_TYPE_AVP13 2525 -#define MACH_TYPE_XXSVIDEOD 2526 -#define MACH_TYPE_VPNEXT 2527 -#define MACH_TYPE_SWARCO_ITC3 2528 -#define MACH_TYPE_TX51 2529 -#define MACH_TYPE_DOLBY_CAT1021 2530 -#define MACH_TYPE_MX28EVK 2531 -#define MACH_TYPE_PHOENIX260 2532 -#define MACH_TYPE_UVACA_STORK 2533 -#define MACH_TYPE_SMARTQ5 2534 -#define MACH_TYPE_ALL3078 2535 -#define MACH_TYPE_CTERA_2BAY_DS 2536 -#define MACH_TYPE_SIOGENTOO3 2537 -#define MACH_TYPE_EPB5000 2538 -#define MACH_TYPE_HY9263 2539 -#define MACH_TYPE_ACER_TEMPO_M900 2540 -#define MACH_TYPE_ACER_TEMPO_DX900 2541 -#define MACH_TYPE_ACER_TEMPO_X960 2542 -#define MACH_TYPE_ACER_ETEN_V900 2543 -#define MACH_TYPE_ACER_ETEN_X900 2544 -#define MACH_TYPE_BONNELL 2545 -#define MACH_TYPE_OHT_MX27 2546 -#define MACH_TYPE_HTCQUARTZ 2547 -#define MACH_TYPE_DAVINCI_DM6467TEVM 2548 -#define MACH_TYPE_C3AX03 2549 -#define MACH_TYPE_MXT_TD60 2550 -#define MACH_TYPE_ESYX 2551 -#define MACH_TYPE_DOVE_DB2 2552 -#define MACH_TYPE_BULLDOG 2553 -#define MACH_TYPE_DERELL_ME2000 2554 -#define MACH_TYPE_BCMRING_BASE 2555 -#define MACH_TYPE_BCMRING_EVM 2556 -#define MACH_TYPE_BCMRING_EVM_JAZZ 2557 -#define MACH_TYPE_BCMRING_SP 2558 -#define MACH_TYPE_BCMRING_SV 2559 -#define MACH_TYPE_BCMRING_SV_JAZZ 2560 -#define MACH_TYPE_BCMRING_TABLET 2561 -#define MACH_TYPE_BCMRING_VP 2562 -#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563 -#define MACH_TYPE_BCMRING_SP_WQVGA 2564 -#define MACH_TYPE_BCMRING_CUSTOM 2565 -#define MACH_TYPE_ACER_S200 2566 -#define MACH_TYPE_BT270 2567 -#define MACH_TYPE_ISEO 2568 -#define MACH_TYPE_CEZANNE 2569 -#define MACH_TYPE_LUCCA 2570 -#define MACH_TYPE_SUPERSMART 2571 -#define MACH_TYPE_CS_MISANO 2572 -#define MACH_TYPE_MAGNOLIA2 2573 -#define MACH_TYPE_EMXX 2574 -#define MACH_TYPE_OUTLAW 2575 -#define MACH_TYPE_RIOT_BEI2 2576 -#define MACH_TYPE_RIOT_VOX 2577 -#define MACH_TYPE_RIOT_X37 2578 -#define MACH_TYPE_MEGA25MX 2579 -#define MACH_TYPE_BENZINA2 2580 -#define MACH_TYPE_IGNITE 2581 -#define MACH_TYPE_FOGGIA 2582 -#define MACH_TYPE_AREZZO 2583 -#define MACH_TYPE_LEICA_SKYWALKER 2584 -#define MACH_TYPE_JACINTO2_JAMR 2585 -#define MACH_TYPE_GTS_NOVA 2586 -#define MACH_TYPE_P3600 2587 -#define MACH_TYPE_DLT2 2588 -#define MACH_TYPE_DF3120 2589 -#define MACH_TYPE_ECUCORE_9G20 2590 -#define MACH_TYPE_NAUTEL_LPC3240 2591 -#define MACH_TYPE_GLACIER 2592 -#define MACH_TYPE_PHRAZER_BULLDOG 2593 -#define MACH_TYPE_OMAP3_BULLDOG 2594 -#define MACH_TYPE_PCA101 2595 -#define MACH_TYPE_BUZZC 2596 -#define MACH_TYPE_SASIE2 2597 -#define MACH_TYPE_DAVINCI_CIO 2598 -#define MACH_TYPE_SMARTMETER_DL 2599 -#define MACH_TYPE_WZL6410 2600 -#define MACH_TYPE_WZL6410M 2601 -#define MACH_TYPE_WZL6410F 2602 -#define MACH_TYPE_WZL6410I 2603 -#define MACH_TYPE_SPACECOM1 2604 -#define MACH_TYPE_PINGU920 2605 -#define MACH_TYPE_BRAVOC 2606 -#define MACH_TYPE_CYBO2440 2607 -#define MACH_TYPE_VDSSW 2608 -#define MACH_TYPE_ROMULUS 2609 -#define MACH_TYPE_OMAP_MAGIC 2610 -#define MACH_TYPE_ELTD100 2611 -#define MACH_TYPE_CAPC7117 2612 -#define MACH_TYPE_SWAN 2613 -#define MACH_TYPE_VEU 2614 -#define MACH_TYPE_RM2 2615 -#define MACH_TYPE_TT2100 2616 -#define MACH_TYPE_VENICE 2617 -#define MACH_TYPE_PC7323 2618 -#define MACH_TYPE_MASP 2619 -#define MACH_TYPE_FUJITSU_TVSTBSOC 2620 -#define MACH_TYPE_FUJITSU_TVSTBSOC1 2621 -#define MACH_TYPE_LEXIKON 2622 -#define MACH_TYPE_MINI2440V2 2623 -#define MACH_TYPE_ICONTROL 2624 -#define MACH_TYPE_SHEEVAD 2625 -#define MACH_TYPE_QSD8X50A_ST1_1 2626 -#define MACH_TYPE_QSD8X50A_ST1_5 2627 -#define MACH_TYPE_BEE 2628 -#define MACH_TYPE_MX23EVK 2629 -#define MACH_TYPE_AP4EVB 2630 -#define MACH_TYPE_STOCKHOLM 2631 -#define MACH_TYPE_LPC_H3131 2632 -#define MACH_TYPE_STINGRAY 2633 -#define MACH_TYPE_KRAKEN 2634 -#define MACH_TYPE_GW2388 2635 -#define MACH_TYPE_JADECPU 2636 -#define MACH_TYPE_CARLISLE 2637 -#define MACH_TYPE_LUX_SFT9 2638 -#define MACH_TYPE_NEMID_TB 2639 -#define MACH_TYPE_TERRIER 2640 -#define MACH_TYPE_TURBOT 2641 -#define MACH_TYPE_SANDDAB 2642 -#define MACH_TYPE_MX35_CICADA 2643 -#define MACH_TYPE_GHI2703D 2644 -#define MACH_TYPE_LUX_SFX9 2645 -#define MACH_TYPE_LUX_SF9G 2646 -#define MACH_TYPE_LUX_EDK9 2647 -#define MACH_TYPE_HW90240 2648 -#define MACH_TYPE_DM365_LEOPARD 2649 -#define MACH_TYPE_MITYOMAPL138 2650 -#define MACH_TYPE_SCAT110 2651 -#define MACH_TYPE_ACER_A1 2652 -#define MACH_TYPE_CMCONTROL 2653 -#define MACH_TYPE_PELCO_LAMAR 2654 -#define MACH_TYPE_RFP43 2655 -#define MACH_TYPE_SK86R0301 2656 -#define MACH_TYPE_CTPXA 2657 -#define MACH_TYPE_EPB_ARM9_A 2658 -#define MACH_TYPE_GURUPLUG 2659 -#define MACH_TYPE_SPEAR310 2660 -#define MACH_TYPE_SPEAR320 2661 -#define MACH_TYPE_ROBOTX 2662 -#define MACH_TYPE_LSXHL 2663 -#define MACH_TYPE_SMARTLITE 2664 -#define MACH_TYPE_CWS2 2665 -#define MACH_TYPE_M619 2666 -#define MACH_TYPE_SMARTVIEW 2667 -#define MACH_TYPE_LSA_SALSA 2668 -#define MACH_TYPE_KIZBOX 2669 -#define MACH_TYPE_HTCCHARMER 2670 -#define MACH_TYPE_GUF_NESO_LT 2671 -#define MACH_TYPE_PM9G45 2672 -#define MACH_TYPE_HTCPANTHER 2673 -#define MACH_TYPE_HTCPANTHER_CDMA 2674 -#define MACH_TYPE_REB01 2675 -#define MACH_TYPE_AQUILA 2676 -#define MACH_TYPE_SPARK_SLS_HW2 2677 -#define MACH_TYPE_ESATA_SHEEVAPLUG 2678 -#define MACH_TYPE_SURF7X30 2679 -#define MACH_TYPE_MICRO2440 2680 -#define MACH_TYPE_AM2440 2681 -#define MACH_TYPE_TQ2440 2682 -#define MACH_TYPE_LPC2478OEM 2683 -#define MACH_TYPE_AK880X 2684 -#define MACH_TYPE_COBRA3530 2685 -#define MACH_TYPE_PMPPB 2686 -#define MACH_TYPE_U6715 2687 -#define MACH_TYPE_AXAR1500_SENDER 2688 -#define MACH_TYPE_G30_DVB 2689 -#define MACH_TYPE_VC088X 2690 -#define MACH_TYPE_MIOA702 2691 -#define MACH_TYPE_HPMIN 2692 -#define MACH_TYPE_AK880XAK 2693 -#define MACH_TYPE_ARM926TOMAP850 2694 -#define MACH_TYPE_LKEVM 2695 -#define MACH_TYPE_MW6410 2696 -#define MACH_TYPE_TERASTATION_WXL 2697 -#define MACH_TYPE_CPU8000E 2698 -#define MACH_TYPE_CATANIA 2699 -#define MACH_TYPE_TOKYO 2700 -#define MACH_TYPE_MSM7201A_SURF 2701 -#define MACH_TYPE_MSM7201A_FFA 2702 -#define MACH_TYPE_MSM7X25_SURF 2703 -#define MACH_TYPE_MSM7X25_FFA 2704 -#define MACH_TYPE_MSM7X27_SURF 2705 -#define MACH_TYPE_MSM7X27_FFA 2706 -#define MACH_TYPE_MSM7X30_FFA 2707 -#define MACH_TYPE_QSD8X50_SURF 2708 -#define MACH_TYPE_QSD8X50_COMET 2709 -#define MACH_TYPE_QSD8X50_FFA 2710 -#define MACH_TYPE_QSD8X50A_SURF 2711 -#define MACH_TYPE_QSD8X50A_FFA 2712 -#define MACH_TYPE_XGCP10 2713 -#define MACH_TYPE_MCGWUMTS2A 2714 -#define MACH_TYPE_MOBIKT 2715 -#define MACH_TYPE_MX53_EVK 2716 -#define MACH_TYPE_IGEP0030 2717 -#define MACH_TYPE_AXELL_H40_H50_CTRL 2718 - -#ifdef CONFIG_ARCH_EBSA110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA110 -# endif -# define machine_is_ebsa110() (machine_arch_type == MACH_TYPE_EBSA110) -#else -# define machine_is_ebsa110() (0) -#endif - -#ifdef CONFIG_ARCH_RPC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCPC -# endif -# define machine_is_riscpc() (machine_arch_type == MACH_TYPE_RISCPC) -#else -# define machine_is_riscpc() (0) -#endif - -#ifdef CONFIG_ARCH_NEXUSPCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXUSPCI -# endif -# define machine_is_nexuspci() (machine_arch_type == MACH_TYPE_NEXUSPCI) -#else -# define machine_is_nexuspci() (0) -#endif - -#ifdef CONFIG_ARCH_EBSA285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA285 -# endif -# define machine_is_ebsa285() (machine_arch_type == MACH_TYPE_EBSA285) -#else -# define machine_is_ebsa285() (0) -#endif - -#ifdef CONFIG_ARCH_NETWINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETWINDER -# endif -# define machine_is_netwinder() (machine_arch_type == MACH_TYPE_NETWINDER) -#else -# define machine_is_netwinder() (0) -#endif - -#ifdef CONFIG_ARCH_CATS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATS -# endif -# define machine_is_cats() (machine_arch_type == MACH_TYPE_CATS) -#else -# define machine_is_cats() (0) -#endif - -#ifdef CONFIG_ARCH_TBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBOX -# endif -# define machine_is_tbox() (machine_arch_type == MACH_TYPE_TBOX) -#else -# define machine_is_tbox() (0) -#endif - -#ifdef CONFIG_ARCH_CO285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CO285 -# endif -# define machine_is_co285() (machine_arch_type == MACH_TYPE_CO285) -#else -# define machine_is_co285() (0) -#endif - -#ifdef CONFIG_ARCH_CLPS7110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLPS7110 -# endif -# define machine_is_clps7110() (machine_arch_type == MACH_TYPE_CLPS7110) -#else -# define machine_is_clps7110() (0) -#endif - -#ifdef CONFIG_ARCH_ARC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCHIMEDES -# endif -# define machine_is_archimedes() (machine_arch_type == MACH_TYPE_ARCHIMEDES) -#else -# define machine_is_archimedes() (0) -#endif - -#ifdef CONFIG_ARCH_A5K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A5K -# endif -# define machine_is_a5k() (machine_arch_type == MACH_TYPE_A5K) -#else -# define machine_is_a5k() (0) -#endif - -#ifdef CONFIG_ARCH_ETOILE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETOILE -# endif -# define machine_is_etoile() (machine_arch_type == MACH_TYPE_ETOILE) -#else -# define machine_is_etoile() (0) -#endif - -#ifdef CONFIG_ARCH_LACIE_NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LACIE_NAS -# endif -# define machine_is_lacie_nas() (machine_arch_type == MACH_TYPE_LACIE_NAS) -#else -# define machine_is_lacie_nas() (0) -#endif - -#ifdef CONFIG_ARCH_CLPS7500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLPS7500 -# endif -# define machine_is_clps7500() (machine_arch_type == MACH_TYPE_CLPS7500) -#else -# define machine_is_clps7500() (0) -#endif - -#ifdef CONFIG_ARCH_SHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHARK -# endif -# define machine_is_shark() (machine_arch_type == MACH_TYPE_SHARK) -#else -# define machine_is_shark() (0) -#endif - -#ifdef CONFIG_SA1100_BRUTUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRUTUS -# endif -# define machine_is_brutus() (machine_arch_type == MACH_TYPE_BRUTUS) -#else -# define machine_is_brutus() (0) -#endif - -#ifdef CONFIG_ARCH_PERSONAL_SERVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERSONAL_SERVER -# endif -# define machine_is_personal_server() (machine_arch_type == MACH_TYPE_PERSONAL_SERVER) -#else -# define machine_is_personal_server() (0) -#endif - -#ifdef CONFIG_SA1100_ITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITSY -# endif -# define machine_is_itsy() (machine_arch_type == MACH_TYPE_ITSY) -#else -# define machine_is_itsy() (0) -#endif - -#ifdef CONFIG_ARCH_L7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_L7200 -# endif -# define machine_is_l7200() (machine_arch_type == MACH_TYPE_L7200) -#else -# define machine_is_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_PLEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLEB -# endif -# define machine_is_pleb() (machine_arch_type == MACH_TYPE_PLEB) -#else -# define machine_is_pleb() (0) -#endif - -#ifdef CONFIG_ARCH_INTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTEGRATOR -# endif -# define machine_is_integrator() (machine_arch_type == MACH_TYPE_INTEGRATOR) -#else -# define machine_is_integrator() (0) -#endif - -#ifdef CONFIG_SA1100_H3600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3600 -# endif -# define machine_is_h3600() (machine_arch_type == MACH_TYPE_H3600) -#else -# define machine_is_h3600() (0) -#endif - -#ifdef CONFIG_ARCH_IXP1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP1200 -# endif -# define machine_is_ixp1200() (machine_arch_type == MACH_TYPE_IXP1200) -#else -# define machine_is_ixp1200() (0) -#endif - -#ifdef CONFIG_ARCH_P720T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P720T -# endif -# define machine_is_p720t() (machine_arch_type == MACH_TYPE_P720T) -#else -# define machine_is_p720t() (0) -#endif - -#ifdef CONFIG_SA1100_ASSABET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASSABET -# endif -# define machine_is_assabet() (machine_arch_type == MACH_TYPE_ASSABET) -#else -# define machine_is_assabet() (0) -#endif - -#ifdef CONFIG_SA1100_VICTOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VICTOR -# endif -# define machine_is_victor() (machine_arch_type == MACH_TYPE_VICTOR) -#else -# define machine_is_victor() (0) -#endif - -#ifdef CONFIG_SA1100_LART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LART -# endif -# define machine_is_lart() (machine_arch_type == MACH_TYPE_LART) -#else -# define machine_is_lart() (0) -#endif - -#ifdef CONFIG_SA1100_RANGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RANGER -# endif -# define machine_is_ranger() (machine_arch_type == MACH_TYPE_RANGER) -#else -# define machine_is_ranger() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSCLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSCLIENT -# endif -# define machine_is_graphicsclient() (machine_arch_type == MACH_TYPE_GRAPHICSCLIENT) -#else -# define machine_is_graphicsclient() (0) -#endif - -#ifdef CONFIG_SA1100_XP860 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP860 -# endif -# define machine_is_xp860() (machine_arch_type == MACH_TYPE_XP860) -#else -# define machine_is_xp860() (0) -#endif - -#ifdef CONFIG_SA1100_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CERF -# endif -# define machine_is_cerf() (machine_arch_type == MACH_TYPE_CERF) -#else -# define machine_is_cerf() (0) -#endif - -#ifdef CONFIG_SA1100_NANOENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANOENGINE -# endif -# define machine_is_nanoengine() (machine_arch_type == MACH_TYPE_NANOENGINE) -#else -# define machine_is_nanoengine() (0) -#endif - -#ifdef CONFIG_SA1100_FPIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FPIC -# endif -# define machine_is_fpic() (machine_arch_type == MACH_TYPE_FPIC) -#else -# define machine_is_fpic() (0) -#endif - -#ifdef CONFIG_SA1100_EXTENEX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXTENEX1 -# endif -# define machine_is_extenex1() (machine_arch_type == MACH_TYPE_EXTENEX1) -#else -# define machine_is_extenex1() (0) -#endif - -#ifdef CONFIG_SA1100_SHERMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHERMAN -# endif -# define machine_is_sherman() (machine_arch_type == MACH_TYPE_SHERMAN) -#else -# define machine_is_sherman() (0) -#endif - -#ifdef CONFIG_SA1100_ACCELENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_SA -# endif -# define machine_is_accelent_sa() (machine_arch_type == MACH_TYPE_ACCELENT_SA) -#else -# define machine_is_accelent_sa() (0) -#endif - -#ifdef CONFIG_ARCH_L7200_ACCELENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_L7200 -# endif -# define machine_is_accelent_l7200() (machine_arch_type == MACH_TYPE_ACCELENT_L7200) -#else -# define machine_is_accelent_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_NETPORT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETPORT -# endif -# define machine_is_netport() (machine_arch_type == MACH_TYPE_NETPORT) -#else -# define machine_is_netport() (0) -#endif - -#ifdef CONFIG_SA1100_PANGOLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PANGOLIN -# endif -# define machine_is_pangolin() (machine_arch_type == MACH_TYPE_PANGOLIN) -#else -# define machine_is_pangolin() (0) -#endif - -#ifdef CONFIG_SA1100_YOPY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOPY -# endif -# define machine_is_yopy() (machine_arch_type == MACH_TYPE_YOPY) -#else -# define machine_is_yopy() (0) -#endif - -#ifdef CONFIG_SA1100_COOLIDGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COOLIDGE -# endif -# define machine_is_coolidge() (machine_arch_type == MACH_TYPE_COOLIDGE) -#else -# define machine_is_coolidge() (0) -#endif - -#ifdef CONFIG_SA1100_HUW_WEBPANEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUW_WEBPANEL -# endif -# define machine_is_huw_webpanel() (machine_arch_type == MACH_TYPE_HUW_WEBPANEL) -#else -# define machine_is_huw_webpanel() (0) -#endif - -#ifdef CONFIG_ARCH_SPOTME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOTME -# endif -# define machine_is_spotme() (machine_arch_type == MACH_TYPE_SPOTME) -#else -# define machine_is_spotme() (0) -#endif - -#ifdef CONFIG_ARCH_FREEBIRD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FREEBIRD -# endif -# define machine_is_freebird() (machine_arch_type == MACH_TYPE_FREEBIRD) -#else -# define machine_is_freebird() (0) -#endif - -#ifdef CONFIG_ARCH_TI925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI925 -# endif -# define machine_is_ti925() (machine_arch_type == MACH_TYPE_TI925) -#else -# define machine_is_ti925() (0) -#endif - -#ifdef CONFIG_ARCH_RISCSTATION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCSTATION -# endif -# define machine_is_riscstation() (machine_arch_type == MACH_TYPE_RISCSTATION) -#else -# define machine_is_riscstation() (0) -#endif - -#ifdef CONFIG_SA1100_CAVY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAVY -# endif -# define machine_is_cavy() (machine_arch_type == MACH_TYPE_CAVY) -#else -# define machine_is_cavy() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA720 -# endif -# define machine_is_jornada720() (machine_arch_type == MACH_TYPE_JORNADA720) -#else -# define machine_is_jornada720() (0) -#endif - -#ifdef CONFIG_SA1100_OMNIMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMNIMETER -# endif -# define machine_is_omnimeter() (machine_arch_type == MACH_TYPE_OMNIMETER) -#else -# define machine_is_omnimeter() (0) -#endif - -#ifdef CONFIG_ARCH_EDB7211 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB7211 -# endif -# define machine_is_edb7211() (machine_arch_type == MACH_TYPE_EDB7211) -#else -# define machine_is_edb7211() (0) -#endif - -#ifdef CONFIG_SA1100_CITYGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CITYGO -# endif -# define machine_is_citygo() (machine_arch_type == MACH_TYPE_CITYGO) -#else -# define machine_is_citygo() (0) -#endif - -#ifdef CONFIG_SA1100_PFS168 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PFS168 -# endif -# define machine_is_pfs168() (machine_arch_type == MACH_TYPE_PFS168) -#else -# define machine_is_pfs168() (0) -#endif - -#ifdef CONFIG_SA1100_SPOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOT -# endif -# define machine_is_spot() (machine_arch_type == MACH_TYPE_SPOT) -#else -# define machine_is_spot() (0) -#endif - -#ifdef CONFIG_SA1100_FLEXANET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXANET -# endif -# define machine_is_flexanet() (machine_arch_type == MACH_TYPE_FLEXANET) -#else -# define machine_is_flexanet() (0) -#endif - -#ifdef CONFIG_ARCH_WEBPAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBPAL -# endif -# define machine_is_webpal() (machine_arch_type == MACH_TYPE_WEBPAL) -#else -# define machine_is_webpal() (0) -#endif - -#ifdef CONFIG_SA1100_LINPDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINPDA -# endif -# define machine_is_linpda() (machine_arch_type == MACH_TYPE_LINPDA) -#else -# define machine_is_linpda() (0) -#endif - -#ifdef CONFIG_ARCH_ANAKIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANAKIN -# endif -# define machine_is_anakin() (machine_arch_type == MACH_TYPE_ANAKIN) -#else -# define machine_is_anakin() (0) -#endif - -#ifdef CONFIG_SA1100_MVI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MVI -# endif -# define machine_is_mvi() (machine_arch_type == MACH_TYPE_MVI) -#else -# define machine_is_mvi() (0) -#endif - -#ifdef CONFIG_SA1100_JUPITER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JUPITER -# endif -# define machine_is_jupiter() (machine_arch_type == MACH_TYPE_JUPITER) -#else -# define machine_is_jupiter() (0) -#endif - -#ifdef CONFIG_ARCH_PSIONW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSIONW -# endif -# define machine_is_psionw() (machine_arch_type == MACH_TYPE_PSIONW) -#else -# define machine_is_psionw() (0) -#endif - -#ifdef CONFIG_SA1100_ALN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALN -# endif -# define machine_is_aln() (machine_arch_type == MACH_TYPE_ALN) -#else -# define machine_is_aln() (0) -#endif - -#ifdef CONFIG_ARCH_CAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMELOT -# endif -# define machine_is_epxa() (machine_arch_type == MACH_TYPE_CAMELOT) -#else -# define machine_is_epxa() (0) -#endif - -#ifdef CONFIG_SA1100_GDS2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GDS2200 -# endif -# define machine_is_gds2200() (machine_arch_type == MACH_TYPE_GDS2200) -#else -# define machine_is_gds2200() (0) -#endif - -#ifdef CONFIG_SA1100_PSION_SERIES7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSION_SERIES7 -# endif -# define machine_is_netbook() (machine_arch_type == MACH_TYPE_PSION_SERIES7) -#else -# define machine_is_netbook() (0) -#endif - -#ifdef CONFIG_SA1100_XFILE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XFILE -# endif -# define machine_is_xfile() (machine_arch_type == MACH_TYPE_XFILE) -#else -# define machine_is_xfile() (0) -#endif - -#ifdef CONFIG_ARCH_ACCELENT_EP9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_EP9312 -# endif -# define machine_is_accelent_ep9312() (machine_arch_type == MACH_TYPE_ACCELENT_EP9312) -#else -# define machine_is_accelent_ep9312() (0) -#endif - -#ifdef CONFIG_ARCH_IC200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IC200 -# endif -# define machine_is_ic200() (machine_arch_type == MACH_TYPE_IC200) -#else -# define machine_is_ic200() (0) -#endif - -#ifdef CONFIG_SA1100_CREDITLART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CREDITLART -# endif -# define machine_is_creditlart() (machine_arch_type == MACH_TYPE_CREDITLART) -#else -# define machine_is_creditlart() (0) -#endif - -#ifdef CONFIG_SA1100_HTM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTM -# endif -# define machine_is_htm() (machine_arch_type == MACH_TYPE_HTM) -#else -# define machine_is_htm() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80310 -# endif -# define machine_is_iq80310() (machine_arch_type == MACH_TYPE_IQ80310) -#else -# define machine_is_iq80310() (0) -#endif - -#ifdef CONFIG_SA1100_FREEBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FREEBOT -# endif -# define machine_is_freebot() (machine_arch_type == MACH_TYPE_FREEBOT) -#else -# define machine_is_freebot() (0) -#endif - -#ifdef CONFIG_ARCH_ENTEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENTEL -# endif -# define machine_is_entel() (machine_arch_type == MACH_TYPE_ENTEL) -#else -# define machine_is_entel() (0) -#endif - -#ifdef CONFIG_ARCH_ENP3510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENP3510 -# endif -# define machine_is_enp3510() (machine_arch_type == MACH_TYPE_ENP3510) -#else -# define machine_is_enp3510() (0) -#endif - -#ifdef CONFIG_SA1100_TRIZEPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS -# endif -# define machine_is_trizeps() (machine_arch_type == MACH_TYPE_TRIZEPS) -#else -# define machine_is_trizeps() (0) -#endif - -#ifdef CONFIG_SA1100_NESA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NESA -# endif -# define machine_is_nesa() (machine_arch_type == MACH_TYPE_NESA) -#else -# define machine_is_nesa() (0) -#endif - -#ifdef CONFIG_ARCH_VENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENUS -# endif -# define machine_is_venus() (machine_arch_type == MACH_TYPE_VENUS) -#else -# define machine_is_venus() (0) -#endif - -#ifdef CONFIG_ARCH_TARDIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TARDIS -# endif -# define machine_is_tardis() (machine_arch_type == MACH_TYPE_TARDIS) -#else -# define machine_is_tardis() (0) -#endif - -#ifdef CONFIG_ARCH_MERCURY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MERCURY -# endif -# define machine_is_mercury() (machine_arch_type == MACH_TYPE_MERCURY) -#else -# define machine_is_mercury() (0) -#endif - -#ifdef CONFIG_SA1100_EMPEG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPEG -# endif -# define machine_is_empeg() (machine_arch_type == MACH_TYPE_EMPEG) -#else -# define machine_is_empeg() (0) -#endif - -#ifdef CONFIG_ARCH_I80200FCC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I80200FCC -# endif -# define machine_is_adi_evb() (machine_arch_type == MACH_TYPE_I80200FCC) -#else -# define machine_is_adi_evb() (0) -#endif - -#ifdef CONFIG_SA1100_ITT_CPB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITT_CPB -# endif -# define machine_is_itt_cpb() (machine_arch_type == MACH_TYPE_ITT_CPB) -#else -# define machine_is_itt_cpb() (0) -#endif - -#ifdef CONFIG_SA1100_SVC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVC -# endif -# define machine_is_svc() (machine_arch_type == MACH_TYPE_SVC) -#else -# define machine_is_svc() (0) -#endif - -#ifdef CONFIG_SA1100_ALPHA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALPHA2 -# endif -# define machine_is_alpha2() (machine_arch_type == MACH_TYPE_ALPHA2) -#else -# define machine_is_alpha2() (0) -#endif - -#ifdef CONFIG_SA1100_ALPHA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALPHA1 -# endif -# define machine_is_alpha1() (machine_arch_type == MACH_TYPE_ALPHA1) -#else -# define machine_is_alpha1() (0) -#endif - -#ifdef CONFIG_ARCH_NETARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETARM -# endif -# define machine_is_netarm() (machine_arch_type == MACH_TYPE_NETARM) -#else -# define machine_is_netarm() (0) -#endif - -#ifdef CONFIG_SA1100_SIMPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMPAD -# endif -# define machine_is_simpad() (machine_arch_type == MACH_TYPE_SIMPAD) -#else -# define machine_is_simpad() (0) -#endif - -#ifdef CONFIG_ARCH_PDA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDA1 -# endif -# define machine_is_pda1() (machine_arch_type == MACH_TYPE_PDA1) -#else -# define machine_is_pda1() (0) -#endif - -#ifdef CONFIG_ARCH_LUBBOCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUBBOCK -# endif -# define machine_is_lubbock() (machine_arch_type == MACH_TYPE_LUBBOCK) -#else -# define machine_is_lubbock() (0) -#endif - -#ifdef CONFIG_ARCH_ANIKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANIKO -# endif -# define machine_is_aniko() (machine_arch_type == MACH_TYPE_ANIKO) -#else -# define machine_is_aniko() (0) -#endif - -#ifdef CONFIG_ARCH_CLEP7212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLEP7212 -# endif -# define machine_is_clep7212() (machine_arch_type == MACH_TYPE_CLEP7212) -#else -# define machine_is_clep7212() (0) -#endif - -#ifdef CONFIG_ARCH_CS89712 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS89712 -# endif -# define machine_is_cs89712() (machine_arch_type == MACH_TYPE_CS89712) -#else -# define machine_is_cs89712() (0) -#endif - -#ifdef CONFIG_SA1100_WEARARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEARARM -# endif -# define machine_is_weararm() (machine_arch_type == MACH_TYPE_WEARARM) -#else -# define machine_is_weararm() (0) -#endif - -#ifdef CONFIG_SA1100_POSSIO_PX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSSIO_PX -# endif -# define machine_is_possio_px() (machine_arch_type == MACH_TYPE_POSSIO_PX) -#else -# define machine_is_possio_px() (0) -#endif - -#ifdef CONFIG_SA1100_SIDEARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEARM -# endif -# define machine_is_sidearm() (machine_arch_type == MACH_TYPE_SIDEARM) -#else -# define machine_is_sidearm() (0) -#endif - -#ifdef CONFIG_SA1100_STORK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK -# endif -# define machine_is_stork() (machine_arch_type == MACH_TYPE_STORK) -#else -# define machine_is_stork() (0) -#endif - -#ifdef CONFIG_SA1100_SHANNON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHANNON -# endif -# define machine_is_shannon() (machine_arch_type == MACH_TYPE_SHANNON) -#else -# define machine_is_shannon() (0) -#endif - -#ifdef CONFIG_ARCH_ACE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACE -# endif -# define machine_is_ace() (machine_arch_type == MACH_TYPE_ACE) -#else -# define machine_is_ace() (0) -#endif - -#ifdef CONFIG_SA1100_BALLYARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLYARM -# endif -# define machine_is_ballyarm() (machine_arch_type == MACH_TYPE_BALLYARM) -#else -# define machine_is_ballyarm() (0) -#endif - -#ifdef CONFIG_SA1100_SIMPUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMPUTER -# endif -# define machine_is_simputer() (machine_arch_type == MACH_TYPE_SIMPUTER) -#else -# define machine_is_simputer() (0) -#endif - -#ifdef CONFIG_SA1100_NEXTERM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXTERM -# endif -# define machine_is_nexterm() (machine_arch_type == MACH_TYPE_NEXTERM) -#else -# define machine_is_nexterm() (0) -#endif - -#ifdef CONFIG_SA1100_SA1100_ELF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SA1100_ELF -# endif -# define machine_is_sa1100_elf() (machine_arch_type == MACH_TYPE_SA1100_ELF) -#else -# define machine_is_sa1100_elf() (0) -#endif - -#ifdef CONFIG_SA1100_GATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GATOR -# endif -# define machine_is_gator() (machine_arch_type == MACH_TYPE_GATOR) -#else -# define machine_is_gator() (0) -#endif - -#ifdef CONFIG_ARCH_GRANITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRANITE -# endif -# define machine_is_granite() (machine_arch_type == MACH_TYPE_GRANITE) -#else -# define machine_is_granite() (0) -#endif - -#ifdef CONFIG_SA1100_CONSUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONSUS -# endif -# define machine_is_consus() (machine_arch_type == MACH_TYPE_CONSUS) -#else -# define machine_is_consus() (0) -#endif - -#ifdef CONFIG_ARCH_AAED2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AAED2000 -# endif -# define machine_is_aaed2000() (machine_arch_type == MACH_TYPE_AAED2000) -#else -# define machine_is_aaed2000() (0) -#endif - -#ifdef CONFIG_ARCH_CDB89712 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDB89712 -# endif -# define machine_is_cdb89712() (machine_arch_type == MACH_TYPE_CDB89712) -#else -# define machine_is_cdb89712() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSMASTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSMASTER -# endif -# define machine_is_graphicsmaster() (machine_arch_type == MACH_TYPE_GRAPHICSMASTER) -#else -# define machine_is_graphicsmaster() (0) -#endif - -#ifdef CONFIG_SA1100_ADSBITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSY -# endif -# define machine_is_adsbitsy() (machine_arch_type == MACH_TYPE_ADSBITSY) -#else -# define machine_is_adsbitsy() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_IDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IDP -# endif -# define machine_is_pxa_idp() (machine_arch_type == MACH_TYPE_PXA_IDP) -#else -# define machine_is_pxa_idp() (0) -#endif - -#ifdef CONFIG_ARCH_PLCE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLCE -# endif -# define machine_is_plce() (machine_arch_type == MACH_TYPE_PLCE) -#else -# define machine_is_plce() (0) -#endif - -#ifdef CONFIG_SA1100_PT_SYSTEM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT_SYSTEM3 -# endif -# define machine_is_pt_system3() (machine_arch_type == MACH_TYPE_PT_SYSTEM3) -#else -# define machine_is_pt_system3() (0) -#endif - -#ifdef CONFIG_ARCH_MEDALB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEDALB -# endif -# define machine_is_murphy() (machine_arch_type == MACH_TYPE_MEDALB) -#else -# define machine_is_murphy() (0) -#endif - -#ifdef CONFIG_ARCH_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EAGLE -# endif -# define machine_is_eagle() (machine_arch_type == MACH_TYPE_EAGLE) -#else -# define machine_is_eagle() (0) -#endif - -#ifdef CONFIG_ARCH_DSC21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC21 -# endif -# define machine_is_dsc21() (machine_arch_type == MACH_TYPE_DSC21) -#else -# define machine_is_dsc21() (0) -#endif - -#ifdef CONFIG_ARCH_DSC24 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC24 -# endif -# define machine_is_dsc24() (machine_arch_type == MACH_TYPE_DSC24) -#else -# define machine_is_dsc24() (0) -#endif - -#ifdef CONFIG_ARCH_TI5472 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI5472 -# endif -# define machine_is_ti5472() (machine_arch_type == MACH_TYPE_TI5472) -#else -# define machine_is_ti5472() (0) -#endif - -#ifdef CONFIG_ARCH_AUTCPU12 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUTCPU12 -# endif -# define machine_is_autcpu12() (machine_arch_type == MACH_TYPE_AUTCPU12) -#else -# define machine_is_autcpu12() (0) -#endif - -#ifdef CONFIG_ARCH_UENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UENGINE -# endif -# define machine_is_uengine() (machine_arch_type == MACH_TYPE_UENGINE) -#else -# define machine_is_uengine() (0) -#endif - -#ifdef CONFIG_SA1100_BLUESTEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUESTEM -# endif -# define machine_is_bluestem() (machine_arch_type == MACH_TYPE_BLUESTEM) -#else -# define machine_is_bluestem() (0) -#endif - -#ifdef CONFIG_ARCH_XINGU8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XINGU8 -# endif -# define machine_is_xingu8() (machine_arch_type == MACH_TYPE_XINGU8) -#else -# define machine_is_xingu8() (0) -#endif - -#ifdef CONFIG_ARCH_BUSHSTB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUSHSTB -# endif -# define machine_is_bushstb() (machine_arch_type == MACH_TYPE_BUSHSTB) -#else -# define machine_is_bushstb() (0) -#endif - -#ifdef CONFIG_SA1100_EPSILON1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPSILON1 -# endif -# define machine_is_epsilon1() (machine_arch_type == MACH_TYPE_EPSILON1) -#else -# define machine_is_epsilon1() (0) -#endif - -#ifdef CONFIG_SA1100_BALLOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLOON -# endif -# define machine_is_balloon() (machine_arch_type == MACH_TYPE_BALLOON) -#else -# define machine_is_balloon() (0) -#endif - -#ifdef CONFIG_ARCH_PUPPY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUPPY -# endif -# define machine_is_puppy() (machine_arch_type == MACH_TYPE_PUPPY) -#else -# define machine_is_puppy() (0) -#endif - -#ifdef CONFIG_SA1100_ELROY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELROY -# endif -# define machine_is_elroy() (machine_arch_type == MACH_TYPE_ELROY) -#else -# define machine_is_elroy() (0) -#endif - -#ifdef CONFIG_ARCH_GMS720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GMS720 -# endif -# define machine_is_gms720() (machine_arch_type == MACH_TYPE_GMS720) -#else -# define machine_is_gms720() (0) -#endif - -#ifdef CONFIG_ARCH_S24X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S24X -# endif -# define machine_is_s24x() (machine_arch_type == MACH_TYPE_S24X) -#else -# define machine_is_s24x() (0) -#endif - -#ifdef CONFIG_ARCH_JTEL_CLEP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JTEL_CLEP7312 -# endif -# define machine_is_jtel_clep7312() (machine_arch_type == MACH_TYPE_JTEL_CLEP7312) -#else -# define machine_is_jtel_clep7312() (0) -#endif - -#ifdef CONFIG_ARCH_CX821XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX821XX -# endif -# define machine_is_cx821xx() (machine_arch_type == MACH_TYPE_CX821XX) -#else -# define machine_is_cx821xx() (0) -#endif - -#ifdef CONFIG_ARCH_EDB7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB7312 -# endif -# define machine_is_edb7312() (machine_arch_type == MACH_TYPE_EDB7312) -#else -# define machine_is_edb7312() (0) -#endif - -#ifdef CONFIG_SA1100_BSA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSA1110 -# endif -# define machine_is_bsa1110() (machine_arch_type == MACH_TYPE_BSA1110) -#else -# define machine_is_bsa1110() (0) -#endif - -#ifdef CONFIG_ARCH_POWERPIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POWERPIN -# endif -# define machine_is_powerpin() (machine_arch_type == MACH_TYPE_POWERPIN) -#else -# define machine_is_powerpin() (0) -#endif - -#ifdef CONFIG_ARCH_OPENARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENARM -# endif -# define machine_is_openarm() (machine_arch_type == MACH_TYPE_OPENARM) -#else -# define machine_is_openarm() (0) -#endif - -#ifdef CONFIG_SA1100_WHITECHAPEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WHITECHAPEL -# endif -# define machine_is_whitechapel() (machine_arch_type == MACH_TYPE_WHITECHAPEL) -#else -# define machine_is_whitechapel() (0) -#endif - -#ifdef CONFIG_SA1100_H3100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3100 -# endif -# define machine_is_h3100() (machine_arch_type == MACH_TYPE_H3100) -#else -# define machine_is_h3100() (0) -#endif - -#ifdef CONFIG_SA1100_H3800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3800 -# endif -# define machine_is_h3800() (machine_arch_type == MACH_TYPE_H3800) -#else -# define machine_is_h3800() (0) -#endif - -#ifdef CONFIG_ARCH_BLUE_V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUE_V1 -# endif -# define machine_is_blue_v1() (machine_arch_type == MACH_TYPE_BLUE_V1) -#else -# define machine_is_blue_v1() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_CERF -# endif -# define machine_is_pxa_cerf() (machine_arch_type == MACH_TYPE_PXA_CERF) -#else -# define machine_is_pxa_cerf() (0) -#endif - -#ifdef CONFIG_ARCH_ARM7TEVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM7TEVB -# endif -# define machine_is_arm7tevb() (machine_arch_type == MACH_TYPE_ARM7TEVB) -#else -# define machine_is_arm7tevb() (0) -#endif - -#ifdef CONFIG_SA1100_D7400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D7400 -# endif -# define machine_is_d7400() (machine_arch_type == MACH_TYPE_D7400) -#else -# define machine_is_d7400() (0) -#endif - -#ifdef CONFIG_ARCH_PIRANHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIRANHA -# endif -# define machine_is_piranha() (machine_arch_type == MACH_TYPE_PIRANHA) -#else -# define machine_is_piranha() (0) -#endif - -#ifdef CONFIG_SA1100_SBCAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBCAMELOT -# endif -# define machine_is_sbcamelot() (machine_arch_type == MACH_TYPE_SBCAMELOT) -#else -# define machine_is_sbcamelot() (0) -#endif - -#ifdef CONFIG_SA1100_KINGS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KINGS -# endif -# define machine_is_kings() (machine_arch_type == MACH_TYPE_KINGS) -#else -# define machine_is_kings() (0) -#endif - -#ifdef CONFIG_ARCH_SMDK2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2400 -# endif -# define machine_is_smdk2400() (machine_arch_type == MACH_TYPE_SMDK2400) -#else -# define machine_is_smdk2400() (0) -#endif - -#ifdef CONFIG_SA1100_COLLIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLLIE -# endif -# define machine_is_collie() (machine_arch_type == MACH_TYPE_COLLIE) -#else -# define machine_is_collie() (0) -#endif - -#ifdef CONFIG_ARCH_IDR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDR -# endif -# define machine_is_idr() (machine_arch_type == MACH_TYPE_IDR) -#else -# define machine_is_idr() (0) -#endif - -#ifdef CONFIG_SA1100_BADGE4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BADGE4 -# endif -# define machine_is_badge4() (machine_arch_type == MACH_TYPE_BADGE4) -#else -# define machine_is_badge4() (0) -#endif - -#ifdef CONFIG_ARCH_WEBNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBNET -# endif -# define machine_is_webnet() (machine_arch_type == MACH_TYPE_WEBNET) -#else -# define machine_is_webnet() (0) -#endif - -#ifdef CONFIG_SA1100_D7300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D7300 -# endif -# define machine_is_d7300() (machine_arch_type == MACH_TYPE_D7300) -#else -# define machine_is_d7300() (0) -#endif - -#ifdef CONFIG_SA1100_CEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEP -# endif -# define machine_is_cep() (machine_arch_type == MACH_TYPE_CEP) -#else -# define machine_is_cep() (0) -#endif - -#ifdef CONFIG_ARCH_FORTUNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET -# endif -# define machine_is_fortunet() (machine_arch_type == MACH_TYPE_FORTUNET) -#else -# define machine_is_fortunet() (0) -#endif - -#ifdef CONFIG_ARCH_VC547X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC547X -# endif -# define machine_is_vc547x() (machine_arch_type == MACH_TYPE_VC547X) -#else -# define machine_is_vc547x() (0) -#endif - -#ifdef CONFIG_SA1100_FILEWALKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FILEWALKER -# endif -# define machine_is_filewalker() (machine_arch_type == MACH_TYPE_FILEWALKER) -#else -# define machine_is_filewalker() (0) -#endif - -#ifdef CONFIG_SA1100_NETGATEWAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETGATEWAY -# endif -# define machine_is_netgateway() (machine_arch_type == MACH_TYPE_NETGATEWAY) -#else -# define machine_is_netgateway() (0) -#endif - -#ifdef CONFIG_SA1100_SYMBOL2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYMBOL2800 -# endif -# define machine_is_symbol2800() (machine_arch_type == MACH_TYPE_SYMBOL2800) -#else -# define machine_is_symbol2800() (0) -#endif - -#ifdef CONFIG_SA1100_SUNS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUNS -# endif -# define machine_is_suns() (machine_arch_type == MACH_TYPE_SUNS) -#else -# define machine_is_suns() (0) -#endif - -#ifdef CONFIG_SA1100_FRODO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRODO -# endif -# define machine_is_frodo() (machine_arch_type == MACH_TYPE_FRODO) -#else -# define machine_is_frodo() (0) -#endif - -#ifdef CONFIG_SA1100_MACH_TYTE_MS301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MACH_TYTE_MS301 -# endif -# define machine_is_ms301() (machine_arch_type == MACH_TYPE_MACH_TYTE_MS301) -#else -# define machine_is_ms301() (0) -#endif - -#ifdef CONFIG_ARCH_MX1ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1ADS -# endif -# define machine_is_mx1ads() (machine_arch_type == MACH_TYPE_MX1ADS) -#else -# define machine_is_mx1ads() (0) -#endif - -#ifdef CONFIG_ARCH_H7201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7201 -# endif -# define machine_is_h7201() (machine_arch_type == MACH_TYPE_H7201) -#else -# define machine_is_h7201() (0) -#endif - -#ifdef CONFIG_ARCH_H7202 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7202 -# endif -# define machine_is_h7202() (machine_arch_type == MACH_TYPE_H7202) -#else -# define machine_is_h7202() (0) -#endif - -#ifdef CONFIG_ARCH_AMICO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMICO -# endif -# define machine_is_amico() (machine_arch_type == MACH_TYPE_AMICO) -#else -# define machine_is_amico() (0) -#endif - -#ifdef CONFIG_SA1100_IAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IAM -# endif -# define machine_is_iam() (machine_arch_type == MACH_TYPE_IAM) -#else -# define machine_is_iam() (0) -#endif - -#ifdef CONFIG_SA1100_TT530 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT530 -# endif -# define machine_is_tt530() (machine_arch_type == MACH_TYPE_TT530) -#else -# define machine_is_tt530() (0) -#endif - -#ifdef CONFIG_ARCH_SAM2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM2400 -# endif -# define machine_is_sam2400() (machine_arch_type == MACH_TYPE_SAM2400) -#else -# define machine_is_sam2400() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA56X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA56X -# endif -# define machine_is_jornada56x() (machine_arch_type == MACH_TYPE_JORNADA56X) -#else -# define machine_is_jornada56x() (0) -#endif - -#ifdef CONFIG_SA1100_ACTIVE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTIVE -# endif -# define machine_is_active() (machine_arch_type == MACH_TYPE_ACTIVE) -#else -# define machine_is_active() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80321 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80321 -# endif -# define machine_is_iq80321() (machine_arch_type == MACH_TYPE_IQ80321) -#else -# define machine_is_iq80321() (0) -#endif - -#ifdef CONFIG_SA1100_WID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WID -# endif -# define machine_is_wid() (machine_arch_type == MACH_TYPE_WID) -#else -# define machine_is_wid() (0) -#endif - -#ifdef CONFIG_ARCH_SABINAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SABINAL -# endif -# define machine_is_sabinal() (machine_arch_type == MACH_TYPE_SABINAL) -#else -# define machine_is_sabinal() (0) -#endif - -#ifdef CONFIG_ARCH_IXP425_MATACUMBE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425_MATACUMBE -# endif -# define machine_is_ixp425_matacumbe() (machine_arch_type == MACH_TYPE_IXP425_MATACUMBE) -#else -# define machine_is_ixp425_matacumbe() (0) -#endif - -#ifdef CONFIG_SA1100_MINIPRINT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINIPRINT -# endif -# define machine_is_miniprint() (machine_arch_type == MACH_TYPE_MINIPRINT) -#else -# define machine_is_miniprint() (0) -#endif - -#ifdef CONFIG_ARCH_ADM510X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADM510X -# endif -# define machine_is_adm510x() (machine_arch_type == MACH_TYPE_ADM510X) -#else -# define machine_is_adm510x() (0) -#endif - -#ifdef CONFIG_SA1100_SVS200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVS200 -# endif -# define machine_is_svs200() (machine_arch_type == MACH_TYPE_SVS200) -#else -# define machine_is_svs200() (0) -#endif - -#ifdef CONFIG_ARCH_ATG_TCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATG_TCU -# endif -# define machine_is_atg_tcu() (machine_arch_type == MACH_TYPE_ATG_TCU) -#else -# define machine_is_atg_tcu() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA820 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA820 -# endif -# define machine_is_jornada820() (machine_arch_type == MACH_TYPE_JORNADA820) -#else -# define machine_is_jornada820() (0) -#endif - -#ifdef CONFIG_ARCH_S3C44B0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C44B0 -# endif -# define machine_is_s3c44b0() (machine_arch_type == MACH_TYPE_S3C44B0) -#else -# define machine_is_s3c44b0() (0) -#endif - -#ifdef CONFIG_ARCH_MARGIS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARGIS2 -# endif -# define machine_is_margis2() (machine_arch_type == MACH_TYPE_MARGIS2) -#else -# define machine_is_margis2() (0) -#endif - -#ifdef CONFIG_ARCH_KS8695 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695 -# endif -# define machine_is_ks8695() (machine_arch_type == MACH_TYPE_KS8695) -#else -# define machine_is_ks8695() (0) -#endif - -#ifdef CONFIG_ARCH_BRH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRH -# endif -# define machine_is_brh() (machine_arch_type == MACH_TYPE_BRH) -#else -# define machine_is_brh() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2410 -# endif -# define machine_is_s3c2410() (machine_arch_type == MACH_TYPE_S3C2410) -#else -# define machine_is_s3c2410() (0) -#endif - -#ifdef CONFIG_ARCH_POSSIO_PX30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSSIO_PX30 -# endif -# define machine_is_possio_px30() (machine_arch_type == MACH_TYPE_POSSIO_PX30) -#else -# define machine_is_possio_px30() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2800 -# endif -# define machine_is_s3c2800() (machine_arch_type == MACH_TYPE_S3C2800) -#else -# define machine_is_s3c2800() (0) -#endif - -#ifdef CONFIG_SA1100_FLEETWOOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEETWOOD -# endif -# define machine_is_fleetwood() (machine_arch_type == MACH_TYPE_FLEETWOOD) -#else -# define machine_is_fleetwood() (0) -#endif - -#ifdef CONFIG_ARCH_OMAHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAHA -# endif -# define machine_is_omaha() (machine_arch_type == MACH_TYPE_OMAHA) -#else -# define machine_is_omaha() (0) -#endif - -#ifdef CONFIG_ARCH_TA7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7 -# endif -# define machine_is_ta7() (machine_arch_type == MACH_TYPE_TA7) -#else -# define machine_is_ta7() (0) -#endif - -#ifdef CONFIG_SA1100_NOVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOVA -# endif -# define machine_is_nova() (machine_arch_type == MACH_TYPE_NOVA) -#else -# define machine_is_nova() (0) -#endif - -#ifdef CONFIG_ARCH_HMK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMK -# endif -# define machine_is_hmk() (machine_arch_type == MACH_TYPE_HMK) -#else -# define machine_is_hmk() (0) -#endif - -#ifdef CONFIG_ARCH_KARO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KARO -# endif -# define machine_is_karo() (machine_arch_type == MACH_TYPE_KARO) -#else -# define machine_is_karo() (0) -#endif - -#ifdef CONFIG_SA1100_FESTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FESTER -# endif -# define machine_is_fester() (machine_arch_type == MACH_TYPE_FESTER) -#else -# define machine_is_fester() (0) -#endif - -#ifdef CONFIG_ARCH_GPI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GPI -# endif -# define machine_is_gpi() (machine_arch_type == MACH_TYPE_GPI) -#else -# define machine_is_gpi() (0) -#endif - -#ifdef CONFIG_ARCH_SMDK2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410 -# endif -# define machine_is_smdk2410() (machine_arch_type == MACH_TYPE_SMDK2410) -#else -# define machine_is_smdk2410() (0) -#endif - -#ifdef CONFIG_ARCH_I519 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I519 -# endif -# define machine_is_i519() (machine_arch_type == MACH_TYPE_I519) -#else -# define machine_is_i519() (0) -#endif - -#ifdef CONFIG_SA1100_NEXIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXIO -# endif -# define machine_is_nexio() (machine_arch_type == MACH_TYPE_NEXIO) -#else -# define machine_is_nexio() (0) -#endif - -#ifdef CONFIG_SA1100_BITBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BITBOX -# endif -# define machine_is_bitbox() (machine_arch_type == MACH_TYPE_BITBOX) -#else -# define machine_is_bitbox() (0) -#endif - -#ifdef CONFIG_SA1100_G200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G200 -# endif -# define machine_is_g200() (machine_arch_type == MACH_TYPE_G200) -#else -# define machine_is_g200() (0) -#endif - -#ifdef CONFIG_SA1100_GILL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GILL -# endif -# define machine_is_gill() (machine_arch_type == MACH_TYPE_GILL) -#else -# define machine_is_gill() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_MERCURY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_MERCURY -# endif -# define machine_is_pxa_mercury() (machine_arch_type == MACH_TYPE_PXA_MERCURY) -#else -# define machine_is_pxa_mercury() (0) -#endif - -#ifdef CONFIG_ARCH_CEIVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEIVA -# endif -# define machine_is_ceiva() (machine_arch_type == MACH_TYPE_CEIVA) -#else -# define machine_is_ceiva() (0) -#endif - -#ifdef CONFIG_SA1100_FRET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRET -# endif -# define machine_is_fret() (machine_arch_type == MACH_TYPE_FRET) -#else -# define machine_is_fret() (0) -#endif - -#ifdef CONFIG_SA1100_EMAILPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMAILPHONE -# endif -# define machine_is_emailphone() (machine_arch_type == MACH_TYPE_EMAILPHONE) -#else -# define machine_is_emailphone() (0) -#endif - -#ifdef CONFIG_ARCH_H3900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3900 -# endif -# define machine_is_h3900() (machine_arch_type == MACH_TYPE_H3900) -#else -# define machine_is_h3900() (0) -#endif - -#ifdef CONFIG_ARCH_PXA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA1 -# endif -# define machine_is_pxa1() (machine_arch_type == MACH_TYPE_PXA1) -#else -# define machine_is_pxa1() (0) -#endif - -#ifdef CONFIG_SA1100_KOAN369 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOAN369 -# endif -# define machine_is_koan369() (machine_arch_type == MACH_TYPE_KOAN369) -#else -# define machine_is_koan369() (0) -#endif - -#ifdef CONFIG_ARCH_COGENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COGENT -# endif -# define machine_is_cogent() (machine_arch_type == MACH_TYPE_COGENT) -#else -# define machine_is_cogent() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER -# endif -# define machine_is_esl_simputer() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER) -#else -# define machine_is_esl_simputer() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER_CLR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_CLR -# endif -# define machine_is_esl_simputer_clr() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_CLR) -#else -# define machine_is_esl_simputer_clr() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER_BW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_BW -# endif -# define machine_is_esl_simputer_bw() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_BW) -#else -# define machine_is_esl_simputer_bw() (0) -#endif - -#ifdef CONFIG_ARCH_HHP_CRADLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHP_CRADLE -# endif -# define machine_is_hhp_cradle() (machine_arch_type == MACH_TYPE_HHP_CRADLE) -#else -# define machine_is_hhp_cradle() (0) -#endif - -#ifdef CONFIG_ARCH_HE500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HE500 -# endif -# define machine_is_he500() (machine_arch_type == MACH_TYPE_HE500) -#else -# define machine_is_he500() (0) -#endif - -#ifdef CONFIG_SA1100_INHANDELF2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDELF2 -# endif -# define machine_is_inhandelf2() (machine_arch_type == MACH_TYPE_INHANDELF2) -#else -# define machine_is_inhandelf2() (0) -#endif - -#ifdef CONFIG_SA1100_INHANDFTIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDFTIP -# endif -# define machine_is_inhandftip() (machine_arch_type == MACH_TYPE_INHANDFTIP) -#else -# define machine_is_inhandftip() (0) -#endif - -#ifdef CONFIG_SA1100_DNP1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DNP1110 -# endif -# define machine_is_dnp1110() (machine_arch_type == MACH_TYPE_DNP1110) -#else -# define machine_is_dnp1110() (0) -#endif - -#ifdef CONFIG_SA1100_PNP1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNP1110 -# endif -# define machine_is_pnp1110() (machine_arch_type == MACH_TYPE_PNP1110) -#else -# define machine_is_pnp1110() (0) -#endif - -#ifdef CONFIG_ARCH_CSB226 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB226 -# endif -# define machine_is_csb226() (machine_arch_type == MACH_TYPE_CSB226) -#else -# define machine_is_csb226() (0) -#endif - -#ifdef CONFIG_SA1100_ARNOLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARNOLD -# endif -# define machine_is_arnold() (machine_arch_type == MACH_TYPE_ARNOLD) -#else -# define machine_is_arnold() (0) -#endif - -#ifdef CONFIG_MACH_VOICEBLUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOICEBLUE -# endif -# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE) -#else -# define machine_is_voiceblue() (0) -#endif - -#ifdef CONFIG_ARCH_JZ8028 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JZ8028 -# endif -# define machine_is_jz8028() (machine_arch_type == MACH_TYPE_JZ8028) -#else -# define machine_is_jz8028() (0) -#endif - -#ifdef CONFIG_ARCH_H5400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H5400 -# endif -# define machine_is_h5400() (machine_arch_type == MACH_TYPE_H5400) -#else -# define machine_is_h5400() (0) -#endif - -#ifdef CONFIG_SA1100_FORTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTE -# endif -# define machine_is_forte() (machine_arch_type == MACH_TYPE_FORTE) -#else -# define machine_is_forte() (0) -#endif - -#ifdef CONFIG_SA1100_ACAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACAM -# endif -# define machine_is_acam() (machine_arch_type == MACH_TYPE_ACAM) -#else -# define machine_is_acam() (0) -#endif - -#ifdef CONFIG_SA1100_ABOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ABOX -# endif -# define machine_is_abox() (machine_arch_type == MACH_TYPE_ABOX) -#else -# define machine_is_abox() (0) -#endif - -#ifdef CONFIG_ARCH_ATMEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATMEL -# endif -# define machine_is_atmel() (machine_arch_type == MACH_TYPE_ATMEL) -#else -# define machine_is_atmel() (0) -#endif - -#ifdef CONFIG_ARCH_SITSANG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SITSANG -# endif -# define machine_is_sitsang() (machine_arch_type == MACH_TYPE_SITSANG) -#else -# define machine_is_sitsang() (0) -#endif - -#ifdef CONFIG_SA1100_CPU1110LCDNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPU1110LCDNET -# endif -# define machine_is_cpu1110lcdnet() (machine_arch_type == MACH_TYPE_CPU1110LCDNET) -#else -# define machine_is_cpu1110lcdnet() (0) -#endif - -#ifdef CONFIG_ARCH_MPL_VCMA9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPL_VCMA9 -# endif -# define machine_is_mpl_vcma9() (machine_arch_type == MACH_TYPE_MPL_VCMA9) -#else -# define machine_is_mpl_vcma9() (0) -#endif - -#ifdef CONFIG_ARCH_OPUS_A1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPUS_A1 -# endif -# define machine_is_opus_a1() (machine_arch_type == MACH_TYPE_OPUS_A1) -#else -# define machine_is_opus_a1() (0) -#endif - -#ifdef CONFIG_ARCH_DAYTONA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAYTONA -# endif -# define machine_is_daytona() (machine_arch_type == MACH_TYPE_DAYTONA) -#else -# define machine_is_daytona() (0) -#endif - -#ifdef CONFIG_SA1100_KILLBEAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KILLBEAR -# endif -# define machine_is_killbear() (machine_arch_type == MACH_TYPE_KILLBEAR) -#else -# define machine_is_killbear() (0) -#endif - -#ifdef CONFIG_ARCH_YOHO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOHO -# endif -# define machine_is_yoho() (machine_arch_type == MACH_TYPE_YOHO) -#else -# define machine_is_yoho() (0) -#endif - -#ifdef CONFIG_ARCH_JASPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JASPER -# endif -# define machine_is_jasper() (machine_arch_type == MACH_TYPE_JASPER) -#else -# define machine_is_jasper() (0) -#endif - -#ifdef CONFIG_ARCH_DSC25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC25 -# endif -# define machine_is_dsc25() (machine_arch_type == MACH_TYPE_DSC25) -#else -# define machine_is_dsc25() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_INNOVATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_INNOVATOR -# endif -# define machine_is_omap_innovator() (machine_arch_type == MACH_TYPE_OMAP_INNOVATOR) -#else -# define machine_is_omap_innovator() (0) -#endif - -#ifdef CONFIG_ARCH_RAMSES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAMSES -# endif -# define machine_is_mnci() (machine_arch_type == MACH_TYPE_RAMSES) -#else -# define machine_is_mnci() (0) -#endif - -#ifdef CONFIG_ARCH_S28X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S28X -# endif -# define machine_is_s28x() (machine_arch_type == MACH_TYPE_S28X) -#else -# define machine_is_s28x() (0) -#endif - -#ifdef CONFIG_ARCH_MPORT3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT3 -# endif -# define machine_is_mport3() (machine_arch_type == MACH_TYPE_MPORT3) -#else -# define machine_is_mport3() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_EAGLE250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_EAGLE250 -# endif -# define machine_is_pxa_eagle250() (machine_arch_type == MACH_TYPE_PXA_EAGLE250) -#else -# define machine_is_pxa_eagle250() (0) -#endif - -#ifdef CONFIG_ARCH_PDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDB -# endif -# define machine_is_pdb() (machine_arch_type == MACH_TYPE_PDB) -#else -# define machine_is_pdb() (0) -#endif - -#ifdef CONFIG_SA1100_BLUE_2G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUE_2G -# endif -# define machine_is_blue_2g() (machine_arch_type == MACH_TYPE_BLUE_2G) -#else -# define machine_is_blue_2g() (0) -#endif - -#ifdef CONFIG_SA1100_BLUEARCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEARCH -# endif -# define machine_is_bluearch() (machine_arch_type == MACH_TYPE_BLUEARCH) -#else -# define machine_is_bluearch() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2400 -# endif -# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400) -#else -# define machine_is_ixdp2400() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2800 -# endif -# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800) -#else -# define machine_is_ixdp2800() (0) -#endif - -#ifdef CONFIG_SA1100_EXPLORER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPLORER -# endif -# define machine_is_explorer() (machine_arch_type == MACH_TYPE_EXPLORER) -#else -# define machine_is_explorer() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP425 -# endif -# define machine_is_ixdp425() (machine_arch_type == MACH_TYPE_IXDP425) -#else -# define machine_is_ixdp425() (0) -#endif - -#ifdef CONFIG_ARCH_CHIMP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHIMP -# endif -# define machine_is_chimp() (machine_arch_type == MACH_TYPE_CHIMP) -#else -# define machine_is_chimp() (0) -#endif - -#ifdef CONFIG_ARCH_STORK_NEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK_NEST -# endif -# define machine_is_stork_nest() (machine_arch_type == MACH_TYPE_STORK_NEST) -#else -# define machine_is_stork_nest() (0) -#endif - -#ifdef CONFIG_ARCH_STORK_EGG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK_EGG -# endif -# define machine_is_stork_egg() (machine_arch_type == MACH_TYPE_STORK_EGG) -#else -# define machine_is_stork_egg() (0) -#endif - -#ifdef CONFIG_SA1100_WISMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WISMO -# endif -# define machine_is_wismo() (machine_arch_type == MACH_TYPE_WISMO) -#else -# define machine_is_wismo() (0) -#endif - -#ifdef CONFIG_ARCH_EZLINX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZLINX -# endif -# define machine_is_ezlinx() (machine_arch_type == MACH_TYPE_EZLINX) -#else -# define machine_is_ezlinx() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200 -# endif -# define machine_is_at91rm9200() (machine_arch_type == MACH_TYPE_AT91RM9200) -#else -# define machine_is_at91rm9200() (0) -#endif - -#ifdef CONFIG_ARCH_ADTECH_ORION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADTECH_ORION -# endif -# define machine_is_adtech_orion() (machine_arch_type == MACH_TYPE_ADTECH_ORION) -#else -# define machine_is_adtech_orion() (0) -#endif - -#ifdef CONFIG_ARCH_NEPTUNE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEPTUNE -# endif -# define machine_is_neptune() (machine_arch_type == MACH_TYPE_NEPTUNE) -#else -# define machine_is_neptune() (0) -#endif - -#ifdef CONFIG_SA1100_HACKKIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HACKKIT -# endif -# define machine_is_hackkit() (machine_arch_type == MACH_TYPE_HACKKIT) -#else -# define machine_is_hackkit() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_WINS30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_WINS30 -# endif -# define machine_is_pxa_wins30() (machine_arch_type == MACH_TYPE_PXA_WINS30) -#else -# define machine_is_pxa_wins30() (0) -#endif - -#ifdef CONFIG_SA1100_LAVINNA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LAVINNA -# endif -# define machine_is_lavinna() (machine_arch_type == MACH_TYPE_LAVINNA) -#else -# define machine_is_lavinna() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_UENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_UENGINE -# endif -# define machine_is_pxa_uengine() (machine_arch_type == MACH_TYPE_PXA_UENGINE) -#else -# define machine_is_pxa_uengine() (0) -#endif - -#ifdef CONFIG_ARCH_INNOKOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INNOKOM -# endif -# define machine_is_innokom() (machine_arch_type == MACH_TYPE_INNOKOM) -#else -# define machine_is_innokom() (0) -#endif - -#ifdef CONFIG_ARCH_BMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BMS -# endif -# define machine_is_bms() (machine_arch_type == MACH_TYPE_BMS) -#else -# define machine_is_bms() (0) -#endif - -#ifdef CONFIG_ARCH_IXCDP1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXCDP1100 -# endif -# define machine_is_ixcdp1100() (machine_arch_type == MACH_TYPE_IXCDP1100) -#else -# define machine_is_ixcdp1100() (0) -#endif - -#ifdef CONFIG_ARCH_PRPMC1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRPMC1100 -# endif -# define machine_is_prpmc1100() (machine_arch_type == MACH_TYPE_PRPMC1100) -#else -# define machine_is_prpmc1100() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200DK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200DK -# endif -# define machine_is_at91rm9200dk() (machine_arch_type == MACH_TYPE_AT91RM9200DK) -#else -# define machine_is_at91rm9200dk() (0) -#endif - -#ifdef CONFIG_ARCH_ARMSTICK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMSTICK -# endif -# define machine_is_armstick() (machine_arch_type == MACH_TYPE_ARMSTICK) -#else -# define machine_is_armstick() (0) -#endif - -#ifdef CONFIG_ARCH_ARMONIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMONIE -# endif -# define machine_is_armonie() (machine_arch_type == MACH_TYPE_ARMONIE) -#else -# define machine_is_armonie() (0) -#endif - -#ifdef CONFIG_ARCH_MPORT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT1 -# endif -# define machine_is_mport1() (machine_arch_type == MACH_TYPE_MPORT1) -#else -# define machine_is_mport1() (0) -#endif - -#ifdef CONFIG_ARCH_S3C5410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C5410 -# endif -# define machine_is_s3c5410() (machine_arch_type == MACH_TYPE_S3C5410) -#else -# define machine_is_s3c5410() (0) -#endif - -#ifdef CONFIG_ARCH_ZCP320A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZCP320A -# endif -# define machine_is_zcp320a() (machine_arch_type == MACH_TYPE_ZCP320A) -#else -# define machine_is_zcp320a() (0) -#endif - -#ifdef CONFIG_ARCH_I_BOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I_BOX -# endif -# define machine_is_i_box() (machine_arch_type == MACH_TYPE_I_BOX) -#else -# define machine_is_i_box() (0) -#endif - -#ifdef CONFIG_ARCH_STLC1502 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STLC1502 -# endif -# define machine_is_stlc1502() (machine_arch_type == MACH_TYPE_STLC1502) -#else -# define machine_is_stlc1502() (0) -#endif - -#ifdef CONFIG_ARCH_SIREN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIREN -# endif -# define machine_is_siren() (machine_arch_type == MACH_TYPE_SIREN) -#else -# define machine_is_siren() (0) -#endif - -#ifdef CONFIG_ARCH_GREENLAKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GREENLAKE -# endif -# define machine_is_greenlake() (machine_arch_type == MACH_TYPE_GREENLAKE) -#else -# define machine_is_greenlake() (0) -#endif - -#ifdef CONFIG_ARCH_ARGUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARGUS -# endif -# define machine_is_argus() (machine_arch_type == MACH_TYPE_ARGUS) -#else -# define machine_is_argus() (0) -#endif - -#ifdef CONFIG_SA1100_COMBADGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMBADGE -# endif -# define machine_is_combadge() (machine_arch_type == MACH_TYPE_COMBADGE) -#else -# define machine_is_combadge() (0) -#endif - -#ifdef CONFIG_ARCH_ROKEPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROKEPXA -# endif -# define machine_is_rokepxa() (machine_arch_type == MACH_TYPE_ROKEPXA) -#else -# define machine_is_rokepxa() (0) -#endif - -#ifdef CONFIG_ARCH_CINTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CINTEGRATOR -# endif -# define machine_is_cintegrator() (machine_arch_type == MACH_TYPE_CINTEGRATOR) -#else -# define machine_is_cintegrator() (0) -#endif - -#ifdef CONFIG_ARCH_GUIDEA07 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUIDEA07 -# endif -# define machine_is_guidea07() (machine_arch_type == MACH_TYPE_GUIDEA07) -#else -# define machine_is_guidea07() (0) -#endif - -#ifdef CONFIG_ARCH_TAT257 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAT257 -# endif -# define machine_is_tat257() (machine_arch_type == MACH_TYPE_TAT257) -#else -# define machine_is_tat257() (0) -#endif - -#ifdef CONFIG_ARCH_IGP2425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGP2425 -# endif -# define machine_is_igp2425() (machine_arch_type == MACH_TYPE_IGP2425) -#else -# define machine_is_igp2425() (0) -#endif - -#ifdef CONFIG_ARCH_BLUEGRAMMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEGRAMMA -# endif -# define machine_is_bluegrama() (machine_arch_type == MACH_TYPE_BLUEGRAMMA) -#else -# define machine_is_bluegrama() (0) -#endif - -#ifdef CONFIG_ARCH_IPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPOD -# endif -# define machine_is_ipod() (machine_arch_type == MACH_TYPE_IPOD) -#else -# define machine_is_ipod() (0) -#endif - -#ifdef CONFIG_ARCH_ADSBITSYX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYX -# endif -# define machine_is_adsbitsyx() (machine_arch_type == MACH_TYPE_ADSBITSYX) -#else -# define machine_is_adsbitsyx() (0) -#endif - -#ifdef CONFIG_ARCH_TRIZEPS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS2 -# endif -# define machine_is_trizeps2() (machine_arch_type == MACH_TYPE_TRIZEPS2) -#else -# define machine_is_trizeps2() (0) -#endif - -#ifdef CONFIG_ARCH_VIPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIPER -# endif -# define machine_is_viper() (machine_arch_type == MACH_TYPE_VIPER) -#else -# define machine_is_viper() (0) -#endif - -#ifdef CONFIG_SA1100_ADSBITSYPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYPLUS -# endif -# define machine_is_adsbitsyplus() (machine_arch_type == MACH_TYPE_ADSBITSYPLUS) -#else -# define machine_is_adsbitsyplus() (0) -#endif - -#ifdef CONFIG_SA1100_ADSAGC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSAGC -# endif -# define machine_is_adsagc() (machine_arch_type == MACH_TYPE_ADSAGC) -#else -# define machine_is_adsagc() (0) -#endif - -#ifdef CONFIG_ARCH_STP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STP7312 -# endif -# define machine_is_stp7312() (machine_arch_type == MACH_TYPE_STP7312) -#else -# define machine_is_stp7312() (0) -#endif - -#ifdef CONFIG_MACH_NX_PHNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PHNX -# endif -# define machine_is_nx_phnx() (machine_arch_type == MACH_TYPE_NX_PHNX) -#else -# define machine_is_nx_phnx() (0) -#endif - -#ifdef CONFIG_ARCH_WEP_EP250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEP_EP250 -# endif -# define machine_is_wep_ep250() (machine_arch_type == MACH_TYPE_WEP_EP250) -#else -# define machine_is_wep_ep250() (0) -#endif - -#ifdef CONFIG_ARCH_INHANDELF3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDELF3 -# endif -# define machine_is_inhandelf3() (machine_arch_type == MACH_TYPE_INHANDELF3) -#else -# define machine_is_inhandelf3() (0) -#endif - -#ifdef CONFIG_ARCH_ADI_COYOTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADI_COYOTE -# endif -# define machine_is_adi_coyote() (machine_arch_type == MACH_TYPE_ADI_COYOTE) -#else -# define machine_is_adi_coyote() (0) -#endif - -#ifdef CONFIG_ARCH_IYONIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IYONIX -# endif -# define machine_is_iyonix() (machine_arch_type == MACH_TYPE_IYONIX) -#else -# define machine_is_iyonix() (0) -#endif - -#ifdef CONFIG_ARCH_DAMICAM_SA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAMICAM_SA1110 -# endif -# define machine_is_damicam1() (machine_arch_type == MACH_TYPE_DAMICAM_SA1110) -#else -# define machine_is_damicam1() (0) -#endif - -#ifdef CONFIG_ARCH_MEG03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEG03 -# endif -# define machine_is_meg03() (machine_arch_type == MACH_TYPE_MEG03) -#else -# define machine_is_meg03() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_WHITECHAPEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_WHITECHAPEL -# endif -# define machine_is_pxa_whitechapel() (machine_arch_type == MACH_TYPE_PXA_WHITECHAPEL) -#else -# define machine_is_pxa_whitechapel() (0) -#endif - -#ifdef CONFIG_ARCH_NWSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NWSC -# endif -# define machine_is_nwsc() (machine_arch_type == MACH_TYPE_NWSC) -#else -# define machine_is_nwsc() (0) -#endif - -#ifdef CONFIG_ARCH_NWLARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NWLARM -# endif -# define machine_is_nwlarm() (machine_arch_type == MACH_TYPE_NWLARM) -#else -# define machine_is_nwlarm() (0) -#endif - -#ifdef CONFIG_ARCH_IXP425_MGUARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425_MGUARD -# endif -# define machine_is_ixp425_mguard() (machine_arch_type == MACH_TYPE_IXP425_MGUARD) -#else -# define machine_is_ixp425_mguard() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_NETDCU4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_NETDCU4 -# endif -# define machine_is_pxa_netdcu4() (machine_arch_type == MACH_TYPE_PXA_NETDCU4) -#else -# define machine_is_pxa_netdcu4() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2401 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2401 -# endif -# define machine_is_ixdp2401() (machine_arch_type == MACH_TYPE_IXDP2401) -#else -# define machine_is_ixdp2401() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2801 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2801 -# endif -# define machine_is_ixdp2801() (machine_arch_type == MACH_TYPE_IXDP2801) -#else -# define machine_is_ixdp2801() (0) -#endif - -#ifdef CONFIG_ARCH_ZODIAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZODIAC -# endif -# define machine_is_zodiac() (machine_arch_type == MACH_TYPE_ZODIAC) -#else -# define machine_is_zodiac() (0) -#endif - -#ifdef CONFIG_ARCH_ARMMODUL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMMODUL -# endif -# define machine_is_armmodul() (machine_arch_type == MACH_TYPE_ARMMODUL) -#else -# define machine_is_armmodul() (0) -#endif - -#ifdef CONFIG_SA1100_KETOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KETOP -# endif -# define machine_is_ketop() (machine_arch_type == MACH_TYPE_KETOP) -#else -# define machine_is_ketop() (0) -#endif - -#ifdef CONFIG_ARCH_AV7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AV7200 -# endif -# define machine_is_av7200() (machine_arch_type == MACH_TYPE_AV7200) -#else -# define machine_is_av7200() (0) -#endif - -#ifdef CONFIG_ARCH_ARCH_TI925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCH_TI925 -# endif -# define machine_is_arch_ti925() (machine_arch_type == MACH_TYPE_ARCH_TI925) -#else -# define machine_is_arch_ti925() (0) -#endif - -#ifdef CONFIG_ARCH_ACQ200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ200 -# endif -# define machine_is_acq200() (machine_arch_type == MACH_TYPE_ACQ200) -#else -# define machine_is_acq200() (0) -#endif - -#ifdef CONFIG_SA1100_PT_DAFIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT_DAFIT -# endif -# define machine_is_pt_dafit() (machine_arch_type == MACH_TYPE_PT_DAFIT) -#else -# define machine_is_pt_dafit() (0) -#endif - -#ifdef CONFIG_ARCH_IHBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IHBA -# endif -# define machine_is_ihba() (machine_arch_type == MACH_TYPE_IHBA) -#else -# define machine_is_ihba() (0) -#endif - -#ifdef CONFIG_ARCH_QUINQUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUINQUE -# endif -# define machine_is_quinque() (machine_arch_type == MACH_TYPE_QUINQUE) -#else -# define machine_is_quinque() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRAONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRAONE -# endif -# define machine_is_nimbraone() (machine_arch_type == MACH_TYPE_NIMBRAONE) -#else -# define machine_is_nimbraone() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRA29X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA29X -# endif -# define machine_is_nimbra29x() (machine_arch_type == MACH_TYPE_NIMBRA29X) -#else -# define machine_is_nimbra29x() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRA210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA210 -# endif -# define machine_is_nimbra210() (machine_arch_type == MACH_TYPE_NIMBRA210) -#else -# define machine_is_nimbra210() (0) -#endif - -#ifdef CONFIG_ARCH_HHP_D95XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHP_D95XX -# endif -# define machine_is_hhp_d95xx() (machine_arch_type == MACH_TYPE_HHP_D95XX) -#else -# define machine_is_hhp_d95xx() (0) -#endif - -#ifdef CONFIG_ARCH_LABARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LABARM -# endif -# define machine_is_labarm() (machine_arch_type == MACH_TYPE_LABARM) -#else -# define machine_is_labarm() (0) -#endif - -#ifdef CONFIG_ARCH_M825XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M825XX -# endif -# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) -#else -# define machine_is_m825xx() (0) -#endif - -#ifdef CONFIG_SA1100_M7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M7100 -# endif -# define machine_is_m7100() (machine_arch_type == MACH_TYPE_M7100) -#else -# define machine_is_m7100() (0) -#endif - -#ifdef CONFIG_ARCH_NIPC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIPC2 -# endif -# define machine_is_nipc2() (machine_arch_type == MACH_TYPE_NIPC2) -#else -# define machine_is_nipc2() (0) -#endif - -#ifdef CONFIG_ARCH_FU7202 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FU7202 -# endif -# define machine_is_fu7202() (machine_arch_type == MACH_TYPE_FU7202) -#else -# define machine_is_fu7202() (0) -#endif - -#ifdef CONFIG_ARCH_ADSAGX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSAGX -# endif -# define machine_is_adsagx() (machine_arch_type == MACH_TYPE_ADSAGX) -#else -# define machine_is_adsagx() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_POOH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_POOH -# endif -# define machine_is_pxa_pooh() (machine_arch_type == MACH_TYPE_PXA_POOH) -#else -# define machine_is_pxa_pooh() (0) -#endif - -#ifdef CONFIG_ARCH_BANDON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BANDON -# endif -# define machine_is_bandon() (machine_arch_type == MACH_TYPE_BANDON) -#else -# define machine_is_bandon() (0) -#endif - -#ifdef CONFIG_ARCH_PCM7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM7210 -# endif -# define machine_is_pcm7210() (machine_arch_type == MACH_TYPE_PCM7210) -#else -# define machine_is_pcm7210() (0) -#endif - -#ifdef CONFIG_ARCH_NMS9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NMS9200 -# endif -# define machine_is_nms9200() (machine_arch_type == MACH_TYPE_NMS9200) -#else -# define machine_is_nms9200() (0) -#endif - -#ifdef CONFIG_ARCH_LOGODL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGODL -# endif -# define machine_is_logodl() (machine_arch_type == MACH_TYPE_LOGODL) -#else -# define machine_is_logodl() (0) -#endif - -#ifdef CONFIG_SA1100_M7140 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M7140 -# endif -# define machine_is_m7140() (machine_arch_type == MACH_TYPE_M7140) -#else -# define machine_is_m7140() (0) -#endif - -#ifdef CONFIG_ARCH_KOREBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOREBOT -# endif -# define machine_is_korebot() (machine_arch_type == MACH_TYPE_KOREBOT) -#else -# define machine_is_korebot() (0) -#endif - -#ifdef CONFIG_ARCH_IQ31244 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ31244 -# endif -# define machine_is_iq31244() (machine_arch_type == MACH_TYPE_IQ31244) -#else -# define machine_is_iq31244() (0) -#endif - -#ifdef CONFIG_SA1100_KOAN393 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOAN393 -# endif -# define machine_is_koan393() (machine_arch_type == MACH_TYPE_KOAN393) -#else -# define machine_is_koan393() (0) -#endif - -#ifdef CONFIG_ARCH_INHANDFTIP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDFTIP3 -# endif -# define machine_is_inhandftip3() (machine_arch_type == MACH_TYPE_INHANDFTIP3) -#else -# define machine_is_inhandftip3() (0) -#endif - -#ifdef CONFIG_ARCH_GONZO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GONZO -# endif -# define machine_is_gonzo() (machine_arch_type == MACH_TYPE_GONZO) -#else -# define machine_is_gonzo() (0) -#endif - -#ifdef CONFIG_ARCH_BAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BAST -# endif -# define machine_is_bast() (machine_arch_type == MACH_TYPE_BAST) -#else -# define machine_is_bast() (0) -#endif - -#ifdef CONFIG_ARCH_SCANPASS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCANPASS -# endif -# define machine_is_scanpass() (machine_arch_type == MACH_TYPE_SCANPASS) -#else -# define machine_is_scanpass() (0) -#endif - -#ifdef CONFIG_ARCH_EP7312_POOH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP7312_POOH -# endif -# define machine_is_ep7312_pooh() (machine_arch_type == MACH_TYPE_EP7312_POOH) -#else -# define machine_is_ep7312_pooh() (0) -#endif - -#ifdef CONFIG_ARCH_TA7S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7S -# endif -# define machine_is_ta7s() (machine_arch_type == MACH_TYPE_TA7S) -#else -# define machine_is_ta7s() (0) -#endif - -#ifdef CONFIG_ARCH_TA7V -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7V -# endif -# define machine_is_ta7v() (machine_arch_type == MACH_TYPE_TA7V) -#else -# define machine_is_ta7v() (0) -#endif - -#ifdef CONFIG_SA1100_ICARUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICARUS -# endif -# define machine_is_icarus() (machine_arch_type == MACH_TYPE_ICARUS) -#else -# define machine_is_icarus() (0) -#endif - -#ifdef CONFIG_ARCH_H1900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H1900 -# endif -# define machine_is_h1900() (machine_arch_type == MACH_TYPE_H1900) -#else -# define machine_is_h1900() (0) -#endif - -#ifdef CONFIG_SA1100_GEMINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMINI -# endif -# define machine_is_gemini() (machine_arch_type == MACH_TYPE_GEMINI) -#else -# define machine_is_gemini() (0) -#endif - -#ifdef CONFIG_ARCH_AXIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXIM -# endif -# define machine_is_axim() (machine_arch_type == MACH_TYPE_AXIM) -#else -# define machine_is_axim() (0) -#endif - -#ifdef CONFIG_ARCH_AUDIOTRON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUDIOTRON -# endif -# define machine_is_audiotron() (machine_arch_type == MACH_TYPE_AUDIOTRON) -#else -# define machine_is_audiotron() (0) -#endif - -#ifdef CONFIG_ARCH_H2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H2200 -# endif -# define machine_is_h2200() (machine_arch_type == MACH_TYPE_H2200) -#else -# define machine_is_h2200() (0) -#endif - -#ifdef CONFIG_ARCH_LOOX600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX600 -# endif -# define machine_is_loox600() (machine_arch_type == MACH_TYPE_LOOX600) -#else -# define machine_is_loox600() (0) -#endif - -#ifdef CONFIG_ARCH_NIOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIOP -# endif -# define machine_is_niop() (machine_arch_type == MACH_TYPE_NIOP) -#else -# define machine_is_niop() (0) -#endif - -#ifdef CONFIG_ARCH_DM310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM310 -# endif -# define machine_is_dm310() (machine_arch_type == MACH_TYPE_DM310) -#else -# define machine_is_dm310() (0) -#endif - -#ifdef CONFIG_ARCH_SEEDPXA_C2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEEDPXA_C2 -# endif -# define machine_is_seedpxa_c2() (machine_arch_type == MACH_TYPE_SEEDPXA_C2) -#else -# define machine_is_seedpxa_c2() (0) -#endif - -#ifdef CONFIG_ARCH_IXP4XX_MGUARD_PCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP4XX_MGUARD_PCI -# endif -# define machine_is_ixp4xx_mguardpci() (machine_arch_type == MACH_TYPE_IXP4XX_MGUARD_PCI) -#else -# define machine_is_ixp4xx_mguardpci() (0) -#endif - -#ifdef CONFIG_ARCH_H1940 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H1940 -# endif -# define machine_is_h1940() (machine_arch_type == MACH_TYPE_H1940) -#else -# define machine_is_h1940() (0) -#endif - -#ifdef CONFIG_ARCH_SCORPIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCORPIO -# endif -# define machine_is_scorpio() (machine_arch_type == MACH_TYPE_SCORPIO) -#else -# define machine_is_scorpio() (0) -#endif - -#ifdef CONFIG_ARCH_VIVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIVA -# endif -# define machine_is_viva() (machine_arch_type == MACH_TYPE_VIVA) -#else -# define machine_is_viva() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_XCARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_XCARD -# endif -# define machine_is_pxa_xcard() (machine_arch_type == MACH_TYPE_PXA_XCARD) -#else -# define machine_is_pxa_xcard() (0) -#endif - -#ifdef CONFIG_ARCH_CSB335 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB335 -# endif -# define machine_is_csb335() (machine_arch_type == MACH_TYPE_CSB335) -#else -# define machine_is_csb335() (0) -#endif - -#ifdef CONFIG_ARCH_IXRD425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXRD425 -# endif -# define machine_is_ixrd425() (machine_arch_type == MACH_TYPE_IXRD425) -#else -# define machine_is_ixrd425() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80315 -# endif -# define machine_is_iq80315() (machine_arch_type == MACH_TYPE_IQ80315) -#else -# define machine_is_iq80315() (0) -#endif - -#ifdef CONFIG_ARCH_NMP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NMP7312 -# endif -# define machine_is_nmp7312() (machine_arch_type == MACH_TYPE_NMP7312) -#else -# define machine_is_nmp7312() (0) -#endif - -#ifdef CONFIG_ARCH_CX861XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX861XX -# endif -# define machine_is_cx861xx() (machine_arch_type == MACH_TYPE_CX861XX) -#else -# define machine_is_cx861xx() (0) -#endif - -#ifdef CONFIG_ARCH_ENP2611 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENP2611 -# endif -# define machine_is_enp2611() (machine_arch_type == MACH_TYPE_ENP2611) -#else -# define machine_is_enp2611() (0) -#endif - -#ifdef CONFIG_SA1100_XDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDA -# endif -# define machine_is_xda() (machine_arch_type == MACH_TYPE_XDA) -#else -# define machine_is_xda() (0) -#endif - -#ifdef CONFIG_ARCH_CSIR_IMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSIR_IMS -# endif -# define machine_is_csir_ims() (machine_arch_type == MACH_TYPE_CSIR_IMS) -#else -# define machine_is_csir_ims() (0) -#endif - -#ifdef CONFIG_ARCH_IXP421_DNAEETH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP421_DNAEETH -# endif -# define machine_is_ixp421_dnaeeth() (machine_arch_type == MACH_TYPE_IXP421_DNAEETH) -#else -# define machine_is_ixp421_dnaeeth() (0) -#endif - -#ifdef CONFIG_ARCH_POCKETSERV9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POCKETSERV9200 -# endif -# define machine_is_pocketserv9200() (machine_arch_type == MACH_TYPE_POCKETSERV9200) -#else -# define machine_is_pocketserv9200() (0) -#endif - -#ifdef CONFIG_ARCH_TOTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOTO -# endif -# define machine_is_toto() (machine_arch_type == MACH_TYPE_TOTO) -#else -# define machine_is_toto() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2440 -# endif -# define machine_is_s3c2440() (machine_arch_type == MACH_TYPE_S3C2440) -#else -# define machine_is_s3c2440() (0) -#endif - -#ifdef CONFIG_ARCH_KS8695P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695P -# endif -# define machine_is_ks8695p() (machine_arch_type == MACH_TYPE_KS8695P) -#else -# define machine_is_ks8695p() (0) -#endif - -#ifdef CONFIG_ARCH_SE4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE4000 -# endif -# define machine_is_se4000() (machine_arch_type == MACH_TYPE_SE4000) -#else -# define machine_is_se4000() (0) -#endif - -#ifdef CONFIG_ARCH_QUADRICEPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUADRICEPS -# endif -# define machine_is_quadriceps() (machine_arch_type == MACH_TYPE_QUADRICEPS) -#else -# define machine_is_quadriceps() (0) -#endif - -#ifdef CONFIG_ARCH_BRONCO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRONCO -# endif -# define machine_is_bronco() (machine_arch_type == MACH_TYPE_BRONCO) -#else -# define machine_is_bronco() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_WIRELESS_TAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_WIRELESS_TAB -# endif -# define machine_is_esl_wireless_tab() (machine_arch_type == MACH_TYPE_ESL_WIRELESS_TAB) -#else -# define machine_is_esl_wireless_tab() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SOFCOMP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SOFCOMP -# endif -# define machine_is_esl_sofcomp() (machine_arch_type == MACH_TYPE_ESL_SOFCOMP) -#else -# define machine_is_esl_sofcomp() (0) -#endif - -#ifdef CONFIG_ARCH_S5C7375 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5C7375 -# endif -# define machine_is_s5c7375() (machine_arch_type == MACH_TYPE_S5C7375) -#else -# define machine_is_s5c7375() (0) -#endif - -#ifdef CONFIG_ARCH_SPEARHEAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEARHEAD -# endif -# define machine_is_spearhead() (machine_arch_type == MACH_TYPE_SPEARHEAD) -#else -# define machine_is_spearhead() (0) -#endif - -#ifdef CONFIG_ARCH_PANTERA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PANTERA -# endif -# define machine_is_pantera() (machine_arch_type == MACH_TYPE_PANTERA) -#else -# define machine_is_pantera() (0) -#endif - -#ifdef CONFIG_ARCH_PRAYOGLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRAYOGLITE -# endif -# define machine_is_prayoglite() (machine_arch_type == MACH_TYPE_PRAYOGLITE) -#else -# define machine_is_prayoglite() (0) -#endif - -#ifdef CONFIG_ARCH_GUMSTIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUMSTIX -# endif -# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIX) -#else -# define machine_is_gumstix() (0) -#endif - -#ifdef CONFIG_ARCH_RCUBE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RCUBE -# endif -# define machine_is_rcube() (machine_arch_type == MACH_TYPE_RCUBE) -#else -# define machine_is_rcube() (0) -#endif - -#ifdef CONFIG_ARCH_REA_OLV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA_OLV -# endif -# define machine_is_rea_olv() (machine_arch_type == MACH_TYPE_REA_OLV) -#else -# define machine_is_rea_olv() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_IPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IPHONE -# endif -# define machine_is_pxa_iphone() (machine_arch_type == MACH_TYPE_PXA_IPHONE) -#else -# define machine_is_pxa_iphone() (0) -#endif - -#ifdef CONFIG_ARCH_S3C3410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C3410 -# endif -# define machine_is_s3c3410() (machine_arch_type == MACH_TYPE_S3C3410) -#else -# define machine_is_s3c3410() (0) -#endif - -#ifdef CONFIG_ARCH_ESPD_4510B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESPD_4510B -# endif -# define machine_is_espd_4510b() (machine_arch_type == MACH_TYPE_ESPD_4510B) -#else -# define machine_is_espd_4510b() (0) -#endif - -#ifdef CONFIG_ARCH_MP1X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP1X -# endif -# define machine_is_mp1x() (machine_arch_type == MACH_TYPE_MP1X) -#else -# define machine_is_mp1x() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200TB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200TB -# endif -# define machine_is_at91rm9200tb() (machine_arch_type == MACH_TYPE_AT91RM9200TB) -#else -# define machine_is_at91rm9200tb() (0) -#endif - -#ifdef CONFIG_ARCH_ADSVGX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSVGX -# endif -# define machine_is_adsvgx() (machine_arch_type == MACH_TYPE_ADSVGX) -#else -# define machine_is_adsvgx() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H2 -# endif -# define machine_is_omap_h2() (machine_arch_type == MACH_TYPE_OMAP_H2) -#else -# define machine_is_omap_h2() (0) -#endif - -#ifdef CONFIG_ARCH_PELEE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELEE -# endif -# define machine_is_pelee() (machine_arch_type == MACH_TYPE_PELEE) -#else -# define machine_is_pelee() (0) -#endif - -#ifdef CONFIG_MACH_E740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E740 -# endif -# define machine_is_e740() (machine_arch_type == MACH_TYPE_E740) -#else -# define machine_is_e740() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80331 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80331 -# endif -# define machine_is_iq80331() (machine_arch_type == MACH_TYPE_IQ80331) -#else -# define machine_is_iq80331() (0) -#endif - -#ifdef CONFIG_ARCH_VERSATILE_PB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERSATILE_PB -# endif -# define machine_is_versatile_pb() (machine_arch_type == MACH_TYPE_VERSATILE_PB) -#else -# define machine_is_versatile_pb() (0) -#endif - -#ifdef CONFIG_MACH_KEV7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KEV7A400 -# endif -# define machine_is_kev7a400() (machine_arch_type == MACH_TYPE_KEV7A400) -#else -# define machine_is_kev7a400() (0) -#endif - -#ifdef CONFIG_MACH_LPD7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD7A400 -# endif -# define machine_is_lpd7a400() (machine_arch_type == MACH_TYPE_LPD7A400) -#else -# define machine_is_lpd7a400() (0) -#endif - -#ifdef CONFIG_MACH_LPD7A404 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD7A404 -# endif -# define machine_is_lpd7a404() (machine_arch_type == MACH_TYPE_LPD7A404) -#else -# define machine_is_lpd7a404() (0) -#endif - -#ifdef CONFIG_ARCH_FUJITSU_CAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_CAMELOT -# endif -# define machine_is_fujitsu_camelot() (machine_arch_type == MACH_TYPE_FUJITSU_CAMELOT) -#else -# define machine_is_fujitsu_camelot() (0) -#endif - -#ifdef CONFIG_ARCH_JANUS2M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JANUS2M -# endif -# define machine_is_janus2m() (machine_arch_type == MACH_TYPE_JANUS2M) -#else -# define machine_is_janus2m() (0) -#endif - -#ifdef CONFIG_MACH_EMBTF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMBTF -# endif -# define machine_is_embtf() (machine_arch_type == MACH_TYPE_EMBTF) -#else -# define machine_is_embtf() (0) -#endif - -#ifdef CONFIG_MACH_HPM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPM -# endif -# define machine_is_hpm() (machine_arch_type == MACH_TYPE_HPM) -#else -# define machine_is_hpm() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2410TK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410TK -# endif -# define machine_is_smdk2410tk() (machine_arch_type == MACH_TYPE_SMDK2410TK) -#else -# define machine_is_smdk2410tk() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2410AJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410AJ -# endif -# define machine_is_smdk2410aj() (machine_arch_type == MACH_TYPE_SMDK2410AJ) -#else -# define machine_is_smdk2410aj() (0) -#endif - -#ifdef CONFIG_MACH_STREETRACER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STREETRACER -# endif -# define machine_is_streetracer() (machine_arch_type == MACH_TYPE_STREETRACER) -#else -# define machine_is_streetracer() (0) -#endif - -#ifdef CONFIG_MACH_EFRAME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EFRAME -# endif -# define machine_is_eframe() (machine_arch_type == MACH_TYPE_EFRAME) -#else -# define machine_is_eframe() (0) -#endif - -#ifdef CONFIG_MACH_CSB337 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB337 -# endif -# define machine_is_csb337() (machine_arch_type == MACH_TYPE_CSB337) -#else -# define machine_is_csb337() (0) -#endif - -#ifdef CONFIG_MACH_PXA_LARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_LARK -# endif -# define machine_is_pxa_lark() (machine_arch_type == MACH_TYPE_PXA_LARK) -#else -# define machine_is_pxa_lark() (0) -#endif - -#ifdef CONFIG_MACH_PNP2110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNP2110 -# endif -# define machine_is_pxa_pnp2110() (machine_arch_type == MACH_TYPE_PNP2110) -#else -# define machine_is_pxa_pnp2110() (0) -#endif - -#ifdef CONFIG_MACH_TCC72X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCC72X -# endif -# define machine_is_tcc72x() (machine_arch_type == MACH_TYPE_TCC72X) -#else -# define machine_is_tcc72x() (0) -#endif - -#ifdef CONFIG_MACH_ALTAIR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALTAIR -# endif -# define machine_is_altair() (machine_arch_type == MACH_TYPE_ALTAIR) -#else -# define machine_is_altair() (0) -#endif - -#ifdef CONFIG_MACH_KC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KC3 -# endif -# define machine_is_kc3() (machine_arch_type == MACH_TYPE_KC3) -#else -# define machine_is_kc3() (0) -#endif - -#ifdef CONFIG_MACH_SINTEFTD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SINTEFTD -# endif -# define machine_is_sinteftd() (machine_arch_type == MACH_TYPE_SINTEFTD) -#else -# define machine_is_sinteftd() (0) -#endif - -#ifdef CONFIG_MACH_MAINSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAINSTONE -# endif -# define machine_is_mainstone() (machine_arch_type == MACH_TYPE_MAINSTONE) -#else -# define machine_is_mainstone() (0) -#endif - -#ifdef CONFIG_MACH_ADAY4X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADAY4X -# endif -# define machine_is_aday4x() (machine_arch_type == MACH_TYPE_ADAY4X) -#else -# define machine_is_aday4x() (0) -#endif - -#ifdef CONFIG_MACH_LITE300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LITE300 -# endif -# define machine_is_lite300() (machine_arch_type == MACH_TYPE_LITE300) -#else -# define machine_is_lite300() (0) -#endif - -#ifdef CONFIG_MACH_S5C7376 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5C7376 -# endif -# define machine_is_s5c7376() (machine_arch_type == MACH_TYPE_S5C7376) -#else -# define machine_is_s5c7376() (0) -#endif - -#ifdef CONFIG_MACH_MT02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT02 -# endif -# define machine_is_mt02() (machine_arch_type == MACH_TYPE_MT02) -#else -# define machine_is_mt02() (0) -#endif - -#ifdef CONFIG_MACH_MPORT3S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT3S -# endif -# define machine_is_mport3s() (machine_arch_type == MACH_TYPE_MPORT3S) -#else -# define machine_is_mport3s() (0) -#endif - -#ifdef CONFIG_MACH_RA_ALPHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RA_ALPHA -# endif -# define machine_is_ra_alpha() (machine_arch_type == MACH_TYPE_RA_ALPHA) -#else -# define machine_is_ra_alpha() (0) -#endif - -#ifdef CONFIG_MACH_XCEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XCEP -# endif -# define machine_is_xcep() (machine_arch_type == MACH_TYPE_XCEP) -#else -# define machine_is_xcep() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_VULCAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_VULCAN -# endif -# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) -#else -# define machine_is_arcom_vulcan() (0) -#endif - -#ifdef CONFIG_MACH_STARGATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGATE -# endif -# define machine_is_stargate() (machine_arch_type == MACH_TYPE_STARGATE) -#else -# define machine_is_stargate() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLOJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLOJ -# endif -# define machine_is_armadilloj() (machine_arch_type == MACH_TYPE_ARMADILLOJ) -#else -# define machine_is_armadilloj() (0) -#endif - -#ifdef CONFIG_MACH_ELROY_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELROY_JACK -# endif -# define machine_is_elroy_jack() (machine_arch_type == MACH_TYPE_ELROY_JACK) -#else -# define machine_is_elroy_jack() (0) -#endif - -#ifdef CONFIG_MACH_BACKEND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BACKEND -# endif -# define machine_is_backend() (machine_arch_type == MACH_TYPE_BACKEND) -#else -# define machine_is_backend() (0) -#endif - -#ifdef CONFIG_MACH_S5LINBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5LINBOX -# endif -# define machine_is_s5linbox() (machine_arch_type == MACH_TYPE_S5LINBOX) -#else -# define machine_is_s5linbox() (0) -#endif - -#ifdef CONFIG_MACH_NOMADIK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOMADIK -# endif -# define machine_is_nomadik() (machine_arch_type == MACH_TYPE_NOMADIK) -#else -# define machine_is_nomadik() (0) -#endif - -#ifdef CONFIG_MACH_IA_CPU_9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_CPU_9200 -# endif -# define machine_is_ia_cpu_9200() (machine_arch_type == MACH_TYPE_IA_CPU_9200) -#else -# define machine_is_ia_cpu_9200() (0) -#endif - -#ifdef CONFIG_MACH_AT91_BJA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91_BJA1 -# endif -# define machine_is_at91_bja1() (machine_arch_type == MACH_TYPE_AT91_BJA1) -#else -# define machine_is_at91_bja1() (0) -#endif - -#ifdef CONFIG_MACH_CORGI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORGI -# endif -# define machine_is_corgi() (machine_arch_type == MACH_TYPE_CORGI) -#else -# define machine_is_corgi() (0) -#endif - -#ifdef CONFIG_MACH_POODLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POODLE -# endif -# define machine_is_poodle() (machine_arch_type == MACH_TYPE_POODLE) -#else -# define machine_is_poodle() (0) -#endif - -#ifdef CONFIG_MACH_TEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEN -# endif -# define machine_is_ten() (machine_arch_type == MACH_TYPE_TEN) -#else -# define machine_is_ten() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP5P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP5P -# endif -# define machine_is_roverp5p() (machine_arch_type == MACH_TYPE_ROVERP5P) -#else -# define machine_is_roverp5p() (0) -#endif - -#ifdef CONFIG_MACH_SC2700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC2700 -# endif -# define machine_is_sc2700() (machine_arch_type == MACH_TYPE_SC2700) -#else -# define machine_is_sc2700() (0) -#endif - -#ifdef CONFIG_MACH_EX_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EX_EAGLE -# endif -# define machine_is_ex_eagle() (machine_arch_type == MACH_TYPE_EX_EAGLE) -#else -# define machine_is_ex_eagle() (0) -#endif - -#ifdef CONFIG_MACH_NX_PXA12 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PXA12 -# endif -# define machine_is_nx_pxa12() (machine_arch_type == MACH_TYPE_NX_PXA12) -#else -# define machine_is_nx_pxa12() (0) -#endif - -#ifdef CONFIG_MACH_NX_PXA5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PXA5 -# endif -# define machine_is_nx_pxa5() (machine_arch_type == MACH_TYPE_NX_PXA5) -#else -# define machine_is_nx_pxa5() (0) -#endif - -#ifdef CONFIG_MACH_BLACKBOARD2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKBOARD2 -# endif -# define machine_is_blackboard2() (machine_arch_type == MACH_TYPE_BLACKBOARD2) -#else -# define machine_is_blackboard2() (0) -#endif - -#ifdef CONFIG_MACH_I819 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I819 -# endif -# define machine_is_i819() (machine_arch_type == MACH_TYPE_I819) -#else -# define machine_is_i819() (0) -#endif - -#ifdef CONFIG_MACH_IXMB995E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXMB995E -# endif -# define machine_is_ixmb995e() (machine_arch_type == MACH_TYPE_IXMB995E) -#else -# define machine_is_ixmb995e() (0) -#endif - -#ifdef CONFIG_MACH_SKYRIDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYRIDER -# endif -# define machine_is_skyrider() (machine_arch_type == MACH_TYPE_SKYRIDER) -#else -# define machine_is_skyrider() (0) -#endif - -#ifdef CONFIG_MACH_SKYHAWK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYHAWK -# endif -# define machine_is_skyhawk() (machine_arch_type == MACH_TYPE_SKYHAWK) -#else -# define machine_is_skyhawk() (0) -#endif - -#ifdef CONFIG_MACH_ENTERPRISE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENTERPRISE -# endif -# define machine_is_enterprise() (machine_arch_type == MACH_TYPE_ENTERPRISE) -#else -# define machine_is_enterprise() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410 -# endif -# define machine_is_dep2410() (machine_arch_type == MACH_TYPE_DEP2410) -#else -# define machine_is_dep2410() (0) -#endif - -#ifdef CONFIG_MACH_ARMCORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMCORE -# endif -# define machine_is_armcore() (machine_arch_type == MACH_TYPE_ARMCORE) -#else -# define machine_is_armcore() (0) -#endif - -#ifdef CONFIG_MACH_HOBBIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOBBIT -# endif -# define machine_is_hobbit() (machine_arch_type == MACH_TYPE_HOBBIT) -#else -# define machine_is_hobbit() (0) -#endif - -#ifdef CONFIG_MACH_H7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7210 -# endif -# define machine_is_h7210() (machine_arch_type == MACH_TYPE_H7210) -#else -# define machine_is_h7210() (0) -#endif - -#ifdef CONFIG_MACH_PXA_NETDCU5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_NETDCU5 -# endif -# define machine_is_pxa_netdcu5() (machine_arch_type == MACH_TYPE_PXA_NETDCU5) -#else -# define machine_is_pxa_netdcu5() (0) -#endif - -#ifdef CONFIG_MACH_ACC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACC -# endif -# define machine_is_acc() (machine_arch_type == MACH_TYPE_ACC) -#else -# define machine_is_acc() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA -# endif -# define machine_is_esl_sarva() (machine_arch_type == MACH_TYPE_ESL_SARVA) -#else -# define machine_is_esl_sarva() (0) -#endif - -#ifdef CONFIG_MACH_XM250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XM250 -# endif -# define machine_is_xm250() (machine_arch_type == MACH_TYPE_XM250) -#else -# define machine_is_xm250() (0) -#endif - -#ifdef CONFIG_MACH_T6TC1XB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T6TC1XB -# endif -# define machine_is_t6tc1xb() (machine_arch_type == MACH_TYPE_T6TC1XB) -#else -# define machine_is_t6tc1xb() (0) -#endif - -#ifdef CONFIG_MACH_ESS710 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESS710 -# endif -# define machine_is_ess710() (machine_arch_type == MACH_TYPE_ESS710) -#else -# define machine_is_ess710() (0) -#endif - -#ifdef CONFIG_MACH_MX31ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31ADS -# endif -# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) -#else -# define machine_is_mx31ads() (0) -#endif - -#ifdef CONFIG_MACH_HIMALAYA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIMALAYA -# endif -# define machine_is_himalaya() (machine_arch_type == MACH_TYPE_HIMALAYA) -#else -# define machine_is_himalaya() (0) -#endif - -#ifdef CONFIG_MACH_BOLFENK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BOLFENK -# endif -# define machine_is_bolfenk() (machine_arch_type == MACH_TYPE_BOLFENK) -#else -# define machine_is_bolfenk() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200KR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200KR -# endif -# define machine_is_at91rm9200kr() (machine_arch_type == MACH_TYPE_AT91RM9200KR) -#else -# define machine_is_at91rm9200kr() (0) -#endif - -#ifdef CONFIG_MACH_EDB9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9312 -# endif -# define machine_is_edb9312() (machine_arch_type == MACH_TYPE_EDB9312) -#else -# define machine_is_edb9312() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_GENERIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_GENERIC -# endif -# define machine_is_omap_generic() (machine_arch_type == MACH_TYPE_OMAP_GENERIC) -#else -# define machine_is_omap_generic() (0) -#endif - -#ifdef CONFIG_MACH_AXIMX3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXIMX3 -# endif -# define machine_is_aximx3() (machine_arch_type == MACH_TYPE_AXIMX3) -#else -# define machine_is_aximx3() (0) -#endif - -#ifdef CONFIG_MACH_EB67XDIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB67XDIP -# endif -# define machine_is_eb67xdip() (machine_arch_type == MACH_TYPE_EB67XDIP) -#else -# define machine_is_eb67xdip() (0) -#endif - -#ifdef CONFIG_MACH_WEBTXS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBTXS -# endif -# define machine_is_webtxs() (machine_arch_type == MACH_TYPE_WEBTXS) -#else -# define machine_is_webtxs() (0) -#endif - -#ifdef CONFIG_MACH_HAWK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAWK -# endif -# define machine_is_hawk() (machine_arch_type == MACH_TYPE_HAWK) -#else -# define machine_is_hawk() (0) -#endif - -#ifdef CONFIG_MACH_CCAT91SBC001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCAT91SBC001 -# endif -# define machine_is_ccat91sbc001() (machine_arch_type == MACH_TYPE_CCAT91SBC001) -#else -# define machine_is_ccat91sbc001() (0) -#endif - -#ifdef CONFIG_MACH_EXPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPRESSO -# endif -# define machine_is_expresso() (machine_arch_type == MACH_TYPE_EXPRESSO) -#else -# define machine_is_expresso() (0) -#endif - -#ifdef CONFIG_MACH_H4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4000 -# endif -# define machine_is_h4000() (machine_arch_type == MACH_TYPE_H4000) -#else -# define machine_is_h4000() (0) -#endif - -#ifdef CONFIG_MACH_DINO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DINO -# endif -# define machine_is_dino() (machine_arch_type == MACH_TYPE_DINO) -#else -# define machine_is_dino() (0) -#endif - -#ifdef CONFIG_MACH_ML675K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML675K -# endif -# define machine_is_ml675k() (machine_arch_type == MACH_TYPE_ML675K) -#else -# define machine_is_ml675k() (0) -#endif - -#ifdef CONFIG_MACH_EDB9301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9301 -# endif -# define machine_is_edb9301() (machine_arch_type == MACH_TYPE_EDB9301) -#else -# define machine_is_edb9301() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315 -# endif -# define machine_is_edb9315() (machine_arch_type == MACH_TYPE_EDB9315) -#else -# define machine_is_edb9315() (0) -#endif - -#ifdef CONFIG_MACH_RECIVA_TT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RECIVA_TT -# endif -# define machine_is_reciva_tt() (machine_arch_type == MACH_TYPE_RECIVA_TT) -#else -# define machine_is_reciva_tt() (0) -#endif - -#ifdef CONFIG_MACH_CSTCB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSTCB01 -# endif -# define machine_is_cstcb01() (machine_arch_type == MACH_TYPE_CSTCB01) -#else -# define machine_is_cstcb01() (0) -#endif - -#ifdef CONFIG_MACH_CSTCB1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSTCB1 -# endif -# define machine_is_cstcb1() (machine_arch_type == MACH_TYPE_CSTCB1) -#else -# define machine_is_cstcb1() (0) -#endif - -#ifdef CONFIG_MACH_SHADWELL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHADWELL -# endif -# define machine_is_shadwell() (machine_arch_type == MACH_TYPE_SHADWELL) -#else -# define machine_is_shadwell() (0) -#endif - -#ifdef CONFIG_MACH_GOEPEL263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOEPEL263 -# endif -# define machine_is_goepel263() (machine_arch_type == MACH_TYPE_GOEPEL263) -#else -# define machine_is_goepel263() (0) -#endif - -#ifdef CONFIG_MACH_ACQ100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ100 -# endif -# define machine_is_acq100() (machine_arch_type == MACH_TYPE_ACQ100) -#else -# define machine_is_acq100() (0) -#endif - -#ifdef CONFIG_MACH_MX1FS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1FS2 -# endif -# define machine_is_mx1fs2() (machine_arch_type == MACH_TYPE_MX1FS2) -#else -# define machine_is_mx1fs2() (0) -#endif - -#ifdef CONFIG_MACH_HIPTOP_G1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIPTOP_G1 -# endif -# define machine_is_hiptop_g1() (machine_arch_type == MACH_TYPE_HIPTOP_G1) -#else -# define machine_is_hiptop_g1() (0) -#endif - -#ifdef CONFIG_MACH_SPARKY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPARKY -# endif -# define machine_is_sparky() (machine_arch_type == MACH_TYPE_SPARKY) -#else -# define machine_is_sparky() (0) -#endif - -#ifdef CONFIG_MACH_NS9750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NS9750 -# endif -# define machine_is_ns9750() (machine_arch_type == MACH_TYPE_NS9750) -#else -# define machine_is_ns9750() (0) -#endif - -#ifdef CONFIG_MACH_PHOENIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHOENIX -# endif -# define machine_is_phoenix() (machine_arch_type == MACH_TYPE_PHOENIX) -#else -# define machine_is_phoenix() (0) -#endif - -#ifdef CONFIG_MACH_VR1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VR1000 -# endif -# define machine_is_vr1000() (machine_arch_type == MACH_TYPE_VR1000) -#else -# define machine_is_vr1000() (0) -#endif - -#ifdef CONFIG_MACH_DEISTERPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTERPXA -# endif -# define machine_is_deisterpxa() (machine_arch_type == MACH_TYPE_DEISTERPXA) -#else -# define machine_is_deisterpxa() (0) -#endif - -#ifdef CONFIG_MACH_BCM1160 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM1160 -# endif -# define machine_is_bcm1160() (machine_arch_type == MACH_TYPE_BCM1160) -#else -# define machine_is_bcm1160() (0) -#endif - -#ifdef CONFIG_MACH_PCM022 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM022 -# endif -# define machine_is_pcm022() (machine_arch_type == MACH_TYPE_PCM022) -#else -# define machine_is_pcm022() (0) -#endif - -#ifdef CONFIG_MACH_ADSGCX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSGCX -# endif -# define machine_is_adsgcx() (machine_arch_type == MACH_TYPE_ADSGCX) -#else -# define machine_is_adsgcx() (0) -#endif - -#ifdef CONFIG_MACH_DREADNAUGHT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DREADNAUGHT -# endif -# define machine_is_dreadnaught() (machine_arch_type == MACH_TYPE_DREADNAUGHT) -#else -# define machine_is_dreadnaught() (0) -#endif - -#ifdef CONFIG_MACH_DM320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM320 -# endif -# define machine_is_dm320() (machine_arch_type == MACH_TYPE_DM320) -#else -# define machine_is_dm320() (0) -#endif - -#ifdef CONFIG_MACH_MARKOV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARKOV -# endif -# define machine_is_markov() (machine_arch_type == MACH_TYPE_MARKOV) -#else -# define machine_is_markov() (0) -#endif - -#ifdef CONFIG_MACH_COS7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COS7A400 -# endif -# define machine_is_cos7a400() (machine_arch_type == MACH_TYPE_COS7A400) -#else -# define machine_is_cos7a400() (0) -#endif - -#ifdef CONFIG_MACH_MILANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MILANO -# endif -# define machine_is_milano() (machine_arch_type == MACH_TYPE_MILANO) -#else -# define machine_is_milano() (0) -#endif - -#ifdef CONFIG_MACH_UE9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UE9328 -# endif -# define machine_is_ue9328() (machine_arch_type == MACH_TYPE_UE9328) -#else -# define machine_is_ue9328() (0) -#endif - -#ifdef CONFIG_MACH_UEX255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UEX255 -# endif -# define machine_is_uex255() (machine_arch_type == MACH_TYPE_UEX255) -#else -# define machine_is_uex255() (0) -#endif - -#ifdef CONFIG_MACH_UE2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UE2410 -# endif -# define machine_is_ue2410() (machine_arch_type == MACH_TYPE_UE2410) -#else -# define machine_is_ue2410() (0) -#endif - -#ifdef CONFIG_MACH_A620 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A620 -# endif -# define machine_is_a620() (machine_arch_type == MACH_TYPE_A620) -#else -# define machine_is_a620() (0) -#endif - -#ifdef CONFIG_MACH_OCELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCELOT -# endif -# define machine_is_ocelot() (machine_arch_type == MACH_TYPE_OCELOT) -#else -# define machine_is_ocelot() (0) -#endif - -#ifdef CONFIG_MACH_CHEETAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHEETAH -# endif -# define machine_is_cheetah() (machine_arch_type == MACH_TYPE_CHEETAH) -#else -# define machine_is_cheetah() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PERSEUS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PERSEUS2 -# endif -# define machine_is_omap_perseus2() (machine_arch_type == MACH_TYPE_OMAP_PERSEUS2) -#else -# define machine_is_omap_perseus2() (0) -#endif - -#ifdef CONFIG_MACH_ZVUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZVUE -# endif -# define machine_is_zvue() (machine_arch_type == MACH_TYPE_ZVUE) -#else -# define machine_is_zvue() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP1 -# endif -# define machine_is_roverp1() (machine_arch_type == MACH_TYPE_ROVERP1) -#else -# define machine_is_roverp1() (0) -#endif - -#ifdef CONFIG_MACH_ASIDIAL2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASIDIAL2 -# endif -# define machine_is_asidial2() (machine_arch_type == MACH_TYPE_ASIDIAL2) -#else -# define machine_is_asidial2() (0) -#endif - -#ifdef CONFIG_MACH_S3C24A0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C24A0 -# endif -# define machine_is_s3c24a0() (machine_arch_type == MACH_TYPE_S3C24A0) -#else -# define machine_is_s3c24a0() (0) -#endif - -#ifdef CONFIG_MACH_E800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E800 -# endif -# define machine_is_e800() (machine_arch_type == MACH_TYPE_E800) -#else -# define machine_is_e800() (0) -#endif - -#ifdef CONFIG_MACH_E750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E750 -# endif -# define machine_is_e750() (machine_arch_type == MACH_TYPE_E750) -#else -# define machine_is_e750() (0) -#endif - -#ifdef CONFIG_MACH_S3C5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C5500 -# endif -# define machine_is_s3c5500() (machine_arch_type == MACH_TYPE_S3C5500) -#else -# define machine_is_s3c5500() (0) -#endif - -#ifdef CONFIG_MACH_SMDK5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK5500 -# endif -# define machine_is_smdk5500() (machine_arch_type == MACH_TYPE_SMDK5500) -#else -# define machine_is_smdk5500() (0) -#endif - -#ifdef CONFIG_MACH_SIGNALSYNC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIGNALSYNC -# endif -# define machine_is_signalsync() (machine_arch_type == MACH_TYPE_SIGNALSYNC) -#else -# define machine_is_signalsync() (0) -#endif - -#ifdef CONFIG_MACH_NBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NBC -# endif -# define machine_is_nbc() (machine_arch_type == MACH_TYPE_NBC) -#else -# define machine_is_nbc() (0) -#endif - -#ifdef CONFIG_MACH_KODIAK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KODIAK -# endif -# define machine_is_kodiak() (machine_arch_type == MACH_TYPE_KODIAK) -#else -# define machine_is_kodiak() (0) -#endif - -#ifdef CONFIG_MACH_NETBOOKPRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETBOOKPRO -# endif -# define machine_is_netbookpro() (machine_arch_type == MACH_TYPE_NETBOOKPRO) -#else -# define machine_is_netbookpro() (0) -#endif - -#ifdef CONFIG_MACH_HW90200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90200 -# endif -# define machine_is_hw90200() (machine_arch_type == MACH_TYPE_HW90200) -#else -# define machine_is_hw90200() (0) -#endif - -#ifdef CONFIG_MACH_CONDOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONDOR -# endif -# define machine_is_condor() (machine_arch_type == MACH_TYPE_CONDOR) -#else -# define machine_is_condor() (0) -#endif - -#ifdef CONFIG_MACH_CUP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CUP -# endif -# define machine_is_cup() (machine_arch_type == MACH_TYPE_CUP) -#else -# define machine_is_cup() (0) -#endif - -#ifdef CONFIG_MACH_KITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KITE -# endif -# define machine_is_kite() (machine_arch_type == MACH_TYPE_KITE) -#else -# define machine_is_kite() (0) -#endif - -#ifdef CONFIG_MACH_SCB9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCB9328 -# endif -# define machine_is_scb9328() (machine_arch_type == MACH_TYPE_SCB9328) -#else -# define machine_is_scb9328() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H3 -# endif -# define machine_is_omap_h3() (machine_arch_type == MACH_TYPE_OMAP_H3) -#else -# define machine_is_omap_h3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H4 -# endif -# define machine_is_omap_h4() (machine_arch_type == MACH_TYPE_OMAP_H4) -#else -# define machine_is_omap_h4() (0) -#endif - -#ifdef CONFIG_MACH_N10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N10 -# endif -# define machine_is_n10() (machine_arch_type == MACH_TYPE_N10) -#else -# define machine_is_n10() (0) -#endif - -#ifdef CONFIG_MACH_MONTAJADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MONTAJADE -# endif -# define machine_is_montejade() (machine_arch_type == MACH_TYPE_MONTAJADE) -#else -# define machine_is_montejade() (0) -#endif - -#ifdef CONFIG_MACH_SG560 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560 -# endif -# define machine_is_sg560() (machine_arch_type == MACH_TYPE_SG560) -#else -# define machine_is_sg560() (0) -#endif - -#ifdef CONFIG_MACH_DP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP1000 -# endif -# define machine_is_dp1000() (machine_arch_type == MACH_TYPE_DP1000) -#else -# define machine_is_dp1000() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_OSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_OSK -# endif -# define machine_is_omap_osk() (machine_arch_type == MACH_TYPE_OMAP_OSK) -#else -# define machine_is_omap_osk() (0) -#endif - -#ifdef CONFIG_MACH_RG100V3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RG100V3 -# endif -# define machine_is_rg100v3() (machine_arch_type == MACH_TYPE_RG100V3) -#else -# define machine_is_rg100v3() (0) -#endif - -#ifdef CONFIG_MACH_MX2ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2ADS -# endif -# define machine_is_mx2ads() (machine_arch_type == MACH_TYPE_MX2ADS) -#else -# define machine_is_mx2ads() (0) -#endif - -#ifdef CONFIG_MACH_PXA_KILO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_KILO -# endif -# define machine_is_pxa_kilo() (machine_arch_type == MACH_TYPE_PXA_KILO) -#else -# define machine_is_pxa_kilo() (0) -#endif - -#ifdef CONFIG_MACH_IXP4XX_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP4XX_EAGLE -# endif -# define machine_is_ixp4xx_eagle() (machine_arch_type == MACH_TYPE_IXP4XX_EAGLE) -#else -# define machine_is_ixp4xx_eagle() (0) -#endif - -#ifdef CONFIG_MACH_TOSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOSA -# endif -# define machine_is_tosa() (machine_arch_type == MACH_TYPE_TOSA) -#else -# define machine_is_tosa() (0) -#endif - -#ifdef CONFIG_MACH_MB2520F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB2520F -# endif -# define machine_is_mb2520f() (machine_arch_type == MACH_TYPE_MB2520F) -#else -# define machine_is_mb2520f() (0) -#endif - -#ifdef CONFIG_MACH_EMC1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMC1000 -# endif -# define machine_is_emc1000() (machine_arch_type == MACH_TYPE_EMC1000) -#else -# define machine_is_emc1000() (0) -#endif - -#ifdef CONFIG_MACH_TIDSC25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIDSC25 -# endif -# define machine_is_tidsc25() (machine_arch_type == MACH_TYPE_TIDSC25) -#else -# define machine_is_tidsc25() (0) -#endif - -#ifdef CONFIG_MACH_AKCPMXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKCPMXL -# endif -# define machine_is_akcpmxl() (machine_arch_type == MACH_TYPE_AKCPMXL) -#else -# define machine_is_akcpmxl() (0) -#endif - -#ifdef CONFIG_MACH_AV3XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AV3XX -# endif -# define machine_is_av3xx() (machine_arch_type == MACH_TYPE_AV3XX) -#else -# define machine_is_av3xx() (0) -#endif - -#ifdef CONFIG_MACH_AVILA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVILA -# endif -# define machine_is_avila() (machine_arch_type == MACH_TYPE_AVILA) -#else -# define machine_is_avila() (0) -#endif - -#ifdef CONFIG_MACH_PXA_MPM10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_MPM10 -# endif -# define machine_is_pxa_mpm10() (machine_arch_type == MACH_TYPE_PXA_MPM10) -#else -# define machine_is_pxa_mpm10() (0) -#endif - -#ifdef CONFIG_MACH_PXA_KYANITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_KYANITE -# endif -# define machine_is_pxa_kyanite() (machine_arch_type == MACH_TYPE_PXA_KYANITE) -#else -# define machine_is_pxa_kyanite() (0) -#endif - -#ifdef CONFIG_MACH_SGOLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGOLD -# endif -# define machine_is_sgold() (machine_arch_type == MACH_TYPE_SGOLD) -#else -# define machine_is_sgold() (0) -#endif - -#ifdef CONFIG_MACH_OSCAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSCAR -# endif -# define machine_is_oscar() (machine_arch_type == MACH_TYPE_OSCAR) -#else -# define machine_is_oscar() (0) -#endif - -#ifdef CONFIG_MACH_EPXA4USB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPXA4USB2 -# endif -# define machine_is_epxa4usb2() (machine_arch_type == MACH_TYPE_EPXA4USB2) -#else -# define machine_is_epxa4usb2() (0) -#endif - -#ifdef CONFIG_MACH_XSENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSENGINE -# endif -# define machine_is_xsengine() (machine_arch_type == MACH_TYPE_XSENGINE) -#else -# define machine_is_xsengine() (0) -#endif - -#ifdef CONFIG_MACH_IP600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP600 -# endif -# define machine_is_ip600() (machine_arch_type == MACH_TYPE_IP600) -#else -# define machine_is_ip600() (0) -#endif - -#ifdef CONFIG_MACH_MCAN2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCAN2 -# endif -# define machine_is_mcan2() (machine_arch_type == MACH_TYPE_MCAN2) -#else -# define machine_is_mcan2() (0) -#endif - -#ifdef CONFIG_MACH_DDI_BLUERIDGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DDI_BLUERIDGE -# endif -# define machine_is_ddi_blueridge() (machine_arch_type == MACH_TYPE_DDI_BLUERIDGE) -#else -# define machine_is_ddi_blueridge() (0) -#endif - -#ifdef CONFIG_MACH_SKYMINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYMINDER -# endif -# define machine_is_skyminder() (machine_arch_type == MACH_TYPE_SKYMINDER) -#else -# define machine_is_skyminder() (0) -#endif - -#ifdef CONFIG_MACH_LPD79520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79520 -# endif -# define machine_is_lpd79520() (machine_arch_type == MACH_TYPE_LPD79520) -#else -# define machine_is_lpd79520() (0) -#endif - -#ifdef CONFIG_MACH_EDB9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9302 -# endif -# define machine_is_edb9302() (machine_arch_type == MACH_TYPE_EDB9302) -#else -# define machine_is_edb9302() (0) -#endif - -#ifdef CONFIG_MACH_HW90340 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90340 -# endif -# define machine_is_hw90340() (machine_arch_type == MACH_TYPE_HW90340) -#else -# define machine_is_hw90340() (0) -#endif - -#ifdef CONFIG_MACH_CIP_BOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CIP_BOX -# endif -# define machine_is_cip_box() (machine_arch_type == MACH_TYPE_CIP_BOX) -#else -# define machine_is_cip_box() (0) -#endif - -#ifdef CONFIG_MACH_IVPN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IVPN -# endif -# define machine_is_ivpn() (machine_arch_type == MACH_TYPE_IVPN) -#else -# define machine_is_ivpn() (0) -#endif - -#ifdef CONFIG_MACH_RSOC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSOC2 -# endif -# define machine_is_rsoc2() (machine_arch_type == MACH_TYPE_RSOC2) -#else -# define machine_is_rsoc2() (0) -#endif - -#ifdef CONFIG_MACH_HUSKY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUSKY -# endif -# define machine_is_husky() (machine_arch_type == MACH_TYPE_HUSKY) -#else -# define machine_is_husky() (0) -#endif - -#ifdef CONFIG_MACH_BOXER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BOXER -# endif -# define machine_is_boxer() (machine_arch_type == MACH_TYPE_BOXER) -#else -# define machine_is_boxer() (0) -#endif - -#ifdef CONFIG_MACH_SHEPHERD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEPHERD -# endif -# define machine_is_shepherd() (machine_arch_type == MACH_TYPE_SHEPHERD) -#else -# define machine_is_shepherd() (0) -#endif - -#ifdef CONFIG_MACH_AML42800AA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML42800AA -# endif -# define machine_is_aml42800aa() (machine_arch_type == MACH_TYPE_AML42800AA) -#else -# define machine_is_aml42800aa() (0) -#endif - -#ifdef CONFIG_MACH_LPC2294 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC2294 -# endif -# define machine_is_lpc2294() (machine_arch_type == MACH_TYPE_LPC2294) -#else -# define machine_is_lpc2294() (0) -#endif - -#ifdef CONFIG_MACH_SWITCHGRASS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWITCHGRASS -# endif -# define machine_is_switchgrass() (machine_arch_type == MACH_TYPE_SWITCHGRASS) -#else -# define machine_is_switchgrass() (0) -#endif - -#ifdef CONFIG_MACH_ENS_CMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENS_CMU -# endif -# define machine_is_ens_cmu() (machine_arch_type == MACH_TYPE_ENS_CMU) -#else -# define machine_is_ens_cmu() (0) -#endif - -#ifdef CONFIG_MACH_MM6_SDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MM6_SDB -# endif -# define machine_is_mm6_sdb() (machine_arch_type == MACH_TYPE_MM6_SDB) -#else -# define machine_is_mm6_sdb() (0) -#endif - -#ifdef CONFIG_MACH_SATURN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SATURN -# endif -# define machine_is_saturn() (machine_arch_type == MACH_TYPE_SATURN) -#else -# define machine_is_saturn() (0) -#endif - -#ifdef CONFIG_MACH_I30030EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I30030EVB -# endif -# define machine_is_i30030evb() (machine_arch_type == MACH_TYPE_I30030EVB) -#else -# define machine_is_i30030evb() (0) -#endif - -#ifdef CONFIG_MACH_MXC27530EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27530EVB -# endif -# define machine_is_mxc27530evb() (machine_arch_type == MACH_TYPE_MXC27530EVB) -#else -# define machine_is_mxc27530evb() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2800 -# endif -# define machine_is_smdk2800() (machine_arch_type == MACH_TYPE_SMDK2800) -#else -# define machine_is_smdk2800() (0) -#endif - -#ifdef CONFIG_MACH_MTWILSON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTWILSON -# endif -# define machine_is_mtwilson() (machine_arch_type == MACH_TYPE_MTWILSON) -#else -# define machine_is_mtwilson() (0) -#endif - -#ifdef CONFIG_MACH_ZITI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZITI -# endif -# define machine_is_ziti() (machine_arch_type == MACH_TYPE_ZITI) -#else -# define machine_is_ziti() (0) -#endif - -#ifdef CONFIG_MACH_GRANDFATHER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRANDFATHER -# endif -# define machine_is_grandfather() (machine_arch_type == MACH_TYPE_GRANDFATHER) -#else -# define machine_is_grandfather() (0) -#endif - -#ifdef CONFIG_MACH_TENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TENGINE -# endif -# define machine_is_tengine() (machine_arch_type == MACH_TYPE_TENGINE) -#else -# define machine_is_tengine() (0) -#endif - -#ifdef CONFIG_MACH_S3C2460 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2460 -# endif -# define machine_is_s3c2460() (machine_arch_type == MACH_TYPE_S3C2460) -#else -# define machine_is_s3c2460() (0) -#endif - -#ifdef CONFIG_MACH_PDM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDM -# endif -# define machine_is_pdm() (machine_arch_type == MACH_TYPE_PDM) -#else -# define machine_is_pdm() (0) -#endif - -#ifdef CONFIG_MACH_H4700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4700 -# endif -# define machine_is_h4700() (machine_arch_type == MACH_TYPE_H4700) -#else -# define machine_is_h4700() (0) -#endif - -#ifdef CONFIG_MACH_H6300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6300 -# endif -# define machine_is_h6300() (machine_arch_type == MACH_TYPE_H6300) -#else -# define machine_is_h6300() (0) -#endif - -#ifdef CONFIG_MACH_RZ1700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RZ1700 -# endif -# define machine_is_rz1700() (machine_arch_type == MACH_TYPE_RZ1700) -#else -# define machine_is_rz1700() (0) -#endif - -#ifdef CONFIG_MACH_A716 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A716 -# endif -# define machine_is_a716() (machine_arch_type == MACH_TYPE_A716) -#else -# define machine_is_a716() (0) -#endif - -#ifdef CONFIG_MACH_ESTK2440A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESTK2440A -# endif -# define machine_is_estk2440a() (machine_arch_type == MACH_TYPE_ESTK2440A) -#else -# define machine_is_estk2440a() (0) -#endif - -#ifdef CONFIG_MACH_ATWIXP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATWIXP425 -# endif -# define machine_is_atwixp425() (machine_arch_type == MACH_TYPE_ATWIXP425) -#else -# define machine_is_atwixp425() (0) -#endif - -#ifdef CONFIG_MACH_CSB336 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB336 -# endif -# define machine_is_csb336() (machine_arch_type == MACH_TYPE_CSB336) -#else -# define machine_is_csb336() (0) -#endif - -#ifdef CONFIG_MACH_RIRM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIRM2 -# endif -# define machine_is_rirm2() (machine_arch_type == MACH_TYPE_RIRM2) -#else -# define machine_is_rirm2() (0) -#endif - -#ifdef CONFIG_MACH_CX23518 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX23518 -# endif -# define machine_is_cx23518() (machine_arch_type == MACH_TYPE_CX23518) -#else -# define machine_is_cx23518() (0) -#endif - -#ifdef CONFIG_MACH_CX2351X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX2351X -# endif -# define machine_is_cx2351x() (machine_arch_type == MACH_TYPE_CX2351X) -#else -# define machine_is_cx2351x() (0) -#endif - -#ifdef CONFIG_MACH_COMPUTIME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPUTIME -# endif -# define machine_is_computime() (machine_arch_type == MACH_TYPE_COMPUTIME) -#else -# define machine_is_computime() (0) -#endif - -#ifdef CONFIG_MACH_IZARUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IZARUS -# endif -# define machine_is_izarus() (machine_arch_type == MACH_TYPE_IZARUS) -#else -# define machine_is_izarus() (0) -#endif - -#ifdef CONFIG_MACH_RTS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RTS -# endif -# define machine_is_pxa_rts() (machine_arch_type == MACH_TYPE_RTS) -#else -# define machine_is_pxa_rts() (0) -#endif - -#ifdef CONFIG_MACH_SE5100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE5100 -# endif -# define machine_is_se5100() (machine_arch_type == MACH_TYPE_SE5100) -#else -# define machine_is_se5100() (0) -#endif - -#ifdef CONFIG_MACH_S3C2510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2510 -# endif -# define machine_is_s3c2510() (machine_arch_type == MACH_TYPE_S3C2510) -#else -# define machine_is_s3c2510() (0) -#endif - -#ifdef CONFIG_MACH_CSB437TL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB437TL -# endif -# define machine_is_csb437tl() (machine_arch_type == MACH_TYPE_CSB437TL) -#else -# define machine_is_csb437tl() (0) -#endif - -#ifdef CONFIG_MACH_SLAUSON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLAUSON -# endif -# define machine_is_slauson() (machine_arch_type == MACH_TYPE_SLAUSON) -#else -# define machine_is_slauson() (0) -#endif - -#ifdef CONFIG_MACH_PEARLRIVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEARLRIVER -# endif -# define machine_is_pearlriver() (machine_arch_type == MACH_TYPE_PEARLRIVER) -#else -# define machine_is_pearlriver() (0) -#endif - -#ifdef CONFIG_MACH_TDC_P210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TDC_P210 -# endif -# define machine_is_tdc_p210() (machine_arch_type == MACH_TYPE_TDC_P210) -#else -# define machine_is_tdc_p210() (0) -#endif - -#ifdef CONFIG_MACH_SG580 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG580 -# endif -# define machine_is_sg580() (machine_arch_type == MACH_TYPE_SG580) -#else -# define machine_is_sg580() (0) -#endif - -#ifdef CONFIG_MACH_WRSBCARM7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRSBCARM7 -# endif -# define machine_is_wrsbcarm7() (machine_arch_type == MACH_TYPE_WRSBCARM7) -#else -# define machine_is_wrsbcarm7() (0) -#endif - -#ifdef CONFIG_MACH_IPD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPD -# endif -# define machine_is_ipd() (machine_arch_type == MACH_TYPE_IPD) -#else -# define machine_is_ipd() (0) -#endif - -#ifdef CONFIG_MACH_PXA_DNP2110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_DNP2110 -# endif -# define machine_is_pxa_dnp2110() (machine_arch_type == MACH_TYPE_PXA_DNP2110) -#else -# define machine_is_pxa_dnp2110() (0) -#endif - -#ifdef CONFIG_MACH_XAENIAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XAENIAX -# endif -# define machine_is_xaeniax() (machine_arch_type == MACH_TYPE_XAENIAX) -#else -# define machine_is_xaeniax() (0) -#endif - -#ifdef CONFIG_MACH_SOMN4250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOMN4250 -# endif -# define machine_is_somn4250() (machine_arch_type == MACH_TYPE_SOMN4250) -#else -# define machine_is_somn4250() (0) -#endif - -#ifdef CONFIG_MACH_PLEB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLEB2 -# endif -# define machine_is_pleb2() (machine_arch_type == MACH_TYPE_PLEB2) -#else -# define machine_is_pleb2() (0) -#endif - -#ifdef CONFIG_MACH_CORNWALLIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORNWALLIS -# endif -# define machine_is_cornwallis() (machine_arch_type == MACH_TYPE_CORNWALLIS) -#else -# define machine_is_cornwallis() (0) -#endif - -#ifdef CONFIG_MACH_GURNEY_DRV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GURNEY_DRV -# endif -# define machine_is_gurney_drv() (machine_arch_type == MACH_TYPE_GURNEY_DRV) -#else -# define machine_is_gurney_drv() (0) -#endif - -#ifdef CONFIG_MACH_CHAFFEE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHAFFEE -# endif -# define machine_is_chaffee() (machine_arch_type == MACH_TYPE_CHAFFEE) -#else -# define machine_is_chaffee() (0) -#endif - -#ifdef CONFIG_MACH_RMS101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMS101 -# endif -# define machine_is_rms101() (machine_arch_type == MACH_TYPE_RMS101) -#else -# define machine_is_rms101() (0) -#endif - -#ifdef CONFIG_MACH_RX3715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RX3715 -# endif -# define machine_is_rx3715() (machine_arch_type == MACH_TYPE_RX3715) -#else -# define machine_is_rx3715() (0) -#endif - -#ifdef CONFIG_MACH_SWIFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWIFT -# endif -# define machine_is_swift() (machine_arch_type == MACH_TYPE_SWIFT) -#else -# define machine_is_swift() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP7 -# endif -# define machine_is_roverp7() (machine_arch_type == MACH_TYPE_ROVERP7) -#else -# define machine_is_roverp7() (0) -#endif - -#ifdef CONFIG_MACH_PR818S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PR818S -# endif -# define machine_is_pr818s() (machine_arch_type == MACH_TYPE_PR818S) -#else -# define machine_is_pr818s() (0) -#endif - -#ifdef CONFIG_MACH_TRXPRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRXPRO -# endif -# define machine_is_trxpro() (machine_arch_type == MACH_TYPE_TRXPRO) -#else -# define machine_is_trxpro() (0) -#endif - -#ifdef CONFIG_MACH_NSLU2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSLU2 -# endif -# define machine_is_nslu2() (machine_arch_type == MACH_TYPE_NSLU2) -#else -# define machine_is_nslu2() (0) -#endif - -#ifdef CONFIG_MACH_E400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E400 -# endif -# define machine_is_e400() (machine_arch_type == MACH_TYPE_E400) -#else -# define machine_is_e400() (0) -#endif - -#ifdef CONFIG_MACH_TRAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRAB -# endif -# define machine_is_trab() (machine_arch_type == MACH_TYPE_TRAB) -#else -# define machine_is_trab() (0) -#endif - -#ifdef CONFIG_MACH_CMC_PU2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMC_PU2 -# endif -# define machine_is_cmc_pu2() (machine_arch_type == MACH_TYPE_CMC_PU2) -#else -# define machine_is_cmc_pu2() (0) -#endif - -#ifdef CONFIG_MACH_FULCRUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FULCRUM -# endif -# define machine_is_fulcrum() (machine_arch_type == MACH_TYPE_FULCRUM) -#else -# define machine_is_fulcrum() (0) -#endif - -#ifdef CONFIG_MACH_NETGATE42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETGATE42X -# endif -# define machine_is_netgate42x() (machine_arch_type == MACH_TYPE_NETGATE42X) -#else -# define machine_is_netgate42x() (0) -#endif - -#ifdef CONFIG_MACH_STR710 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STR710 -# endif -# define machine_is_str710() (machine_arch_type == MACH_TYPE_STR710) -#else -# define machine_is_str710() (0) -#endif - -#ifdef CONFIG_MACH_IXDPG425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDPG425 -# endif -# define machine_is_ixdpg425() (machine_arch_type == MACH_TYPE_IXDPG425) -#else -# define machine_is_ixdpg425() (0) -#endif - -#ifdef CONFIG_MACH_TOMTOMGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOMTOMGO -# endif -# define machine_is_tomtomgo() (machine_arch_type == MACH_TYPE_TOMTOMGO) -#else -# define machine_is_tomtomgo() (0) -#endif - -#ifdef CONFIG_MACH_VERSATILE_AB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERSATILE_AB -# endif -# define machine_is_versatile_ab() (machine_arch_type == MACH_TYPE_VERSATILE_AB) -#else -# define machine_is_versatile_ab() (0) -#endif - -#ifdef CONFIG_MACH_EDB9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9307 -# endif -# define machine_is_edb9307() (machine_arch_type == MACH_TYPE_EDB9307) -#else -# define machine_is_edb9307() (0) -#endif - -#ifdef CONFIG_MACH_SG565 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG565 -# endif -# define machine_is_sg565() (machine_arch_type == MACH_TYPE_SG565) -#else -# define machine_is_sg565() (0) -#endif - -#ifdef CONFIG_MACH_LPD79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79524 -# endif -# define machine_is_lpd79524() (machine_arch_type == MACH_TYPE_LPD79524) -#else -# define machine_is_lpd79524() (0) -#endif - -#ifdef CONFIG_MACH_LPD79525 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79525 -# endif -# define machine_is_lpd79525() (machine_arch_type == MACH_TYPE_LPD79525) -#else -# define machine_is_lpd79525() (0) -#endif - -#ifdef CONFIG_MACH_RMS100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMS100 -# endif -# define machine_is_rms100() (machine_arch_type == MACH_TYPE_RMS100) -#else -# define machine_is_rms100() (0) -#endif - -#ifdef CONFIG_MACH_KB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9200 -# endif -# define machine_is_kb9200() (machine_arch_type == MACH_TYPE_KB9200) -#else -# define machine_is_kb9200() (0) -#endif - -#ifdef CONFIG_MACH_SX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SX1 -# endif -# define machine_is_sx1() (machine_arch_type == MACH_TYPE_SX1) -#else -# define machine_is_sx1() (0) -#endif - -#ifdef CONFIG_MACH_HMS39C7092 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMS39C7092 -# endif -# define machine_is_hms39c7092() (machine_arch_type == MACH_TYPE_HMS39C7092) -#else -# define machine_is_hms39c7092() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO -# endif -# define machine_is_armadillo() (machine_arch_type == MACH_TYPE_ARMADILLO) -#else -# define machine_is_armadillo() (0) -#endif - -#ifdef CONFIG_MACH_IPCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPCU -# endif -# define machine_is_ipcu() (machine_arch_type == MACH_TYPE_IPCU) -#else -# define machine_is_ipcu() (0) -#endif - -#ifdef CONFIG_MACH_LOOX720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX720 -# endif -# define machine_is_loox720() (machine_arch_type == MACH_TYPE_LOOX720) -#else -# define machine_is_loox720() (0) -#endif - -#ifdef CONFIG_MACH_IXDP465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP465 -# endif -# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465) -#else -# define machine_is_ixdp465() (0) -#endif - -#ifdef CONFIG_MACH_IXDP2351 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2351 -# endif -# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351) -#else -# define machine_is_ixdp2351() (0) -#endif - -#ifdef CONFIG_MACH_ADSVIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSVIX -# endif -# define machine_is_adsvix() (machine_arch_type == MACH_TYPE_ADSVIX) -#else -# define machine_is_adsvix() (0) -#endif - -#ifdef CONFIG_MACH_DM270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM270 -# endif -# define machine_is_dm270() (machine_arch_type == MACH_TYPE_DM270) -#else -# define machine_is_dm270() (0) -#endif - -#ifdef CONFIG_MACH_SOCLTPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOCLTPLUS -# endif -# define machine_is_socltplus() (machine_arch_type == MACH_TYPE_SOCLTPLUS) -#else -# define machine_is_socltplus() (0) -#endif - -#ifdef CONFIG_MACH_ECIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECIA -# endif -# define machine_is_ecia() (machine_arch_type == MACH_TYPE_ECIA) -#else -# define machine_is_ecia() (0) -#endif - -#ifdef CONFIG_MACH_CM4008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM4008 -# endif -# define machine_is_cm4008() (machine_arch_type == MACH_TYPE_CM4008) -#else -# define machine_is_cm4008() (0) -#endif - -#ifdef CONFIG_MACH_P2001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P2001 -# endif -# define machine_is_p2001() (machine_arch_type == MACH_TYPE_P2001) -#else -# define machine_is_p2001() (0) -#endif - -#ifdef CONFIG_MACH_TWISTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TWISTER -# endif -# define machine_is_twister() (machine_arch_type == MACH_TYPE_TWISTER) -#else -# define machine_is_twister() (0) -#endif - -#ifdef CONFIG_MACH_MUDSHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MUDSHARK -# endif -# define machine_is_mudshark() (machine_arch_type == MACH_TYPE_MUDSHARK) -#else -# define machine_is_mudshark() (0) -#endif - -#ifdef CONFIG_MACH_HB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HB2 -# endif -# define machine_is_hb2() (machine_arch_type == MACH_TYPE_HB2) -#else -# define machine_is_hb2() (0) -#endif - -#ifdef CONFIG_MACH_IQ80332 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80332 -# endif -# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332) -#else -# define machine_is_iq80332() (0) -#endif - -#ifdef CONFIG_MACH_SENDT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SENDT -# endif -# define machine_is_sendt() (machine_arch_type == MACH_TYPE_SENDT) -#else -# define machine_is_sendt() (0) -#endif - -#ifdef CONFIG_MACH_MX2JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2JAZZ -# endif -# define machine_is_mx2jazz() (machine_arch_type == MACH_TYPE_MX2JAZZ) -#else -# define machine_is_mx2jazz() (0) -#endif - -#ifdef CONFIG_MACH_MULTIIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIIO -# endif -# define machine_is_multiio() (machine_arch_type == MACH_TYPE_MULTIIO) -#else -# define machine_is_multiio() (0) -#endif - -#ifdef CONFIG_MACH_HRDISPLAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HRDISPLAY -# endif -# define machine_is_hrdisplay() (machine_arch_type == MACH_TYPE_HRDISPLAY) -#else -# define machine_is_hrdisplay() (0) -#endif - -#ifdef CONFIG_MACH_MXC27530ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27530ADS -# endif -# define machine_is_mxc27530ads() (machine_arch_type == MACH_TYPE_MXC27530ADS) -#else -# define machine_is_mxc27530ads() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS3 -# endif -# define machine_is_trizeps3() (machine_arch_type == MACH_TYPE_TRIZEPS3) -#else -# define machine_is_trizeps3() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZA -# endif -# define machine_is_zefeerdza() (machine_arch_type == MACH_TYPE_ZEFEERDZA) -#else -# define machine_is_zefeerdza() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZB -# endif -# define machine_is_zefeerdzb() (machine_arch_type == MACH_TYPE_ZEFEERDZB) -#else -# define machine_is_zefeerdzb() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZG -# endif -# define machine_is_zefeerdzg() (machine_arch_type == MACH_TYPE_ZEFEERDZG) -#else -# define machine_is_zefeerdzg() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZN -# endif -# define machine_is_zefeerdzn() (machine_arch_type == MACH_TYPE_ZEFEERDZN) -#else -# define machine_is_zefeerdzn() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZQ -# endif -# define machine_is_zefeerdzq() (machine_arch_type == MACH_TYPE_ZEFEERDZQ) -#else -# define machine_is_zefeerdzq() (0) -#endif - -#ifdef CONFIG_MACH_GTWX5715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTWX5715 -# endif -# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715) -#else -# define machine_is_gtwx5715() (0) -#endif - -#ifdef CONFIG_MACH_ASTRO_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASTRO_JACK -# endif -# define machine_is_astro_jack() (machine_arch_type == MACH_TYPE_ASTRO_JACK) -#else -# define machine_is_astro_jack() (0) -#endif - -#ifdef CONFIG_MACH_TIP03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIP03 -# endif -# define machine_is_tip03() (machine_arch_type == MACH_TYPE_TIP03) -#else -# define machine_is_tip03() (0) -#endif - -#ifdef CONFIG_MACH_A9200EC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9200EC -# endif -# define machine_is_a9200ec() (machine_arch_type == MACH_TYPE_A9200EC) -#else -# define machine_is_a9200ec() (0) -#endif - -#ifdef CONFIG_MACH_PNX0105 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX0105 -# endif -# define machine_is_pnx0105() (machine_arch_type == MACH_TYPE_PNX0105) -#else -# define machine_is_pnx0105() (0) -#endif - -#ifdef CONFIG_MACH_ADCPOECPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADCPOECPU -# endif -# define machine_is_adcpoecpu() (machine_arch_type == MACH_TYPE_ADCPOECPU) -#else -# define machine_is_adcpoecpu() (0) -#endif - -#ifdef CONFIG_MACH_CSB637 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB637 -# endif -# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637) -#else -# define machine_is_csb637() (0) -#endif - -#ifdef CONFIG_MACH_MB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9200 -# endif -# define machine_is_mb9200() (machine_arch_type == MACH_TYPE_MB9200) -#else -# define machine_is_mb9200() (0) -#endif - -#ifdef CONFIG_MACH_KULUN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KULUN -# endif -# define machine_is_kulun() (machine_arch_type == MACH_TYPE_KULUN) -#else -# define machine_is_kulun() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER -# endif -# define machine_is_snapper() (machine_arch_type == MACH_TYPE_SNAPPER) -#else -# define machine_is_snapper() (0) -#endif - -#ifdef CONFIG_MACH_OPTIMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPTIMA -# endif -# define machine_is_optima() (machine_arch_type == MACH_TYPE_OPTIMA) -#else -# define machine_is_optima() (0) -#endif - -#ifdef CONFIG_MACH_DLHSBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DLHSBC -# endif -# define machine_is_dlhsbc() (machine_arch_type == MACH_TYPE_DLHSBC) -#else -# define machine_is_dlhsbc() (0) -#endif - -#ifdef CONFIG_MACH_X30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X30 -# endif -# define machine_is_x30() (machine_arch_type == MACH_TYPE_X30) -#else -# define machine_is_x30() (0) -#endif - -#ifdef CONFIG_MACH_N30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N30 -# endif -# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30) -#else -# define machine_is_n30() (0) -#endif - -#ifdef CONFIG_MACH_MANGA_KS8695 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MANGA_KS8695 -# endif -# define machine_is_manga_ks8695() (machine_arch_type == MACH_TYPE_MANGA_KS8695) -#else -# define machine_is_manga_ks8695() (0) -#endif - -#ifdef CONFIG_MACH_AJAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AJAX -# endif -# define machine_is_ajax() (machine_arch_type == MACH_TYPE_AJAX) -#else -# define machine_is_ajax() (0) -#endif - -#ifdef CONFIG_MACH_NEC_MP900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEC_MP900 -# endif -# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900) -#else -# define machine_is_nec_mp900() (0) -#endif - -#ifdef CONFIG_MACH_VVTK1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVTK1000 -# endif -# define machine_is_vvtk1000() (machine_arch_type == MACH_TYPE_VVTK1000) -#else -# define machine_is_vvtk1000() (0) -#endif - -#ifdef CONFIG_MACH_KAFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KAFA -# endif -# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA) -#else -# define machine_is_kafa() (0) -#endif - -#ifdef CONFIG_MACH_VVTK3000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVTK3000 -# endif -# define machine_is_vvtk3000() (machine_arch_type == MACH_TYPE_VVTK3000) -#else -# define machine_is_vvtk3000() (0) -#endif - -#ifdef CONFIG_MACH_PIMX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIMX1 -# endif -# define machine_is_pimx1() (machine_arch_type == MACH_TYPE_PIMX1) -#else -# define machine_is_pimx1() (0) -#endif - -#ifdef CONFIG_MACH_OLLIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLLIE -# endif -# define machine_is_ollie() (machine_arch_type == MACH_TYPE_OLLIE) -#else -# define machine_is_ollie() (0) -#endif - -#ifdef CONFIG_MACH_SKYMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYMAX -# endif -# define machine_is_skymax() (machine_arch_type == MACH_TYPE_SKYMAX) -#else -# define machine_is_skymax() (0) -#endif - -#ifdef CONFIG_MACH_JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JAZZ -# endif -# define machine_is_jazz() (machine_arch_type == MACH_TYPE_JAZZ) -#else -# define machine_is_jazz() (0) -#endif - -#ifdef CONFIG_MACH_TEL_T3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEL_T3 -# endif -# define machine_is_tel_t3() (machine_arch_type == MACH_TYPE_TEL_T3) -#else -# define machine_is_tel_t3() (0) -#endif - -#ifdef CONFIG_MACH_AISINO_FCR255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AISINO_FCR255 -# endif -# define machine_is_aisino_fcr255() (machine_arch_type == MACH_TYPE_AISINO_FCR255) -#else -# define machine_is_aisino_fcr255() (0) -#endif - -#ifdef CONFIG_MACH_BTWEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTWEB -# endif -# define machine_is_btweb() (machine_arch_type == MACH_TYPE_BTWEB) -#else -# define machine_is_btweb() (0) -#endif - -#ifdef CONFIG_MACH_DBG_LH79520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DBG_LH79520 -# endif -# define machine_is_dbg_lh79520() (machine_arch_type == MACH_TYPE_DBG_LH79520) -#else -# define machine_is_dbg_lh79520() (0) -#endif - -#ifdef CONFIG_MACH_CM41XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM41XX -# endif -# define machine_is_cm41xx() (machine_arch_type == MACH_TYPE_CM41XX) -#else -# define machine_is_cm41xx() (0) -#endif - -#ifdef CONFIG_MACH_TS72XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS72XX -# endif -# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX) -#else -# define machine_is_ts72xx() (0) -#endif - -#ifdef CONFIG_MACH_NGGPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NGGPXA -# endif -# define machine_is_nggpxa() (machine_arch_type == MACH_TYPE_NGGPXA) -#else -# define machine_is_nggpxa() (0) -#endif - -#ifdef CONFIG_MACH_CSB535 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB535 -# endif -# define machine_is_csb535() (machine_arch_type == MACH_TYPE_CSB535) -#else -# define machine_is_csb535() (0) -#endif - -#ifdef CONFIG_MACH_CSB536 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB536 -# endif -# define machine_is_csb536() (machine_arch_type == MACH_TYPE_CSB536) -#else -# define machine_is_csb536() (0) -#endif - -#ifdef CONFIG_MACH_PXA_TRAKPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_TRAKPOD -# endif -# define machine_is_pxa_trakpod() (machine_arch_type == MACH_TYPE_PXA_TRAKPOD) -#else -# define machine_is_pxa_trakpod() (0) -#endif - -#ifdef CONFIG_MACH_PRAXIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRAXIS -# endif -# define machine_is_praxis() (machine_arch_type == MACH_TYPE_PRAXIS) -#else -# define machine_is_praxis() (0) -#endif - -#ifdef CONFIG_MACH_LH75411 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LH75411 -# endif -# define machine_is_lh75411() (machine_arch_type == MACH_TYPE_LH75411) -#else -# define machine_is_lh75411() (0) -#endif - -#ifdef CONFIG_MACH_OTOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTOM -# endif -# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM) -#else -# define machine_is_otom() (0) -#endif - -#ifdef CONFIG_MACH_NEXCODER_2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXCODER_2440 -# endif -# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440) -#else -# define machine_is_nexcoder_2440() (0) -#endif - -#ifdef CONFIG_MACH_LOOX410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX410 -# endif -# define machine_is_loox410() (machine_arch_type == MACH_TYPE_LOOX410) -#else -# define machine_is_loox410() (0) -#endif - -#ifdef CONFIG_MACH_WESTLAKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WESTLAKE -# endif -# define machine_is_westlake() (machine_arch_type == MACH_TYPE_WESTLAKE) -#else -# define machine_is_westlake() (0) -#endif - -#ifdef CONFIG_MACH_NSB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB -# endif -# define machine_is_nsb() (machine_arch_type == MACH_TYPE_NSB) -#else -# define machine_is_nsb() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_STN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_STN -# endif -# define machine_is_esl_sarva_stn() (machine_arch_type == MACH_TYPE_ESL_SARVA_STN) -#else -# define machine_is_esl_sarva_stn() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_TFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_TFT -# endif -# define machine_is_esl_sarva_tft() (machine_arch_type == MACH_TYPE_ESL_SARVA_TFT) -#else -# define machine_is_esl_sarva_tft() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_IAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_IAD -# endif -# define machine_is_esl_sarva_iad() (machine_arch_type == MACH_TYPE_ESL_SARVA_IAD) -#else -# define machine_is_esl_sarva_iad() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_ACC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_ACC -# endif -# define machine_is_esl_sarva_acc() (machine_arch_type == MACH_TYPE_ESL_SARVA_ACC) -#else -# define machine_is_esl_sarva_acc() (0) -#endif - -#ifdef CONFIG_MACH_TYPHOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TYPHOON -# endif -# define machine_is_typhoon() (machine_arch_type == MACH_TYPE_TYPHOON) -#else -# define machine_is_typhoon() (0) -#endif - -#ifdef CONFIG_MACH_CNAV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNAV -# endif -# define machine_is_cnav() (machine_arch_type == MACH_TYPE_CNAV) -#else -# define machine_is_cnav() (0) -#endif - -#ifdef CONFIG_MACH_A730 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A730 -# endif -# define machine_is_a730() (machine_arch_type == MACH_TYPE_A730) -#else -# define machine_is_a730() (0) -#endif - -#ifdef CONFIG_MACH_NETSTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSTAR -# endif -# define machine_is_netstar() (machine_arch_type == MACH_TYPE_NETSTAR) -#else -# define machine_is_netstar() (0) -#endif - -#ifdef CONFIG_MACH_PHASEFALE_SUPERCON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHASEFALE_SUPERCON -# endif -# define machine_is_supercon() (machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON) -#else -# define machine_is_supercon() (0) -#endif - -#ifdef CONFIG_MACH_SHIVA1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHIVA1100 -# endif -# define machine_is_shiva1100() (machine_arch_type == MACH_TYPE_SHIVA1100) -#else -# define machine_is_shiva1100() (0) -#endif - -#ifdef CONFIG_MACH_ETEXSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETEXSC -# endif -# define machine_is_etexsc() (machine_arch_type == MACH_TYPE_ETEXSC) -#else -# define machine_is_etexsc() (0) -#endif - -#ifdef CONFIG_MACH_IXDPG465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDPG465 -# endif -# define machine_is_ixdpg465() (machine_arch_type == MACH_TYPE_IXDPG465) -#else -# define machine_is_ixdpg465() (0) -#endif - -#ifdef CONFIG_MACH_A9M2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M2410 -# endif -# define machine_is_a9m2410() (machine_arch_type == MACH_TYPE_A9M2410) -#else -# define machine_is_a9m2410() (0) -#endif - -#ifdef CONFIG_MACH_A9M2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M2440 -# endif -# define machine_is_a9m2440() (machine_arch_type == MACH_TYPE_A9M2440) -#else -# define machine_is_a9m2440() (0) -#endif - -#ifdef CONFIG_MACH_A9M9750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M9750 -# endif -# define machine_is_a9m9750() (machine_arch_type == MACH_TYPE_A9M9750) -#else -# define machine_is_a9m9750() (0) -#endif - -#ifdef CONFIG_MACH_A9M9360 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M9360 -# endif -# define machine_is_a9m9360() (machine_arch_type == MACH_TYPE_A9M9360) -#else -# define machine_is_a9m9360() (0) -#endif - -#ifdef CONFIG_MACH_UNC90 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNC90 -# endif -# define machine_is_unc90() (machine_arch_type == MACH_TYPE_UNC90) -#else -# define machine_is_unc90() (0) -#endif - -#ifdef CONFIG_MACH_ECO920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECO920 -# endif -# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920) -#else -# define machine_is_eco920() (0) -#endif - -#ifdef CONFIG_MACH_SATVIEW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SATVIEW -# endif -# define machine_is_satview() (machine_arch_type == MACH_TYPE_SATVIEW) -#else -# define machine_is_satview() (0) -#endif - -#ifdef CONFIG_MACH_ROADRUNNER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROADRUNNER -# endif -# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER) -#else -# define machine_is_roadrunner() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200EK -# endif -# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK) -#else -# define machine_is_at91rm9200ek() (0) -#endif - -#ifdef CONFIG_MACH_GP32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GP32 -# endif -# define machine_is_gp32() (machine_arch_type == MACH_TYPE_GP32) -#else -# define machine_is_gp32() (0) -#endif - -#ifdef CONFIG_MACH_GEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEM -# endif -# define machine_is_gem() (machine_arch_type == MACH_TYPE_GEM) -#else -# define machine_is_gem() (0) -#endif - -#ifdef CONFIG_MACH_I858 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I858 -# endif -# define machine_is_i858() (machine_arch_type == MACH_TYPE_I858) -#else -# define machine_is_i858() (0) -#endif - -#ifdef CONFIG_MACH_HX2750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HX2750 -# endif -# define machine_is_hx2750() (machine_arch_type == MACH_TYPE_HX2750) -#else -# define machine_is_hx2750() (0) -#endif - -#ifdef CONFIG_MACH_MXC91131EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC91131EVB -# endif -# define machine_is_mxc91131evb() (machine_arch_type == MACH_TYPE_MXC91131EVB) -#else -# define machine_is_mxc91131evb() (0) -#endif - -#ifdef CONFIG_MACH_P700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P700 -# endif -# define machine_is_p700() (machine_arch_type == MACH_TYPE_P700) -#else -# define machine_is_p700() (0) -#endif - -#ifdef CONFIG_MACH_CPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPE -# endif -# define machine_is_cpe() (machine_arch_type == MACH_TYPE_CPE) -#else -# define machine_is_cpe() (0) -#endif - -#ifdef CONFIG_MACH_SPITZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPITZ -# endif -# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ) -#else -# define machine_is_spitz() (0) -#endif - -#ifdef CONFIG_MACH_NIMBRA340 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA340 -# endif -# define machine_is_nimbra340() (machine_arch_type == MACH_TYPE_NIMBRA340) -#else -# define machine_is_nimbra340() (0) -#endif - -#ifdef CONFIG_MACH_LPC22XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC22XX -# endif -# define machine_is_lpc22xx() (machine_arch_type == MACH_TYPE_LPC22XX) -#else -# define machine_is_lpc22xx() (0) -#endif - -#ifdef CONFIG_MACH_COMET3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMET3 -# endif -# define machine_is_omap_comet3() (machine_arch_type == MACH_TYPE_COMET3) -#else -# define machine_is_omap_comet3() (0) -#endif - -#ifdef CONFIG_MACH_COMET4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMET4 -# endif -# define machine_is_omap_comet4() (machine_arch_type == MACH_TYPE_COMET4) -#else -# define machine_is_omap_comet4() (0) -#endif - -#ifdef CONFIG_MACH_CSB625 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB625 -# endif -# define machine_is_csb625() (machine_arch_type == MACH_TYPE_CSB625) -#else -# define machine_is_csb625() (0) -#endif - -#ifdef CONFIG_MACH_FORTUNET2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET2 -# endif -# define machine_is_fortunet2() (machine_arch_type == MACH_TYPE_FORTUNET2) -#else -# define machine_is_fortunet2() (0) -#endif - -#ifdef CONFIG_MACH_S5H2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5H2200 -# endif -# define machine_is_s5h2200() (machine_arch_type == MACH_TYPE_S5H2200) -#else -# define machine_is_s5h2200() (0) -#endif - -#ifdef CONFIG_MACH_OPTORM920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPTORM920 -# endif -# define machine_is_optorm920() (machine_arch_type == MACH_TYPE_OPTORM920) -#else -# define machine_is_optorm920() (0) -#endif - -#ifdef CONFIG_MACH_ADSBITSYXB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYXB -# endif -# define machine_is_adsbitsyxb() (machine_arch_type == MACH_TYPE_ADSBITSYXB) -#else -# define machine_is_adsbitsyxb() (0) -#endif - -#ifdef CONFIG_MACH_ADSSPHERE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSSPHERE -# endif -# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE) -#else -# define machine_is_adssphere() (0) -#endif - -#ifdef CONFIG_MACH_ADSPORTAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSPORTAL -# endif -# define machine_is_adsportal() (machine_arch_type == MACH_TYPE_ADSPORTAL) -#else -# define machine_is_adsportal() (0) -#endif - -#ifdef CONFIG_MACH_LN2410SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LN2410SBC -# endif -# define machine_is_ln2410sbc() (machine_arch_type == MACH_TYPE_LN2410SBC) -#else -# define machine_is_ln2410sbc() (0) -#endif - -#ifdef CONFIG_MACH_CB3RUFC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CB3RUFC -# endif -# define machine_is_cb3rufc() (machine_arch_type == MACH_TYPE_CB3RUFC) -#else -# define machine_is_cb3rufc() (0) -#endif - -#ifdef CONFIG_MACH_MP2USB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP2USB -# endif -# define machine_is_mp2usb() (machine_arch_type == MACH_TYPE_MP2USB) -#else -# define machine_is_mp2usb() (0) -#endif - -#ifdef CONFIG_MACH_NTNP425C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NTNP425C -# endif -# define machine_is_ntnp425c() (machine_arch_type == MACH_TYPE_NTNP425C) -#else -# define machine_is_ntnp425c() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI -# endif -# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) -#else -# define machine_is_colibri() (0) -#endif - -#ifdef CONFIG_MACH_PCM7220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM7220 -# endif -# define machine_is_pcm7220() (machine_arch_type == MACH_TYPE_PCM7220) -#else -# define machine_is_pcm7220() (0) -#endif - -#ifdef CONFIG_MACH_GATEWAY7001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GATEWAY7001 -# endif -# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) -#else -# define machine_is_gateway7001() (0) -#endif - -#ifdef CONFIG_MACH_PCM027 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM027 -# endif -# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) -#else -# define machine_is_pcm027() (0) -#endif - -#ifdef CONFIG_MACH_CMPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMPXA -# endif -# define machine_is_cmpxa() (machine_arch_type == MACH_TYPE_CMPXA) -#else -# define machine_is_cmpxa() (0) -#endif - -#ifdef CONFIG_MACH_ANUBIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANUBIS -# endif -# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) -#else -# define machine_is_anubis() (0) -#endif - -#ifdef CONFIG_MACH_ITE8152 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITE8152 -# endif -# define machine_is_ite8152() (machine_arch_type == MACH_TYPE_ITE8152) -#else -# define machine_is_ite8152() (0) -#endif - -#ifdef CONFIG_MACH_LPC3XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC3XXX -# endif -# define machine_is_lpc3xxx() (machine_arch_type == MACH_TYPE_LPC3XXX) -#else -# define machine_is_lpc3xxx() (0) -#endif - -#ifdef CONFIG_MACH_PUPPETEER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUPPETEER -# endif -# define machine_is_puppeteer() (machine_arch_type == MACH_TYPE_PUPPETEER) -#else -# define machine_is_puppeteer() (0) -#endif - -#ifdef CONFIG_MACH_E570 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E570 -# endif -# define machine_is_e570() (machine_arch_type == MACH_TYPE_E570) -#else -# define machine_is_e570() (0) -#endif - -#ifdef CONFIG_MACH_X50 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X50 -# endif -# define machine_is_x50() (machine_arch_type == MACH_TYPE_X50) -#else -# define machine_is_x50() (0) -#endif - -#ifdef CONFIG_MACH_RECON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RECON -# endif -# define machine_is_recon() (machine_arch_type == MACH_TYPE_RECON) -#else -# define machine_is_recon() (0) -#endif - -#ifdef CONFIG_MACH_XBOARDGP8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XBOARDGP8 -# endif -# define machine_is_xboardgp8() (machine_arch_type == MACH_TYPE_XBOARDGP8) -#else -# define machine_is_xboardgp8() (0) -#endif - -#ifdef CONFIG_MACH_FPIC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FPIC2 -# endif -# define machine_is_fpic2() (machine_arch_type == MACH_TYPE_FPIC2) -#else -# define machine_is_fpic2() (0) -#endif - -#ifdef CONFIG_MACH_AKITA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKITA -# endif -# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) -#else -# define machine_is_akita() (0) -#endif - -#ifdef CONFIG_MACH_A81 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A81 -# endif -# define machine_is_a81() (machine_arch_type == MACH_TYPE_A81) -#else -# define machine_is_a81() (0) -#endif - -#ifdef CONFIG_MACH_SVM_SC25X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVM_SC25X -# endif -# define machine_is_svm_sc25x() (machine_arch_type == MACH_TYPE_SVM_SC25X) -#else -# define machine_is_svm_sc25x() (0) -#endif - -#ifdef CONFIG_MACH_VADATECH020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VADATECH020 -# endif -# define machine_is_vt020() (machine_arch_type == MACH_TYPE_VADATECH020) -#else -# define machine_is_vt020() (0) -#endif - -#ifdef CONFIG_MACH_TLI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLI -# endif -# define machine_is_tli() (machine_arch_type == MACH_TYPE_TLI) -#else -# define machine_is_tli() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315LC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315LC -# endif -# define machine_is_edb9315lc() (machine_arch_type == MACH_TYPE_EDB9315LC) -#else -# define machine_is_edb9315lc() (0) -#endif - -#ifdef CONFIG_MACH_PASSEC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PASSEC -# endif -# define machine_is_passec() (machine_arch_type == MACH_TYPE_PASSEC) -#else -# define machine_is_passec() (0) -#endif - -#ifdef CONFIG_MACH_DS_TIGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS_TIGER -# endif -# define machine_is_ds_tiger() (machine_arch_type == MACH_TYPE_DS_TIGER) -#else -# define machine_is_ds_tiger() (0) -#endif - -#ifdef CONFIG_MACH_E310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E310 -# endif -# define machine_is_e310() (machine_arch_type == MACH_TYPE_E310) -#else -# define machine_is_e310() (0) -#endif - -#ifdef CONFIG_MACH_E330 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E330 -# endif -# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) -#else -# define machine_is_e330() (0) -#endif - -#ifdef CONFIG_MACH_RT3000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RT3000 -# endif -# define machine_is_rt3000() (machine_arch_type == MACH_TYPE_RT3000) -#else -# define machine_is_rt3000() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA770 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA770 -# endif -# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) -#else -# define machine_is_nokia770() (0) -#endif - -#ifdef CONFIG_MACH_PNX0106 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX0106 -# endif -# define machine_is_pnx0106() (machine_arch_type == MACH_TYPE_PNX0106) -#else -# define machine_is_pnx0106() (0) -#endif - -#ifdef CONFIG_MACH_HX21XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HX21XX -# endif -# define machine_is_hx21xx() (machine_arch_type == MACH_TYPE_HX21XX) -#else -# define machine_is_hx21xx() (0) -#endif - -#ifdef CONFIG_MACH_FARADAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FARADAY -# endif -# define machine_is_faraday() (machine_arch_type == MACH_TYPE_FARADAY) -#else -# define machine_is_faraday() (0) -#endif - -#ifdef CONFIG_MACH_SBC9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC9312 -# endif -# define machine_is_sbc9312() (machine_arch_type == MACH_TYPE_SBC9312) -#else -# define machine_is_sbc9312() (0) -#endif - -#ifdef CONFIG_MACH_BATMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BATMAN -# endif -# define machine_is_batman() (machine_arch_type == MACH_TYPE_BATMAN) -#else -# define machine_is_batman() (0) -#endif - -#ifdef CONFIG_MACH_JPD201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JPD201 -# endif -# define machine_is_jpd201() (machine_arch_type == MACH_TYPE_JPD201) -#else -# define machine_is_jpd201() (0) -#endif - -#ifdef CONFIG_MACH_MIPSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIPSA -# endif -# define machine_is_mipsa() (machine_arch_type == MACH_TYPE_MIPSA) -#else -# define machine_is_mipsa() (0) -#endif - -#ifdef CONFIG_MACH_KACOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KACOM -# endif -# define machine_is_kacom() (machine_arch_type == MACH_TYPE_KACOM) -#else -# define machine_is_kacom() (0) -#endif - -#ifdef CONFIG_MACH_SWARCOCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCOCPU -# endif -# define machine_is_swarcocpu() (machine_arch_type == MACH_TYPE_SWARCOCPU) -#else -# define machine_is_swarcocpu() (0) -#endif - -#ifdef CONFIG_MACH_SWARCODSL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCODSL -# endif -# define machine_is_swarcodsl() (machine_arch_type == MACH_TYPE_SWARCODSL) -#else -# define machine_is_swarcodsl() (0) -#endif - -#ifdef CONFIG_MACH_BLUEANGEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEANGEL -# endif -# define machine_is_blueangel() (machine_arch_type == MACH_TYPE_BLUEANGEL) -#else -# define machine_is_blueangel() (0) -#endif - -#ifdef CONFIG_MACH_HAIRYGRAMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAIRYGRAMA -# endif -# define machine_is_hairygrama() (machine_arch_type == MACH_TYPE_HAIRYGRAMA) -#else -# define machine_is_hairygrama() (0) -#endif - -#ifdef CONFIG_MACH_BANFF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BANFF -# endif -# define machine_is_banff() (machine_arch_type == MACH_TYPE_BANFF) -#else -# define machine_is_banff() (0) -#endif - -#ifdef CONFIG_MACH_CARMEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARMEVA -# endif -# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) -#else -# define machine_is_carmeva() (0) -#endif - -#ifdef CONFIG_MACH_SAM255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM255 -# endif -# define machine_is_sam255() (machine_arch_type == MACH_TYPE_SAM255) -#else -# define machine_is_sam255() (0) -#endif - -#ifdef CONFIG_MACH_PPM10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PPM10 -# endif -# define machine_is_ppm10() (machine_arch_type == MACH_TYPE_PPM10) -#else -# define machine_is_ppm10() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315A -# endif -# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) -#else -# define machine_is_edb9315a() (0) -#endif - -#ifdef CONFIG_MACH_SUNSET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUNSET -# endif -# define machine_is_sunset() (machine_arch_type == MACH_TYPE_SUNSET) -#else -# define machine_is_sunset() (0) -#endif - -#ifdef CONFIG_MACH_STARGATE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGATE2 -# endif -# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) -#else -# define machine_is_stargate2() (0) -#endif - -#ifdef CONFIG_MACH_INTELMOTE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTELMOTE2 -# endif -# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) -#else -# define machine_is_intelmote2() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS4 -# endif -# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) -#else -# define machine_is_trizeps4() (0) -#endif - -#ifdef CONFIG_MACH_MAINSTONE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAINSTONE2 -# endif -# define machine_is_mainstone2() (machine_arch_type == MACH_TYPE_MAINSTONE2) -#else -# define machine_is_mainstone2() (0) -#endif - -#ifdef CONFIG_MACH_EZ_IXP42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_IXP42X -# endif -# define machine_is_ez_ixp42x() (machine_arch_type == MACH_TYPE_EZ_IXP42X) -#else -# define machine_is_ez_ixp42x() (0) -#endif - -#ifdef CONFIG_MACH_TAPWAVE_ZODIAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAPWAVE_ZODIAC -# endif -# define machine_is_tapwave_zodiac() (machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC) -#else -# define machine_is_tapwave_zodiac() (0) -#endif - -#ifdef CONFIG_MACH_UNIVERSALMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIVERSALMETER -# endif -# define machine_is_universalmeter() (machine_arch_type == MACH_TYPE_UNIVERSALMETER) -#else -# define machine_is_universalmeter() (0) -#endif - -#ifdef CONFIG_MACH_HICOARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HICOARM9 -# endif -# define machine_is_hicoarm9() (machine_arch_type == MACH_TYPE_HICOARM9) -#else -# define machine_is_hicoarm9() (0) -#endif - -#ifdef CONFIG_MACH_PNX4008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4008 -# endif -# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) -#else -# define machine_is_pnx4008() (0) -#endif - -#ifdef CONFIG_MACH_KWS6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KWS6000 -# endif -# define machine_is_kws6000() (machine_arch_type == MACH_TYPE_KWS6000) -#else -# define machine_is_kws6000() (0) -#endif - -#ifdef CONFIG_MACH_PORTUX920T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PORTUX920T -# endif -# define machine_is_portux920t() (machine_arch_type == MACH_TYPE_PORTUX920T) -#else -# define machine_is_portux920t() (0) -#endif - -#ifdef CONFIG_MACH_EZ_X5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_X5 -# endif -# define machine_is_ez_x5() (machine_arch_type == MACH_TYPE_EZ_X5) -#else -# define machine_is_ez_x5() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_RUDOLPH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_RUDOLPH -# endif -# define machine_is_omap_rudolph() (machine_arch_type == MACH_TYPE_OMAP_RUDOLPH) -#else -# define machine_is_omap_rudolph() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT91 -# endif -# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) -#else -# define machine_is_cpuat91() (0) -#endif - -#ifdef CONFIG_MACH_REA9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA9200 -# endif -# define machine_is_rea9200() (machine_arch_type == MACH_TYPE_REA9200) -#else -# define machine_is_rea9200() (0) -#endif - -#ifdef CONFIG_MACH_ACTS_PUNE_SA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTS_PUNE_SA1110 -# endif -# define machine_is_acts_pune_sa1110() (machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110) -#else -# define machine_is_acts_pune_sa1110() (0) -#endif - -#ifdef CONFIG_MACH_IXP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425 -# endif -# define machine_is_ixp425() (machine_arch_type == MACH_TYPE_IXP425) -#else -# define machine_is_ixp425() (0) -#endif - -#ifdef CONFIG_MACH_I30030ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I30030ADS -# endif -# define machine_is_i30030ads() (machine_arch_type == MACH_TYPE_I30030ADS) -#else -# define machine_is_i30030ads() (0) -#endif - -#ifdef CONFIG_MACH_PERCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERCH -# endif -# define machine_is_perch() (machine_arch_type == MACH_TYPE_PERCH) -#else -# define machine_is_perch() (0) -#endif - -#ifdef CONFIG_MACH_EIS05R1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EIS05R1 -# endif -# define machine_is_eis05r1() (machine_arch_type == MACH_TYPE_EIS05R1) -#else -# define machine_is_eis05r1() (0) -#endif - -#ifdef CONFIG_MACH_PEPPERPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEPPERPAD -# endif -# define machine_is_pepperpad() (machine_arch_type == MACH_TYPE_PEPPERPAD) -#else -# define machine_is_pepperpad() (0) -#endif - -#ifdef CONFIG_MACH_SB3010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SB3010 -# endif -# define machine_is_sb3010() (machine_arch_type == MACH_TYPE_SB3010) -#else -# define machine_is_sb3010() (0) -#endif - -#ifdef CONFIG_MACH_RM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RM9200 -# endif -# define machine_is_rm9200() (machine_arch_type == MACH_TYPE_RM9200) -#else -# define machine_is_rm9200() (0) -#endif - -#ifdef CONFIG_MACH_DMA03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DMA03 -# endif -# define machine_is_dma03() (machine_arch_type == MACH_TYPE_DMA03) -#else -# define machine_is_dma03() (0) -#endif - -#ifdef CONFIG_MACH_ROAD_S101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROAD_S101 -# endif -# define machine_is_road_s101() (machine_arch_type == MACH_TYPE_ROAD_S101) -#else -# define machine_is_road_s101() (0) -#endif - -#ifdef CONFIG_MACH_IQ81340SC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ81340SC -# endif -# define machine_is_iq81340sc() (machine_arch_type == MACH_TYPE_IQ81340SC) -#else -# define machine_is_iq81340sc() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_B -# endif -# define machine_is_iq_nextgen_b() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B) -#else -# define machine_is_iq_nextgen_b() (0) -#endif - -#ifdef CONFIG_MACH_IQ81340MC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ81340MC -# endif -# define machine_is_iq81340mc() (machine_arch_type == MACH_TYPE_IQ81340MC) -#else -# define machine_is_iq81340mc() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_D -# endif -# define machine_is_iq_nextgen_d() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D) -#else -# define machine_is_iq_nextgen_d() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_E -# endif -# define machine_is_iq_nextgen_e() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E) -#else -# define machine_is_iq_nextgen_e() (0) -#endif - -#ifdef CONFIG_MACH_MALLOW_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MALLOW_AT91 -# endif -# define machine_is_mallow_at91() (machine_arch_type == MACH_TYPE_MALLOW_AT91) -#else -# define machine_is_mallow_at91() (0) -#endif - -#ifdef CONFIG_MACH_CYBERTRACKER_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBERTRACKER_I -# endif -# define machine_is_cybertracker_i() (machine_arch_type == MACH_TYPE_CYBERTRACKER_I) -#else -# define machine_is_cybertracker_i() (0) -#endif - -#ifdef CONFIG_MACH_GESBC931X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC931X -# endif -# define machine_is_gesbc931x() (machine_arch_type == MACH_TYPE_GESBC931X) -#else -# define machine_is_gesbc931x() (0) -#endif - -#ifdef CONFIG_MACH_CENTIPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CENTIPAD -# endif -# define machine_is_centipad() (machine_arch_type == MACH_TYPE_CENTIPAD) -#else -# define machine_is_centipad() (0) -#endif - -#ifdef CONFIG_MACH_ARMSOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMSOC -# endif -# define machine_is_armsoc() (machine_arch_type == MACH_TYPE_ARMSOC) -#else -# define machine_is_armsoc() (0) -#endif - -#ifdef CONFIG_MACH_SE4200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE4200 -# endif -# define machine_is_se4200() (machine_arch_type == MACH_TYPE_SE4200) -#else -# define machine_is_se4200() (0) -#endif - -#ifdef CONFIG_MACH_EMS197A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMS197A -# endif -# define machine_is_ems197a() (machine_arch_type == MACH_TYPE_EMS197A) -#else -# define machine_is_ems197a() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9 -# endif -# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) -#else -# define machine_is_micro9() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9L -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9L -# endif -# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) -#else -# define machine_is_micro9l() (0) -#endif - -#ifdef CONFIG_MACH_UC5471DSP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UC5471DSP -# endif -# define machine_is_uc5471dsp() (machine_arch_type == MACH_TYPE_UC5471DSP) -#else -# define machine_is_uc5471dsp() (0) -#endif - -#ifdef CONFIG_MACH_SJ5471ENG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SJ5471ENG -# endif -# define machine_is_sj5471eng() (machine_arch_type == MACH_TYPE_SJ5471ENG) -#else -# define machine_is_sj5471eng() (0) -#endif - -#ifdef CONFIG_MACH_CMPXA26X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMPXA26X -# endif -# define machine_is_none() (machine_arch_type == MACH_TYPE_CMPXA26X) -#else -# define machine_is_none() (0) -#endif - -#ifdef CONFIG_MACH_NC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NC -# endif -# define machine_is_nc1() (machine_arch_type == MACH_TYPE_NC) -#else -# define machine_is_nc1() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTE -# endif -# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) -#else -# define machine_is_omap_palmte() (0) -#endif - -#ifdef CONFIG_MACH_AJAX52X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AJAX52X -# endif -# define machine_is_ajax52x() (machine_arch_type == MACH_TYPE_AJAX52X) -#else -# define machine_is_ajax52x() (0) -#endif - -#ifdef CONFIG_MACH_SIRIUSTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIRIUSTAR -# endif -# define machine_is_siriustar() (machine_arch_type == MACH_TYPE_SIRIUSTAR) -#else -# define machine_is_siriustar() (0) -#endif - -#ifdef CONFIG_MACH_IODATA_HDLG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IODATA_HDLG -# endif -# define machine_is_iodata_hdlg() (machine_arch_type == MACH_TYPE_IODATA_HDLG) -#else -# define machine_is_iodata_hdlg() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200UTL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200UTL -# endif -# define machine_is_at91rm9200utl() (machine_arch_type == MACH_TYPE_AT91RM9200UTL) -#else -# define machine_is_at91rm9200utl() (0) -#endif - -#ifdef CONFIG_MACH_BIOSAFE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIOSAFE -# endif -# define machine_is_biosafe() (machine_arch_type == MACH_TYPE_BIOSAFE) -#else -# define machine_is_biosafe() (0) -#endif - -#ifdef CONFIG_MACH_MP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP1000 -# endif -# define machine_is_mp1000() (machine_arch_type == MACH_TYPE_MP1000) -#else -# define machine_is_mp1000() (0) -#endif - -#ifdef CONFIG_MACH_PARSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PARSY -# endif -# define machine_is_parsy() (machine_arch_type == MACH_TYPE_PARSY) -#else -# define machine_is_parsy() (0) -#endif - -#ifdef CONFIG_MACH_CCXP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCXP -# endif -# define machine_is_ccxp270() (machine_arch_type == MACH_TYPE_CCXP) -#else -# define machine_is_ccxp270() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_GSAMPLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_GSAMPLE -# endif -# define machine_is_omap_gsample() (machine_arch_type == MACH_TYPE_OMAP_GSAMPLE) -#else -# define machine_is_omap_gsample() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_EB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_EB -# endif -# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) -#else -# define machine_is_realview_eb() (0) -#endif - -#ifdef CONFIG_MACH_SAMOA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMOA -# endif -# define machine_is_samoa() (machine_arch_type == MACH_TYPE_SAMOA) -#else -# define machine_is_samoa() (0) -#endif - -#ifdef CONFIG_MACH_PALMT3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMT3 -# endif -# define machine_is_palmt3() (machine_arch_type == MACH_TYPE_PALMT3) -#else -# define machine_is_palmt3() (0) -#endif - -#ifdef CONFIG_MACH_I878 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I878 -# endif -# define machine_is_i878() (machine_arch_type == MACH_TYPE_I878) -#else -# define machine_is_i878() (0) -#endif - -#ifdef CONFIG_MACH_BORZOI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BORZOI -# endif -# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) -#else -# define machine_is_borzoi() (0) -#endif - -#ifdef CONFIG_MACH_GECKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GECKO -# endif -# define machine_is_gecko() (machine_arch_type == MACH_TYPE_GECKO) -#else -# define machine_is_gecko() (0) -#endif - -#ifdef CONFIG_MACH_DS101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS101 -# endif -# define machine_is_ds101() (machine_arch_type == MACH_TYPE_DS101) -#else -# define machine_is_ds101() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTT2 -# endif -# define machine_is_omap_palmtt2() (machine_arch_type == MACH_TYPE_OMAP_PALMTT2) -#else -# define machine_is_omap_palmtt2() (0) -#endif - -#ifdef CONFIG_MACH_PALMLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMLD -# endif -# define machine_is_palmld() (machine_arch_type == MACH_TYPE_PALMLD) -#else -# define machine_is_palmld() (0) -#endif - -#ifdef CONFIG_MACH_CC9C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9C -# endif -# define machine_is_cc9c() (machine_arch_type == MACH_TYPE_CC9C) -#else -# define machine_is_cc9c() (0) -#endif - -#ifdef CONFIG_MACH_SBC1670 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC1670 -# endif -# define machine_is_sbc1670() (machine_arch_type == MACH_TYPE_SBC1670) -#else -# define machine_is_sbc1670() (0) -#endif - -#ifdef CONFIG_MACH_IXDP28X5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP28X5 -# endif -# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) -#else -# define machine_is_ixdp28x5() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTT -# endif -# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) -#else -# define machine_is_omap_palmtt() (0) -#endif - -#ifdef CONFIG_MACH_ML696K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML696K -# endif -# define machine_is_ml696k() (machine_arch_type == MACH_TYPE_ML696K) -#else -# define machine_is_ml696k() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_ZEUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_ZEUS -# endif -# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) -#else -# define machine_is_arcom_zeus() (0) -#endif - -#ifdef CONFIG_MACH_OSIRIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSIRIS -# endif -# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) -#else -# define machine_is_osiris() (0) -#endif - -#ifdef CONFIG_MACH_MAESTRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAESTRO -# endif -# define machine_is_maestro() (machine_arch_type == MACH_TYPE_MAESTRO) -#else -# define machine_is_maestro() (0) -#endif - -#ifdef CONFIG_MACH_PALMTE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTE2 -# endif -# define machine_is_palmte2() (machine_arch_type == MACH_TYPE_PALMTE2) -#else -# define machine_is_palmte2() (0) -#endif - -#ifdef CONFIG_MACH_IXBBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXBBM -# endif -# define machine_is_ixbbm() (machine_arch_type == MACH_TYPE_IXBBM) -#else -# define machine_is_ixbbm() (0) -#endif - -#ifdef CONFIG_MACH_MX27ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27ADS -# endif -# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27ADS) -#else -# define machine_is_mx27ads() (0) -#endif - -#ifdef CONFIG_MACH_AX8004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AX8004 -# endif -# define machine_is_ax8004() (machine_arch_type == MACH_TYPE_AX8004) -#else -# define machine_is_ax8004() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9261EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9261EK -# endif -# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) -#else -# define machine_is_at91sam9261ek() (0) -#endif - -#ifdef CONFIG_MACH_LOFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOFT -# endif -# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) -#else -# define machine_is_loft() (0) -#endif - -#ifdef CONFIG_MACH_MAGPIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGPIE -# endif -# define machine_is_magpie() (machine_arch_type == MACH_TYPE_MAGPIE) -#else -# define machine_is_magpie() (0) -#endif - -#ifdef CONFIG_MACH_MX21ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX21ADS -# endif -# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21ADS) -#else -# define machine_is_mx21ads() (0) -#endif - -#ifdef CONFIG_MACH_MB87M3400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB87M3400 -# endif -# define machine_is_mb87m3400() (machine_arch_type == MACH_TYPE_MB87M3400) -#else -# define machine_is_mb87m3400() (0) -#endif - -#ifdef CONFIG_MACH_MGUARD_DELTA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MGUARD_DELTA -# endif -# define machine_is_mguard_delta() (machine_arch_type == MACH_TYPE_MGUARD_DELTA) -#else -# define machine_is_mguard_delta() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DVDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DVDP -# endif -# define machine_is_davinci_dvdp() (machine_arch_type == MACH_TYPE_DAVINCI_DVDP) -#else -# define machine_is_davinci_dvdp() (0) -#endif - -#ifdef CONFIG_MACH_HTCUNIVERSAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCUNIVERSAL -# endif -# define machine_is_htcuniversal() (machine_arch_type == MACH_TYPE_HTCUNIVERSAL) -#else -# define machine_is_htcuniversal() (0) -#endif - -#ifdef CONFIG_MACH_TPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPAD -# endif -# define machine_is_tpad() (machine_arch_type == MACH_TYPE_TPAD) -#else -# define machine_is_tpad() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP3 -# endif -# define machine_is_roverp3() (machine_arch_type == MACH_TYPE_ROVERP3) -#else -# define machine_is_roverp3() (0) -#endif - -#ifdef CONFIG_MACH_JORNADA928 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA928 -# endif -# define machine_is_jornada928() (machine_arch_type == MACH_TYPE_JORNADA928) -#else -# define machine_is_jornada928() (0) -#endif - -#ifdef CONFIG_MACH_MV88FXX81 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88FXX81 -# endif -# define machine_is_mv88fxx81() (machine_arch_type == MACH_TYPE_MV88FXX81) -#else -# define machine_is_mv88fxx81() (0) -#endif - -#ifdef CONFIG_MACH_STMP36XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP36XX -# endif -# define machine_is_stmp36xx() (machine_arch_type == MACH_TYPE_STMP36XX) -#else -# define machine_is_stmp36xx() (0) -#endif - -#ifdef CONFIG_MACH_SXNI79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SXNI79524 -# endif -# define machine_is_sxni79524() (machine_arch_type == MACH_TYPE_SXNI79524) -#else -# define machine_is_sxni79524() (0) -#endif - -#ifdef CONFIG_MACH_AMS_DELTA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMS_DELTA -# endif -# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) -#else -# define machine_is_ams_delta() (0) -#endif - -#ifdef CONFIG_MACH_URANIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_URANIUM -# endif -# define machine_is_uranium() (machine_arch_type == MACH_TYPE_URANIUM) -#else -# define machine_is_uranium() (0) -#endif - -#ifdef CONFIG_MACH_UCON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCON -# endif -# define machine_is_ucon() (machine_arch_type == MACH_TYPE_UCON) -#else -# define machine_is_ucon() (0) -#endif - -#ifdef CONFIG_MACH_NAS100D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS100D -# endif -# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) -#else -# define machine_is_nas100d() (0) -#endif - -#ifdef CONFIG_MACH_L083_1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_L083_1000 -# endif -# define machine_is_l083() (machine_arch_type == MACH_TYPE_L083_1000) -#else -# define machine_is_l083() (0) -#endif - -#ifdef CONFIG_MACH_EZX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX -# endif -# define machine_is_ezx() (machine_arch_type == MACH_TYPE_EZX) -#else -# define machine_is_ezx() (0) -#endif - -#ifdef CONFIG_MACH_PNX5220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX5220 -# endif -# define machine_is_pnx5220() (machine_arch_type == MACH_TYPE_PNX5220) -#else -# define machine_is_pnx5220() (0) -#endif - -#ifdef CONFIG_MACH_BUTTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUTTE -# endif -# define machine_is_butte() (machine_arch_type == MACH_TYPE_BUTTE) -#else -# define machine_is_butte() (0) -#endif - -#ifdef CONFIG_MACH_SRM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SRM2 -# endif -# define machine_is_srm2() (machine_arch_type == MACH_TYPE_SRM2) -#else -# define machine_is_srm2() (0) -#endif - -#ifdef CONFIG_MACH_DSBR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSBR -# endif -# define machine_is_dsbr() (machine_arch_type == MACH_TYPE_DSBR) -#else -# define machine_is_dsbr() (0) -#endif - -#ifdef CONFIG_MACH_CRYSTALBALL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CRYSTALBALL -# endif -# define machine_is_crystalball() (machine_arch_type == MACH_TYPE_CRYSTALBALL) -#else -# define machine_is_crystalball() (0) -#endif - -#ifdef CONFIG_MACH_TINYPXA27X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TINYPXA27X -# endif -# define machine_is_tinypxa27x() (machine_arch_type == MACH_TYPE_TINYPXA27X) -#else -# define machine_is_tinypxa27x() (0) -#endif - -#ifdef CONFIG_MACH_HERBIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERBIE -# endif -# define machine_is_herbie() (machine_arch_type == MACH_TYPE_HERBIE) -#else -# define machine_is_herbie() (0) -#endif - -#ifdef CONFIG_MACH_MAGICIAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGICIAN -# endif -# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) -#else -# define machine_is_magician() (0) -#endif - -#ifdef CONFIG_MACH_CM4002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM4002 -# endif -# define machine_is_cm4002() (machine_arch_type == MACH_TYPE_CM4002) -#else -# define machine_is_cm4002() (0) -#endif - -#ifdef CONFIG_MACH_B4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_B4 -# endif -# define machine_is_b4() (machine_arch_type == MACH_TYPE_B4) -#else -# define machine_is_b4() (0) -#endif - -#ifdef CONFIG_MACH_MAUI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAUI -# endif -# define machine_is_maui() (machine_arch_type == MACH_TYPE_MAUI) -#else -# define machine_is_maui() (0) -#endif - -#ifdef CONFIG_MACH_CYBERTRACKER_G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBERTRACKER_G -# endif -# define machine_is_cybertracker_g() (machine_arch_type == MACH_TYPE_CYBERTRACKER_G) -#else -# define machine_is_cybertracker_g() (0) -#endif - -#ifdef CONFIG_MACH_NXDKN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXDKN -# endif -# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) -#else -# define machine_is_nxdkn() (0) -#endif - -#ifdef CONFIG_MACH_MIO8390 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIO8390 -# endif -# define machine_is_mio8390() (machine_arch_type == MACH_TYPE_MIO8390) -#else -# define machine_is_mio8390() (0) -#endif - -#ifdef CONFIG_MACH_OMI_BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMI_BOARD -# endif -# define machine_is_omi_board() (machine_arch_type == MACH_TYPE_OMI_BOARD) -#else -# define machine_is_omi_board() (0) -#endif - -#ifdef CONFIG_MACH_MX21CIV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX21CIV -# endif -# define machine_is_mx21civ() (machine_arch_type == MACH_TYPE_MX21CIV) -#else -# define machine_is_mx21civ() (0) -#endif - -#ifdef CONFIG_MACH_MAHI_CDAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAHI_CDAC -# endif -# define machine_is_mahi_cdac() (machine_arch_type == MACH_TYPE_MAHI_CDAC) -#else -# define machine_is_mahi_cdac() (0) -#endif - -#ifdef CONFIG_MACH_PALMTX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTX -# endif -# define machine_is_palmtx() (machine_arch_type == MACH_TYPE_PALMTX) -#else -# define machine_is_palmtx() (0) -#endif - -#ifdef CONFIG_MACH_S3C2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2413 -# endif -# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) -#else -# define machine_is_s3c2413() (0) -#endif - -#ifdef CONFIG_MACH_SAMSYS_EP0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMSYS_EP0 -# endif -# define machine_is_samsys_ep0() (machine_arch_type == MACH_TYPE_SAMSYS_EP0) -#else -# define machine_is_samsys_ep0() (0) -#endif - -#ifdef CONFIG_MACH_WG302V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WG302V1 -# endif -# define machine_is_wg302v1() (machine_arch_type == MACH_TYPE_WG302V1) -#else -# define machine_is_wg302v1() (0) -#endif - -#ifdef CONFIG_MACH_WG302V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WG302V2 -# endif -# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) -#else -# define machine_is_wg302v2() (0) -#endif - -#ifdef CONFIG_MACH_EB42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB42X -# endif -# define machine_is_eb42x() (machine_arch_type == MACH_TYPE_EB42X) -#else -# define machine_is_eb42x() (0) -#endif - -#ifdef CONFIG_MACH_IQ331ES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ331ES -# endif -# define machine_is_iq331es() (machine_arch_type == MACH_TYPE_IQ331ES) -#else -# define machine_is_iq331es() (0) -#endif - -#ifdef CONFIG_MACH_COSYDSP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COSYDSP -# endif -# define machine_is_cosydsp() (machine_arch_type == MACH_TYPE_COSYDSP) -#else -# define machine_is_cosydsp() (0) -#endif - -#ifdef CONFIG_MACH_UPLAT7D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UPLAT7D -# endif -# define machine_is_uplat7d_proto() (machine_arch_type == MACH_TYPE_UPLAT7D) -#else -# define machine_is_uplat7d_proto() (0) -#endif - -#ifdef CONFIG_MACH_PTDAVINCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTDAVINCI -# endif -# define machine_is_ptdavinci() (machine_arch_type == MACH_TYPE_PTDAVINCI) -#else -# define machine_is_ptdavinci() (0) -#endif - -#ifdef CONFIG_MACH_MBUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBUS -# endif -# define machine_is_mbus() (machine_arch_type == MACH_TYPE_MBUS) -#else -# define machine_is_mbus() (0) -#endif - -#ifdef CONFIG_MACH_NADIA2VB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NADIA2VB -# endif -# define machine_is_nadia2vb() (machine_arch_type == MACH_TYPE_NADIA2VB) -#else -# define machine_is_nadia2vb() (0) -#endif - -#ifdef CONFIG_MACH_R1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_R1000 -# endif -# define machine_is_r1000() (machine_arch_type == MACH_TYPE_R1000) -#else -# define machine_is_r1000() (0) -#endif - -#ifdef CONFIG_MACH_HW90250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90250 -# endif -# define machine_is_hw90250() (machine_arch_type == MACH_TYPE_HW90250) -#else -# define machine_is_hw90250() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430SDP -# endif -# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) -#else -# define machine_is_omap_2430sdp() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_EVM -# endif -# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) -#else -# define machine_is_davinci_evm() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TORNADO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TORNADO -# endif -# define machine_is_omap_tornado() (machine_arch_type == MACH_TYPE_OMAP_TORNADO) -#else -# define machine_is_omap_tornado() (0) -#endif - -#ifdef CONFIG_MACH_OLOCREEK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLOCREEK -# endif -# define machine_is_olocreek() (machine_arch_type == MACH_TYPE_OLOCREEK) -#else -# define machine_is_olocreek() (0) -#endif - -#ifdef CONFIG_MACH_PALMZ72 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMZ72 -# endif -# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) -#else -# define machine_is_palmz72() (0) -#endif - -#ifdef CONFIG_MACH_NXDB500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXDB500 -# endif -# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) -#else -# define machine_is_nxdb500() (0) -#endif - -#ifdef CONFIG_MACH_APF9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APF9328 -# endif -# define machine_is_apf9328() (machine_arch_type == MACH_TYPE_APF9328) -#else -# define machine_is_apf9328() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_WIPOQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_WIPOQ -# endif -# define machine_is_omap_wipoq() (machine_arch_type == MACH_TYPE_OMAP_WIPOQ) -#else -# define machine_is_omap_wipoq() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TWIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TWIP -# endif -# define machine_is_omap_twip() (machine_arch_type == MACH_TYPE_OMAP_TWIP) -#else -# define machine_is_omap_twip() (0) -#endif - -#ifdef CONFIG_MACH_TREO650 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO650 -# endif -# define machine_is_treo650() (machine_arch_type == MACH_TYPE_TREO650) -#else -# define machine_is_treo650() (0) -#endif - -#ifdef CONFIG_MACH_ACUMEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACUMEN -# endif -# define machine_is_acumen() (machine_arch_type == MACH_TYPE_ACUMEN) -#else -# define machine_is_acumen() (0) -#endif - -#ifdef CONFIG_MACH_XP100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP100 -# endif -# define machine_is_xp100() (machine_arch_type == MACH_TYPE_XP100) -#else -# define machine_is_xp100() (0) -#endif - -#ifdef CONFIG_MACH_FS2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FS2410 -# endif -# define machine_is_fs2410() (machine_arch_type == MACH_TYPE_FS2410) -#else -# define machine_is_fs2410() (0) -#endif - -#ifdef CONFIG_MACH_PXA270_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA270_CERF -# endif -# define machine_is_pxa270_cerf() (machine_arch_type == MACH_TYPE_PXA270_CERF) -#else -# define machine_is_pxa270_cerf() (0) -#endif - -#ifdef CONFIG_MACH_SQ2FTLPALM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SQ2FTLPALM -# endif -# define machine_is_sq2ftlpalm() (machine_arch_type == MACH_TYPE_SQ2FTLPALM) -#else -# define machine_is_sq2ftlpalm() (0) -#endif - -#ifdef CONFIG_MACH_BSEMSERVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSEMSERVER -# endif -# define machine_is_bsemserver() (machine_arch_type == MACH_TYPE_BSEMSERVER) -#else -# define machine_is_bsemserver() (0) -#endif - -#ifdef CONFIG_MACH_NETCLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETCLIENT -# endif -# define machine_is_netclient() (machine_arch_type == MACH_TYPE_NETCLIENT) -#else -# define machine_is_netclient() (0) -#endif - -#ifdef CONFIG_MACH_PALMT5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMT5 -# endif -# define machine_is_palmt5() (machine_arch_type == MACH_TYPE_PALMT5) -#else -# define machine_is_palmt5() (0) -#endif - -#ifdef CONFIG_MACH_PALMTC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTC -# endif -# define machine_is_palmtc() (machine_arch_type == MACH_TYPE_PALMTC) -#else -# define machine_is_palmtc() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_APOLLON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_APOLLON -# endif -# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) -#else -# define machine_is_omap_apollon() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030EVB -# endif -# define machine_is_mxc30030evb() (machine_arch_type == MACH_TYPE_MXC30030EVB) -#else -# define machine_is_mxc30030evb() (0) -#endif - -#ifdef CONFIG_MACH_REA_2D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA_2D -# endif -# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D) -#else -# define machine_is_rea_cpu2() (0) -#endif - -#ifdef CONFIG_MACH_TI3E524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI3E524 -# endif -# define machine_is_eti3e524() (machine_arch_type == MACH_TYPE_TI3E524) -#else -# define machine_is_eti3e524() (0) -#endif - -#ifdef CONFIG_MACH_ATEB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATEB9200 -# endif -# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) -#else -# define machine_is_ateb9200() (0) -#endif - -#ifdef CONFIG_MACH_AUCKLAND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUCKLAND -# endif -# define machine_is_auckland() (machine_arch_type == MACH_TYPE_AUCKLAND) -#else -# define machine_is_auckland() (0) -#endif - -#ifdef CONFIG_MACH_AK3320M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AK3320M -# endif -# define machine_is_ak3220m() (machine_arch_type == MACH_TYPE_AK3320M) -#else -# define machine_is_ak3220m() (0) -#endif - -#ifdef CONFIG_MACH_DURAMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DURAMAX -# endif -# define machine_is_duramax() (machine_arch_type == MACH_TYPE_DURAMAX) -#else -# define machine_is_duramax() (0) -#endif - -#ifdef CONFIG_MACH_N35 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N35 -# endif -# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) -#else -# define machine_is_n35() (0) -#endif - -#ifdef CONFIG_MACH_PRONGHORN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRONGHORN -# endif -# define machine_is_pronghorn() (machine_arch_type == MACH_TYPE_PRONGHORN) -#else -# define machine_is_pronghorn() (0) -#endif - -#ifdef CONFIG_MACH_FUNDY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUNDY -# endif -# define machine_is_fundy() (machine_arch_type == MACH_TYPE_FUNDY) -#else -# define machine_is_fundy() (0) -#endif - -#ifdef CONFIG_MACH_LOGICPD_PXA270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 -# endif -# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) -#else -# define machine_is_logicpd_pxa270() (0) -#endif - -#ifdef CONFIG_MACH_CPU777 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPU777 -# endif -# define machine_is_cpu777() (machine_arch_type == MACH_TYPE_CPU777) -#else -# define machine_is_cpu777() (0) -#endif - -#ifdef CONFIG_MACH_SIMICON9201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMICON9201 -# endif -# define machine_is_simicon9201() (machine_arch_type == MACH_TYPE_SIMICON9201) -#else -# define machine_is_simicon9201() (0) -#endif - -#ifdef CONFIG_MACH_LEAP2_HPM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEAP2_HPM -# endif -# define machine_is_leap2_hpm() (machine_arch_type == MACH_TYPE_LEAP2_HPM) -#else -# define machine_is_leap2_hpm() (0) -#endif - -#ifdef CONFIG_MACH_CM922TXA10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM922TXA10 -# endif -# define machine_is_cm922txa10() (machine_arch_type == MACH_TYPE_CM922TXA10) -#else -# define machine_is_cm922txa10() (0) -#endif - -#ifdef CONFIG_MACH_PXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA -# endif -# define machine_is_sandgate() (machine_arch_type == MACH_TYPE_PXA) -#else -# define machine_is_sandgate() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2 -# endif -# define machine_is_sandgate2() (machine_arch_type == MACH_TYPE_SANDGATE2) -#else -# define machine_is_sandgate2() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2G -# endif -# define machine_is_sandgate2g() (machine_arch_type == MACH_TYPE_SANDGATE2G) -#else -# define machine_is_sandgate2g() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2P -# endif -# define machine_is_sandgate2p() (machine_arch_type == MACH_TYPE_SANDGATE2P) -#else -# define machine_is_sandgate2p() (0) -#endif - -#ifdef CONFIG_MACH_FRED_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRED_JACK -# endif -# define machine_is_fred_jack() (machine_arch_type == MACH_TYPE_FRED_JACK) -#else -# define machine_is_fred_jack() (0) -#endif - -#ifdef CONFIG_MACH_TTG_COLOR1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TTG_COLOR1 -# endif -# define machine_is_ttg_color1() (machine_arch_type == MACH_TYPE_TTG_COLOR1) -#else -# define machine_is_ttg_color1() (0) -#endif - -#ifdef CONFIG_MACH_NXEB500HMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXEB500HMI -# endif -# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) -#else -# define machine_is_nxeb500hmi() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU8 -# endif -# define machine_is_netdcu8() (machine_arch_type == MACH_TYPE_NETDCU8) -#else -# define machine_is_netdcu8() (0) -#endif - -#ifdef CONFIG_MACH_NG_FVX538 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NG_FVX538 -# endif -# define machine_is_ng_fvx538() (machine_arch_type == MACH_TYPE_NG_FVX538) -#else -# define machine_is_ng_fvx538() (0) -#endif - -#ifdef CONFIG_MACH_NG_FVS338 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NG_FVS338 -# endif -# define machine_is_ng_fvs338() (machine_arch_type == MACH_TYPE_NG_FVS338) -#else -# define machine_is_ng_fvs338() (0) -#endif - -#ifdef CONFIG_MACH_PNX4103 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4103 -# endif -# define machine_is_pnx4103() (machine_arch_type == MACH_TYPE_PNX4103) -#else -# define machine_is_pnx4103() (0) -#endif - -#ifdef CONFIG_MACH_HESDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HESDB -# endif -# define machine_is_hesdb() (machine_arch_type == MACH_TYPE_HESDB) -#else -# define machine_is_hesdb() (0) -#endif - -#ifdef CONFIG_MACH_XSILO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSILO -# endif -# define machine_is_xsilo() (machine_arch_type == MACH_TYPE_XSILO) -#else -# define machine_is_xsilo() (0) -#endif - -#ifdef CONFIG_MACH_ESPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESPRESSO -# endif -# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) -#else -# define machine_is_espresso() (0) -#endif - -#ifdef CONFIG_MACH_EMLC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMLC -# endif -# define machine_is_emlc() (machine_arch_type == MACH_TYPE_EMLC) -#else -# define machine_is_emlc() (0) -#endif - -#ifdef CONFIG_MACH_SISTERON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SISTERON -# endif -# define machine_is_sisteron() (machine_arch_type == MACH_TYPE_SISTERON) -#else -# define machine_is_sisteron() (0) -#endif - -#ifdef CONFIG_MACH_RX1950 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RX1950 -# endif -# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) -#else -# define machine_is_rx1950() (0) -#endif - -#ifdef CONFIG_MACH_TSC_VENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TSC_VENUS -# endif -# define machine_is_tsc_venus() (machine_arch_type == MACH_TYPE_TSC_VENUS) -#else -# define machine_is_tsc_venus() (0) -#endif - -#ifdef CONFIG_MACH_DS101J -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS101J -# endif -# define machine_is_ds101j() (machine_arch_type == MACH_TYPE_DS101J) -#else -# define machine_is_ds101j() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030ADS -# endif -# define machine_is_mxc30030ads() (machine_arch_type == MACH_TYPE_MXC30030ADS) -#else -# define machine_is_mxc30030ads() (0) -#endif - -#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_WIMAXSOC -# endif -# define machine_is_fujitsu_wimaxsoc() (machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC) -#else -# define machine_is_fujitsu_wimaxsoc() (0) -#endif - -#ifdef CONFIG_MACH_DUALPCMODEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DUALPCMODEM -# endif -# define machine_is_dualpcmodem() (machine_arch_type == MACH_TYPE_DUALPCMODEM) -#else -# define machine_is_dualpcmodem() (0) -#endif - -#ifdef CONFIG_MACH_GESBC9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC9312 -# endif -# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) -#else -# define machine_is_gesbc9312() (0) -#endif - -#ifdef CONFIG_MACH_HTCAPACHE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCAPACHE -# endif -# define machine_is_htcapache() (machine_arch_type == MACH_TYPE_HTCAPACHE) -#else -# define machine_is_htcapache() (0) -#endif - -#ifdef CONFIG_MACH_IXDP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP435 -# endif -# define machine_is_ixdp435() (machine_arch_type == MACH_TYPE_IXDP435) -#else -# define machine_is_ixdp435() (0) -#endif - -#ifdef CONFIG_MACH_CATPROVT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATPROVT100 -# endif -# define machine_is_catprovt100() (machine_arch_type == MACH_TYPE_CATPROVT100) -#else -# define machine_is_catprovt100() (0) -#endif - -#ifdef CONFIG_MACH_PICOTUX1XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOTUX1XX -# endif -# define machine_is_picotux1xx() (machine_arch_type == MACH_TYPE_PICOTUX1XX) -#else -# define machine_is_picotux1xx() (0) -#endif - -#ifdef CONFIG_MACH_PICOTUX2XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOTUX2XX -# endif -# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX) -#else -# define machine_is_picotux2xx() (0) -#endif - -#ifdef CONFIG_MACH_DSMG600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSMG600 -# endif -# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600) -#else -# define machine_is_dsmg600() (0) -#endif - -#ifdef CONFIG_MACH_EMPC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPC2 -# endif -# define machine_is_empc2() (machine_arch_type == MACH_TYPE_EMPC2) -#else -# define machine_is_empc2() (0) -#endif - -#ifdef CONFIG_MACH_VENTURA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENTURA -# endif -# define machine_is_ventura() (machine_arch_type == MACH_TYPE_VENTURA) -#else -# define machine_is_ventura() (0) -#endif - -#ifdef CONFIG_MACH_PHIDGET_SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHIDGET_SBC -# endif -# define machine_is_phidget_sbc() (machine_arch_type == MACH_TYPE_PHIDGET_SBC) -#else -# define machine_is_phidget_sbc() (0) -#endif - -#ifdef CONFIG_MACH_IJ3K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IJ3K -# endif -# define machine_is_ij3k() (machine_arch_type == MACH_TYPE_IJ3K) -#else -# define machine_is_ij3k() (0) -#endif - -#ifdef CONFIG_MACH_PISGAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PISGAH -# endif -# define machine_is_pisgah() (machine_arch_type == MACH_TYPE_PISGAH) -#else -# define machine_is_pisgah() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_FSAMPLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE -# endif -# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE) -#else -# define machine_is_omap_fsample() (0) -#endif - -#ifdef CONFIG_MACH_SG720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG720 -# endif -# define machine_is_sg720() (machine_arch_type == MACH_TYPE_SG720) -#else -# define machine_is_sg720() (0) -#endif - -#ifdef CONFIG_MACH_REDFOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REDFOX -# endif -# define machine_is_redfox() (machine_arch_type == MACH_TYPE_REDFOX) -#else -# define machine_is_redfox() (0) -#endif - -#ifdef CONFIG_MACH_MYSH_EP9315_1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MYSH_EP9315_1 -# endif -# define machine_is_mysh_ep9315_1() (machine_arch_type == MACH_TYPE_MYSH_EP9315_1) -#else -# define machine_is_mysh_ep9315_1() (0) -#endif - -#ifdef CONFIG_MACH_TPF106 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPF106 -# endif -# define machine_is_tpf106() (machine_arch_type == MACH_TYPE_TPF106) -#else -# define machine_is_tpf106() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200KG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200KG -# endif -# define machine_is_at91rm9200kg() (machine_arch_type == MACH_TYPE_AT91RM9200KG) -#else -# define machine_is_at91rm9200kg() (0) -#endif - -#ifdef CONFIG_MACH_SLEDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLEDB -# endif -# define machine_is_rcmt2() (machine_arch_type == MACH_TYPE_SLEDB) -#else -# define machine_is_rcmt2() (0) -#endif - -#ifdef CONFIG_MACH_ONTRACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ONTRACK -# endif -# define machine_is_ontrack() (machine_arch_type == MACH_TYPE_ONTRACK) -#else -# define machine_is_ontrack() (0) -#endif - -#ifdef CONFIG_MACH_PM1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM1200 -# endif -# define machine_is_pm1200() (machine_arch_type == MACH_TYPE_PM1200) -#else -# define machine_is_pm1200() (0) -#endif - -#ifdef CONFIG_MACH_ESS24XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESS24XXX -# endif -# define machine_is_ess24562() (machine_arch_type == MACH_TYPE_ESS24XXX) -#else -# define machine_is_ess24562() (0) -#endif - -#ifdef CONFIG_MACH_COREMP7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COREMP7 -# endif -# define machine_is_coremp7() (machine_arch_type == MACH_TYPE_COREMP7) -#else -# define machine_is_coremp7() (0) -#endif - -#ifdef CONFIG_MACH_NEXCODER_6446 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXCODER_6446 -# endif -# define machine_is_nexcoder_6446() (machine_arch_type == MACH_TYPE_NEXCODER_6446) -#else -# define machine_is_nexcoder_6446() (0) -#endif - -#ifdef CONFIG_MACH_STVC8380 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STVC8380 -# endif -# define machine_is_stvc8380() (machine_arch_type == MACH_TYPE_STVC8380) -#else -# define machine_is_stvc8380() (0) -#endif - -#ifdef CONFIG_MACH_TEKLYNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEKLYNX -# endif -# define machine_is_teklynx() (machine_arch_type == MACH_TYPE_TEKLYNX) -#else -# define machine_is_teklynx() (0) -#endif - -#ifdef CONFIG_MACH_CARBONADO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARBONADO -# endif -# define machine_is_carbonado() (machine_arch_type == MACH_TYPE_CARBONADO) -#else -# define machine_is_carbonado() (0) -#endif - -#ifdef CONFIG_MACH_SYSMOS_MP730 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYSMOS_MP730 -# endif -# define machine_is_sysmos_mp730() (machine_arch_type == MACH_TYPE_SYSMOS_MP730) -#else -# define machine_is_sysmos_mp730() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_CL15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_CL15 -# endif -# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15) -#else -# define machine_is_snapper_cl15() (0) -#endif - -#ifdef CONFIG_MACH_PGIGIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PGIGIM -# endif -# define machine_is_pgigim() (machine_arch_type == MACH_TYPE_PGIGIM) -#else -# define machine_is_pgigim() (0) -#endif - -#ifdef CONFIG_MACH_PTX9160P2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTX9160P2 -# endif -# define machine_is_ptx9160p2() (machine_arch_type == MACH_TYPE_PTX9160P2) -#else -# define machine_is_ptx9160p2() (0) -#endif - -#ifdef CONFIG_MACH_DCORE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DCORE1 -# endif -# define machine_is_dcore1() (machine_arch_type == MACH_TYPE_DCORE1) -#else -# define machine_is_dcore1() (0) -#endif - -#ifdef CONFIG_MACH_VICTORPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VICTORPXA -# endif -# define machine_is_victorpxa() (machine_arch_type == MACH_TYPE_VICTORPXA) -#else -# define machine_is_victorpxa() (0) -#endif - -#ifdef CONFIG_MACH_MX2DTB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2DTB -# endif -# define machine_is_mx2dtb() (machine_arch_type == MACH_TYPE_MX2DTB) -#else -# define machine_is_mx2dtb() (0) -#endif - -#ifdef CONFIG_MACH_PXA_IREX_ER0100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IREX_ER0100 -# endif -# define machine_is_pxa_irex_er0100() (machine_arch_type == MACH_TYPE_PXA_IREX_ER0100) -#else -# define machine_is_pxa_irex_er0100() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMZ71 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMZ71 -# endif -# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71) -#else -# define machine_is_omap_palmz71() (0) -#endif - -#ifdef CONFIG_MACH_BARTEC_DEG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BARTEC_DEG -# endif -# define machine_is_bartec_deg() (machine_arch_type == MACH_TYPE_BARTEC_DEG) -#else -# define machine_is_bartec_deg() (0) -#endif - -#ifdef CONFIG_MACH_HW50251 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW50251 -# endif -# define machine_is_hw50251() (machine_arch_type == MACH_TYPE_HW50251) -#else -# define machine_is_hw50251() (0) -#endif - -#ifdef CONFIG_MACH_IBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IBOX -# endif -# define machine_is_ibox() (machine_arch_type == MACH_TYPE_IBOX) -#else -# define machine_is_ibox() (0) -#endif - -#ifdef CONFIG_MACH_ATLASLH7A404 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLASLH7A404 -# endif -# define machine_is_atlaslh7a404() (machine_arch_type == MACH_TYPE_ATLASLH7A404) -#else -# define machine_is_atlaslh7a404() (0) -#endif - -#ifdef CONFIG_MACH_PT2026 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT2026 -# endif -# define machine_is_pt2026() (machine_arch_type == MACH_TYPE_PT2026) -#else -# define machine_is_pt2026() (0) -#endif - -#ifdef CONFIG_MACH_HTCALPINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCALPINE -# endif -# define machine_is_htcalpine() (machine_arch_type == MACH_TYPE_HTCALPINE) -#else -# define machine_is_htcalpine() (0) -#endif - -#ifdef CONFIG_MACH_BARTEC_VTU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BARTEC_VTU -# endif -# define machine_is_bartec_vtu() (machine_arch_type == MACH_TYPE_BARTEC_VTU) -#else -# define machine_is_bartec_vtu() (0) -#endif - -#ifdef CONFIG_MACH_VCOREII -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCOREII -# endif -# define machine_is_vcoreii() (machine_arch_type == MACH_TYPE_VCOREII) -#else -# define machine_is_vcoreii() (0) -#endif - -#ifdef CONFIG_MACH_PDNB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDNB3 -# endif -# define machine_is_pdnb3() (machine_arch_type == MACH_TYPE_PDNB3) -#else -# define machine_is_pdnb3() (0) -#endif - -#ifdef CONFIG_MACH_HTCBEETLES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCBEETLES -# endif -# define machine_is_htcbeetles() (machine_arch_type == MACH_TYPE_HTCBEETLES) -#else -# define machine_is_htcbeetles() (0) -#endif - -#ifdef CONFIG_MACH_S3C6400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C6400 -# endif -# define machine_is_s3c6400() (machine_arch_type == MACH_TYPE_S3C6400) -#else -# define machine_is_s3c6400() (0) -#endif - -#ifdef CONFIG_MACH_S3C2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2443 -# endif -# define machine_is_s3c2443() (machine_arch_type == MACH_TYPE_S3C2443) -#else -# define machine_is_s3c2443() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_LDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_LDK -# endif -# define machine_is_omap_ldk() (machine_arch_type == MACH_TYPE_OMAP_LDK) -#else -# define machine_is_omap_ldk() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2460 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2460 -# endif -# define machine_is_smdk2460() (machine_arch_type == MACH_TYPE_SMDK2460) -#else -# define machine_is_smdk2460() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2440 -# endif -# define machine_is_smdk2440() (machine_arch_type == MACH_TYPE_SMDK2440) -#else -# define machine_is_smdk2440() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2412 -# endif -# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412) -#else -# define machine_is_smdk2412() (0) -#endif - -#ifdef CONFIG_MACH_WEBBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBBOX -# endif -# define machine_is_webbox() (machine_arch_type == MACH_TYPE_WEBBOX) -#else -# define machine_is_webbox() (0) -#endif - -#ifdef CONFIG_MACH_CWWNDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWWNDP -# endif -# define machine_is_cwwndp() (machine_arch_type == MACH_TYPE_CWWNDP) -#else -# define machine_is_cwwndp() (0) -#endif - -#ifdef CONFIG_MACH_DRAGON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DRAGON -# endif -# define machine_is_i839() (machine_arch_type == MACH_TYPE_DRAGON) -#else -# define machine_is_i839() (0) -#endif - -#ifdef CONFIG_MACH_OPENDO_CPU_BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENDO_CPU_BOARD -# endif -# define machine_is_opendo_cpu_board() (machine_arch_type == MACH_TYPE_OPENDO_CPU_BOARD) -#else -# define machine_is_opendo_cpu_board() (0) -#endif - -#ifdef CONFIG_MACH_CCM2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCM2200 -# endif -# define machine_is_ccm2200() (machine_arch_type == MACH_TYPE_CCM2200) -#else -# define machine_is_ccm2200() (0) -#endif - -#ifdef CONFIG_MACH_ETWARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETWARM -# endif -# define machine_is_etwarm() (machine_arch_type == MACH_TYPE_ETWARM) -#else -# define machine_is_etwarm() (0) -#endif - -#ifdef CONFIG_MACH_M93030 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M93030 -# endif -# define machine_is_m93030() (machine_arch_type == MACH_TYPE_M93030) -#else -# define machine_is_m93030() (0) -#endif - -#ifdef CONFIG_MACH_CC7U -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC7U -# endif -# define machine_is_cc7u() (machine_arch_type == MACH_TYPE_CC7U) -#else -# define machine_is_cc7u() (0) -#endif - -#ifdef CONFIG_MACH_MTT_RANGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTT_RANGER -# endif -# define machine_is_mtt_ranger() (machine_arch_type == MACH_TYPE_MTT_RANGER) -#else -# define machine_is_mtt_ranger() (0) -#endif - -#ifdef CONFIG_MACH_NEXUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXUS -# endif -# define machine_is_nexus() (machine_arch_type == MACH_TYPE_NEXUS) -#else -# define machine_is_nexus() (0) -#endif - -#ifdef CONFIG_MACH_DESMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DESMAN -# endif -# define machine_is_desman() (machine_arch_type == MACH_TYPE_DESMAN) -#else -# define machine_is_desman() (0) -#endif - -#ifdef CONFIG_MACH_BKDE303 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BKDE303 -# endif -# define machine_is_bkde303() (machine_arch_type == MACH_TYPE_BKDE303) -#else -# define machine_is_bkde303() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2413 -# endif -# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413) -#else -# define machine_is_smdk2413() (0) -#endif - -#ifdef CONFIG_MACH_AML_M7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M7200 -# endif -# define machine_is_aml_m7200() (machine_arch_type == MACH_TYPE_AML_M7200) -#else -# define machine_is_aml_m7200() (0) -#endif - -#ifdef CONFIG_MACH_AML_M5900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M5900 -# endif -# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900) -#else -# define machine_is_aml_m5900() (0) -#endif - -#ifdef CONFIG_MACH_SG640 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG640 -# endif -# define machine_is_sg640() (machine_arch_type == MACH_TYPE_SG640) -#else -# define machine_is_sg640() (0) -#endif - -#ifdef CONFIG_MACH_EDG79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDG79524 -# endif -# define machine_is_edg79524() (machine_arch_type == MACH_TYPE_EDG79524) -#else -# define machine_is_edg79524() (0) -#endif - -#ifdef CONFIG_MACH_AI2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AI2410 -# endif -# define machine_is_ai2410() (machine_arch_type == MACH_TYPE_AI2410) -#else -# define machine_is_ai2410() (0) -#endif - -#ifdef CONFIG_MACH_IXP465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP465 -# endif -# define machine_is_ixp465() (machine_arch_type == MACH_TYPE_IXP465) -#else -# define machine_is_ixp465() (0) -#endif - -#ifdef CONFIG_MACH_BALLOON3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLOON3 -# endif -# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) -#else -# define machine_is_balloon3() (0) -#endif - -#ifdef CONFIG_MACH_HEINS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HEINS -# endif -# define machine_is_heins() (machine_arch_type == MACH_TYPE_HEINS) -#else -# define machine_is_heins() (0) -#endif - -#ifdef CONFIG_MACH_MPLUSEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPLUSEVA -# endif -# define machine_is_mpluseva() (machine_arch_type == MACH_TYPE_MPLUSEVA) -#else -# define machine_is_mpluseva() (0) -#endif - -#ifdef CONFIG_MACH_RT042 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RT042 -# endif -# define machine_is_rt042() (machine_arch_type == MACH_TYPE_RT042) -#else -# define machine_is_rt042() (0) -#endif - -#ifdef CONFIG_MACH_CWIEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWIEM -# endif -# define machine_is_cwiem() (machine_arch_type == MACH_TYPE_CWIEM) -#else -# define machine_is_cwiem() (0) -#endif - -#ifdef CONFIG_MACH_CM_X270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X270 -# endif -# define machine_is_cm_x270() (machine_arch_type == MACH_TYPE_CM_X270) -#else -# define machine_is_cm_x270() (0) -#endif - -#ifdef CONFIG_MACH_CM_X255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X255 -# endif -# define machine_is_cm_x255() (machine_arch_type == MACH_TYPE_CM_X255) -#else -# define machine_is_cm_x255() (0) -#endif - -#ifdef CONFIG_MACH_ESH_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESH_AT91 -# endif -# define machine_is_esh_at91() (machine_arch_type == MACH_TYPE_ESH_AT91) -#else -# define machine_is_esh_at91() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE3 -# endif -# define machine_is_sandgate3() (machine_arch_type == MACH_TYPE_SANDGATE3) -#else -# define machine_is_sandgate3() (0) -#endif - -#ifdef CONFIG_MACH_PRIMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRIMO -# endif -# define machine_is_primo() (machine_arch_type == MACH_TYPE_PRIMO) -#else -# define machine_is_primo() (0) -#endif - -#ifdef CONFIG_MACH_GEMSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMSTONE -# endif -# define machine_is_gemstone() (machine_arch_type == MACH_TYPE_GEMSTONE) -#else -# define machine_is_gemstone() (0) -#endif - -#ifdef CONFIG_MACH_PRONGHORNMETRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRONGHORNMETRO -# endif -# define machine_is_pronghorn_metro() (machine_arch_type == MACH_TYPE_PRONGHORNMETRO) -#else -# define machine_is_pronghorn_metro() (0) -#endif - -#ifdef CONFIG_MACH_SIDEWINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEWINDER -# endif -# define machine_is_sidewinder() (machine_arch_type == MACH_TYPE_SIDEWINDER) -#else -# define machine_is_sidewinder() (0) -#endif - -#ifdef CONFIG_MACH_PICOMOD1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOMOD1 -# endif -# define machine_is_picomod1() (machine_arch_type == MACH_TYPE_PICOMOD1) -#else -# define machine_is_picomod1() (0) -#endif - -#ifdef CONFIG_MACH_SG590 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG590 -# endif -# define machine_is_sg590() (machine_arch_type == MACH_TYPE_SG590) -#else -# define machine_is_sg590() (0) -#endif - -#ifdef CONFIG_MACH_AKAI9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKAI9307 -# endif -# define machine_is_akai9307() (machine_arch_type == MACH_TYPE_AKAI9307) -#else -# define machine_is_akai9307() (0) -#endif - -#ifdef CONFIG_MACH_FONTAINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FONTAINE -# endif -# define machine_is_fontaine() (machine_arch_type == MACH_TYPE_FONTAINE) -#else -# define machine_is_fontaine() (0) -#endif - -#ifdef CONFIG_MACH_WOMBAT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WOMBAT -# endif -# define machine_is_wombat() (machine_arch_type == MACH_TYPE_WOMBAT) -#else -# define machine_is_wombat() (0) -#endif - -#ifdef CONFIG_MACH_ACQ300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ300 -# endif -# define machine_is_acq300() (machine_arch_type == MACH_TYPE_ACQ300) -#else -# define machine_is_acq300() (0) -#endif - -#ifdef CONFIG_MACH_MOD_270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOD_270 -# endif -# define machine_is_mod272() (machine_arch_type == MACH_TYPE_MOD_270) -#else -# define machine_is_mod272() (0) -#endif - -#ifdef CONFIG_MACH_VC0820 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC0820 -# endif -# define machine_is_vmc_vc0820() (machine_arch_type == MACH_TYPE_VC0820) -#else -# define machine_is_vmc_vc0820() (0) -#endif - -#ifdef CONFIG_MACH_ANI_AIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANI_AIM -# endif -# define machine_is_ani_aim() (machine_arch_type == MACH_TYPE_ANI_AIM) -#else -# define machine_is_ani_aim() (0) -#endif - -#ifdef CONFIG_MACH_JELLYFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JELLYFISH -# endif -# define machine_is_jellyfish() (machine_arch_type == MACH_TYPE_JELLYFISH) -#else -# define machine_is_jellyfish() (0) -#endif - -#ifdef CONFIG_MACH_AMANITA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMANITA -# endif -# define machine_is_amanita() (machine_arch_type == MACH_TYPE_AMANITA) -#else -# define machine_is_amanita() (0) -#endif - -#ifdef CONFIG_MACH_VLINK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VLINK -# endif -# define machine_is_vlink() (machine_arch_type == MACH_TYPE_VLINK) -#else -# define machine_is_vlink() (0) -#endif - -#ifdef CONFIG_MACH_DEXFLEX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEXFLEX -# endif -# define machine_is_dexflex() (machine_arch_type == MACH_TYPE_DEXFLEX) -#else -# define machine_is_dexflex() (0) -#endif - -#ifdef CONFIG_MACH_EIGEN_TTQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EIGEN_TTQ -# endif -# define machine_is_eigen_ttq() (machine_arch_type == MACH_TYPE_EIGEN_TTQ) -#else -# define machine_is_eigen_ttq() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_TITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_TITAN -# endif -# define machine_is_arcom_titan() (machine_arch_type == MACH_TYPE_ARCOM_TITAN) -#else -# define machine_is_arcom_titan() (0) -#endif - -#ifdef CONFIG_MACH_TABLA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TABLA -# endif -# define machine_is_tabla() (machine_arch_type == MACH_TYPE_TABLA) -#else -# define machine_is_tabla() (0) -#endif - -#ifdef CONFIG_MACH_MDIRAC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MDIRAC3 -# endif -# define machine_is_mdirac3() (machine_arch_type == MACH_TYPE_MDIRAC3) -#else -# define machine_is_mdirac3() (0) -#endif - -#ifdef CONFIG_MACH_MRHFBP2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MRHFBP2 -# endif -# define machine_is_mrhfbp2() (machine_arch_type == MACH_TYPE_MRHFBP2) -#else -# define machine_is_mrhfbp2() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200RB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200RB -# endif -# define machine_is_at91rm9200rb() (machine_arch_type == MACH_TYPE_AT91RM9200RB) -#else -# define machine_is_at91rm9200rb() (0) -#endif - -#ifdef CONFIG_MACH_ANI_APM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANI_APM -# endif -# define machine_is_ani_apm() (machine_arch_type == MACH_TYPE_ANI_APM) -#else -# define machine_is_ani_apm() (0) -#endif - -#ifdef CONFIG_MACH_ELLA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELLA1 -# endif -# define machine_is_ella1() (machine_arch_type == MACH_TYPE_ELLA1) -#else -# define machine_is_ella1() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_PXA27X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_PXA27X -# endif -# define machine_is_inhand_pxa27x() (machine_arch_type == MACH_TYPE_INHAND_PXA27X) -#else -# define machine_is_inhand_pxa27x() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_PXA25X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_PXA25X -# endif -# define machine_is_inhand_pxa25x() (machine_arch_type == MACH_TYPE_INHAND_PXA25X) -#else -# define machine_is_inhand_pxa25x() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_XM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_XM -# endif -# define machine_is_empos_xm() (machine_arch_type == MACH_TYPE_EMPOS_XM) -#else -# define machine_is_empos_xm() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS -# endif -# define machine_is_empos() (machine_arch_type == MACH_TYPE_EMPOS) -#else -# define machine_is_empos() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_TINY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_TINY -# endif -# define machine_is_empos_tiny() (machine_arch_type == MACH_TYPE_EMPOS_TINY) -#else -# define machine_is_empos_tiny() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_SM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_SM -# endif -# define machine_is_empos_sm() (machine_arch_type == MACH_TYPE_EMPOS_SM) -#else -# define machine_is_empos_sm() (0) -#endif - -#ifdef CONFIG_MACH_EGRET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EGRET -# endif -# define machine_is_egret() (machine_arch_type == MACH_TYPE_EGRET) -#else -# define machine_is_egret() (0) -#endif - -#ifdef CONFIG_MACH_OSTRICH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSTRICH -# endif -# define machine_is_ostrich() (machine_arch_type == MACH_TYPE_OSTRICH) -#else -# define machine_is_ostrich() (0) -#endif - -#ifdef CONFIG_MACH_N50 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N50 -# endif -# define machine_is_n50() (machine_arch_type == MACH_TYPE_N50) -#else -# define machine_is_n50() (0) -#endif - -#ifdef CONFIG_MACH_ECBAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECBAT91 -# endif -# define machine_is_ecbat91() (machine_arch_type == MACH_TYPE_ECBAT91) -#else -# define machine_is_ecbat91() (0) -#endif - -#ifdef CONFIG_MACH_STAREAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAREAST -# endif -# define machine_is_stareast() (machine_arch_type == MACH_TYPE_STAREAST) -#else -# define machine_is_stareast() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DW -# endif -# define machine_is_dspg_dw() (machine_arch_type == MACH_TYPE_DSPG_DW) -#else -# define machine_is_dspg_dw() (0) -#endif - -#ifdef CONFIG_MACH_ONEARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ONEARM -# endif -# define machine_is_onearm() (machine_arch_type == MACH_TYPE_ONEARM) -#else -# define machine_is_onearm() (0) -#endif - -#ifdef CONFIG_MACH_MRG110_6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MRG110_6 -# endif -# define machine_is_mrg110_6() (machine_arch_type == MACH_TYPE_MRG110_6) -#else -# define machine_is_mrg110_6() (0) -#endif - -#ifdef CONFIG_MACH_WRT300NV2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRT300NV2 -# endif -# define machine_is_wrt300nv2() (machine_arch_type == MACH_TYPE_WRT300NV2) -#else -# define machine_is_wrt300nv2() (0) -#endif - -#ifdef CONFIG_MACH_XM_BULVERDE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XM_BULVERDE -# endif -# define machine_is_xm_bulverde() (machine_arch_type == MACH_TYPE_XM_BULVERDE) -#else -# define machine_is_xm_bulverde() (0) -#endif - -#ifdef CONFIG_MACH_MSM6100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM6100 -# endif -# define machine_is_msm6100() (machine_arch_type == MACH_TYPE_MSM6100) -#else -# define machine_is_msm6100() (0) -#endif - -#ifdef CONFIG_MACH_ETI_B1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_B1 -# endif -# define machine_is_eti_b1() (machine_arch_type == MACH_TYPE_ETI_B1) -#else -# define machine_is_eti_b1() (0) -#endif - -#ifdef CONFIG_MACH_ZILOG_ZA9L -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZILOG_ZA9L -# endif -# define machine_is_za9l_series() (machine_arch_type == MACH_TYPE_ZILOG_ZA9L) -#else -# define machine_is_za9l_series() (0) -#endif - -#ifdef CONFIG_MACH_BIT2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIT2440 -# endif -# define machine_is_bit2440() (machine_arch_type == MACH_TYPE_BIT2440) -#else -# define machine_is_bit2440() (0) -#endif - -#ifdef CONFIG_MACH_NBI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NBI -# endif -# define machine_is_nbi() (machine_arch_type == MACH_TYPE_NBI) -#else -# define machine_is_nbi() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2443 -# endif -# define machine_is_smdk2443() (machine_arch_type == MACH_TYPE_SMDK2443) -#else -# define machine_is_smdk2443() (0) -#endif - -#ifdef CONFIG_MACH_VDAVINCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VDAVINCI -# endif -# define machine_is_vdavinci() (machine_arch_type == MACH_TYPE_VDAVINCI) -#else -# define machine_is_vdavinci() (0) -#endif - -#ifdef CONFIG_MACH_ATC6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATC6 -# endif -# define machine_is_atc6() (machine_arch_type == MACH_TYPE_ATC6) -#else -# define machine_is_atc6() (0) -#endif - -#ifdef CONFIG_MACH_MULTMDW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTMDW -# endif -# define machine_is_multmdw() (machine_arch_type == MACH_TYPE_MULTMDW) -#else -# define machine_is_multmdw() (0) -#endif - -#ifdef CONFIG_MACH_MBA2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBA2440 -# endif -# define machine_is_mba2440() (machine_arch_type == MACH_TYPE_MBA2440) -#else -# define machine_is_mba2440() (0) -#endif - -#ifdef CONFIG_MACH_ECSD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECSD -# endif -# define machine_is_ecsd() (machine_arch_type == MACH_TYPE_ECSD) -#else -# define machine_is_ecsd() (0) -#endif - -#ifdef CONFIG_MACH_PALMZ31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMZ31 -# endif -# define machine_is_palmz31() (machine_arch_type == MACH_TYPE_PALMZ31) -#else -# define machine_is_palmz31() (0) -#endif - -#ifdef CONFIG_MACH_FSG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FSG -# endif -# define machine_is_fsg() (machine_arch_type == MACH_TYPE_FSG) -#else -# define machine_is_fsg() (0) -#endif - -#ifdef CONFIG_MACH_RAZOR101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAZOR101 -# endif -# define machine_is_razor101() (machine_arch_type == MACH_TYPE_RAZOR101) -#else -# define machine_is_razor101() (0) -#endif - -#ifdef CONFIG_MACH_OPERA_TDM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPERA_TDM -# endif -# define machine_is_opera_tdm() (machine_arch_type == MACH_TYPE_OPERA_TDM) -#else -# define machine_is_opera_tdm() (0) -#endif - -#ifdef CONFIG_MACH_COMCERTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMCERTO -# endif -# define machine_is_comcerto() (machine_arch_type == MACH_TYPE_COMCERTO) -#else -# define machine_is_comcerto() (0) -#endif - -#ifdef CONFIG_MACH_TB0319 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TB0319 -# endif -# define machine_is_tb0319() (machine_arch_type == MACH_TYPE_TB0319) -#else -# define machine_is_tb0319() (0) -#endif - -#ifdef CONFIG_MACH_KWS8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KWS8000 -# endif -# define machine_is_kws8000() (machine_arch_type == MACH_TYPE_KWS8000) -#else -# define machine_is_kws8000() (0) -#endif - -#ifdef CONFIG_MACH_B2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_B2 -# endif -# define machine_is_b2() (machine_arch_type == MACH_TYPE_B2) -#else -# define machine_is_b2() (0) -#endif - -#ifdef CONFIG_MACH_LCL54 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LCL54 -# endif -# define machine_is_lcl54() (machine_arch_type == MACH_TYPE_LCL54) -#else -# define machine_is_lcl54() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260EK -# endif -# define machine_is_at91sam9260ek() (machine_arch_type == MACH_TYPE_AT91SAM9260EK) -#else -# define machine_is_at91sam9260ek() (0) -#endif - -#ifdef CONFIG_MACH_GLANTANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GLANTANK -# endif -# define machine_is_glantank() (machine_arch_type == MACH_TYPE_GLANTANK) -#else -# define machine_is_glantank() (0) -#endif - -#ifdef CONFIG_MACH_N2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N2100 -# endif -# define machine_is_n2100() (machine_arch_type == MACH_TYPE_N2100) -#else -# define machine_is_n2100() (0) -#endif - -#ifdef CONFIG_MACH_N4100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N4100 -# endif -# define machine_is_n4100() (machine_arch_type == MACH_TYPE_N4100) -#else -# define machine_is_n4100() (0) -#endif - -#ifdef CONFIG_MACH_VERTICAL_RSC4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERTICAL_RSC4 -# endif -# define machine_is_rsc4() (machine_arch_type == MACH_TYPE_VERTICAL_RSC4) -#else -# define machine_is_rsc4() (0) -#endif - -#ifdef CONFIG_MACH_SG8100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG8100 -# endif -# define machine_is_sg8100() (machine_arch_type == MACH_TYPE_SG8100) -#else -# define machine_is_sg8100() (0) -#endif - -#ifdef CONFIG_MACH_IM42XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IM42XX -# endif -# define machine_is_im42xx() (machine_arch_type == MACH_TYPE_IM42XX) -#else -# define machine_is_im42xx() (0) -#endif - -#ifdef CONFIG_MACH_FTXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FTXX -# endif -# define machine_is_ftxx() (machine_arch_type == MACH_TYPE_FTXX) -#else -# define machine_is_ftxx() (0) -#endif - -#ifdef CONFIG_MACH_LWFUSION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LWFUSION -# endif -# define machine_is_lwfusion() (machine_arch_type == MACH_TYPE_LWFUSION) -#else -# define machine_is_lwfusion() (0) -#endif - -#ifdef CONFIG_MACH_QT2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QT2410 -# endif -# define machine_is_qt2410() (machine_arch_type == MACH_TYPE_QT2410) -#else -# define machine_is_qt2410() (0) -#endif - -#ifdef CONFIG_MACH_KIXRP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXRP435 -# endif -# define machine_is_kixrp435() (machine_arch_type == MACH_TYPE_KIXRP435) -#else -# define machine_is_kixrp435() (0) -#endif - -#ifdef CONFIG_MACH_CCW9C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9C -# endif -# define machine_is_ccw9c() (machine_arch_type == MACH_TYPE_CCW9C) -#else -# define machine_is_ccw9c() (0) -#endif - -#ifdef CONFIG_MACH_DABHS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DABHS -# endif -# define machine_is_dabhs() (machine_arch_type == MACH_TYPE_DABHS) -#else -# define machine_is_dabhs() (0) -#endif - -#ifdef CONFIG_MACH_GZMX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GZMX -# endif -# define machine_is_gzmx() (machine_arch_type == MACH_TYPE_GZMX) -#else -# define machine_is_gzmx() (0) -#endif - -#ifdef CONFIG_MACH_IPNW100AP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPNW100AP -# endif -# define machine_is_ipnw100ap() (machine_arch_type == MACH_TYPE_IPNW100AP) -#else -# define machine_is_ipnw100ap() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360DEV -# endif -# define machine_is_cc9p9360dev() (machine_arch_type == MACH_TYPE_CC9P9360DEV) -#else -# define machine_is_cc9p9360dev() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9750DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9750DEV -# endif -# define machine_is_cc9p9750dev() (machine_arch_type == MACH_TYPE_CC9P9750DEV) -#else -# define machine_is_cc9p9750dev() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360VAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360VAL -# endif -# define machine_is_cc9p9360val() (machine_arch_type == MACH_TYPE_CC9P9360VAL) -#else -# define machine_is_cc9p9360val() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9750VAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9750VAL -# endif -# define machine_is_cc9p9750val() (machine_arch_type == MACH_TYPE_CC9P9750VAL) -#else -# define machine_is_cc9p9750val() (0) -#endif - -#ifdef CONFIG_MACH_NX70V -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX70V -# endif -# define machine_is_nx70v() (machine_arch_type == MACH_TYPE_NX70V) -#else -# define machine_is_nx70v() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200DF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200DF -# endif -# define machine_is_at91rm9200df() (machine_arch_type == MACH_TYPE_AT91RM9200DF) -#else -# define machine_is_at91rm9200df() (0) -#endif - -#ifdef CONFIG_MACH_SE_PILOT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE_PILOT2 -# endif -# define machine_is_se_pilot2() (machine_arch_type == MACH_TYPE_SE_PILOT2) -#else -# define machine_is_se_pilot2() (0) -#endif - -#ifdef CONFIG_MACH_MTCN_T800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTCN_T800 -# endif -# define machine_is_mtcn_t800() (machine_arch_type == MACH_TYPE_MTCN_T800) -#else -# define machine_is_mtcn_t800() (0) -#endif - -#ifdef CONFIG_MACH_VCMX212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCMX212 -# endif -# define machine_is_vcmx212() (machine_arch_type == MACH_TYPE_VCMX212) -#else -# define machine_is_vcmx212() (0) -#endif - -#ifdef CONFIG_MACH_LYNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LYNX -# endif -# define machine_is_lynx() (machine_arch_type == MACH_TYPE_LYNX) -#else -# define machine_is_lynx() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260ID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260ID -# endif -# define machine_is_at91sam9260id() (machine_arch_type == MACH_TYPE_AT91SAM9260ID) -#else -# define machine_is_at91sam9260id() (0) -#endif - -#ifdef CONFIG_MACH_HW86052 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW86052 -# endif -# define machine_is_hw86052() (machine_arch_type == MACH_TYPE_HW86052) -#else -# define machine_is_hw86052() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI3 -# endif -# define machine_is_pilz_pmi3() (machine_arch_type == MACH_TYPE_PILZ_PMI3) -#else -# define machine_is_pilz_pmi3() (0) -#endif - -#ifdef CONFIG_MACH_EDB9302A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9302A -# endif -# define machine_is_edb9302a() (machine_arch_type == MACH_TYPE_EDB9302A) -#else -# define machine_is_edb9302a() (0) -#endif - -#ifdef CONFIG_MACH_EDB9307A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9307A -# endif -# define machine_is_edb9307a() (machine_arch_type == MACH_TYPE_EDB9307A) -#else -# define machine_is_edb9307a() (0) -#endif - -#ifdef CONFIG_MACH_CT_DFS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT_DFS -# endif -# define machine_is_ct_dfs() (machine_arch_type == MACH_TYPE_CT_DFS) -#else -# define machine_is_ct_dfs() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI4 -# endif -# define machine_is_pilz_pmi4() (machine_arch_type == MACH_TYPE_PILZ_PMI4) -#else -# define machine_is_pilz_pmi4() (0) -#endif - -#ifdef CONFIG_MACH_XCEEDNP_IXP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XCEEDNP_IXP -# endif -# define machine_is_xceednp_ixp() (machine_arch_type == MACH_TYPE_XCEEDNP_IXP) -#else -# define machine_is_xceednp_ixp() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2442B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2442B -# endif -# define machine_is_smdk2442b() (machine_arch_type == MACH_TYPE_SMDK2442B) -#else -# define machine_is_smdk2442b() (0) -#endif - -#ifdef CONFIG_MACH_XNODE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XNODE -# endif -# define machine_is_xnode() (machine_arch_type == MACH_TYPE_XNODE) -#else -# define machine_is_xnode() (0) -#endif - -#ifdef CONFIG_MACH_AIDX270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AIDX270 -# endif -# define machine_is_aidx270() (machine_arch_type == MACH_TYPE_AIDX270) -#else -# define machine_is_aidx270() (0) -#endif - -#ifdef CONFIG_MACH_REMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REMA -# endif -# define machine_is_rema() (machine_arch_type == MACH_TYPE_REMA) -#else -# define machine_is_rema() (0) -#endif - -#ifdef CONFIG_MACH_BPS1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BPS1000 -# endif -# define machine_is_bps1000() (machine_arch_type == MACH_TYPE_BPS1000) -#else -# define machine_is_bps1000() (0) -#endif - -#ifdef CONFIG_MACH_HW90350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90350 -# endif -# define machine_is_hw90350() (machine_arch_type == MACH_TYPE_HW90350) -#else -# define machine_is_hw90350() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_3430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_3430SDP -# endif -# define machine_is_omap_3430sdp() (machine_arch_type == MACH_TYPE_OMAP_3430SDP) -#else -# define machine_is_omap_3430sdp() (0) -#endif - -#ifdef CONFIG_MACH_BLUETOUCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUETOUCH -# endif -# define machine_is_bluetouch() (machine_arch_type == MACH_TYPE_BLUETOUCH) -#else -# define machine_is_bluetouch() (0) -#endif - -#ifdef CONFIG_MACH_VSTMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VSTMS -# endif -# define machine_is_vstms() (machine_arch_type == MACH_TYPE_VSTMS) -#else -# define machine_is_vstms() (0) -#endif - -#ifdef CONFIG_MACH_XSBASE270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSBASE270 -# endif -# define machine_is_xsbase270() (machine_arch_type == MACH_TYPE_XSBASE270) -#else -# define machine_is_xsbase270() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260EK_CN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260EK_CN -# endif -# define machine_is_at91sam9260ek_cn() (machine_arch_type == MACH_TYPE_AT91SAM9260EK_CN) -#else -# define machine_is_at91sam9260ek_cn() (0) -#endif - -#ifdef CONFIG_MACH_ADSTURBOXB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSTURBOXB -# endif -# define machine_is_adsturboxb() (machine_arch_type == MACH_TYPE_ADSTURBOXB) -#else -# define machine_is_adsturboxb() (0) -#endif - -#ifdef CONFIG_MACH_OTI4110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTI4110 -# endif -# define machine_is_oti4110() (machine_arch_type == MACH_TYPE_OTI4110) -#else -# define machine_is_oti4110() (0) -#endif - -#ifdef CONFIG_MACH_HME_PXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HME_PXA -# endif -# define machine_is_hme_pxa() (machine_arch_type == MACH_TYPE_HME_PXA) -#else -# define machine_is_hme_pxa() (0) -#endif - -#ifdef CONFIG_MACH_DEISTERDCA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTERDCA -# endif -# define machine_is_deisterdca() (machine_arch_type == MACH_TYPE_DEISTERDCA) -#else -# define machine_is_deisterdca() (0) -#endif - -#ifdef CONFIG_MACH_CES_SSEM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CES_SSEM2 -# endif -# define machine_is_ces_ssem2() (machine_arch_type == MACH_TYPE_CES_SSEM2) -#else -# define machine_is_ces_ssem2() (0) -#endif - -#ifdef CONFIG_MACH_CES_MTR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CES_MTR -# endif -# define machine_is_ces_mtr() (machine_arch_type == MACH_TYPE_CES_MTR) -#else -# define machine_is_ces_mtr() (0) -#endif - -#ifdef CONFIG_MACH_TDS_AVNG_SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TDS_AVNG_SBC -# endif -# define machine_is_tds_avng_sbc() (machine_arch_type == MACH_TYPE_TDS_AVNG_SBC) -#else -# define machine_is_tds_avng_sbc() (0) -#endif - -#ifdef CONFIG_MACH_EVEREST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVEREST -# endif -# define machine_is_everest() (machine_arch_type == MACH_TYPE_EVEREST) -#else -# define machine_is_everest() (0) -#endif - -#ifdef CONFIG_MACH_PNX4010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4010 -# endif -# define machine_is_pnx4010() (machine_arch_type == MACH_TYPE_PNX4010) -#else -# define machine_is_pnx4010() (0) -#endif - -#ifdef CONFIG_MACH_OXNAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OXNAS -# endif -# define machine_is_oxnas() (machine_arch_type == MACH_TYPE_OXNAS) -#else -# define machine_is_oxnas() (0) -#endif - -#ifdef CONFIG_MACH_FIORI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FIORI -# endif -# define machine_is_fiori() (machine_arch_type == MACH_TYPE_FIORI) -#else -# define machine_is_fiori() (0) -#endif - -#ifdef CONFIG_MACH_ML1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML1200 -# endif -# define machine_is_ml1200() (machine_arch_type == MACH_TYPE_ML1200) -#else -# define machine_is_ml1200() (0) -#endif - -#ifdef CONFIG_MACH_PECOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PECOS -# endif -# define machine_is_pecos() (machine_arch_type == MACH_TYPE_PECOS) -#else -# define machine_is_pecos() (0) -#endif - -#ifdef CONFIG_MACH_NB2XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NB2XXX -# endif -# define machine_is_nb2xxx() (machine_arch_type == MACH_TYPE_NB2XXX) -#else -# define machine_is_nb2xxx() (0) -#endif - -#ifdef CONFIG_MACH_HW6900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW6900 -# endif -# define machine_is_hw6900() (machine_arch_type == MACH_TYPE_HW6900) -#else -# define machine_is_hw6900() (0) -#endif - -#ifdef CONFIG_MACH_CDCS_QUOLL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDCS_QUOLL -# endif -# define machine_is_cdcs_quoll() (machine_arch_type == MACH_TYPE_CDCS_QUOLL) -#else -# define machine_is_cdcs_quoll() (0) -#endif - -#ifdef CONFIG_MACH_QUICKSILVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUICKSILVER -# endif -# define machine_is_quicksilver() (machine_arch_type == MACH_TYPE_QUICKSILVER) -#else -# define machine_is_quicksilver() (0) -#endif - -#ifdef CONFIG_MACH_UPLAT926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UPLAT926 -# endif -# define machine_is_uplat926() (machine_arch_type == MACH_TYPE_UPLAT926) -#else -# define machine_is_uplat926() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410_THOMAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410_THOMAS -# endif -# define machine_is_dep2410_dep2410() (machine_arch_type == MACH_TYPE_DEP2410_THOMAS) -#else -# define machine_is_dep2410_dep2410() (0) -#endif - -#ifdef CONFIG_MACH_DTK2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DTK2410 -# endif -# define machine_is_dtk2410() (machine_arch_type == MACH_TYPE_DTK2410) -#else -# define machine_is_dtk2410() (0) -#endif - -#ifdef CONFIG_MACH_CHILI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHILI -# endif -# define machine_is_chili() (machine_arch_type == MACH_TYPE_CHILI) -#else -# define machine_is_chili() (0) -#endif - -#ifdef CONFIG_MACH_DEMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEMETER -# endif -# define machine_is_demeter() (machine_arch_type == MACH_TYPE_DEMETER) -#else -# define machine_is_demeter() (0) -#endif - -#ifdef CONFIG_MACH_DIONYSUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIONYSUS -# endif -# define machine_is_dionysus() (machine_arch_type == MACH_TYPE_DIONYSUS) -#else -# define machine_is_dionysus() (0) -#endif - -#ifdef CONFIG_MACH_AS352X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS352X -# endif -# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) -#else -# define machine_is_as352x() (0) -#endif - -#ifdef CONFIG_MACH_SERVICE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SERVICE -# endif -# define machine_is_service() (machine_arch_type == MACH_TYPE_SERVICE) -#else -# define machine_is_service() (0) -#endif - -#ifdef CONFIG_MACH_CS_E9301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS_E9301 -# endif -# define machine_is_cs_e9301() (machine_arch_type == MACH_TYPE_CS_E9301) -#else -# define machine_is_cs_e9301() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9M -# endif -# define machine_is_micro9m() (machine_arch_type == MACH_TYPE_MICRO9M) -#else -# define machine_is_micro9m() (0) -#endif - -#ifdef CONFIG_MACH_IA_MOSPCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_MOSPCK -# endif -# define machine_is_ia_mospck() (machine_arch_type == MACH_TYPE_IA_MOSPCK) -#else -# define machine_is_ia_mospck() (0) -#endif - -#ifdef CONFIG_MACH_QL201B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QL201B -# endif -# define machine_is_ql201b() (machine_arch_type == MACH_TYPE_QL201B) -#else -# define machine_is_ql201b() (0) -#endif - -#ifdef CONFIG_MACH_BBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBM -# endif -# define machine_is_bbm() (machine_arch_type == MACH_TYPE_BBM) -#else -# define machine_is_bbm() (0) -#endif - -#ifdef CONFIG_MACH_EXXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXXX -# endif -# define machine_is_exxx() (machine_arch_type == MACH_TYPE_EXXX) -#else -# define machine_is_exxx() (0) -#endif - -#ifdef CONFIG_MACH_WMA11B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WMA11B -# endif -# define machine_is_wma11b() (machine_arch_type == MACH_TYPE_WMA11B) -#else -# define machine_is_wma11b() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ATLAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ATLAS -# endif -# define machine_is_pelco_atlas() (machine_arch_type == MACH_TYPE_PELCO_ATLAS) -#else -# define machine_is_pelco_atlas() (0) -#endif - -#ifdef CONFIG_MACH_G500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G500 -# endif -# define machine_is_g500() (machine_arch_type == MACH_TYPE_G500) -#else -# define machine_is_g500() (0) -#endif - -#ifdef CONFIG_MACH_BUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUG -# endif -# define machine_is_bug() (machine_arch_type == MACH_TYPE_BUG) -#else -# define machine_is_bug() (0) -#endif - -#ifdef CONFIG_MACH_MX33ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX33ADS -# endif -# define machine_is_mx33ads() (machine_arch_type == MACH_TYPE_MX33ADS) -#else -# define machine_is_mx33ads() (0) -#endif - -#ifdef CONFIG_MACH_CHUB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUB -# endif -# define machine_is_chub() (machine_arch_type == MACH_TYPE_CHUB) -#else -# define machine_is_chub() (0) -#endif - -#ifdef CONFIG_MACH_NEO1973_GTA01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEO1973_GTA01 -# endif -# define machine_is_neo1973_gta01() (machine_arch_type == MACH_TYPE_NEO1973_GTA01) -#else -# define machine_is_neo1973_gta01() (0) -#endif - -#ifdef CONFIG_MACH_W90N740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90N740 -# endif -# define machine_is_w90n740() (machine_arch_type == MACH_TYPE_W90N740) -#else -# define machine_is_w90n740() (0) -#endif - -#ifdef CONFIG_MACH_MEDALLION_SA2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEDALLION_SA2410 -# endif -# define machine_is_medallion_sa2410() (machine_arch_type == MACH_TYPE_MEDALLION_SA2410) -#else -# define machine_is_medallion_sa2410() (0) -#endif - -#ifdef CONFIG_MACH_IA_CPU_9200_2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_CPU_9200_2 -# endif -# define machine_is_ia_cpu_9200_2() (machine_arch_type == MACH_TYPE_IA_CPU_9200_2) -#else -# define machine_is_ia_cpu_9200_2() (0) -#endif - -#ifdef CONFIG_MACH_DIMMRM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIMMRM9200 -# endif -# define machine_is_dimmrm9200() (machine_arch_type == MACH_TYPE_DIMMRM9200) -#else -# define machine_is_dimmrm9200() (0) -#endif - -#ifdef CONFIG_MACH_PM9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM9261 -# endif -# define machine_is_pm9261() (machine_arch_type == MACH_TYPE_PM9261) -#else -# define machine_is_pm9261() (0) -#endif - -#ifdef CONFIG_MACH_ML7304 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML7304 -# endif -# define machine_is_ml7304() (machine_arch_type == MACH_TYPE_ML7304) -#else -# define machine_is_ml7304() (0) -#endif - -#ifdef CONFIG_MACH_UCP250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCP250 -# endif -# define machine_is_ucp250() (machine_arch_type == MACH_TYPE_UCP250) -#else -# define machine_is_ucp250() (0) -#endif - -#ifdef CONFIG_MACH_INTBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTBOARD -# endif -# define machine_is_intboard() (machine_arch_type == MACH_TYPE_INTBOARD) -#else -# define machine_is_intboard() (0) -#endif - -#ifdef CONFIG_MACH_GULFSTREAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GULFSTREAM -# endif -# define machine_is_gulfstream() (machine_arch_type == MACH_TYPE_GULFSTREAM) -#else -# define machine_is_gulfstream() (0) -#endif - -#ifdef CONFIG_MACH_LABQUEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LABQUEST -# endif -# define machine_is_labquest() (machine_arch_type == MACH_TYPE_LABQUEST) -#else -# define machine_is_labquest() (0) -#endif - -#ifdef CONFIG_MACH_VCMX313 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCMX313 -# endif -# define machine_is_vcmx313() (machine_arch_type == MACH_TYPE_VCMX313) -#else -# define machine_is_vcmx313() (0) -#endif - -#ifdef CONFIG_MACH_URG200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_URG200 -# endif -# define machine_is_urg200() (machine_arch_type == MACH_TYPE_URG200) -#else -# define machine_is_urg200() (0) -#endif - -#ifdef CONFIG_MACH_CPUX255LCDNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUX255LCDNET -# endif -# define machine_is_cpux255lcdnet() (machine_arch_type == MACH_TYPE_CPUX255LCDNET) -#else -# define machine_is_cpux255lcdnet() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU9 -# endif -# define machine_is_netdcu9() (machine_arch_type == MACH_TYPE_NETDCU9) -#else -# define machine_is_netdcu9() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU10 -# endif -# define machine_is_netdcu10() (machine_arch_type == MACH_TYPE_NETDCU10) -#else -# define machine_is_netdcu10() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DGA -# endif -# define machine_is_dspg_dga() (machine_arch_type == MACH_TYPE_DSPG_DGA) -#else -# define machine_is_dspg_dga() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DVW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DVW -# endif -# define machine_is_dspg_dvw() (machine_arch_type == MACH_TYPE_DSPG_DVW) -#else -# define machine_is_dspg_dvw() (0) -#endif - -#ifdef CONFIG_MACH_SOLOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOLOS -# endif -# define machine_is_solos() (machine_arch_type == MACH_TYPE_SOLOS) -#else -# define machine_is_solos() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263EK -# endif -# define machine_is_at91sam9263ek() (machine_arch_type == MACH_TYPE_AT91SAM9263EK) -#else -# define machine_is_at91sam9263ek() (0) -#endif - -#ifdef CONFIG_MACH_OSSTBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSSTBOX -# endif -# define machine_is_osstbox() (machine_arch_type == MACH_TYPE_OSSTBOX) -#else -# define machine_is_osstbox() (0) -#endif - -#ifdef CONFIG_MACH_KBAT9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBAT9261 -# endif -# define machine_is_kbat9261() (machine_arch_type == MACH_TYPE_KBAT9261) -#else -# define machine_is_kbat9261() (0) -#endif - -#ifdef CONFIG_MACH_CT1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT1100 -# endif -# define machine_is_ct1100() (machine_arch_type == MACH_TYPE_CT1100) -#else -# define machine_is_ct1100() (0) -#endif - -#ifdef CONFIG_MACH_AKCPPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKCPPXA -# endif -# define machine_is_akcppxa() (machine_arch_type == MACH_TYPE_AKCPPXA) -#else -# define machine_is_akcppxa() (0) -#endif - -#ifdef CONFIG_MACH_OCHAYA1020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCHAYA1020 -# endif -# define machine_is_ochaya1020() (machine_arch_type == MACH_TYPE_OCHAYA1020) -#else -# define machine_is_ochaya1020() (0) -#endif - -#ifdef CONFIG_MACH_HITRACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HITRACK -# endif -# define machine_is_hitrack() (machine_arch_type == MACH_TYPE_HITRACK) -#else -# define machine_is_hitrack() (0) -#endif - -#ifdef CONFIG_MACH_SYME1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYME1 -# endif -# define machine_is_syme1() (machine_arch_type == MACH_TYPE_SYME1) -#else -# define machine_is_syme1() (0) -#endif - -#ifdef CONFIG_MACH_SYHL1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYHL1 -# endif -# define machine_is_syhl1() (machine_arch_type == MACH_TYPE_SYHL1) -#else -# define machine_is_syhl1() (0) -#endif - -#ifdef CONFIG_MACH_EMPCA400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPCA400 -# endif -# define machine_is_empca400() (machine_arch_type == MACH_TYPE_EMPCA400) -#else -# define machine_is_empca400() (0) -#endif - -#ifdef CONFIG_MACH_EM7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM7210 -# endif -# define machine_is_em7210() (machine_arch_type == MACH_TYPE_EM7210) -#else -# define machine_is_em7210() (0) -#endif - -#ifdef CONFIG_MACH_HTCHERMES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCHERMES -# endif -# define machine_is_htchermes() (machine_arch_type == MACH_TYPE_HTCHERMES) -#else -# define machine_is_htchermes() (0) -#endif - -#ifdef CONFIG_MACH_ETI_C1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_C1 -# endif -# define machine_is_eti_c1() (machine_arch_type == MACH_TYPE_ETI_C1) -#else -# define machine_is_eti_c1() (0) -#endif - -#ifdef CONFIG_MACH_AC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AC100 -# endif -# define machine_is_ac100() (machine_arch_type == MACH_TYPE_AC100) -#else -# define machine_is_ac100() (0) -#endif - -#ifdef CONFIG_MACH_SNEETCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNEETCH -# endif -# define machine_is_sneetch() (machine_arch_type == MACH_TYPE_SNEETCH) -#else -# define machine_is_sneetch() (0) -#endif - -#ifdef CONFIG_MACH_STUDENTMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STUDENTMATE -# endif -# define machine_is_studentmate() (machine_arch_type == MACH_TYPE_STUDENTMATE) -#else -# define machine_is_studentmate() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2410 -# endif -# define machine_is_zir2410() (machine_arch_type == MACH_TYPE_ZIR2410) -#else -# define machine_is_zir2410() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2413 -# endif -# define machine_is_zir2413() (machine_arch_type == MACH_TYPE_ZIR2413) -#else -# define machine_is_zir2413() (0) -#endif - -#ifdef CONFIG_MACH_DLONIP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DLONIP3 -# endif -# define machine_is_dlonip3() (machine_arch_type == MACH_TYPE_DLONIP3) -#else -# define machine_is_dlonip3() (0) -#endif - -#ifdef CONFIG_MACH_INSTREAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INSTREAM -# endif -# define machine_is_instream() (machine_arch_type == MACH_TYPE_INSTREAM) -#else -# define machine_is_instream() (0) -#endif - -#ifdef CONFIG_MACH_AMBARELLA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMBARELLA -# endif -# define machine_is_ambarella() (machine_arch_type == MACH_TYPE_AMBARELLA) -#else -# define machine_is_ambarella() (0) -#endif - -#ifdef CONFIG_MACH_NEVIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEVIS -# endif -# define machine_is_nevis() (machine_arch_type == MACH_TYPE_NEVIS) -#else -# define machine_is_nevis() (0) -#endif - -#ifdef CONFIG_MACH_HTC_TRINITY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_TRINITY -# endif -# define machine_is_htc_trinity() (machine_arch_type == MACH_TYPE_HTC_TRINITY) -#else -# define machine_is_htc_trinity() (0) -#endif - -#ifdef CONFIG_MACH_QL202B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QL202B -# endif -# define machine_is_ql202b() (machine_arch_type == MACH_TYPE_QL202B) -#else -# define machine_is_ql202b() (0) -#endif - -#ifdef CONFIG_MACH_VPAC270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VPAC270 -# endif -# define machine_is_vpac270() (machine_arch_type == MACH_TYPE_VPAC270) -#else -# define machine_is_vpac270() (0) -#endif - -#ifdef CONFIG_MACH_RD129 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD129 -# endif -# define machine_is_rd129() (machine_arch_type == MACH_TYPE_RD129) -#else -# define machine_is_rd129() (0) -#endif - -#ifdef CONFIG_MACH_HTCWIZARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCWIZARD -# endif -# define machine_is_htcwizard() (machine_arch_type == MACH_TYPE_HTCWIZARD) -#else -# define machine_is_htcwizard() (0) -#endif - -#ifdef CONFIG_MACH_TREO680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO680 -# endif -# define machine_is_treo680() (machine_arch_type == MACH_TYPE_TREO680) -#else -# define machine_is_treo680() (0) -#endif - -#ifdef CONFIG_MACH_TECON_TMEZON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TECON_TMEZON -# endif -# define machine_is_tecon_tmezon() (machine_arch_type == MACH_TYPE_TECON_TMEZON) -#else -# define machine_is_tecon_tmezon() (0) -#endif - -#ifdef CONFIG_MACH_ZYLONITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZYLONITE -# endif -# define machine_is_zylonite() (machine_arch_type == MACH_TYPE_ZYLONITE) -#else -# define machine_is_zylonite() (0) -#endif - -#ifdef CONFIG_MACH_GENE1270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENE1270 -# endif -# define machine_is_gene1270() (machine_arch_type == MACH_TYPE_GENE1270) -#else -# define machine_is_gene1270() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2412 -# endif -# define machine_is_zir2412() (machine_arch_type == MACH_TYPE_ZIR2412) -#else -# define machine_is_zir2412() (0) -#endif - -#ifdef CONFIG_MACH_MX31LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31LITE -# endif -# define machine_is_mx31lite() (machine_arch_type == MACH_TYPE_MX31LITE) -#else -# define machine_is_mx31lite() (0) -#endif - -#ifdef CONFIG_MACH_T700WX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T700WX -# endif -# define machine_is_t700wx() (machine_arch_type == MACH_TYPE_T700WX) -#else -# define machine_is_t700wx() (0) -#endif - -#ifdef CONFIG_MACH_VF100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VF100 -# endif -# define machine_is_vf100() (machine_arch_type == MACH_TYPE_VF100) -#else -# define machine_is_vf100() (0) -#endif - -#ifdef CONFIG_MACH_NSB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB2 -# endif -# define machine_is_nsb2() (machine_arch_type == MACH_TYPE_NSB2) -#else -# define machine_is_nsb2() (0) -#endif - -#ifdef CONFIG_MACH_NXHMI_BB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHMI_BB -# endif -# define machine_is_nxhmi_bb() (machine_arch_type == MACH_TYPE_NXHMI_BB) -#else -# define machine_is_nxhmi_bb() (0) -#endif - -#ifdef CONFIG_MACH_NXHMI_RE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHMI_RE -# endif -# define machine_is_nxhmi_re() (machine_arch_type == MACH_TYPE_NXHMI_RE) -#else -# define machine_is_nxhmi_re() (0) -#endif - -#ifdef CONFIG_MACH_N4100PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N4100PRO -# endif -# define machine_is_n4100pro() (machine_arch_type == MACH_TYPE_N4100PRO) -#else -# define machine_is_n4100pro() (0) -#endif - -#ifdef CONFIG_MACH_SAM9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9260 -# endif -# define machine_is_sam9260() (machine_arch_type == MACH_TYPE_SAM9260) -#else -# define machine_is_sam9260() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TREO600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TREO600 -# endif -# define machine_is_omap_treo600() (machine_arch_type == MACH_TYPE_OMAP_TREO600) -#else -# define machine_is_omap_treo600() (0) -#endif - -#ifdef CONFIG_MACH_INDY2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INDY2410 -# endif -# define machine_is_indy2410() (machine_arch_type == MACH_TYPE_INDY2410) -#else -# define machine_is_indy2410() (0) -#endif - -#ifdef CONFIG_MACH_NELT_A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NELT_A -# endif -# define machine_is_nelt_a() (machine_arch_type == MACH_TYPE_NELT_A) -#else -# define machine_is_nelt_a() (0) -#endif - -#ifdef CONFIG_MACH_N311 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N311 -# endif -# define machine_is_n311() (machine_arch_type == MACH_TYPE_N311) -#else -# define machine_is_n311() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260VGK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260VGK -# endif -# define machine_is_at91sam9260vgk() (machine_arch_type == MACH_TYPE_AT91SAM9260VGK) -#else -# define machine_is_at91sam9260vgk() (0) -#endif - -#ifdef CONFIG_MACH_AT91LEPPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91LEPPE -# endif -# define machine_is_at91leppe() (machine_arch_type == MACH_TYPE_AT91LEPPE) -#else -# define machine_is_at91leppe() (0) -#endif - -#ifdef CONFIG_MACH_AT91LEPCCN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91LEPCCN -# endif -# define machine_is_at91lepccn() (machine_arch_type == MACH_TYPE_AT91LEPCCN) -#else -# define machine_is_at91lepccn() (0) -#endif - -#ifdef CONFIG_MACH_APC7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APC7100 -# endif -# define machine_is_apc7100() (machine_arch_type == MACH_TYPE_APC7100) -#else -# define machine_is_apc7100() (0) -#endif - -#ifdef CONFIG_MACH_STARGAZER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGAZER -# endif -# define machine_is_stargazer() (machine_arch_type == MACH_TYPE_STARGAZER) -#else -# define machine_is_stargazer() (0) -#endif - -#ifdef CONFIG_MACH_SONATA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONATA -# endif -# define machine_is_sonata() (machine_arch_type == MACH_TYPE_SONATA) -#else -# define machine_is_sonata() (0) -#endif - -#ifdef CONFIG_MACH_SCHMOOGIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCHMOOGIE -# endif -# define machine_is_schmoogie() (machine_arch_type == MACH_TYPE_SCHMOOGIE) -#else -# define machine_is_schmoogie() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOL -# endif -# define machine_is_aztool() (machine_arch_type == MACH_TYPE_AZTOOL) -#else -# define machine_is_aztool() (0) -#endif - -#ifdef CONFIG_MACH_MIOA701 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIOA701 -# endif -# define machine_is_mioa701() (machine_arch_type == MACH_TYPE_MIOA701) -#else -# define machine_is_mioa701() (0) -#endif - -#ifdef CONFIG_MACH_SXNI9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SXNI9260 -# endif -# define machine_is_sxni9260() (machine_arch_type == MACH_TYPE_SXNI9260) -#else -# define machine_is_sxni9260() (0) -#endif - -#ifdef CONFIG_MACH_MXC27520EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27520EVB -# endif -# define machine_is_mxc27520evb() (machine_arch_type == MACH_TYPE_MXC27520EVB) -#else -# define machine_is_mxc27520evb() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO5X0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO5X0 -# endif -# define machine_is_armadillo5x0() (machine_arch_type == MACH_TYPE_ARMADILLO5X0) -#else -# define machine_is_armadillo5x0() (0) -#endif - -#ifdef CONFIG_MACH_MB9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9260 -# endif -# define machine_is_mb9260() (machine_arch_type == MACH_TYPE_MB9260) -#else -# define machine_is_mb9260() (0) -#endif - -#ifdef CONFIG_MACH_MB9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9263 -# endif -# define machine_is_mb9263() (machine_arch_type == MACH_TYPE_MB9263) -#else -# define machine_is_mb9263() (0) -#endif - -#ifdef CONFIG_MACH_IPAC9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPAC9302 -# endif -# define machine_is_ipac9302() (machine_arch_type == MACH_TYPE_IPAC9302) -#else -# define machine_is_ipac9302() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360JS -# endif -# define machine_is_cc9p9360js() (machine_arch_type == MACH_TYPE_CC9P9360JS) -#else -# define machine_is_cc9p9360js() (0) -#endif - -#ifdef CONFIG_MACH_GALLIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GALLIUM -# endif -# define machine_is_gallium() (machine_arch_type == MACH_TYPE_GALLIUM) -#else -# define machine_is_gallium() (0) -#endif - -#ifdef CONFIG_MACH_MSC2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSC2410 -# endif -# define machine_is_msc2410() (machine_arch_type == MACH_TYPE_MSC2410) -#else -# define machine_is_msc2410() (0) -#endif - -#ifdef CONFIG_MACH_GHI270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GHI270 -# endif -# define machine_is_ghi270() (machine_arch_type == MACH_TYPE_GHI270) -#else -# define machine_is_ghi270() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_LEONARDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_LEONARDO -# endif -# define machine_is_davinci_leonardo() (machine_arch_type == MACH_TYPE_DAVINCI_LEONARDO) -#else -# define machine_is_davinci_leonardo() (0) -#endif - -#ifdef CONFIG_MACH_OIAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OIAB -# endif -# define machine_is_oiab() (machine_arch_type == MACH_TYPE_OIAB) -#else -# define machine_is_oiab() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6400 -# endif -# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400) -#else -# define machine_is_smdk6400() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N800 -# endif -# define machine_is_nokia_n800() (machine_arch_type == MACH_TYPE_NOKIA_N800) -#else -# define machine_is_nokia_n800() (0) -#endif - -#ifdef CONFIG_MACH_GREENPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GREENPHONE -# endif -# define machine_is_greenphone() (machine_arch_type == MACH_TYPE_GREENPHONE) -#else -# define machine_is_greenphone() (0) -#endif - -#ifdef CONFIG_MACH_COMPEXWP18 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPEXWP18 -# endif -# define machine_is_compex42x() (machine_arch_type == MACH_TYPE_COMPEXWP18) -#else -# define machine_is_compex42x() (0) -#endif - -#ifdef CONFIG_MACH_XMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XMATE -# endif -# define machine_is_xmate() (machine_arch_type == MACH_TYPE_XMATE) -#else -# define machine_is_xmate() (0) -#endif - -#ifdef CONFIG_MACH_ENERGIZER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENERGIZER -# endif -# define machine_is_energizer() (machine_arch_type == MACH_TYPE_ENERGIZER) -#else -# define machine_is_energizer() (0) -#endif - -#ifdef CONFIG_MACH_IME1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IME1 -# endif -# define machine_is_ime1() (machine_arch_type == MACH_TYPE_IME1) -#else -# define machine_is_ime1() (0) -#endif - -#ifdef CONFIG_MACH_SWEDATMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWEDATMS -# endif -# define machine_is_sweda_tms() (machine_arch_type == MACH_TYPE_SWEDATMS) -#else -# define machine_is_sweda_tms() (0) -#endif - -#ifdef CONFIG_MACH_NTNP435C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NTNP435C -# endif -# define machine_is_ntnp435c() (machine_arch_type == MACH_TYPE_NTNP435C) -#else -# define machine_is_ntnp435c() (0) -#endif - -#ifdef CONFIG_MACH_SPECTRO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPECTRO2 -# endif -# define machine_is_spectro2() (machine_arch_type == MACH_TYPE_SPECTRO2) -#else -# define machine_is_spectro2() (0) -#endif - -#ifdef CONFIG_MACH_H6039 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6039 -# endif -# define machine_is_h6039() (machine_arch_type == MACH_TYPE_H6039) -#else -# define machine_is_h6039() (0) -#endif - -#ifdef CONFIG_MACH_EP80219 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP80219 -# endif -# define machine_is_ep80219() (machine_arch_type == MACH_TYPE_EP80219) -#else -# define machine_is_ep80219() (0) -#endif - -#ifdef CONFIG_MACH_SAMOA_II -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMOA_II -# endif -# define machine_is_samoa_ii() (machine_arch_type == MACH_TYPE_SAMOA_II) -#else -# define machine_is_samoa_ii() (0) -#endif - -#ifdef CONFIG_MACH_CWMXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMXL -# endif -# define machine_is_cwmxl() (machine_arch_type == MACH_TYPE_CWMXL) -#else -# define machine_is_cwmxl() (0) -#endif - -#ifdef CONFIG_MACH_AS9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS9200 -# endif -# define machine_is_as9200() (machine_arch_type == MACH_TYPE_AS9200) -#else -# define machine_is_as9200() (0) -#endif - -#ifdef CONFIG_MACH_SFX1149 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFX1149 -# endif -# define machine_is_sfx1149() (machine_arch_type == MACH_TYPE_SFX1149) -#else -# define machine_is_sfx1149() (0) -#endif - -#ifdef CONFIG_MACH_NAVI010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAVI010 -# endif -# define machine_is_navi010() (machine_arch_type == MACH_TYPE_NAVI010) -#else -# define machine_is_navi010() (0) -#endif - -#ifdef CONFIG_MACH_MULTMDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTMDP -# endif -# define machine_is_multmdp() (machine_arch_type == MACH_TYPE_MULTMDP) -#else -# define machine_is_multmdp() (0) -#endif - -#ifdef CONFIG_MACH_SCB9520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCB9520 -# endif -# define machine_is_scb9520() (machine_arch_type == MACH_TYPE_SCB9520) -#else -# define machine_is_scb9520() (0) -#endif - -#ifdef CONFIG_MACH_HTCATHENA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCATHENA -# endif -# define machine_is_htcathena() (machine_arch_type == MACH_TYPE_HTCATHENA) -#else -# define machine_is_htcathena() (0) -#endif - -#ifdef CONFIG_MACH_XP179 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP179 -# endif -# define machine_is_xp179() (machine_arch_type == MACH_TYPE_XP179) -#else -# define machine_is_xp179() (0) -#endif - -#ifdef CONFIG_MACH_H4300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4300 -# endif -# define machine_is_h4300() (machine_arch_type == MACH_TYPE_H4300) -#else -# define machine_is_h4300() (0) -#endif - -#ifdef CONFIG_MACH_GORAMO_MLR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GORAMO_MLR -# endif -# define machine_is_goramo_mlr() (machine_arch_type == MACH_TYPE_GORAMO_MLR) -#else -# define machine_is_goramo_mlr() (0) -#endif - -#ifdef CONFIG_MACH_MXC30020EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30020EVB -# endif -# define machine_is_mxc30020evb() (machine_arch_type == MACH_TYPE_MXC30020EVB) -#else -# define machine_is_mxc30020evb() (0) -#endif - -#ifdef CONFIG_MACH_ADSBITSYG5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYG5 -# endif -# define machine_is_adsbitsyg5() (machine_arch_type == MACH_TYPE_ADSBITSYG5) -#else -# define machine_is_adsbitsyg5() (0) -#endif - -#ifdef CONFIG_MACH_ADSPORTALPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSPORTALPLUS -# endif -# define machine_is_adsportalplus() (machine_arch_type == MACH_TYPE_ADSPORTALPLUS) -#else -# define machine_is_adsportalplus() (0) -#endif - -#ifdef CONFIG_MACH_MMSP2PLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMSP2PLUS -# endif -# define machine_is_mmsp2plus() (machine_arch_type == MACH_TYPE_MMSP2PLUS) -#else -# define machine_is_mmsp2plus() (0) -#endif - -#ifdef CONFIG_MACH_EM_X270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM_X270 -# endif -# define machine_is_em_x270() (machine_arch_type == MACH_TYPE_EM_X270) -#else -# define machine_is_em_x270() (0) -#endif - -#ifdef CONFIG_MACH_TPP302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPP302 -# endif -# define machine_is_tpp302() (machine_arch_type == MACH_TYPE_TPP302) -#else -# define machine_is_tpp302() (0) -#endif - -#ifdef CONFIG_MACH_TPM104 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM104 -# endif -# define machine_is_tpp104() (machine_arch_type == MACH_TYPE_TPM104) -#else -# define machine_is_tpp104() (0) -#endif - -#ifdef CONFIG_MACH_TPM102 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM102 -# endif -# define machine_is_tpm102() (machine_arch_type == MACH_TYPE_TPM102) -#else -# define machine_is_tpm102() (0) -#endif - -#ifdef CONFIG_MACH_TPM109 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM109 -# endif -# define machine_is_tpm109() (machine_arch_type == MACH_TYPE_TPM109) -#else -# define machine_is_tpm109() (0) -#endif - -#ifdef CONFIG_MACH_FBXO1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FBXO1 -# endif -# define machine_is_fbxo1() (machine_arch_type == MACH_TYPE_FBXO1) -#else -# define machine_is_fbxo1() (0) -#endif - -#ifdef CONFIG_MACH_HXD8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HXD8 -# endif -# define machine_is_hxd8() (machine_arch_type == MACH_TYPE_HXD8) -#else -# define machine_is_hxd8() (0) -#endif - -#ifdef CONFIG_MACH_NEO1973_GTA02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEO1973_GTA02 -# endif -# define machine_is_neo1973_gta02() (machine_arch_type == MACH_TYPE_NEO1973_GTA02) -#else -# define machine_is_neo1973_gta02() (0) -#endif - -#ifdef CONFIG_MACH_EMTEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMTEST -# endif -# define machine_is_emtest() (machine_arch_type == MACH_TYPE_EMTEST) -#else -# define machine_is_emtest() (0) -#endif - -#ifdef CONFIG_MACH_AD6900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AD6900 -# endif -# define machine_is_ad6900() (machine_arch_type == MACH_TYPE_AD6900) -#else -# define machine_is_ad6900() (0) -#endif - -#ifdef CONFIG_MACH_EUROPA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUROPA -# endif -# define machine_is_europa() (machine_arch_type == MACH_TYPE_EUROPA) -#else -# define machine_is_europa() (0) -#endif - -#ifdef CONFIG_MACH_METROCONNECT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_METROCONNECT -# endif -# define machine_is_metroconnect() (machine_arch_type == MACH_TYPE_METROCONNECT) -#else -# define machine_is_metroconnect() (0) -#endif - -#ifdef CONFIG_MACH_EZ_S2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_S2410 -# endif -# define machine_is_ez_s2410() (machine_arch_type == MACH_TYPE_EZ_S2410) -#else -# define machine_is_ez_s2410() (0) -#endif - -#ifdef CONFIG_MACH_EZ_S2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_S2440 -# endif -# define machine_is_ez_s2440() (machine_arch_type == MACH_TYPE_EZ_S2440) -#else -# define machine_is_ez_s2440() (0) -#endif - -#ifdef CONFIG_MACH_EZ_EP9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_EP9312 -# endif -# define machine_is_ez_ep9312() (machine_arch_type == MACH_TYPE_EZ_EP9312) -#else -# define machine_is_ez_ep9312() (0) -#endif - -#ifdef CONFIG_MACH_EZ_EP9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_EP9315 -# endif -# define machine_is_ez_ep9315() (machine_arch_type == MACH_TYPE_EZ_EP9315) -#else -# define machine_is_ez_ep9315() (0) -#endif - -#ifdef CONFIG_MACH_EZ_X7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_X7 -# endif -# define machine_is_ez_x7() (machine_arch_type == MACH_TYPE_EZ_X7) -#else -# define machine_is_ez_x7() (0) -#endif - -#ifdef CONFIG_MACH_GODOTDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GODOTDB -# endif -# define machine_is_godotdb() (machine_arch_type == MACH_TYPE_GODOTDB) -#else -# define machine_is_godotdb() (0) -#endif - -#ifdef CONFIG_MACH_MISTRAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MISTRAL -# endif -# define machine_is_mistral() (machine_arch_type == MACH_TYPE_MISTRAL) -#else -# define machine_is_mistral() (0) -#endif - -#ifdef CONFIG_MACH_MSM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM -# endif -# define machine_is_msm() (machine_arch_type == MACH_TYPE_MSM) -#else -# define machine_is_msm() (0) -#endif - -#ifdef CONFIG_MACH_CT5910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT5910 -# endif -# define machine_is_ct5910() (machine_arch_type == MACH_TYPE_CT5910) -#else -# define machine_is_ct5910() (0) -#endif - -#ifdef CONFIG_MACH_CT5912 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT5912 -# endif -# define machine_is_ct5912() (machine_arch_type == MACH_TYPE_CT5912) -#else -# define machine_is_ct5912() (0) -#endif - -#ifdef CONFIG_MACH_HYNET_INE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYNET_INE -# endif -# define machine_is_hynet_ine() (machine_arch_type == MACH_TYPE_HYNET_INE) -#else -# define machine_is_hynet_ine() (0) -#endif - -#ifdef CONFIG_MACH_HYNET_APP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYNET_APP -# endif -# define machine_is_hynet_app() (machine_arch_type == MACH_TYPE_HYNET_APP) -#else -# define machine_is_hynet_app() (0) -#endif - -#ifdef CONFIG_MACH_MSM7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7200 -# endif -# define machine_is_msm7200() (machine_arch_type == MACH_TYPE_MSM7200) -#else -# define machine_is_msm7200() (0) -#endif - -#ifdef CONFIG_MACH_MSM7600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7600 -# endif -# define machine_is_msm7600() (machine_arch_type == MACH_TYPE_MSM7600) -#else -# define machine_is_msm7600() (0) -#endif - -#ifdef CONFIG_MACH_CEB255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEB255 -# endif -# define machine_is_ceb255() (machine_arch_type == MACH_TYPE_CEB255) -#else -# define machine_is_ceb255() (0) -#endif - -#ifdef CONFIG_MACH_CIEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CIEL -# endif -# define machine_is_ciel() (machine_arch_type == MACH_TYPE_CIEL) -#else -# define machine_is_ciel() (0) -#endif - -#ifdef CONFIG_MACH_SLM5650 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLM5650 -# endif -# define machine_is_slm5650() (machine_arch_type == MACH_TYPE_SLM5650) -#else -# define machine_is_slm5650() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9RLEK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9RLEK -# endif -# define machine_is_at91sam9rlek() (machine_arch_type == MACH_TYPE_AT91SAM9RLEK) -#else -# define machine_is_at91sam9rlek() (0) -#endif - -#ifdef CONFIG_MACH_COMTECH_ROUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMTECH_ROUTER -# endif -# define machine_is_comtech_router() (machine_arch_type == MACH_TYPE_COMTECH_ROUTER) -#else -# define machine_is_comtech_router() (0) -#endif - -#ifdef CONFIG_MACH_SBC2410X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2410X -# endif -# define machine_is_sbc2410x() (machine_arch_type == MACH_TYPE_SBC2410X) -#else -# define machine_is_sbc2410x() (0) -#endif - -#ifdef CONFIG_MACH_AT4X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT4X0BD -# endif -# define machine_is_at4x0bd() (machine_arch_type == MACH_TYPE_AT4X0BD) -#else -# define machine_is_at4x0bd() (0) -#endif - -#ifdef CONFIG_MACH_CBIFR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CBIFR -# endif -# define machine_is_cbifr() (machine_arch_type == MACH_TYPE_CBIFR) -#else -# define machine_is_cbifr() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_QUANTUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_QUANTUM -# endif -# define machine_is_arcom_quantum() (machine_arch_type == MACH_TYPE_ARCOM_QUANTUM) -#else -# define machine_is_arcom_quantum() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX520 -# endif -# define machine_is_matrix520() (machine_arch_type == MACH_TYPE_MATRIX520) -#else -# define machine_is_matrix520() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX510 -# endif -# define machine_is_matrix510() (machine_arch_type == MACH_TYPE_MATRIX510) -#else -# define machine_is_matrix510() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX500 -# endif -# define machine_is_matrix500() (machine_arch_type == MACH_TYPE_MATRIX500) -#else -# define machine_is_matrix500() (0) -#endif - -#ifdef CONFIG_MACH_M501 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M501 -# endif -# define machine_is_m501() (machine_arch_type == MACH_TYPE_M501) -#else -# define machine_is_m501() (0) -#endif - -#ifdef CONFIG_MACH_AAEON1270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AAEON1270 -# endif -# define machine_is_aaeon1270() (machine_arch_type == MACH_TYPE_AAEON1270) -#else -# define machine_is_aaeon1270() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX500EV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX500EV -# endif -# define machine_is_matrix500ev() (machine_arch_type == MACH_TYPE_MATRIX500EV) -#else -# define machine_is_matrix500ev() (0) -#endif - -#ifdef CONFIG_MACH_PAC500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PAC500 -# endif -# define machine_is_pac500() (machine_arch_type == MACH_TYPE_PAC500) -#else -# define machine_is_pac500() (0) -#endif - -#ifdef CONFIG_MACH_PNX8181 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX8181 -# endif -# define machine_is_pnx8181() (machine_arch_type == MACH_TYPE_PNX8181) -#else -# define machine_is_pnx8181() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI320 -# endif -# define machine_is_colibri320() (machine_arch_type == MACH_TYPE_COLIBRI320) -#else -# define machine_is_colibri320() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOLBB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOLBB -# endif -# define machine_is_aztoolbb() (machine_arch_type == MACH_TYPE_AZTOOLBB) -#else -# define machine_is_aztoolbb() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOLG2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOLG2 -# endif -# define machine_is_aztoolg2() (machine_arch_type == MACH_TYPE_AZTOOLG2) -#else -# define machine_is_aztoolg2() (0) -#endif - -#ifdef CONFIG_MACH_DVLHOST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DVLHOST -# endif -# define machine_is_dvlhost() (machine_arch_type == MACH_TYPE_DVLHOST) -#else -# define machine_is_dvlhost() (0) -#endif - -#ifdef CONFIG_MACH_ZIR9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR9200 -# endif -# define machine_is_zir9200() (machine_arch_type == MACH_TYPE_ZIR9200) -#else -# define machine_is_zir9200() (0) -#endif - -#ifdef CONFIG_MACH_ZIR9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR9260 -# endif -# define machine_is_zir9260() (machine_arch_type == MACH_TYPE_ZIR9260) -#else -# define machine_is_zir9260() (0) -#endif - -#ifdef CONFIG_MACH_COCOPAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COCOPAH -# endif -# define machine_is_cocopah() (machine_arch_type == MACH_TYPE_COCOPAH) -#else -# define machine_is_cocopah() (0) -#endif - -#ifdef CONFIG_MACH_NDS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NDS -# endif -# define machine_is_nds() (machine_arch_type == MACH_TYPE_NDS) -#else -# define machine_is_nds() (0) -#endif - -#ifdef CONFIG_MACH_ROSENCRANTZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROSENCRANTZ -# endif -# define machine_is_rosencrantz() (machine_arch_type == MACH_TYPE_ROSENCRANTZ) -#else -# define machine_is_rosencrantz() (0) -#endif - -#ifdef CONFIG_MACH_FTTX_ODSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FTTX_ODSC -# endif -# define machine_is_fttx_odsc() (machine_arch_type == MACH_TYPE_FTTX_ODSC) -#else -# define machine_is_fttx_odsc() (0) -#endif - -#ifdef CONFIG_MACH_CLASSE_R6904 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLASSE_R6904 -# endif -# define machine_is_classe_r6904() (machine_arch_type == MACH_TYPE_CLASSE_R6904) -#else -# define machine_is_classe_r6904() (0) -#endif - -#ifdef CONFIG_MACH_CAM60 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAM60 -# endif -# define machine_is_cam60() (machine_arch_type == MACH_TYPE_CAM60) -#else -# define machine_is_cam60() (0) -#endif - -#ifdef CONFIG_MACH_MXC30031ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30031ADS -# endif -# define machine_is_mxc30031ads() (machine_arch_type == MACH_TYPE_MXC30031ADS) -#else -# define machine_is_mxc30031ads() (0) -#endif - -#ifdef CONFIG_MACH_DATACALL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DATACALL -# endif -# define machine_is_datacall() (machine_arch_type == MACH_TYPE_DATACALL) -#else -# define machine_is_datacall() (0) -#endif - -#ifdef CONFIG_MACH_AT91EB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91EB01 -# endif -# define machine_is_at91eb01() (machine_arch_type == MACH_TYPE_AT91EB01) -#else -# define machine_is_at91eb01() (0) -#endif - -#ifdef CONFIG_MACH_RTY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RTY -# endif -# define machine_is_rty() (machine_arch_type == MACH_TYPE_RTY) -#else -# define machine_is_rty() (0) -#endif - -#ifdef CONFIG_MACH_DWL2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DWL2100 -# endif -# define machine_is_dwl2100() (machine_arch_type == MACH_TYPE_DWL2100) -#else -# define machine_is_dwl2100() (0) -#endif - -#ifdef CONFIG_MACH_VINSI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VINSI -# endif -# define machine_is_vinsi() (machine_arch_type == MACH_TYPE_VINSI) -#else -# define machine_is_vinsi() (0) -#endif - -#ifdef CONFIG_MACH_DB88F5281 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB88F5281 -# endif -# define machine_is_db88f5281() (machine_arch_type == MACH_TYPE_DB88F5281) -#else -# define machine_is_db88f5281() (0) -#endif - -#ifdef CONFIG_MACH_CSB726 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB726 -# endif -# define machine_is_csb726() (machine_arch_type == MACH_TYPE_CSB726) -#else -# define machine_is_csb726() (0) -#endif - -#ifdef CONFIG_MACH_TIK27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIK27 -# endif -# define machine_is_tik27() (machine_arch_type == MACH_TYPE_TIK27) -#else -# define machine_is_tik27() (0) -#endif - -#ifdef CONFIG_MACH_MX_UC7420 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX_UC7420 -# endif -# define machine_is_mx_uc7420() (machine_arch_type == MACH_TYPE_MX_UC7420) -#else -# define machine_is_mx_uc7420() (0) -#endif - -#ifdef CONFIG_MACH_RIRM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIRM3 -# endif -# define machine_is_rirm3() (machine_arch_type == MACH_TYPE_RIRM3) -#else -# define machine_is_rirm3() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ODYSSEY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ODYSSEY -# endif -# define machine_is_pelco_odyssey() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEY) -#else -# define machine_is_pelco_odyssey() (0) -#endif - -#ifdef CONFIG_MACH_ADX_ABOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_ABOX -# endif -# define machine_is_adx_abox() (machine_arch_type == MACH_TYPE_ADX_ABOX) -#else -# define machine_is_adx_abox() (0) -#endif - -#ifdef CONFIG_MACH_ADX_TPID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_TPID -# endif -# define machine_is_adx_tpid() (machine_arch_type == MACH_TYPE_ADX_TPID) -#else -# define machine_is_adx_tpid() (0) -#endif - -#ifdef CONFIG_MACH_MINICHECK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINICHECK -# endif -# define machine_is_minicheck() (machine_arch_type == MACH_TYPE_MINICHECK) -#else -# define machine_is_minicheck() (0) -#endif - -#ifdef CONFIG_MACH_IDAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDAM -# endif -# define machine_is_idam() (machine_arch_type == MACH_TYPE_IDAM) -#else -# define machine_is_idam() (0) -#endif - -#ifdef CONFIG_MACH_MARIO_MX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARIO_MX -# endif -# define machine_is_mario_mx() (machine_arch_type == MACH_TYPE_MARIO_MX) -#else -# define machine_is_mario_mx() (0) -#endif - -#ifdef CONFIG_MACH_VI1888 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VI1888 -# endif -# define machine_is_vi1888() (machine_arch_type == MACH_TYPE_VI1888) -#else -# define machine_is_vi1888() (0) -#endif - -#ifdef CONFIG_MACH_ZR4230 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZR4230 -# endif -# define machine_is_zr4230() (machine_arch_type == MACH_TYPE_ZR4230) -#else -# define machine_is_zr4230() (0) -#endif - -#ifdef CONFIG_MACH_T1_IX_BLUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T1_IX_BLUE -# endif -# define machine_is_t1_ix_blue() (machine_arch_type == MACH_TYPE_T1_IX_BLUE) -#else -# define machine_is_t1_ix_blue() (0) -#endif - -#ifdef CONFIG_MACH_SYHQ2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYHQ2 -# endif -# define machine_is_syhq2() (machine_arch_type == MACH_TYPE_SYHQ2) -#else -# define machine_is_syhq2() (0) -#endif - -#ifdef CONFIG_MACH_COMPUTIME_R3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPUTIME_R3 -# endif -# define machine_is_computime_r3() (machine_arch_type == MACH_TYPE_COMPUTIME_R3) -#else -# define machine_is_computime_r3() (0) -#endif - -#ifdef CONFIG_MACH_ORATIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATIS -# endif -# define machine_is_oratis() (machine_arch_type == MACH_TYPE_ORATIS) -#else -# define machine_is_oratis() (0) -#endif - -#ifdef CONFIG_MACH_MIKKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIKKO -# endif -# define machine_is_mikko() (machine_arch_type == MACH_TYPE_MIKKO) -#else -# define machine_is_mikko() (0) -#endif - -#ifdef CONFIG_MACH_HOLON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOLON -# endif -# define machine_is_holon() (machine_arch_type == MACH_TYPE_HOLON) -#else -# define machine_is_holon() (0) -#endif - -#ifdef CONFIG_MACH_OLIP8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLIP8 -# endif -# define machine_is_olip8() (machine_arch_type == MACH_TYPE_OLIP8) -#else -# define machine_is_olip8() (0) -#endif - -#ifdef CONFIG_MACH_GHI270HG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GHI270HG -# endif -# define machine_is_ghi270hg() (machine_arch_type == MACH_TYPE_GHI270HG) -#else -# define machine_is_ghi270hg() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM6467_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM6467_EVM -# endif -# define machine_is_davinci_dm6467_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467_EVM) -#else -# define machine_is_davinci_dm6467_evm() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM355_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM355_EVM -# endif -# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM) -#else -# define machine_is_davinci_dm355_evm() (0) -#endif - -#ifdef CONFIG_MACH_BLACKRIVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKRIVER -# endif -# define machine_is_blackriver() (machine_arch_type == MACH_TYPE_BLACKRIVER) -#else -# define machine_is_blackriver() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATEWP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATEWP -# endif -# define machine_is_sandgate_wp() (machine_arch_type == MACH_TYPE_SANDGATEWP) -#else -# define machine_is_sandgate_wp() (0) -#endif - -#ifdef CONFIG_MACH_CDOTBWSG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDOTBWSG -# endif -# define machine_is_cdotbwsg() (machine_arch_type == MACH_TYPE_CDOTBWSG) -#else -# define machine_is_cdotbwsg() (0) -#endif - -#ifdef CONFIG_MACH_QUARK963 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUARK963 -# endif -# define machine_is_quark963() (machine_arch_type == MACH_TYPE_QUARK963) -#else -# define machine_is_quark963() (0) -#endif - -#ifdef CONFIG_MACH_CSB735 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB735 -# endif -# define machine_is_csb735() (machine_arch_type == MACH_TYPE_CSB735) -#else -# define machine_is_csb735() (0) -#endif - -#ifdef CONFIG_MACH_LITTLETON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LITTLETON -# endif -# define machine_is_littleton() (machine_arch_type == MACH_TYPE_LITTLETON) -#else -# define machine_is_littleton() (0) -#endif - -#ifdef CONFIG_MACH_MIO_P550 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIO_P550 -# endif -# define machine_is_mio_p550() (machine_arch_type == MACH_TYPE_MIO_P550) -#else -# define machine_is_mio_p550() (0) -#endif - -#ifdef CONFIG_MACH_MOTION2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTION2440 -# endif -# define machine_is_motion2440() (machine_arch_type == MACH_TYPE_MOTION2440) -#else -# define machine_is_motion2440() (0) -#endif - -#ifdef CONFIG_MACH_IMM500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMM500 -# endif -# define machine_is_imm500() (machine_arch_type == MACH_TYPE_IMM500) -#else -# define machine_is_imm500() (0) -#endif - -#ifdef CONFIG_MACH_HOMEMATIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOMEMATIC -# endif -# define machine_is_homematic() (machine_arch_type == MACH_TYPE_HOMEMATIC) -#else -# define machine_is_homematic() (0) -#endif - -#ifdef CONFIG_MACH_ERMINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ERMINE -# endif -# define machine_is_ermine() (machine_arch_type == MACH_TYPE_ERMINE) -#else -# define machine_is_ermine() (0) -#endif - -#ifdef CONFIG_MACH_KB9202B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9202B -# endif -# define machine_is_kb9202b() (machine_arch_type == MACH_TYPE_KB9202B) -#else -# define machine_is_kb9202b() (0) -#endif - -#ifdef CONFIG_MACH_HS1XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HS1XX -# endif -# define machine_is_hs1xx() (machine_arch_type == MACH_TYPE_HS1XX) -#else -# define machine_is_hs1xx() (0) -#endif - -#ifdef CONFIG_MACH_STUDENTMATE2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STUDENTMATE2440 -# endif -# define machine_is_studentmate2440() (machine_arch_type == MACH_TYPE_STUDENTMATE2440) -#else -# define machine_is_studentmate2440() (0) -#endif - -#ifdef CONFIG_MACH_ARVOO_L1_Z1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARVOO_L1_Z1 -# endif -# define machine_is_arvoo_l1_z1() (machine_arch_type == MACH_TYPE_ARVOO_L1_Z1) -#else -# define machine_is_arvoo_l1_z1() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410K -# endif -# define machine_is_dep2410k() (machine_arch_type == MACH_TYPE_DEP2410K) -#else -# define machine_is_dep2410k() (0) -#endif - -#ifdef CONFIG_MACH_XXSVIDEO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XXSVIDEO -# endif -# define machine_is_xxsvideo() (machine_arch_type == MACH_TYPE_XXSVIDEO) -#else -# define machine_is_xxsvideo() (0) -#endif - -#ifdef CONFIG_MACH_IM4004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IM4004 -# endif -# define machine_is_im4004() (machine_arch_type == MACH_TYPE_IM4004) -#else -# define machine_is_im4004() (0) -#endif - -#ifdef CONFIG_MACH_OCHAYA1050 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCHAYA1050 -# endif -# define machine_is_ochaya1050() (machine_arch_type == MACH_TYPE_OCHAYA1050) -#else -# define machine_is_ochaya1050() (0) -#endif - -#ifdef CONFIG_MACH_LEP9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEP9261 -# endif -# define machine_is_lep9261() (machine_arch_type == MACH_TYPE_LEP9261) -#else -# define machine_is_lep9261() (0) -#endif - -#ifdef CONFIG_MACH_SVENMEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVENMEB -# endif -# define machine_is_svenmeb() (machine_arch_type == MACH_TYPE_SVENMEB) -#else -# define machine_is_svenmeb() (0) -#endif - -#ifdef CONFIG_MACH_FORTUNET2NE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET2NE -# endif -# define machine_is_fortunet2ne() (machine_arch_type == MACH_TYPE_FORTUNET2NE) -#else -# define machine_is_fortunet2ne() (0) -#endif - -#ifdef CONFIG_MACH_NXHX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHX -# endif -# define machine_is_nxhx() (machine_arch_type == MACH_TYPE_NXHX) -#else -# define machine_is_nxhx() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PB11MP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PB11MP -# endif -# define machine_is_realview_pb11mp() (machine_arch_type == MACH_TYPE_REALVIEW_PB11MP) -#else -# define machine_is_realview_pb11mp() (0) -#endif - -#ifdef CONFIG_MACH_IDS500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDS500 -# endif -# define machine_is_ids500() (machine_arch_type == MACH_TYPE_IDS500) -#else -# define machine_is_ids500() (0) -#endif - -#ifdef CONFIG_MACH_ORS_N725 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORS_N725 -# endif -# define machine_is_ors_n725() (machine_arch_type == MACH_TYPE_ORS_N725) -#else -# define machine_is_ors_n725() (0) -#endif - -#ifdef CONFIG_MACH_HSDARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HSDARM -# endif -# define machine_is_hsdarm() (machine_arch_type == MACH_TYPE_HSDARM) -#else -# define machine_is_hsdarm() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON003 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON003 -# endif -# define machine_is_sha_pon003() (machine_arch_type == MACH_TYPE_SHA_PON003) -#else -# define machine_is_sha_pon003() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON004 -# endif -# define machine_is_sha_pon004() (machine_arch_type == MACH_TYPE_SHA_PON004) -#else -# define machine_is_sha_pon004() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON007 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON007 -# endif -# define machine_is_sha_pon007() (machine_arch_type == MACH_TYPE_SHA_PON007) -#else -# define machine_is_sha_pon007() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON011 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON011 -# endif -# define machine_is_sha_pon011() (machine_arch_type == MACH_TYPE_SHA_PON011) -#else -# define machine_is_sha_pon011() (0) -#endif - -#ifdef CONFIG_MACH_H6042 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6042 -# endif -# define machine_is_h6042() (machine_arch_type == MACH_TYPE_H6042) -#else -# define machine_is_h6042() (0) -#endif - -#ifdef CONFIG_MACH_H6043 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6043 -# endif -# define machine_is_h6043() (machine_arch_type == MACH_TYPE_H6043) -#else -# define machine_is_h6043() (0) -#endif - -#ifdef CONFIG_MACH_LOOXC550 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOXC550 -# endif -# define machine_is_looxc550() (machine_arch_type == MACH_TYPE_LOOXC550) -#else -# define machine_is_looxc550() (0) -#endif - -#ifdef CONFIG_MACH_CNTY_TITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNTY_TITAN -# endif -# define machine_is_cnty_titan() (machine_arch_type == MACH_TYPE_CNTY_TITAN) -#else -# define machine_is_cnty_titan() (0) -#endif - -#ifdef CONFIG_MACH_APP3XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APP3XX -# endif -# define machine_is_app3xx() (machine_arch_type == MACH_TYPE_APP3XX) -#else -# define machine_is_app3xx() (0) -#endif - -#ifdef CONFIG_MACH_SIDEOATSGRAMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEOATSGRAMA -# endif -# define machine_is_sideoatsgrama() (machine_arch_type == MACH_TYPE_SIDEOATSGRAMA) -#else -# define machine_is_sideoatsgrama() (0) -#endif - -#ifdef CONFIG_MACH_TREO700P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO700P -# endif -# define machine_is_treo700p() (machine_arch_type == MACH_TYPE_TREO700P) -#else -# define machine_is_treo700p() (0) -#endif - -#ifdef CONFIG_MACH_TREO700W -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO700W -# endif -# define machine_is_treo700w() (machine_arch_type == MACH_TYPE_TREO700W) -#else -# define machine_is_treo700w() (0) -#endif - -#ifdef CONFIG_MACH_TREO750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO750 -# endif -# define machine_is_treo750() (machine_arch_type == MACH_TYPE_TREO750) -#else -# define machine_is_treo750() (0) -#endif - -#ifdef CONFIG_MACH_TREO755P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO755P -# endif -# define machine_is_treo755p() (machine_arch_type == MACH_TYPE_TREO755P) -#else -# define machine_is_treo755p() (0) -#endif - -#ifdef CONFIG_MACH_EZREGANUT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZREGANUT9200 -# endif -# define machine_is_ezreganut9200() (machine_arch_type == MACH_TYPE_EZREGANUT9200) -#else -# define machine_is_ezreganut9200() (0) -#endif - -#ifdef CONFIG_MACH_SARGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SARGE -# endif -# define machine_is_sarge() (machine_arch_type == MACH_TYPE_SARGE) -#else -# define machine_is_sarge() (0) -#endif - -#ifdef CONFIG_MACH_A696 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A696 -# endif -# define machine_is_a696() (machine_arch_type == MACH_TYPE_A696) -#else -# define machine_is_a696() (0) -#endif - -#ifdef CONFIG_MACH_TURTLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TURTLE -# endif -# define machine_is_turtle1916() (machine_arch_type == MACH_TYPE_TURTLE) -#else -# define machine_is_turtle1916() (0) -#endif - -#ifdef CONFIG_MACH_MX27_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27_3DS -# endif -# define machine_is_mx27_3ds() (machine_arch_type == MACH_TYPE_MX27_3DS) -#else -# define machine_is_mx27_3ds() (0) -#endif - -#ifdef CONFIG_MACH_BISHOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BISHOP -# endif -# define machine_is_bishop() (machine_arch_type == MACH_TYPE_BISHOP) -#else -# define machine_is_bishop() (0) -#endif - -#ifdef CONFIG_MACH_PXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXX -# endif -# define machine_is_pxx() (machine_arch_type == MACH_TYPE_PXX) -#else -# define machine_is_pxx() (0) -#endif - -#ifdef CONFIG_MACH_REDWOOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REDWOOD -# endif -# define machine_is_redwood() (machine_arch_type == MACH_TYPE_REDWOOD) -#else -# define machine_is_redwood() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430DLP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430DLP -# endif -# define machine_is_omap_2430dlp() (machine_arch_type == MACH_TYPE_OMAP_2430DLP) -#else -# define machine_is_omap_2430dlp() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430OSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430OSK -# endif -# define machine_is_omap_2430osk() (machine_arch_type == MACH_TYPE_OMAP_2430OSK) -#else -# define machine_is_omap_2430osk() (0) -#endif - -#ifdef CONFIG_MACH_SARDINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SARDINE -# endif -# define machine_is_sardine() (machine_arch_type == MACH_TYPE_SARDINE) -#else -# define machine_is_sardine() (0) -#endif - -#ifdef CONFIG_MACH_HALIBUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HALIBUT -# endif -# define machine_is_halibut() (machine_arch_type == MACH_TYPE_HALIBUT) -#else -# define machine_is_halibut() (0) -#endif - -#ifdef CONFIG_MACH_TROUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TROUT -# endif -# define machine_is_trout() (machine_arch_type == MACH_TYPE_TROUT) -#else -# define machine_is_trout() (0) -#endif - -#ifdef CONFIG_MACH_GOLDFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOLDFISH -# endif -# define machine_is_goldfish() (machine_arch_type == MACH_TYPE_GOLDFISH) -#else -# define machine_is_goldfish() (0) -#endif - -#ifdef CONFIG_MACH_GESBC2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC2440 -# endif -# define machine_is_gesbc2440() (machine_arch_type == MACH_TYPE_GESBC2440) -#else -# define machine_is_gesbc2440() (0) -#endif - -#ifdef CONFIG_MACH_NOMAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOMAD -# endif -# define machine_is_nomad() (machine_arch_type == MACH_TYPE_NOMAD) -#else -# define machine_is_nomad() (0) -#endif - -#ifdef CONFIG_MACH_ROSALIND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROSALIND -# endif -# define machine_is_rosalind() (machine_arch_type == MACH_TYPE_ROSALIND) -#else -# define machine_is_rosalind() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215 -# endif -# define machine_is_cc9p9215() (machine_arch_type == MACH_TYPE_CC9P9215) -#else -# define machine_is_cc9p9215() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9210 -# endif -# define machine_is_cc9p9210() (machine_arch_type == MACH_TYPE_CC9P9210) -#else -# define machine_is_cc9p9210() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215JS -# endif -# define machine_is_cc9p9215js() (machine_arch_type == MACH_TYPE_CC9P9215JS) -#else -# define machine_is_cc9p9215js() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9210JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9210JS -# endif -# define machine_is_cc9p9210js() (machine_arch_type == MACH_TYPE_CC9P9210JS) -#else -# define machine_is_cc9p9210js() (0) -#endif - -#ifdef CONFIG_MACH_NASFFE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NASFFE -# endif -# define machine_is_nasffe() (machine_arch_type == MACH_TYPE_NASFFE) -#else -# define machine_is_nasffe() (0) -#endif - -#ifdef CONFIG_MACH_TN2X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TN2X0BD -# endif -# define machine_is_tn2x0bd() (machine_arch_type == MACH_TYPE_TN2X0BD) -#else -# define machine_is_tn2x0bd() (0) -#endif - -#ifdef CONFIG_MACH_GWMPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GWMPXA -# endif -# define machine_is_gwmpxa() (machine_arch_type == MACH_TYPE_GWMPXA) -#else -# define machine_is_gwmpxa() (0) -#endif - -#ifdef CONFIG_MACH_EXYPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXYPLUS -# endif -# define machine_is_exyplus() (machine_arch_type == MACH_TYPE_EXYPLUS) -#else -# define machine_is_exyplus() (0) -#endif - -#ifdef CONFIG_MACH_JADOO21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADOO21 -# endif -# define machine_is_jadoo21() (machine_arch_type == MACH_TYPE_JADOO21) -#else -# define machine_is_jadoo21() (0) -#endif - -#ifdef CONFIG_MACH_LOOXN560 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOXN560 -# endif -# define machine_is_looxn560() (machine_arch_type == MACH_TYPE_LOOXN560) -#else -# define machine_is_looxn560() (0) -#endif - -#ifdef CONFIG_MACH_BONSAI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BONSAI -# endif -# define machine_is_bonsai() (machine_arch_type == MACH_TYPE_BONSAI) -#else -# define machine_is_bonsai() (0) -#endif - -#ifdef CONFIG_MACH_ADSMILGATO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSMILGATO -# endif -# define machine_is_adsmilgato() (machine_arch_type == MACH_TYPE_ADSMILGATO) -#else -# define machine_is_adsmilgato() (0) -#endif - -#ifdef CONFIG_MACH_GBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GBA -# endif -# define machine_is_gba() (machine_arch_type == MACH_TYPE_GBA) -#else -# define machine_is_gba() (0) -#endif - -#ifdef CONFIG_MACH_H6044 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6044 -# endif -# define machine_is_h6044() (machine_arch_type == MACH_TYPE_H6044) -#else -# define machine_is_h6044() (0) -#endif - -#ifdef CONFIG_MACH_APP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APP -# endif -# define machine_is_app() (machine_arch_type == MACH_TYPE_APP) -#else -# define machine_is_app() (0) -#endif - -#ifdef CONFIG_MACH_TCT_HAMMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCT_HAMMER -# endif -# define machine_is_tct_hammer() (machine_arch_type == MACH_TYPE_TCT_HAMMER) -#else -# define machine_is_tct_hammer() (0) -#endif - -#ifdef CONFIG_MACH_HERALD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERALD -# endif -# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD) -#else -# define machine_is_herald() (0) -#endif - -#ifdef CONFIG_MACH_ARTEMIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARTEMIS -# endif -# define machine_is_artemis() (machine_arch_type == MACH_TYPE_ARTEMIS) -#else -# define machine_is_artemis() (0) -#endif - -#ifdef CONFIG_MACH_HTCTITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCTITAN -# endif -# define machine_is_htctitan() (machine_arch_type == MACH_TYPE_HTCTITAN) -#else -# define machine_is_htctitan() (0) -#endif - -#ifdef CONFIG_MACH_QRANIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QRANIUM -# endif -# define machine_is_qranium() (machine_arch_type == MACH_TYPE_QRANIUM) -#else -# define machine_is_qranium() (0) -#endif - -#ifdef CONFIG_MACH_ADX_WSC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_WSC2 -# endif -# define machine_is_adx_wsc2() (machine_arch_type == MACH_TYPE_ADX_WSC2) -#else -# define machine_is_adx_wsc2() (0) -#endif - -#ifdef CONFIG_MACH_ADX_MEDCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_MEDCOM -# endif -# define machine_is_adx_medcom() (machine_arch_type == MACH_TYPE_ADX_MEDCOM) -#else -# define machine_is_adx_medcom() (0) -#endif - -#ifdef CONFIG_MACH_BBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBOARD -# endif -# define machine_is_bboard() (machine_arch_type == MACH_TYPE_BBOARD) -#else -# define machine_is_bboard() (0) -#endif - -#ifdef CONFIG_MACH_CAMBRIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMBRIA -# endif -# define machine_is_cambria() (machine_arch_type == MACH_TYPE_CAMBRIA) -#else -# define machine_is_cambria() (0) -#endif - -#ifdef CONFIG_MACH_MT7XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT7XXX -# endif -# define machine_is_mt7xxx() (machine_arch_type == MACH_TYPE_MT7XXX) -#else -# define machine_is_mt7xxx() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX512 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX512 -# endif -# define machine_is_matrix512() (machine_arch_type == MACH_TYPE_MATRIX512) -#else -# define machine_is_matrix512() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX522 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX522 -# endif -# define machine_is_matrix522() (machine_arch_type == MACH_TYPE_MATRIX522) -#else -# define machine_is_matrix522() (0) -#endif - -#ifdef CONFIG_MACH_IPAC5010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPAC5010 -# endif -# define machine_is_ipac5010() (machine_arch_type == MACH_TYPE_IPAC5010) -#else -# define machine_is_ipac5010() (0) -#endif - -#ifdef CONFIG_MACH_SAKURA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAKURA -# endif -# define machine_is_sakura() (machine_arch_type == MACH_TYPE_SAKURA) -#else -# define machine_is_sakura() (0) -#endif - -#ifdef CONFIG_MACH_GROCX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GROCX -# endif -# define machine_is_grocx() (machine_arch_type == MACH_TYPE_GROCX) -#else -# define machine_is_grocx() (0) -#endif - -#ifdef CONFIG_MACH_PM9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM9263 -# endif -# define machine_is_pm9263() (machine_arch_type == MACH_TYPE_PM9263) -#else -# define machine_is_pm9263() (0) -#endif - -#ifdef CONFIG_MACH_SIM_ONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIM_ONE -# endif -# define machine_is_sim_one() (machine_arch_type == MACH_TYPE_SIM_ONE) -#else -# define machine_is_sim_one() (0) -#endif - -#ifdef CONFIG_MACH_ACQ132 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ132 -# endif -# define machine_is_acq132() (machine_arch_type == MACH_TYPE_ACQ132) -#else -# define machine_is_acq132() (0) -#endif - -#ifdef CONFIG_MACH_DATR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DATR -# endif -# define machine_is_datr() (machine_arch_type == MACH_TYPE_DATR) -#else -# define machine_is_datr() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX1 -# endif -# define machine_is_actux1() (machine_arch_type == MACH_TYPE_ACTUX1) -#else -# define machine_is_actux1() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX2 -# endif -# define machine_is_actux2() (machine_arch_type == MACH_TYPE_ACTUX2) -#else -# define machine_is_actux2() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX3 -# endif -# define machine_is_actux3() (machine_arch_type == MACH_TYPE_ACTUX3) -#else -# define machine_is_actux3() (0) -#endif - -#ifdef CONFIG_MACH_FLEXIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXIT -# endif -# define machine_is_flexit() (machine_arch_type == MACH_TYPE_FLEXIT) -#else -# define machine_is_flexit() (0) -#endif - -#ifdef CONFIG_MACH_BH2X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BH2X0BD -# endif -# define machine_is_bh2x0bd() (machine_arch_type == MACH_TYPE_BH2X0BD) -#else -# define machine_is_bh2x0bd() (0) -#endif - -#ifdef CONFIG_MACH_ATB2002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATB2002 -# endif -# define machine_is_atb2002() (machine_arch_type == MACH_TYPE_ATB2002) -#else -# define machine_is_atb2002() (0) -#endif - -#ifdef CONFIG_MACH_XENON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XENON -# endif -# define machine_is_xenon() (machine_arch_type == MACH_TYPE_XENON) -#else -# define machine_is_xenon() (0) -#endif - -#ifdef CONFIG_MACH_FM607 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FM607 -# endif -# define machine_is_fm607() (machine_arch_type == MACH_TYPE_FM607) -#else -# define machine_is_fm607() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX514 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX514 -# endif -# define machine_is_matrix514() (machine_arch_type == MACH_TYPE_MATRIX514) -#else -# define machine_is_matrix514() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX524 -# endif -# define machine_is_matrix524() (machine_arch_type == MACH_TYPE_MATRIX524) -#else -# define machine_is_matrix524() (0) -#endif - -#ifdef CONFIG_MACH_INPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INPOD -# endif -# define machine_is_inpod() (machine_arch_type == MACH_TYPE_INPOD) -#else -# define machine_is_inpod() (0) -#endif - -#ifdef CONFIG_MACH_JIVE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JIVE -# endif -# define machine_is_jive() (machine_arch_type == MACH_TYPE_JIVE) -#else -# define machine_is_jive() (0) -#endif - -#ifdef CONFIG_MACH_TLL_MX21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLL_MX21 -# endif -# define machine_is_tll_mx21() (machine_arch_type == MACH_TYPE_TLL_MX21) -#else -# define machine_is_tll_mx21() (0) -#endif - -#ifdef CONFIG_MACH_SBC2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2800 -# endif -# define machine_is_sbc2800() (machine_arch_type == MACH_TYPE_SBC2800) -#else -# define machine_is_sbc2800() (0) -#endif - -#ifdef CONFIG_MACH_CC7UCAMRY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC7UCAMRY -# endif -# define machine_is_cc7ucamry() (machine_arch_type == MACH_TYPE_CC7UCAMRY) -#else -# define machine_is_cc7ucamry() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SC15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SC15 -# endif -# define machine_is_ubisys_p9_sc15() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC15) -#else -# define machine_is_ubisys_p9_sc15() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SSC2D10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SSC2D10 -# endif -# define machine_is_ubisys_p9_ssc2d10() (machine_arch_type == MACH_TYPE_UBISYS_P9_SSC2D10) -#else -# define machine_is_ubisys_p9_ssc2d10() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_RCU3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_RCU3 -# endif -# define machine_is_ubisys_p9_rcu3() (machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3) -#else -# define machine_is_ubisys_p9_rcu3() (0) -#endif - -#ifdef CONFIG_MACH_AML_M8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M8000 -# endif -# define machine_is_aml_m8000() (machine_arch_type == MACH_TYPE_AML_M8000) -#else -# define machine_is_aml_m8000() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_270 -# endif -# define machine_is_snapper_270() (machine_arch_type == MACH_TYPE_SNAPPER_270) -#else -# define machine_is_snapper_270() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_BBX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_BBX -# endif -# define machine_is_omap_bbx() (machine_arch_type == MACH_TYPE_OMAP_BBX) -#else -# define machine_is_omap_bbx() (0) -#endif - -#ifdef CONFIG_MACH_UCN2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCN2410 -# endif -# define machine_is_ucn2410() (machine_arch_type == MACH_TYPE_UCN2410) -#else -# define machine_is_ucn2410() (0) -#endif - -#ifdef CONFIG_MACH_SAM9_L9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9_L9260 -# endif -# define machine_is_sam9_l9260() (machine_arch_type == MACH_TYPE_SAM9_L9260) -#else -# define machine_is_sam9_l9260() (0) -#endif - -#ifdef CONFIG_MACH_ETI_C2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_C2 -# endif -# define machine_is_eti_c2() (machine_arch_type == MACH_TYPE_ETI_C2) -#else -# define machine_is_eti_c2() (0) -#endif - -#ifdef CONFIG_MACH_AVALANCHE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVALANCHE -# endif -# define machine_is_avalanche() (machine_arch_type == MACH_TYPE_AVALANCHE) -#else -# define machine_is_avalanche() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PB1176 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PB1176 -# endif -# define machine_is_realview_pb1176() (machine_arch_type == MACH_TYPE_REALVIEW_PB1176) -#else -# define machine_is_realview_pb1176() (0) -#endif - -#ifdef CONFIG_MACH_DP1500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP1500 -# endif -# define machine_is_dp1500() (machine_arch_type == MACH_TYPE_DP1500) -#else -# define machine_is_dp1500() (0) -#endif - -#ifdef CONFIG_MACH_APPLE_IPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APPLE_IPHONE -# endif -# define machine_is_apple_iphone() (machine_arch_type == MACH_TYPE_APPLE_IPHONE) -#else -# define machine_is_apple_iphone() (0) -#endif - -#ifdef CONFIG_MACH_YL9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YL9200 -# endif -# define machine_is_yl9200() (machine_arch_type == MACH_TYPE_YL9200) -#else -# define machine_is_yl9200() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5182 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5182 -# endif -# define machine_is_rd88f5182() (machine_arch_type == MACH_TYPE_RD88F5182) -#else -# define machine_is_rd88f5182() (0) -#endif - -#ifdef CONFIG_MACH_KUROBOX_PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KUROBOX_PRO -# endif -# define machine_is_kurobox_pro() (machine_arch_type == MACH_TYPE_KUROBOX_PRO) -#else -# define machine_is_kurobox_pro() (0) -#endif - -#ifdef CONFIG_MACH_SE_POET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE_POET -# endif -# define machine_is_se_poet() (machine_arch_type == MACH_TYPE_SE_POET) -#else -# define machine_is_se_poet() (0) -#endif - -#ifdef CONFIG_MACH_MX31_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31_3DS -# endif -# define machine_is_mx31_3ds() (machine_arch_type == MACH_TYPE_MX31_3DS) -#else -# define machine_is_mx31_3ds() (0) -#endif - -#ifdef CONFIG_MACH_R270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_R270 -# endif -# define machine_is_r270() (machine_arch_type == MACH_TYPE_R270) -#else -# define machine_is_r270() (0) -#endif - -#ifdef CONFIG_MACH_ARMOUR21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMOUR21 -# endif -# define machine_is_armour21() (machine_arch_type == MACH_TYPE_ARMOUR21) -#else -# define machine_is_armour21() (0) -#endif - -#ifdef CONFIG_MACH_DT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DT2 -# endif -# define machine_is_dt2() (machine_arch_type == MACH_TYPE_DT2) -#else -# define machine_is_dt2() (0) -#endif - -#ifdef CONFIG_MACH_VT4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VT4 -# endif -# define machine_is_vt4() (machine_arch_type == MACH_TYPE_VT4) -#else -# define machine_is_vt4() (0) -#endif - -#ifdef CONFIG_MACH_TYCO320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TYCO320 -# endif -# define machine_is_tyco320() (machine_arch_type == MACH_TYPE_TYCO320) -#else -# define machine_is_tyco320() (0) -#endif - -#ifdef CONFIG_MACH_ADMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADMA -# endif -# define machine_is_adma() (machine_arch_type == MACH_TYPE_ADMA) -#else -# define machine_is_adma() (0) -#endif - -#ifdef CONFIG_MACH_WP188 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WP188 -# endif -# define machine_is_wp188() (machine_arch_type == MACH_TYPE_WP188) -#else -# define machine_is_wp188() (0) -#endif - -#ifdef CONFIG_MACH_CORSICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORSICA -# endif -# define machine_is_corsica() (machine_arch_type == MACH_TYPE_CORSICA) -#else -# define machine_is_corsica() (0) -#endif - -#ifdef CONFIG_MACH_BIGEYE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIGEYE -# endif -# define machine_is_bigeye() (machine_arch_type == MACH_TYPE_BIGEYE) -#else -# define machine_is_bigeye() (0) -#endif - -#ifdef CONFIG_MACH_TLL5000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLL5000 -# endif -# define machine_is_tll5000() (machine_arch_type == MACH_TYPE_TLL5000) -#else -# define machine_is_tll5000() (0) -#endif - -#ifdef CONFIG_MACH_BEBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEBOT -# endif -# define machine_is_bebot() (machine_arch_type == MACH_TYPE_BEBOT) -#else -# define machine_is_bebot() (0) -#endif - -#ifdef CONFIG_MACH_QONG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QONG -# endif -# define machine_is_qong() (machine_arch_type == MACH_TYPE_QONG) -#else -# define machine_is_qong() (0) -#endif - -#ifdef CONFIG_MACH_TCOMPACT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCOMPACT -# endif -# define machine_is_tcompact() (machine_arch_type == MACH_TYPE_TCOMPACT) -#else -# define machine_is_tcompact() (0) -#endif - -#ifdef CONFIG_MACH_PUMA5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUMA5 -# endif -# define machine_is_puma5() (machine_arch_type == MACH_TYPE_PUMA5) -#else -# define machine_is_puma5() (0) -#endif - -#ifdef CONFIG_MACH_ELARA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELARA -# endif -# define machine_is_elara() (machine_arch_type == MACH_TYPE_ELARA) -#else -# define machine_is_elara() (0) -#endif - -#ifdef CONFIG_MACH_ELLINGTON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELLINGTON -# endif -# define machine_is_ellington() (machine_arch_type == MACH_TYPE_ELLINGTON) -#else -# define machine_is_ellington() (0) -#endif - -#ifdef CONFIG_MACH_XDA_ATOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDA_ATOM -# endif -# define machine_is_xda_atom() (machine_arch_type == MACH_TYPE_XDA_ATOM) -#else -# define machine_is_xda_atom() (0) -#endif - -#ifdef CONFIG_MACH_ENERGIZER2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENERGIZER2 -# endif -# define machine_is_energizer2() (machine_arch_type == MACH_TYPE_ENERGIZER2) -#else -# define machine_is_energizer2() (0) -#endif - -#ifdef CONFIG_MACH_ODIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ODIN -# endif -# define machine_is_odin() (machine_arch_type == MACH_TYPE_ODIN) -#else -# define machine_is_odin() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX4 -# endif -# define machine_is_actux4() (machine_arch_type == MACH_TYPE_ACTUX4) -#else -# define machine_is_actux4() (0) -#endif - -#ifdef CONFIG_MACH_ESL_OMAP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_OMAP -# endif -# define machine_is_esl_omap() (machine_arch_type == MACH_TYPE_ESL_OMAP) -#else -# define machine_is_esl_omap() (0) -#endif - -#ifdef CONFIG_MACH_OMAP2EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP2EVM -# endif -# define machine_is_omap2evm() (machine_arch_type == MACH_TYPE_OMAP2EVM) -#else -# define machine_is_omap2evm() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3EVM -# endif -# define machine_is_omap3evm() (machine_arch_type == MACH_TYPE_OMAP3EVM) -#else -# define machine_is_omap3evm() (0) -#endif - -#ifdef CONFIG_MACH_ADX_PCU57 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_PCU57 -# endif -# define machine_is_adx_pcu57() (machine_arch_type == MACH_TYPE_ADX_PCU57) -#else -# define machine_is_adx_pcu57() (0) -#endif - -#ifdef CONFIG_MACH_MONACO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MONACO -# endif -# define machine_is_monaco() (machine_arch_type == MACH_TYPE_MONACO) -#else -# define machine_is_monaco() (0) -#endif - -#ifdef CONFIG_MACH_LEVANTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEVANTE -# endif -# define machine_is_levante() (machine_arch_type == MACH_TYPE_LEVANTE) -#else -# define machine_is_levante() (0) -#endif - -#ifdef CONFIG_MACH_TMXIPX425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TMXIPX425 -# endif -# define machine_is_tmxipx425() (machine_arch_type == MACH_TYPE_TMXIPX425) -#else -# define machine_is_tmxipx425() (0) -#endif - -#ifdef CONFIG_MACH_LEEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEEP -# endif -# define machine_is_leep() (machine_arch_type == MACH_TYPE_LEEP) -#else -# define machine_is_leep() (0) -#endif - -#ifdef CONFIG_MACH_RAAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAAD -# endif -# define machine_is_raad() (machine_arch_type == MACH_TYPE_RAAD) -#else -# define machine_is_raad() (0) -#endif - -#ifdef CONFIG_MACH_DNS323 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DNS323 -# endif -# define machine_is_dns323() (machine_arch_type == MACH_TYPE_DNS323) -#else -# define machine_is_dns323() (0) -#endif - -#ifdef CONFIG_MACH_AP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AP1000 -# endif -# define machine_is_ap1000() (machine_arch_type == MACH_TYPE_AP1000) -#else -# define machine_is_ap1000() (0) -#endif - -#ifdef CONFIG_MACH_A9SAM6432 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9SAM6432 -# endif -# define machine_is_a9sam6432() (machine_arch_type == MACH_TYPE_A9SAM6432) -#else -# define machine_is_a9sam6432() (0) -#endif - -#ifdef CONFIG_MACH_SHINY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHINY -# endif -# define machine_is_shiny() (machine_arch_type == MACH_TYPE_SHINY) -#else -# define machine_is_shiny() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BEAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BEAGLE -# endif -# define machine_is_omap3_beagle() (machine_arch_type == MACH_TYPE_OMAP3_BEAGLE) -#else -# define machine_is_omap3_beagle() (0) -#endif - -#ifdef CONFIG_MACH_CSR_BDB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSR_BDB2 -# endif -# define machine_is_csr_bdb2() (machine_arch_type == MACH_TYPE_CSR_BDB2) -#else -# define machine_is_csr_bdb2() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N810 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N810 -# endif -# define machine_is_nokia_n810() (machine_arch_type == MACH_TYPE_NOKIA_N810) -#else -# define machine_is_nokia_n810() (0) -#endif - -#ifdef CONFIG_MACH_C270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C270 -# endif -# define machine_is_c270() (machine_arch_type == MACH_TYPE_C270) -#else -# define machine_is_c270() (0) -#endif - -#ifdef CONFIG_MACH_SENTRY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SENTRY -# endif -# define machine_is_sentry() (machine_arch_type == MACH_TYPE_SENTRY) -#else -# define machine_is_sentry() (0) -#endif - -#ifdef CONFIG_MACH_PCM038 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM038 -# endif -# define machine_is_pcm038() (machine_arch_type == MACH_TYPE_PCM038) -#else -# define machine_is_pcm038() (0) -#endif - -#ifdef CONFIG_MACH_ANC300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANC300 -# endif -# define machine_is_anc300() (machine_arch_type == MACH_TYPE_ANC300) -#else -# define machine_is_anc300() (0) -#endif - -#ifdef CONFIG_MACH_HTCKAISER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCKAISER -# endif -# define machine_is_htckaiser() (machine_arch_type == MACH_TYPE_HTCKAISER) -#else -# define machine_is_htckaiser() (0) -#endif - -#ifdef CONFIG_MACH_SBAT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBAT100 -# endif -# define machine_is_sbat100() (machine_arch_type == MACH_TYPE_SBAT100) -#else -# define machine_is_sbat100() (0) -#endif - -#ifdef CONFIG_MACH_MODUNORM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MODUNORM -# endif -# define machine_is_modunorm() (machine_arch_type == MACH_TYPE_MODUNORM) -#else -# define machine_is_modunorm() (0) -#endif - -#ifdef CONFIG_MACH_PELOS_TWARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELOS_TWARM -# endif -# define machine_is_pelos_twarm() (machine_arch_type == MACH_TYPE_PELOS_TWARM) -#else -# define machine_is_pelos_twarm() (0) -#endif - -#ifdef CONFIG_MACH_FLANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLANK -# endif -# define machine_is_flank() (machine_arch_type == MACH_TYPE_FLANK) -#else -# define machine_is_flank() (0) -#endif - -#ifdef CONFIG_MACH_SIRLOIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIRLOIN -# endif -# define machine_is_sirloin() (machine_arch_type == MACH_TYPE_SIRLOIN) -#else -# define machine_is_sirloin() (0) -#endif - -#ifdef CONFIG_MACH_BRISKET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRISKET -# endif -# define machine_is_brisket() (machine_arch_type == MACH_TYPE_BRISKET) -#else -# define machine_is_brisket() (0) -#endif - -#ifdef CONFIG_MACH_CHUCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUCK -# endif -# define machine_is_chuck() (machine_arch_type == MACH_TYPE_CHUCK) -#else -# define machine_is_chuck() (0) -#endif - -#ifdef CONFIG_MACH_OTTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTTER -# endif -# define machine_is_otter() (machine_arch_type == MACH_TYPE_OTTER) -#else -# define machine_is_otter() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_LDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_LDK -# endif -# define machine_is_davinci_ldk() (machine_arch_type == MACH_TYPE_DAVINCI_LDK) -#else -# define machine_is_davinci_ldk() (0) -#endif - -#ifdef CONFIG_MACH_PHREEDOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHREEDOM -# endif -# define machine_is_phreedom() (machine_arch_type == MACH_TYPE_PHREEDOM) -#else -# define machine_is_phreedom() (0) -#endif - -#ifdef CONFIG_MACH_SG310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG310 -# endif -# define machine_is_sg310() (machine_arch_type == MACH_TYPE_SG310) -#else -# define machine_is_sg310() (0) -#endif - -#ifdef CONFIG_MACH_TS209 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS209 -# endif -# define machine_is_ts_x09() (machine_arch_type == MACH_TYPE_TS209) -#else -# define machine_is_ts_x09() (0) -#endif - -#ifdef CONFIG_MACH_AT91CAP9ADK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91CAP9ADK -# endif -# define machine_is_at91cap9adk() (machine_arch_type == MACH_TYPE_AT91CAP9ADK) -#else -# define machine_is_at91cap9adk() (0) -#endif - -#ifdef CONFIG_MACH_TION9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TION9315 -# endif -# define machine_is_tion9315() (machine_arch_type == MACH_TYPE_TION9315) -#else -# define machine_is_tion9315() (0) -#endif - -#ifdef CONFIG_MACH_MAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAST -# endif -# define machine_is_mast() (machine_arch_type == MACH_TYPE_MAST) -#else -# define machine_is_mast() (0) -#endif - -#ifdef CONFIG_MACH_PFW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PFW -# endif -# define machine_is_pfw() (machine_arch_type == MACH_TYPE_PFW) -#else -# define machine_is_pfw() (0) -#endif - -#ifdef CONFIG_MACH_YL_P2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YL_P2440 -# endif -# define machine_is_yl_p2440() (machine_arch_type == MACH_TYPE_YL_P2440) -#else -# define machine_is_yl_p2440() (0) -#endif - -#ifdef CONFIG_MACH_ZSBC32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZSBC32 -# endif -# define machine_is_zsbc32() (machine_arch_type == MACH_TYPE_ZSBC32) -#else -# define machine_is_zsbc32() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PACE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PACE2 -# endif -# define machine_is_omap_pace2() (machine_arch_type == MACH_TYPE_OMAP_PACE2) -#else -# define machine_is_omap_pace2() (0) -#endif - -#ifdef CONFIG_MACH_IMX_PACE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX_PACE2 -# endif -# define machine_is_imx_pace2() (machine_arch_type == MACH_TYPE_IMX_PACE2) -#else -# define machine_is_imx_pace2() (0) -#endif - -#ifdef CONFIG_MACH_MX31MOBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31MOBOARD -# endif -# define machine_is_mx31moboard() (machine_arch_type == MACH_TYPE_MX31MOBOARD) -#else -# define machine_is_mx31moboard() (0) -#endif - -#ifdef CONFIG_MACH_MX37_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX37_3DS -# endif -# define machine_is_mx37_3ds() (machine_arch_type == MACH_TYPE_MX37_3DS) -#else -# define machine_is_mx37_3ds() (0) -#endif - -#ifdef CONFIG_MACH_RCC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RCC -# endif -# define machine_is_rcc() (machine_arch_type == MACH_TYPE_RCC) -#else -# define machine_is_rcc() (0) -#endif - -#ifdef CONFIG_MACH_ARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM9 -# endif -# define machine_is_dmp() (machine_arch_type == MACH_TYPE_ARM9) -#else -# define machine_is_dmp() (0) -#endif - -#ifdef CONFIG_MACH_VISION_EP9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VISION_EP9307 -# endif -# define machine_is_vision_ep9307() (machine_arch_type == MACH_TYPE_VISION_EP9307) -#else -# define machine_is_vision_ep9307() (0) -#endif - -#ifdef CONFIG_MACH_SCLY1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCLY1000 -# endif -# define machine_is_scly1000() (machine_arch_type == MACH_TYPE_SCLY1000) -#else -# define machine_is_scly1000() (0) -#endif - -#ifdef CONFIG_MACH_FONTEL_EP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FONTEL_EP -# endif -# define machine_is_fontel_ep() (machine_arch_type == MACH_TYPE_FONTEL_EP) -#else -# define machine_is_fontel_ep() (0) -#endif - -#ifdef CONFIG_MACH_VOICEBLUE3G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOICEBLUE3G -# endif -# define machine_is_voiceblue3g() (machine_arch_type == MACH_TYPE_VOICEBLUE3G) -#else -# define machine_is_voiceblue3g() (0) -#endif - -#ifdef CONFIG_MACH_TT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT9200 -# endif -# define machine_is_tt9200() (machine_arch_type == MACH_TYPE_TT9200) -#else -# define machine_is_tt9200() (0) -#endif - -#ifdef CONFIG_MACH_DIGI2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIGI2410 -# endif -# define machine_is_digi2410() (machine_arch_type == MACH_TYPE_DIGI2410) -#else -# define machine_is_digi2410() (0) -#endif - -#ifdef CONFIG_MACH_TERASTATION_PRO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERASTATION_PRO2 -# endif -# define machine_is_terastation_pro2() (machine_arch_type == MACH_TYPE_TERASTATION_PRO2) -#else -# define machine_is_terastation_pro2() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_PRO -# endif -# define machine_is_linkstation_pro() (machine_arch_type == MACH_TYPE_LINKSTATION_PRO) -#else -# define machine_is_linkstation_pro() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_A780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_A780 -# endif -# define machine_is_motorola_a780() (machine_arch_type == MACH_TYPE_MOTOROLA_A780) -#else -# define machine_is_motorola_a780() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E6 -# endif -# define machine_is_motorola_e6() (machine_arch_type == MACH_TYPE_MOTOROLA_E6) -#else -# define machine_is_motorola_e6() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E2 -# endif -# define machine_is_motorola_e2() (machine_arch_type == MACH_TYPE_MOTOROLA_E2) -#else -# define machine_is_motorola_e2() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E680 -# endif -# define machine_is_motorola_e680() (machine_arch_type == MACH_TYPE_MOTOROLA_E680) -#else -# define machine_is_motorola_e680() (0) -#endif - -#ifdef CONFIG_MACH_UR2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UR2410 -# endif -# define machine_is_ur2410() (machine_arch_type == MACH_TYPE_UR2410) -#else -# define machine_is_ur2410() (0) -#endif - -#ifdef CONFIG_MACH_TAS9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAS9261 -# endif -# define machine_is_tas9261() (machine_arch_type == MACH_TYPE_TAS9261) -#else -# define machine_is_tas9261() (0) -#endif - -#ifdef CONFIG_MACH_HERMES_HD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERMES_HD -# endif -# define machine_is_davinci_hermes_hd() (machine_arch_type == MACH_TYPE_HERMES_HD) -#else -# define machine_is_davinci_hermes_hd() (0) -#endif - -#ifdef CONFIG_MACH_PERSEO_HD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERSEO_HD -# endif -# define machine_is_davinci_perseo_hd() (machine_arch_type == MACH_TYPE_PERSEO_HD) -#else -# define machine_is_davinci_perseo_hd() (0) -#endif - -#ifdef CONFIG_MACH_STARGAZER2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGAZER2 -# endif -# define machine_is_stargazer2() (machine_arch_type == MACH_TYPE_STARGAZER2) -#else -# define machine_is_stargazer2() (0) -#endif - -#ifdef CONFIG_MACH_E350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E350 -# endif -# define machine_is_e350() (machine_arch_type == MACH_TYPE_E350) -#else -# define machine_is_e350() (0) -#endif - -#ifdef CONFIG_MACH_WPCM450 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WPCM450 -# endif -# define machine_is_wpcm450() (machine_arch_type == MACH_TYPE_WPCM450) -#else -# define machine_is_wpcm450() (0) -#endif - -#ifdef CONFIG_MACH_CARTESIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARTESIO -# endif -# define machine_is_cartesio() (machine_arch_type == MACH_TYPE_CARTESIO) -#else -# define machine_is_cartesio() (0) -#endif - -#ifdef CONFIG_MACH_TOYBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOYBOX -# endif -# define machine_is_toybox() (machine_arch_type == MACH_TYPE_TOYBOX) -#else -# define machine_is_toybox() (0) -#endif - -#ifdef CONFIG_MACH_TX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX27 -# endif -# define machine_is_tx27() (machine_arch_type == MACH_TYPE_TX27) -#else -# define machine_is_tx27() (0) -#endif - -#ifdef CONFIG_MACH_TS409 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS409 -# endif -# define machine_is_ts409() (machine_arch_type == MACH_TYPE_TS409) -#else -# define machine_is_ts409() (0) -#endif - -#ifdef CONFIG_MACH_P300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P300 -# endif -# define machine_is_p300() (machine_arch_type == MACH_TYPE_P300) -#else -# define machine_is_p300() (0) -#endif - -#ifdef CONFIG_MACH_XDACOMET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDACOMET -# endif -# define machine_is_xdacomet() (machine_arch_type == MACH_TYPE_XDACOMET) -#else -# define machine_is_xdacomet() (0) -#endif - -#ifdef CONFIG_MACH_DEXFLEX2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEXFLEX2 -# endif -# define machine_is_dexflex2() (machine_arch_type == MACH_TYPE_DEXFLEX2) -#else -# define machine_is_dexflex2() (0) -#endif - -#ifdef CONFIG_MACH_OW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OW -# endif -# define machine_is_ow() (machine_arch_type == MACH_TYPE_OW) -#else -# define machine_is_ow() (0) -#endif - -#ifdef CONFIG_MACH_ARMEBS3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMEBS3 -# endif -# define machine_is_armebs3() (machine_arch_type == MACH_TYPE_ARMEBS3) -#else -# define machine_is_armebs3() (0) -#endif - -#ifdef CONFIG_MACH_U3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U3 -# endif -# define machine_is_u3() (machine_arch_type == MACH_TYPE_U3) -#else -# define machine_is_u3() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2450 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2450 -# endif -# define machine_is_smdk2450() (machine_arch_type == MACH_TYPE_SMDK2450) -#else -# define machine_is_smdk2450() (0) -#endif - -#ifdef CONFIG_MACH_RSI_EWS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSI_EWS -# endif -# define machine_is_rsi_ews() (machine_arch_type == MACH_TYPE_RSI_EWS) -#else -# define machine_is_rsi_ews() (0) -#endif - -#ifdef CONFIG_MACH_TNB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNB -# endif -# define machine_is_tnb() (machine_arch_type == MACH_TYPE_TNB) -#else -# define machine_is_tnb() (0) -#endif - -#ifdef CONFIG_MACH_TOEPATH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOEPATH -# endif -# define machine_is_toepath() (machine_arch_type == MACH_TYPE_TOEPATH) -#else -# define machine_is_toepath() (0) -#endif - -#ifdef CONFIG_MACH_KB9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9263 -# endif -# define machine_is_kb9263() (machine_arch_type == MACH_TYPE_KB9263) -#else -# define machine_is_kb9263() (0) -#endif - -#ifdef CONFIG_MACH_MT7108 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT7108 -# endif -# define machine_is_mt7108() (machine_arch_type == MACH_TYPE_MT7108) -#else -# define machine_is_mt7108() (0) -#endif - -#ifdef CONFIG_MACH_SMTR2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMTR2440 -# endif -# define machine_is_smtr2440() (machine_arch_type == MACH_TYPE_SMTR2440) -#else -# define machine_is_smtr2440() (0) -#endif - -#ifdef CONFIG_MACH_MANAO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MANAO -# endif -# define machine_is_manao() (machine_arch_type == MACH_TYPE_MANAO) -#else -# define machine_is_manao() (0) -#endif - -#ifdef CONFIG_MACH_CM_X300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X300 -# endif -# define machine_is_cm_x300() (machine_arch_type == MACH_TYPE_CM_X300) -#else -# define machine_is_cm_x300() (0) -#endif - -#ifdef CONFIG_MACH_GULFSTREAM_KP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GULFSTREAM_KP -# endif -# define machine_is_gulfstream_kp() (machine_arch_type == MACH_TYPE_GULFSTREAM_KP) -#else -# define machine_is_gulfstream_kp() (0) -#endif - -#ifdef CONFIG_MACH_LANREADYFN522 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LANREADYFN522 -# endif -# define machine_is_lanreadyfn522() (machine_arch_type == MACH_TYPE_LANREADYFN522) -#else -# define machine_is_lanreadyfn522() (0) -#endif - -#ifdef CONFIG_MACH_ARMA37 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMA37 -# endif -# define machine_is_arma37() (machine_arch_type == MACH_TYPE_ARMA37) -#else -# define machine_is_arma37() (0) -#endif - -#ifdef CONFIG_MACH_MENDEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MENDEL -# endif -# define machine_is_mendel() (machine_arch_type == MACH_TYPE_MENDEL) -#else -# define machine_is_mendel() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ILIAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ILIAD -# endif -# define machine_is_pelco_iliad() (machine_arch_type == MACH_TYPE_PELCO_ILIAD) -#else -# define machine_is_pelco_iliad() (0) -#endif - -#ifdef CONFIG_MACH_UNIT2P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIT2P -# endif -# define machine_is_unit2p() (machine_arch_type == MACH_TYPE_UNIT2P) -#else -# define machine_is_unit2p() (0) -#endif - -#ifdef CONFIG_MACH_INC20OTTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INC20OTTER -# endif -# define machine_is_inc20otter() (machine_arch_type == MACH_TYPE_INC20OTTER) -#else -# define machine_is_inc20otter() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20EK -# endif -# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK) -#else -# define machine_is_at91sam9g20ek() (0) -#endif - -#ifdef CONFIG_MACH_STORCENTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORCENTER -# endif -# define machine_is_sc_ge2() (machine_arch_type == MACH_TYPE_STORCENTER) -#else -# define machine_is_sc_ge2() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6410 -# endif -# define machine_is_smdk6410() (machine_arch_type == MACH_TYPE_SMDK6410) -#else -# define machine_is_smdk6410() (0) -#endif - -#ifdef CONFIG_MACH_U300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U300 -# endif -# define machine_is_u300() (machine_arch_type == MACH_TYPE_U300) -#else -# define machine_is_u300() (0) -#endif - -#ifdef CONFIG_MACH_U500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U500 -# endif -# define machine_is_u500() (machine_arch_type == MACH_TYPE_U500) -#else -# define machine_is_u500() (0) -#endif - -#ifdef CONFIG_MACH_DS9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS9260 -# endif -# define machine_is_ds9260() (machine_arch_type == MACH_TYPE_DS9260) -#else -# define machine_is_ds9260() (0) -#endif - -#ifdef CONFIG_MACH_RIVERROCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIVERROCK -# endif -# define machine_is_riverrock() (machine_arch_type == MACH_TYPE_RIVERROCK) -#else -# define machine_is_riverrock() (0) -#endif - -#ifdef CONFIG_MACH_SCIBATH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCIBATH -# endif -# define machine_is_scibath() (machine_arch_type == MACH_TYPE_SCIBATH) -#else -# define machine_is_scibath() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM7SE512EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM7SE512EK -# endif -# define machine_is_at91sam7se() (machine_arch_type == MACH_TYPE_AT91SAM7SE512EK) -#else -# define machine_is_at91sam7se() (0) -#endif - -#ifdef CONFIG_MACH_WRT350N_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRT350N_V2 -# endif -# define machine_is_wrt350n_v2() (machine_arch_type == MACH_TYPE_WRT350N_V2) -#else -# define machine_is_wrt350n_v2() (0) -#endif - -#ifdef CONFIG_MACH_MULTIMEDIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIMEDIA -# endif -# define machine_is_multimedia() (machine_arch_type == MACH_TYPE_MULTIMEDIA) -#else -# define machine_is_multimedia() (0) -#endif - -#ifdef CONFIG_MACH_MARVIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVIN -# endif -# define machine_is_marvin() (machine_arch_type == MACH_TYPE_MARVIN) -#else -# define machine_is_marvin() (0) -#endif - -#ifdef CONFIG_MACH_X500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X500 -# endif -# define machine_is_x500() (machine_arch_type == MACH_TYPE_X500) -#else -# define machine_is_x500() (0) -#endif - -#ifdef CONFIG_MACH_AWLUG4LCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AWLUG4LCU -# endif -# define machine_is_awlug4lcu() (machine_arch_type == MACH_TYPE_AWLUG4LCU) -#else -# define machine_is_awlug4lcu() (0) -#endif - -#ifdef CONFIG_MACH_PALERMOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALERMOC -# endif -# define machine_is_palermoc() (machine_arch_type == MACH_TYPE_PALERMOC) -#else -# define machine_is_palermoc() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_LDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_LDP -# endif -# define machine_is_omap_ldp() (machine_arch_type == MACH_TYPE_OMAP_LDP) -#else -# define machine_is_omap_ldp() (0) -#endif - -#ifdef CONFIG_MACH_IP500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP500 -# endif -# define machine_is_ip500() (machine_arch_type == MACH_TYPE_IP500) -#else -# define machine_is_ip500() (0) -#endif - -#ifdef CONFIG_MACH_ASE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASE2 -# endif -# define machine_is_ase2() (machine_arch_type == MACH_TYPE_ASE2) -#else -# define machine_is_ase2() (0) -#endif - -#ifdef CONFIG_MACH_MX35EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35EVB -# endif -# define machine_is_mx35evb() (machine_arch_type == MACH_TYPE_MX35EVB) -#else -# define machine_is_mx35evb() (0) -#endif - -#ifdef CONFIG_MACH_AML_M8050 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M8050 -# endif -# define machine_is_aml_m8050() (machine_arch_type == MACH_TYPE_AML_M8050) -#else -# define machine_is_aml_m8050() (0) -#endif - -#ifdef CONFIG_MACH_MX35_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_3DS -# endif -# define machine_is_mx35_3ds() (machine_arch_type == MACH_TYPE_MX35_3DS) -#else -# define machine_is_mx35_3ds() (0) -#endif - -#ifdef CONFIG_MACH_MARS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARS -# endif -# define machine_is_mars() (machine_arch_type == MACH_TYPE_MARS) -#else -# define machine_is_mars() (0) -#endif - -#ifdef CONFIG_MACH_NEUROS_OSD2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEUROS_OSD2 -# endif -# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2) -#else -# define machine_is_neuros_osd2() (0) -#endif - -#ifdef CONFIG_MACH_BADGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BADGER -# endif -# define machine_is_badger() (machine_arch_type == MACH_TYPE_BADGER) -#else -# define machine_is_badger() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS4WL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS4WL -# endif -# define machine_is_trizeps4wl() (machine_arch_type == MACH_TYPE_TRIZEPS4WL) -#else -# define machine_is_trizeps4wl() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS5 -# endif -# define machine_is_trizeps5() (machine_arch_type == MACH_TYPE_TRIZEPS5) -#else -# define machine_is_trizeps5() (0) -#endif - -#ifdef CONFIG_MACH_MARLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARLIN -# endif -# define machine_is_marlin() (machine_arch_type == MACH_TYPE_MARLIN) -#else -# define machine_is_marlin() (0) -#endif - -#ifdef CONFIG_MACH_TS78XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS78XX -# endif -# define machine_is_ts78xx() (machine_arch_type == MACH_TYPE_TS78XX) -#else -# define machine_is_ts78xx() (0) -#endif - -#ifdef CONFIG_MACH_HPIPAQ214 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPIPAQ214 -# endif -# define machine_is_hpipaq214() (machine_arch_type == MACH_TYPE_HPIPAQ214) -#else -# define machine_is_hpipaq214() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940DCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940DCM -# endif -# define machine_is_at572d940dcm() (machine_arch_type == MACH_TYPE_AT572D940DCM) -#else -# define machine_is_at572d940dcm() (0) -#endif - -#ifdef CONFIG_MACH_NE1BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NE1BOARD -# endif -# define machine_is_ne1board() (machine_arch_type == MACH_TYPE_NE1BOARD) -#else -# define machine_is_ne1board() (0) -#endif - -#ifdef CONFIG_MACH_ZANTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZANTE -# endif -# define machine_is_zante() (machine_arch_type == MACH_TYPE_ZANTE) -#else -# define machine_is_zante() (0) -#endif - -#ifdef CONFIG_MACH_SFFSDR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFFSDR -# endif -# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) -#else -# define machine_is_sffsdr() (0) -#endif - -#ifdef CONFIG_MACH_TW2662 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TW2662 -# endif -# define machine_is_tw2662() (machine_arch_type == MACH_TYPE_TW2662) -#else -# define machine_is_tw2662() (0) -#endif - -#ifdef CONFIG_MACH_VF10XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VF10XX -# endif -# define machine_is_vf10xx() (machine_arch_type == MACH_TYPE_VF10XX) -#else -# define machine_is_vf10xx() (0) -#endif - -#ifdef CONFIG_MACH_ZORAN43XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZORAN43XX -# endif -# define machine_is_zoran43xx() (machine_arch_type == MACH_TYPE_ZORAN43XX) -#else -# define machine_is_zoran43xx() (0) -#endif - -#ifdef CONFIG_MACH_SONIX926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONIX926 -# endif -# define machine_is_sonix926() (machine_arch_type == MACH_TYPE_SONIX926) -#else -# define machine_is_sonix926() (0) -#endif - -#ifdef CONFIG_MACH_CELESTIALSEMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CELESTIALSEMI -# endif -# define machine_is_celestialsemi() (machine_arch_type == MACH_TYPE_CELESTIALSEMI) -#else -# define machine_is_celestialsemi() (0) -#endif - -#ifdef CONFIG_MACH_CC9M2443JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9M2443JS -# endif -# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) -#else -# define machine_is_cc9m2443js() (0) -#endif - -#ifdef CONFIG_MACH_TW5334 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TW5334 -# endif -# define machine_is_tw5334() (machine_arch_type == MACH_TYPE_TW5334) -#else -# define machine_is_tw5334() (0) -#endif - -#ifdef CONFIG_MACH_HTCARTEMIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCARTEMIS -# endif -# define machine_is_omap_htcartemis() (machine_arch_type == MACH_TYPE_HTCARTEMIS) -#else -# define machine_is_omap_htcartemis() (0) -#endif - -#ifdef CONFIG_MACH_NAL_HLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAL_HLITE -# endif -# define machine_is_nal_hlite() (machine_arch_type == MACH_TYPE_NAL_HLITE) -#else -# define machine_is_nal_hlite() (0) -#endif - -#ifdef CONFIG_MACH_HTCVOGUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCVOGUE -# endif -# define machine_is_htcvogue() (machine_arch_type == MACH_TYPE_HTCVOGUE) -#else -# define machine_is_htcvogue() (0) -#endif - -#ifdef CONFIG_MACH_SMARTWEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTWEB -# endif -# define machine_is_smartweb() (machine_arch_type == MACH_TYPE_SMARTWEB) -#else -# define machine_is_smartweb() (0) -#endif - -#ifdef CONFIG_MACH_MV86XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV86XX -# endif -# define machine_is_mv86xx() (machine_arch_type == MACH_TYPE_MV86XX) -#else -# define machine_is_mv86xx() (0) -#endif - -#ifdef CONFIG_MACH_MV87XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV87XX -# endif -# define machine_is_mv87xx() (machine_arch_type == MACH_TYPE_MV87XX) -#else -# define machine_is_mv87xx() (0) -#endif - -#ifdef CONFIG_MACH_SONGYOUNGHO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONGYOUNGHO -# endif -# define machine_is_songyoungho() (machine_arch_type == MACH_TYPE_SONGYOUNGHO) -#else -# define machine_is_songyoungho() (0) -#endif - -#ifdef CONFIG_MACH_YOUNGHOTEMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOUNGHOTEMA -# endif -# define machine_is_younghotema() (machine_arch_type == MACH_TYPE_YOUNGHOTEMA) -#else -# define machine_is_younghotema() (0) -#endif - -#ifdef CONFIG_MACH_PCM037 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM037 -# endif -# define machine_is_pcm037() (machine_arch_type == MACH_TYPE_PCM037) -#else -# define machine_is_pcm037() (0) -#endif - -#ifdef CONFIG_MACH_MMVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMVP -# endif -# define machine_is_mmvp() (machine_arch_type == MACH_TYPE_MMVP) -#else -# define machine_is_mmvp() (0) -#endif - -#ifdef CONFIG_MACH_MMAP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMAP -# endif -# define machine_is_mmap() (machine_arch_type == MACH_TYPE_MMAP) -#else -# define machine_is_mmap() (0) -#endif - -#ifdef CONFIG_MACH_PTID2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTID2410 -# endif -# define machine_is_ptid2410() (machine_arch_type == MACH_TYPE_PTID2410) -#else -# define machine_is_ptid2410() (0) -#endif - -#ifdef CONFIG_MACH_JAMES_926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JAMES_926 -# endif -# define machine_is_james_926() (machine_arch_type == MACH_TYPE_JAMES_926) -#else -# define machine_is_james_926() (0) -#endif - -#ifdef CONFIG_MACH_FM6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FM6000 -# endif -# define machine_is_fm6000() (machine_arch_type == MACH_TYPE_FM6000) -#else -# define machine_is_fm6000() (0) -#endif - -#ifdef CONFIG_MACH_DB88F6281_BP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB88F6281_BP -# endif -# define machine_is_db88f6281_bp() (machine_arch_type == MACH_TYPE_DB88F6281_BP) -#else -# define machine_is_db88f6281_bp() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6192_NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6192_NAS -# endif -# define machine_is_rd88f6192_nas() (machine_arch_type == MACH_TYPE_RD88F6192_NAS) -#else -# define machine_is_rd88f6192_nas() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6281 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6281 -# endif -# define machine_is_rd88f6281() (machine_arch_type == MACH_TYPE_RD88F6281) -#else -# define machine_is_rd88f6281() (0) -#endif - -#ifdef CONFIG_MACH_DB78X00_BP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB78X00_BP -# endif -# define machine_is_db78x00_bp() (machine_arch_type == MACH_TYPE_DB78X00_BP) -#else -# define machine_is_db78x00_bp() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2416 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2416 -# endif -# define machine_is_smdk2416() (machine_arch_type == MACH_TYPE_SMDK2416) -#else -# define machine_is_smdk2416() (0) -#endif - -#ifdef CONFIG_MACH_OCE_SPIDER_SI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCE_SPIDER_SI -# endif -# define machine_is_oce_spider_si() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SI) -#else -# define machine_is_oce_spider_si() (0) -#endif - -#ifdef CONFIG_MACH_OCE_SPIDER_SK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCE_SPIDER_SK -# endif -# define machine_is_oce_spider_sk() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SK) -#else -# define machine_is_oce_spider_sk() (0) -#endif - -#ifdef CONFIG_MACH_ROVERN6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERN6 -# endif -# define machine_is_rovern6() (machine_arch_type == MACH_TYPE_ROVERN6) -#else -# define machine_is_rovern6() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_EVOLUTION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_EVOLUTION -# endif -# define machine_is_pelco_evolution() (machine_arch_type == MACH_TYPE_PELCO_EVOLUTION) -#else -# define machine_is_pelco_evolution() (0) -#endif - -#ifdef CONFIG_MACH_WBD111 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WBD111 -# endif -# define machine_is_wbd111() (machine_arch_type == MACH_TYPE_WBD111) -#else -# define machine_is_wbd111() (0) -#endif - -#ifdef CONFIG_MACH_ELARACPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELARACPE -# endif -# define machine_is_elaracpe() (machine_arch_type == MACH_TYPE_ELARACPE) -#else -# define machine_is_elaracpe() (0) -#endif - -#ifdef CONFIG_MACH_MABV3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MABV3 -# endif -# define machine_is_mabv3() (machine_arch_type == MACH_TYPE_MABV3) -#else -# define machine_is_mabv3() (0) -#endif - -#ifdef CONFIG_MACH_MV2120 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV2120 -# endif -# define machine_is_mv2120() (machine_arch_type == MACH_TYPE_MV2120) -#else -# define machine_is_mv2120() (0) -#endif - -#ifdef CONFIG_MACH_CSB737 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB737 -# endif -# define machine_is_csb737() (machine_arch_type == MACH_TYPE_CSB737) -#else -# define machine_is_csb737() (0) -#endif - -#ifdef CONFIG_MACH_MX51_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_3DS -# endif -# define machine_is_mx51_3ds() (machine_arch_type == MACH_TYPE_MX51_3DS) -#else -# define machine_is_mx51_3ds() (0) -#endif - -#ifdef CONFIG_MACH_G900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G900 -# endif -# define machine_is_g900() (machine_arch_type == MACH_TYPE_G900) -#else -# define machine_is_g900() (0) -#endif - -#ifdef CONFIG_MACH_APF27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APF27 -# endif -# define machine_is_apf27() (machine_arch_type == MACH_TYPE_APF27) -#else -# define machine_is_apf27() (0) -#endif - -#ifdef CONFIG_MACH_GGUS2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GGUS2000 -# endif -# define machine_is_ggus2000() (machine_arch_type == MACH_TYPE_GGUS2000) -#else -# define machine_is_ggus2000() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430_MIMIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430_MIMIC -# endif -# define machine_is_omap_2430_mimic() (machine_arch_type == MACH_TYPE_OMAP_2430_MIMIC) -#else -# define machine_is_omap_2430_mimic() (0) -#endif - -#ifdef CONFIG_MACH_IMX27LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27LITE -# endif -# define machine_is_imx27lite() (machine_arch_type == MACH_TYPE_IMX27LITE) -#else -# define machine_is_imx27lite() (0) -#endif - -#ifdef CONFIG_MACH_ALMEX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALMEX -# endif -# define machine_is_almex() (machine_arch_type == MACH_TYPE_ALMEX) -#else -# define machine_is_almex() (0) -#endif - -#ifdef CONFIG_MACH_CONTROL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONTROL -# endif -# define machine_is_control() (machine_arch_type == MACH_TYPE_CONTROL) -#else -# define machine_is_control() (0) -#endif - -#ifdef CONFIG_MACH_MBA2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBA2410 -# endif -# define machine_is_mba2410() (machine_arch_type == MACH_TYPE_MBA2410) -#else -# define machine_is_mba2410() (0) -#endif - -#ifdef CONFIG_MACH_VOLCANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOLCANO -# endif -# define machine_is_volcano() (machine_arch_type == MACH_TYPE_VOLCANO) -#else -# define machine_is_volcano() (0) -#endif - -#ifdef CONFIG_MACH_ZENITH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZENITH -# endif -# define machine_is_zenith() (machine_arch_type == MACH_TYPE_ZENITH) -#else -# define machine_is_zenith() (0) -#endif - -#ifdef CONFIG_MACH_MUCHIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MUCHIP -# endif -# define machine_is_muchip() (machine_arch_type == MACH_TYPE_MUCHIP) -#else -# define machine_is_muchip() (0) -#endif - -#ifdef CONFIG_MACH_MAGELLAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGELLAN -# endif -# define machine_is_magellan() (machine_arch_type == MACH_TYPE_MAGELLAN) -#else -# define machine_is_magellan() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9260 -# endif -# define machine_is_usb_a9260() (machine_arch_type == MACH_TYPE_USB_A9260) -#else -# define machine_is_usb_a9260() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9263 -# endif -# define machine_is_usb_a9263() (machine_arch_type == MACH_TYPE_USB_A9263) -#else -# define machine_is_usb_a9263() (0) -#endif - -#ifdef CONFIG_MACH_QIL_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QIL_A9260 -# endif -# define machine_is_qil_a9260() (machine_arch_type == MACH_TYPE_QIL_A9260) -#else -# define machine_is_qil_a9260() (0) -#endif - -#ifdef CONFIG_MACH_CME9210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CME9210 -# endif -# define machine_is_cme9210() (machine_arch_type == MACH_TYPE_CME9210) -#else -# define machine_is_cme9210() (0) -#endif - -#ifdef CONFIG_MACH_HCZH4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HCZH4 -# endif -# define machine_is_hczh4() (machine_arch_type == MACH_TYPE_HCZH4) -#else -# define machine_is_hczh4() (0) -#endif - -#ifdef CONFIG_MACH_SPEARBASIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEARBASIC -# endif -# define machine_is_spearbasic() (machine_arch_type == MACH_TYPE_SPEARBASIC) -#else -# define machine_is_spearbasic() (0) -#endif - -#ifdef CONFIG_MACH_DEP2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2440 -# endif -# define machine_is_dep2440() (machine_arch_type == MACH_TYPE_DEP2440) -#else -# define machine_is_dep2440() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GXR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GXR -# endif -# define machine_is_hdl_gxr() (machine_arch_type == MACH_TYPE_HDL_GXR) -#else -# define machine_is_hdl_gxr() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GT -# endif -# define machine_is_hdl_gt() (machine_arch_type == MACH_TYPE_HDL_GT) -#else -# define machine_is_hdl_gt() (0) -#endif - -#ifdef CONFIG_MACH_HDL_4G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_4G -# endif -# define machine_is_hdl_4g() (machine_arch_type == MACH_TYPE_HDL_4G) -#else -# define machine_is_hdl_4g() (0) -#endif - -#ifdef CONFIG_MACH_S3C6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C6000 -# endif -# define machine_is_s3c6000() (machine_arch_type == MACH_TYPE_S3C6000) -#else -# define machine_is_s3c6000() (0) -#endif - -#ifdef CONFIG_MACH_MMSP2_MDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMSP2_MDK -# endif -# define machine_is_mmsp2_mdk() (machine_arch_type == MACH_TYPE_MMSP2_MDK) -#else -# define machine_is_mmsp2_mdk() (0) -#endif - -#ifdef CONFIG_MACH_MPX220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPX220 -# endif -# define machine_is_mpx220() (machine_arch_type == MACH_TYPE_MPX220) -#else -# define machine_is_mpx220() (0) -#endif - -#ifdef CONFIG_MACH_KZM_ARM11_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KZM_ARM11_01 -# endif -# define machine_is_kzm_arm11_01() (machine_arch_type == MACH_TYPE_KZM_ARM11_01) -#else -# define machine_is_kzm_arm11_01() (0) -#endif - -#ifdef CONFIG_MACH_HTC_POLARIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_POLARIS -# endif -# define machine_is_htc_polaris() (machine_arch_type == MACH_TYPE_HTC_POLARIS) -#else -# define machine_is_htc_polaris() (0) -#endif - -#ifdef CONFIG_MACH_HTC_KAISER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_KAISER -# endif -# define machine_is_htc_kaiser() (machine_arch_type == MACH_TYPE_HTC_KAISER) -#else -# define machine_is_htc_kaiser() (0) -#endif - -#ifdef CONFIG_MACH_LG_KS20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LG_KS20 -# endif -# define machine_is_lg_ks20() (machine_arch_type == MACH_TYPE_LG_KS20) -#else -# define machine_is_lg_ks20() (0) -#endif - -#ifdef CONFIG_MACH_HHGPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHGPS -# endif -# define machine_is_hhgps() (machine_arch_type == MACH_TYPE_HHGPS) -#else -# define machine_is_hhgps() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N810_WIMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N810_WIMAX -# endif -# define machine_is_nokia_n810_wimax() (machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX) -#else -# define machine_is_nokia_n810_wimax() (0) -#endif - -#ifdef CONFIG_MACH_INSIGHT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INSIGHT -# endif -# define machine_is_insight() (machine_arch_type == MACH_TYPE_INSIGHT) -#else -# define machine_is_insight() (0) -#endif - -#ifdef CONFIG_MACH_SAPPHIRE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAPPHIRE -# endif -# define machine_is_sapphire() (machine_arch_type == MACH_TYPE_SAPPHIRE) -#else -# define machine_is_sapphire() (0) -#endif - -#ifdef CONFIG_MACH_CSB637XO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB637XO -# endif -# define machine_is_csb637xo() (machine_arch_type == MACH_TYPE_CSB637XO) -#else -# define machine_is_csb637xo() (0) -#endif - -#ifdef CONFIG_MACH_EVISIONG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVISIONG -# endif -# define machine_is_evisiong() (machine_arch_type == MACH_TYPE_EVISIONG) -#else -# define machine_is_evisiong() (0) -#endif - -#ifdef CONFIG_MACH_STMP37XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP37XX -# endif -# define machine_is_stmp37xx() (machine_arch_type == MACH_TYPE_STMP37XX) -#else -# define machine_is_stmp37xx() (0) -#endif - -#ifdef CONFIG_MACH_STMP378X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP378X -# endif -# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP378X) -#else -# define machine_is_stmp378x() (0) -#endif - -#ifdef CONFIG_MACH_TNT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNT -# endif -# define machine_is_tnt() (machine_arch_type == MACH_TYPE_TNT) -#else -# define machine_is_tnt() (0) -#endif - -#ifdef CONFIG_MACH_TBXT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBXT -# endif -# define machine_is_tbxt() (machine_arch_type == MACH_TYPE_TBXT) -#else -# define machine_is_tbxt() (0) -#endif - -#ifdef CONFIG_MACH_PLAYMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLAYMATE -# endif -# define machine_is_playmate() (machine_arch_type == MACH_TYPE_PLAYMATE) -#else -# define machine_is_playmate() (0) -#endif - -#ifdef CONFIG_MACH_PNS10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNS10 -# endif -# define machine_is_pns10() (machine_arch_type == MACH_TYPE_PNS10) -#else -# define machine_is_pns10() (0) -#endif - -#ifdef CONFIG_MACH_EZNAVI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZNAVI -# endif -# define machine_is_eznavi() (machine_arch_type == MACH_TYPE_EZNAVI) -#else -# define machine_is_eznavi() (0) -#endif - -#ifdef CONFIG_MACH_PS4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PS4000 -# endif -# define machine_is_ps4000() (machine_arch_type == MACH_TYPE_PS4000) -#else -# define machine_is_ps4000() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A780 -# endif -# define machine_is_ezx_a780() (machine_arch_type == MACH_TYPE_EZX_A780) -#else -# define machine_is_ezx_a780() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E680 -# endif -# define machine_is_ezx_e680() (machine_arch_type == MACH_TYPE_EZX_E680) -#else -# define machine_is_ezx_e680() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A1200 -# endif -# define machine_is_ezx_a1200() (machine_arch_type == MACH_TYPE_EZX_A1200) -#else -# define machine_is_ezx_a1200() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E6 -# endif -# define machine_is_ezx_e6() (machine_arch_type == MACH_TYPE_EZX_E6) -#else -# define machine_is_ezx_e6() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E2 -# endif -# define machine_is_ezx_e2() (machine_arch_type == MACH_TYPE_EZX_E2) -#else -# define machine_is_ezx_e2() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A910 -# endif -# define machine_is_ezx_a910() (machine_arch_type == MACH_TYPE_EZX_A910) -#else -# define machine_is_ezx_a910() (0) -#endif - -#ifdef CONFIG_MACH_CWMX31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMX31 -# endif -# define machine_is_cwmx31() (machine_arch_type == MACH_TYPE_CWMX31) -#else -# define machine_is_cwmx31() (0) -#endif - -#ifdef CONFIG_MACH_SL2312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SL2312 -# endif -# define machine_is_sl2312() (machine_arch_type == MACH_TYPE_SL2312) -#else -# define machine_is_sl2312() (0) -#endif - -#ifdef CONFIG_MACH_BLENNY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLENNY -# endif -# define machine_is_blenny() (machine_arch_type == MACH_TYPE_BLENNY) -#else -# define machine_is_blenny() (0) -#endif - -#ifdef CONFIG_MACH_DS107 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS107 -# endif -# define machine_is_ds107() (machine_arch_type == MACH_TYPE_DS107) -#else -# define machine_is_ds107() (0) -#endif - -#ifdef CONFIG_MACH_DSX07 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSX07 -# endif -# define machine_is_dsx07() (machine_arch_type == MACH_TYPE_DSX07) -#else -# define machine_is_dsx07() (0) -#endif - -#ifdef CONFIG_MACH_PICOCOM1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOCOM1 -# endif -# define machine_is_picocom1() (machine_arch_type == MACH_TYPE_PICOCOM1) -#else -# define machine_is_picocom1() (0) -#endif - -#ifdef CONFIG_MACH_LYNX_WOLVERINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LYNX_WOLVERINE -# endif -# define machine_is_lynx_wolverine() (machine_arch_type == MACH_TYPE_LYNX_WOLVERINE) -#else -# define machine_is_lynx_wolverine() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SC19 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SC19 -# endif -# define machine_is_ubisys_p9_sc19() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC19) -#else -# define machine_is_ubisys_p9_sc19() (0) -#endif - -#ifdef CONFIG_MACH_KRATOS_LOW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRATOS_LOW -# endif -# define machine_is_kratos_low() (machine_arch_type == MACH_TYPE_KRATOS_LOW) -#else -# define machine_is_kratos_low() (0) -#endif - -#ifdef CONFIG_MACH_M700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M700 -# endif -# define machine_is_m700() (machine_arch_type == MACH_TYPE_M700) -#else -# define machine_is_m700() (0) -#endif - -#ifdef CONFIG_MACH_EDMINI_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDMINI_V2 -# endif -# define machine_is_edmini_v2() (machine_arch_type == MACH_TYPE_EDMINI_V2) -#else -# define machine_is_edmini_v2() (0) -#endif - -#ifdef CONFIG_MACH_ZIPIT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIPIT2 -# endif -# define machine_is_zipit2() (machine_arch_type == MACH_TYPE_ZIPIT2) -#else -# define machine_is_zipit2() (0) -#endif - -#ifdef CONFIG_MACH_HSLFEMTOCELL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HSLFEMTOCELL -# endif -# define machine_is_hslfemtocell() (machine_arch_type == MACH_TYPE_HSLFEMTOCELL) -#else -# define machine_is_hslfemtocell() (0) -#endif - -#ifdef CONFIG_MACH_DAINTREE_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAINTREE_AT91 -# endif -# define machine_is_daintree_at91() (machine_arch_type == MACH_TYPE_DAINTREE_AT91) -#else -# define machine_is_daintree_at91() (0) -#endif - -#ifdef CONFIG_MACH_SG560USB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560USB -# endif -# define machine_is_sg560usb() (machine_arch_type == MACH_TYPE_SG560USB) -#else -# define machine_is_sg560usb() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_PANDORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_PANDORA -# endif -# define machine_is_omap3_pandora() (machine_arch_type == MACH_TYPE_OMAP3_PANDORA) -#else -# define machine_is_omap3_pandora() (0) -#endif - -#ifdef CONFIG_MACH_USR8200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USR8200 -# endif -# define machine_is_usr8200() (machine_arch_type == MACH_TYPE_USR8200) -#else -# define machine_is_usr8200() (0) -#endif - -#ifdef CONFIG_MACH_S1S65K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S1S65K -# endif -# define machine_is_s1s65k() (machine_arch_type == MACH_TYPE_S1S65K) -#else -# define machine_is_s1s65k() (0) -#endif - -#ifdef CONFIG_MACH_S2S65A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S2S65A -# endif -# define machine_is_s2s65a() (machine_arch_type == MACH_TYPE_S2S65A) -#else -# define machine_is_s2s65a() (0) -#endif - -#ifdef CONFIG_MACH_ICORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICORE -# endif -# define machine_is_icore() (machine_arch_type == MACH_TYPE_ICORE) -#else -# define machine_is_icore() (0) -#endif - -#ifdef CONFIG_MACH_MSS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSS2 -# endif -# define machine_is_mss2() (machine_arch_type == MACH_TYPE_MSS2) -#else -# define machine_is_mss2() (0) -#endif - -#ifdef CONFIG_MACH_BELMONT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BELMONT -# endif -# define machine_is_belmont() (machine_arch_type == MACH_TYPE_BELMONT) -#else -# define machine_is_belmont() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP525 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP525 -# endif -# define machine_is_asusp525() (machine_arch_type == MACH_TYPE_ASUSP525) -#else -# define machine_is_asusp525() (0) -#endif - -#ifdef CONFIG_MACH_LB88RC8480 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LB88RC8480 -# endif -# define machine_is_lb88rc8480() (machine_arch_type == MACH_TYPE_LB88RC8480) -#else -# define machine_is_lb88rc8480() (0) -#endif - -#ifdef CONFIG_MACH_HIPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIPXA -# endif -# define machine_is_hipxa() (machine_arch_type == MACH_TYPE_HIPXA) -#else -# define machine_is_hipxa() (0) -#endif - -#ifdef CONFIG_MACH_MX25_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX25_3DS -# endif -# define machine_is_mx25_3ds() (machine_arch_type == MACH_TYPE_MX25_3DS) -#else -# define machine_is_mx25_3ds() (0) -#endif - -#ifdef CONFIG_MACH_M800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M800 -# endif -# define machine_is_m800() (machine_arch_type == MACH_TYPE_M800) -#else -# define machine_is_m800() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3530_LV_SOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3530_LV_SOM -# endif -# define machine_is_omap3530_lv_som() (machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM) -#else -# define machine_is_omap3530_lv_som() (0) -#endif - -#ifdef CONFIG_MACH_PRIMA_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRIMA_EVB -# endif -# define machine_is_prima_evb() (machine_arch_type == MACH_TYPE_PRIMA_EVB) -#else -# define machine_is_prima_evb() (0) -#endif - -#ifdef CONFIG_MACH_MX31BT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31BT1 -# endif -# define machine_is_mx31bt1() (machine_arch_type == MACH_TYPE_MX31BT1) -#else -# define machine_is_mx31bt1() (0) -#endif - -#ifdef CONFIG_MACH_ATLAS4_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLAS4_EVB -# endif -# define machine_is_atlas4_evb() (machine_arch_type == MACH_TYPE_ATLAS4_EVB) -#else -# define machine_is_atlas4_evb() (0) -#endif - -#ifdef CONFIG_MACH_MX31CICADA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31CICADA -# endif -# define machine_is_mx31cicada() (machine_arch_type == MACH_TYPE_MX31CICADA) -#else -# define machine_is_mx31cicada() (0) -#endif - -#ifdef CONFIG_MACH_MI424WR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MI424WR -# endif -# define machine_is_mi424wr() (machine_arch_type == MACH_TYPE_MI424WR) -#else -# define machine_is_mi424wr() (0) -#endif - -#ifdef CONFIG_MACH_AXS_ULTRAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXS_ULTRAX -# endif -# define machine_is_axs_ultrax() (machine_arch_type == MACH_TYPE_AXS_ULTRAX) -#else -# define machine_is_axs_ultrax() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940DEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940DEB -# endif -# define machine_is_at572d940deb() (machine_arch_type == MACH_TYPE_AT572D940DEB) -#else -# define machine_is_at572d940deb() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DA830_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM -# endif -# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) -#else -# define machine_is_davinci_da830_evm() (0) -#endif - -#ifdef CONFIG_MACH_EP9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP9302 -# endif -# define machine_is_ep9302() (machine_arch_type == MACH_TYPE_EP9302) -#else -# define machine_is_ep9302() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940HFEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940HFEB -# endif -# define machine_is_at572d940hfek() (machine_arch_type == MACH_TYPE_AT572D940HFEB) -#else -# define machine_is_at572d940hfek() (0) -#endif - -#ifdef CONFIG_MACH_CYBOOK3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBOOK3 -# endif -# define machine_is_cybook3() (machine_arch_type == MACH_TYPE_CYBOOK3) -#else -# define machine_is_cybook3() (0) -#endif - -#ifdef CONFIG_MACH_WDG002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WDG002 -# endif -# define machine_is_wdg002() (machine_arch_type == MACH_TYPE_WDG002) -#else -# define machine_is_wdg002() (0) -#endif - -#ifdef CONFIG_MACH_SG560ADSL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560ADSL -# endif -# define machine_is_sg560adsl() (machine_arch_type == MACH_TYPE_SG560ADSL) -#else -# define machine_is_sg560adsl() (0) -#endif - -#ifdef CONFIG_MACH_NEXTIO_N2800_ICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXTIO_N2800_ICA -# endif -# define machine_is_nextio_n2800_ica() (machine_arch_type == MACH_TYPE_NEXTIO_N2800_ICA) -#else -# define machine_is_nextio_n2800_ica() (0) -#endif - -#ifdef CONFIG_MACH_DOVE_DB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOVE_DB -# endif -# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB) -#else -# define machine_is_dove_db() (0) -#endif - -#ifdef CONFIG_MACH_MARVELL_NEWDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVELL_NEWDB -# endif -# define machine_is_marvell_newdb() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) -#else -# define machine_is_marvell_newdb() (0) -#endif - -#ifdef CONFIG_MACH_VANDIHUD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VANDIHUD -# endif -# define machine_is_vandihud() (machine_arch_type == MACH_TYPE_VANDIHUD) -#else -# define machine_is_vandihud() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_E8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_E8 -# endif -# define machine_is_magx_e8() (machine_arch_type == MACH_TYPE_MAGX_E8) -#else -# define machine_is_magx_e8() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_Z6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_Z6 -# endif -# define machine_is_magx_z6() (machine_arch_type == MACH_TYPE_MAGX_Z6) -#else -# define machine_is_magx_z6() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_V8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_V8 -# endif -# define machine_is_magx_v8() (machine_arch_type == MACH_TYPE_MAGX_V8) -#else -# define machine_is_magx_v8() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_U9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_U9 -# endif -# define machine_is_magx_u9() (machine_arch_type == MACH_TYPE_MAGX_U9) -#else -# define machine_is_magx_u9() (0) -#endif - -#ifdef CONFIG_MACH_TOUGHCF08 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOUGHCF08 -# endif -# define machine_is_toughcf08() (machine_arch_type == MACH_TYPE_TOUGHCF08) -#else -# define machine_is_toughcf08() (0) -#endif - -#ifdef CONFIG_MACH_ZW4400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZW4400 -# endif -# define machine_is_zw4400() (machine_arch_type == MACH_TYPE_ZW4400) -#else -# define machine_is_zw4400() (0) -#endif - -#ifdef CONFIG_MACH_MARAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARAT91 -# endif -# define machine_is_marat91() (machine_arch_type == MACH_TYPE_MARAT91) -#else -# define machine_is_marat91() (0) -#endif - -#ifdef CONFIG_MACH_OVERO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OVERO -# endif -# define machine_is_overo() (machine_arch_type == MACH_TYPE_OVERO) -#else -# define machine_is_overo() (0) -#endif - -#ifdef CONFIG_MACH_AT2440EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT2440EVB -# endif -# define machine_is_at2440evb() (machine_arch_type == MACH_TYPE_AT2440EVB) -#else -# define machine_is_at2440evb() (0) -#endif - -#ifdef CONFIG_MACH_NEOCORE926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEOCORE926 -# endif -# define machine_is_neocore926() (machine_arch_type == MACH_TYPE_NEOCORE926) -#else -# define machine_is_neocore926() (0) -#endif - -#ifdef CONFIG_MACH_WNR854T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WNR854T -# endif -# define machine_is_wnr854t() (machine_arch_type == MACH_TYPE_WNR854T) -#else -# define machine_is_wnr854t() (0) -#endif - -#ifdef CONFIG_MACH_IMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27 -# endif -# define machine_is_imx27() (machine_arch_type == MACH_TYPE_IMX27) -#else -# define machine_is_imx27() (0) -#endif - -#ifdef CONFIG_MACH_MOOSE_DB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOOSE_DB -# endif -# define machine_is_moose_db() (machine_arch_type == MACH_TYPE_MOOSE_DB) -#else -# define machine_is_moose_db() (0) -#endif - -#ifdef CONFIG_MACH_FAB4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FAB4 -# endif -# define machine_is_fab4() (machine_arch_type == MACH_TYPE_FAB4) -#else -# define machine_is_fab4() (0) -#endif - -#ifdef CONFIG_MACH_HTCDIAMOND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCDIAMOND -# endif -# define machine_is_htcdiamond() (machine_arch_type == MACH_TYPE_HTCDIAMOND) -#else -# define machine_is_htcdiamond() (0) -#endif - -#ifdef CONFIG_MACH_FIONA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FIONA -# endif -# define machine_is_fiona() (machine_arch_type == MACH_TYPE_FIONA) -#else -# define machine_is_fiona() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030_X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030_X -# endif -# define machine_is_mxc30030_x() (machine_arch_type == MACH_TYPE_MXC30030_X) -#else -# define machine_is_mxc30030_x() (0) -#endif - -#ifdef CONFIG_MACH_BMP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BMP1000 -# endif -# define machine_is_bmp1000() (machine_arch_type == MACH_TYPE_BMP1000) -#else -# define machine_is_bmp1000() (0) -#endif - -#ifdef CONFIG_MACH_LOGI9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGI9200 -# endif -# define machine_is_logi9200() (machine_arch_type == MACH_TYPE_LOGI9200) -#else -# define machine_is_logi9200() (0) -#endif - -#ifdef CONFIG_MACH_TQMA31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TQMA31 -# endif -# define machine_is_tqma31() (machine_arch_type == MACH_TYPE_TQMA31) -#else -# define machine_is_tqma31() (0) -#endif - -#ifdef CONFIG_MACH_CCW9P9215JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9P9215JS -# endif -# define machine_is_ccw9p9215js() (machine_arch_type == MACH_TYPE_CCW9P9215JS) -#else -# define machine_is_ccw9p9215js() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5181L_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5181L_GE -# endif -# define machine_is_rd88f5181l_ge() (machine_arch_type == MACH_TYPE_RD88F5181L_GE) -#else -# define machine_is_rd88f5181l_ge() (0) -#endif - -#ifdef CONFIG_MACH_SIFMAIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIFMAIN -# endif -# define machine_is_sifmain() (machine_arch_type == MACH_TYPE_SIFMAIN) -#else -# define machine_is_sifmain() (0) -#endif - -#ifdef CONFIG_MACH_SAM9_L9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9_L9261 -# endif -# define machine_is_sam9_l9261() (machine_arch_type == MACH_TYPE_SAM9_L9261) -#else -# define machine_is_sam9_l9261() (0) -#endif - -#ifdef CONFIG_MACH_CC9M2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9M2443 -# endif -# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) -#else -# define machine_is_cc9m2443() (0) -#endif - -#ifdef CONFIG_MACH_XARIA300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XARIA300 -# endif -# define machine_is_xaria300() (machine_arch_type == MACH_TYPE_XARIA300) -#else -# define machine_is_xaria300() (0) -#endif - -#ifdef CONFIG_MACH_IT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IT9200 -# endif -# define machine_is_it9200() (machine_arch_type == MACH_TYPE_IT9200) -#else -# define machine_is_it9200() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5181L_FXO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5181L_FXO -# endif -# define machine_is_rd88f5181l_fxo() (machine_arch_type == MACH_TYPE_RD88F5181L_FXO) -#else -# define machine_is_rd88f5181l_fxo() (0) -#endif - -#ifdef CONFIG_MACH_KRISS_SENSOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRISS_SENSOR -# endif -# define machine_is_kriss_sensor() (machine_arch_type == MACH_TYPE_KRISS_SENSOR) -#else -# define machine_is_kriss_sensor() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI5 -# endif -# define machine_is_pilz_pmi5() (machine_arch_type == MACH_TYPE_PILZ_PMI5) -#else -# define machine_is_pilz_pmi5() (0) -#endif - -#ifdef CONFIG_MACH_JADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADE -# endif -# define machine_is_jade() (machine_arch_type == MACH_TYPE_JADE) -#else -# define machine_is_jade() (0) -#endif - -#ifdef CONFIG_MACH_KS8695_SOFTPLC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695_SOFTPLC -# endif -# define machine_is_ks8695_softplc() (machine_arch_type == MACH_TYPE_KS8695_SOFTPLC) -#else -# define machine_is_ks8695_softplc() (0) -#endif - -#ifdef CONFIG_MACH_GPRISC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GPRISC3 -# endif -# define machine_is_gprisc3() (machine_arch_type == MACH_TYPE_GPRISC3) -#else -# define machine_is_gprisc3() (0) -#endif - -#ifdef CONFIG_MACH_STAMP9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAMP9G20 -# endif -# define machine_is_stamp9g20() (machine_arch_type == MACH_TYPE_STAMP9G20) -#else -# define machine_is_stamp9g20() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6430 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6430 -# endif -# define machine_is_smdk6430() (machine_arch_type == MACH_TYPE_SMDK6430) -#else -# define machine_is_smdk6430() (0) -#endif - -#ifdef CONFIG_MACH_SMDKC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKC100 -# endif -# define machine_is_smdkc100() (machine_arch_type == MACH_TYPE_SMDKC100) -#else -# define machine_is_smdkc100() (0) -#endif - -#ifdef CONFIG_MACH_TAVOREVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAVOREVB -# endif -# define machine_is_tavorevb() (machine_arch_type == MACH_TYPE_TAVOREVB) -#else -# define machine_is_tavorevb() (0) -#endif - -#ifdef CONFIG_MACH_SAAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAAR -# endif -# define machine_is_saar() (machine_arch_type == MACH_TYPE_SAAR) -#else -# define machine_is_saar() (0) -#endif - -#ifdef CONFIG_MACH_DEISTER_EYECAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTER_EYECAM -# endif -# define machine_is_deister_eyecam() (machine_arch_type == MACH_TYPE_DEISTER_EYECAM) -#else -# define machine_is_deister_eyecam() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9M10G45EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK -# endif -# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK) -#else -# define machine_is_at91sam9m10g45ek() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_PRODUO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_PRODUO -# endif -# define machine_is_linkstation_produo() (machine_arch_type == MACH_TYPE_LINKSTATION_PRODUO) -#else -# define machine_is_linkstation_produo() (0) -#endif - -#ifdef CONFIG_MACH_HIT_B0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIT_B0 -# endif -# define machine_is_hit_b0() (machine_arch_type == MACH_TYPE_HIT_B0) -#else -# define machine_is_hit_b0() (0) -#endif - -#ifdef CONFIG_MACH_ADX_RMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_RMU -# endif -# define machine_is_adx_rmu() (machine_arch_type == MACH_TYPE_ADX_RMU) -#else -# define machine_is_adx_rmu() (0) -#endif - -#ifdef CONFIG_MACH_XG_CPE_MAIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XG_CPE_MAIN -# endif -# define machine_is_xg_cpe_main() (machine_arch_type == MACH_TYPE_XG_CPE_MAIN) -#else -# define machine_is_xg_cpe_main() (0) -#endif - -#ifdef CONFIG_MACH_EDB9407A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9407A -# endif -# define machine_is_edb9407a() (machine_arch_type == MACH_TYPE_EDB9407A) -#else -# define machine_is_edb9407a() (0) -#endif - -#ifdef CONFIG_MACH_DTB9608 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DTB9608 -# endif -# define machine_is_dtb9608() (machine_arch_type == MACH_TYPE_DTB9608) -#else -# define machine_is_dtb9608() (0) -#endif - -#ifdef CONFIG_MACH_EM104V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM104V1 -# endif -# define machine_is_em104v1() (machine_arch_type == MACH_TYPE_EM104V1) -#else -# define machine_is_em104v1() (0) -#endif - -#ifdef CONFIG_MACH_DEMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEMO -# endif -# define machine_is_demo() (machine_arch_type == MACH_TYPE_DEMO) -#else -# define machine_is_demo() (0) -#endif - -#ifdef CONFIG_MACH_LOGI9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGI9260 -# endif -# define machine_is_logi9260() (machine_arch_type == MACH_TYPE_LOGI9260) -#else -# define machine_is_logi9260() (0) -#endif - -#ifdef CONFIG_MACH_MX31_EXM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31_EXM32 -# endif -# define machine_is_mx31_exm32() (machine_arch_type == MACH_TYPE_MX31_EXM32) -#else -# define machine_is_mx31_exm32() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9G20 -# endif -# define machine_is_usb_a9g20() (machine_arch_type == MACH_TYPE_USB_A9G20) -#else -# define machine_is_usb_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_PICPROJE2008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICPROJE2008 -# endif -# define machine_is_picproje2008() (machine_arch_type == MACH_TYPE_PICPROJE2008) -#else -# define machine_is_picproje2008() (0) -#endif - -#ifdef CONFIG_MACH_CS_E9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS_E9315 -# endif -# define machine_is_cs_e9315() (machine_arch_type == MACH_TYPE_CS_E9315) -#else -# define machine_is_cs_e9315() (0) -#endif - -#ifdef CONFIG_MACH_QIL_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QIL_A9G20 -# endif -# define machine_is_qil_a9g20() (machine_arch_type == MACH_TYPE_QIL_A9G20) -#else -# define machine_is_qil_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON020 -# endif -# define machine_is_sha_pon020() (machine_arch_type == MACH_TYPE_SHA_PON020) -#else -# define machine_is_sha_pon020() (0) -#endif - -#ifdef CONFIG_MACH_NAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAD -# endif -# define machine_is_nad() (machine_arch_type == MACH_TYPE_NAD) -#else -# define machine_is_nad() (0) -#endif - -#ifdef CONFIG_MACH_SBC35_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC35_A9260 -# endif -# define machine_is_sbc35_a9260() (machine_arch_type == MACH_TYPE_SBC35_A9260) -#else -# define machine_is_sbc35_a9260() (0) -#endif - -#ifdef CONFIG_MACH_SBC35_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC35_A9G20 -# endif -# define machine_is_sbc35_a9g20() (machine_arch_type == MACH_TYPE_SBC35_A9G20) -#else -# define machine_is_sbc35_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_BEGINNING -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_BEGINNING -# endif -# define machine_is_davinci_beginning() (machine_arch_type == MACH_TYPE_DAVINCI_BEGINNING) -#else -# define machine_is_davinci_beginning() (0) -#endif - -#ifdef CONFIG_MACH_UWC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UWC -# endif -# define machine_is_uwc() (machine_arch_type == MACH_TYPE_UWC) -#else -# define machine_is_uwc() (0) -#endif - -#ifdef CONFIG_MACH_MXLADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXLADS -# endif -# define machine_is_mxlads() (machine_arch_type == MACH_TYPE_MXLADS) -#else -# define machine_is_mxlads() (0) -#endif - -#ifdef CONFIG_MACH_HTCNIKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCNIKE -# endif -# define machine_is_htcnike() (machine_arch_type == MACH_TYPE_HTCNIKE) -#else -# define machine_is_htcnike() (0) -#endif - -#ifdef CONFIG_MACH_DEISTER_PXA270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTER_PXA270 -# endif -# define machine_is_deister_pxa270() (machine_arch_type == MACH_TYPE_DEISTER_PXA270) -#else -# define machine_is_deister_pxa270() (0) -#endif - -#ifdef CONFIG_MACH_CME9210JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CME9210JS -# endif -# define machine_is_cme9210js() (machine_arch_type == MACH_TYPE_CME9210JS) -#else -# define machine_is_cme9210js() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360 -# endif -# define machine_is_cc9p9360() (machine_arch_type == MACH_TYPE_CC9P9360) -#else -# define machine_is_cc9p9360() (0) -#endif - -#ifdef CONFIG_MACH_MOCHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOCHA -# endif -# define machine_is_mocha() (machine_arch_type == MACH_TYPE_MOCHA) -#else -# define machine_is_mocha() (0) -#endif - -#ifdef CONFIG_MACH_WAPD170AG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WAPD170AG -# endif -# define machine_is_wapd170ag() (machine_arch_type == MACH_TYPE_WAPD170AG) -#else -# define machine_is_wapd170ag() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_MINI -# endif -# define machine_is_linkstation_mini() (machine_arch_type == MACH_TYPE_LINKSTATION_MINI) -#else -# define machine_is_linkstation_mini() (0) -#endif - -#ifdef CONFIG_MACH_AFEB9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFEB9260 -# endif -# define machine_is_afeb9260() (machine_arch_type == MACH_TYPE_AFEB9260) -#else -# define machine_is_afeb9260() (0) -#endif - -#ifdef CONFIG_MACH_W90X900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90X900 -# endif -# define machine_is_w90x900() (machine_arch_type == MACH_TYPE_W90X900) -#else -# define machine_is_w90x900() (0) -#endif - -#ifdef CONFIG_MACH_W90X700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90X700 -# endif -# define machine_is_w90x700() (machine_arch_type == MACH_TYPE_W90X700) -#else -# define machine_is_w90x700() (0) -#endif - -#ifdef CONFIG_MACH_KT300IP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KT300IP -# endif -# define machine_is_kt300ip() (machine_arch_type == MACH_TYPE_KT300IP) -#else -# define machine_is_kt300ip() (0) -#endif - -#ifdef CONFIG_MACH_KT300IP_G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KT300IP_G20 -# endif -# define machine_is_kt300ip_g20() (machine_arch_type == MACH_TYPE_KT300IP_G20) -#else -# define machine_is_kt300ip_g20() (0) -#endif - -#ifdef CONFIG_MACH_SRCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SRCM -# endif -# define machine_is_srcm() (machine_arch_type == MACH_TYPE_SRCM) -#else -# define machine_is_srcm() (0) -#endif - -#ifdef CONFIG_MACH_WLNX_9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WLNX_9260 -# endif -# define machine_is_wlnx_9260() (machine_arch_type == MACH_TYPE_WLNX_9260) -#else -# define machine_is_wlnx_9260() (0) -#endif - -#ifdef CONFIG_MACH_OPENMOKO_GTA03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENMOKO_GTA03 -# endif -# define machine_is_openmoko_gta03() (machine_arch_type == MACH_TYPE_OPENMOKO_GTA03) -#else -# define machine_is_openmoko_gta03() (0) -#endif - -#ifdef CONFIG_MACH_OSPREY2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSPREY2 -# endif -# define machine_is_osprey2() (machine_arch_type == MACH_TYPE_OSPREY2) -#else -# define machine_is_osprey2() (0) -#endif - -#ifdef CONFIG_MACH_KBIO9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBIO9260 -# endif -# define machine_is_kbio9260() (machine_arch_type == MACH_TYPE_KBIO9260) -#else -# define machine_is_kbio9260() (0) -#endif - -#ifdef CONFIG_MACH_GINZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GINZA -# endif -# define machine_is_ginza() (machine_arch_type == MACH_TYPE_GINZA) -#else -# define machine_is_ginza() (0) -#endif - -#ifdef CONFIG_MACH_A636N -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A636N -# endif -# define machine_is_a636n() (machine_arch_type == MACH_TYPE_A636N) -#else -# define machine_is_a636n() (0) -#endif - -#ifdef CONFIG_MACH_IMX27IPCAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27IPCAM -# endif -# define machine_is_imx27ipcam() (machine_arch_type == MACH_TYPE_IMX27IPCAM) -#else -# define machine_is_imx27ipcam() (0) -#endif - -#ifdef CONFIG_MACH_NEMOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEMOC -# endif -# define machine_is_nemoc() (machine_arch_type == MACH_TYPE_NEMOC) -#else -# define machine_is_nemoc() (0) -#endif - -#ifdef CONFIG_MACH_GENEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENEVA -# endif -# define machine_is_geneva() (machine_arch_type == MACH_TYPE_GENEVA) -#else -# define machine_is_geneva() (0) -#endif - -#ifdef CONFIG_MACH_HTCPHAROS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPHAROS -# endif -# define machine_is_htcpharos() (machine_arch_type == MACH_TYPE_HTCPHAROS) -#else -# define machine_is_htcpharos() (0) -#endif - -#ifdef CONFIG_MACH_NEONC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEONC -# endif -# define machine_is_neonc() (machine_arch_type == MACH_TYPE_NEONC) -#else -# define machine_is_neonc() (0) -#endif - -#ifdef CONFIG_MACH_NAS7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS7100 -# endif -# define machine_is_nas7100() (machine_arch_type == MACH_TYPE_NAS7100) -#else -# define machine_is_nas7100() (0) -#endif - -#ifdef CONFIG_MACH_TEUPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEUPHONE -# endif -# define machine_is_teuphone() (machine_arch_type == MACH_TYPE_TEUPHONE) -#else -# define machine_is_teuphone() (0) -#endif - -#ifdef CONFIG_MACH_ANNAX_ETH2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANNAX_ETH2 -# endif -# define machine_is_annax_eth2() (machine_arch_type == MACH_TYPE_ANNAX_ETH2) -#else -# define machine_is_annax_eth2() (0) -#endif - -#ifdef CONFIG_MACH_CSB733 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB733 -# endif -# define machine_is_csb733() (machine_arch_type == MACH_TYPE_CSB733) -#else -# define machine_is_csb733() (0) -#endif - -#ifdef CONFIG_MACH_BK3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BK3 -# endif -# define machine_is_bk3() (machine_arch_type == MACH_TYPE_BK3) -#else -# define machine_is_bk3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_EM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_EM32 -# endif -# define machine_is_omap_em32() (machine_arch_type == MACH_TYPE_OMAP_EM32) -#else -# define machine_is_omap_em32() (0) -#endif - -#ifdef CONFIG_MACH_ET9261CP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ET9261CP -# endif -# define machine_is_et9261cp() (machine_arch_type == MACH_TYPE_ET9261CP) -#else -# define machine_is_et9261cp() (0) -#endif - -#ifdef CONFIG_MACH_JASPERC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JASPERC -# endif -# define machine_is_jasperc() (machine_arch_type == MACH_TYPE_JASPERC) -#else -# define machine_is_jasperc() (0) -#endif - -#ifdef CONFIG_MACH_ISSI_ARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ISSI_ARM9 -# endif -# define machine_is_issi_arm9() (machine_arch_type == MACH_TYPE_ISSI_ARM9) -#else -# define machine_is_issi_arm9() (0) -#endif - -#ifdef CONFIG_MACH_UED -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UED -# endif -# define machine_is_ued() (machine_arch_type == MACH_TYPE_UED) -#else -# define machine_is_ued() (0) -#endif - -#ifdef CONFIG_MACH_ESIBLADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESIBLADE -# endif -# define machine_is_esiblade() (machine_arch_type == MACH_TYPE_ESIBLADE) -#else -# define machine_is_esiblade() (0) -#endif - -#ifdef CONFIG_MACH_EYE02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EYE02 -# endif -# define machine_is_eye02() (machine_arch_type == MACH_TYPE_EYE02) -#else -# define machine_is_eye02() (0) -#endif - -#ifdef CONFIG_MACH_IMX27KBD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27KBD -# endif -# define machine_is_imx27kbd() (machine_arch_type == MACH_TYPE_IMX27KBD) -#else -# define machine_is_imx27kbd() (0) -#endif - -#ifdef CONFIG_MACH_SST61VC010_FPGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SST61VC010_FPGA -# endif -# define machine_is_sst61vc010_fpga() (machine_arch_type == MACH_TYPE_SST61VC010_FPGA) -#else -# define machine_is_sst61vc010_fpga() (0) -#endif - -#ifdef CONFIG_MACH_KIXVP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXVP435 -# endif -# define machine_is_kixvp435() (machine_arch_type == MACH_TYPE_KIXVP435) -#else -# define machine_is_kixvp435() (0) -#endif - -#ifdef CONFIG_MACH_KIXNP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXNP435 -# endif -# define machine_is_kixnp435() (machine_arch_type == MACH_TYPE_KIXNP435) -#else -# define machine_is_kixnp435() (0) -#endif - -#ifdef CONFIG_MACH_AFRICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFRICA -# endif -# define machine_is_africa() (machine_arch_type == MACH_TYPE_AFRICA) -#else -# define machine_is_africa() (0) -#endif - -#ifdef CONFIG_MACH_NH233 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NH233 -# endif -# define machine_is_nh233() (machine_arch_type == MACH_TYPE_NH233) -#else -# define machine_is_nh233() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6183AP_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6183AP_GE -# endif -# define machine_is_rd88f6183ap_ge() (machine_arch_type == MACH_TYPE_RD88F6183AP_GE) -#else -# define machine_is_rd88f6183ap_ge() (0) -#endif - -#ifdef CONFIG_MACH_BCM4760 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM4760 -# endif -# define machine_is_bcm4760() (machine_arch_type == MACH_TYPE_BCM4760) -#else -# define machine_is_bcm4760() (0) -#endif - -#ifdef CONFIG_MACH_EDDY_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDDY_V2 -# endif -# define machine_is_eddy_v2() (machine_arch_type == MACH_TYPE_EDDY_V2) -#else -# define machine_is_eddy_v2() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PBA8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PBA8 -# endif -# define machine_is_realview_pba8() (machine_arch_type == MACH_TYPE_REALVIEW_PBA8) -#else -# define machine_is_realview_pba8() (0) -#endif - -#ifdef CONFIG_MACH_HID_A7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HID_A7 -# endif -# define machine_is_hid_a7() (machine_arch_type == MACH_TYPE_HID_A7) -#else -# define machine_is_hid_a7() (0) -#endif - -#ifdef CONFIG_MACH_HERO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERO -# endif -# define machine_is_hero() (machine_arch_type == MACH_TYPE_HERO) -#else -# define machine_is_hero() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_POSEIDON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_POSEIDON -# endif -# define machine_is_omap_poseidon() (machine_arch_type == MACH_TYPE_OMAP_POSEIDON) -#else -# define machine_is_omap_poseidon() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PBX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PBX -# endif -# define machine_is_realview_pbx() (machine_arch_type == MACH_TYPE_REALVIEW_PBX) -#else -# define machine_is_realview_pbx() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9S -# endif -# define machine_is_micro9s() (machine_arch_type == MACH_TYPE_MICRO9S) -#else -# define machine_is_micro9s() (0) -#endif - -#ifdef CONFIG_MACH_MAKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAKO -# endif -# define machine_is_mako() (machine_arch_type == MACH_TYPE_MAKO) -#else -# define machine_is_mako() (0) -#endif - -#ifdef CONFIG_MACH_XDAFLAME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDAFLAME -# endif -# define machine_is_xdaflame() (machine_arch_type == MACH_TYPE_XDAFLAME) -#else -# define machine_is_xdaflame() (0) -#endif - -#ifdef CONFIG_MACH_PHIDGET_SBC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHIDGET_SBC2 -# endif -# define machine_is_phidget_sbc2() (machine_arch_type == MACH_TYPE_PHIDGET_SBC2) -#else -# define machine_is_phidget_sbc2() (0) -#endif - -#ifdef CONFIG_MACH_LIMESTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIMESTONE -# endif -# define machine_is_limestone() (machine_arch_type == MACH_TYPE_LIMESTONE) -#else -# define machine_is_limestone() (0) -#endif - -#ifdef CONFIG_MACH_IPROBE_C32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPROBE_C32 -# endif -# define machine_is_iprobe_c32() (machine_arch_type == MACH_TYPE_IPROBE_C32) -#else -# define machine_is_iprobe_c32() (0) -#endif - -#ifdef CONFIG_MACH_RUT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RUT100 -# endif -# define machine_is_rut100() (machine_arch_type == MACH_TYPE_RUT100) -#else -# define machine_is_rut100() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP535 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP535 -# endif -# define machine_is_asusp535() (machine_arch_type == MACH_TYPE_ASUSP535) -#else -# define machine_is_asusp535() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL -# endif -# define machine_is_htcraphael() (machine_arch_type == MACH_TYPE_HTCRAPHAEL) -#else -# define machine_is_htcraphael() (0) -#endif - -#ifdef CONFIG_MACH_SYGDG1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYGDG1 -# endif -# define machine_is_sygdg1() (machine_arch_type == MACH_TYPE_SYGDG1) -#else -# define machine_is_sygdg1() (0) -#endif - -#ifdef CONFIG_MACH_SYGDG2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYGDG2 -# endif -# define machine_is_sygdg2() (machine_arch_type == MACH_TYPE_SYGDG2) -#else -# define machine_is_sygdg2() (0) -#endif - -#ifdef CONFIG_MACH_SEOUL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEOUL -# endif -# define machine_is_seoul() (machine_arch_type == MACH_TYPE_SEOUL) -#else -# define machine_is_seoul() (0) -#endif - -#ifdef CONFIG_MACH_SALERNO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SALERNO -# endif -# define machine_is_salerno() (machine_arch_type == MACH_TYPE_SALERNO) -#else -# define machine_is_salerno() (0) -#endif - -#ifdef CONFIG_MACH_UCN_S3C64XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCN_S3C64XX -# endif -# define machine_is_ucn_s3c64xx() (machine_arch_type == MACH_TYPE_UCN_S3C64XX) -#else -# define machine_is_ucn_s3c64xx() (0) -#endif - -#ifdef CONFIG_MACH_MSM7201A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7201A -# endif -# define machine_is_msm7201a() (machine_arch_type == MACH_TYPE_MSM7201A) -#else -# define machine_is_msm7201a() (0) -#endif - -#ifdef CONFIG_MACH_LPR1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPR1 -# endif -# define machine_is_lpr1() (machine_arch_type == MACH_TYPE_LPR1) -#else -# define machine_is_lpr1() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO500FX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO500FX -# endif -# define machine_is_armadillo500fx() (machine_arch_type == MACH_TYPE_ARMADILLO500FX) -#else -# define machine_is_armadillo500fx() (0) -#endif - -#ifdef CONFIG_MACH_G3EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G3EVM -# endif -# define machine_is_g3evm() (machine_arch_type == MACH_TYPE_G3EVM) -#else -# define machine_is_g3evm() (0) -#endif - -#ifdef CONFIG_MACH_Z3_DM355 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z3_DM355 -# endif -# define machine_is_z3_dm355() (machine_arch_type == MACH_TYPE_Z3_DM355) -#else -# define machine_is_z3_dm355() (0) -#endif - -#ifdef CONFIG_MACH_W90P910EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P910EVB -# endif -# define machine_is_w90p910evb() (machine_arch_type == MACH_TYPE_W90P910EVB) -#else -# define machine_is_w90p910evb() (0) -#endif - -#ifdef CONFIG_MACH_W90P920EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P920EVB -# endif -# define machine_is_w90p920evb() (machine_arch_type == MACH_TYPE_W90P920EVB) -#else -# define machine_is_w90p920evb() (0) -#endif - -#ifdef CONFIG_MACH_W90P950EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P950EVB -# endif -# define machine_is_w90p950evb() (machine_arch_type == MACH_TYPE_W90P950EVB) -#else -# define machine_is_w90p950evb() (0) -#endif - -#ifdef CONFIG_MACH_W90N960EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90N960EVB -# endif -# define machine_is_w90n960evb() (machine_arch_type == MACH_TYPE_W90N960EVB) -#else -# define machine_is_w90n960evb() (0) -#endif - -#ifdef CONFIG_MACH_CAMHD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMHD -# endif -# define machine_is_camhd() (machine_arch_type == MACH_TYPE_CAMHD) -#else -# define machine_is_camhd() (0) -#endif - -#ifdef CONFIG_MACH_MVC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MVC100 -# endif -# define machine_is_mvc100() (machine_arch_type == MACH_TYPE_MVC100) -#else -# define machine_is_mvc100() (0) -#endif - -#ifdef CONFIG_MACH_ELECTRUM_200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELECTRUM_200 -# endif -# define machine_is_electrum_200() (machine_arch_type == MACH_TYPE_ELECTRUM_200) -#else -# define machine_is_electrum_200() (0) -#endif - -#ifdef CONFIG_MACH_HTCJADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCJADE -# endif -# define machine_is_htcjade() (machine_arch_type == MACH_TYPE_HTCJADE) -#else -# define machine_is_htcjade() (0) -#endif - -#ifdef CONFIG_MACH_MEMPHIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEMPHIS -# endif -# define machine_is_memphis() (machine_arch_type == MACH_TYPE_MEMPHIS) -#else -# define machine_is_memphis() (0) -#endif - -#ifdef CONFIG_MACH_IMX27SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27SBC -# endif -# define machine_is_imx27sbc() (machine_arch_type == MACH_TYPE_IMX27SBC) -#else -# define machine_is_imx27sbc() (0) -#endif - -#ifdef CONFIG_MACH_LEXTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEXTAR -# endif -# define machine_is_lextar() (machine_arch_type == MACH_TYPE_LEXTAR) -#else -# define machine_is_lextar() (0) -#endif - -#ifdef CONFIG_MACH_MV88F6281GTW_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88F6281GTW_GE -# endif -# define machine_is_mv88f6281gtw_ge() (machine_arch_type == MACH_TYPE_MV88F6281GTW_GE) -#else -# define machine_is_mv88f6281gtw_ge() (0) -#endif - -#ifdef CONFIG_MACH_NCP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NCP -# endif -# define machine_is_ncp() (machine_arch_type == MACH_TYPE_NCP) -#else -# define machine_is_ncp() (0) -#endif - -#ifdef CONFIG_MACH_Z32AN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z32AN -# endif -# define machine_is_z32an_series() (machine_arch_type == MACH_TYPE_Z32AN) -#else -# define machine_is_z32an_series() (0) -#endif - -#ifdef CONFIG_MACH_TMQ_CAPD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TMQ_CAPD -# endif -# define machine_is_tmq_capd() (machine_arch_type == MACH_TYPE_TMQ_CAPD) -#else -# define machine_is_tmq_capd() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_WL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_WL -# endif -# define machine_is_omap3_wl() (machine_arch_type == MACH_TYPE_OMAP3_WL) -#else -# define machine_is_omap3_wl() (0) -#endif - -#ifdef CONFIG_MACH_CHUMBY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUMBY -# endif -# define machine_is_chumby() (machine_arch_type == MACH_TYPE_CHUMBY) -#else -# define machine_is_chumby() (0) -#endif - -#ifdef CONFIG_MACH_ATSARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATSARM9 -# endif -# define machine_is_atsarm9() (machine_arch_type == MACH_TYPE_ATSARM9) -#else -# define machine_is_atsarm9() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM365_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM365_EVM -# endif -# define machine_is_davinci_dm365_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM) -#else -# define machine_is_davinci_dm365_evm() (0) -#endif - -#ifdef CONFIG_MACH_BAHAMAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BAHAMAS -# endif -# define machine_is_bahamas() (machine_arch_type == MACH_TYPE_BAHAMAS) -#else -# define machine_is_bahamas() (0) -#endif - -#ifdef CONFIG_MACH_DAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAS -# endif -# define machine_is_das() (machine_arch_type == MACH_TYPE_DAS) -#else -# define machine_is_das() (0) -#endif - -#ifdef CONFIG_MACH_MINIDAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINIDAS -# endif -# define machine_is_minidas() (machine_arch_type == MACH_TYPE_MINIDAS) -#else -# define machine_is_minidas() (0) -#endif - -#ifdef CONFIG_MACH_VK1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VK1000 -# endif -# define machine_is_vk1000() (machine_arch_type == MACH_TYPE_VK1000) -#else -# define machine_is_vk1000() (0) -#endif - -#ifdef CONFIG_MACH_CENTRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CENTRO -# endif -# define machine_is_centro() (machine_arch_type == MACH_TYPE_CENTRO) -#else -# define machine_is_centro() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY -# endif -# define machine_is_ctera_2bay() (machine_arch_type == MACH_TYPE_CTERA_2BAY) -#else -# define machine_is_ctera_2bay() (0) -#endif - -#ifdef CONFIG_MACH_EDGECONNECT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDGECONNECT -# endif -# define machine_is_edgeconnect() (machine_arch_type == MACH_TYPE_EDGECONNECT) -#else -# define machine_is_edgeconnect() (0) -#endif - -#ifdef CONFIG_MACH_ND27000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ND27000 -# endif -# define machine_is_nd27000() (machine_arch_type == MACH_TYPE_ND27000) -#else -# define machine_is_nd27000() (0) -#endif - -#ifdef CONFIG_MACH_GEMALTO_COBRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMALTO_COBRA -# endif -# define machine_is_cobra() (machine_arch_type == MACH_TYPE_GEMALTO_COBRA) -#else -# define machine_is_cobra() (0) -#endif - -#ifdef CONFIG_MACH_INGELABS_COMET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INGELABS_COMET -# endif -# define machine_is_ingelabs_comet() (machine_arch_type == MACH_TYPE_INGELABS_COMET) -#else -# define machine_is_ingelabs_comet() (0) -#endif - -#ifdef CONFIG_MACH_POLLUX_WIZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POLLUX_WIZ -# endif -# define machine_is_pollux_wiz() (machine_arch_type == MACH_TYPE_POLLUX_WIZ) -#else -# define machine_is_pollux_wiz() (0) -#endif - -#ifdef CONFIG_MACH_BLACKSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKSTONE -# endif -# define machine_is_blackstone() (machine_arch_type == MACH_TYPE_BLACKSTONE) -#else -# define machine_is_blackstone() (0) -#endif - -#ifdef CONFIG_MACH_TOPAZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOPAZ -# endif -# define machine_is_topaz() (machine_arch_type == MACH_TYPE_TOPAZ) -#else -# define machine_is_topaz() (0) -#endif - -#ifdef CONFIG_MACH_AIXLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AIXLE -# endif -# define machine_is_aixle() (machine_arch_type == MACH_TYPE_AIXLE) -#else -# define machine_is_aixle() (0) -#endif - -#ifdef CONFIG_MACH_MW998 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MW998 -# endif -# define machine_is_mw998() (machine_arch_type == MACH_TYPE_MW998) -#else -# define machine_is_mw998() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_RX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_RX51 -# endif -# define machine_is_nokia_rx51() (machine_arch_type == MACH_TYPE_NOKIA_RX51) -#else -# define machine_is_nokia_rx51() (0) -#endif - -#ifdef CONFIG_MACH_VSC5605EV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VSC5605EV -# endif -# define machine_is_vsc5605ev() (machine_arch_type == MACH_TYPE_VSC5605EV) -#else -# define machine_is_vsc5605ev() (0) -#endif - -#ifdef CONFIG_MACH_NT98700DK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NT98700DK -# endif -# define machine_is_nt98700dk() (machine_arch_type == MACH_TYPE_NT98700DK) -#else -# define machine_is_nt98700dk() (0) -#endif - -#ifdef CONFIG_MACH_ICONTACT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICONTACT -# endif -# define machine_is_icontact() (machine_arch_type == MACH_TYPE_ICONTACT) -#else -# define machine_is_icontact() (0) -#endif - -#ifdef CONFIG_MACH_SWARCO_FRCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCO_FRCPU -# endif -# define machine_is_swarco_frcpu() (machine_arch_type == MACH_TYPE_SWARCO_FRCPU) -#else -# define machine_is_swarco_frcpu() (0) -#endif - -#ifdef CONFIG_MACH_SWARCO_SCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCO_SCPU -# endif -# define machine_is_swarco_scpu() (machine_arch_type == MACH_TYPE_SWARCO_SCPU) -#else -# define machine_is_swarco_scpu() (0) -#endif - -#ifdef CONFIG_MACH_BBOX_P16 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBOX_P16 -# endif -# define machine_is_bbox_p16() (machine_arch_type == MACH_TYPE_BBOX_P16) -#else -# define machine_is_bbox_p16() (0) -#endif - -#ifdef CONFIG_MACH_BSTD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSTD -# endif -# define machine_is_bstd() (machine_arch_type == MACH_TYPE_BSTD) -#else -# define machine_is_bstd() (0) -#endif - -#ifdef CONFIG_MACH_SBC2440II -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2440II -# endif -# define machine_is_sbc2440ii() (machine_arch_type == MACH_TYPE_SBC2440II) -#else -# define machine_is_sbc2440ii() (0) -#endif - -#ifdef CONFIG_MACH_PCM034 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM034 -# endif -# define machine_is_pcm034() (machine_arch_type == MACH_TYPE_PCM034) -#else -# define machine_is_pcm034() (0) -#endif - -#ifdef CONFIG_MACH_NESO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NESO -# endif -# define machine_is_neso() (machine_arch_type == MACH_TYPE_NESO) -#else -# define machine_is_neso() (0) -#endif - -#ifdef CONFIG_MACH_WLNX_9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WLNX_9G20 -# endif -# define machine_is_wlnx_9g20() (machine_arch_type == MACH_TYPE_WLNX_9G20) -#else -# define machine_is_wlnx_9g20() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_ZOOM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_ZOOM2 -# endif -# define machine_is_omap_zoom2() (machine_arch_type == MACH_TYPE_OMAP_ZOOM2) -#else -# define machine_is_omap_zoom2() (0) -#endif - -#ifdef CONFIG_MACH_TOTEMNOVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOTEMNOVA -# endif -# define machine_is_totemnova() (machine_arch_type == MACH_TYPE_TOTEMNOVA) -#else -# define machine_is_totemnova() (0) -#endif - -#ifdef CONFIG_MACH_C5000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C5000 -# endif -# define machine_is_c5000() (machine_arch_type == MACH_TYPE_C5000) -#else -# define machine_is_c5000() (0) -#endif - -#ifdef CONFIG_MACH_UNIPO_AT91SAM9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIPO_AT91SAM9263 -# endif -# define machine_is_unipo_at91sam9263() (machine_arch_type == MACH_TYPE_UNIPO_AT91SAM9263) -#else -# define machine_is_unipo_at91sam9263() (0) -#endif - -#ifdef CONFIG_MACH_ETHERNUT5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETHERNUT5 -# endif -# define machine_is_ethernut5() (machine_arch_type == MACH_TYPE_ETHERNUT5) -#else -# define machine_is_ethernut5() (0) -#endif - -#ifdef CONFIG_MACH_ARM11 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM11 -# endif -# define machine_is_arm11() (machine_arch_type == MACH_TYPE_ARM11) -#else -# define machine_is_arm11() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9260 -# endif -# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260) -#else -# define machine_is_cpuat9260() (0) -#endif - -#ifdef CONFIG_MACH_CPUPXA255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUPXA255 -# endif -# define machine_is_cpupxa255() (machine_arch_type == MACH_TYPE_CPUPXA255) -#else -# define machine_is_cpupxa255() (0) -#endif - -#ifdef CONFIG_MACH_CPUIMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUIMX27 -# endif -# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) -#else -# define machine_is_eukrea_cpuimx27() (0) -#endif - -#ifdef CONFIG_MACH_CHEFLUX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHEFLUX -# endif -# define machine_is_cheflux() (machine_arch_type == MACH_TYPE_CHEFLUX) -#else -# define machine_is_cheflux() (0) -#endif - -#ifdef CONFIG_MACH_EB_CPUX9K2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB_CPUX9K2 -# endif -# define machine_is_eb_cpux9k2() (machine_arch_type == MACH_TYPE_EB_CPUX9K2) -#else -# define machine_is_eb_cpux9k2() (0) -#endif - -#ifdef CONFIG_MACH_OPCOTEC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPCOTEC -# endif -# define machine_is_opcotec() (machine_arch_type == MACH_TYPE_OPCOTEC) -#else -# define machine_is_opcotec() (0) -#endif - -#ifdef CONFIG_MACH_YT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YT -# endif -# define machine_is_yt() (machine_arch_type == MACH_TYPE_YT) -#else -# define machine_is_yt() (0) -#endif - -#ifdef CONFIG_MACH_MOTOQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOQ -# endif -# define machine_is_motoq() (machine_arch_type == MACH_TYPE_MOTOQ) -#else -# define machine_is_motoq() (0) -#endif - -#ifdef CONFIG_MACH_BSB1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSB1 -# endif -# define machine_is_bsb1() (machine_arch_type == MACH_TYPE_BSB1) -#else -# define machine_is_bsb1() (0) -#endif - -#ifdef CONFIG_MACH_ACS5K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACS5K -# endif -# define machine_is_acs5k() (machine_arch_type == MACH_TYPE_ACS5K) -#else -# define machine_is_acs5k() (0) -#endif - -#ifdef CONFIG_MACH_MILAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MILAN -# endif -# define machine_is_milan() (machine_arch_type == MACH_TYPE_MILAN) -#else -# define machine_is_milan() (0) -#endif - -#ifdef CONFIG_MACH_QUARTZV2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUARTZV2 -# endif -# define machine_is_quartzv2() (machine_arch_type == MACH_TYPE_QUARTZV2) -#else -# define machine_is_quartzv2() (0) -#endif - -#ifdef CONFIG_MACH_RSVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSVP -# endif -# define machine_is_rsvp() (machine_arch_type == MACH_TYPE_RSVP) -#else -# define machine_is_rsvp() (0) -#endif - -#ifdef CONFIG_MACH_RMP200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMP200 -# endif -# define machine_is_rmp200() (machine_arch_type == MACH_TYPE_RMP200) -#else -# define machine_is_rmp200() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_9260 -# endif -# define machine_is_snapper_9260() (machine_arch_type == MACH_TYPE_SNAPPER_9260) -#else -# define machine_is_snapper_9260() (0) -#endif - -#ifdef CONFIG_MACH_DSM320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSM320 -# endif -# define machine_is_dsm320() (machine_arch_type == MACH_TYPE_DSM320) -#else -# define machine_is_dsm320() (0) -#endif - -#ifdef CONFIG_MACH_ADSGCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSGCM -# endif -# define machine_is_adsgcm() (machine_arch_type == MACH_TYPE_ADSGCM) -#else -# define machine_is_adsgcm() (0) -#endif - -#ifdef CONFIG_MACH_ASE2_400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASE2_400 -# endif -# define machine_is_ase2_400() (machine_arch_type == MACH_TYPE_ASE2_400) -#else -# define machine_is_ase2_400() (0) -#endif - -#ifdef CONFIG_MACH_PIZZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIZZA -# endif -# define machine_is_pizza() (machine_arch_type == MACH_TYPE_PIZZA) -#else -# define machine_is_pizza() (0) -#endif - -#ifdef CONFIG_MACH_SPOT_NGPL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOT_NGPL -# endif -# define machine_is_spot_ngpl() (machine_arch_type == MACH_TYPE_SPOT_NGPL) -#else -# define machine_is_spot_ngpl() (0) -#endif - -#ifdef CONFIG_MACH_ARMATA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMATA -# endif -# define machine_is_armata() (machine_arch_type == MACH_TYPE_ARMATA) -#else -# define machine_is_armata() (0) -#endif - -#ifdef CONFIG_MACH_EXEDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXEDA -# endif -# define machine_is_exeda() (machine_arch_type == MACH_TYPE_EXEDA) -#else -# define machine_is_exeda() (0) -#endif - -#ifdef CONFIG_MACH_MX31SF005 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31SF005 -# endif -# define machine_is_mx31sf005() (machine_arch_type == MACH_TYPE_MX31SF005) -#else -# define machine_is_mx31sf005() (0) -#endif - -#ifdef CONFIG_MACH_F5D8231_4_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_F5D8231_4_V2 -# endif -# define machine_is_f5d8231_4_v2() (machine_arch_type == MACH_TYPE_F5D8231_4_V2) -#else -# define machine_is_f5d8231_4_v2() (0) -#endif - -#ifdef CONFIG_MACH_Q2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Q2440 -# endif -# define machine_is_q2440() (machine_arch_type == MACH_TYPE_Q2440) -#else -# define machine_is_q2440() (0) -#endif - -#ifdef CONFIG_MACH_QQ2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QQ2440 -# endif -# define machine_is_qq2440() (machine_arch_type == MACH_TYPE_QQ2440) -#else -# define machine_is_qq2440() (0) -#endif - -#ifdef CONFIG_MACH_MINI2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI2440 -# endif -# define machine_is_mini2440() (machine_arch_type == MACH_TYPE_MINI2440) -#else -# define machine_is_mini2440() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI300 -# endif -# define machine_is_colibri300() (machine_arch_type == MACH_TYPE_COLIBRI300) -#else -# define machine_is_colibri300() (0) -#endif - -#ifdef CONFIG_MACH_JADES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADES -# endif -# define machine_is_jades() (machine_arch_type == MACH_TYPE_JADES) -#else -# define machine_is_jades() (0) -#endif - -#ifdef CONFIG_MACH_SPARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPARK -# endif -# define machine_is_spark() (machine_arch_type == MACH_TYPE_SPARK) -#else -# define machine_is_spark() (0) -#endif - -#ifdef CONFIG_MACH_BENZINA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZINA -# endif -# define machine_is_benzina() (machine_arch_type == MACH_TYPE_BENZINA) -#else -# define machine_is_benzina() (0) -#endif - -#ifdef CONFIG_MACH_BLAZE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLAZE -# endif -# define machine_is_blaze() (machine_arch_type == MACH_TYPE_BLAZE) -#else -# define machine_is_blaze() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_LS_HGL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_LS_HGL -# endif -# define machine_is_linkstation_ls_hgl() (machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL) -#else -# define machine_is_linkstation_ls_hgl() (0) -#endif - -#ifdef CONFIG_MACH_HTCVENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCVENUS -# endif -# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCVENUS) -#else -# define machine_is_htckovsky() (0) -#endif - -#ifdef CONFIG_MACH_SONY_PRS505 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONY_PRS505 -# endif -# define machine_is_sony_prs505() (machine_arch_type == MACH_TYPE_SONY_PRS505) -#else -# define machine_is_sony_prs505() (0) -#endif - -#ifdef CONFIG_MACH_HANLIN_V3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HANLIN_V3 -# endif -# define machine_is_hanlin_v3() (machine_arch_type == MACH_TYPE_HANLIN_V3) -#else -# define machine_is_hanlin_v3() (0) -#endif - -#ifdef CONFIG_MACH_SAPPHIRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAPPHIRA -# endif -# define machine_is_sapphira() (machine_arch_type == MACH_TYPE_SAPPHIRA) -#else -# define machine_is_sapphira() (0) -#endif - -#ifdef CONFIG_MACH_DACK_SDA_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DACK_SDA_01 -# endif -# define machine_is_dack_sda_01() (machine_arch_type == MACH_TYPE_DACK_SDA_01) -#else -# define machine_is_dack_sda_01() (0) -#endif - -#ifdef CONFIG_MACH_ARMBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMBOX -# endif -# define machine_is_armbox() (machine_arch_type == MACH_TYPE_ARMBOX) -#else -# define machine_is_armbox() (0) -#endif - -#ifdef CONFIG_MACH_HARRIS_RVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HARRIS_RVP -# endif -# define machine_is_harris_rvp() (machine_arch_type == MACH_TYPE_HARRIS_RVP) -#else -# define machine_is_harris_rvp() (0) -#endif - -#ifdef CONFIG_MACH_RIBALDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIBALDO -# endif -# define machine_is_ribaldo() (machine_arch_type == MACH_TYPE_RIBALDO) -#else -# define machine_is_ribaldo() (0) -#endif - -#ifdef CONFIG_MACH_AGORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AGORA -# endif -# define machine_is_agora() (machine_arch_type == MACH_TYPE_AGORA) -#else -# define machine_is_agora() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_MINI -# endif -# define machine_is_omap3_mini() (machine_arch_type == MACH_TYPE_OMAP3_MINI) -#else -# define machine_is_omap3_mini() (0) -#endif - -#ifdef CONFIG_MACH_A9SAM6432_B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9SAM6432_B -# endif -# define machine_is_a9sam6432_b() (machine_arch_type == MACH_TYPE_A9SAM6432_B) -#else -# define machine_is_a9sam6432_b() (0) -#endif - -#ifdef CONFIG_MACH_USG2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USG2410 -# endif -# define machine_is_usg2410() (machine_arch_type == MACH_TYPE_USG2410) -#else -# define machine_is_usg2410() (0) -#endif - -#ifdef CONFIG_MACH_PC72052_I10_REVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC72052_I10_REVB -# endif -# define machine_is_pc72052_i10_revb() (machine_arch_type == MACH_TYPE_PC72052_I10_REVB) -#else -# define machine_is_pc72052_i10_revb() (0) -#endif - -#ifdef CONFIG_MACH_MX35_EXM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_EXM32 -# endif -# define machine_is_mx35_exm32() (machine_arch_type == MACH_TYPE_MX35_EXM32) -#else -# define machine_is_mx35_exm32() (0) -#endif - -#ifdef CONFIG_MACH_TOPAS910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOPAS910 -# endif -# define machine_is_topas910() (machine_arch_type == MACH_TYPE_TOPAS910) -#else -# define machine_is_topas910() (0) -#endif - -#ifdef CONFIG_MACH_HYENA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYENA -# endif -# define machine_is_hyena() (machine_arch_type == MACH_TYPE_HYENA) -#else -# define machine_is_hyena() (0) -#endif - -#ifdef CONFIG_MACH_POSPAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSPAX -# endif -# define machine_is_pospax() (machine_arch_type == MACH_TYPE_POSPAX) -#else -# define machine_is_pospax() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GX -# endif -# define machine_is_hdl_gx() (machine_arch_type == MACH_TYPE_HDL_GX) -#else -# define machine_is_hdl_gx() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_4BAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_4BAY -# endif -# define machine_is_ctera_4bay() (machine_arch_type == MACH_TYPE_CTERA_4BAY) -#else -# define machine_is_ctera_4bay() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_C -# endif -# define machine_is_ctera_plug_c() (machine_arch_type == MACH_TYPE_CTERA_PLUG_C) -#else -# define machine_is_ctera_plug_c() (0) -#endif - -#ifdef CONFIG_MACH_CRWEA_PLUG_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CRWEA_PLUG_I -# endif -# define machine_is_crwea_plug_i() (machine_arch_type == MACH_TYPE_CRWEA_PLUG_I) -#else -# define machine_is_crwea_plug_i() (0) -#endif - -#ifdef CONFIG_MACH_EGAUGE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EGAUGE2 -# endif -# define machine_is_egauge2() (machine_arch_type == MACH_TYPE_EGAUGE2) -#else -# define machine_is_egauge2() (0) -#endif - -#ifdef CONFIG_MACH_DIDJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIDJ -# endif -# define machine_is_didj() (machine_arch_type == MACH_TYPE_DIDJ) -#else -# define machine_is_didj() (0) -#endif - -#ifdef CONFIG_MACH_MEISTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEISTER -# endif -# define machine_is_m_s3c2443() (machine_arch_type == MACH_TYPE_MEISTER) -#else -# define machine_is_m_s3c2443() (0) -#endif - -#ifdef CONFIG_MACH_HTCBLACKSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCBLACKSTONE -# endif -# define machine_is_htcblackstone() (machine_arch_type == MACH_TYPE_HTCBLACKSTONE) -#else -# define machine_is_htcblackstone() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9G20 -# endif -# define machine_is_cpuat9g20() (machine_arch_type == MACH_TYPE_CPUAT9G20) -#else -# define machine_is_cpuat9g20() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6440 -# endif -# define machine_is_smdk6440() (machine_arch_type == MACH_TYPE_SMDK6440) -#else -# define machine_is_smdk6440() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_35XX_MVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_35XX_MVP -# endif -# define machine_is_omap_35xx_mvp() (machine_arch_type == MACH_TYPE_OMAP_35XX_MVP) -#else -# define machine_is_omap_35xx_mvp() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_I -# endif -# define machine_is_ctera_plug_i() (machine_arch_type == MACH_TYPE_CTERA_PLUG_I) -#else -# define machine_is_ctera_plug_i() (0) -#endif - -#ifdef CONFIG_MACH_PVG610 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PVG610 -# endif -# define machine_is_pvg610_100() (machine_arch_type == MACH_TYPE_PVG610) -#else -# define machine_is_pvg610_100() (0) -#endif - -#ifdef CONFIG_MACH_HPRW6815 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPRW6815 -# endif -# define machine_is_hprw6815() (machine_arch_type == MACH_TYPE_HPRW6815) -#else -# define machine_is_hprw6815() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_OSWALD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_OSWALD -# endif -# define machine_is_omap3_oswald() (machine_arch_type == MACH_TYPE_OMAP3_OSWALD) -#else -# define machine_is_omap3_oswald() (0) -#endif - -#ifdef CONFIG_MACH_NAS4220B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS4220B -# endif -# define machine_is_nas4220b() (machine_arch_type == MACH_TYPE_NAS4220B) -#else -# define machine_is_nas4220b() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA -# endif -# define machine_is_htcraphael_cdma() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA) -#else -# define machine_is_htcraphael_cdma() (0) -#endif - -#ifdef CONFIG_MACH_HTCDIAMOND_CDMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCDIAMOND_CDMA -# endif -# define machine_is_htcdiamond_cdma() (machine_arch_type == MACH_TYPE_HTCDIAMOND_CDMA) -#else -# define machine_is_htcdiamond_cdma() (0) -#endif - -#ifdef CONFIG_MACH_SCALER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCALER -# endif -# define machine_is_scaler() (machine_arch_type == MACH_TYPE_SCALER) -#else -# define machine_is_scaler() (0) -#endif - -#ifdef CONFIG_MACH_ZYLONITE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZYLONITE2 -# endif -# define machine_is_zylonite2() (machine_arch_type == MACH_TYPE_ZYLONITE2) -#else -# define machine_is_zylonite2() (0) -#endif - -#ifdef CONFIG_MACH_ASPENITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASPENITE -# endif -# define machine_is_aspenite() (machine_arch_type == MACH_TYPE_ASPENITE) -#else -# define machine_is_aspenite() (0) -#endif - -#ifdef CONFIG_MACH_TETON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TETON -# endif -# define machine_is_teton() (machine_arch_type == MACH_TYPE_TETON) -#else -# define machine_is_teton() (0) -#endif - -#ifdef CONFIG_MACH_TTC_DKB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TTC_DKB -# endif -# define machine_is_ttc_dkb() (machine_arch_type == MACH_TYPE_TTC_DKB) -#else -# define machine_is_ttc_dkb() (0) -#endif - -#ifdef CONFIG_MACH_BISHOP2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BISHOP2 -# endif -# define machine_is_bishop2() (machine_arch_type == MACH_TYPE_BISHOP2) -#else -# define machine_is_bishop2() (0) -#endif - -#ifdef CONFIG_MACH_IPPV5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPPV5 -# endif -# define machine_is_ippv5() (machine_arch_type == MACH_TYPE_IPPV5) -#else -# define machine_is_ippv5() (0) -#endif - -#ifdef CONFIG_MACH_FARM926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FARM926 -# endif -# define machine_is_farm926() (machine_arch_type == MACH_TYPE_FARM926) -#else -# define machine_is_farm926() (0) -#endif - -#ifdef CONFIG_MACH_MMCCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMCCPU -# endif -# define machine_is_mmccpu() (machine_arch_type == MACH_TYPE_MMCCPU) -#else -# define machine_is_mmccpu() (0) -#endif - -#ifdef CONFIG_MACH_SGMSFL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGMSFL -# endif -# define machine_is_sgmsfl() (machine_arch_type == MACH_TYPE_SGMSFL) -#else -# define machine_is_sgmsfl() (0) -#endif - -#ifdef CONFIG_MACH_TT8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT8000 -# endif -# define machine_is_tt8000() (machine_arch_type == MACH_TYPE_TT8000) -#else -# define machine_is_tt8000() (0) -#endif - -#ifdef CONFIG_MACH_ZRN4300LP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZRN4300LP -# endif -# define machine_is_zrn4300lp() (machine_arch_type == MACH_TYPE_ZRN4300LP) -#else -# define machine_is_zrn4300lp() (0) -#endif - -#ifdef CONFIG_MACH_MPTC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPTC -# endif -# define machine_is_mptc() (machine_arch_type == MACH_TYPE_MPTC) -#else -# define machine_is_mptc() (0) -#endif - -#ifdef CONFIG_MACH_H6051 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6051 -# endif -# define machine_is_h6051() (machine_arch_type == MACH_TYPE_H6051) -#else -# define machine_is_h6051() (0) -#endif - -#ifdef CONFIG_MACH_PVG610_101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PVG610_101 -# endif -# define machine_is_pvg610_101() (machine_arch_type == MACH_TYPE_PVG610_101) -#else -# define machine_is_pvg610_101() (0) -#endif - -#ifdef CONFIG_MACH_STAMP9261_PC_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAMP9261_PC_EVB -# endif -# define machine_is_stamp9261_pc_evb() (machine_arch_type == MACH_TYPE_STAMP9261_PC_EVB) -#else -# define machine_is_stamp9261_pc_evb() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ODYSSEUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ODYSSEUS -# endif -# define machine_is_pelco_odysseus() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEUS) -#else -# define machine_is_pelco_odysseus() (0) -#endif - -#ifdef CONFIG_MACH_TNY_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_A9260 -# endif -# define machine_is_tny_a9260() (machine_arch_type == MACH_TYPE_TNY_A9260) -#else -# define machine_is_tny_a9260() (0) -#endif - -#ifdef CONFIG_MACH_TNY_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_A9G20 -# endif -# define machine_is_tny_a9g20() (machine_arch_type == MACH_TYPE_TNY_A9G20) -#else -# define machine_is_tny_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_AESOP_MP2530F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AESOP_MP2530F -# endif -# define machine_is_aesop_mp2530f() (machine_arch_type == MACH_TYPE_AESOP_MP2530F) -#else -# define machine_is_aesop_mp2530f() (0) -#endif - -#ifdef CONFIG_MACH_DX900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DX900 -# endif -# define machine_is_dx900() (machine_arch_type == MACH_TYPE_DX900) -#else -# define machine_is_dx900() (0) -#endif - -#ifdef CONFIG_MACH_CPODC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPODC2 -# endif -# define machine_is_cpodc2() (machine_arch_type == MACH_TYPE_CPODC2) -#else -# define machine_is_cpodc2() (0) -#endif - -#ifdef CONFIG_MACH_TILT_8925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TILT_8925 -# endif -# define machine_is_tilt_8925() (machine_arch_type == MACH_TYPE_TILT_8925) -#else -# define machine_is_tilt_8925() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM357_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM357_EVM -# endif -# define machine_is_davinci_dm357_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM357_EVM) -#else -# define machine_is_davinci_dm357_evm() (0) -#endif - -#ifdef CONFIG_MACH_SWORDFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWORDFISH -# endif -# define machine_is_swordfish() (machine_arch_type == MACH_TYPE_SWORDFISH) -#else -# define machine_is_swordfish() (0) -#endif - -#ifdef CONFIG_MACH_CORVUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORVUS -# endif -# define machine_is_corvus() (machine_arch_type == MACH_TYPE_CORVUS) -#else -# define machine_is_corvus() (0) -#endif - -#ifdef CONFIG_MACH_TAURUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAURUS -# endif -# define machine_is_taurus() (machine_arch_type == MACH_TYPE_TAURUS) -#else -# define machine_is_taurus() (0) -#endif - -#ifdef CONFIG_MACH_AXM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXM -# endif -# define machine_is_axm() (machine_arch_type == MACH_TYPE_AXM) -#else -# define machine_is_axm() (0) -#endif - -#ifdef CONFIG_MACH_AXC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXC -# endif -# define machine_is_axc() (machine_arch_type == MACH_TYPE_AXC) -#else -# define machine_is_axc() (0) -#endif - -#ifdef CONFIG_MACH_BABY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BABY -# endif -# define machine_is_baby() (machine_arch_type == MACH_TYPE_BABY) -#else -# define machine_is_baby() (0) -#endif - -#ifdef CONFIG_MACH_MP200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP200 -# endif -# define machine_is_mp200() (machine_arch_type == MACH_TYPE_MP200) -#else -# define machine_is_mp200() (0) -#endif - -#ifdef CONFIG_MACH_PCM043 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM043 -# endif -# define machine_is_pcm043() (machine_arch_type == MACH_TYPE_PCM043) -#else -# define machine_is_pcm043() (0) -#endif - -#ifdef CONFIG_MACH_HANLIN_V3C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HANLIN_V3C -# endif -# define machine_is_hanlin_v3c() (machine_arch_type == MACH_TYPE_HANLIN_V3C) -#else -# define machine_is_hanlin_v3c() (0) -#endif - -#ifdef CONFIG_MACH_KBK9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBK9G20 -# endif -# define machine_is_kbk9g20() (machine_arch_type == MACH_TYPE_KBK9G20) -#else -# define machine_is_kbk9g20() (0) -#endif - -#ifdef CONFIG_MACH_ADSTURBOG5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSTURBOG5 -# endif -# define machine_is_adsturbog5() (machine_arch_type == MACH_TYPE_ADSTURBOG5) -#else -# define machine_is_adsturbog5() (0) -#endif - -#ifdef CONFIG_MACH_AVENGER_LITE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVENGER_LITE1 -# endif -# define machine_is_avenger_lite1() (machine_arch_type == MACH_TYPE_AVENGER_LITE1) -#else -# define machine_is_avenger_lite1() (0) -#endif - -#ifdef CONFIG_MACH_SUC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUC -# endif -# define machine_is_suc82x() (machine_arch_type == MACH_TYPE_SUC) -#else -# define machine_is_suc82x() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM7S256 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM7S256 -# endif -# define machine_is_at91sam7s256() (machine_arch_type == MACH_TYPE_AT91SAM7S256) -#else -# define machine_is_at91sam7s256() (0) -#endif - -#ifdef CONFIG_MACH_MENDOZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MENDOZA -# endif -# define machine_is_mendoza() (machine_arch_type == MACH_TYPE_MENDOZA) -#else -# define machine_is_mendoza() (0) -#endif - -#ifdef CONFIG_MACH_KIRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIRA -# endif -# define machine_is_kira() (machine_arch_type == MACH_TYPE_KIRA) -#else -# define machine_is_kira() (0) -#endif - -#ifdef CONFIG_MACH_MX1HBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1HBM -# endif -# define machine_is_mx1hbm() (machine_arch_type == MACH_TYPE_MX1HBM) -#else -# define machine_is_mx1hbm() (0) -#endif - -#ifdef CONFIG_MACH_QUATRO43XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUATRO43XX -# endif -# define machine_is_quatro43xx() (machine_arch_type == MACH_TYPE_QUATRO43XX) -#else -# define machine_is_quatro43xx() (0) -#endif - -#ifdef CONFIG_MACH_QUATRO4230 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUATRO4230 -# endif -# define machine_is_quatro4230() (machine_arch_type == MACH_TYPE_QUATRO4230) -#else -# define machine_is_quatro4230() (0) -#endif - -#ifdef CONFIG_MACH_NSB400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB400 -# endif -# define machine_is_nsb400() (machine_arch_type == MACH_TYPE_NSB400) -#else -# define machine_is_nsb400() (0) -#endif - -#ifdef CONFIG_MACH_DRP255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DRP255 -# endif -# define machine_is_drp255() (machine_arch_type == MACH_TYPE_DRP255) -#else -# define machine_is_drp255() (0) -#endif - -#ifdef CONFIG_MACH_THOTH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_THOTH -# endif -# define machine_is_thoth() (machine_arch_type == MACH_TYPE_THOTH) -#else -# define machine_is_thoth() (0) -#endif - -#ifdef CONFIG_MACH_FIRESTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FIRESTONE -# endif -# define machine_is_firestone() (machine_arch_type == MACH_TYPE_FIRESTONE) -#else -# define machine_is_firestone() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP750 -# endif -# define machine_is_asusp750() (machine_arch_type == MACH_TYPE_ASUSP750) -#else -# define machine_is_asusp750() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_DL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_DL -# endif -# define machine_is_ctera_dl() (machine_arch_type == MACH_TYPE_CTERA_DL) -#else -# define machine_is_ctera_dl() (0) -#endif - -#ifdef CONFIG_MACH_SOCR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOCR -# endif -# define machine_is_socr() (machine_arch_type == MACH_TYPE_SOCR) -#else -# define machine_is_socr() (0) -#endif - -#ifdef CONFIG_MACH_HTCOXYGEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCOXYGEN -# endif -# define machine_is_htcoxygen() (machine_arch_type == MACH_TYPE_HTCOXYGEN) -#else -# define machine_is_htcoxygen() (0) -#endif - -#ifdef CONFIG_MACH_HEROC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HEROC -# endif -# define machine_is_heroc() (machine_arch_type == MACH_TYPE_HEROC) -#else -# define machine_is_heroc() (0) -#endif - -#ifdef CONFIG_MACH_ZENO6800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZENO6800 -# endif -# define machine_is_zeno6800() (machine_arch_type == MACH_TYPE_ZENO6800) -#else -# define machine_is_zeno6800() (0) -#endif - -#ifdef CONFIG_MACH_SC2MCS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC2MCS -# endif -# define machine_is_sc2mcs() (machine_arch_type == MACH_TYPE_SC2MCS) -#else -# define machine_is_sc2mcs() (0) -#endif - -#ifdef CONFIG_MACH_GENE100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENE100 -# endif -# define machine_is_gene100() (machine_arch_type == MACH_TYPE_GENE100) -#else -# define machine_is_gene100() (0) -#endif - -#ifdef CONFIG_MACH_AS353X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS353X -# endif -# define machine_is_as353x() (machine_arch_type == MACH_TYPE_AS353X) -#else -# define machine_is_as353x() (0) -#endif - -#ifdef CONFIG_MACH_SHEEVAPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEEVAPLUG -# endif -# define machine_is_sheevaplug() (machine_arch_type == MACH_TYPE_SHEEVAPLUG) -#else -# define machine_is_sheevaplug() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20 -# endif -# define machine_is_at91sam9g20() (machine_arch_type == MACH_TYPE_AT91SAM9G20) -#else -# define machine_is_at91sam9g20() (0) -#endif - -#ifdef CONFIG_MACH_MV88F6192GTW_FE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88F6192GTW_FE -# endif -# define machine_is_mv88f6192gtw_fe() (machine_arch_type == MACH_TYPE_MV88F6192GTW_FE) -#else -# define machine_is_mv88f6192gtw_fe() (0) -#endif - -#ifdef CONFIG_MACH_CC9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9200 -# endif -# define machine_is_cc9200() (machine_arch_type == MACH_TYPE_CC9200) -#else -# define machine_is_cc9200() (0) -#endif - -#ifdef CONFIG_MACH_SM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SM9200 -# endif -# define machine_is_sm9200() (machine_arch_type == MACH_TYPE_SM9200) -#else -# define machine_is_sm9200() (0) -#endif - -#ifdef CONFIG_MACH_TP9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TP9200 -# endif -# define machine_is_tp9200() (machine_arch_type == MACH_TYPE_TP9200) -#else -# define machine_is_tp9200() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPERDV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPERDV -# endif -# define machine_is_snapperdv() (machine_arch_type == MACH_TYPE_SNAPPERDV) -#else -# define machine_is_snapperdv() (0) -#endif - -#ifdef CONFIG_MACH_AVENGERS_LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVENGERS_LITE -# endif -# define machine_is_avengers_lite() (machine_arch_type == MACH_TYPE_AVENGERS_LITE) -#else -# define machine_is_avengers_lite() (0) -#endif - -#ifdef CONFIG_MACH_AVENGERS_LITE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVENGERS_LITE1 -# endif -# define machine_is_avengers_lite1() (machine_arch_type == MACH_TYPE_AVENGERS_LITE1) -#else -# define machine_is_avengers_lite1() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3AXON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3AXON -# endif -# define machine_is_omap3axon() (machine_arch_type == MACH_TYPE_OMAP3AXON) -#else -# define machine_is_omap3axon() (0) -#endif - -#ifdef CONFIG_MACH_MA8XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MA8XX -# endif -# define machine_is_ma8xx() (machine_arch_type == MACH_TYPE_MA8XX) -#else -# define machine_is_ma8xx() (0) -#endif - -#ifdef CONFIG_MACH_MP201EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP201EK -# endif -# define machine_is_mp201ek() (machine_arch_type == MACH_TYPE_MP201EK) -#else -# define machine_is_mp201ek() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_TUX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_TUX -# endif -# define machine_is_davinci_tux() (machine_arch_type == MACH_TYPE_DAVINCI_TUX) -#else -# define machine_is_davinci_tux() (0) -#endif - -#ifdef CONFIG_MACH_MPA1600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPA1600 -# endif -# define machine_is_mpa1600() (machine_arch_type == MACH_TYPE_MPA1600) -#else -# define machine_is_mpa1600() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_TROY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_TROY -# endif -# define machine_is_pelco_troy() (machine_arch_type == MACH_TYPE_PELCO_TROY) -#else -# define machine_is_pelco_troy() (0) -#endif - -#ifdef CONFIG_MACH_NSB667 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB667 -# endif -# define machine_is_nsb667() (machine_arch_type == MACH_TYPE_NSB667) -#else -# define machine_is_nsb667() (0) -#endif - -#ifdef CONFIG_MACH_ROVERS5_4MPIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERS5_4MPIX -# endif -# define machine_is_rovers5_4mpix() (machine_arch_type == MACH_TYPE_ROVERS5_4MPIX) -#else -# define machine_is_rovers5_4mpix() (0) -#endif - -#ifdef CONFIG_MACH_TWOCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TWOCOM -# endif -# define machine_is_twocom() (machine_arch_type == MACH_TYPE_TWOCOM) -#else -# define machine_is_twocom() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_RCU3R2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_RCU3R2 -# endif -# define machine_is_ubisys_p9_rcu3r2() (machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3R2) -#else -# define machine_is_ubisys_p9_rcu3r2() (0) -#endif - -#ifdef CONFIG_MACH_HERO_ESPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERO_ESPRESSO -# endif -# define machine_is_hero_espresso() (machine_arch_type == MACH_TYPE_HERO_ESPRESSO) -#else -# define machine_is_hero_espresso() (0) -#endif - -#ifdef CONFIG_MACH_AFEUSB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFEUSB -# endif -# define machine_is_afeusb() (machine_arch_type == MACH_TYPE_AFEUSB) -#else -# define machine_is_afeusb() (0) -#endif - -#ifdef CONFIG_MACH_T830 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T830 -# endif -# define machine_is_t830() (machine_arch_type == MACH_TYPE_T830) -#else -# define machine_is_t830() (0) -#endif - -#ifdef CONFIG_MACH_SPD8020_CC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPD8020_CC -# endif -# define machine_is_spd8020_cc() (machine_arch_type == MACH_TYPE_SPD8020_CC) -#else -# define machine_is_spd8020_cc() (0) -#endif - -#ifdef CONFIG_MACH_OM_3D7K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OM_3D7K -# endif -# define machine_is_om_3d7k() (machine_arch_type == MACH_TYPE_OM_3D7K) -#else -# define machine_is_om_3d7k() (0) -#endif - -#ifdef CONFIG_MACH_PICOCOM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOCOM2 -# endif -# define machine_is_picocom2() (machine_arch_type == MACH_TYPE_PICOCOM2) -#else -# define machine_is_picocom2() (0) -#endif - -#ifdef CONFIG_MACH_UWG4MX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UWG4MX27 -# endif -# define machine_is_uwg4mx27() (machine_arch_type == MACH_TYPE_UWG4MX27) -#else -# define machine_is_uwg4mx27() (0) -#endif - -#ifdef CONFIG_MACH_UWG4MX31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UWG4MX31 -# endif -# define machine_is_uwg4mx31() (machine_arch_type == MACH_TYPE_UWG4MX31) -#else -# define machine_is_uwg4mx31() (0) -#endif - -#ifdef CONFIG_MACH_CHERRY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHERRY -# endif -# define machine_is_cherry() (machine_arch_type == MACH_TYPE_CHERRY) -#else -# define machine_is_cherry() (0) -#endif - -#ifdef CONFIG_MACH_MX51_BABBAGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_BABBAGE -# endif -# define machine_is_mx51_babbage() (machine_arch_type == MACH_TYPE_MX51_BABBAGE) -#else -# define machine_is_mx51_babbage() (0) -#endif - -#ifdef CONFIG_MACH_S3C2440TURKIYE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2440TURKIYE -# endif -# define machine_is_s3c2440turkiye() (machine_arch_type == MACH_TYPE_S3C2440TURKIYE) -#else -# define machine_is_s3c2440turkiye() (0) -#endif - -#ifdef CONFIG_MACH_TX37 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX37 -# endif -# define machine_is_tx37() (machine_arch_type == MACH_TYPE_TX37) -#else -# define machine_is_tx37() (0) -#endif - -#ifdef CONFIG_MACH_SBC2800_9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2800_9G20 -# endif -# define machine_is_sbc2800_9g20() (machine_arch_type == MACH_TYPE_SBC2800_9G20) -#else -# define machine_is_sbc2800_9g20() (0) -#endif - -#ifdef CONFIG_MACH_BENZGLB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZGLB -# endif -# define machine_is_benzglb() (machine_arch_type == MACH_TYPE_BENZGLB) -#else -# define machine_is_benzglb() (0) -#endif - -#ifdef CONFIG_MACH_BENZTD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZTD -# endif -# define machine_is_benztd() (machine_arch_type == MACH_TYPE_BENZTD) -#else -# define machine_is_benztd() (0) -#endif - -#ifdef CONFIG_MACH_CARTESIO_PLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARTESIO_PLUS -# endif -# define machine_is_cartesio_plus() (machine_arch_type == MACH_TYPE_CARTESIO_PLUS) -#else -# define machine_is_cartesio_plus() (0) -#endif - -#ifdef CONFIG_MACH_SOLRAD_G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOLRAD_G20 -# endif -# define machine_is_solrad_g20() (machine_arch_type == MACH_TYPE_SOLRAD_G20) -#else -# define machine_is_solrad_g20() (0) -#endif - -#ifdef CONFIG_MACH_MX27WALLACE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27WALLACE -# endif -# define machine_is_mx27wallace() (machine_arch_type == MACH_TYPE_MX27WALLACE) -#else -# define machine_is_mx27wallace() (0) -#endif - -#ifdef CONFIG_MACH_FMZWEBMODUL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FMZWEBMODUL -# endif -# define machine_is_fmzwebmodul() (machine_arch_type == MACH_TYPE_FMZWEBMODUL) -#else -# define machine_is_fmzwebmodul() (0) -#endif - -#ifdef CONFIG_MACH_RD78X00_MASA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD78X00_MASA -# endif -# define machine_is_rd78x00_masa() (machine_arch_type == MACH_TYPE_RD78X00_MASA) -#else -# define machine_is_rd78x00_masa() (0) -#endif - -#ifdef CONFIG_MACH_SMALLOGGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMALLOGGER -# endif -# define machine_is_smallogger() (machine_arch_type == MACH_TYPE_SMALLOGGER) -#else -# define machine_is_smallogger() (0) -#endif - -#ifdef CONFIG_MACH_CCW9P9215 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9P9215 -# endif -# define machine_is_ccw9p9215() (machine_arch_type == MACH_TYPE_CCW9P9215) -#else -# define machine_is_ccw9p9215() (0) -#endif - -#ifdef CONFIG_MACH_DM355_LEOPARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM355_LEOPARD -# endif -# define machine_is_dm355_leopard() (machine_arch_type == MACH_TYPE_DM355_LEOPARD) -#else -# define machine_is_dm355_leopard() (0) -#endif - -#ifdef CONFIG_MACH_TS219 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS219 -# endif -# define machine_is_ts219() (machine_arch_type == MACH_TYPE_TS219) -#else -# define machine_is_ts219() (0) -#endif - -#ifdef CONFIG_MACH_TNY_A9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_A9263 -# endif -# define machine_is_tny_a9263() (machine_arch_type == MACH_TYPE_TNY_A9263) -#else -# define machine_is_tny_a9263() (0) -#endif - -#ifdef CONFIG_MACH_APOLLO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APOLLO -# endif -# define machine_is_apollo() (machine_arch_type == MACH_TYPE_APOLLO) -#else -# define machine_is_apollo() (0) -#endif - -#ifdef CONFIG_MACH_AT91CAP9STK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91CAP9STK -# endif -# define machine_is_at91cap9stk() (machine_arch_type == MACH_TYPE_AT91CAP9STK) -#else -# define machine_is_at91cap9stk() (0) -#endif - -#ifdef CONFIG_MACH_SPC300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPC300 -# endif -# define machine_is_spc300() (machine_arch_type == MACH_TYPE_SPC300) -#else -# define machine_is_spc300() (0) -#endif - -#ifdef CONFIG_MACH_EKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EKO -# endif -# define machine_is_eko() (machine_arch_type == MACH_TYPE_EKO) -#else -# define machine_is_eko() (0) -#endif - -#ifdef CONFIG_MACH_CCW9M2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9M2443 -# endif -# define machine_is_ccw9m2443() (machine_arch_type == MACH_TYPE_CCW9M2443) -#else -# define machine_is_ccw9m2443() (0) -#endif - -#ifdef CONFIG_MACH_CCW9M2443JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9M2443JS -# endif -# define machine_is_ccw9m2443js() (machine_arch_type == MACH_TYPE_CCW9M2443JS) -#else -# define machine_is_ccw9m2443js() (0) -#endif - -#ifdef CONFIG_MACH_M2M_ROUTER_DEVICE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M2M_ROUTER_DEVICE -# endif -# define machine_is_m2m_router_device() (machine_arch_type == MACH_TYPE_M2M_ROUTER_DEVICE) -#else -# define machine_is_m2m_router_device() (0) -#endif - -#ifdef CONFIG_MACH_STAR9104NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAR9104NAS -# endif -# define machine_is_str9104nas() (machine_arch_type == MACH_TYPE_STAR9104NAS) -#else -# define machine_is_str9104nas() (0) -#endif - -#ifdef CONFIG_MACH_PCA100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCA100 -# endif -# define machine_is_pca100() (machine_arch_type == MACH_TYPE_PCA100) -#else -# define machine_is_pca100() (0) -#endif - -#ifdef CONFIG_MACH_Z3_DM365_MOD_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z3_DM365_MOD_01 -# endif -# define machine_is_z3_dm365_mod_01() (machine_arch_type == MACH_TYPE_Z3_DM365_MOD_01) -#else -# define machine_is_z3_dm365_mod_01() (0) -#endif - -#ifdef CONFIG_MACH_HIPOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIPOX -# endif -# define machine_is_hipox() (machine_arch_type == MACH_TYPE_HIPOX) -#else -# define machine_is_hipox() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_PITEDS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_PITEDS -# endif -# define machine_is_omap3_piteds() (machine_arch_type == MACH_TYPE_OMAP3_PITEDS) -#else -# define machine_is_omap3_piteds() (0) -#endif - -#ifdef CONFIG_MACH_BM150R -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BM150R -# endif -# define machine_is_bm150r() (machine_arch_type == MACH_TYPE_BM150R) -#else -# define machine_is_bm150r() (0) -#endif - -#ifdef CONFIG_MACH_TBONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBONE -# endif -# define machine_is_tbone() (machine_arch_type == MACH_TYPE_TBONE) -#else -# define machine_is_tbone() (0) -#endif - -#ifdef CONFIG_MACH_MERLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MERLIN -# endif -# define machine_is_merlin() (machine_arch_type == MACH_TYPE_MERLIN) -#else -# define machine_is_merlin() (0) -#endif - -#ifdef CONFIG_MACH_FALCON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FALCON -# endif -# define machine_is_falcon() (machine_arch_type == MACH_TYPE_FALCON) -#else -# define machine_is_falcon() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DA850_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DA850_EVM -# endif -# define machine_is_davinci_da850_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) -#else -# define machine_is_davinci_da850_evm() (0) -#endif - -#ifdef CONFIG_MACH_S5P6440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5P6440 -# endif -# define machine_is_s5p6440() (machine_arch_type == MACH_TYPE_S5P6440) -#else -# define machine_is_s5p6440() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G10EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G10EK -# endif -# define machine_is_at91sam9g10ek() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK) -#else -# define machine_is_at91sam9g10ek() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_4430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_4430SDP -# endif -# define machine_is_omap_4430sdp() (machine_arch_type == MACH_TYPE_OMAP_4430SDP) -#else -# define machine_is_omap_4430sdp() (0) -#endif - -#ifdef CONFIG_MACH_LPC313X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC313X -# endif -# define machine_is_lpc313x() (machine_arch_type == MACH_TYPE_LPC313X) -#else -# define machine_is_lpc313x() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_ZN5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_ZN5 -# endif -# define machine_is_magx_zn5() (machine_arch_type == MACH_TYPE_MAGX_ZN5) -#else -# define machine_is_magx_zn5() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_EM30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_EM30 -# endif -# define machine_is_magx_em30() (machine_arch_type == MACH_TYPE_MAGX_EM30) -#else -# define machine_is_magx_em30() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_VE66 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_VE66 -# endif -# define machine_is_magx_ve66() (machine_arch_type == MACH_TYPE_MAGX_VE66) -#else -# define machine_is_magx_ve66() (0) -#endif - -#ifdef CONFIG_MACH_MEESC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEESC -# endif -# define machine_is_meesc() (machine_arch_type == MACH_TYPE_MEESC) -#else -# define machine_is_meesc() (0) -#endif - -#ifdef CONFIG_MACH_OTC570 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTC570 -# endif -# define machine_is_otc570() (machine_arch_type == MACH_TYPE_OTC570) -#else -# define machine_is_otc570() (0) -#endif - -#ifdef CONFIG_MACH_BCU2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCU2412 -# endif -# define machine_is_bcu2412() (machine_arch_type == MACH_TYPE_BCU2412) -#else -# define machine_is_bcu2412() (0) -#endif - -#ifdef CONFIG_MACH_BEACON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEACON -# endif -# define machine_is_beacon() (machine_arch_type == MACH_TYPE_BEACON) -#else -# define machine_is_beacon() (0) -#endif - -#ifdef CONFIG_MACH_ACTIA_TGW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTIA_TGW -# endif -# define machine_is_actia_tgw() (machine_arch_type == MACH_TYPE_ACTIA_TGW) -#else -# define machine_is_actia_tgw() (0) -#endif - -#ifdef CONFIG_MACH_E4430 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E4430 -# endif -# define machine_is_e4430() (machine_arch_type == MACH_TYPE_E4430) -#else -# define machine_is_e4430() (0) -#endif - -#ifdef CONFIG_MACH_QL300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QL300 -# endif -# define machine_is_ql300() (machine_arch_type == MACH_TYPE_QL300) -#else -# define machine_is_ql300() (0) -#endif - -#ifdef CONFIG_MACH_BTMAVB101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTMAVB101 -# endif -# define machine_is_btmavb101() (machine_arch_type == MACH_TYPE_BTMAVB101) -#else -# define machine_is_btmavb101() (0) -#endif - -#ifdef CONFIG_MACH_BTMAWB101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTMAWB101 -# endif -# define machine_is_btmawb101() (machine_arch_type == MACH_TYPE_BTMAWB101) -#else -# define machine_is_btmawb101() (0) -#endif - -#ifdef CONFIG_MACH_SQ201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SQ201 -# endif -# define machine_is_sq201() (machine_arch_type == MACH_TYPE_SQ201) -#else -# define machine_is_sq201() (0) -#endif - -#ifdef CONFIG_MACH_QUATRO45XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUATRO45XX -# endif -# define machine_is_quatro45xx() (machine_arch_type == MACH_TYPE_QUATRO45XX) -#else -# define machine_is_quatro45xx() (0) -#endif - -#ifdef CONFIG_MACH_OPENPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENPAD -# endif -# define machine_is_openpad() (machine_arch_type == MACH_TYPE_OPENPAD) -#else -# define machine_is_openpad() (0) -#endif - -#ifdef CONFIG_MACH_TX25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX25 -# endif -# define machine_is_tx25() (machine_arch_type == MACH_TYPE_TX25) -#else -# define machine_is_tx25() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_TORPEDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_TORPEDO -# endif -# define machine_is_omap3_torpedo() (machine_arch_type == MACH_TYPE_OMAP3_TORPEDO) -#else -# define machine_is_omap3_torpedo() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL_K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL_K -# endif -# define machine_is_htcraphael_k() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_K) -#else -# define machine_is_htcraphael_k() (0) -#endif - -#ifdef CONFIG_MACH_LAL43 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LAL43 -# endif -# define machine_is_lal43() (machine_arch_type == MACH_TYPE_LAL43) -#else -# define machine_is_lal43() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA500 -# endif -# define machine_is_htcraphael_cdma500() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA500) -#else -# define machine_is_htcraphael_cdma500() (0) -#endif - -#ifdef CONFIG_MACH_ANW6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANW6410 -# endif -# define machine_is_anw6410() (machine_arch_type == MACH_TYPE_ANW6410) -#else -# define machine_is_anw6410() (0) -#endif - -#ifdef CONFIG_MACH_HTCPROPHET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPROPHET -# endif -# define machine_is_htcprophet() (machine_arch_type == MACH_TYPE_HTCPROPHET) -#else -# define machine_is_htcprophet() (0) -#endif - -#ifdef CONFIG_MACH_CFA_10022 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CFA_10022 -# endif -# define machine_is_cfa_10022() (machine_arch_type == MACH_TYPE_CFA_10022) -#else -# define machine_is_cfa_10022() (0) -#endif - -#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27_VISSTRIM_M10 -# endif -# define machine_is_imx27_visstrim_m10() (machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10) -#else -# define machine_is_imx27_visstrim_m10() (0) -#endif - -#ifdef CONFIG_MACH_PX2IMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PX2IMX27 -# endif -# define machine_is_px2imx27() (machine_arch_type == MACH_TYPE_PX2IMX27) -#else -# define machine_is_px2imx27() (0) -#endif - -#ifdef CONFIG_MACH_STM3210E_EVAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STM3210E_EVAL -# endif -# define machine_is_stm3210e_eval() (machine_arch_type == MACH_TYPE_STM3210E_EVAL) -#else -# define machine_is_stm3210e_eval() (0) -#endif - -#ifdef CONFIG_MACH_DVS10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DVS10 -# endif -# define machine_is_dvs10() (machine_arch_type == MACH_TYPE_DVS10) -#else -# define machine_is_dvs10() (0) -#endif - -#ifdef CONFIG_MACH_PORTUXG20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PORTUXG20 -# endif -# define machine_is_portuxg20() (machine_arch_type == MACH_TYPE_PORTUXG20) -#else -# define machine_is_portuxg20() (0) -#endif - -#ifdef CONFIG_MACH_ARM_SPV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM_SPV -# endif -# define machine_is_arm_spv() (machine_arch_type == MACH_TYPE_ARM_SPV) -#else -# define machine_is_arm_spv() (0) -#endif - -#ifdef CONFIG_MACH_SMDKC110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKC110 -# endif -# define machine_is_smdkc110() (machine_arch_type == MACH_TYPE_SMDKC110) -#else -# define machine_is_smdkc110() (0) -#endif - -#ifdef CONFIG_MACH_CABESPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CABESPRESSO -# endif -# define machine_is_cabespresso() (machine_arch_type == MACH_TYPE_CABESPRESSO) -#else -# define machine_is_cabespresso() (0) -#endif - -#ifdef CONFIG_MACH_HMC800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMC800 -# endif -# define machine_is_hmc800() (machine_arch_type == MACH_TYPE_HMC800) -#else -# define machine_is_hmc800() (0) -#endif - -#ifdef CONFIG_MACH_SHOLES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHOLES -# endif -# define machine_is_sholes() (machine_arch_type == MACH_TYPE_SHOLES) -#else -# define machine_is_sholes() (0) -#endif - -#ifdef CONFIG_MACH_BTMXC31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTMXC31 -# endif -# define machine_is_btmxc31() (machine_arch_type == MACH_TYPE_BTMXC31) -#else -# define machine_is_btmxc31() (0) -#endif - -#ifdef CONFIG_MACH_DT501 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DT501 -# endif -# define machine_is_dt501() (machine_arch_type == MACH_TYPE_DT501) -#else -# define machine_is_dt501() (0) -#endif - -#ifdef CONFIG_MACH_KTX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KTX -# endif -# define machine_is_ktx() (machine_arch_type == MACH_TYPE_KTX) -#else -# define machine_is_ktx() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3517EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3517EVM -# endif -# define machine_is_omap3517evm() (machine_arch_type == MACH_TYPE_OMAP3517EVM) -#else -# define machine_is_omap3517evm() (0) -#endif - -#ifdef CONFIG_MACH_NETSPACE_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSPACE_V2 -# endif -# define machine_is_netspace_v2() (machine_arch_type == MACH_TYPE_NETSPACE_V2) -#else -# define machine_is_netspace_v2() (0) -#endif - -#ifdef CONFIG_MACH_NETSPACE_MAX_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSPACE_MAX_V2 -# endif -# define machine_is_netspace_max_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2) -#else -# define machine_is_netspace_max_v2() (0) -#endif - -#ifdef CONFIG_MACH_D2NET_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D2NET_V2 -# endif -# define machine_is_d2net_v2() (machine_arch_type == MACH_TYPE_D2NET_V2) -#else -# define machine_is_d2net_v2() (0) -#endif - -#ifdef CONFIG_MACH_NET2BIG_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET2BIG_V2 -# endif -# define machine_is_net2big_v2() (machine_arch_type == MACH_TYPE_NET2BIG_V2) -#else -# define machine_is_net2big_v2() (0) -#endif - -#ifdef CONFIG_MACH_NET4BIG_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET4BIG_V2 -# endif -# define machine_is_net4big_v2() (machine_arch_type == MACH_TYPE_NET4BIG_V2) -#else -# define machine_is_net4big_v2() (0) -#endif - -#ifdef CONFIG_MACH_NET5BIG_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET5BIG_V2 -# endif -# define machine_is_net5big_v2() (machine_arch_type == MACH_TYPE_NET5BIG_V2) -#else -# define machine_is_net5big_v2() (0) -#endif - -#ifdef CONFIG_MACH_ENDB2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENDB2443 -# endif -# define machine_is_endb2443() (machine_arch_type == MACH_TYPE_ENDB2443) -#else -# define machine_is_endb2443() (0) -#endif - -#ifdef CONFIG_MACH_INETSPACE_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INETSPACE_V2 -# endif -# define machine_is_inetspace_v2() (machine_arch_type == MACH_TYPE_INETSPACE_V2) -#else -# define machine_is_inetspace_v2() (0) -#endif - -#ifdef CONFIG_MACH_TROS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TROS -# endif -# define machine_is_tros() (machine_arch_type == MACH_TYPE_TROS) -#else -# define machine_is_tros() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_HOMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_HOMER -# endif -# define machine_is_pelco_homer() (machine_arch_type == MACH_TYPE_PELCO_HOMER) -#else -# define machine_is_pelco_homer() (0) -#endif - -#ifdef CONFIG_MACH_OFSP8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OFSP8 -# endif -# define machine_is_ofsp8() (machine_arch_type == MACH_TYPE_OFSP8) -#else -# define machine_is_ofsp8() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G45EKES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G45EKES -# endif -# define machine_is_at91sam9g45ekes() (machine_arch_type == MACH_TYPE_AT91SAM9G45EKES) -#else -# define machine_is_at91sam9g45ekes() (0) -#endif - -#ifdef CONFIG_MACH_GUF_CUPID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUF_CUPID -# endif -# define machine_is_guf_cupid() (machine_arch_type == MACH_TYPE_GUF_CUPID) -#else -# define machine_is_guf_cupid() (0) -#endif - -#ifdef CONFIG_MACH_EAB1R -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EAB1R -# endif -# define machine_is_eab1r() (machine_arch_type == MACH_TYPE_EAB1R) -#else -# define machine_is_eab1r() (0) -#endif - -#ifdef CONFIG_MACH_DESIREC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DESIREC -# endif -# define machine_is_desirec() (machine_arch_type == MACH_TYPE_DESIREC) -#else -# define machine_is_desirec() (0) -#endif - -#ifdef CONFIG_MACH_CORDOBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORDOBA -# endif -# define machine_is_cordoba() (machine_arch_type == MACH_TYPE_CORDOBA) -#else -# define machine_is_cordoba() (0) -#endif - -#ifdef CONFIG_MACH_IRVINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IRVINE -# endif -# define machine_is_irvine() (machine_arch_type == MACH_TYPE_IRVINE) -#else -# define machine_is_irvine() (0) -#endif - -#ifdef CONFIG_MACH_SFF772 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFF772 -# endif -# define machine_is_sff772() (machine_arch_type == MACH_TYPE_SFF772) -#else -# define machine_is_sff772() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_MILANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_MILANO -# endif -# define machine_is_pelco_milano() (machine_arch_type == MACH_TYPE_PELCO_MILANO) -#else -# define machine_is_pelco_milano() (0) -#endif - -#ifdef CONFIG_MACH_PC7302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC7302 -# endif -# define machine_is_pc7302() (machine_arch_type == MACH_TYPE_PC7302) -#else -# define machine_is_pc7302() (0) -#endif - -#ifdef CONFIG_MACH_BIP6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIP6000 -# endif -# define machine_is_bip6000() (machine_arch_type == MACH_TYPE_BIP6000) -#else -# define machine_is_bip6000() (0) -#endif - -#ifdef CONFIG_MACH_SILVERMOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SILVERMOON -# endif -# define machine_is_silvermoon() (machine_arch_type == MACH_TYPE_SILVERMOON) -#else -# define machine_is_silvermoon() (0) -#endif - -#ifdef CONFIG_MACH_VC0830 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC0830 -# endif -# define machine_is_vc0830() (machine_arch_type == MACH_TYPE_VC0830) -#else -# define machine_is_vc0830() (0) -#endif - -#ifdef CONFIG_MACH_DT430 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DT430 -# endif -# define machine_is_dt430() (machine_arch_type == MACH_TYPE_DT430) -#else -# define machine_is_dt430() (0) -#endif - -#ifdef CONFIG_MACH_JI42PF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JI42PF -# endif -# define machine_is_ji42pf() (machine_arch_type == MACH_TYPE_JI42PF) -#else -# define machine_is_ji42pf() (0) -#endif - -#ifdef CONFIG_MACH_GNET_KSM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_KSM -# endif -# define machine_is_gnet_ksm() (machine_arch_type == MACH_TYPE_GNET_KSM) -#else -# define machine_is_gnet_ksm() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SGM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SGM -# endif -# define machine_is_gnet_sgm() (machine_arch_type == MACH_TYPE_GNET_SGM) -#else -# define machine_is_gnet_sgm() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SGR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SGR -# endif -# define machine_is_gnet_sgr() (machine_arch_type == MACH_TYPE_GNET_SGR) -#else -# define machine_is_gnet_sgr() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_ICETEKEVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_ICETEKEVM -# endif -# define machine_is_omap3_icetekevm() (machine_arch_type == MACH_TYPE_OMAP3_ICETEKEVM) -#else -# define machine_is_omap3_icetekevm() (0) -#endif - -#ifdef CONFIG_MACH_PNP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNP -# endif -# define machine_is_pnp() (machine_arch_type == MACH_TYPE_PNP) -#else -# define machine_is_pnp() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY_K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY_K -# endif -# define machine_is_ctera_2bay_k() (machine_arch_type == MACH_TYPE_CTERA_2BAY_K) -#else -# define machine_is_ctera_2bay_k() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY_U -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY_U -# endif -# define machine_is_ctera_2bay_u() (machine_arch_type == MACH_TYPE_CTERA_2BAY_U) -#else -# define machine_is_ctera_2bay_u() (0) -#endif - -#ifdef CONFIG_MACH_SAS_C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAS_C -# endif -# define machine_is_sas_c() (machine_arch_type == MACH_TYPE_SAS_C) -#else -# define machine_is_sas_c() (0) -#endif - -#ifdef CONFIG_MACH_VMA2315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VMA2315 -# endif -# define machine_is_vma2315() (machine_arch_type == MACH_TYPE_VMA2315) -#else -# define machine_is_vma2315() (0) -#endif - -#ifdef CONFIG_MACH_VCS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCS -# endif -# define machine_is_vcs() (machine_arch_type == MACH_TYPE_VCS) -#else -# define machine_is_vcs() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR600 -# endif -# define machine_is_spear600() (machine_arch_type == MACH_TYPE_SPEAR600) -#else -# define machine_is_spear600() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR300 -# endif -# define machine_is_spear300() (machine_arch_type == MACH_TYPE_SPEAR300) -#else -# define machine_is_spear300() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR1300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR1300 -# endif -# define machine_is_spear1300() (machine_arch_type == MACH_TYPE_SPEAR1300) -#else -# define machine_is_spear1300() (0) -#endif - -#ifdef CONFIG_MACH_LILLY1131 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LILLY1131 -# endif -# define machine_is_lilly1131() (machine_arch_type == MACH_TYPE_LILLY1131) -#else -# define machine_is_lilly1131() (0) -#endif - -#ifdef CONFIG_MACH_ARVOO_AX301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARVOO_AX301 -# endif -# define machine_is_arvoo_ax301() (machine_arch_type == MACH_TYPE_ARVOO_AX301) -#else -# define machine_is_arvoo_ax301() (0) -#endif - -#ifdef CONFIG_MACH_MAPPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAPPHONE -# endif -# define machine_is_mapphone() (machine_arch_type == MACH_TYPE_MAPPHONE) -#else -# define machine_is_mapphone() (0) -#endif - -#ifdef CONFIG_MACH_LEGEND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEGEND -# endif -# define machine_is_legend() (machine_arch_type == MACH_TYPE_LEGEND) -#else -# define machine_is_legend() (0) -#endif - -#ifdef CONFIG_MACH_SALSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SALSA -# endif -# define machine_is_salsa() (machine_arch_type == MACH_TYPE_SALSA) -#else -# define machine_is_salsa() (0) -#endif - -#ifdef CONFIG_MACH_LOUNGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOUNGE -# endif -# define machine_is_lounge() (machine_arch_type == MACH_TYPE_LOUNGE) -#else -# define machine_is_lounge() (0) -#endif - -#ifdef CONFIG_MACH_VISION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VISION -# endif -# define machine_is_vision() (machine_arch_type == MACH_TYPE_VISION) -#else -# define machine_is_vision() (0) -#endif - -#ifdef CONFIG_MACH_VMB20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VMB20 -# endif -# define machine_is_vmb20() (machine_arch_type == MACH_TYPE_VMB20) -#else -# define machine_is_vmb20() (0) -#endif - -#ifdef CONFIG_MACH_HY2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HY2410 -# endif -# define machine_is_hy2410() (machine_arch_type == MACH_TYPE_HY2410) -#else -# define machine_is_hy2410() (0) -#endif - -#ifdef CONFIG_MACH_HY9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HY9315 -# endif -# define machine_is_hy9315() (machine_arch_type == MACH_TYPE_HY9315) -#else -# define machine_is_hy9315() (0) -#endif - -#ifdef CONFIG_MACH_BULLWINKLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BULLWINKLE -# endif -# define machine_is_bullwinkle() (machine_arch_type == MACH_TYPE_BULLWINKLE) -#else -# define machine_is_bullwinkle() (0) -#endif - -#ifdef CONFIG_MACH_ARM_ULTIMATOR2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM_ULTIMATOR2 -# endif -# define machine_is_arm_ultimator2() (machine_arch_type == MACH_TYPE_ARM_ULTIMATOR2) -#else -# define machine_is_arm_ultimator2() (0) -#endif - -#ifdef CONFIG_MACH_VS_V210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VS_V210 -# endif -# define machine_is_vs_v210() (machine_arch_type == MACH_TYPE_VS_V210) -#else -# define machine_is_vs_v210() (0) -#endif - -#ifdef CONFIG_MACH_VS_V212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VS_V212 -# endif -# define machine_is_vs_v212() (machine_arch_type == MACH_TYPE_VS_V212) -#else -# define machine_is_vs_v212() (0) -#endif - -#ifdef CONFIG_MACH_HMT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMT -# endif -# define machine_is_hmt() (machine_arch_type == MACH_TYPE_HMT) -#else -# define machine_is_hmt() (0) -#endif - -#ifdef CONFIG_MACH_SUEN3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUEN3 -# endif -# define machine_is_suen3() (machine_arch_type == MACH_TYPE_SUEN3) -#else -# define machine_is_suen3() (0) -#endif - -#ifdef CONFIG_MACH_VESPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VESPER -# endif -# define machine_is_vesper() (machine_arch_type == MACH_TYPE_VESPER) -#else -# define machine_is_vesper() (0) -#endif - -#ifdef CONFIG_MACH_STR9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STR9 -# endif -# define machine_is_str9() (machine_arch_type == MACH_TYPE_STR9) -#else -# define machine_is_str9() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_WL_FF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_WL_FF -# endif -# define machine_is_omap3_wl_ff() (machine_arch_type == MACH_TYPE_OMAP3_WL_FF) -#else -# define machine_is_omap3_wl_ff() (0) -#endif - -#ifdef CONFIG_MACH_SIMCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMCOM -# endif -# define machine_is_simcom() (machine_arch_type == MACH_TYPE_SIMCOM) -#else -# define machine_is_simcom() (0) -#endif - -#ifdef CONFIG_MACH_MCWEBIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCWEBIO -# endif -# define machine_is_mcwebio() (machine_arch_type == MACH_TYPE_MCWEBIO) -#else -# define machine_is_mcwebio() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_PHRAZER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_PHRAZER -# endif -# define machine_is_omap3_phrazer() (machine_arch_type == MACH_TYPE_OMAP3_PHRAZER) -#else -# define machine_is_omap3_phrazer() (0) -#endif - -#ifdef CONFIG_MACH_DARWIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DARWIN -# endif -# define machine_is_darwin() (machine_arch_type == MACH_TYPE_DARWIN) -#else -# define machine_is_darwin() (0) -#endif - -#ifdef CONFIG_MACH_ORATISCOMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISCOMU -# endif -# define machine_is_oratiscomu() (machine_arch_type == MACH_TYPE_ORATISCOMU) -#else -# define machine_is_oratiscomu() (0) -#endif - -#ifdef CONFIG_MACH_RTSBC20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RTSBC20 -# endif -# define machine_is_rtsbc20() (machine_arch_type == MACH_TYPE_RTSBC20) -#else -# define machine_is_rtsbc20() (0) -#endif - -#ifdef CONFIG_MACH_I780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I780 -# endif -# define machine_is_sgh_i780() (machine_arch_type == MACH_TYPE_I780) -#else -# define machine_is_sgh_i780() (0) -#endif - -#ifdef CONFIG_MACH_GEMINI324 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMINI324 -# endif -# define machine_is_gemini324() (machine_arch_type == MACH_TYPE_GEMINI324) -#else -# define machine_is_gemini324() (0) -#endif - -#ifdef CONFIG_MACH_ORATISLAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISLAN -# endif -# define machine_is_oratislan() (machine_arch_type == MACH_TYPE_ORATISLAN) -#else -# define machine_is_oratislan() (0) -#endif - -#ifdef CONFIG_MACH_ORATISALOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISALOG -# endif -# define machine_is_oratisalog() (machine_arch_type == MACH_TYPE_ORATISALOG) -#else -# define machine_is_oratisalog() (0) -#endif - -#ifdef CONFIG_MACH_ORATISMADI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISMADI -# endif -# define machine_is_oratismadi() (machine_arch_type == MACH_TYPE_ORATISMADI) -#else -# define machine_is_oratismadi() (0) -#endif - -#ifdef CONFIG_MACH_ORATISOT16 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISOT16 -# endif -# define machine_is_oratisot16() (machine_arch_type == MACH_TYPE_ORATISOT16) -#else -# define machine_is_oratisot16() (0) -#endif - -#ifdef CONFIG_MACH_ORATISDESK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISDESK -# endif -# define machine_is_oratisdesk() (machine_arch_type == MACH_TYPE_ORATISDESK) -#else -# define machine_is_oratisdesk() (0) -#endif - -#ifdef CONFIG_MACH_VEXPRESS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VEXPRESS -# endif -# define machine_is_vexpress() (machine_arch_type == MACH_TYPE_VEXPRESS) -#else -# define machine_is_vexpress() (0) -#endif - -#ifdef CONFIG_MACH_SINTEXO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SINTEXO -# endif -# define machine_is_sintexo() (machine_arch_type == MACH_TYPE_SINTEXO) -#else -# define machine_is_sintexo() (0) -#endif - -#ifdef CONFIG_MACH_CM3389 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM3389 -# endif -# define machine_is_cm3389() (machine_arch_type == MACH_TYPE_CM3389) -#else -# define machine_is_cm3389() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_CIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_CIO -# endif -# define machine_is_omap3_cio() (machine_arch_type == MACH_TYPE_OMAP3_CIO) -#else -# define machine_is_omap3_cio() (0) -#endif - -#ifdef CONFIG_MACH_SGH_I900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGH_I900 -# endif -# define machine_is_sgh_i900() (machine_arch_type == MACH_TYPE_SGH_I900) -#else -# define machine_is_sgh_i900() (0) -#endif - -#ifdef CONFIG_MACH_BST100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BST100 -# endif -# define machine_is_bst100() (machine_arch_type == MACH_TYPE_BST100) -#else -# define machine_is_bst100() (0) -#endif - -#ifdef CONFIG_MACH_PASSION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PASSION -# endif -# define machine_is_passion() (machine_arch_type == MACH_TYPE_PASSION) -#else -# define machine_is_passion() (0) -#endif - -#ifdef CONFIG_MACH_INDESIGN_AT91SAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INDESIGN_AT91SAM -# endif -# define machine_is_indesign_at91sam() (machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM) -#else -# define machine_is_indesign_at91sam() (0) -#endif - -#ifdef CONFIG_MACH_C4_BADGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C4_BADGER -# endif -# define machine_is_c4_badger() (machine_arch_type == MACH_TYPE_C4_BADGER) -#else -# define machine_is_c4_badger() (0) -#endif - -#ifdef CONFIG_MACH_C4_VIPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C4_VIPER -# endif -# define machine_is_c4_viper() (machine_arch_type == MACH_TYPE_C4_VIPER) -#else -# define machine_is_c4_viper() (0) -#endif - -#ifdef CONFIG_MACH_D2NET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D2NET -# endif -# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET) -#else -# define machine_is_d2net() (0) -#endif - -#ifdef CONFIG_MACH_BIGDISK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIGDISK -# endif -# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK) -#else -# define machine_is_bigdisk() (0) -#endif - -#ifdef CONFIG_MACH_NOTALVISION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOTALVISION -# endif -# define machine_is_notalvision() (machine_arch_type == MACH_TYPE_NOTALVISION) -#else -# define machine_is_notalvision() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_KBOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_KBOC -# endif -# define machine_is_omap3_kboc() (machine_arch_type == MACH_TYPE_OMAP3_KBOC) -#else -# define machine_is_omap3_kboc() (0) -#endif - -#ifdef CONFIG_MACH_CYCLONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYCLONE -# endif -# define machine_is_cyclone() (machine_arch_type == MACH_TYPE_CYCLONE) -#else -# define machine_is_cyclone() (0) -#endif - -#ifdef CONFIG_MACH_NINJA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NINJA -# endif -# define machine_is_ninja() (machine_arch_type == MACH_TYPE_NINJA) -#else -# define machine_is_ninja() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC -# endif -# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC) -#else -# define machine_is_at91sam9g20ek_2mmc() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING -# endif -# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING) -#else -# define machine_is_bcmring() (0) -#endif - -#ifdef CONFIG_MACH_RESOL_DL2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RESOL_DL2 -# endif -# define machine_is_resol_dl2() (machine_arch_type == MACH_TYPE_RESOL_DL2) -#else -# define machine_is_resol_dl2() (0) -#endif - -#ifdef CONFIG_MACH_IFOSW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IFOSW -# endif -# define machine_is_ifosw() (machine_arch_type == MACH_TYPE_IFOSW) -#else -# define machine_is_ifosw() (0) -#endif - -#ifdef CONFIG_MACH_HTCRHODIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRHODIUM -# endif -# define machine_is_htcrhodium() (machine_arch_type == MACH_TYPE_HTCRHODIUM) -#else -# define machine_is_htcrhodium() (0) -#endif - -#ifdef CONFIG_MACH_HTCTOPAZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCTOPAZ -# endif -# define machine_is_htctopaz() (machine_arch_type == MACH_TYPE_HTCTOPAZ) -#else -# define machine_is_htctopaz() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX504 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX504 -# endif -# define machine_is_matrix504() (machine_arch_type == MACH_TYPE_MATRIX504) -#else -# define machine_is_matrix504() (0) -#endif - -#ifdef CONFIG_MACH_MRFSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MRFSA -# endif -# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA) -#else -# define machine_is_mrfsa() (0) -#endif - -#ifdef CONFIG_MACH_SC_P270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC_P270 -# endif -# define machine_is_sc_p270() (machine_arch_type == MACH_TYPE_SC_P270) -#else -# define machine_is_sc_p270() (0) -#endif - -#ifdef CONFIG_MACH_ATLAS5_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLAS5_EVB -# endif -# define machine_is_atlas5_evb() (machine_arch_type == MACH_TYPE_ATLAS5_EVB) -#else -# define machine_is_atlas5_evb() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_LOBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_LOBOX -# endif -# define machine_is_pelco_lobox() (machine_arch_type == MACH_TYPE_PELCO_LOBOX) -#else -# define machine_is_pelco_lobox() (0) -#endif - -#ifdef CONFIG_MACH_DILAX_PCU200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DILAX_PCU200 -# endif -# define machine_is_dilax_pcu200() (machine_arch_type == MACH_TYPE_DILAX_PCU200) -#else -# define machine_is_dilax_pcu200() (0) -#endif - -#ifdef CONFIG_MACH_LEONARDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEONARDO -# endif -# define machine_is_leonardo() (machine_arch_type == MACH_TYPE_LEONARDO) -#else -# define machine_is_leonardo() (0) -#endif - -#ifdef CONFIG_MACH_ZORAN_APPROACH7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZORAN_APPROACH7 -# endif -# define machine_is_zoran_approach7() (machine_arch_type == MACH_TYPE_ZORAN_APPROACH7) -#else -# define machine_is_zoran_approach7() (0) -#endif - -#ifdef CONFIG_MACH_DP6XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP6XX -# endif -# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX) -#else -# define machine_is_dp6xx() (0) -#endif - -#ifdef CONFIG_MACH_BCM2153_VESPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM2153_VESPER -# endif -# define machine_is_bcm2153_vesper() (machine_arch_type == MACH_TYPE_BCM2153_VESPER) -#else -# define machine_is_bcm2153_vesper() (0) -#endif - -#ifdef CONFIG_MACH_MAHIMAHI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAHIMAHI -# endif -# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI) -#else -# define machine_is_mahimahi() (0) -#endif - -#ifdef CONFIG_MACH_CLICKC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLICKC -# endif -# define machine_is_clickc() (machine_arch_type == MACH_TYPE_CLICKC) -#else -# define machine_is_clickc() (0) -#endif - -#ifdef CONFIG_MACH_ZB_GATEWAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZB_GATEWAY -# endif -# define machine_is_zb_gateway() (machine_arch_type == MACH_TYPE_ZB_GATEWAY) -#else -# define machine_is_zb_gateway() (0) -#endif - -#ifdef CONFIG_MACH_TAZCARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAZCARD -# endif -# define machine_is_tazcard() (machine_arch_type == MACH_TYPE_TAZCARD) -#else -# define machine_is_tazcard() (0) -#endif - -#ifdef CONFIG_MACH_TAZDEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAZDEV -# endif -# define machine_is_tazdev() (machine_arch_type == MACH_TYPE_TAZDEV) -#else -# define machine_is_tazdev() (0) -#endif - -#ifdef CONFIG_MACH_ANNAX_CB_ARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANNAX_CB_ARM -# endif -# define machine_is_annax_cb_arm() (machine_arch_type == MACH_TYPE_ANNAX_CB_ARM) -#else -# define machine_is_annax_cb_arm() (0) -#endif - -#ifdef CONFIG_MACH_ANNAX_DM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANNAX_DM3 -# endif -# define machine_is_annax_dm3() (machine_arch_type == MACH_TYPE_ANNAX_DM3) -#else -# define machine_is_annax_dm3() (0) -#endif - -#ifdef CONFIG_MACH_CEREBRIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEREBRIC -# endif -# define machine_is_cerebric() (machine_arch_type == MACH_TYPE_CEREBRIC) -#else -# define machine_is_cerebric() (0) -#endif - -#ifdef CONFIG_MACH_ORCA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORCA -# endif -# define machine_is_orca() (machine_arch_type == MACH_TYPE_ORCA) -#else -# define machine_is_orca() (0) -#endif - -#ifdef CONFIG_MACH_PC9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC9260 -# endif -# define machine_is_pc9260() (machine_arch_type == MACH_TYPE_PC9260) -#else -# define machine_is_pc9260() (0) -#endif - -#ifdef CONFIG_MACH_EMS285A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMS285A -# endif -# define machine_is_ems285a() (machine_arch_type == MACH_TYPE_EMS285A) -#else -# define machine_is_ems285a() (0) -#endif - -#ifdef CONFIG_MACH_GEC2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEC2410 -# endif -# define machine_is_gec2410() (machine_arch_type == MACH_TYPE_GEC2410) -#else -# define machine_is_gec2410() (0) -#endif - -#ifdef CONFIG_MACH_GEC2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEC2440 -# endif -# define machine_is_gec2440() (machine_arch_type == MACH_TYPE_GEC2440) -#else -# define machine_is_gec2440() (0) -#endif - -#ifdef CONFIG_MACH_ARCH_MW903 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCH_MW903 -# endif -# define machine_is_mw903() (machine_arch_type == MACH_TYPE_ARCH_MW903) -#else -# define machine_is_mw903() (0) -#endif - -#ifdef CONFIG_MACH_MW2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MW2440 -# endif -# define machine_is_mw2440() (machine_arch_type == MACH_TYPE_MW2440) -#else -# define machine_is_mw2440() (0) -#endif - -#ifdef CONFIG_MACH_ECAC2378 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECAC2378 -# endif -# define machine_is_ecac2378() (machine_arch_type == MACH_TYPE_ECAC2378) -#else -# define machine_is_ecac2378() (0) -#endif - -#ifdef CONFIG_MACH_TAZKIOSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAZKIOSK -# endif -# define machine_is_tazkiosk() (machine_arch_type == MACH_TYPE_TAZKIOSK) -#else -# define machine_is_tazkiosk() (0) -#endif - -#ifdef CONFIG_MACH_WHITERABBIT_MCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WHITERABBIT_MCH -# endif -# define machine_is_whiterabbit_mch() (machine_arch_type == MACH_TYPE_WHITERABBIT_MCH) -#else -# define machine_is_whiterabbit_mch() (0) -#endif - -#ifdef CONFIG_MACH_SBOX9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBOX9263 -# endif -# define machine_is_sbox9263() (machine_arch_type == MACH_TYPE_SBOX9263) -#else -# define machine_is_sbox9263() (0) -#endif - -#ifdef CONFIG_MACH_OREO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OREO -# endif -# define machine_is_oreo() (machine_arch_type == MACH_TYPE_OREO) -#else -# define machine_is_oreo() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6442 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6442 -# endif -# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442) -#else -# define machine_is_smdk6442() (0) -#endif - -#ifdef CONFIG_MACH_OPENRD_BASE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENRD_BASE -# endif -# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) -#else -# define machine_is_openrd_base() (0) -#endif - -#ifdef CONFIG_MACH_INCREDIBLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INCREDIBLE -# endif -# define machine_is_incredible() (machine_arch_type == MACH_TYPE_INCREDIBLE) -#else -# define machine_is_incredible() (0) -#endif - -#ifdef CONFIG_MACH_INCREDIBLEC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INCREDIBLEC -# endif -# define machine_is_incrediblec() (machine_arch_type == MACH_TYPE_INCREDIBLEC) -#else -# define machine_is_incrediblec() (0) -#endif - -#ifdef CONFIG_MACH_HEROCT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HEROCT -# endif -# define machine_is_heroct() (machine_arch_type == MACH_TYPE_HEROCT) -#else -# define machine_is_heroct() (0) -#endif - -#ifdef CONFIG_MACH_MMNET1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMNET1000 -# endif -# define machine_is_mmnet1000() (machine_arch_type == MACH_TYPE_MMNET1000) -#else -# define machine_is_mmnet1000() (0) -#endif - -#ifdef CONFIG_MACH_DEVKIT8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEVKIT8000 -# endif -# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000) -#else -# define machine_is_devkit8000() (0) -#endif - -#ifdef CONFIG_MACH_DEVKIT9000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEVKIT9000 -# endif -# define machine_is_devkit9000() (machine_arch_type == MACH_TYPE_DEVKIT9000) -#else -# define machine_is_devkit9000() (0) -#endif - -#ifdef CONFIG_MACH_MX31TXTR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31TXTR -# endif -# define machine_is_mx31txtr() (machine_arch_type == MACH_TYPE_MX31TXTR) -#else -# define machine_is_mx31txtr() (0) -#endif - -#ifdef CONFIG_MACH_U380 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U380 -# endif -# define machine_is_u380() (machine_arch_type == MACH_TYPE_U380) -#else -# define machine_is_u380() (0) -#endif - -#ifdef CONFIG_MACH_HUALU_BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUALU_BOARD -# endif -# define machine_is_oamp3_hualu() (machine_arch_type == MACH_TYPE_HUALU_BOARD) -#else -# define machine_is_oamp3_hualu() (0) -#endif - -#ifdef CONFIG_MACH_NPCMX50 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NPCMX50 -# endif -# define machine_is_npcmx50() (machine_arch_type == MACH_TYPE_NPCMX50) -#else -# define machine_is_npcmx50() (0) -#endif - -#ifdef CONFIG_MACH_MX51_LANGE51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_LANGE51 -# endif -# define machine_is_mx51_lange51() (machine_arch_type == MACH_TYPE_MX51_LANGE51) -#else -# define machine_is_mx51_lange51() (0) -#endif - -#ifdef CONFIG_MACH_MX51_LANGE52 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_LANGE52 -# endif -# define machine_is_mx51_lange52() (machine_arch_type == MACH_TYPE_MX51_LANGE52) -#else -# define machine_is_mx51_lange52() (0) -#endif - -#ifdef CONFIG_MACH_RIOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOM -# endif -# define machine_is_riom() (machine_arch_type == MACH_TYPE_RIOM) -#else -# define machine_is_riom() (0) -#endif - -#ifdef CONFIG_MACH_COMCAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMCAS -# endif -# define machine_is_comcas() (machine_arch_type == MACH_TYPE_COMCAS) -#else -# define machine_is_comcas() (0) -#endif - -#ifdef CONFIG_MACH_WSI_MX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WSI_MX27 -# endif -# define machine_is_wsi_mx27() (machine_arch_type == MACH_TYPE_WSI_MX27) -#else -# define machine_is_wsi_mx27() (0) -#endif - -#ifdef CONFIG_MACH_CM_T35 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_T35 -# endif -# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35) -#else -# define machine_is_cm_t35() (0) -#endif - -#ifdef CONFIG_MACH_NET2BIG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET2BIG -# endif -# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG) -#else -# define machine_is_net2big() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_A1600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_A1600 -# endif -# define machine_is_motorola_a1600() (machine_arch_type == MACH_TYPE_MOTOROLA_A1600) -#else -# define machine_is_motorola_a1600() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0020 -# endif -# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020) -#else -# define machine_is_igep0020() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0010 -# endif -# define machine_is_igep0010() (machine_arch_type == MACH_TYPE_IGEP0010) -#else -# define machine_is_igep0010() (0) -#endif - -#ifdef CONFIG_MACH_MV6281GTWGE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV6281GTWGE2 -# endif -# define machine_is_mv6281gtwge2() (machine_arch_type == MACH_TYPE_MV6281GTWGE2) -#else -# define machine_is_mv6281gtwge2() (0) -#endif - -#ifdef CONFIG_MACH_SCAT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCAT100 -# endif -# define machine_is_scat100() (machine_arch_type == MACH_TYPE_SCAT100) -#else -# define machine_is_scat100() (0) -#endif - -#ifdef CONFIG_MACH_SANMINA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANMINA -# endif -# define machine_is_sanmina() (machine_arch_type == MACH_TYPE_SANMINA) -#else -# define machine_is_sanmina() (0) -#endif - -#ifdef CONFIG_MACH_MOMENTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOMENTO -# endif -# define machine_is_momento() (machine_arch_type == MACH_TYPE_MOMENTO) -#else -# define machine_is_momento() (0) -#endif - -#ifdef CONFIG_MACH_NUC9XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC9XX -# endif -# define machine_is_nuc9xx() (machine_arch_type == MACH_TYPE_NUC9XX) -#else -# define machine_is_nuc9xx() (0) -#endif - -#ifdef CONFIG_MACH_NUC910EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC910EVB -# endif -# define machine_is_nuc910evb() (machine_arch_type == MACH_TYPE_NUC910EVB) -#else -# define machine_is_nuc910evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC920EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC920EVB -# endif -# define machine_is_nuc920evb() (machine_arch_type == MACH_TYPE_NUC920EVB) -#else -# define machine_is_nuc920evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC950EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC950EVB -# endif -# define machine_is_nuc950evb() (machine_arch_type == MACH_TYPE_NUC950EVB) -#else -# define machine_is_nuc950evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC945EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC945EVB -# endif -# define machine_is_nuc945evb() (machine_arch_type == MACH_TYPE_NUC945EVB) -#else -# define machine_is_nuc945evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC960EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC960EVB -# endif -# define machine_is_nuc960evb() (machine_arch_type == MACH_TYPE_NUC960EVB) -#else -# define machine_is_nuc960evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC932EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC932EVB -# endif -# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB) -#else -# define machine_is_nuc932evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC900 -# endif -# define machine_is_nuc900() (machine_arch_type == MACH_TYPE_NUC900) -#else -# define machine_is_nuc900() (0) -#endif - -#ifdef CONFIG_MACH_SD1SOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SD1SOC -# endif -# define machine_is_sd1soc() (machine_arch_type == MACH_TYPE_SD1SOC) -#else -# define machine_is_sd1soc() (0) -#endif - -#ifdef CONFIG_MACH_LN2440BC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LN2440BC -# endif -# define machine_is_ln2440bc() (machine_arch_type == MACH_TYPE_LN2440BC) -#else -# define machine_is_ln2440bc() (0) -#endif - -#ifdef CONFIG_MACH_RSBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSBC -# endif -# define machine_is_rsbc() (machine_arch_type == MACH_TYPE_RSBC) -#else -# define machine_is_rsbc() (0) -#endif - -#ifdef CONFIG_MACH_OPENRD_CLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENRD_CLIENT -# endif -# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT) -#else -# define machine_is_openrd_client() (0) -#endif - -#ifdef CONFIG_MACH_HPIPAQ11X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPIPAQ11X -# endif -# define machine_is_hpipaq11x() (machine_arch_type == MACH_TYPE_HPIPAQ11X) -#else -# define machine_is_hpipaq11x() (0) -#endif - -#ifdef CONFIG_MACH_WAYLAND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WAYLAND -# endif -# define machine_is_wayland() (machine_arch_type == MACH_TYPE_WAYLAND) -#else -# define machine_is_wayland() (0) -#endif - -#ifdef CONFIG_MACH_ACNBSX102 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACNBSX102 -# endif -# define machine_is_acnbsx102() (machine_arch_type == MACH_TYPE_ACNBSX102) -#else -# define machine_is_acnbsx102() (0) -#endif - -#ifdef CONFIG_MACH_HWAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HWAT91 -# endif -# define machine_is_hwat91() (machine_arch_type == MACH_TYPE_HWAT91) -#else -# define machine_is_hwat91() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263CS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263CS -# endif -# define machine_is_at91sam9263cs() (machine_arch_type == MACH_TYPE_AT91SAM9263CS) -#else -# define machine_is_at91sam9263cs() (0) -#endif - -#ifdef CONFIG_MACH_CSB732 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB732 -# endif -# define machine_is_csb732() (machine_arch_type == MACH_TYPE_CSB732) -#else -# define machine_is_csb732() (0) -#endif - -#ifdef CONFIG_MACH_U8500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U8500 -# endif -# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) -#else -# define machine_is_u8500() (0) -#endif - -#ifdef CONFIG_MACH_HUQIU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUQIU -# endif -# define machine_is_huqiu() (machine_arch_type == MACH_TYPE_HUQIU) -#else -# define machine_is_huqiu() (0) -#endif - -#ifdef CONFIG_MACH_MX51_KUNLUN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_KUNLUN -# endif -# define machine_is_mx51_kunlun() (machine_arch_type == MACH_TYPE_MX51_KUNLUN) -#else -# define machine_is_mx51_kunlun() (0) -#endif - -#ifdef CONFIG_MACH_PMT1G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PMT1G -# endif -# define machine_is_pmt1g() (machine_arch_type == MACH_TYPE_PMT1G) -#else -# define machine_is_pmt1g() (0) -#endif - -#ifdef CONFIG_MACH_HTCELF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCELF -# endif -# define machine_is_htcelf() (machine_arch_type == MACH_TYPE_HTCELF) -#else -# define machine_is_htcelf() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO420 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO420 -# endif -# define machine_is_armadillo420() (machine_arch_type == MACH_TYPE_ARMADILLO420) -#else -# define machine_is_armadillo420() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO440 -# endif -# define machine_is_armadillo440() (machine_arch_type == MACH_TYPE_ARMADILLO440) -#else -# define machine_is_armadillo440() (0) -#endif - -#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U_CHIP_DUAL_ARM -# endif -# define machine_is_u_chip_dual_arm() (machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM) -#else -# define machine_is_u_chip_dual_arm() (0) -#endif - -#ifdef CONFIG_MACH_CSR_BDB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSR_BDB3 -# endif -# define machine_is_csr_bdb3() (machine_arch_type == MACH_TYPE_CSR_BDB3) -#else -# define machine_is_csr_bdb3() (0) -#endif - -#ifdef CONFIG_MACH_DOLBY_CAT1018 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOLBY_CAT1018 -# endif -# define machine_is_dolby_cat1018() (machine_arch_type == MACH_TYPE_DOLBY_CAT1018) -#else -# define machine_is_dolby_cat1018() (0) -#endif - -#ifdef CONFIG_MACH_HY9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HY9307 -# endif -# define machine_is_hy9307() (machine_arch_type == MACH_TYPE_HY9307) -#else -# define machine_is_hy9307() (0) -#endif - -#ifdef CONFIG_MACH_A_ES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A_ES -# endif -# define machine_is_aspire_easystore() (machine_arch_type == MACH_TYPE_A_ES) -#else -# define machine_is_aspire_easystore() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_IRIF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_IRIF -# endif -# define machine_is_davinci_irif() (machine_arch_type == MACH_TYPE_DAVINCI_IRIF) -#else -# define machine_is_davinci_irif() (0) -#endif - -#ifdef CONFIG_MACH_AGAMA9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AGAMA9263 -# endif -# define machine_is_agama9263() (machine_arch_type == MACH_TYPE_AGAMA9263) -#else -# define machine_is_agama9263() (0) -#endif - -#ifdef CONFIG_MACH_MARVELL_JASPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVELL_JASPER -# endif -# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER) -#else -# define machine_is_marvell_jasper() (0) -#endif - -#ifdef CONFIG_MACH_FLINT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLINT -# endif -# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT) -#else -# define machine_is_flint() (0) -#endif - -#ifdef CONFIG_MACH_TAVOREVB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAVOREVB3 -# endif -# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3) -#else -# define machine_is_tavorevb3() (0) -#endif - -#ifdef CONFIG_MACH_SCH_M490 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCH_M490 -# endif -# define machine_is_sch_m490() (machine_arch_type == MACH_TYPE_SCH_M490) -#else -# define machine_is_sch_m490() (0) -#endif - -#ifdef CONFIG_MACH_RBL01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RBL01 -# endif -# define machine_is_rbl01() (machine_arch_type == MACH_TYPE_RBL01) -#else -# define machine_is_rbl01() (0) -#endif - -#ifdef CONFIG_MACH_OMNIFI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMNIFI -# endif -# define machine_is_omnifi() (machine_arch_type == MACH_TYPE_OMNIFI) -#else -# define machine_is_omnifi() (0) -#endif - -#ifdef CONFIG_MACH_OTAVALO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTAVALO -# endif -# define machine_is_otavalo() (machine_arch_type == MACH_TYPE_OTAVALO) -#else -# define machine_is_otavalo() (0) -#endif - -#ifdef CONFIG_MACH_SIENNA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIENNA -# endif -# define machine_is_siena() (machine_arch_type == MACH_TYPE_SIENNA) -#else -# define machine_is_siena() (0) -#endif - -#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_EXCALIBUR_S620 -# endif -# define machine_is_htc_excalibur_s620() (machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620) -#else -# define machine_is_htc_excalibur_s620() (0) -#endif - -#ifdef CONFIG_MACH_HTC_OPAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_OPAL -# endif -# define machine_is_htc_opal() (machine_arch_type == MACH_TYPE_HTC_OPAL) -#else -# define machine_is_htc_opal() (0) -#endif - -#ifdef CONFIG_MACH_TOUCHBOOK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOUCHBOOK -# endif -# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK) -#else -# define machine_is_touchbook() (0) -#endif - -#ifdef CONFIG_MACH_LATTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LATTE -# endif -# define machine_is_latte() (machine_arch_type == MACH_TYPE_LATTE) -#else -# define machine_is_latte() (0) -#endif - -#ifdef CONFIG_MACH_XA200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XA200 -# endif -# define machine_is_xa200() (machine_arch_type == MACH_TYPE_XA200) -#else -# define machine_is_xa200() (0) -#endif - -#ifdef CONFIG_MACH_NIMROD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMROD -# endif -# define machine_is_nimrod() (machine_arch_type == MACH_TYPE_NIMROD) -#else -# define machine_is_nimrod() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215_3G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215_3G -# endif -# define machine_is_cc9p9215_3g() (machine_arch_type == MACH_TYPE_CC9P9215_3G) -#else -# define machine_is_cc9p9215_3g() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215_3GJS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215_3GJS -# endif -# define machine_is_cc9p9215_3gjs() (machine_arch_type == MACH_TYPE_CC9P9215_3GJS) -#else -# define machine_is_cc9p9215_3gjs() (0) -#endif - -#ifdef CONFIG_MACH_TK71 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TK71 -# endif -# define machine_is_tk71() (machine_arch_type == MACH_TYPE_TK71) -#else -# define machine_is_tk71() (0) -#endif - -#ifdef CONFIG_MACH_COMHAM3525 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMHAM3525 -# endif -# define machine_is_comham3525() (machine_arch_type == MACH_TYPE_COMHAM3525) -#else -# define machine_is_comham3525() (0) -#endif - -#ifdef CONFIG_MACH_MX31EREBUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31EREBUS -# endif -# define machine_is_mx31erebus() (machine_arch_type == MACH_TYPE_MX31EREBUS) -#else -# define machine_is_mx31erebus() (0) -#endif - -#ifdef CONFIG_MACH_MCARDMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCARDMX27 -# endif -# define machine_is_mcardmx27() (machine_arch_type == MACH_TYPE_MCARDMX27) -#else -# define machine_is_mcardmx27() (0) -#endif - -#ifdef CONFIG_MACH_PARADISE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PARADISE -# endif -# define machine_is_paradise() (machine_arch_type == MACH_TYPE_PARADISE) -#else -# define machine_is_paradise() (0) -#endif - -#ifdef CONFIG_MACH_TIDE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIDE -# endif -# define machine_is_tide() (machine_arch_type == MACH_TYPE_TIDE) -#else -# define machine_is_tide() (0) -#endif - -#ifdef CONFIG_MACH_WZL2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL2440 -# endif -# define machine_is_wzl2440() (machine_arch_type == MACH_TYPE_WZL2440) -#else -# define machine_is_wzl2440() (0) -#endif - -#ifdef CONFIG_MACH_SDRDEMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SDRDEMO -# endif -# define machine_is_sdrdemo() (machine_arch_type == MACH_TYPE_SDRDEMO) -#else -# define machine_is_sdrdemo() (0) -#endif - -#ifdef CONFIG_MACH_ETHERCAN2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETHERCAN2 -# endif -# define machine_is_ethercan2() (machine_arch_type == MACH_TYPE_ETHERCAN2) -#else -# define machine_is_ethercan2() (0) -#endif - -#ifdef CONFIG_MACH_ECMIMG20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECMIMG20 -# endif -# define machine_is_ecmimg20() (machine_arch_type == MACH_TYPE_ECMIMG20) -#else -# define machine_is_ecmimg20() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_DRAGON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_DRAGON -# endif -# define machine_is_omap_dragon() (machine_arch_type == MACH_TYPE_OMAP_DRAGON) -#else -# define machine_is_omap_dragon() (0) -#endif - -#ifdef CONFIG_MACH_HALO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HALO -# endif -# define machine_is_halo() (machine_arch_type == MACH_TYPE_HALO) -#else -# define machine_is_halo() (0) -#endif - -#ifdef CONFIG_MACH_HUANGSHAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUANGSHAN -# endif -# define machine_is_huangshan() (machine_arch_type == MACH_TYPE_HUANGSHAN) -#else -# define machine_is_huangshan() (0) -#endif - -#ifdef CONFIG_MACH_VL_MA2SC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VL_MA2SC -# endif -# define machine_is_vl_ma2sc() (machine_arch_type == MACH_TYPE_VL_MA2SC) -#else -# define machine_is_vl_ma2sc() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_RC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_RC -# endif -# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC) -#else -# define machine_is_raumfeld_rc() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR -# endif -# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR) -#else -# define machine_is_raumfeld_connector() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_SPEAKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER -# endif -# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER) -#else -# define machine_is_raumfeld_speaker() (0) -#endif - -#ifdef CONFIG_MACH_MULTIBUS_MASTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIBUS_MASTER -# endif -# define machine_is_multibus_master() (machine_arch_type == MACH_TYPE_MULTIBUS_MASTER) -#else -# define machine_is_multibus_master() (0) -#endif - -#ifdef CONFIG_MACH_MULTIBUS_PBK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIBUS_PBK -# endif -# define machine_is_multibus_pbk() (machine_arch_type == MACH_TYPE_MULTIBUS_PBK) -#else -# define machine_is_multibus_pbk() (0) -#endif - -#ifdef CONFIG_MACH_TNETV107X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNETV107X -# endif -# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X) -#else -# define machine_is_tnetv107x() (0) -#endif - -#ifdef CONFIG_MACH_SNAKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAKE -# endif -# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE) -#else -# define machine_is_snake() (0) -#endif - -#ifdef CONFIG_MACH_CWMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMX27 -# endif -# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27) -#else -# define machine_is_cwmx27() (0) -#endif - -#ifdef CONFIG_MACH_SCH_M480 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCH_M480 -# endif -# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480) -#else -# define machine_is_sch_m480() (0) -#endif - -#ifdef CONFIG_MACH_PLATYPUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLATYPUS -# endif -# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS) -#else -# define machine_is_platypus() (0) -#endif - -#ifdef CONFIG_MACH_PSS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSS2 -# endif -# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2) -#else -# define machine_is_pss2() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_APM150 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_APM150 -# endif -# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150) -#else -# define machine_is_davinci_apm150() (0) -#endif - -#ifdef CONFIG_MACH_STR9100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STR9100 -# endif -# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100) -#else -# define machine_is_str9100() (0) -#endif - -#ifdef CONFIG_MACH_NET5BIG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET5BIG -# endif -# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG) -#else -# define machine_is_net5big() (0) -#endif - -#ifdef CONFIG_MACH_SEABED9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEABED9263 -# endif -# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263) -#else -# define machine_is_seabed9263() (0) -#endif - -#ifdef CONFIG_MACH_MX51_M2ID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_M2ID -# endif -# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID) -#else -# define machine_is_mx51_m2id() (0) -#endif - -#ifdef CONFIG_MACH_OCTVOCPLUS_EB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB -# endif -# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB) -#else -# define machine_is_octvocplus_eb() (0) -#endif - -#ifdef CONFIG_MACH_KLK_FIREFOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KLK_FIREFOX -# endif -# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX) -#else -# define machine_is_klk_firefox() (0) -#endif - -#ifdef CONFIG_MACH_KLK_WIRMA_MODULE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE -# endif -# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE) -#else -# define machine_is_klk_wirma_module() (0) -#endif - -#ifdef CONFIG_MACH_KLK_WIRMA_MMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI -# endif -# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI) -#else -# define machine_is_klk_wirma_mmi() (0) -#endif - -#ifdef CONFIG_MACH_SUPERSONIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUPERSONIC -# endif -# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC) -#else -# define machine_is_supersonic() (0) -#endif - -#ifdef CONFIG_MACH_LIBERTY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIBERTY -# endif -# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY) -#else -# define machine_is_liberty() (0) -#endif - -#ifdef CONFIG_MACH_MH355 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MH355 -# endif -# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355) -#else -# define machine_is_mh355() (0) -#endif - -#ifdef CONFIG_MACH_PC7802 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC7802 -# endif -# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802) -#else -# define machine_is_pc7802() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SGC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SGC -# endif -# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC) -#else -# define machine_is_gnet_sgc() (0) -#endif - -#ifdef CONFIG_MACH_EINSTEIN15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EINSTEIN15 -# endif -# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15) -#else -# define machine_is_einstein15() (0) -#endif - -#ifdef CONFIG_MACH_CMPD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMPD -# endif -# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD) -#else -# define machine_is_cmpd() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_HASE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_HASE1 -# endif -# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1) -#else -# define machine_is_davinci_hase1() (0) -#endif - -#ifdef CONFIG_MACH_LGEINCITEPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LGEINCITEPHONE -# endif -# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE) -#else -# define machine_is_lgeincitephone() (0) -#endif - -#ifdef CONFIG_MACH_EA313X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EA313X -# endif -# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X) -#else -# define machine_is_ea313x() (0) -#endif - -#ifdef CONFIG_MACH_FWBD_39064 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FWBD_39064 -# endif -# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064) -#else -# define machine_is_fwbd_39064() (0) -#endif - -#ifdef CONFIG_MACH_FWBD_390128 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FWBD_390128 -# endif -# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128) -#else -# define machine_is_fwbd_390128() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_MOE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_MOE -# endif -# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE) -#else -# define machine_is_pelco_moe() (0) -#endif - -#ifdef CONFIG_MACH_MINIMIX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINIMIX27 -# endif -# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27) -#else -# define machine_is_minimix27() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_THUNDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_THUNDER -# endif -# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER) -#else -# define machine_is_omap3_thunder() (0) -#endif - -#ifdef CONFIG_MACH_PASSIONC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PASSIONC -# endif -# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC) -#else -# define machine_is_passionc() (0) -#endif - -#ifdef CONFIG_MACH_MX27AMATA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27AMATA -# endif -# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA) -#else -# define machine_is_mx27amata() (0) -#endif - -#ifdef CONFIG_MACH_BGAT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BGAT1 -# endif -# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1) -#else -# define machine_is_bgat1() (0) -#endif - -#ifdef CONFIG_MACH_BUZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUZZ -# endif -# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ) -#else -# define machine_is_buzz() (0) -#endif - -#ifdef CONFIG_MACH_MB9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9G20 -# endif -# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20) -#else -# define machine_is_mb9g20() (0) -#endif - -#ifdef CONFIG_MACH_YUSHAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YUSHAN -# endif -# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN) -#else -# define machine_is_yushan() (0) -#endif - -#ifdef CONFIG_MACH_LIZARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIZARD -# endif -# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD) -#else -# define machine_is_lizard() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3POLYCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3POLYCOM -# endif -# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM) -#else -# define machine_is_omap3polycom() (0) -#endif - -#ifdef CONFIG_MACH_SMDKV210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKV210 -# endif -# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210) -#else -# define machine_is_smdkv210() (0) -#endif - -#ifdef CONFIG_MACH_BRAVO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRAVO -# endif -# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO) -#else -# define machine_is_bravo() (0) -#endif - -#ifdef CONFIG_MACH_SIOGENTOO1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIOGENTOO1 -# endif -# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1) -#else -# define machine_is_siogentoo1() (0) -#endif - -#ifdef CONFIG_MACH_SIOGENTOO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIOGENTOO2 -# endif -# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2) -#else -# define machine_is_siogentoo2() (0) -#endif - -#ifdef CONFIG_MACH_SM3K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SM3K -# endif -# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K) -#else -# define machine_is_sm3k() (0) -#endif - -#ifdef CONFIG_MACH_ACER_TEMPO_F900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900 -# endif -# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900) -#else -# define machine_is_acer_tempo_f900() (0) -#endif - -#ifdef CONFIG_MACH_SST61VC010_DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SST61VC010_DEV -# endif -# define machine_is_sst61vc010_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV) -#else -# define machine_is_sst61vc010_dev() (0) -#endif - -#ifdef CONFIG_MACH_GLITTERTIND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GLITTERTIND -# endif -# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND) -#else -# define machine_is_glittertind() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_ZOOM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_ZOOM3 -# endif -# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3) -#else -# define machine_is_omap_zoom3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_3630SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_3630SDP -# endif -# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP) -#else -# define machine_is_omap_3630sdp() (0) -#endif - -#ifdef CONFIG_MACH_CYBOOK2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBOOK2440 -# endif -# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440) -#else -# define machine_is_cybook2440() (0) -#endif - -#ifdef CONFIG_MACH_TORINO_S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TORINO_S -# endif -# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S) -#else -# define machine_is_torino_s() (0) -#endif - -#ifdef CONFIG_MACH_HAVANA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAVANA -# endif -# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA) -#else -# define machine_is_havana() (0) -#endif - -#ifdef CONFIG_MACH_BEAUMONT_11 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEAUMONT_11 -# endif -# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11) -#else -# define machine_is_beaumont_11() (0) -#endif - -#ifdef CONFIG_MACH_VANGUARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VANGUARD -# endif -# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD) -#else -# define machine_is_vanguard() (0) -#endif - -#ifdef CONFIG_MACH_S5PC110_DRACO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5PC110_DRACO -# endif -# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO) -#else -# define machine_is_s5pc110_draco() (0) -#endif - -#ifdef CONFIG_MACH_CARTESIO_TWO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARTESIO_TWO -# endif -# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO) -#else -# define machine_is_cartesio_two() (0) -#endif - -#ifdef CONFIG_MACH_ASTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASTER -# endif -# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER) -#else -# define machine_is_aster() (0) -#endif - -#ifdef CONFIG_MACH_VOGUESV210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOGUESV210 -# endif -# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210) -#else -# define machine_is_voguesv210() (0) -#endif - -#ifdef CONFIG_MACH_ACM500X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACM500X -# endif -# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X) -#else -# define machine_is_acm500x() (0) -#endif - -#ifdef CONFIG_MACH_KM9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KM9260 -# endif -# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260) -#else -# define machine_is_km9260() (0) -#endif - -#ifdef CONFIG_MACH_NIDEFLEXG1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIDEFLEXG1 -# endif -# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1) -#else -# define machine_is_nideflexg1() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_IO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO -# endif -# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO) -#else -# define machine_is_ctera_plug_io() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQ7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQ7 -# endif -# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7) -#else -# define machine_is_smartq7() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G10EK2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2 -# endif -# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2) -#else -# define machine_is_at91sam9g10ek2() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP527 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP527 -# endif -# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527) -#else -# define machine_is_asusp527() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20MPM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2 -# endif -# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2) -#else -# define machine_is_at91sam9g20mpm2() (0) -#endif - -#ifdef CONFIG_MACH_TOPASA900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOPASA900 -# endif -# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900) -#else -# define machine_is_topasa900() (0) -#endif - -#ifdef CONFIG_MACH_ELECTRUM_100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELECTRUM_100 -# endif -# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100) -#else -# define machine_is_electrum_100() (0) -#endif - -#ifdef CONFIG_MACH_MX51GRB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51GRB -# endif -# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB) -#else -# define machine_is_mx51grb() (0) -#endif - -#ifdef CONFIG_MACH_XEA300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XEA300 -# endif -# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300) -#else -# define machine_is_xea300() (0) -#endif - -#ifdef CONFIG_MACH_HTCSTARTREK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCSTARTREK -# endif -# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK) -#else -# define machine_is_htcstartrek() (0) -#endif - -#ifdef CONFIG_MACH_LIMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIMA -# endif -# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA) -#else -# define machine_is_lima() (0) -#endif - -#ifdef CONFIG_MACH_CSB740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB740 -# endif -# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740) -#else -# define machine_is_csb740() (0) -#endif - -#ifdef CONFIG_MACH_USB_S8815 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_S8815 -# endif -# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815) -#else -# define machine_is_usb_s8815() (0) -#endif - -#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN -# endif -# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN) -#else -# define machine_is_watson_efm_plugin() (0) -#endif - -#ifdef CONFIG_MACH_MILKYWAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MILKYWAY -# endif -# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY) -#else -# define machine_is_milkyway() (0) -#endif - -#ifdef CONFIG_MACH_G4EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G4EVM -# endif -# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM) -#else -# define machine_is_g4evm() (0) -#endif - -#ifdef CONFIG_MACH_PICOMOD6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOMOD6 -# endif -# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6) -#else -# define machine_is_picomod6() (0) -#endif - -#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD -# endif -# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD) -#else -# define machine_is_omapl138_hawkboard() (0) -#endif - -#ifdef CONFIG_MACH_IP6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP6000 -# endif -# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000) -#else -# define machine_is_ip6000() (0) -#endif - -#ifdef CONFIG_MACH_IP6010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP6010 -# endif -# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010) -#else -# define machine_is_ip6010() (0) -#endif - -#ifdef CONFIG_MACH_UTM400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UTM400 -# endif -# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400) -#else -# define machine_is_utm400() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_ZYBEX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX -# endif -# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX) -#else -# define machine_is_omap3_zybex() (0) -#endif - -#ifdef CONFIG_MACH_WIRELESS_SPACE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WIRELESS_SPACE -# endif -# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE) -#else -# define machine_is_wireless_space() (0) -#endif - -#ifdef CONFIG_MACH_SX560 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SX560 -# endif -# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560) -#else -# define machine_is_sx560() (0) -#endif - -#ifdef CONFIG_MACH_TS41X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS41X -# endif -# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X) -#else -# define machine_is_ts41x() (0) -#endif - -#ifdef CONFIG_MACH_ELPHEL10373 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELPHEL10373 -# endif -# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373) -#else -# define machine_is_elphel10373() (0) -#endif - -#ifdef CONFIG_MACH_RHOBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RHOBOT -# endif -# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT) -#else -# define machine_is_rhobot() (0) -#endif - -#ifdef CONFIG_MACH_MX51_REFRESH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_REFRESH -# endif -# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH) -#else -# define machine_is_mx51_refresh() (0) -#endif - -#ifdef CONFIG_MACH_LS9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LS9260 -# endif -# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260) -#else -# define machine_is_ls9260() (0) -#endif - -#ifdef CONFIG_MACH_SHANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHANK -# endif -# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK) -#else -# define machine_is_shank() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_ST1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_ST1 -# endif -# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1) -#else -# define machine_is_qsd8x50_st1() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9M10EKES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES -# endif -# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES) -#else -# define machine_is_at91sam9m10ekes() (0) -#endif - -#ifdef CONFIG_MACH_HIRAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIRAM -# endif -# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM) -#else -# define machine_is_hiram() (0) -#endif - -#ifdef CONFIG_MACH_PHY3250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHY3250 -# endif -# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250) -#else -# define machine_is_phy3250() (0) -#endif - -#ifdef CONFIG_MACH_EA3250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EA3250 -# endif -# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250) -#else -# define machine_is_ea3250() (0) -#endif - -#ifdef CONFIG_MACH_FDI3250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FDI3250 -# endif -# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250) -#else -# define machine_is_fdi3250() (0) -#endif - -#ifdef CONFIG_MACH_WHITESTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WHITESTONE -# endif -# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) -#else -# define machine_is_whitestone() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263NIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263NIT -# endif -# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT) -#else -# define machine_is_at91sam9263nit() (0) -#endif - -#ifdef CONFIG_MACH_CCMX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCMX51 -# endif -# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51) -#else -# define machine_is_ccmx51() (0) -#endif - -#ifdef CONFIG_MACH_CCMX51JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCMX51JS -# endif -# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS) -#else -# define machine_is_ccmx51js() (0) -#endif - -#ifdef CONFIG_MACH_CCWMX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCWMX51 -# endif -# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51) -#else -# define machine_is_ccwmx51() (0) -#endif - -#ifdef CONFIG_MACH_CCWMX51JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCWMX51JS -# endif -# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS) -#else -# define machine_is_ccwmx51js() (0) -#endif - -#ifdef CONFIG_MACH_MINI6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI6410 -# endif -# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410) -#else -# define machine_is_mini6410() (0) -#endif - -#ifdef CONFIG_MACH_TINY6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TINY6410 -# endif -# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410) -#else -# define machine_is_tiny6410() (0) -#endif - -#ifdef CONFIG_MACH_NANO6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANO6410 -# endif -# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410) -#else -# define machine_is_nano6410() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940HFNLDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940HFNLDB -# endif -# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB) -#else -# define machine_is_at572d940hfnldb() (0) -#endif - -#ifdef CONFIG_MACH_HTCLEO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCLEO -# endif -# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO) -#else -# define machine_is_htcleo() (0) -#endif - -#ifdef CONFIG_MACH_AVP13 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVP13 -# endif -# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13) -#else -# define machine_is_avp13() (0) -#endif - -#ifdef CONFIG_MACH_XXSVIDEOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XXSVIDEOD -# endif -# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD) -#else -# define machine_is_xxsvideod() (0) -#endif - -#ifdef CONFIG_MACH_VPNEXT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VPNEXT -# endif -# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT) -#else -# define machine_is_vpnext() (0) -#endif - -#ifdef CONFIG_MACH_SWARCO_ITC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCO_ITC3 -# endif -# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3) -#else -# define machine_is_swarco_itc3() (0) -#endif - -#ifdef CONFIG_MACH_TX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX51 -# endif -# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51) -#else -# define machine_is_tx51() (0) -#endif - -#ifdef CONFIG_MACH_DOLBY_CAT1021 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOLBY_CAT1021 -# endif -# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021) -#else -# define machine_is_dolby_cat1021() (0) -#endif - -#ifdef CONFIG_MACH_MX28EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX28EVK -# endif -# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK) -#else -# define machine_is_mx28evk() (0) -#endif - -#ifdef CONFIG_MACH_PHOENIX260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHOENIX260 -# endif -# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260) -#else -# define machine_is_phoenix260() (0) -#endif - -#ifdef CONFIG_MACH_UVACA_STORK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UVACA_STORK -# endif -# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK) -#else -# define machine_is_uvaca_stork() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQ5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQ5 -# endif -# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5) -#else -# define machine_is_smartq5() (0) -#endif - -#ifdef CONFIG_MACH_ALL3078 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALL3078 -# endif -# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078) -#else -# define machine_is_all3078() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY_DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS -# endif -# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS) -#else -# define machine_is_ctera_2bay_ds() (0) -#endif - -#ifdef CONFIG_MACH_SIOGENTOO3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIOGENTOO3 -# endif -# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3) -#else -# define machine_is_siogentoo3() (0) -#endif - -#ifdef CONFIG_MACH_EPB5000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPB5000 -# endif -# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000) -#else -# define machine_is_epb5000() (0) -#endif - -#ifdef CONFIG_MACH_HY9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HY9263 -# endif -# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263) -#else -# define machine_is_hy9263() (0) -#endif - -#ifdef CONFIG_MACH_ACER_TEMPO_M900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900 -# endif -# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900) -#else -# define machine_is_acer_tempo_m900() (0) -#endif - -#ifdef CONFIG_MACH_ACER_TEMPO_DX900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900 -# endif -# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900) -#else -# define machine_is_acer_tempo_dx650() (0) -#endif - -#ifdef CONFIG_MACH_ACER_TEMPO_X960 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960 -# endif -# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960) -#else -# define machine_is_acer_tempo_x960() (0) -#endif - -#ifdef CONFIG_MACH_ACER_ETEN_V900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_ETEN_V900 -# endif -# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900) -#else -# define machine_is_acer_eten_v900() (0) -#endif - -#ifdef CONFIG_MACH_ACER_ETEN_X900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_ETEN_X900 -# endif -# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900) -#else -# define machine_is_acer_eten_x900() (0) -#endif - -#ifdef CONFIG_MACH_BONNELL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BONNELL -# endif -# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL) -#else -# define machine_is_bonnell() (0) -#endif - -#ifdef CONFIG_MACH_OHT_MX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OHT_MX27 -# endif -# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27) -#else -# define machine_is_oht_mx27() (0) -#endif - -#ifdef CONFIG_MACH_HTCQUARTZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCQUARTZ -# endif -# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ) -#else -# define machine_is_htcquartz() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM -# endif -# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM) -#else -# define machine_is_davinci_dm6467tevm() (0) -#endif - -#ifdef CONFIG_MACH_C3AX03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C3AX03 -# endif -# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03) -#else -# define machine_is_c3ax03() (0) -#endif - -#ifdef CONFIG_MACH_MXT_TD60 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXT_TD60 -# endif -# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60) -#else -# define machine_is_mxt_td60() (0) -#endif - -#ifdef CONFIG_MACH_ESYX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESYX -# endif -# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX) -#else -# define machine_is_esyx() (0) -#endif - -#ifdef CONFIG_MACH_DOVE_DB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOVE_DB2 -# endif -# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB2) -#else -# define machine_is_dove_db2() (0) -#endif - -#ifdef CONFIG_MACH_BULLDOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BULLDOG -# endif -# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG) -#else -# define machine_is_bulldog() (0) -#endif - -#ifdef CONFIG_MACH_DERELL_ME2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DERELL_ME2000 -# endif -# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000) -#else -# define machine_is_derell_me2000() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_BASE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_BASE -# endif -# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE) -#else -# define machine_is_bcmring_base() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_EVM -# endif -# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM) -#else -# define machine_is_bcmring_evm() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ -# endif -# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ) -#else -# define machine_is_bcmring_evm_jazz() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_SP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_SP -# endif -# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP) -#else -# define machine_is_bcmring_sp() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_SV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_SV -# endif -# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV) -#else -# define machine_is_bcmring_sv() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_SV_JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ -# endif -# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ) -#else -# define machine_is_bcmring_sv_jazz() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_TABLET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_TABLET -# endif -# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET) -#else -# define machine_is_bcmring_tablet() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_VP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_VP -# endif -# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP) -#else -# define machine_is_bcmring_vp() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR -# endif -# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR) -#else -# define machine_is_bcmring_evm_seikor() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_SP_WQVGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA -# endif -# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA) -#else -# define machine_is_bcmring_sp_wqvga() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_CUSTOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM -# endif -# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM) -#else -# define machine_is_bcmring_custom() (0) -#endif - -#ifdef CONFIG_MACH_ACER_S200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_S200 -# endif -# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200) -#else -# define machine_is_acer_s200() (0) -#endif - -#ifdef CONFIG_MACH_BT270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BT270 -# endif -# define machine_is_bt270() (machine_arch_type == MACH_TYPE_BT270) -#else -# define machine_is_bt270() (0) -#endif - -#ifdef CONFIG_MACH_ISEO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ISEO -# endif -# define machine_is_iseo() (machine_arch_type == MACH_TYPE_ISEO) -#else -# define machine_is_iseo() (0) -#endif - -#ifdef CONFIG_MACH_CEZANNE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEZANNE -# endif -# define machine_is_cezanne() (machine_arch_type == MACH_TYPE_CEZANNE) -#else -# define machine_is_cezanne() (0) -#endif - -#ifdef CONFIG_MACH_LUCCA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUCCA -# endif -# define machine_is_lucca() (machine_arch_type == MACH_TYPE_LUCCA) -#else -# define machine_is_lucca() (0) -#endif - -#ifdef CONFIG_MACH_SUPERSMART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUPERSMART -# endif -# define machine_is_supersmart() (machine_arch_type == MACH_TYPE_SUPERSMART) -#else -# define machine_is_supersmart() (0) -#endif - -#ifdef CONFIG_MACH_CS_MISANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS_MISANO -# endif -# define machine_is_arm11_board() (machine_arch_type == MACH_TYPE_CS_MISANO) -#else -# define machine_is_arm11_board() (0) -#endif - -#ifdef CONFIG_MACH_MAGNOLIA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGNOLIA2 -# endif -# define machine_is_magnolia2() (machine_arch_type == MACH_TYPE_MAGNOLIA2) -#else -# define machine_is_magnolia2() (0) -#endif - -#ifdef CONFIG_MACH_EMXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMXX -# endif -# define machine_is_emxx() (machine_arch_type == MACH_TYPE_EMXX) -#else -# define machine_is_emxx() (0) -#endif - -#ifdef CONFIG_MACH_OUTLAW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OUTLAW -# endif -# define machine_is_outlaw() (machine_arch_type == MACH_TYPE_OUTLAW) -#else -# define machine_is_outlaw() (0) -#endif - -#ifdef CONFIG_MACH_RIOT_BEI2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOT_BEI2 -# endif -# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2) -#else -# define machine_is_riot_bei2() (0) -#endif - -#ifdef CONFIG_MACH_RIOT_VOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOT_VOX -# endif -# define machine_is_riot_vox() (machine_arch_type == MACH_TYPE_RIOT_VOX) -#else -# define machine_is_riot_vox() (0) -#endif - -#ifdef CONFIG_MACH_RIOT_X37 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOT_X37 -# endif -# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37) -#else -# define machine_is_riot_x37() (0) -#endif - -#ifdef CONFIG_MACH_MEGA25MX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEGA25MX -# endif -# define machine_is_mega25mx() (machine_arch_type == MACH_TYPE_MEGA25MX) -#else -# define machine_is_mega25mx() (0) -#endif - -#ifdef CONFIG_MACH_BENZINA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZINA2 -# endif -# define machine_is_benzina2() (machine_arch_type == MACH_TYPE_BENZINA2) -#else -# define machine_is_benzina2() (0) -#endif - -#ifdef CONFIG_MACH_IGNITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGNITE -# endif -# define machine_is_ignite() (machine_arch_type == MACH_TYPE_IGNITE) -#else -# define machine_is_ignite() (0) -#endif - -#ifdef CONFIG_MACH_FOGGIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FOGGIA -# endif -# define machine_is_foggia() (machine_arch_type == MACH_TYPE_FOGGIA) -#else -# define machine_is_foggia() (0) -#endif - -#ifdef CONFIG_MACH_AREZZO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AREZZO -# endif -# define machine_is_arezzo() (machine_arch_type == MACH_TYPE_AREZZO) -#else -# define machine_is_arezzo() (0) -#endif - -#ifdef CONFIG_MACH_LEICA_SKYWALKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEICA_SKYWALKER -# endif -# define machine_is_leica_skywalker() (machine_arch_type == MACH_TYPE_LEICA_SKYWALKER) -#else -# define machine_is_leica_skywalker() (0) -#endif - -#ifdef CONFIG_MACH_JACINTO2_JAMR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JACINTO2_JAMR -# endif -# define machine_is_jacinto2_jamr() (machine_arch_type == MACH_TYPE_JACINTO2_JAMR) -#else -# define machine_is_jacinto2_jamr() (0) -#endif - -#ifdef CONFIG_MACH_GTS_NOVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTS_NOVA -# endif -# define machine_is_gts_nova() (machine_arch_type == MACH_TYPE_GTS_NOVA) -#else -# define machine_is_gts_nova() (0) -#endif - -#ifdef CONFIG_MACH_P3600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P3600 -# endif -# define machine_is_p3600() (machine_arch_type == MACH_TYPE_P3600) -#else -# define machine_is_p3600() (0) -#endif - -#ifdef CONFIG_MACH_DLT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DLT2 -# endif -# define machine_is_dlt2() (machine_arch_type == MACH_TYPE_DLT2) -#else -# define machine_is_dlt2() (0) -#endif - -#ifdef CONFIG_MACH_DF3120 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DF3120 -# endif -# define machine_is_df3120() (machine_arch_type == MACH_TYPE_DF3120) -#else -# define machine_is_df3120() (0) -#endif - -#ifdef CONFIG_MACH_ECUCORE_9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECUCORE_9G20 -# endif -# define machine_is_ecucore_9g20() (machine_arch_type == MACH_TYPE_ECUCORE_9G20) -#else -# define machine_is_ecucore_9g20() (0) -#endif - -#ifdef CONFIG_MACH_NAUTEL_LPC3240 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAUTEL_LPC3240 -# endif -# define machine_is_nautel_lpc3240() (machine_arch_type == MACH_TYPE_NAUTEL_LPC3240) -#else -# define machine_is_nautel_lpc3240() (0) -#endif - -#ifdef CONFIG_MACH_GLACIER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GLACIER -# endif -# define machine_is_glacier() (machine_arch_type == MACH_TYPE_GLACIER) -#else -# define machine_is_glacier() (0) -#endif - -#ifdef CONFIG_MACH_PHRAZER_BULLDOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHRAZER_BULLDOG -# endif -# define machine_is_phrazer_bulldog() (machine_arch_type == MACH_TYPE_PHRAZER_BULLDOG) -#else -# define machine_is_phrazer_bulldog() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BULLDOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BULLDOG -# endif -# define machine_is_omap3_bulldog() (machine_arch_type == MACH_TYPE_OMAP3_BULLDOG) -#else -# define machine_is_omap3_bulldog() (0) -#endif - -#ifdef CONFIG_MACH_PCA101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCA101 -# endif -# define machine_is_pca101() (machine_arch_type == MACH_TYPE_PCA101) -#else -# define machine_is_pca101() (0) -#endif - -#ifdef CONFIG_MACH_BUZZC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUZZC -# endif -# define machine_is_buzzc() (machine_arch_type == MACH_TYPE_BUZZC) -#else -# define machine_is_buzzc() (0) -#endif - -#ifdef CONFIG_MACH_SASIE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SASIE2 -# endif -# define machine_is_sasie2() (machine_arch_type == MACH_TYPE_SASIE2) -#else -# define machine_is_sasie2() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_CIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_CIO -# endif -# define machine_is_davinci_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO) -#else -# define machine_is_davinci_cio() (0) -#endif - -#ifdef CONFIG_MACH_SMARTMETER_DL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTMETER_DL -# endif -# define machine_is_smartmeter_dl() (machine_arch_type == MACH_TYPE_SMARTMETER_DL) -#else -# define machine_is_smartmeter_dl() (0) -#endif - -#ifdef CONFIG_MACH_WZL6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL6410 -# endif -# define machine_is_wzl6410() (machine_arch_type == MACH_TYPE_WZL6410) -#else -# define machine_is_wzl6410() (0) -#endif - -#ifdef CONFIG_MACH_WZL6410M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL6410M -# endif -# define machine_is_wzl6410m() (machine_arch_type == MACH_TYPE_WZL6410M) -#else -# define machine_is_wzl6410m() (0) -#endif - -#ifdef CONFIG_MACH_WZL6410F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL6410F -# endif -# define machine_is_wzl6410f() (machine_arch_type == MACH_TYPE_WZL6410F) -#else -# define machine_is_wzl6410f() (0) -#endif - -#ifdef CONFIG_MACH_WZL6410I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL6410I -# endif -# define machine_is_wzl6410i() (machine_arch_type == MACH_TYPE_WZL6410I) -#else -# define machine_is_wzl6410i() (0) -#endif - -#ifdef CONFIG_MACH_SPACECOM1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPACECOM1 -# endif -# define machine_is_spacecom1() (machine_arch_type == MACH_TYPE_SPACECOM1) -#else -# define machine_is_spacecom1() (0) -#endif - -#ifdef CONFIG_MACH_PINGU920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PINGU920 -# endif -# define machine_is_pingu920() (machine_arch_type == MACH_TYPE_PINGU920) -#else -# define machine_is_pingu920() (0) -#endif - -#ifdef CONFIG_MACH_BRAVOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRAVOC -# endif -# define machine_is_bravoc() (machine_arch_type == MACH_TYPE_BRAVOC) -#else -# define machine_is_bravoc() (0) -#endif - -#ifdef CONFIG_MACH_CYBO2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBO2440 -# endif -# define machine_is_cybo2440() (machine_arch_type == MACH_TYPE_CYBO2440) -#else -# define machine_is_cybo2440() (0) -#endif - -#ifdef CONFIG_MACH_VDSSW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VDSSW -# endif -# define machine_is_vdssw() (machine_arch_type == MACH_TYPE_VDSSW) -#else -# define machine_is_vdssw() (0) -#endif - -#ifdef CONFIG_MACH_ROMULUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROMULUS -# endif -# define machine_is_romulus() (machine_arch_type == MACH_TYPE_ROMULUS) -#else -# define machine_is_romulus() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_MAGIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_MAGIC -# endif -# define machine_is_omap_magic() (machine_arch_type == MACH_TYPE_OMAP_MAGIC) -#else -# define machine_is_omap_magic() (0) -#endif - -#ifdef CONFIG_MACH_ELTD100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELTD100 -# endif -# define machine_is_eltd100() (machine_arch_type == MACH_TYPE_ELTD100) -#else -# define machine_is_eltd100() (0) -#endif - -#ifdef CONFIG_MACH_CAPC7117 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAPC7117 -# endif -# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117) -#else -# define machine_is_capc7117() (0) -#endif - -#ifdef CONFIG_MACH_SWAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWAN -# endif -# define machine_is_swan() (machine_arch_type == MACH_TYPE_SWAN) -#else -# define machine_is_swan() (0) -#endif - -#ifdef CONFIG_MACH_VEU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VEU -# endif -# define machine_is_veu() (machine_arch_type == MACH_TYPE_VEU) -#else -# define machine_is_veu() (0) -#endif - -#ifdef CONFIG_MACH_RM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RM2 -# endif -# define machine_is_rm2() (machine_arch_type == MACH_TYPE_RM2) -#else -# define machine_is_rm2() (0) -#endif - -#ifdef CONFIG_MACH_TT2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT2100 -# endif -# define machine_is_tt2100() (machine_arch_type == MACH_TYPE_TT2100) -#else -# define machine_is_tt2100() (0) -#endif - -#ifdef CONFIG_MACH_VENICE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENICE -# endif -# define machine_is_venice() (machine_arch_type == MACH_TYPE_VENICE) -#else -# define machine_is_venice() (0) -#endif - -#ifdef CONFIG_MACH_PC7323 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC7323 -# endif -# define machine_is_pc7323() (machine_arch_type == MACH_TYPE_PC7323) -#else -# define machine_is_pc7323() (0) -#endif - -#ifdef CONFIG_MACH_MASP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MASP -# endif -# define machine_is_masp() (machine_arch_type == MACH_TYPE_MASP) -#else -# define machine_is_masp() (0) -#endif - -#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC -# endif -# define machine_is_fujitsu_tvstbsoc0() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC) -#else -# define machine_is_fujitsu_tvstbsoc0() (0) -#endif - -#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC1 -# endif -# define machine_is_fujitsu_tvstbsoc1() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC1) -#else -# define machine_is_fujitsu_tvstbsoc1() (0) -#endif - -#ifdef CONFIG_MACH_LEXIKON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEXIKON -# endif -# define machine_is_lexikon() (machine_arch_type == MACH_TYPE_LEXIKON) -#else -# define machine_is_lexikon() (0) -#endif - -#ifdef CONFIG_MACH_MINI2440V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI2440V2 -# endif -# define machine_is_mini2440v2() (machine_arch_type == MACH_TYPE_MINI2440V2) -#else -# define machine_is_mini2440v2() (0) -#endif - -#ifdef CONFIG_MACH_ICONTROL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICONTROL -# endif -# define machine_is_icontrol() (machine_arch_type == MACH_TYPE_ICONTROL) -#else -# define machine_is_icontrol() (0) -#endif - -#ifdef CONFIG_MACH_SHEEVAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEEVAD -# endif -# define machine_is_sheevad() (machine_arch_type == MACH_TYPE_SHEEVAD) -#else -# define machine_is_sheevad() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_ST1_1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_1 -# endif -# define machine_is_qsd8x50a_st1_1() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_1) -#else -# define machine_is_qsd8x50a_st1_1() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_ST1_5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_5 -# endif -# define machine_is_qsd8x50a_st1_5() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5) -#else -# define machine_is_qsd8x50a_st1_5() (0) -#endif - -#ifdef CONFIG_MACH_BEE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEE -# endif -# define machine_is_bee() (machine_arch_type == MACH_TYPE_BEE) -#else -# define machine_is_bee() (0) -#endif - -#ifdef CONFIG_MACH_MX23EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX23EVK -# endif -# define machine_is_mx23evk() (machine_arch_type == MACH_TYPE_MX23EVK) -#else -# define machine_is_mx23evk() (0) -#endif - -#ifdef CONFIG_MACH_AP4EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AP4EVB -# endif -# define machine_is_ap4evb() (machine_arch_type == MACH_TYPE_AP4EVB) -#else -# define machine_is_ap4evb() (0) -#endif - -#ifdef CONFIG_MACH_STOCKHOLM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STOCKHOLM -# endif -# define machine_is_stockholm() (machine_arch_type == MACH_TYPE_STOCKHOLM) -#else -# define machine_is_stockholm() (0) -#endif - -#ifdef CONFIG_MACH_LPC_H3131 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC_H3131 -# endif -# define machine_is_lpc_h3131() (machine_arch_type == MACH_TYPE_LPC_H3131) -#else -# define machine_is_lpc_h3131() (0) -#endif - -#ifdef CONFIG_MACH_STINGRAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STINGRAY -# endif -# define machine_is_stingray() (machine_arch_type == MACH_TYPE_STINGRAY) -#else -# define machine_is_stingray() (0) -#endif - -#ifdef CONFIG_MACH_KRAKEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRAKEN -# endif -# define machine_is_kraken() (machine_arch_type == MACH_TYPE_KRAKEN) -#else -# define machine_is_kraken() (0) -#endif - -#ifdef CONFIG_MACH_GW2388 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GW2388 -# endif -# define machine_is_gw2388() (machine_arch_type == MACH_TYPE_GW2388) -#else -# define machine_is_gw2388() (0) -#endif - -#ifdef CONFIG_MACH_JADECPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADECPU -# endif -# define machine_is_jadecpu() (machine_arch_type == MACH_TYPE_JADECPU) -#else -# define machine_is_jadecpu() (0) -#endif - -#ifdef CONFIG_MACH_CARLISLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARLISLE -# endif -# define machine_is_carlisle() (machine_arch_type == MACH_TYPE_CARLISLE) -#else -# define machine_is_carlisle() (0) -#endif - -#ifdef CONFIG_MACH_LUX_SFT9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUX_SFT9 -# endif -# define machine_is_lux_sf9() (machine_arch_type == MACH_TYPE_LUX_SFT9) -#else -# define machine_is_lux_sf9() (0) -#endif - -#ifdef CONFIG_MACH_NEMID_TB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEMID_TB -# endif -# define machine_is_nemid_tb() (machine_arch_type == MACH_TYPE_NEMID_TB) -#else -# define machine_is_nemid_tb() (0) -#endif - -#ifdef CONFIG_MACH_TERRIER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERRIER -# endif -# define machine_is_terrier() (machine_arch_type == MACH_TYPE_TERRIER) -#else -# define machine_is_terrier() (0) -#endif - -#ifdef CONFIG_MACH_TURBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TURBOT -# endif -# define machine_is_turbot() (machine_arch_type == MACH_TYPE_TURBOT) -#else -# define machine_is_turbot() (0) -#endif - -#ifdef CONFIG_MACH_SANDDAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDDAB -# endif -# define machine_is_sanddab() (machine_arch_type == MACH_TYPE_SANDDAB) -#else -# define machine_is_sanddab() (0) -#endif - -#ifdef CONFIG_MACH_MX35_CICADA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_CICADA -# endif -# define machine_is_mx35_cicada() (machine_arch_type == MACH_TYPE_MX35_CICADA) -#else -# define machine_is_mx35_cicada() (0) -#endif - -#ifdef CONFIG_MACH_GHI2703D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GHI2703D -# endif -# define machine_is_ghi2703d() (machine_arch_type == MACH_TYPE_GHI2703D) -#else -# define machine_is_ghi2703d() (0) -#endif - -#ifdef CONFIG_MACH_LUX_SFX9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUX_SFX9 -# endif -# define machine_is_lux_sfx9() (machine_arch_type == MACH_TYPE_LUX_SFX9) -#else -# define machine_is_lux_sfx9() (0) -#endif - -#ifdef CONFIG_MACH_LUX_SF9G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUX_SF9G -# endif -# define machine_is_lux_sf9g() (machine_arch_type == MACH_TYPE_LUX_SF9G) -#else -# define machine_is_lux_sf9g() (0) -#endif - -#ifdef CONFIG_MACH_LUX_EDK9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUX_EDK9 -# endif -# define machine_is_lux_edk9() (machine_arch_type == MACH_TYPE_LUX_EDK9) -#else -# define machine_is_lux_edk9() (0) -#endif - -#ifdef CONFIG_MACH_HW90240 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90240 -# endif -# define machine_is_hw90240() (machine_arch_type == MACH_TYPE_HW90240) -#else -# define machine_is_hw90240() (0) -#endif - -#ifdef CONFIG_MACH_DM365_LEOPARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM365_LEOPARD -# endif -# define machine_is_dm365_leopard() (machine_arch_type == MACH_TYPE_DM365_LEOPARD) -#else -# define machine_is_dm365_leopard() (0) -#endif - -#ifdef CONFIG_MACH_MITYOMAPL138 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MITYOMAPL138 -# endif -# define machine_is_mityomapl138() (machine_arch_type == MACH_TYPE_MITYOMAPL138) -#else -# define machine_is_mityomapl138() (0) -#endif - -#ifdef CONFIG_MACH_SCAT110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCAT110 -# endif -# define machine_is_scat110() (machine_arch_type == MACH_TYPE_SCAT110) -#else -# define machine_is_scat110() (0) -#endif - -#ifdef CONFIG_MACH_ACER_A1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_A1 -# endif -# define machine_is_acer_a1() (machine_arch_type == MACH_TYPE_ACER_A1) -#else -# define machine_is_acer_a1() (0) -#endif - -#ifdef CONFIG_MACH_CMCONTROL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMCONTROL -# endif -# define machine_is_cmcontrol() (machine_arch_type == MACH_TYPE_CMCONTROL) -#else -# define machine_is_cmcontrol() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_LAMAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_LAMAR -# endif -# define machine_is_pelco_lamar() (machine_arch_type == MACH_TYPE_PELCO_LAMAR) -#else -# define machine_is_pelco_lamar() (0) -#endif - -#ifdef CONFIG_MACH_RFP43 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RFP43 -# endif -# define machine_is_rfp43() (machine_arch_type == MACH_TYPE_RFP43) -#else -# define machine_is_rfp43() (0) -#endif - -#ifdef CONFIG_MACH_SK86R0301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SK86R0301 -# endif -# define machine_is_sk86r0301() (machine_arch_type == MACH_TYPE_SK86R0301) -#else -# define machine_is_sk86r0301() (0) -#endif - -#ifdef CONFIG_MACH_CTPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTPXA -# endif -# define machine_is_ctpxa() (machine_arch_type == MACH_TYPE_CTPXA) -#else -# define machine_is_ctpxa() (0) -#endif - -#ifdef CONFIG_MACH_EPB_ARM9_A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPB_ARM9_A -# endif -# define machine_is_epb_arm9_a() (machine_arch_type == MACH_TYPE_EPB_ARM9_A) -#else -# define machine_is_epb_arm9_a() (0) -#endif - -#ifdef CONFIG_MACH_GURUPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GURUPLUG -# endif -# define machine_is_guruplug() (machine_arch_type == MACH_TYPE_GURUPLUG) -#else -# define machine_is_guruplug() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR310 -# endif -# define machine_is_spear310() (machine_arch_type == MACH_TYPE_SPEAR310) -#else -# define machine_is_spear310() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR320 -# endif -# define machine_is_spear320() (machine_arch_type == MACH_TYPE_SPEAR320) -#else -# define machine_is_spear320() (0) -#endif - -#ifdef CONFIG_MACH_ROBOTX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROBOTX -# endif -# define machine_is_robotx() (machine_arch_type == MACH_TYPE_ROBOTX) -#else -# define machine_is_robotx() (0) -#endif - -#ifdef CONFIG_MACH_LSXHL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LSXHL -# endif -# define machine_is_lsxhl() (machine_arch_type == MACH_TYPE_LSXHL) -#else -# define machine_is_lsxhl() (0) -#endif - -#ifdef CONFIG_MACH_SMARTLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTLITE -# endif -# define machine_is_smartlite() (machine_arch_type == MACH_TYPE_SMARTLITE) -#else -# define machine_is_smartlite() (0) -#endif - -#ifdef CONFIG_MACH_CWS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWS2 -# endif -# define machine_is_cws2() (machine_arch_type == MACH_TYPE_CWS2) -#else -# define machine_is_cws2() (0) -#endif - -#ifdef CONFIG_MACH_M619 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M619 -# endif -# define machine_is_m619() (machine_arch_type == MACH_TYPE_M619) -#else -# define machine_is_m619() (0) -#endif - -#ifdef CONFIG_MACH_SMARTVIEW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTVIEW -# endif -# define machine_is_smartview() (machine_arch_type == MACH_TYPE_SMARTVIEW) -#else -# define machine_is_smartview() (0) -#endif - -#ifdef CONFIG_MACH_LSA_SALSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LSA_SALSA -# endif -# define machine_is_lsa_salsa() (machine_arch_type == MACH_TYPE_LSA_SALSA) -#else -# define machine_is_lsa_salsa() (0) -#endif - -#ifdef CONFIG_MACH_KIZBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIZBOX -# endif -# define machine_is_kizbox() (machine_arch_type == MACH_TYPE_KIZBOX) -#else -# define machine_is_kizbox() (0) -#endif - -#ifdef CONFIG_MACH_HTCCHARMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCCHARMER -# endif -# define machine_is_htccharmer() (machine_arch_type == MACH_TYPE_HTCCHARMER) -#else -# define machine_is_htccharmer() (0) -#endif - -#ifdef CONFIG_MACH_GUF_NESO_LT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUF_NESO_LT -# endif -# define machine_is_guf_neso_lt() (machine_arch_type == MACH_TYPE_GUF_NESO_LT) -#else -# define machine_is_guf_neso_lt() (0) -#endif - -#ifdef CONFIG_MACH_PM9G45 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM9G45 -# endif -# define machine_is_pm9g45() (machine_arch_type == MACH_TYPE_PM9G45) -#else -# define machine_is_pm9g45() (0) -#endif - -#ifdef CONFIG_MACH_HTCPANTHER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPANTHER -# endif -# define machine_is_htcpanther() (machine_arch_type == MACH_TYPE_HTCPANTHER) -#else -# define machine_is_htcpanther() (0) -#endif - -#ifdef CONFIG_MACH_HTCPANTHER_CDMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPANTHER_CDMA -# endif -# define machine_is_htcpanther_cdma() (machine_arch_type == MACH_TYPE_HTCPANTHER_CDMA) -#else -# define machine_is_htcpanther_cdma() (0) -#endif - -#ifdef CONFIG_MACH_REB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REB01 -# endif -# define machine_is_reb01() (machine_arch_type == MACH_TYPE_REB01) -#else -# define machine_is_reb01() (0) -#endif - -#ifdef CONFIG_MACH_AQUILA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AQUILA -# endif -# define machine_is_aquila() (machine_arch_type == MACH_TYPE_AQUILA) -#else -# define machine_is_aquila() (0) -#endif - -#ifdef CONFIG_MACH_SPARK_SLS_HW2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPARK_SLS_HW2 -# endif -# define machine_is_spark_sls_hw2() (machine_arch_type == MACH_TYPE_SPARK_SLS_HW2) -#else -# define machine_is_spark_sls_hw2() (0) -#endif - -#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESATA_SHEEVAPLUG -# endif -# define machine_is_sheeva_esata() (machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG) -#else -# define machine_is_sheeva_esata() (0) -#endif - -#ifdef CONFIG_MACH_SURF7X30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SURF7X30 -# endif -# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_SURF7X30) -#else -# define machine_is_msm7x30_surf() (0) -#endif - -#ifdef CONFIG_MACH_MICRO2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO2440 -# endif -# define machine_is_micro2440() (machine_arch_type == MACH_TYPE_MICRO2440) -#else -# define machine_is_micro2440() (0) -#endif - -#ifdef CONFIG_MACH_AM2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AM2440 -# endif -# define machine_is_am2440() (machine_arch_type == MACH_TYPE_AM2440) -#else -# define machine_is_am2440() (0) -#endif - -#ifdef CONFIG_MACH_TQ2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TQ2440 -# endif -# define machine_is_tq2440() (machine_arch_type == MACH_TYPE_TQ2440) -#else -# define machine_is_tq2440() (0) -#endif - -#ifdef CONFIG_MACH_LPC2478OEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC2478OEM -# endif -# define machine_is_lpc2478oem() (machine_arch_type == MACH_TYPE_LPC2478OEM) -#else -# define machine_is_lpc2478oem() (0) -#endif - -#ifdef CONFIG_MACH_AK880X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AK880X -# endif -# define machine_is_ak880x() (machine_arch_type == MACH_TYPE_AK880X) -#else -# define machine_is_ak880x() (0) -#endif - -#ifdef CONFIG_MACH_COBRA3530 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COBRA3530 -# endif -# define machine_is_cobra3530() (machine_arch_type == MACH_TYPE_COBRA3530) -#else -# define machine_is_cobra3530() (0) -#endif - -#ifdef CONFIG_MACH_PMPPB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PMPPB -# endif -# define machine_is_pmppb() (machine_arch_type == MACH_TYPE_PMPPB) -#else -# define machine_is_pmppb() (0) -#endif - -#ifdef CONFIG_MACH_U6715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U6715 -# endif -# define machine_is_u6715() (machine_arch_type == MACH_TYPE_U6715) -#else -# define machine_is_u6715() (0) -#endif - -#ifdef CONFIG_MACH_AXAR1500_SENDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXAR1500_SENDER -# endif -# define machine_is_axar1500_sender() (machine_arch_type == MACH_TYPE_AXAR1500_SENDER) -#else -# define machine_is_axar1500_sender() (0) -#endif - -#ifdef CONFIG_MACH_G30_DVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G30_DVB -# endif -# define machine_is_g30_dvb() (machine_arch_type == MACH_TYPE_G30_DVB) -#else -# define machine_is_g30_dvb() (0) -#endif - -#ifdef CONFIG_MACH_VC088X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC088X -# endif -# define machine_is_vc088x() (machine_arch_type == MACH_TYPE_VC088X) -#else -# define machine_is_vc088x() (0) -#endif - -#ifdef CONFIG_MACH_MIOA702 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIOA702 -# endif -# define machine_is_mioa702() (machine_arch_type == MACH_TYPE_MIOA702) -#else -# define machine_is_mioa702() (0) -#endif - -#ifdef CONFIG_MACH_HPMIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPMIN -# endif -# define machine_is_hpmin() (machine_arch_type == MACH_TYPE_HPMIN) -#else -# define machine_is_hpmin() (0) -#endif - -#ifdef CONFIG_MACH_AK880XAK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AK880XAK -# endif -# define machine_is_ak880xak() (machine_arch_type == MACH_TYPE_AK880XAK) -#else -# define machine_is_ak880xak() (0) -#endif - -#ifdef CONFIG_MACH_ARM926TOMAP850 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM926TOMAP850 -# endif -# define machine_is_arm926tomap850() (machine_arch_type == MACH_TYPE_ARM926TOMAP850) -#else -# define machine_is_arm926tomap850() (0) -#endif - -#ifdef CONFIG_MACH_LKEVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LKEVM -# endif -# define machine_is_lkevm() (machine_arch_type == MACH_TYPE_LKEVM) -#else -# define machine_is_lkevm() (0) -#endif - -#ifdef CONFIG_MACH_MW6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MW6410 -# endif -# define machine_is_mw6410() (machine_arch_type == MACH_TYPE_MW6410) -#else -# define machine_is_mw6410() (0) -#endif - -#ifdef CONFIG_MACH_TERASTATION_WXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERASTATION_WXL -# endif -# define machine_is_terastation_wxl() (machine_arch_type == MACH_TYPE_TERASTATION_WXL) -#else -# define machine_is_terastation_wxl() (0) -#endif - -#ifdef CONFIG_MACH_CPU8000E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPU8000E -# endif -# define machine_is_cpu8000e() (machine_arch_type == MACH_TYPE_CPU8000E) -#else -# define machine_is_cpu8000e() (0) -#endif - -#ifdef CONFIG_MACH_CATANIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATANIA -# endif -# define machine_is_catania() (machine_arch_type == MACH_TYPE_CATANIA) -#else -# define machine_is_catania() (0) -#endif - -#ifdef CONFIG_MACH_TOKYO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOKYO -# endif -# define machine_is_tokyo() (machine_arch_type == MACH_TYPE_TOKYO) -#else -# define machine_is_tokyo() (0) -#endif - -#ifdef CONFIG_MACH_MSM7201A_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7201A_SURF -# endif -# define machine_is_msm7201a_surf() (machine_arch_type == MACH_TYPE_MSM7201A_SURF) -#else -# define machine_is_msm7201a_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7201A_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7201A_FFA -# endif -# define machine_is_msm7201a_ffa() (machine_arch_type == MACH_TYPE_MSM7201A_FFA) -#else -# define machine_is_msm7201a_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X25_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X25_SURF -# endif -# define machine_is_msm7x25_surf() (machine_arch_type == MACH_TYPE_MSM7X25_SURF) -#else -# define machine_is_msm7x25_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X25_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X25_FFA -# endif -# define machine_is_msm7x25_ffa() (machine_arch_type == MACH_TYPE_MSM7X25_FFA) -#else -# define machine_is_msm7x25_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27_SURF -# endif -# define machine_is_msm7x27_surf() (machine_arch_type == MACH_TYPE_MSM7X27_SURF) -#else -# define machine_is_msm7x27_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27_FFA -# endif -# define machine_is_msm7x27_ffa() (machine_arch_type == MACH_TYPE_MSM7X27_FFA) -#else -# define machine_is_msm7x27_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X30_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X30_FFA -# endif -# define machine_is_msm7x30_ffa() (machine_arch_type == MACH_TYPE_MSM7X30_FFA) -#else -# define machine_is_msm7x30_ffa() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_SURF -# endif -# define machine_is_qsd8x50_surf() (machine_arch_type == MACH_TYPE_QSD8X50_SURF) -#else -# define machine_is_qsd8x50_surf() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_COMET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_COMET -# endif -# define machine_is_qsd8x50_comet() (machine_arch_type == MACH_TYPE_QSD8X50_COMET) -#else -# define machine_is_qsd8x50_comet() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_FFA -# endif -# define machine_is_qsd8x50_ffa() (machine_arch_type == MACH_TYPE_QSD8X50_FFA) -#else -# define machine_is_qsd8x50_ffa() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_SURF -# endif -# define machine_is_qsd8x50a_surf() (machine_arch_type == MACH_TYPE_QSD8X50A_SURF) -#else -# define machine_is_qsd8x50a_surf() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_FFA -# endif -# define machine_is_qsd8x50a_ffa() (machine_arch_type == MACH_TYPE_QSD8X50A_FFA) -#else -# define machine_is_qsd8x50a_ffa() (0) -#endif - -#ifdef CONFIG_MACH_XGCP10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XGCP10 -# endif -# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_XGCP10) -#else -# define machine_is_adx_xgcp10() (0) -#endif - -#ifdef CONFIG_MACH_MCGWUMTS2A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCGWUMTS2A -# endif -# define machine_is_mcgwumts2a() (machine_arch_type == MACH_TYPE_MCGWUMTS2A) -#else -# define machine_is_mcgwumts2a() (0) -#endif - -#ifdef CONFIG_MACH_MOBIKT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOBIKT -# endif -# define machine_is_mobikt() (machine_arch_type == MACH_TYPE_MOBIKT) -#else -# define machine_is_mobikt() (0) -#endif - -#ifdef CONFIG_MACH_MX53_EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX53_EVK -# endif -# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK) -#else -# define machine_is_mx53_evk() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0030 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0030 -# endif -# define machine_is_igep0030() (machine_arch_type == MACH_TYPE_IGEP0030) -#else -# define machine_is_igep0030() (0) -#endif - -#ifdef CONFIG_MACH_AXELL_H40_H50_CTRL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXELL_H40_H50_CTRL -# endif -# define machine_is_axell_h40_h50_ctrl() (machine_arch_type == MACH_TYPE_AXELL_H40_H50_CTRL) -#else -# define machine_is_axell_h40_h50_ctrl() (0) -#endif - -/* - * These have not yet been registered - */ - -#ifndef machine_arch_type -#define machine_arch_type __machine_arch_type -#endif - -#endif diff --git a/include/asm-blackfin/config-pre.h b/include/asm-blackfin/config-pre.h deleted file mode 100644 index 1170a2a904..0000000000 --- a/include/asm-blackfin/config-pre.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * config-pre.h - common defines for Blackfin boards in config.h - * - * Copyright (c) 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__ -#define __ASM_BLACKFIN_CONFIG_PRE_H__ - -/* Misc helper functions */ -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE. - * Depending on your cpu, some of these may not be valid, check your HRM. - * The actual values here are meaningless as long as they're unique. - */ -#define BFIN_BOOT_BYPASS 1 /* bypass bootrom */ -#define BFIN_BOOT_PARA 2 /* boot ldr out of parallel flash */ -#define BFIN_BOOT_SPI_MASTER 3 /* boot ldr out of serial flash */ -#define BFIN_BOOT_SPI_SLAVE 4 /* boot ldr as spi slave */ -#define BFIN_BOOT_TWI_MASTER 5 /* boot ldr over twi device */ -#define BFIN_BOOT_TWI_SLAVE 6 /* boot ldr over twi slave */ -#define BFIN_BOOT_UART 7 /* boot ldr over uart */ -#define BFIN_BOOT_IDLE 8 /* do nothing, just idle */ -#define BFIN_BOOT_FIFO 9 /* boot ldr out of FIFO */ -#define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */ -#define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */ -#define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */ -#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */ - -#ifndef __ASSEMBLY__ -static inline const char *get_bfin_boot_mode(int bfin_boot) -{ - switch (bfin_boot) { - case BFIN_BOOT_BYPASS: return "bypass"; - case BFIN_BOOT_PARA: return "parallel flash"; - case BFIN_BOOT_SPI_MASTER: return "spi flash"; - case BFIN_BOOT_SPI_SLAVE: return "spi slave"; - case BFIN_BOOT_TWI_MASTER: return "i2c flash"; - case BFIN_BOOT_TWI_SLAVE: return "i2c slave"; - case BFIN_BOOT_UART: return "uart"; - case BFIN_BOOT_IDLE: return "idle"; - case BFIN_BOOT_FIFO: return "fifo"; - case BFIN_BOOT_MEM: return "memory"; - case BFIN_BOOT_16HOST_DMA: return "16bit dma"; - case BFIN_BOOT_8HOST_DMA: return "8bit dma"; - case BFIN_BOOT_NAND: return "nand flash"; - default: return "INVALID"; - } -} -#endif - -/* Most bootroms allow for EVT1 redirection */ -#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \ - && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__) -# undef CONFIG_BFIN_BOOTROM_USES_EVT1 -#else -# define CONFIG_BFIN_BOOTROM_USES_EVT1 -#endif - -/* Define the default SPI CS used when booting out of SPI */ -#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ - defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \ - defined(__ADSPBF51x__) -# define BFIN_BOOT_SPI_SSEL 2 -#else -# define BFIN_BOOT_SPI_SSEL 1 -#endif - -/* We rarely use interrupts, so favor throughput over latency */ -#define CONFIG_BFIN_INS_LOWOVERHEAD - -#endif diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h deleted file mode 100644 index f1b7d0064b..0000000000 --- a/include/asm-blackfin/ptrace.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * U-boot - ptrace.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BLACKFIN_PTRACE_H -#define _BLACKFIN_PTRACE_H - -#define NEW_PT_REGS - -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 7 are data registers R0-R7 - * 8 - 15 are address registers P0-P7 - * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 - * 32 - 33 A registers A0 & A1 - * 34 - status register - * - * We follows above, except: - * 32-33 --- Low 32-bit of A0&1 - * 34-35 --- High 8-bit of A0&1 - */ - -#if defined(NEW_PT_REGS) - -#define PT_IPEND 0 -#define PT_SYSCFG (PT_IPEND+4) -#define PT_SEQSTAT (PT_SYSCFG+4) -#define PT_RETE (PT_SEQSTAT+4) -#define PT_RETN (PT_RETE+4) -#define PT_RETX (PT_RETN+4) -#define PT_RETI (PT_RETX+4) -#define PT_PC PT_RETI -#define PT_RETS (PT_RETI+4) -#define PT_RESERVED (PT_RETS+4) -#define PT_ASTAT (PT_RESERVED+4) -#define PT_LB1 (PT_ASTAT+4) -#define PT_LB0 (PT_LB1+4) -#define PT_LT1 (PT_LB0+4) -#define PT_LT0 (PT_LT1+4) -#define PT_LC1 (PT_LT0+4) -#define PT_LC0 (PT_LC1+4) -#define PT_A1W (PT_LC0+4) -#define PT_A1X (PT_A1W+4) -#define PT_A0W (PT_A1X+4) -#define PT_A0X (PT_A0W+4) -#define PT_B3 (PT_A0X+4) -#define PT_B2 (PT_B3+4) -#define PT_B1 (PT_B2+4) -#define PT_B0 (PT_B1+4) -#define PT_L3 (PT_B0+4) -#define PT_L2 (PT_L3+4) -#define PT_L1 (PT_L2+4) -#define PT_L0 (PT_L1+4) -#define PT_M3 (PT_L0+4) -#define PT_M2 (PT_M3+4) -#define PT_M1 (PT_M2+4) -#define PT_M0 (PT_M1+4) -#define PT_I3 (PT_M0+4) -#define PT_I2 (PT_I3+4) -#define PT_I1 (PT_I2+4) -#define PT_I0 (PT_I1+4) -#define PT_USP (PT_I0+4) -#define PT_FP (PT_USP+4) -#define PT_P5 (PT_FP+4) -#define PT_P4 (PT_P5+4) -#define PT_P3 (PT_P4+4) -#define PT_P2 (PT_P3+4) -#define PT_P1 (PT_P2+4) -#define PT_P0 (PT_P1+4) -#define PT_R7 (PT_P0+4) -#define PT_R6 (PT_R7+4) -#define PT_R5 (PT_R6+4) -#define PT_R4 (PT_R5+4) -#define PT_R3 (PT_R4+4) -#define PT_R2 (PT_R3+4) -#define PT_R1 (PT_R2+4) -#define PT_R0 (PT_R1+4) -#define PT_ORIG_R0 (PT_R0+4) -#define PT_SR PT_SEQSTAT - -#else -/* - * Here utilize blackfin : dpregs = [pregs + imm16s4] - * [pregs + imm16s4] = dpregs - * to access defferent saved reg in stack - */ -#define PT_R3 0 -#define PT_R4 4 -#define PT_R2 8 -#define PT_R1 12 -#define PT_P5 16 -#define PT_P4 20 -#define PT_P3 24 -#define PT_P2 28 -#define PT_P1 32 -#define PT_P0 36 -#define PT_R7 40 -#define PT_R6 44 -#define PT_R5 48 -#define PT_PC 52 -#define PT_SEQSTAT 56 /* so-called SR reg */ -#define PT_SR PT_SEQSTAT -#define PT_ASTAT 60 -#define PT_RETS 64 -#define PT_A1w 68 -#define PT_A0w 72 -#define PT_A1x 76 -#define PT_A0x 80 -#define PT_ORIG_R0 84 -#define PT_R0 88 -#define PT_USP 92 -#define PT_FP 96 -#define PT_SP 100 - -/* Added by HuTao, May26 2003 3:18PM */ -#define PT_IPEND 100 - -/* Add SYSCFG register for single stepping support */ -#define PT_SYSCFG 104 - -#endif - -#ifndef __ASSEMBLY__ - -#if defined(NEW_PT_REGS) -/* this struct defines the way the registers are stored on the - * stack during a system call. - */ -struct pt_regs { - long ipend; - long syscfg; - long seqstat; - long rete; - long retn; - long retx; - long pc; - long rets; - long reserved; - long astat; - long lb1; - long lb0; - long lt1; - long lt0; - long lc1; - long lc0; - long a1w; - long a1x; - long a0w; - long a0x; - long b3; - long b2; - long b1; - long b0; - long l3; - long l2; - long l1; - long l0; - long m3; - long m2; - long m1; - long m0; - long i3; - long i2; - long i1; - long i0; - long usp; - long fp; - long p5; - long p4; - long p3; - long p2; - long p1; - long p0; - long r7; - long r6; - long r5; - long r4; - long r3; - long r2; - long r1; - long r0; - long orig_r0; -}; - -#else -/* now we don't know what regs the system call will use */ -struct pt_regs { - long r3; - long r4; - long r2; - long r1; - long p5; - long p4; - long p3; - long p2; - long p1; - long p0; - long r7; - long r6; - long r5; - unsigned long pc; - unsigned long seqstat; - unsigned long astat; - unsigned long rets; - long a1w; - long a0w; - long a1x; - long a0x; - long orig_r0; - long r0; - long usp; - long fp; -/* - * Added for supervisor/user mode switch. - * - * HuTao May26 03 3:23PM - */ - long ipend; - long syscfg; -}; - -#endif - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 /* ptrace signal */ - -#ifdef __KERNEL__ - -#ifndef PS_S -#define PS_S (0x0c00) - -/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode - * 00: user - * 01: supervisor - * 1x: debug - */ - -#define PS_M (0x1000) /* I am not sure why this is required here Akbar */ -#endif - -#define user_mode(regs) (!((regs)->seqstat & PS_S)) -#define instruction_pointer(regs) ((regs)->pc) -extern void show_regs(struct pt_regs *); - -#endif -#endif -#endif diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h deleted file mode 100644 index b90cedacbc..0000000000 --- a/include/asm-blackfin/traps.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * U-boot - traps.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * linux/include/asm/traps.h - * Copyright (C) 1993 Hamish Macdonald - * Lineo, Inc Jul 2001 Tony Kou - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* - */ - -#ifndef _BLACKFIN_TRAPS_H -#define _BLACKFIN_TRAPS_H - -#ifndef __ASSEMBLY__ -typedef void (*e_vector) (void); -extern e_vector vectors[]; -#endif - -#define VEC_SYS (0) -#define VEC_EXCPT01 (1) -#define VEC_EXCPT02 (2) -#define VEC_EXCPT03 (3) -#define VEC_EXCPT04 (4) -#define VEC_EXCPT05 (5) -#define VEC_EXCPT06 (6) -#define VEC_EXCPT07 (7) -#define VEC_EXCPT08 (8) -#define VEC_EXCPT09 (9) -#define VEC_EXCPT10 (10) -#define VEC_EXCPT11 (11) -#define VEC_EXCPT12 (12) -#define VEC_EXCPT13 (13) -#define VEC_EXCPT14 (14) -#define VEC_EXCPT15 (15) -#define VEC_STEP (16) -#define VEC_OVFLOW (17) -#define VEC_UNDEF_I (33) -#define VEC_ILGAL_I (34) -#define VEC_CPLB_VL (35) -#define VEC_MISALI_D (36) -#define VEC_UNCOV (37) -#define VEC_CPLB_M (38) -#define VEC_CPLB_MHIT (39) -#define VEC_WATCH (40) -#define VEC_ISTRU_VL (41) -#define VEC_MISALI_I (42) -#define VEC_CPLB_I_VL (43) -#define VEC_CPLB_I_M (44) -#define VEC_CPLB_I_MHIT (45) -#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ - -#define VECOFF(vec) ((vec)<<2) - -#ifndef __ASSEMBLY__ - -/* Status register bits */ -#define PS_T (0x8000) -#define PS_S (0x0c00) /* Supervisor mode = 0b01 */ -#define PS_D (0x0c00) /* Debug mode = 0b1x */ -#define PS_M (0x1000) -#define PS_C (0x0001) - -#endif -#endif diff --git a/include/asm-i386/interrupt.h b/include/asm-i386/interrupt.h deleted file mode 100644 index 3e2674af68..0000000000 --- a/include/asm-i386/interrupt.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2009 - * Graeme Russ, graeme.russ@gmail.com - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_INTERRUPT_H_ -#define __ASM_INTERRUPT_H_ 1 - -/* cpu/i386/interrupts.c */ -void set_vector(u8 intnum, void *routine); - -/* lib_i386/interupts.c */ -void disable_irq(int irq); -void enable_irq(int irq); - -/* Architecture specific functions */ -void mask_irq(int irq); -void unmask_irq(int irq); -void specific_eoi(int irq); - -extern char exception_stack[]; - -#define __isr__ void __attribute__ ((regparm(0))) - -#endif diff --git a/include/asm-i386/u-boot-i386.h b/include/asm-i386/u-boot-i386.h deleted file mode 100644 index 7c99c8c57d..0000000000 --- a/include/asm-i386/u-boot-i386.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _U_BOOT_I386_H_ -#define _U_BOOT_I386_H_ 1 - -/* cpu/.../cpu.c */ -int cpu_init_r(void); -int cpu_init_f(void); - -/* cpu/.../timer.c */ -void timer_isr(void *); -typedef void (timer_fnc_t) (void); -int register_timer_isr (timer_fnc_t *isr_func); - -/* Architecture specific - can be in cpu/i386/, lib_i386/, or $(BOARD)/ */ -int timer_init(void); - -/* cpu/.../interrupts.c */ -int cpu_init_interrupts(void); - -/* board/.../... */ -int board_init(void); -int dram_init(void); - -void isa_unmap_rom(u32 addr); -u32 isa_map_rom(u32 bus_addr, int size); - -/* lib_i386/... */ -int video_bios_init(void); -int video_init(void); - - -#endif /* _U_BOOT_I386_H_ */ diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h deleted file mode 100644 index b5a4cb54a7..0000000000 --- a/include/asm-m68k/immap_5253.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * MCF5253 Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5253__ -#define __IMMAP_5253__ - -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) - -#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) -#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) - -#include -#include -#include -#include - -typedef struct canex_ctrl { - can_msg_t msg[32]; /* 0x80 Message Buffer 0-31 */ -} canex_t; - -#endif /* __IMMAP_5253__ */ diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h deleted file mode 100644 index 267bfd994a..0000000000 --- a/include/asm-m68k/m520x.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * m520x.h -- Definitions for Freescale Coldfire 520x - * - * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __M520X__ -#define __M520X__ - -/* *** System Control Module (SCM) *** */ -#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) -#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) -#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) -#define MPROT_MTR 4 -#define MPROT_MTW 2 -#define MPROT_MPL 1 - -#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) -#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) -#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) - -#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) - -#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) -#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) -#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) -#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) -#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) -#define SCM_PACRC_PACR23(x) ((x) & 0x0F) - -#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) -#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) -#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) -#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) -#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) -#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) -#define SCM_PACRD_PACR31(x) ((x) & 0x0F) - -#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) -#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) -#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) -#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) -#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) - -#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) -#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) -#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) - -#define PACR_SP 4 -#define PACR_WP 2 -#define PACR_TP 1 - -#define SCM_BMT_BME (0x00000008) -#define SCM_BMT_BMT_MASK (0x07) -#define SCM_BMT_BMT(x) ((x) & 0x07) -#define SCM_BMT_BMT1024 (0x0000) -#define SCM_BMT_BMT512 (0x0001) -#define SCM_BMT_BMT256 (0x0002) -#define SCM_BMT_BMT128 (0x0003) -#define SCM_BMT_BMT64 (0x0004) -#define SCM_BMT_BMT32 (0x0005) -#define SCM_BMT_BMT16 (0x0006) -#define SCM_BMT_BMT8 (0x0007) - -#define SCM_CWCR_RO (0x8000) -#define SCM_CWCR_CWR_WH (0x0100) -#define SCM_CWCR_CWE (0x0080) -#define SCM_CWRI_WINDOW (0x0060) -#define SCM_CWRI_RESET (0x0040) -#define SCM_CWRI_INT_RESET (0x0020) -#define SCM_CWRI_INT (0x0000) -#define SCM_CWCR_CWT(x) (((x) & 0x001F)) - -#define SCM_ISR_CFEI (0x02) -#define SCM_ISR_CWIC (0x01) - -#define SCM_CFIER_ECFEI (0x01) - -#define SCM_CFLOC_LOC (0x80) - -#define SCM_CFATR_WRITE (0x80) -#define SCM_CFATR_SZ32 (0x20) -#define SCM_CFATR_SZ16 (0x10) -#define SCM_CFATR_SZ08 (0x00) -#define SCM_CFATR_CACHE (0x08) -#define SCM_CFATR_MODE (0x02) -#define SCM_CFATR_TYPE (0x01) - -/* *** Interrupt Controller (INTC) *** */ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT_F1 (1) -#define INT0_LO_EPORT_F4 (2) -#define INT0_LO_EPORT_F7 (3) -#define INT1_LO_PIT0 (4) -#define INT1_LO_PIT1 (5) -/* 6 - 7 rsvd */ -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM_CWIC (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -/* 29 rsvd */ -#define INT0_LO_I2C (30) -#define INT0_LO_QSPI (31) - -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_FEC0_TXF (36) -#define INT0_HI_FEC0_TXB (37) -#define INT0_HI_FEC0_UN (38) -#define INT0_HI_FEC0_RL (39) -#define INT0_HI_FEC0_RXF (40) -#define INT0_HI_FEC0_RXB (41) -#define INT0_HI_FEC0_MII (42) -#define INT0_HI_FEC0_LC (43) -#define INT0_HI_FEC0_HBERR (44) -#define INT0_HI_FEC0_GRA (45) -#define INT0_HI_FEC0_EBERR (46) -#define INT0_HI_FEC0_BABT (47) -#define INT0_HI_FEC0_BABR (48) -/* 49 - 61 rsvd */ -#define INT0_HI_SCMISR_CFEI (62) - -/* *** Reset Controller Module (RCM) *** */ -#define RCM_RCR_SOFTRST (0x80) -#define RCM_RCR_FRCRSTOUT (0x40) - -#define RCM_RSR_SOFT (0x20) -#define RCM_RSR_WDOG (0x10) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_LOL (0x01) - -/* *** Chip Configuration Module (CCM) *** */ -#define CCM_CCR_CSC (0x0200) -#define CCM_CCR_OSCFREQ (0x0080) -#define CCM_CCR_LIMP (0x0040) -#define CCM_CCR_LOAD (0x0020) -#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3) -#define CCM_CCR_OSC_MODE (0x0004) -#define CCM_CCR_PLL_MODE (0x0002) -#define CCM_CCR_RESERVED (0x0001) - -#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) -#define CCM_CIR_PRN(x) ((x) & 0x003F) - -/* *** General Purpose I/O (GPIO) *** */ -#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F) -#define GPIO_PDR_BE(x) ((x) & 0x0F) -#define GPIO_PDR_CS(x) (((x) & 0x07) << 1) -#define GPIO_PDR_FECI2C(x) ((x) & 0x0F) -#define GPIO_PDR_QSPI(x) ((x) & 0x0F) -#define GPIO_PDR_TIMER(x) ((x) & 0x0F) -#define GPIO_PDR_UART(x) ((x) & 0xFF) -#define GPIO_PDR_FECH(x) ((x) & 0xFF) -#define GPIO_PDR_FECL(x) ((x) & 0xFF) - -#define GPIO_PAR_FBCTL_OE (0x10) -#define GPIO_PAR_FBCTL_TA (0x08) -#define GPIO_PAR_FBCTL_RWB (0x04) -#define GPIO_PAR_FBCTL_TS_MASK (0xFC) -#define GPIO_PAR_FBCTL_TS_TS (0x03) -#define GPIO_PAR_FBCTL_TS_DMA (0x02) - -#define GPIO_PAR_BE3 (0x08) -#define GPIO_PAR_BE2 (0x04) -#define GPIO_PAR_BE1 (0x02) -#define GPIO_PAR_BE0 (0x01) - -#define GPIO_PAR_CS3 (0x08) -#define GPIO_PAR_CS2 (0x04) -#define GPIO_PAR_CS1_MASK (0xFC) -#define GPIO_PAR_CS1_CS1 (0x03) -#define GPIO_PAR_CS1_SDCS1 (0x02) - -#define GPIO_PAR_FECI2C_RMII_MASK (0x0F) -#define GPIO_PAR_FECI2C_MDC_MASK (0x3F) -#define GPIO_PAR_FECI2C_MDC_MDC (0xC0) -#define GPIO_PAR_FECI2C_MDC_SCL (0x80) -#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40) -#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF) -#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30) -#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) -#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10) -#define GPIO_PAR_FECI2C_I2C_MASK (0xF0) -#define GPIO_PAR_FECI2C_SCL_MASK (0xF3) -#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) -#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04) -#define GPIO_PAR_FECI2C_SDA_MASK (0xFC) -#define GPIO_PAR_FECI2C_SDA_SDA (0x03) -#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01) - -#define GPIO_PAR_QSPI_PCS2_MASK (0x3F) -#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0) -#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80) -#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40) -#define GPIO_PAR_QSPI_DIN_MASK (0xCF) -#define GPIO_PAR_QSPI_DIN_DIN (0x30) -#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20) -#define GPIO_PAR_QSPI_DIN_U2CTS (0x10) -#define GPIO_PAR_QSPI_DOUT_MASK (0xF3) -#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C) -#define GPIO_PAR_QSPI_DOUT_SDA (0x08) -#define GPIO_PAR_QSPI_SCK_MASK (0xFC) -#define GPIO_PAR_QSPI_SCK_SCK (0x03) -#define GPIO_PAR_QSPI_SCK_SCL (0x02) - -#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6) -#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4) -#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2) -#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TMR_TIN3_MASK (0x3F) -#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0) -#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80) -#define GPIO_PAR_TMR_TIN3_U2CTS (0x40) -#define GPIO_PAR_TMR_TIN2_MASK (0xCF) -#define GPIO_PAR_TMR_TIN2_TIN2 (0x30) -#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20) -#define GPIO_PAR_TMR_TIN2_U2RTS (0x10) -#define GPIO_PAR_TMR_TIN1_MASK (0xF3) -#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C) -#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08) -#define GPIO_PAR_TMR_TIN1_U2RXD (0x04) -#define GPIO_PAR_TMR_TIN0_MASK (0xFC) -#define GPIO_PAR_TMR_TIN0_TIN0 (0x03) -#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02) -#define GPIO_PAR_TMR_TIN0_U2TXD (0x01) - -#define GPIO_PAR_UART1_MASK (0xF03F) -#define GPIO_PAR_UART0_MASK (0xFFC0) -#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF) -#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00) -#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800) -#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400) -#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300) -#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200) -#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100) -#define GPIO_PAR_UART_U1TXD (0x0080) -#define GPIO_PAR_UART_U1RXD (0x0040) -#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF) -#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030) -#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020) -#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010) -#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3) -#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C) -#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008) -#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004) -#define GPIO_PAR_UART_U0TXD (0x0002) -#define GPIO_PAR_UART_U0RXD (0x0001) - -#define GPIO_PAR_FEC_7W_MASK (0xF3) -#define GPIO_PAR_FEC_7W_FEC (0x0C) -#define GPIO_PAR_FEC_7W_U1RTS (0x04) -#define GPIO_PAR_FEC_MII_MASK (0xFC) -#define GPIO_PAR_FEC_MII_FEC (0x03) -#define GPIO_PAR_FEC_MII_UnCTS (0x01) - -#define GPIO_PAR_IRQ_IRQ4 (0x01) - -#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6) -#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4) -#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2) -#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03) -#define GPIO_MSCR_FB_FBCLK_MASK (0x3F) -#define GPIO_MSCR_FB_DUP_MASK (0xCF) -#define GPIO_MSCR_FB_DLO_MASK (0xF3) -#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC) - -#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4) -#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2) -#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03) -#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF) -#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3) -#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC) - -#define MSCR_25VDDR (0x03) -#define MSCR_18VDDR_FULL (0x02) -#define MSCR_OPENDRAIN (0x01) -#define MSCR_18VDDR_HALF (0x00) - -#define GPIO_DSCR_I2C(x) ((x) & 0x03) -#define GPIO_DSCR_I2C_MASK (0xFC) - -#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_MISC_DBG_MASK (0xCF) -#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3) -#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03) -#define GPIO_DSCR_MISC_TIMER_MASK (0xFC) - -#define GPIO_DSCR_FEC(x) ((x) & 0x03) -#define GPIO_DSCR_FEC_MASK (0xFC) - -#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_UART_UART1_MASK (0xCF) -#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_UART_UART0_MASK (0xF3) -#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03) -#define GPIO_DSCR_UART_IRQ_MASK (0xFC) - -#define GPIO_DSCR_QSPI(x) ((x) & 0x03) -#define GPIO_DSCR_QSPI_MASK (0xFC) - -#define DSCR_50PF (0x03) -#define DSCR_30PF (0x02) -#define DSCR_20PF (0x01) -#define DSCR_10PF (0x00) - -/* *** Phase Locked Loop (PLL) *** */ -#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4) -#define PLL_PODR_CPUDIV_MASK (0x0F) -#define PLL_PODR_BUSDIV(x) ((x) & 0x0F) -#define PLL_PODR_BUSDIV_MASK (0xF0) - -#define PLL_PCR_DITHEN (0x80) -#define PLL_PCR_DITHDEV(x) ((x) & 0x07) -#define PLL_PCR_DITHDEV_MASK (0xF8) - -#endif /* __M520X__ */ diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h deleted file mode 100644 index 824d333114..0000000000 --- a/include/asm-m68k/m5227x.h +++ /dev/null @@ -1,565 +0,0 @@ -/* - * MCF5227x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MCF5227X__ -#define __MCF5227X__ - -/* Interrupt Controller (INTC) */ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM_CWIC (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -#define INT0_LO_I2C (30) -#define INT0_LO_DSPI (31) -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_SCMIR (62) -#define INT0_HI_RTC_ISR (63) - -#define INT1_HI_CAN_BOFFINT (1) -#define INT1_HI_CAN_ERRINT (3) -#define INT1_HI_CAN_BUF0I (4) -#define INT1_HI_CAN_BUF1I (5) -#define INT1_HI_CAN_BUF2I (6) -#define INT1_HI_CAN_BUF3I (7) -#define INT1_HI_CAN_BUF4I (8) -#define INT1_HI_CAN_BUF5I (9) -#define INT1_HI_CAN_BUF6I (10) -#define INT1_HI_CAN_BUF7I (11) -#define INT1_HI_CAN_BUF8I (12) -#define INT1_HI_CAN_BUF9I (13) -#define INT1_HI_CAN_BUF10I (14) -#define INT1_HI_CAN_BUF11I (15) -#define INT1_HI_CAN_BUF12I (16) -#define INT1_HI_CAN_BUF13I (17) -#define INT1_HI_CAN_BUF14I (18) -#define INT1_HI_CAN_BUF15I (19) -#define INT1_HI_PIT0_PIF (43) -#define INT1_HI_PIT1_PIF (44) -#define INT1_HI_USBOTG_STS (47) -#define INT1_HI_SSI_ISR (49) -#define INT1_HI_PWM_INT (50) -#define INT1_HI_LCDC_ISR (51) -#define INT1_HI_CCM_UOCSR (53) -#define INT1_HI_DSPI_EOQF (54) -#define INT1_HI_DSPI_TFFF (55) -#define INT1_HI_DSPI_TCF (56) -#define INT1_HI_DSPI_TFUF (57) -#define INT1_HI_DSPI_RFDF (58) -#define INT1_HI_DSPI_RFOF (59) -#define INT1_HI_DSPI_RFOF_TFUF (60) -#define INT1_HI_TOUCH_ADC (61) -#define INT1_HI_PLL_LOCKS (62) - -/********************************************************************* -* Reset Controller Module (RCM) -*********************************************************************/ - -/* Bit definitions and macros for RCR */ -#define RCM_RCR_FRCRSTOUT (0x40) -#define RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for RSR */ -#define RCM_RSR_LOL (0x01) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_SOFT (0x20) - -/********************************************************************* -* Chip Configuration Module (CCM) -*********************************************************************/ - -/* Bit definitions and macros for CCR */ -#define CCM_CCR_DRAMSEL (0x0100) -#define CCM_CCR_CSC_MASK (0xFF3F) -#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) -#define CCM_CCR_CSC_FBCS5_A22 (0x0080) -#define CCM_CCR_CSC_FB_A23_A22 (0x0040) -#define CCM_CCR_LIMP (0x0020) -#define CCM_CCR_LOAD (0x0010) -#define CCM_CCR_BOOTPS_MASK (0xFFF3) -#define CCM_CCR_BOOTPS_PS16 (0x0008) -#define CCM_CCR_BOOTPS_PS8 (0x0004) -#define CCM_CCR_BOOTPS_PS32 (0x0000) -#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) - -/* Bit definitions and macros for RCON */ -#define CCM_RCON_CSC_MASK (0xFF3F) -#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) -#define CCM_RCON_CSC_FBCS5_A22 (0x0080) -#define CCM_RCON_CSC_FB_A23_A22 (0x0040) -#define CCM_RCON_LIMP (0x0020) -#define CCM_RCON_LOAD (0x0010) -#define CCM_RCON_BOOTPS_MASK (0xFFF3) -#define CCM_RCON_BOOTPS_PS16 (0x0008) -#define CCM_RCON_BOOTPS_PS8 (0x0004) -#define CCM_RCON_BOOTPS_PS32 (0x0000) -#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) - -/* Bit definitions and macros for CIR */ -#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ -#define CCM_CIR_PIN_MASK (0xFFC0) -#define CCM_CIR_PRN_MASK (0x003F) -#define CCM_CIR_PIN_MCF52277 (0x0000) - -/* Bit definitions and macros for MISCCR */ -#define CCM_MISCCR_RTCSRC (0x4000) -#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */ -#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ - -#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */ -#define CCM_MISCCR_BMT_65536 (0) -#define CCM_MISCCR_BMT_32768 (1) -#define CCM_MISCCR_BMT_16384 (2) -#define CCM_MISCCR_BMT_8192 (3) -#define CCM_MISCCR_BMT_4096 (4) -#define CCM_MISCCR_BMT_2048 (5) -#define CCM_MISCCR_BMT_1024 (6) -#define CCM_MISCCR_BMT_512 (7) - -#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ -#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ -#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ -#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ -#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */ -#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */ -#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ - -/* Bit definitions and macros for CDR */ -#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12) -#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */ -#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */ - -/* Bit definitions and macros for UOCSR */ -#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */ -#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */ -#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */ -#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */ -#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */ -#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ -#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ -#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ -#define CCM_UOCSR_SEND (0x0010) /* Session end */ -#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ -#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */ -#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */ - -/********************************************************************* -* General Purpose I/O Module (GPIO) -*********************************************************************/ -/* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_MASK (0x0F) -#define GPIO_PAR_BE_BE3_BE3 (0x08) -#define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_BE2 (0x04) -#define GPIO_PAR_BE_BE2_GPIO (0x00) -#define GPIO_PAR_BE_BE1_BE1 (0x02) -#define GPIO_PAR_BE_BE1_GPIO (0x00) -#define GPIO_PAR_BE_BE0_BE0 (0x01) -#define GPIO_PAR_BE_BE0_GPIO (0x00) - -/* Bit definitions and macros for PAR_CS */ -#define GPIO_PAR_CS_CS3 (0x10) -#define GPIO_PAR_CS_CS2 (0x08) -#define GPIO_PAR_CS_CS1_FBCS1 (0x06) -#define GPIO_PAR_CS_CS1_SDCS1 (0x04) -#define GPIO_PAR_CS_CS1_GPIO (0x00) -#define GPIO_PAR_CS_CS0 (0x01) - -/* Bit definitions and macros for PAR_FBCTL */ -#define GPIO_PAR_FBCTL_OE (0x80) -#define GPIO_PAR_FBCTL_TA (0x40) -#define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TS_MASK (0xE7) -#define GPIO_PAR_FBCTL_TS_FBTS (0x18) -#define GPIO_PAR_FBCTL_TS_DMAACK (0x10) -#define GPIO_PAR_FBCTL_TS_GPIO (0x00) - -/* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_I2C_SCL_MASK (0xF3) -#define GPIO_PAR_I2C_SCL_SCL (0x0C) -#define GPIO_PAR_I2C_SCL_CANTXD (0x08) -#define GPIO_PAR_I2C_SCL_U2TXD (0x04) -#define GPIO_PAR_I2C_SCL_GPIO (0x00) - -#define GPIO_PAR_I2C_SDA_MASK (0xFC) -#define GPIO_PAR_I2C_SDA_SDA (0x03) -#define GPIO_PAR_I2C_SDA_CANRXD (0x02) -#define GPIO_PAR_I2C_SDA_U2RXD (0x01) -#define GPIO_PAR_I2C_SDA_GPIO (0x00) - -/* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U1CTS_MASK (0x3FFF) -#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) -#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) -#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) -#define GPIO_PAR_UART_U1CTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U1RTS_MASK (0xCFFF) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) -#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) -#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) -#define GPIO_PAR_UART_U1RTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U1RXD_MASK (0xF3FF) -#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) -#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) -#define GPIO_PAR_UART_U1RXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U1TXD_MASK (0xFCFF) -#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) -#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) -#define GPIO_PAR_UART_U1TXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U0CTS_MASK (0xFF3F) -#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) -#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) -#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) -#define GPIO_PAR_UART_U0CTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U0RTS_MASK (0xFFCF) -#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) -#define GPIO_PAR_UART_U0RTS_T1IN (0x0020) -#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) -#define GPIO_PAR_UART_U0RTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U0RXD_MASK (0xFFF3) -#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) -#define GPIO_PAR_UART_U0RXD_CANRX (0x0008) -#define GPIO_PAR_UART_U0RXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U0TXD_MASK (0xFFFC) -#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) -#define GPIO_PAR_UART_U0TXD_CANTX (0x0002) -#define GPIO_PAR_UART_U0TXD_GPIO (0x0000) - -/* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_PCS0_MASK (0x3F) -#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) -#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) -#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_MASK (0xCF) -#define GPIO_PAR_DSPI_SIN_SIN (0x30) -#define GPIO_PAR_DSPI_SIN_U2RXD (0x20) -#define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_MASK (0xF3) -#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) -#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) -#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_MASK (0xFC) -#define GPIO_PAR_DSPI_SCK_SCK (0x03) -#define GPIO_PAR_DSPI_SCK_U2CTS (0x02) -#define GPIO_PAR_DSPI_SCK_GPIO (0x00) - -/* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) -#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) -#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) -#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) -#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) -#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) -#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) -#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) -#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) -#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) -#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) -#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) -#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) -#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) -#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) -#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) -#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) - -/* Bit definitions and macros for GPIO_PAR_LCDCTL */ -#define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7) -#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) -#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) -#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) -#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04) -#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02) -#define GPIO_PAR_LCDCTL_LSCLK (0x01) - -/* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ4_MASK (0xF3) -#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) -#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) -#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_MASK (0xFC) -#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) -#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) -#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) -#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) - -/* Bit definitions and macros for GPIO_PAR_LCDH */ -#define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF) -#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) -#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) -#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF) -#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) -#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) -#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F) -#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) -#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) -#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF) -#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) -#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) -#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3) -#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) -#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) -#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC) -#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) -#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) -#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) - -/* Bit definitions and macros for GPIO_PAR_LCDL */ -#define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF) -#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) -#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) -#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF) -#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) -#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) -#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF) -#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) -#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) -#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF) -#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) -#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) -#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF) -#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) -#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) -#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF) -#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) -#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) -#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF) -#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) -#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) -#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF) -#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) -#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) -#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF) -#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) -#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) -#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF) -#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) -#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) -#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF) -#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) -#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) -#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF) -#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) -#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) -#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) - -/* Bit definitions and macros for MSCR_FB */ -#define GPIO_MSCR_FB_DUPPER_MASK (0xCF) -#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) -#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) -#define GPIO_MSCR_FB_DUPPER_OD (0x10) -#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) - -#define GPIO_MSCR_FB_DLOWER_MASK (0xF3) -#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) -#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) -#define GPIO_MSCR_FB_DLOWER_OD (0x04) -#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) - -#define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC) -#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) -#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) -#define GPIO_MSCR_FB_ADDRCTL_OD (0x01) -#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) - -/* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF) -#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) -#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) -#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) -#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) - -#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) -#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) -#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) -#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) -#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) - -#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) -#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) -#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) -#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) -#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00) - -/* Bit definitions and macros for Drive Strength Control */ -#define DSCR_LOAD_50PF (0x03) -#define DSCR_LOAD_30PF (0x02) -#define DSCR_LOAD_20PF (0x01) -#define DSCR_LOAD_10PF (0x00) - -/********************************************************************* -* SDRAM Controller (SDRAMC) -*********************************************************************/ - -/* Bit definitions and macros for SDMR */ -#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ -#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ -#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ -#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ -#define SDRAMC_SDMR_BK_LMR (0x00000000) -#define SDRAMC_SDMR_BK_LEMR (0x40000000) - -/* Bit definitions and macros for SDCR */ -#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ -#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ -#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ -#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ -#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ -#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ -#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ -#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ -#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ -#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ -#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ -#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ -#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ -#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) - -/* Bit definitions and macros for SDCFG1 */ -#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ -#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ -#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ -#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ -#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ -#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ -#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ - -/* Bit definitions and macros for SDCFG2 */ -#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ -#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ -#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ -#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ - -/* Bit definitions and macros for SDCS group */ -#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ -#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ -#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) -#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) -#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) - -/********************************************************************* -* Phase Locked Loop (PLL) -*********************************************************************/ - -/* Bit definitions and macros for PCR */ -#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ -#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */ -#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */ -#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ -#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ -#define PLL_PCR_PFDR_MASK (0x000F0000) -#define PLL_PCR_OUTDIV5_MASK (0x000F0000) -#define PLL_PCR_OUTDIV3_MASK (0x00000F00) -#define PLL_PCR_OUTDIV2_MASK (0x000000F0) -#define PLL_PCR_OUTDIV1_MASK (0x0000000F) - -/* Bit definitions and macros for PSR */ -#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ -#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ -#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ -#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ - -/********************************************************************/ - -#endif /* __MCF5227X__ */ diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h deleted file mode 100644 index 22987ac778..0000000000 --- a/include/asm-m68k/m5235.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * mcf5329.h -- Definitions for Freescale Coldfire 5329 - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef mcf5235_h -#define mcf5235_h -/****************************************************************************/ - -/********************************************************************* -* System Control Module (SCM) -*********************************************************************/ - -/* Bit definition and macros for SCM_IPSBAR */ -#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) -#define SCM_IPSBAR_V (0x00000001) - -/* Bit definition and macros for SCM_RAMBAR */ -#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) -#define SCM_RAMBAR_BDE (0x00000200) - -/* Bit definition and macros for SCM_CRSR */ -#define SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for SCM_CWCR */ -#define SCM_CWCR_CWE (0x80) -#define SCM_CWCR_CWRI (0x40) -#define SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define SCM_CWCR_CWTA (0x04) -#define SCM_CWCR_CWTAVAL (0x02) -#define SCM_CWCR_CWTIC (0x01) - -/* Bit definitions and macros for SCM_LPICR */ -#define SCM_LPICR_ENBSTOP (0x80) -#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) -#define SCM_LPICR_XLPM_IPL_ANY (0x00) -#define SCM_LPICR_XLPM_IPL_L2_7 (0x10) -#define SCM_LPICR_XLPM_IPL_L3_7 (0x20) -#define SCM_LPICR_XLPM_IPL_L4_7 (0x30) -#define SCM_LPICR_XLPM_IPL_L5_7 (0x40) -#define SCM_LPICR_XLPM_IPL_L6_7 (0x50) -#define SCM_LPICR_XLPM_IPL_L7 (0x70) - -/* Bit definitions and macros for SCM_DMAREQC */ -#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) -#define SCM_DMAREQC_EXT_ETPU (0x00080000) -#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000) -#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000) -#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000) -#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) -#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) -#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) -#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) -#define SCM_DMAREQC_DMACn_DTMR0 (0x04) -#define SCM_DMAREQC_DMACn_DTMR1 (0x05) -#define SCM_DMAREQC_DMACn_DTMR2 (0x06) -#define SCM_DMAREQC_DMACn_DTMR3 (0x07) -#define SCM_DMAREQC_DMACn_UART0RX (0x08) -#define SCM_DMAREQC_DMACn_UART1RX (0x09) -#define SCM_DMAREQC_DMACn_UART2RX (0x0A) -#define SCM_DMAREQC_DMACn_UART0TX (0x0C) -#define SCM_DMAREQC_DMACn_UART1TX (0x0D) -#define SCM_DMAREQC_DMACn_UART3TX (0x0E) - -/* Bit definitions and macros for SCM_MPARK */ -#define SCM_MPARK_M2_P_EN (0x02000000) -#define SCM_MPARK_M3_PRTY_MSK (0x00C00000) -#define SCM_MPARK_M3_PRTY_4TH (0x00000000) -#define SCM_MPARK_M3_PRTY_3RD (0x00400000) -#define SCM_MPARK_M3_PRTY_2ND (0x00800000) -#define SCM_MPARK_M3_PRTY_1ST (0x00C00000) -#define SCM_MPARK_M2_PRTY_MSK (0x00300000) -#define SCM_MPARK_M2_PRTY_4TH (0x00000000) -#define SCM_MPARK_M2_PRTY_3RD (0x00100000) -#define SCM_MPARK_M2_PRTY_2ND (0x00200000) -#define SCM_MPARK_M2_PRTY_1ST (0x00300000) -#define SCM_MPARK_M0_PRTY_MSK (0x000C0000) -#define SCM_MPARK_M0_PRTY_4TH (0x00000000) -#define SCM_MPARK_M0_PRTY_3RD (0x00040000) -#define SCM_MPARK_M0_PRTY_2ND (0x00080000) -#define SCM_MPARK_M0_PRTY_1ST (0x000C0000) -#define SCM_MPARK_FIXED (0x00004000) -#define SCM_MPARK_TIMEOUT (0x00002000) -#define SCM_MPARK_PRKLAST (0x00001000) -#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) - -/* Bit definitions and macros for SCM_MPR */ -#define SCM_MPR_MPR3 (0x08) -#define SCM_MPR_MPR2 (0x04) -#define SCM_MPR_MPR1 (0x02) -#define SCM_MPR_MPR0 (0x01) - -/* Bit definitions and macros for SCM_PACRn */ -#define SCM_PACRn_LOCK1 (0x80) -#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4) -#define SCM_PACRn_LOCK0 (0x08) -#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) - -/* Bit definitions and macros for SCM_GPACR */ -#define SCM_PACRn_LOCK (0x80) -#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) - -/********************************************************************* -* SDRAM Controller (SDRAMC) -*********************************************************************/ -/* Bit definitions and macros for SDRAMC_DCR */ -#define SDRAMC_DCR_NAM (0x2000) -#define SDRAMC_DCR_COC (0x1000) -#define SDRAMC_DCR_IS (0x0800) -#define SDRAMC_DCR_RTIM_MASK (0x0C00) -#define SDRAMC_DCR_RTIM_3CLKS (0x0000) -#define SDRAMC_DCR_RTIM_6CLKS (0x0200) -#define SDRAMC_DCR_RTIM_9CLKS (0x0400) -#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8) - -/* Bit definitions and macros for SDRAMC_DARCn */ -#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18) -#define SDRAMC_DARCn_RE (0x00008000) -#define SDRAMC_DARCn_CASL_MASK (0x00003000) -#define SDRAMC_DARCn_CASL_C0 (0x00000000) -#define SDRAMC_DARCn_CASL_C1 (0x00001000) -#define SDRAMC_DARCn_CASL_C2 (0x00002000) -#define SDRAMC_DARCn_CASL_C3 (0x00003000) -#define SDRAMC_DARCn_CBM_MASK (0x00000700) -#define SDRAMC_DARCn_CBM_CMD17 (0x00000000) -#define SDRAMC_DARCn_CBM_CMD18 (0x00000100) -#define SDRAMC_DARCn_CBM_CMD19 (0x00000200) -#define SDRAMC_DARCn_CBM_CMD20 (0x00000300) -#define SDRAMC_DARCn_CBM_CMD21 (0x00000400) -#define SDRAMC_DARCn_CBM_CMD22 (0x00000500) -#define SDRAMC_DARCn_CBM_CMD23 (0x00000600) -#define SDRAMC_DARCn_CBM_CMD24 (0x00000700) -#define SDRAMC_DARCn_IMRS (0x00000040) -#define SDRAMC_DARCn_PS_MASK (0x00000030) -#define SDRAMC_DARCn_PS_32 (0x00000000) -#define SDRAMC_DARCn_PS_16 (0x00000010) -#define SDRAMC_DARCn_PS_8 (0x00000020) -#define SDRAMC_DARCn_IP (0x00000008) - -/* Bit definitions and macros for SDRAMC_DMRn */ -#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18) -#define SDRAMC_DMRn_WP (0x00000100) -#define SDRAMC_DMRn_V (0x00000001) - -/********************************************************************* -* Interrupt Controller (INTC) -*********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_SCM (8) -#define INT0_LO_DMA0 (9) -#define INT0_LO_DMA1 (10) -#define INT0_LO_DMA2 (11) -#define INT0_LO_DMA3 (12) -#define INT0_LO_UART0 (13) -#define INT0_LO_UART1 (14) -#define INT0_LO_UART2 (15) -#define INT0_LO_RSVD1 (16) -#define INT0_LO_I2C (17) -#define INT0_LO_QSPI (18) -#define INT0_LO_DTMR0 (19) -#define INT0_LO_DTMR1 (20) -#define INT0_LO_DTMR2 (21) -#define INT0_LO_DTMR3 (22) -#define INT0_LO_FEC_TXF (23) -#define INT0_LO_FEC_TXB (24) -#define INT0_LO_FEC_UN (25) -#define INT0_LO_FEC_RL (26) -#define INT0_LO_FEC_RXF (27) -#define INT0_LO_FEC_RXB (28) -#define INT0_LO_FEC_MII (29) -#define INT0_LO_FEC_LC (30) -#define INT0_LO_FEC_HBERR (31) -#define INT0_HI_FEC_GRA (32) -#define INT0_HI_FEC_EBERR (33) -#define INT0_HI_FEC_BABT (34) -#define INT0_HI_FEC_BABR (35) -#define INT0_HI_PIT0 (36) -#define INT0_HI_PIT1 (37) -#define INT0_HI_PIT2 (38) -#define INT0_HI_PIT3 (39) -#define INT0_HI_RNG (40) -#define INT0_HI_SKHA (41) -#define INT0_HI_MDHA (42) -#define INT0_HI_CAN1_BUF0I (43) -#define INT0_HI_CAN1_BUF1I (44) -#define INT0_HI_CAN1_BUF2I (45) -#define INT0_HI_CAN1_BUF3I (46) -#define INT0_HI_CAN1_BUF4I (47) -#define INT0_HI_CAN1_BUF5I (48) -#define INT0_HI_CAN1_BUF6I (49) -#define INT0_HI_CAN1_BUF7I (50) -#define INT0_HI_CAN1_BUF8I (51) -#define INT0_HI_CAN1_BUF9I (52) -#define INT0_HI_CAN1_BUF10I (53) -#define INT0_HI_CAN1_BUF11I (54) -#define INT0_HI_CAN1_BUF12I (55) -#define INT0_HI_CAN1_BUF13I (56) -#define INT0_HI_CAN1_BUF14I (57) -#define INT0_HI_CAN1_BUF15I (58) -#define INT0_HI_CAN1_ERRINT (59) -#define INT0_HI_CAN1_BOFFINT (60) -/* 60-63 Reserved */ - -/* 0 - 7 Reserved */ -#define INT1_LO_CAN1_BUF0I (8) -#define INT1_LO_CAN1_BUF1I (9) -#define INT1_LO_CAN1_BUF2I (10) -#define INT1_LO_CAN1_BUF3I (11) -#define INT1_LO_CAN1_BUF4I (12) -#define INT1_LO_CAN1_BUF5I (13) -#define INT1_LO_CAN1_BUF6I (14) -#define INT1_LO_CAN1_BUF7I (15) -#define INT1_LO_CAN1_BUF8I (16) -#define INT1_LO_CAN1_BUF9I (17) -#define INT1_LO_CAN1_BUF10I (18) -#define INT1_LO_CAN1_BUF11I (19) -#define INT1_LO_CAN1_BUF12I (20) -#define INT1_LO_CAN1_BUF13I (21) -#define INT1_LO_CAN1_BUF14I (22) -#define INT1_LO_CAN1_BUF15I (23) -#define INT1_LO_CAN1_ERRINT (24) -#define INT1_LO_CAN1_BOFFINT (25) -/* 26 Reserved */ -#define INT1_LO_ETPU_TC0F (27) -#define INT1_LO_ETPU_TC1F (28) -#define INT1_LO_ETPU_TC2F (29) -#define INT1_LO_ETPU_TC3F (30) -#define INT1_LO_ETPU_TC4F (31) -#define INT1_HI_ETPU_TC5F (32) -#define INT1_HI_ETPU_TC6F (33) -#define INT1_HI_ETPU_TC7F (34) -#define INT1_HI_ETPU_TC8F (35) -#define INT1_HI_ETPU_TC9F (36) -#define INT1_HI_ETPU_TC10F (37) -#define INT1_HI_ETPU_TC11F (38) -#define INT1_HI_ETPU_TC12F (39) -#define INT1_HI_ETPU_TC13F (40) -#define INT1_HI_ETPU_TC14F (41) -#define INT1_HI_ETPU_TC15F (42) -#define INT1_HI_ETPU_TC16F (43) -#define INT1_HI_ETPU_TC17F (44) -#define INT1_HI_ETPU_TC18F (45) -#define INT1_HI_ETPU_TC19F (46) -#define INT1_HI_ETPU_TC20F (47) -#define INT1_HI_ETPU_TC21F (48) -#define INT1_HI_ETPU_TC22F (49) -#define INT1_HI_ETPU_TC23F (50) -#define INT1_HI_ETPU_TC24F (51) -#define INT1_HI_ETPU_TC25F (52) -#define INT1_HI_ETPU_TC26F (53) -#define INT1_HI_ETPU_TC27F (54) -#define INT1_HI_ETPU_TC28F (55) -#define INT1_HI_ETPU_TC29F (56) -#define INT1_HI_ETPU_TC30F (57) -#define INT1_HI_ETPU_TC31F (58) -#define INT1_HI_ETPU_TGIF (59) - -/********************************************************************* -* General Purpose I/O (GPIO) -*********************************************************************/ -/* Bit definitions and macros for GPIO_PODR */ -#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5) -#define GPIO_PODR_ADDR_MASK (0xE0) -#define GPIO_PODR_BS(x) ((x)&0x0F) -#define GPIO_PODR_BS_MASK (0x0F) -#define GPIO_PODR_CS(x) (((x)&0x7F)<<1) -#define GPIO_PODR_CS_MASK (0xFE) -#define GPIO_PODR_SDRAM(X) ((x)&0x3F) -#define GPIO_PODR_SDRAM_MASK (0x3F) -#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x) -#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK -#define GPIO_PODR_UARTH(x) ((x)&0x03) -#define GPIO_PODR_UARTH_MASK (0x03) -#define GPIO_PODR_QSPI(x) ((x)&0x1F) -#define GPIO_PODR_QSPI_MASK (0x1F) -#define GPIO_PODR_ETPU(x) ((x)&0x07) -#define GPIO_PODR_ETPU_MASK (0x07) - -/* Bit definitions and macros for GPIO_PDDR */ -#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x) -#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK -#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x) -#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK -#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x) -#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK -#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X) -#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK -#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x) -#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK -#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x) -#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK -#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x) -#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK -#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x) -#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK - -/* Bit definitions and macros for GPIO_PPDSDR */ -#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x) -#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK -#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x) -#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK -#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x) -#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK -#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X) -#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK -#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x) -#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK -#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x) -#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK -#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x) -#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK -#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x) -#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK - -/* Bit definitions and macros for GPIO_PCLRR */ -#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x) -#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK -#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x) -#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK -#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x) -#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK -#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X) -#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK -#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x) -#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK -#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x) -#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK -#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x) -#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK -#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x) -#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK - -/* Bit definitions and macros for GPIO_PAR */ -#define GPIO_PAR_AD_ADDR23 (0x80) -#define GPIO_PAR_AD_ADDR22 (0x40) -#define GPIO_PAR_AD_ADDR21 (0x20) -#define GPIO_PAR_AD_DATAL (0x01) -#define GPIO_PAR_BUSCTL_OE (0x4000) -#define GPIO_PAR_BUSCTL_TA (0x1000) -#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10) -#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00) -#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400) -#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800) -#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00) -#define GPIO_PAR_BUSCTL_RWB (0x0100) -#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040) -#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010) -#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2) -#define GPIO_PAR_BUSCTL_TS_MASK (0x0C) -#define GPIO_PAR_BUSCTL_TS_GPIO (0x04) -#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08) -#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C) -#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03) -#define GPIO_PAR_BUSCTL_TIP_MASK (0x03) -#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01) -#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02) -#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03) -#define GPIO_PAR_BS(x) ((x)&0x0F) -#define GPIO_PAR_BS_MASK (0x0F) -#define GPIO_PAR_CS(x) (((x)&0x7F)<<1) -#define GPIO_PAR_CS_MASK (0xFE) -#define GPIO_PAR_CS_CS7 (0x80) -#define GPIO_PAR_CS_CS6 (0x40) -#define GPIO_PAR_CS_CS5 (0x20) -#define GPIO_PAR_CS_CS4 (0x10) -#define GPIO_PAR_CS_CS3 (0x08) -#define GPIO_PAR_CS_CS2 (0x04) -#define GPIO_PAR_CS_CS1 (0x02) -#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3 -#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2 -#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6) -#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0) -#define GPIO_PAR_SDRAM_SDWE (0x20) -#define GPIO_PAR_SDRAM_SCAS (0x10) -#define GPIO_PAR_SDRAM_SRAS (0x08) -#define GPIO_PAR_SDRAM_SCKE (0x04) -#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03) -#define GPIO_PAR_SDRAM_SDCS_MASK (0x03) -#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6) -#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0) -#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40) -#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80) -#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0) -#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4) -#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30) -#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10) -#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20) -#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30) -#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) -#define GPIO_PAR_FECI2C_SCL_MASK (0x0C) -#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08) -#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C) -#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03) -#define GPIO_PAR_FECI2C_SDA_MASK (0x03) -#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02) -#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03) -#define GPIO_PAR_UART_DREQ2 (0x8000) -#define GPIO_PAR_UART_CAN1EN (0x4000) -#define GPIO_PAR_UART_U2RXD (0x2000) -#define GPIO_PAR_UART_U2TXD (0x1000) -#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10) -#define GPIO_PAR_UART_U1RXD_MASK (0x0C00) -#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800) -#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) -#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8) -#define GPIO_PAR_UART_U1TXD_MASK (0x0300) -#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200) -#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) -#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6) -#define GPIO_PAR_UART_U1CTS_MASK (0x00C0) -#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080) -#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0) -#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4) -#define GPIO_PAR_UART_U1RTS_MASK (0x0030) -#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030) -#define GPIO_PAR_UART_U0RXD (0x0008) -#define GPIO_PAR_UART_U0TXD (0x0004) -#define GPIO_PAR_UART_U0CTS (0x0002) -#define GPIO_PAR_UART_U0RTS (0x0001) -#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6) -#define GPIO_PAR_QSPI_CS1_MASK (0xC0) -#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80) -#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0) -#define GPIO_PAR_QSPI_CS0 (0x20) -#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3) -#define GPIO_PAR_QSPI_DIN_MASK (0x18) -#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10) -#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18) -#define GPIO_PAR_QSPI_DOUT (0x04) -#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03) -#define GPIO_PAR_QSPI_SCK_MASK (0x03) -#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02) -#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03) -#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14) -#define GPIO_PAR_DT3IN_MASK (0xC000) -#define GPIO_PAR_DT3IN_QSPICS2 (0x4000) -#define GPIO_PAR_DT3IN_U2CTS (0x8000) -#define GPIO_PAR_DT3IN_DT3IN (0xC000) -#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12) -#define GPIO_PAR_DT2IN_MASK (0x3000) -#define GPIO_PAR_DT2IN_DT2OUT (0x1000) -#define GPIO_PAR_DT2IN_DREQ2 (0x2000) -#define GPIO_PAR_DT2IN_DT2IN (0x3000) -#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10) -#define GPIO_PAR_DT1IN_MASK (0x0C00) -#define GPIO_PAR_DT1IN_DT1OUT (0x0400) -#define GPIO_PAR_DT1IN_DREQ1 (0x0800) -#define GPIO_PAR_DT1IN_DT1IN (0x0C00) -#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8) -#define GPIO_PAR_DT0IN_MASK (0x0300) -#define GPIO_PAR_DT0IN_DREQ0 (0x0200) -#define GPIO_PAR_DT0IN_DT0IN (0x0300) -#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6) -#define GPIO_PAR_DT3OUT_MASK (0x00C0) -#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040) -#define GPIO_PAR_DT3OUT_U2RTS (0x0080) -#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0) -#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4) -#define GPIO_PAR_DT2OUT_MASK (0x0030) -#define GPIO_PAR_DT2OUT_DACK2 (0x0020) -#define GPIO_PAR_DT2OUT_DT2OUT (0x0030) -#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2) -#define GPIO_PAR_DT1OUT_MASK (0x000C) -#define GPIO_PAR_DT1OUT_DACK1 (0x0008) -#define GPIO_PAR_DT1OUT_DT1OUT (0x000C) -#define GPIO_PAR_DT0OUT(x) ((x)&0x03) -#define GPIO_PAR_DT0OUT_MASK (0x0003) -#define GPIO_PAR_DT0OUT_DACK0 (0x0002) -#define GPIO_PAR_DT0OUT_DT0OUT (0x0003) -#define GPIO_PAR_ETPU_TCRCLK (0x04) -#define GPIO_PAR_ETPU_UTPU_ODIS (0x02) -#define GPIO_PAR_ETPU_LTPU_ODIS (0x01) - -/* Bit definitions and macros for GPIO_DSCR */ -#define GPIO_DSCR_EIM_EIM1 (0x10) -#define GPIO_DSCR_EIM_EIM0 (0x01) -#define GPIO_DSCR_ETPU_ETPU31_24 (0x40) -#define GPIO_DSCR_ETPU_ETPU23_16 (0x10) -#define GPIO_DSCR_ETPU_ETPU15_8 (0x04) -#define GPIO_DSCR_ETPU_ETPU7_0 (0x01) -#define GPIO_DSCR_FECI2C_FEC (0x10) -#define GPIO_DSCR_FECI2C_I2C (0x01) -#define GPIO_DSCR_UART_IRQ (0x40) -#define GPIO_DSCR_UART_UART2 (0x10) -#define GPIO_DSCR_UART_UART1 (0x04) -#define GPIO_DSCR_UART_UART0 (0x01) -#define GPIO_DSCR_QSPI_QSPI (0x01) -#define GPIO_DSCR_TIMER (0x01) - -/********************************************************************* -* Chip Configuration Module (CCM) -*********************************************************************/ -/* Bit definitions and macros for CCM_RCR */ -#define CCM_RCR_SOFTRST (0x80) -#define CCM_RCR_FRCRSTOUT (0x40) - -/* Bit definitions and macros for CCM_RSR */ -#define CCM_RSR_SOFT (0x20) -#define CCM_RSR_WDR (0x10) -#define CCM_RSR_POR (0x08) -#define CCM_RSR_EXT (0x04) -#define CCM_RSR_LOC (0x02) -#define CCM_RSR_LOL (0x01) - -/* Bit definitions and macros for CCM_CCR */ -#define CCM_CCR_LOAD (0x8000) -#define CCM_CCR_SZEN (0x0040) -#define CCM_CCR_PSTEN (0x0020) -#define CCM_CCR_BME (0x0008) -#define CCM_CCR_BMT(x) ((x)&0x07) -#define CCM_CCR_BMT_MASK (0x0007) -#define CCM_CCR_BMT_64K (0x0000) -#define CCM_CCR_BMT_32K (0x0001) -#define CCM_CCR_BMT_16K (0x0002) -#define CCM_CCR_BMT_8K (0x0003) -#define CCM_CCR_BMT_4K (0x0004) -#define CCM_CCR_BMT_2K (0x0005) -#define CCM_CCR_BMT_1K (0x0006) -#define CCM_CCR_BMT_512 (0x0007) - -/* Bit definitions and macros for CCM_RCON */ -#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8) -#define CCM_RCON_RLOAD (0x0020) -#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define CCM_RCON_BOOTPS_MASK (0x0018) -#define CCM_RCON_BOOTPS_32 (0x0018) -#define CCM_RCON_BOOTPS_16 (0x0008) -#define CCM_RCON_BOOTPS_8 (0x0010) -#define CCM_RCON_MODE (0x0001) - -/* Bit definitions and macros for CCM_CIR */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) -#define CCM_CIR_PRN(x) ((x)&0x003F) - -/********************************************************************* -* PLL Clock Module -*********************************************************************/ -/* Bit definitions and macros for PLL_SYNCR */ -#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24) -#define PLL_SYNCR_MFD_MASK (0x07000000) -#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19) -#define PLL_SYNCR_RFC_MASK (0x00380000) -#define PLL_SYNCR_LOCEN (0x00040000) -#define PLL_SYNCR_LOLRE (0x00020000) -#define PLL_SYNCR_LOCRE (0x00010000) -#define PLL_SYNCR_DISCLK (0x00008000) -#define PLL_SYNCR_LOLIRQ (0x00004000) -#define PLL_SYNCR_LOCIRQ (0x00002000) -#define PLL_SYNCR_RATE (0x00001000) -#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10) -#define PLL_SYNCR_EXP(x) ((x)&0x03FF) - -/* Bit definitions and macros for PLL_SYNSR */ -#define PLL_SYNSR_LOLF (0x00000200) -#define PLL_SYNSR_LOC (0x00000100) -#define PLL_SYNSR_MODE (0x00000080) -#define PLL_SYNSR_PLLSEL (0x00000040) -#define PLL_SYNSR_PLLREF (0x00000020) -#define PLL_SYNSR_LOCKS (0x00000010) -#define PLL_SYNSR_LOCK (0x00000008) -#define PLL_SYNSR_LOCF (0x00000004) -#define PLL_SYNSR_CALDONE (0x00000002) -#define PLL_SYNSR_CALPASS (0x00000001) - -/********************************************************************* -* Watchdog Timer Modules (WTM) -*********************************************************************/ -/* Bit definitions and macros for WTM_WCR */ -#define WTM_WCR_WAIT (0x0008) -#define WTM_WCR_DOZE (0x0004) -#define WTM_WCR_HALTED (0x0002) -#define WTM_WCR_EN (0x0001) - -#endif /* mcf5235_h */ diff --git a/include/asm-m68k/m5301x.h b/include/asm-m68k/m5301x.h deleted file mode 100644 index 80cefc40aa..0000000000 --- a/include/asm-m68k/m5301x.h +++ /dev/null @@ -1,608 +0,0 @@ -/* - * m5301x.h -- Definitions for Freescale Coldfire 5301x - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef m5301x_h -#define m5301x_h - -/* *** System Control Module (SCM) *** */ -#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) -#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) -#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) -#define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12) -#define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8) -#define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4) -#define MPROT_MTR 4 -#define MPROT_MTW 2 -#define MPROT_MPL 1 - -#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) -#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) -#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) -#define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8) - -#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) -#define SCM_PACRB_PACR13(x) (((x) & 0x0F) << 8) - -#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) -#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) -#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) -#define SCM_PACRC_PACR19(x) (((x) & 0x0F) << 16) -#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) -#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) -#define SCM_PACRC_PACR23(x) ((x) & 0x0F) - -#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) -#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) -#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) -#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) -#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) -#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) -#define SCM_PACRD_PACR31(x) ((x) & 0x0F) - -#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) -#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) -#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) -#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) -#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) -#define SCM_PACRE_PACR37(x) (((x) & 0x0F) << 8) -#define SCM_PACRE_PACR39(x) ((x) & 0x0F) - -#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) -#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) -#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) -#define SCM_PACRF_PACR43(x) (((x) & 0x0F) << 16) -#define SCM_PACRF_PACR44(x) (((x) & 0x0F) << 12) -#define SCM_PACRF_PACR45(x) (((x) & 0x0F) << 8) -#define SCM_PACRF_PACR46(x) (((x) & 0x0F) << 4) -#define SCM_PACRF_PACR47(x) ((x) & 0x0F) - -#define SCM_PACRG_PACR48(x) (((x) & 0x0F) << 28) -#define SCM_PACRG_PACR49(x) (((x) & 0x0F) << 24) -#define SCM_PACRG_PACR50(x) (((x) & 0x0F) << 20) -#define SCM_PACRG_PACR51(x) (((x) & 0x0F) << 16) - -#define PACR_SP 4 -#define PACR_WP 2 -#define PACR_TP 1 - -#define SCM_CWCR_RO (0x8000) -#define SCM_CWCR_CWR_WH (0x0100) -#define SCM_CWCR_CWE (0x0080) -#define SCM_CWCR_CWRI_WINDOW (0x0060) -#define SCM_CWCR_CWRI_RESET (0x0040) -#define SCM_CWCR_CWRI_INT_RESET (0x0020) -#define SCM_CWCR_CWRI_INT (0x0000) -#define SCM_CWCR_CWT(x) (((x) & 0x001F)) - -#define SCM_ISR_CFEI (0x02) -#define SCM_ISR_CWIC (0x01) - -#define BCR_GBR (0x00000200) -#define BCR_GBW (0x00000100) -#define BCR_S7 (0x00000080) -#define BCR_S6 (0x00000040) -#define BCR_S4 (0x00000010) -#define BCR_S1 (0x00000002) - -#define SCM_CFIER_ECFEI (0x01) - -#define SCM_CFLOC_LOC (0x80) - -#define SCM_CFATR_WRITE (0x80) -#define SCM_CFATR_SZ32 (0x20) -#define SCM_CFATR_SZ16 (0x10) -#define SCM_CFATR_SZ08 (0x00) -#define SCM_CFATR_CACHE (0x08) -#define SCM_CFATR_MODE (0x02) -#define SCM_CFATR_TYPE (0x01) - -/* *** Interrupt Controller (INTC) *** */ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM_CWIC (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -#define INT0_LO_RSVD1 (29) -#define INT0_LO_I2C (30) -#define INT0_LO_DSPI (31) -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_FEC0_TXF (36) -#define INT0_HI_FEC0_TXB (37) -#define INT0_HI_FEC0_UN (38) -#define INT0_HI_FEC0_RL (39) -#define INT0_HI_FEC0_RXF (40) -#define INT0_HI_FEC0_RXB (41) -#define INT0_HI_FEC0_MII (42) -#define INT0_HI_FEC0_LC (43) -#define INT0_HI_FEC0_HBERR (44) -#define INT0_HI_FEC0_GRA (45) -#define INT0_HI_FEC0_EBERR (46) -#define INT0_HI_FEC0_BABT (47) -#define INT0_HI_FEC0_BABR (48) -#define INT0_HI_FEC1_TXF (49) -#define INT0_HI_FEC1_TXB (50) -#define INT0_HI_FEC1_UN (51) -#define INT0_HI_FEC1_RL (52) -#define INT0_HI_FEC1_RXF (53) -#define INT0_HI_FEC1_RXB (54) -#define INT0_HI_FEC1_MII (55) -#define INT0_HI_FEC1_LC (56) -#define INT0_HI_FEC1_HBERR (57) -#define INT0_HI_FEC1_GRA (58) -#define INT0_HI_FEC1_EBERR (59) -#define INT0_HI_FEC1_BABT (60) -#define INT0_HI_FEC1_BABR (61) -#define INT0_HI_SCM_CFEI (62) - -/* 0 - 24 reserved */ -#define INT1_LO_EPORT1_FLAG0 (25) -#define INT1_LO_EPORT1_FLAG1 (26) -#define INT1_LO_EPORT1_FLAG2 (27) -#define INT1_LO_EPORT1_FLAG3 (28) -#define INT1_LO_EPORT1_FLAG4 (29) -#define INT1_LO_EPORT1_FLAG5 (30) -#define INT1_LO_EPORT1_FLAG6 (31) -#define INT1_LO_EPORT1_FLAG7 (32) -#define INT1_HI_DSPI_EOQF (33) -#define INT1_HI_DSPI_TFFF (34) -#define INT1_HI_DSPI_TCF (35) -#define INT1_HI_DSPI_TFUF (36) -#define INT1_HI_DSPI_RFDF (37) -#define INT1_HI_DSPI_RFOF (38) -#define INT1_HI_DSPI_RFOF_TFUF (39) -#define INT1_HI_RNG_EI (40) -#define INT1_HI_PLL_LOCF (41) -#define INT1_HI_PLL_LOLF (42) -#define INT1_HI_PIT0 (43) -#define INT1_HI_PIT1 (44) -#define INT1_HI_PIT2 (45) -#define INT1_HI_PIT3 (46) -#define INT1_HI_USBOTG_STS (47) -#define INT1_HI_USBHOST_STS (48) -#define INT1_HI_SSI (49) -/* 50 - 51 reserved */ -#define INT1_HI_RTC (52) -#define INT1_HI_CCM_USBSTAT (53) -#define INT1_HI_CODEC_OR (54) -#define INT1_HI_CODEC_RF_TE (55) -#define INT1_HI_CODEC_ROE (56) -#define INT1_HI_CODEC_TUE (57) -/* 58 reserved */ -#define INT1_HI_SIM1_DATA (59) -#define INT1_HI_SIM1_GENERAL (60) -/* 61 - 62 reserved */ -#define INT1_HI_SDHC (63) - -/* *** Reset Controller Module (RCM) *** */ -#define RCM_RCR_SOFTRST (0x80) -#define RCM_RCR_FRCRSTOUT (0x40) - -#define RCM_RSR_SOFT (0x20) -#define RCM_RSR_LOC (0x10) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_LOL (0x01) - -/* *** Chip Configuration Module (CCM) *** */ -#define CCM_CCR_CSC (0x0020) -#define CCM_CCR_BOOTPS (0x0010) -#define CCM_CCR_LOAD (0x0008) -#define CCM_CCR_OSC_MODE (0x0004) -#define CCM_CCR_SDR_MODE (0x0002) -#define CCM_CCR_RESERVED (0x0001) - -#define CCM_RCON_SDR_32BIT_UNIFIED (0x0012) -#define CCM_RCON_DDR_8BIT_SPLIT (0x0010) -#define CCM_RCON_SDR_16BIT_UNIFIED (0x0002) -#define CCM_RCON_DDR_16BIT_SPLIT (0x0000) - -#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) -#define CCM_CIR_PRN(x) ((x) & 0x003F) - -#define CCM_MISCCR_FECM (0x8000) -#define CCM_MISCCR_CDCSRC (0x4000) -#define CCM_MISCCR_PLL_LOCK (0x2000) -#define CCM_MISCCR_LIMP (0x1000) -#define CCM_MISCCR_BME (0x8000) -#define CCM_MISCCR_BMT_MASK (0xF8FF) -#define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) -#define CCM_MISCCR_BMT_512 (0x0700) -#define CCM_MISCCR_BMT_1024 (0x0600) -#define CCM_MISCCR_BMT_2048 (0x0500) -#define CCM_MISCCR_BMT_4096 (0x0400) -#define CCM_MISCCR_BMT_8192 (0x0300) -#define CCM_MISCCR_BMT_16384 (0x0200) -#define CCM_MISCCR_BMT_32768 (0x0100) -#define CCM_MISCCR_BMT_65536 (0x0000) -#define CCM_MISCCR_TIM_DMA (0x0020) -#define CCM_MISCCR_SSI_SRC (0x0010) -#define CCM_MISCCR_USBH_OC (0x0008) -#define CCM_MISCCR_USBO_OC (0x0004) -#define CCM_MISCCR_USB_PUE (0x0002) -#define CCM_MISCCR_USB_SRC (0x0001) - -#define CCM_CDR_LPDIV(x) (((x) & 0x0F) << 8) -#define CCM_CDR_SSIDIV(x) ((x) & 0xFF) - -#define CCM_UOCSR_DPPD (0x2000) -#define CCM_UOCSR_DMPD (0x1000) -#define CCM_UOCSR_DRV_VBUS (0x0800) -#define CCM_UOCSR_CRG_VBUS (0x0400) -#define CCM_UOCSR_DCR_VBUS (0x0200) -#define CCM_UOCSR_DPPU (0x0100) -#define CCM_UOCSR_AVLD (0x0080) -#define CCM_UOCSR_BVLD (0x0040) -#define CCM_UOCSR_VVLD (0x0020) -#define CCM_UOCSR_SEND (0x0010) -#define CCM_UOCSR_PWRFLT (0x0008) -#define CCM_UOCSR_WKUP (0x0004) -#define CCM_UOCSR_UOMIE (0x0002) -#define CCM_UOCSR_XPDE (0x0001) - -#define CCM_UHCSR_PORTIND(x) (((x) & 0x0003) << 14) -#define CCM_UHCSR_DRV_VBUS (0x0010) -#define CCM_UHCSR_PWRFLT (0x0008) -#define CCM_UHCSR_WKUP (0x0004) -#define CCM_UHCSR_UHMIE (0x0002) -#define CCM_UHCSR_XPDE (0x0001) - -#define CCM_CODCR_BGREN (0x8000) -#define CCM_CODCR_REGEN (0x0080) - -#define CCM_MISC2_IGNLL (0x0008) -#define CCM_MISC2_DPS (0x0001) - -/* *** General Purpose I/O (GPIO) *** */ -#define GPIO_PDR_FBCTL ((x) & 0x0F) -#define GPIO_PDR_BE ((x) & 0x0F) -#define GPIO_PDR_CS32 (((x) & 0x03) << 4) -#define GPIO_PDR_CS10 (((x) & 0x03) << 4) -#define GPIO_PDR_DSPI ((x) & 0x7F) -#define GPIO_PDR_FEC0 ((x) & 0x7F) -#define GPIO_PDR_FECI2C ((x) & 0x3F) -#define GPIO_PDR_SIMP1 ((x) & 0x1F) -#define GPIO_PDR_SIMP0 ((x) & 0x1F) -#define GPIO_PDR_TIMER ((x) & 0x0F) -#define GPIO_PDR_UART ((x) & 0x3F) -#define GPIO_PDR_DEBUG (0x01) -#define GPIO_PDR_SDHC ((x) & 0x3F) -#define GPIO_PDR_SSI ((x) & 0x1F) - -#define GPIO_PAR_FBCTL_OE (0x80) -#define GPIO_PAR_FBCTL_TA (0x40) -#define GPIO_PAR_FBCTL_RWB (0x20) -#define GPIO_PAR_FBCTL_TS (0x18) - -#define GPIO_PAR_BE3 (0x40) -#define GPIO_PAR_BE2 (0x10) -#define GPIO_PAR_BE1 (0x04) -#define GPIO_PAR_BE0 (0x01) - -#define GPIO_PAR_CS5 (0x40) -#define GPIO_PAR_CS4 (0x10) -#define GPIO_PAR_CS1_MASK (0xF3) -#define GPIO_PAR_CS1_CS1 (0x0C) -#define GPIO_PAR_CS1_SDCS1 (0x08) -#define GPIO_PAR_CS0_MASK (0xFC) -#define GPIO_PAR_CS0_CS0 (0x03) -#define GPIO_PAR_CS0_CS4 (0x02) - -#define GPIO_PAR_DSPIH_SIN_MASK (0x3F) -#define GPIO_PAR_DSPIH_SIN (0xC0) -#define GPIO_PAR_DSPIH_SIN_U2RXD (0x80) -#define GPIO_PAR_DSPIH_SOUT_MASK (0xCF) -#define GPIO_PAR_DSPIH_SOUT (0x30) -#define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20) -#define GPIO_PAR_DSPIH_SCK_MASK (0xF3) -#define GPIO_PAR_DSPIH_SCK (0x0C) -#define GPIO_PAR_DSPIH_SCK_U2CTS (0x08) -#define GPIO_PAR_DSPIH_PCS0_MASK (0xFC) -#define GPIO_PAR_DSPIH_PCS0 (0x03) -#define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02) - -#define GPIO_PAR_DSPIL_PCS1_MASK (0x3F) -#define GPIO_PAR_DSPIL_PCS1 (0xC0) -#define GPIO_PAR_DSPIL_PCS2_MASK (0xCF) -#define GPIO_PAR_DSPIL_PCS2 (0x30) -#define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20) -#define GPIO_PAR_DSPIL_PCS3_MASK (0xF3) -#define GPIO_PAR_DSPIL_PCS3 (0x0C) -#define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08) - -#define GPIO_PAR_FEC1_7W_FEC (0x40) -#define GPIO_PAR_FEC1_RMII_FEC (0x10) -#define GPIO_PAR_FEC0_7W_FEC (0x04) -#define GPIO_PAR_FEC0_RMII_FEC (0x01) - -/* GPIO_PAR_FECI2C */ -#define GPIO_PAR_FECI2C_RMII0_MASK (0x3F) -#define GPIO_PAR_FECI2C_MDC0 (0x80) -#define GPIO_PAR_FECI2C_MDIO0 (0x40) -#define GPIO_PAR_FECI2C_RMII1_MASK (0xCF) -#define GPIO_PAR_FECI2C_MDC1 (0x20) -#define GPIO_PAR_FECI2C_MDIO1 (0x10) -#define GPIO_PAR_FECI2C_SDA_MASK (0xF3) -#define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2) -#define GPIO_PAR_FECI2C_SDA_SDA (0x0C) -#define GPIO_PAR_FECI2C_SDA_U2TXD (0x08) -#define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04) -#define GPIO_PAR_FECI2C_SCL_MASK (0xFC) -#define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03) -#define GPIO_PAR_FECI2C_SCL_SCL (0x03) -#define GPIO_PAR_FECI2C_SCL_U2RXD (0x02) -#define GPIO_PAR_FECI2C_SCL_MDC1 (0x01) - -#define GPIO_PAR_IRQ0H_IRQ07_MASK (0x3F) -#define GPIO_PAR_IRQ0H_IRQ06_MASK (0xCF) -#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10) -#define GPIO_PAR_IRQ0H_IRQ04_MASK (0xFC) -#define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02) - -#define GPIO_PAR_IRQ0L_IRQ01_MASK (0xF3) -#define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08) - -#define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40) -#define GPIO_PAR_IRQ1H_IRQ16_DDATA2 (0x10) -#define GPIO_PAR_IRQ1H_IRQ15_DDATA1 (0x04) -#define GPIO_PAR_IRQ1H_IRQ14_DDATA0 (0x01) - -#define GPIO_PAR_IRQ1L_IRQ13_PST3 (0x40) -#define GPIO_PAR_IRQ1L_IRQ12_PST2 (0x10) -#define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04) -#define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01) - -#define GPIO_PAR_SIMP1H_DATA1_MASK (0x3F) -#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0) -#define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80) -#define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40) -#define GPIO_PAR_SIMP1H_VEN1_MASK (0xCF) -#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30) -#define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20) -#define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10) -#define GPIO_PAR_SIMP1H_RST1_MASK (0xF3) -#define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C) -#define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08) -#define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04) -#define GPIO_PAR_SIMP1H_PD1_MASK (0xFC) -#define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03) -#define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02) -#define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01) - -#define GPIO_PAR_SIMP1L_CLK_MASK (0x3F) -#define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0) -#define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80) - -#define GPIO_PAR_SIMP0_DATA0 (0x10) -#define GPIO_PAR_SIMP0_VEN0 (0x08) -#define GPIO_PAR_SIMP0_RST0 (0x04) -#define GPIO_PAR_SIMP0_PD0 (0x02) -#define GPIO_PAR_SIMP0_CLK0 (0x01) - -#define GPIO_PAR_TIN3(x) (((x) & 0x03) << 6) -#define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4) -#define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2) -#define GPIO_PAR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TIN3_MASK (0x3F) -#define GPIO_PAR_TIN3_TIN3 (0xC0) -#define GPIO_PAR_TIN3_TOUT3 (0x80) -#define GPIO_PAR_TIN3_IRQ03 (0x40) -#define GPIO_PAR_TIN2_MASK (0xCF) -#define GPIO_PAR_TIN2_TIN2 (0x30) -#define GPIO_PAR_TIN2_TOUT2 (0x20) -#define GPIO_PAR_TIN2_IRQ02 (0x10) -#define GPIO_PAR_TIN1_MASK (0xF3) -#define GPIO_PAR_TIN1_TIN1 (0x0C) -#define GPIO_PAR_TIN1_TOUT1 (0x08) -#define GPIO_PAR_TIN1_DACK1 (0x04) -#define GPIO_PAR_TIN0_MASK (0xFC) -#define GPIO_PAR_TIN0_TIN0 (0x03) -#define GPIO_PAR_TIN0_TOUT0 (0x02) -#define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01) - -#define GPIO_PAR_UART_U2TXD (0x80) -#define GPIO_PAR_UART_U2RXD (0x40) -#define GPIO_PAR_UART_U0TXD (0x20) -#define GPIO_PAR_UART_U0RXD (0x10) -#define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2) -#define GPIO_PAR_UART_CTS0(x) ((x) & 0x03) -#define GPIO_PAR_UART_RTS0_MASK (0xF3) -#define GPIO_PAR_UART_RTS0_U0RTS (0x0C) -#define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08) -#define GPIO_PAR_UART_CTS0_MASK (0xFC) -#define GPIO_PAR_UART_CTS0_U0CTS (0x03) -#define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02) -#define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01) - -#define GPIO_PAR_DEBUG_ALLPST (0x80) - -#define GPIO_PAR_SDHC_DATA3 (0x20) -#define GPIO_PAR_SDHC_DATA2 (0x10) -#define GPIO_PAR_SDHC_DATA1 (0x08) -#define GPIO_PAR_SDHC_DATA0 (0x04) -#define GPIO_PAR_SDHC_CMD (0x02) -#define GPIO_PAR_SDHC_CLK (0x01) - -#define GPIO_PAR_SSIH_RXD(x) (((x) & 0x03) << 6) -#define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4) -#define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2) -#define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03) -#define GPIO_PAR_SSIH_RXD_MASK (0x3F) -#define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0) -#define GPIO_PAR_SSIH_RXD_U1RXD (0x40) -#define GPIO_PAR_SSIH_TXD_MASK (0xCF) -#define GPIO_PAR_SSIH_TXD_SSIRXD (0x30) -#define GPIO_PAR_SSIH_TXD_U1TXD (0x10) -#define GPIO_PAR_SSIH_FS_MASK (0xF3) -#define GPIO_PAR_SSIH_FS_SSIFS (0x0C) -#define GPIO_PAR_SSIH_FS_U1RTS (0x04) -#define GPIO_PAR_SSIH_MCLK_MASK (0xFC) -#define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03) -#define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01) - -#define GPIO_PAR_SSIL_MASK (0x3F) -#define GPIO_PAR_SSIL_BCLK (0xC0) -#define GPIO_PAR_SSIL_U1CTS (0x40) - -#define GPIO_MSCR_MSCR1(x) (((x) & 0x07) << 5) -#define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5) -#define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5) -#define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5) -#define GPIO_MSCR_MSCRn_MASK (0x1F) -#define GPIO_MSCR_MSCRn_SDR (0xE0) -#define GPIO_MSCR_MSCRn_25VDDR (0x60) -#define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20) -#define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00) - -#define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2) -#define GPIO_MSCR_MSCR5_MASK (0xE3) -#define GPIO_MSCR_MSCR5_SDR (0x1C) -#define GPIO_MSCR_MSCR5_25VDDR (0x0C) -#define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04) -#define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00) - -#define GPIO_SRCR_DSPI_MASK (0xFC) -#define GPIO_SRCR_DSPI(x) ((x) & 0x03) -#define GPIO_SRCR_I2C_MASK (0xFC) -#define GPIO_SRCR_I2C(x) ((x) & 0x03) -#define GPIO_SRCR_IRQ_IRQ0_MASK (0xF3) -#define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_IRQ_IRQ1DBG_MASK (0xFC) -#define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03) -#define GPIO_SRCR_SIM_SIMP0_MASK (0xF3) -#define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_SIM_SIMP1_MASK (0xFC) -#define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03) -#define GPIO_SRCR_TIMER_MASK (0xFC) -#define GPIO_SRCR_TIMER(x) ((x) & 0x03) -#define GPIO_SRCR_UART2_MASK (0xF3) -#define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_UART0_MASK (0xFC) -#define GPIO_SRCR_UART0(x) ((x) & 0x03) -#define GPIO_SRCR_SDHC_MASK (0xFC) -#define GPIO_SRCR_SDHC(x) ((x) & 0x03) -#define GPIO_SRCR_SSI_MASK (0xFC) -#define GPIO_SRCR_SSI(x) ((x) & 0x03) - -#define SRCR_HIGHEST (0x03) -#define SRCR_HIGH (0x02) -#define SRCR_LOW (0x01) -#define SRCR_LOWEST (0x00) - -#define GPIO_DSCR_FEC_RMIICLK_MASK (0xCF) -#define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_FEC_RMII0_MASK (0xF3) -#define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_FEC_RMII1_MASK (0xFC) -#define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03) - -#define DSCR_50PF (0x03) -#define DSCR_30PF (0x02) -#define DSCR_20PF (0x01) -#define DSCR_10PF (0x00) - -#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN (0x80) -#define GPIO_PCRH_SIM_VEN1_PULLUP_EN (0x40) -#define GPIO_PCRH_SIM_VEN1_PULLUP (0x20) -#define GPIO_PCRH_SIM_DATA1_PULLUP_EN (0x10) -#define GPIO_PCRH_SIM_DATA1_PULLUP (0x08) -#define GPIO_PCRH_SSI_PULLUP_EN (0x02) -#define GPIO_PCRH_SSI_PULLUP (0x01) - -#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN (0x80) -#define GPIO_PCRL_SDHC_DATA3_PULLUP (0x40) -#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN (0x20) -#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN (0x10) -#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN (0x08) -#define GPIO_PCRL_SDHC_CMD_PULLUP_EN (0x04) - -/* *** Phase Locked Loop (PLL) *** */ -#define PLL_PCR_LOC_IRQ (0x00040000) -#define PLL_PCR_LOC_RE (0x00020000) -#define PLL_PCR_LOC_EN (0x00010000) -#define PLL_PCR_LOL_IRQ (0x00004000) -#define PLL_PCR_LOL_RE (0x00002000) -#define PLL_PCR_LOL_EN (0x00001000) -#define PLL_PCR_REFDIV_MASK (0xFFFFF8FF) -#define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8) -#define PLL_PCR_FBDIV_MASK (0xFFFFFFC0) -#define PLL_PCR_FBDIV(x) ((x) & 0x3F) - -#define PLL_PDR_OUTDIV4_MASK (0x0FFF) -#define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12) -#define PLL_PDR_OUTDIV3_MASK (0xF0FF) -#define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8) -#define PLL_PDR_OUTDIV2_MASK (0xFF0F) -#define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4) -#define PLL_PDR_OUTDIV1_MASK (0xFFF0) -#define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F) -#define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x) -#define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x) -#define PLL_PDR_FB(x) PLL_PDR_OUTDIV2(x) -#define PLL_PDR_CPU(x) PLL_PDR_OUTDIV1(x) - -#define PLL_PSR_LOCF (0x00000200) -#define PLL_PSR_LOC (0x00000100) -#define PLL_PSR_LOLF (0x00000040) -#define PLL_PSR_LOCKS (0x00000020) -#define PLL_PSR_LOCK (0x00000010) -#define PLL_PSR_MODE(x) ((x) & 0x07) - -/* *** Real Time Clock *** */ -#define RTC_OCEN_OSCBYP (0x00000010) -#define RTC_OCEN_CLKEN (0x00000008) - -/* SDRAM */ -#define SDRAMC_SDCR_CKE (0x40000000) -#define SDRAMC_SDCR_REF (0x10000000) - -#endif /* m5301x_h */ diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h deleted file mode 100644 index 596662191c..0000000000 --- a/include/asm-m68k/m5445x.h +++ /dev/null @@ -1,904 +0,0 @@ -/* - * MCF5445x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MCF5445X__ -#define __MCF5445X__ - -/********************************************************************* -* Interrupt Controller (INTC) -*********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -#define INT0_LO_RSVD1 (29) -#define INT0_LO_I2C (30) -#define INT0_LO_QSPI (31) -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_FEC0_TXF (36) -#define INT0_HI_FEC0_TXB (37) -#define INT0_HI_FEC0_UN (38) -#define INT0_HI_FEC0_RL (39) -#define INT0_HI_FEC0_RXF (40) -#define INT0_HI_FEC0_RXB (41) -#define INT0_HI_FEC0_MII (42) -#define INT0_HI_FEC0_LC (43) -#define INT0_HI_FEC0_HBERR (44) -#define INT0_HI_FEC0_GRA (45) -#define INT0_HI_FEC0_EBERR (46) -#define INT0_HI_FEC0_BABT (47) -#define INT0_HI_FEC0_BABR (48) -#define INT0_HI_FEC1_TXF (49) -#define INT0_HI_FEC1_TXB (50) -#define INT0_HI_FEC1_UN (51) -#define INT0_HI_FEC1_RL (52) -#define INT0_HI_FEC1_RXF (53) -#define INT0_HI_FEC1_RXB (54) -#define INT0_HI_FEC1_MII (55) -#define INT0_HI_FEC1_LC (56) -#define INT0_HI_FEC1_HBERR (57) -#define INT0_HI_FEC1_GRA (58) -#define INT0_HI_FEC1_EBERR (59) -#define INT0_HI_FEC1_BABT (60) -#define INT0_HI_FEC1_BABR (61) -#define INT0_HI_SCMIR (62) -#define INT0_HI_RTC_ISR (63) - -#define INT1_HI_DSPI_EOQF (33) -#define INT1_HI_DSPI_TFFF (34) -#define INT1_HI_DSPI_TCF (35) -#define INT1_HI_DSPI_TFUF (36) -#define INT1_HI_DSPI_RFDF (37) -#define INT1_HI_DSPI_RFOF (38) -#define INT1_HI_DSPI_RFOF_TFUF (39) -#define INT1_HI_RNG_EI (40) -#define INT1_HI_PIT0_PIF (43) -#define INT1_HI_PIT1_PIF (44) -#define INT1_HI_PIT2_PIF (45) -#define INT1_HI_PIT3_PIF (46) -#define INT1_HI_USBOTG_USBSTS (47) -#define INT1_HI_SSI_ISR (49) -#define INT1_HI_CCM_UOCSR (53) -#define INT1_HI_ATA_ISR (54) -#define INT1_HI_PCI_SCR (55) -#define INT1_HI_PCI_ASR (56) -#define INT1_HI_PLL_LOCKS (57) - -/********************************************************************* -* Watchdog Timer Modules (WTM) -*********************************************************************/ - -/* Bit definitions and macros for WCR */ -#define WTM_WCR_EN (0x0001) -#define WTM_WCR_HALTED (0x0002) -#define WTM_WCR_DOZE (0x0004) -#define WTM_WCR_WAIT (0x0008) - -/********************************************************************* -* Serial Boot Facility (SBF) -*********************************************************************/ - -/* Bit definitions and macros for SBFCR */ -#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ -#define SBF_SBFCR_FR (0x0010) /* Fast read */ - -/********************************************************************* -* Reset Controller Module (RCM) -*********************************************************************/ - -/* Bit definitions and macros for RCR */ -#define RCM_RCR_FRCRSTOUT (0x40) -#define RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for RSR */ -#define RCM_RSR_LOL (0x01) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_SOFT (0x20) - -/********************************************************************* -* Chip Configuration Module (CCM) -*********************************************************************/ - -/* Bit definitions and macros for CCR_360 */ -#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ -#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ -#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ -#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ -#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ -#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ -#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ -#define CCM_CCR_360_FBCONFIG_MASK (0x00E0) -#define CCM_CCR_360_PLLMULT2_MASK (0x0003) -#define CCM_CCR_360_PLLMULT3_MASK (0x0007) -#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) -#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) -#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) -#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) -#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) -#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) -#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) -#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) -#define CCM_CCR_360_PLLMULT2_12X (0x0000) -#define CCM_CCR_360_PLLMULT2_6X (0x0001) -#define CCM_CCR_360_PLLMULT2_16X (0x0002) -#define CCM_CCR_360_PLLMULT2_8X (0x0003) -#define CCM_CCR_360_PLLMULT3_20X (0x0000) -#define CCM_CCR_360_PLLMULT3_10X (0x0001) -#define CCM_CCR_360_PLLMULT3_24X (0x0002) -#define CCM_CCR_360_PLLMULT3_18X (0x0003) -#define CCM_CCR_360_PLLMULT3_12X (0x0004) -#define CCM_CCR_360_PLLMULT3_6X (0x0005) -#define CCM_CCR_360_PLLMULT3_16X (0x0006) -#define CCM_CCR_360_PLLMULT3_8X (0x0007) - -/* Bit definitions and macros for CCR_256 */ -#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ -#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ -#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ -#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ -#define CCM_CCR_256_FBCONFIG_MASK (0x00E0) -#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) -#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) -#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) -#define CCM_CCR_256_FBCONFIG_M_32 (0x0080) -#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) -#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) -#define CCM_CCR_256_PLLMULT3_MASK (0x0007) -#define CCM_CCR_256_PLLMULT3_20X (0x0000) -#define CCM_CCR_256_PLLMULT3_10X (0x0001) -#define CCM_CCR_256_PLLMULT3_24X (0x0002) -#define CCM_CCR_256_PLLMULT3_18X (0x0003) -#define CCM_CCR_256_PLLMULT3_12X (0x0004) -#define CCM_CCR_256_PLLMULT3_6X (0x0005) -#define CCM_CCR_256_PLLMULT3_16X (0x0006) -#define CCM_CCR_256_PLLMULT3_8X (0x0007) - -/* Bit definitions and macros for RCON_360 */ -#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ -#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ -#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ -#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ -#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ - -/* Bit definitions and macros for RCON_256 */ -#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ -#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ -#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ -#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ - -/* Bit definitions and macros for CIR */ -#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ -#define CCM_CIR_PIN_MASK (0xFFC0) -#define CCM_CIR_PRN_MASK (0x003F) -#define CCM_CIR_PIN_MCF54450 (0x4F<<6) -#define CCM_CIR_PIN_MCF54451 (0x4D<<6) -#define CCM_CIR_PIN_MCF54452 (0x4B<<6) -#define CCM_CIR_PIN_MCF54453 (0x49<<6) -#define CCM_CIR_PIN_MCF54454 (0x4A<<6) -#define CCM_CIR_PIN_MCF54455 (0x48<<6) - -/* Bit definitions and macros for MISCCR */ -#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ -#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ -#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ -#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ -#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ -#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ -#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ -#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ -#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ -#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ -#define CCM_MISCCR_BMT_65536 (0) -#define CCM_MISCCR_BMT_32768 (1) -#define CCM_MISCCR_BMT_16384 (2) -#define CCM_MISCCR_BMT_8192 (3) -#define CCM_MISCCR_BMT_4096 (4) -#define CCM_MISCCR_BMT_2048 (5) -#define CCM_MISCCR_BMT_1024 (6) -#define CCM_MISCCR_BMT_512 (7) -#define CCM_MISCCR_SSIPUS_UP (1) -#define CCM_MISCCR_SSIPUS_DOWN (0) -#define CCM_MISCCR_TIMDMA_TIM (1) -#define CCM_MISCCR_TIMDMA_SSI (0) -#define CCM_MISCCR_SSISRC_CLKIN (0) -#define CCM_MISCCR_SSISRC_PLL (1) -#define CCM_MISCCR_USBOC_ACTHI (0) -#define CCM_MISCCR_USBOV_ACTLO (1) -#define CCM_MISCCR_USBSRC_CLKIN (0) -#define CCM_MISCCR_USBSRC_PLL (1) - -/* Bit definitions and macros for CDR */ -#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ -#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ - -/* Bit definitions and macros for UOCSR */ -#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ -#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ -#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ -#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ -#define CCM_UOCSR_SEND (0x0010) /* Session end */ -#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ -#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ -#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ -#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ -#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ -#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ -#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ -#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ - -/********************************************************************* -* General Purpose I/O Module (GPIO) -*********************************************************************/ - -/* Bit definitions and macros for PAR_FEC */ -#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) -#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) -#define GPIO_PAR_FEC_FEC1_MASK (0x8F) -#define GPIO_PAR_FEC_FEC1_MII (0x70) -#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) -#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) -#define GPIO_PAR_FEC_FEC1_ATA (0x10) -#define GPIO_PAR_FEC_FEC1_GPIO (0x00) -#define GPIO_PAR_FEC_FEC0_MASK (0xF8) -#define GPIO_PAR_FEC_FEC0_MII (0x07) -#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) -#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) -#define GPIO_PAR_FEC_FEC0_ULPI (0x01) -#define GPIO_PAR_FEC_FEC0_GPIO (0x00) - -/* Bit definitions and macros for PAR_DMA */ -#define GPIO_PAR_DMA_DREQ0 (0x01) -#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) -#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) -#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) -#define GPIO_PAR_DMA_DACK1_MASK (0x3F) -#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) -#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) -#define GPIO_PAR_DMA_DACK1_GPIO (0x00) -#define GPIO_PAR_DMA_DREQ1_MASK (0xCF) -#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) -#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) -#define GPIO_PAR_DMA_DREQ1_GPIO (0x00) -#define GPIO_PAR_DMA_DACK0_MASK (0xF3) -#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) -#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) -#define GPIO_PAR_DMA_DACK0_GPIO (0x00) -#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) -#define GPIO_PAR_DMA_DREQ0_GPIO (0x00) - -/* Bit definitions and macros for PAR_FBCTL */ -#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) -#define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TA (0x40) -#define GPIO_PAR_FBCTL_OE (0x80) -#define GPIO_PAR_FBCTL_OE_OE (0x80) -#define GPIO_PAR_FBCTL_OE_GPIO (0x00) -#define GPIO_PAR_FBCTL_TA_TA (0x40) -#define GPIO_PAR_FBCTL_TA_GPIO (0x00) -#define GPIO_PAR_FBCTL_RW_RW (0x20) -#define GPIO_PAR_FBCTL_RW_GPIO (0x00) -#define GPIO_PAR_FBCTL_TS_MASK (0xE7) -#define GPIO_PAR_FBCTL_TS_TS (0x18) -#define GPIO_PAR_FBCTL_TS_ALE (0x10) -#define GPIO_PAR_FBCTL_TS_TBST (0x08) -#define GPIO_PAR_FBCTL_TS_GPIO (0x80) - -/* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_SCK (0x01) -#define GPIO_PAR_DSPI_SOUT (0x02) -#define GPIO_PAR_DSPI_SIN (0x04) -#define GPIO_PAR_DSPI_PCS0 (0x08) -#define GPIO_PAR_DSPI_PCS1 (0x10) -#define GPIO_PAR_DSPI_PCS2 (0x20) -#define GPIO_PAR_DSPI_PCS5 (0x40) -#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) -#define GPIO_PAR_DSPI_PCS5_GPIO (0x00) -#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) -#define GPIO_PAR_DSPI_PCS2_GPIO (0x00) -#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) -#define GPIO_PAR_DSPI_PCS1_GPIO (0x00) -#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) -#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_SIN (0x04) -#define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_SOUT (0x02) -#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_SCK (0x01) -#define GPIO_PAR_DSPI_SCK_GPIO (0x00) - -/* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_BS0 (0x01) -#define GPIO_PAR_BE_BS1 (0x04) -#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) -#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) -#define GPIO_PAR_BE_BE3_MASK (0x3F) -#define GPIO_PAR_BE_BE3_BE3 (0xC0) -#define GPIO_PAR_BE_BE3_TSIZ1 (0x80) -#define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_MASK (0xCF) -#define GPIO_PAR_BE_BE2_BE2 (0x30) -#define GPIO_PAR_BE_BE2_TSIZ0 (0x20) -#define GPIO_PAR_BE_BE2_GPIO (0x00) -#define GPIO_PAR_BE_BE1_BE1 (0x04) -#define GPIO_PAR_BE_BE1_GPIO (0x00) -#define GPIO_PAR_BE_BE0_BE0 (0x01) -#define GPIO_PAR_BE_BE0_GPIO (0x00) - -/* Bit definitions and macros for PAR_CS */ -#define GPIO_PAR_CS_CS1 (0x02) -#define GPIO_PAR_CS_CS2 (0x04) -#define GPIO_PAR_CS_CS3 (0x08) -#define GPIO_PAR_CS_CS3_CS3 (0x08) -#define GPIO_PAR_CS_CS3_GPIO (0x00) -#define GPIO_PAR_CS_CS2_CS2 (0x04) -#define GPIO_PAR_CS_CS2_GPIO (0x00) -#define GPIO_PAR_CS_CS1_CS1 (0x02) -#define GPIO_PAR_CS_CS1_GPIO (0x00) - -/* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) -#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) -#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) -#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) -#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) -#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) -#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) -#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) -#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) -#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) -#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) -#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) -#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) -#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) -#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) -#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) -#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) -#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) -#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) -#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) -#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) - -/* Bit definitions and macros for PAR_USB */ -#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) -#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) -#define GPIO_PAR_USB_VBUSEN_MASK (0xF3) -#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) -#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) -#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) -#define GPIO_PAR_USB_VBUSEN_GPIO (0x00) -#define GPIO_PAR_USB_VBUSOC_MASK (0xFC) -#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) -#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) -#define GPIO_PAR_USB_VBUSOC_GPIO (0x00) - -/* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U0TXD (0x01) -#define GPIO_PAR_UART_U0RXD (0x02) -#define GPIO_PAR_UART_U0RTS (0x04) -#define GPIO_PAR_UART_U0CTS (0x08) -#define GPIO_PAR_UART_U1TXD (0x10) -#define GPIO_PAR_UART_U1RXD (0x20) -#define GPIO_PAR_UART_U1RTS (0x40) -#define GPIO_PAR_UART_U1CTS (0x80) -#define GPIO_PAR_UART_U1CTS_U1CTS (0x80) -#define GPIO_PAR_UART_U1CTS_GPIO (0x00) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x40) -#define GPIO_PAR_UART_U1RTS_GPIO (0x00) -#define GPIO_PAR_UART_U1RXD_U1RXD (0x20) -#define GPIO_PAR_UART_U1RXD_GPIO (0x00) -#define GPIO_PAR_UART_U1TXD_U1TXD (0x10) -#define GPIO_PAR_UART_U1TXD_GPIO (0x00) -#define GPIO_PAR_UART_U0CTS_U0CTS (0x08) -#define GPIO_PAR_UART_U0CTS_GPIO (0x00) -#define GPIO_PAR_UART_U0RTS_U0RTS (0x04) -#define GPIO_PAR_UART_U0RTS_GPIO (0x00) -#define GPIO_PAR_UART_U0RXD_U0RXD (0x02) -#define GPIO_PAR_UART_U0RXD_GPIO (0x00) -#define GPIO_PAR_UART_U0TXD_U0TXD (0x01) -#define GPIO_PAR_UART_U0TXD_GPIO (0x00) - -/* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) -#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) -#define GPIO_PAR_FECI2C_MDIO0 (0x0010) -#define GPIO_PAR_FECI2C_MDC0 (0x0040) -#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) -#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) -#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) -#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) -#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) -#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) -#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) -#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) -#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) -#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) -#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) -#define GPIO_PAR_FECI2C_SCL_SCL (0x000C) -#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) -#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) -#define GPIO_PAR_FECI2C_SDA_SDA (0x0003) -#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) -#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) - -/* Bit definitions and macros for PAR_SSI */ -#define GPIO_PAR_SSI_MCLK (0x0001) -#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) -#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) -#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) -#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) -#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF) -#define GPIO_PAR_SSI_BCLK_BCLK (0x0300) -#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) -#define GPIO_PAR_SSI_BCLK_GPIO (0x0000) -#define GPIO_PAR_SSI_FS_MASK (0xFF3F) -#define GPIO_PAR_SSI_FS_FS (0x00C0) -#define GPIO_PAR_SSI_FS_U1RTS (0x0080) -#define GPIO_PAR_SSI_FS_GPIO (0x0000) -#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF) -#define GPIO_PAR_SSI_SRXD_SRXD (0x0030) -#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) -#define GPIO_PAR_SSI_SRXD_GPIO (0x0000) -#define GPIO_PAR_SSI_STXD_MASK (0xFFF3) -#define GPIO_PAR_SSI_STXD_STXD (0x000C) -#define GPIO_PAR_SSI_STXD_U1TXD (0x0008) -#define GPIO_PAR_SSI_STXD_GPIO (0x0000) -#define GPIO_PAR_SSI_MCLK_MCLK (0x0001) -#define GPIO_PAR_SSI_MCLK_GPIO (0x0000) - -/* Bit definitions and macros for PAR_ATA */ -#define GPIO_PAR_ATA_IORDY (0x0001) -#define GPIO_PAR_ATA_DMARQ (0x0002) -#define GPIO_PAR_ATA_RESET (0x0004) -#define GPIO_PAR_ATA_DA0 (0x0020) -#define GPIO_PAR_ATA_DA1 (0x0040) -#define GPIO_PAR_ATA_DA2 (0x0080) -#define GPIO_PAR_ATA_CS0 (0x0100) -#define GPIO_PAR_ATA_CS1 (0x0200) -#define GPIO_PAR_ATA_BUFEN (0x0400) -#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) -#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) -#define GPIO_PAR_ATA_CS1_CS1 (0x0200) -#define GPIO_PAR_ATA_CS1_GPIO (0x0000) -#define GPIO_PAR_ATA_CS0_CS0 (0x0100) -#define GPIO_PAR_ATA_CS0_GPIO (0x0000) -#define GPIO_PAR_ATA_DA2_DA2 (0x0080) -#define GPIO_PAR_ATA_DA2_GPIO (0x0000) -#define GPIO_PAR_ATA_DA1_DA1 (0x0040) -#define GPIO_PAR_ATA_DA1_GPIO (0x0000) -#define GPIO_PAR_ATA_DA0_DA0 (0x0020) -#define GPIO_PAR_ATA_DA0_GPIO (0x0000) -#define GPIO_PAR_ATA_RESET_RESET (0x0004) -#define GPIO_PAR_ATA_RESET_GPIO (0x0000) -#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) -#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) -#define GPIO_PAR_ATA_IORDY_IORDY (0x0001) -#define GPIO_PAR_ATA_IORDY_GPIO (0x0000) - -/* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ1 (0x02) -#define GPIO_PAR_IRQ_IRQ4 (0x10) -#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) -#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) -#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) - -/* Bit definitions and macros for PAR_PCI */ -#define GPIO_PAR_PCI_REQ0 (0x0001) -#define GPIO_PAR_PCI_REQ1 (0x0004) -#define GPIO_PAR_PCI_REQ2 (0x0010) -#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) -#define GPIO_PAR_PCI_GNT0 (0x0100) -#define GPIO_PAR_PCI_GNT1 (0x0400) -#define GPIO_PAR_PCI_GNT2 (0x1000) -#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) -#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF) -#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) -#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) -#define GPIO_PAR_PCI_GNT3_GPIO (0x0000) -#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) -#define GPIO_PAR_PCI_GNT2_GPIO (0x0000) -#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) -#define GPIO_PAR_PCI_GNT1_GPIO (0x0000) -#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) -#define GPIO_PAR_PCI_GNT0_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F) -#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) -#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) -#define GPIO_PAR_PCI_REQ3_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) -#define GPIO_PAR_PCI_REQ2_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) -#define GPIO_PAR_PCI_REQ1_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) -#define GPIO_PAR_PCI_REQ0_GPIO (0x0000) - -/* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) -#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) -#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) -#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) -#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) -#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) -#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) -#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) -#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) -#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) -#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) -#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) -#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) -#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) -#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) -#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) -#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) -#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) -#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) -#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) -#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) - -/* Bit definitions and macros for MSCR_PCI */ -#define GPIO_MSCR_PCI_PCI (0x01) -#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) -#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) - -/* Bit definitions and macros for DSCR_I2C */ -#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) -#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) -#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) -#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) -#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_FLEXBUS */ -#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) -#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) -#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) -#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) -#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) -#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) -#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) -#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) -#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) -#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) -#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) -#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) -#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) -#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) -#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) -#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) -#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) -#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) -#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) -#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_FEC */ -#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) -#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) -#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) -#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) -#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) -#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) -#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) -#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) -#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) -#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_UART */ -#define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) -#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) -#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) -#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) -#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) -#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) -#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) -#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) -#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) -#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_DSPI */ -#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) -#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) -#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) -#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) -#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_TIMER */ -#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) -#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) -#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) -#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) -#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_SSI */ -#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) -#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) -#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) -#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) -#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_DMA */ -#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) -#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) -#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) -#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) -#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_DEBUG */ -#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) -#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) -#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) -#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) -#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_RESET */ -#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) -#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) -#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) -#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) -#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_IRQ */ -#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) -#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) -#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) -#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) -#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_USB */ -#define GPIO_DSCR_USB_USB(x) (((x)&0x03)) -#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) -#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) -#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) -#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) - -/* Bit definitions and macros for DSCR_ATA */ -#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) -#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) -#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) -#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) -#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) - -/********************************************************************* -* SDRAM Controller (SDRAMC) -*********************************************************************/ - -/* Bit definitions and macros for SDMR */ -#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ -#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ -#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ -#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ -#define SDRAMC_SDMR_BK_LMR (0x00000000) -#define SDRAMC_SDMR_BK_LEMR (0x40000000) - -/* Bit definitions and macros for SDCR */ -#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ -#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ -#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ -#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ -#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ -#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ -#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ -#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ -#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ -#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ -#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ -#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ -#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ -#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) - -/* Bit definitions and macros for SDCFG1 */ -#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ -#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ -#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ -#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ -#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ -#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ -#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ - -/* Bit definitions and macros for SDCFG2 */ -#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ -#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ -#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ -#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ - -/* Bit definitions and macros for SDCS group */ -#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ -#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ -#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) -#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) -#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) - -/********************************************************************* -* Phase Locked Loop (PLL) -*********************************************************************/ - -/* Bit definitions and macros for PCR */ -#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ -#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ -#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ -#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ -#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ -#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ -#define PLL_PCR_PFDR_MASK (0x000F0000) -#define PLL_PCR_OUTDIV5_MASK (0x000F0000) -#define PLL_PCR_OUTDIV4_MASK (0x0000F000) -#define PLL_PCR_OUTDIV3_MASK (0x00000F00) -#define PLL_PCR_OUTDIV2_MASK (0x000000F0) -#define PLL_PCR_OUTDIV1_MASK (0x0000000F) - -/* Bit definitions and macros for PSR */ -#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ -#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ -#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ -#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ - -/********************************************************************* -* PCI -*********************************************************************/ - -/* Bit definitions and macros for SCR */ -#define PCI_SCR_PE (0x80000000) /* Parity Error detected */ -#define PCI_SCR_SE (0x40000000) /* System error signalled */ -#define PCI_SCR_MA (0x20000000) /* Master aboart received */ -#define PCI_SCR_TR (0x10000000) /* Target abort received */ -#define PCI_SCR_TS (0x08000000) /* Target abort signalled */ -#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ -#define PCI_SCR_DP (0x01000000) /* Master data parity err */ -#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ -#define PCI_SCR_R (0x00400000) /* Reserved */ -#define PCI_SCR_66M (0x00200000) /* 66Mhz */ -#define PCI_SCR_C (0x00100000) /* Capabilities list */ -#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ -#define PCI_SCR_S (0x00000100) /* SERR enable */ -#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ -#define PCI_SCR_PER (0x00000040) /* Parity error response */ -#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ -#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ -#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ -#define PCI_SCR_B (0x00000004) /* Bus master enable */ -#define PCI_SCR_M (0x00000002) /* Memory access control */ -#define PCI_SCR_IO (0x00000001) /* I/O access control */ - -#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ -#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ -#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ -#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ - -#define PCI_BAR_BAR0(x) (x & 0xFFFC0000) -#define PCI_BAR_BAR1(x) (x & 0xFFF00000) -#define PCI_BAR_BAR2(x) (x & 0xFFC00000) -#define PCI_BAR_BAR3(x) (x & 0xFF000000) -#define PCI_BAR_BAR4(x) (x & 0xF8000000) -#define PCI_BAR_BAR5(x) (x & 0xE0000000) -#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ -#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ -#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ - -#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ -#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ -#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ -#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ - -#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ -#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ -#define PCI_GSCR_SE (0x10000000) /* SERR detected */ -#define PCI_GSCR_ER (0x08000000) /* Error response detected */ -#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ -#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ -#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ -#define PCI_GSCR_PR (0x00000001) /* PCI reset */ - -#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ -#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ -#define PCI_TCR1_P (0x00010000) /* Prefetch reads */ -#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ - -#define PCI_TCR2_B5E (0x00002000) /* */ -#define PCI_TCR2_B4E (0x00001000) /* */ -#define PCI_TCR2_B3E (0x00000800) /* */ -#define PCI_TCR2_B2E (0x00000400) /* */ -#define PCI_TCR2_B1E (0x00000200) /* */ -#define PCI_TCR2_B0E (0x00000100) /* */ -#define PCI_TCR2_CR (0x00000001) /* */ - -#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) -#define PCI_TBATR_EN (0x00000001) /* Enable */ - -#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ -#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ -#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ -#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ -#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ -#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ -#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ -#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ -#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ - -#define PCI_ICR_REE (0x04000000) /* Retry error enable */ -#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ -#define PCI_ICR_TAE (0x01000000) /* Target abort enable */ -#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) - -/********************************************************************/ - -#endif /* __MCF5445X__ */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h deleted file mode 100644 index 5776bda3e3..0000000000 --- a/include/asm-nios2/bitops.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_BITOPS_H_ -#define __ASM_NIOS2_BITOPS_H_ - - -extern void set_bit(int nr, volatile void * a); -extern void clear_bit(int nr, volatile void * a); -extern int test_and_clear_bit(int nr, volatile void * a); -extern void change_bit(unsigned long nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void * a); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int test_bit(int nr, volatile void * a); -extern int ffs(int i); -#define PLATFORM_FFS - -#endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h deleted file mode 100644 index 01d11efece..0000000000 --- a/include/asm-nios2/io.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_IO_H_ -#define __ASM_NIOS2_IO_H_ - -static inline void sync(void) -{ - __asm__ __volatile__ ("sync" : : : "memory"); -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -extern unsigned char inb (unsigned char *port); -extern unsigned short inw (unsigned short *port); -extern unsigned inl (unsigned port); - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -#define readb(addr)\ - ({unsigned char val;\ - asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define readw(addr)\ - ({unsigned short val;\ - asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define readl(addr)\ - ({unsigned long val;\ - asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) - -#define writeb(addr,val)\ - asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writew(addr,val)\ - asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writel(addr,val)\ - asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val)) - -#define inb(addr) readb(addr) -#define inw(addr) readw(addr) -#define inl(addr) readl(addr) -#define outb(addr,val) writeb(addr,val) -#define outw(addr,val) writew(addr,val) -#define outl(addr,val) writel(addr,val) - -static inline void insb (unsigned long port, void *dst, unsigned long count) -{ - unsigned char *p = dst; - while (count--) *p++ = inb (port); -} -static inline void insw (unsigned long port, void *dst, unsigned long count) -{ - unsigned short *p = dst; - while (count--) *p++ = inw (port); -} -static inline void insl (unsigned long port, void *dst, unsigned long count) -{ - unsigned long *p = dst; - while (count--) *p++ = inl (port); -} - -static inline void outsb (unsigned long port, const void *src, unsigned long count) -{ - const unsigned char *p = src; - while (count--) outb (*p++, port); -} - -static inline void outsw (unsigned long port, const void *src, unsigned long count) -{ - const unsigned short *p = src; - while (count--) outw (*p++, port); -} -static inline void outsl (unsigned long port, const void *src, unsigned long count) -{ - const unsigned long *p = src; - while (count--) outl (*p++, port); -} - -#endif /* __ASM_NIOS2_IO_H_ */ diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h deleted file mode 100644 index ec84f5935f..0000000000 --- a/include/asm-nios2/system.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_NIOS2_SYSTEM_H_ -#define __ASM_NIOS2_SYSTEM_H_ - -#endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h deleted file mode 100644 index 0d78aa400e..0000000000 --- a/include/asm-ppc/config.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#define CONFIG_LMB - -#ifndef CONFIG_MAX_MEM_MAPPED -#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) -#else -#define CONFIG_MAX_MEM_MAPPED (256 << 20) -#endif -#endif - -/* Check if boards need to enable FSL DMA engine for SDRAM init */ -#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) -#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ - ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ - !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) -#define CONFIG_FSL_DMA -#endif -#endif - -#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ - defined(CONFIG_P2020) || defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 -#elif defined(CONFIG_PPC_P4080) -#define CONFIG_MAX_CPUS 8 -#else -#define CONFIG_MAX_CPUS 1 -#endif - -/* - * Provide a default boot page translation virtual address that lines up with - * Freescale's default e500 reset page. - */ -#if (defined(CONFIG_E500) && defined(CONFIG_MP)) -#ifndef CONFIG_BPTR_VIRT_ADDR -#define CONFIG_BPTR_VIRT_ADDR 0xfffff000 -#endif -#endif - -/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ -#if defined(CONFIG_TSEC_ENET) && \ - (defined(CONFIG_P1020) || defined(CONFIG_P1011)) -#define CONFIG_TSECV2 -#endif - -/* Number of TLB CAM entries we have on FSL Book-E chips */ -#if defined(CONFIG_E500MC) -#define CONFIG_SYS_NUM_TLBCAMS 64 -#elif defined(CONFIG_E500) -#define CONFIG_SYS_NUM_TLBCAMS 16 -#endif - -/* Relocation to SDRAM works on all PPC boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -#endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h deleted file mode 100644 index fd1024947d..0000000000 --- a/include/asm-ppc/mmu.h +++ /dev/null @@ -1,759 +0,0 @@ -/* - * PowerPC memory management structures - */ - -#ifndef _PPC_MMU_H_ -#define _PPC_MMU_H_ - -#include - -#ifndef __ASSEMBLY__ -/* Hardware Page Table Entry */ -typedef struct _PTE { -#ifdef CONFIG_PPC64BRIDGE - unsigned long long vsid:52; - unsigned long api:5; - unsigned long :5; - unsigned long h:1; - unsigned long v:1; - unsigned long long rpn:52; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long v:1; /* Entry is valid */ - unsigned long vsid:24; /* Virtual segment identifier */ - unsigned long h:1; /* Hash algorithm indicator */ - unsigned long api:6; /* Abbreviated page index */ - unsigned long rpn:20; /* Real (physical) page number */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :3; /* Unused */ - unsigned long r:1; /* Referenced */ - unsigned long c:1; /* Changed */ - unsigned long w:1; /* Write-thru cache mode */ - unsigned long i:1; /* Cache inhibited */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page protection */ -} PTE; - -/* Values for PP (assumes Ks=0, Kp=1) */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - -/* Segment Register */ -typedef struct _SEGREG { - unsigned long t:1; /* Normal or I/O type */ - unsigned long ks:1; /* Supervisor 'key' (normally 0) */ - unsigned long kp:1; /* User 'key' (normally 1) */ - unsigned long n:1; /* No-execute */ - unsigned long :4; /* Unused */ - unsigned long vsid:24; /* Virtual Segment Identifier */ -} SEGREG; - -/* Block Address Translation (BAT) Registers */ -typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :8; /* unused */ - unsigned long w:1; - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long ks:1; /* Supervisor key (normally 0) */ - unsigned long kp:1; /* User key (normally 1) */ - unsigned long pp:2; /* Page access protections */ -} P601_BATU; - -typedef struct _BATU { /* Upper part of BAT (all except 601) */ -#ifdef CONFIG_PPC64BRIDGE - unsigned long long bepi:47; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long bepi:15; /* Effective page index (virtual address) */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :4; /* Unused */ - unsigned long bl:11; /* Block size mask */ - unsigned long vs:1; /* Supervisor valid */ - unsigned long vp:1; /* User valid */ -} BATU; - -typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long v:1; /* Valid bit */ - unsigned long bl:6; /* Block size mask */ -} P601_BATL; - -typedef struct _BATL { /* Lower part of BAT (all except 601) */ -#ifdef CONFIG_PPC64BRIDGE - unsigned long long brpn:47; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long brpn:15; /* Real page index (physical address) */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :10; /* Unused */ - unsigned long w:1; /* Write-thru cache */ - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded (MBZ in IBAT) */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page access protections */ -} BATL; - -typedef struct _BAT { - BATU batu; /* Upper register */ - BATL batl; /* Lower register */ -} BAT; - -typedef struct _P601_BAT { - P601_BATU batu; /* Upper register */ - P601_BATL batl; /* Lower register */ -} P601_BAT; - -/* - * Simulated two-level MMU. This structure is used by the kernel - * to keep track of MMU mappings and is used to update/maintain - * the hardware HASH table which is really a cache of mappings. - * - * The simulated structures mimic the hardware available on other - * platforms, notably the 80x86 and 680x0. - */ - -typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ -} pte; - -#define PD_SHIFT (10+12) /* Page directory */ -#define PD_MASK 0x02FF -#define PT_SHIFT (12) /* Page Table */ -#define PT_MASK 0x02FF -#define PG_SHIFT (12) /* Page Entry */ - - -/* MMU context */ - -typedef struct _MMU_context { - SEGREG segs[16]; /* Segment registers */ - pte **pmap; /* Two-level page-map structure */ -} MMU_context; - -extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ -extern void _tlbia(void); /* invalidate all TLB entries */ - -#ifdef CONFIG_ADDR_MAP -extern void init_addr_map(void); -#endif - -typedef enum { - IBAT0 = 0, IBAT1, IBAT2, IBAT3, - DBAT0, DBAT1, DBAT2, DBAT3, -#ifdef CONFIG_HIGH_BATS - IBAT4, IBAT5, IBAT6, IBAT7, - DBAT4, DBAT5, DBAT6, DBAT7 -#endif -} ppc_bat_t; - -extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); -extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); -extern void print_bats(void); - -#endif /* __ASSEMBLY__ */ - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - -/* BAT Block size values */ -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -/* Block lengths for processors that support extended block length */ -#ifdef HID0_XBSEN -#define BATU_BL_512M 0x00003ffc -#define BATU_BL_1G 0x00007ffc -#define BATU_BL_2G 0x0000fffc -#define BATU_BL_4G 0x0001fffc -#define BATU_BL_MAX BATU_BL_4G -#else -#define BATU_BL_MAX BATU_BL_256M -#endif - -/* BAT Access Protection */ -#define BPP_XX 0x00 /* No access */ -#define BPP_RX 0x01 /* Read only */ -#define BPP_RW 0x02 /* Read/write */ - -/* Macros to get values from BATs, once data is in the BAT register format */ -#define BATU_VALID(x) (x & 0x3) -#define BATU_VADDR(x) (x & 0xfffe0000) -#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ - | ((x & 0x0e00ULL) << 24) \ - | ((x & 0x04ULL) << 30))) -#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17)) - -/* Used to set up SDR1 register */ -#define HASH_TABLE_SIZE_64K 0x00010000 -#define HASH_TABLE_SIZE_128K 0x00020000 -#define HASH_TABLE_SIZE_256K 0x00040000 -#define HASH_TABLE_SIZE_512K 0x00080000 -#define HASH_TABLE_SIZE_1M 0x00100000 -#define HASH_TABLE_SIZE_2M 0x00200000 -#define HASH_TABLE_SIZE_4M 0x00400000 -#define HASH_TABLE_MASK_64K 0x000 -#define HASH_TABLE_MASK_128K 0x001 -#define HASH_TABLE_MASK_256K 0x003 -#define HASH_TABLE_MASK_512K 0x007 -#define HASH_TABLE_MASK_1M 0x00F -#define HASH_TABLE_MASK_2M 0x01F -#define HASH_TABLE_MASK_4M 0x03F - -/* Control/status registers for the MPC8xx. - * A write operation to these registers causes serialized access. - * During software tablewalk, the registers used perform mask/shift-add - * operations when written/read. A TLB entry is created when the Mx_RPN - * is written, and the contents of several registers are used to - * create the entry. - */ -#define MI_CTR 784 /* Instruction TLB control register */ -#define MI_GPM 0x80000000 /* Set domain manager mode */ -#define MI_PPM 0x40000000 /* Set subpage protection */ -#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MI_RESETVAL 0x00000000 /* Value of register at reset */ - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MI_AP 786 -#define MI_Ks 0x80000000 /* Should not be set */ -#define MI_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MI_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MI_EPN 787 -#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MI_EVALID 0x00000200 /* Entry is valid */ -#define MI_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the instruction TLB, it contains bits that get loaded into the - * TLB entry when the MI_RPN is written. - */ -#define MI_TWC 789 -#define MI_APG 0x000001e0 /* Access protection group (0) */ -#define MI_GUARDED 0x00000010 /* Guarded storage */ -#define MI_PSMASK 0x0000000c /* Mask of page size bits */ -#define MI_PS8MEG 0x0000000c /* 8M page size */ -#define MI_PS512K 0x00000004 /* 512K page size */ -#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MI_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the instruction TLB, using - * additional information from the MI_EPN, and MI_TWC registers. - */ -#define MI_RPN 790 - -/* Define an RPN value for mapping kernel memory to large virtual - * pages for boot initialization. This has real page number of 0, - * large page size, shared page, cache enabled, and valid. - * Also mark all subpages valid and write access. - */ -#define MI_BOOTINIT 0x000001fd - -#define MD_CTR 792 /* Data TLB control register */ -#define MD_GPM 0x80000000 /* Set domain manager mode */ -#define MD_PPM 0x40000000 /* Set subpage protection */ -#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ -#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ -#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MD_RESETVAL 0x04000000 /* Value of register at reset */ - -#define M_CASID 793 /* Address space ID (context) to match */ -#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ - - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MD_AP 794 -#define MD_Ks 0x80000000 /* Should not be set */ -#define MD_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MD_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MD_EPN 795 -#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MD_EVALID 0x00000200 /* Entry is valid */ -#define MD_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* The pointer to the base address of the first level page table. - * During a software tablewalk, reading this register provides the address - * of the entry associated with MD_EPN. - */ -#define M_TWB 796 -#define M_L1TB 0xfffff000 /* Level 1 table base address */ -#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the data TLB, it contains bits that get loaded into the TLB entry - * when the MD_RPN is written. It is also provides the hardware assist - * for finding the PTE address during software tablewalk. - */ -#define MD_TWC 797 -#define MD_L2TB 0xfffff000 /* Level 2 table base address */ -#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ -#define MD_APG 0x000001e0 /* Access protection group (0) */ -#define MD_GUARDED 0x00000010 /* Guarded storage */ -#define MD_PSMASK 0x0000000c /* Mask of page size bits */ -#define MD_PS8MEG 0x0000000c /* 8M page size */ -#define MD_PS512K 0x00000004 /* 512K page size */ -#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MD_WT 0x00000002 /* Use writethrough page attribute */ -#define MD_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the data TLB, using - * additional information from the MD_EPN, and MD_TWC registers. - */ -#define MD_RPN 798 - -/* This is a temporary storage register that could be used to save - * a processor working register during a tablewalk. - */ -#define M_TW 799 - -/* - * At present, all PowerPC 400-class processors share a similar TLB - * architecture. The instruction and data sides share a unified, - * 64-entry, fully-associative TLB which is maintained totally under - * software control. In addition, the instruction side has a - * hardware-managed, 4-entry, fully- associative TLB which serves as a - * first level to the shared TLB. These two TLBs are known as the UTLB - * and ITLB, respectively. - */ - -#define PPC4XX_TLB_SIZE 64 - -/* - * TLB entries are defined by a "high" tag portion and a "low" data - * portion. On all architectures, the data portion is 32-bits. - * - * TLB entries are managed entirely under software control by reading, - * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx - * instructions. - */ - -/* - * FSL Book-E support - */ - -#define MAS0_TLBSEL_MSK 0x30000000 -#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) -#define MAS0_ESEL_MSK 0x0FFF0000 -#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) -#define MAS0_NV(x) ((x) & 0x00000FFF) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) -#define MAS1_TS 0x00001000 -#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) - -#define MAS2_EPN 0xFFFFF000 -#define MAS2_X0 0x00000040 -#define MAS2_X1 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN 0xFFFFF000 -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 - -#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) -#define MAS4_TIDDSEL 0x000F0000 -#define MAS4_TSIZED(x) MAS1_TSIZE(x) -#define MAS4_X0D 0x00000040 -#define MAS4_X1D 0x00000020 -#define MAS4_WD 0x00000010 -#define MAS4_ID 0x00000008 -#define MAS4_MD 0x00000004 -#define MAS4_GD 0x00000002 -#define MAS4_ED 0x00000001 - -#define MAS6_SPID0 0x3FFF0000 -#define MAS6_SPID1 0x00007FFE -#define MAS6_SAS 0x00000001 -#define MAS6_SPID MAS6_SPID0 - -#define MAS7_RPN 0xFFFFFFFF - -#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \ - (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) -#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \ - ((((v) << 31) & MAS1_VALID) |\ - (((iprot) << 30) & MAS1_IPROT) |\ - (MAS1_TID(tid)) |\ - (((ts) << 12) & MAS1_TS) |\ - (MAS1_TSIZE(tsize))) -#define FSL_BOOKE_MAS2(epn, wimge) \ - (((epn) & MAS3_RPN) | (wimge)) -#define FSL_BOOKE_MAS3(rpn, user, perms) \ - (((rpn) & MAS3_RPN) | (user) | (perms)) -#define FSL_BOOKE_MAS7(rpn) \ - (((u64)(rpn)) >> 32) - -#define BOOKE_PAGESZ_1K 0 -#define BOOKE_PAGESZ_4K 1 -#define BOOKE_PAGESZ_16K 2 -#define BOOKE_PAGESZ_64K 3 -#define BOOKE_PAGESZ_256K 4 -#define BOOKE_PAGESZ_1M 5 -#define BOOKE_PAGESZ_4M 6 -#define BOOKE_PAGESZ_16M 7 -#define BOOKE_PAGESZ_64M 8 -#define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1G 10 -#define BOOKE_PAGESZ_4G 11 -#define BOOKE_PAGESZ_16GB 12 -#define BOOKE_PAGESZ_64GB 13 -#define BOOKE_PAGESZ_256GB 14 -#define BOOKE_PAGESZ_1TB 15 - -#ifdef CONFIG_E500 -#ifndef __ASSEMBLY__ -extern void set_tlb(u8 tlb, u32 epn, u64 rpn, - u8 perms, u8 wimge, - u8 ts, u8 esel, u8 tsize, u8 iprot); -extern void disable_tlb(u8 esel); -extern void invalidate_tlb(u8 tlb); -extern void init_tlbs(void); -extern int find_tlb_idx(void *addr, u8 tlbsel); -extern void init_used_tlb_cams(void); -extern int find_free_tlbcam(void); - -extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); - -extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); - -#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ - { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ - .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ - .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ - .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ - .mas7 = FSL_BOOKE_MAS7(_rpn), } - -struct fsl_e_tlb_entry { - u32 mas0; - u32 mas1; - u32 mas2; - u32 mas3; - u32 mas7; -}; - -extern struct fsl_e_tlb_entry tlb_table[]; -extern int num_tlb_entries; -#endif -#endif - -#ifdef CONFIG_E300 -#define LAWAR_EN 0x80000000 -#define LAWAR_SIZE 0x0000003F - -#define LAWAR_TRGT_IF_PCI 0x00000000 -#define LAWAR_TRGT_IF_PCI1 0x00000000 -#define LAWAR_TRGT_IF_PCIX 0x00000000 -#define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_PCIE1 0x00200000 -#define LAWAR_TRGT_IF_PCIE2 0x00100000 -#define LAWAR_TRGT_IF_PCIE3 0x00300000 -#define LAWAR_TRGT_IF_LBC 0x00400000 -#define LAWAR_TRGT_IF_CCSR 0x00800000 -#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 -#define LAWAR_TRGT_IF_RIO 0x00c00000 -#define LAWAR_TRGT_IF_DDR 0x00f00000 -#define LAWAR_TRGT_IF_DDR1 0x00f00000 -#define LAWAR_TRGT_IF_DDR2 0x01600000 - -#define LAWAR_SIZE_BASE 0xa -#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) -#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2) -#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3) -#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4) -#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5) -#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6) -#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7) -#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8) -#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9) -#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10) -#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11) -#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12) -#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13) -#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14) -#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15) -#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16) -#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17) -#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) -#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) -#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) -#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) -#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) -#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) -#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) -#endif - -#ifdef CONFIG_440 -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID )) -#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn)) -#define TLB2(a) ((a) & 0x00000fbf) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ;\ -0: mflr r0 ;\ - mtlr r1 ;\ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - -/*----------------------------------------------------------------------------+ -| TLB specific defines. -+----------------------------------------------------------------------------*/ -#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL -#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL -#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL -#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL -#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL -#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL -#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL -#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL -#define TLB_256MB_SIZE 0x10000000 -#define TLB_16MB_SIZE 0x01000000 -#define TLB_1MB_SIZE 0x00100000 -#define TLB_256KB_SIZE 0x00040000 -#define TLB_64KB_SIZE 0x00010000 -#define TLB_16KB_SIZE 0x00004000 -#define TLB_4KB_SIZE 0x00001000 -#define TLB_1KB_SIZE 0x00000400 - -#define TLB_WORD0_EPN_MASK 0xFFFFFC00 -#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_V_MASK 0x00000200 -#define TLB_WORD0_V_ENABLE 0x00000200 -#define TLB_WORD0_V_DISABLE 0x00000000 -#define TLB_WORD0_TS_MASK 0x00000100 -#define TLB_WORD0_TS_1 0x00000100 -#define TLB_WORD0_TS_0 0x00000000 -#define TLB_WORD0_SIZE_MASK 0x000000F0 -#define TLB_WORD0_SIZE_1KB 0x00000000 -#define TLB_WORD0_SIZE_4KB 0x00000010 -#define TLB_WORD0_SIZE_16KB 0x00000020 -#define TLB_WORD0_SIZE_64KB 0x00000030 -#define TLB_WORD0_SIZE_256KB 0x00000040 -#define TLB_WORD0_SIZE_1MB 0x00000050 -#define TLB_WORD0_SIZE_16MB 0x00000070 -#define TLB_WORD0_SIZE_256MB 0x00000090 -#define TLB_WORD0_TPAR_MASK 0x0000000F -#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD1_RPN_MASK 0xFFFFFC00 -#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_PAR1_MASK 0x00000300 -#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) -#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03) -#define TLB_WORD1_PAR1_0 0x00000000 -#define TLB_WORD1_PAR1_1 0x00000100 -#define TLB_WORD1_PAR1_2 0x00000200 -#define TLB_WORD1_PAR1_3 0x00000300 -#define TLB_WORD1_ERPN_MASK 0x0000000F -#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD2_PAR2_MASK 0xC0000000 -#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30) -#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03) -#define TLB_WORD2_PAR2_0 0x00000000 -#define TLB_WORD2_PAR2_1 0x40000000 -#define TLB_WORD2_PAR2_2 0x80000000 -#define TLB_WORD2_PAR2_3 0xC0000000 -#define TLB_WORD2_U0_MASK 0x00008000 -#define TLB_WORD2_U0_ENABLE 0x00008000 -#define TLB_WORD2_U0_DISABLE 0x00000000 -#define TLB_WORD2_U1_MASK 0x00004000 -#define TLB_WORD2_U1_ENABLE 0x00004000 -#define TLB_WORD2_U1_DISABLE 0x00000000 -#define TLB_WORD2_U2_MASK 0x00002000 -#define TLB_WORD2_U2_ENABLE 0x00002000 -#define TLB_WORD2_U2_DISABLE 0x00000000 -#define TLB_WORD2_U3_MASK 0x00001000 -#define TLB_WORD2_U3_ENABLE 0x00001000 -#define TLB_WORD2_U3_DISABLE 0x00000000 -#define TLB_WORD2_W_MASK 0x00000800 -#define TLB_WORD2_W_ENABLE 0x00000800 -#define TLB_WORD2_W_DISABLE 0x00000000 -#define TLB_WORD2_I_MASK 0x00000400 -#define TLB_WORD2_I_ENABLE 0x00000400 -#define TLB_WORD2_I_DISABLE 0x00000000 -#define TLB_WORD2_M_MASK 0x00000200 -#define TLB_WORD2_M_ENABLE 0x00000200 -#define TLB_WORD2_M_DISABLE 0x00000000 -#define TLB_WORD2_G_MASK 0x00000100 -#define TLB_WORD2_G_ENABLE 0x00000100 -#define TLB_WORD2_G_DISABLE 0x00000000 -#define TLB_WORD2_E_MASK 0x00000080 -#define TLB_WORD2_E_ENABLE 0x00000080 -#define TLB_WORD2_E_DISABLE 0x00000000 -#define TLB_WORD2_UX_MASK 0x00000020 -#define TLB_WORD2_UX_ENABLE 0x00000020 -#define TLB_WORD2_UX_DISABLE 0x00000000 -#define TLB_WORD2_UW_MASK 0x00000010 -#define TLB_WORD2_UW_ENABLE 0x00000010 -#define TLB_WORD2_UW_DISABLE 0x00000000 -#define TLB_WORD2_UR_MASK 0x00000008 -#define TLB_WORD2_UR_ENABLE 0x00000008 -#define TLB_WORD2_UR_DISABLE 0x00000000 -#define TLB_WORD2_SX_MASK 0x00000004 -#define TLB_WORD2_SX_ENABLE 0x00000004 -#define TLB_WORD2_SX_DISABLE 0x00000000 -#define TLB_WORD2_SW_MASK 0x00000002 -#define TLB_WORD2_SW_ENABLE 0x00000002 -#define TLB_WORD2_SW_DISABLE 0x00000000 -#define TLB_WORD2_SR_MASK 0x00000001 -#define TLB_WORD2_SR_ENABLE 0x00000001 -#define TLB_WORD2_SR_DISABLE 0x00000000 - -/*----------------------------------------------------------------------------+ -| Following instructions are not available in Book E mode of the GNU assembler. -+----------------------------------------------------------------------------*/ -#define DCCCI(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(454<<1) - -#define ICCCI(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(966<<1) - -#define DCREAD(rt,ra,rb) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(rb<<11)|(486<<1) - -#define ICREAD(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(998<<1) - -#define TLBSX(rt,ra,rb) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) - -#define TLBWE(rs,ra,ws) .long 0x7c000000|\ - (rs<<21)|(ra<<16)|(ws<<11)|(978<<1) - -#define TLBRE(rt,ra,ws) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) - -#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\ - (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) - -#define MSYNC .long 0x7c000000|\ - (598<<1) - -#define MBAR_INST .long 0x7c000000|\ - (854<<1) - -#ifndef __ASSEMBLY__ -/* Prototypes */ -void mttlb1(unsigned long index, unsigned long value); -void mttlb2(unsigned long index, unsigned long value); -void mttlb3(unsigned long index, unsigned long value); -unsigned long mftlb1(unsigned long index); -unsigned long mftlb2(unsigned long index); -unsigned long mftlb3(unsigned long index); - -void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); -void remove_tlb(u32 vaddr, u32 size); -void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_440 */ -#endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h deleted file mode 100644 index c6da411630..0000000000 --- a/include/asm-ppc/processor.h +++ /dev/null @@ -1,1271 +0,0 @@ -#ifndef __ASM_PPC_PROCESSOR_H -#define __ASM_PPC_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#include - -#include -#include - -/* Machine State Register (MSR) Fields */ - -#ifdef CONFIG_PPC64BRIDGE -#define MSR_SF (1<<63) -#define MSR_ISF (1<<61) -#endif /* CONFIG_PPC64BRIDGE */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ -#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ -#define MSR_SPE (1<<25) /* Enable SPE(e500) */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_WE (1<<18) /* Wait State Enable */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ -#define MSR_ILE (1<<16) /* Interrupt Little Endian */ -#define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_PR (1<<14) /* Problem State / Privilege Level */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check Enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ -#define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ -#define MSR_DS (1<<4) /* Book E Data space */ -#define MSR_PE (1<<3) /* Protection Enable */ -#define MSR_PX (1<<2) /* Protection Exclusive Mode */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ - -#ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_ MSR_ME|MSR_IP|MSR_RI -#else -#define MSR_ MSR_ME|MSR_RI -#endif -#ifndef CONFIG_E500 -#define MSR_KERNEL MSR_|MSR_IR|MSR_DR -#else -#define MSR_KERNEL MSR_ME -#endif - -/* Floating Point Status and Control Register (FPSCR) Fields */ - -#define FPSCR_FX 0x80000000 /* FPU exception summary */ -#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ -#define FPSCR_VX 0x20000000 /* Invalid operation summary */ -#define FPSCR_OX 0x10000000 /* Overflow exception summary */ -#define FPSCR_UX 0x08000000 /* Underflow exception summary */ -#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ -#define FPSCR_XX 0x02000000 /* Inexact exception summary */ -#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ -#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ -#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ -#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ -#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ -#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ -#define FPSCR_FR 0x00040000 /* Fraction rounded */ -#define FPSCR_FI 0x00020000 /* Fraction inexact */ -#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ -#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ -#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ -#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ -#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ -#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ -#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ -#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ -#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ -#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ -#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ -#define FPSCR_RN 0x00000003 /* FPU rounding control */ - -/* Special Purpose Registers (SPRNs)*/ - -/* PPC440 Architecture is BOOK-E */ -#ifdef CONFIG_440 -#define CONFIG_BOOKE -#endif - -#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ -#ifdef CONFIG_BOOKE -#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ -#endif -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_CTR 0x009 /* Count Register */ -#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ -#ifndef CONFIG_BOOKE -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ -#else -#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DAR 0x013 /* Data Address Register */ -#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ -#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ -#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ -#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ -#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ -#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ -#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ -#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ -#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ -#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ -#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ -#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ -#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ -#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ -#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ -#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define DBCR_EDM 0x80000000 -#define DBCR_IDM 0x40000000 -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ -#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ -#define DBCR_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ -#ifndef CONFIG_BOOKE -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ -#else -#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ -#endif /* CONFIG_BOOKE */ -#ifndef CONFIG_BOOKE -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ -#else -#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ -#ifdef CONFIG_BOOKE -#define SPRN_DBDR 0x3f3 /* Debug Data Register */ -#endif -#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ -#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ -#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ -#ifndef CONFIG_BOOKE -#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ -#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ -#endif -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ -#ifndef CONFIG_BOOKE -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ -#else -#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DEC 0x016 /* Decrement Register */ -#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ -#ifdef CONFIG_BOOKE -#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ -#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ -#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ -#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ -#endif -#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ -#ifdef CONFIG_BOOKE -#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ -#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ -#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ -#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ -#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ -#endif -#define SPRN_EAR 0x11A /* External Address Register */ -#ifndef CONFIG_BOOKE -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ -#else -#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ -#endif /* CONFIG_BOOKE */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ -#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ -#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ - -#define HID0_ICE_SHIFT 15 -#define HID0_DCE_SHIFT 14 -#define HID0_DLOCK_SHIFT 12 - -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ - -#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ -#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ -#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ -#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ -#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ -#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ -#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ - -/* Processor Version Register */ - -/* Processor Version Register (PVR) field extraction */ - -#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ -#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ - -/* - * AMCC has further subdivided the standard PowerPC 16-bit version and - * revision subfields of the PVR for the PowerPC 403s into the following: - */ - -#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ -#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ -#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ -#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ -#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ -#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ - -/* e600 core PVR fields */ - -#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ -#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ -#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ -#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ - -/* Processor Version Numbers */ - -#define PVR_403GA 0x00200000 -#define PVR_403GB 0x00200100 -#define PVR_403GC 0x00200200 -#define PVR_403GCX 0x00201400 -#define PVR_405GP 0x40110000 -#define PVR_405GP_RB 0x40110040 -#define PVR_405GP_RC 0x40110082 -#define PVR_405GP_RD 0x401100C4 -#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ -#define PVR_405CR_RA 0x40110041 -#define PVR_405CR_RB 0x401100C5 -#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ -#define PVR_405EP_RA 0x51210950 -#define PVR_405GPR_RB 0x50910951 -#define PVR_405EZ_RA 0x41511460 -#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ -#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ -#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ -#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ -#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ -#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ -#define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */ -#define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */ -#define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */ -#define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */ -#define PVR_440GP_RB 0x40120440 -#define PVR_440GP_RC 0x40120481 -#define PVR_440EP_RA 0x42221850 -#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ -#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ -#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ -#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ -#define PVR_440GX_RA 0x51B21850 -#define PVR_440GX_RB 0x51B21851 -#define PVR_440GX_RC 0x51B21892 -#define PVR_440GX_RF 0x51B21894 -#define PVR_405EP_RB 0x51210950 -#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ -#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ -#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ -#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ -#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ -#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ -#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ -#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ -#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ -#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ -#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/ -#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ -#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ -#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/ -#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ -#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ -#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ -#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ -#define PVR_601 0x00010000 -#define PVR_602 0x00050000 -#define PVR_603 0x00030000 -#define PVR_603e 0x00060000 -#define PVR_603ev 0x00070000 -#define PVR_603r 0x00071000 -#define PVR_604 0x00040000 -#define PVR_604e 0x00090000 -#define PVR_604r 0x000A0000 -#define PVR_620 0x00140000 -#define PVR_740 0x00080000 -#define PVR_750 PVR_740 -#define PVR_740P 0x10080000 -#define PVR_750P PVR_740P -#define PVR_7400 0x000C0000 -#define PVR_7410 0x800C0000 -#define PVR_7450 0x80000000 - -#define PVR_85xx 0x80200000 -#define PVR_85xx_REV1 (PVR_85xx | 0x0010) -#define PVR_85xx_REV2 (PVR_85xx | 0x0020) - -#define PVR_86xx 0x80040000 - -#define PVR_VIRTEX5 0x7ff21912 - -/* - * For the 8xx processors, all of them report the same PVR family for - * the PowerPC core. The various versions of these processors must be - * differentiated by the version number in the Communication Processor - * Module (CPM). - */ -#define PVR_821 0x00500000 -#define PVR_823 PVR_821 -#define PVR_850 PVR_821 -#define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 -#define PVR_8240 0x00810100 - -/* - * PowerQUICC II family processors report different PVR values depending - * on silicon process (HiP3, HiP4, HiP7, etc.) - */ -#define PVR_8260 PVR_8240 -#define PVR_8260_HIP3 0x00810101 -#define PVR_8260_HIP4 0x80811014 -#define PVR_8260_HIP7 0x80822011 -#define PVR_8260_HIP7R1 0x80822013 -#define PVR_8260_HIP7RA 0x80822014 - -/* - * MPC 52xx - */ -#define PVR_5200 0x80822011 -#define PVR_5200B 0x80822014 - -/* - * System Version Register - */ - -/* System Version Register (SVR) field extraction */ - -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ - -#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ - -#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ -#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ - -#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ -#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ - -/* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ - -/* whether MPC8xxxE (i.e. has SEC) */ -#if defined(CONFIG_MPC85xx) -#define IS_E_PROCESSOR(svr) (svr & 0x80000) -#else -#if defined(CONFIG_MPC83xx) -#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) -#endif -#endif - -#define IS_SVR_REV(svr, maj, min) \ - ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) - -/* - * SVR_SOC_VER() Version Values - */ - -#define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 -#define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 -#define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 -#define SVR_8540 0x803000 -#define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 -#define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 -#define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 -#define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 -#define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 -#define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 -#define SVR_8560 0x807000 -#define SVR_8567 0x807600 -#define SVR_8567_E 0x807E00 -#define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 -#define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 -#define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 -#define SVR_P1011 0x80E500 -#define SVR_P1011_E 0x80ED00 -#define SVR_P1020 0x80E400 -#define SVR_P1020_E 0x80EC00 -#define SVR_P2010 0x80E300 -#define SVR_P2010_E 0x80EB00 -#define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 -#define SVR_P4040 0x820100 -#define SVR_P4040_E 0x820900 -#define SVR_P4080 0x820000 -#define SVR_P4080_E 0x820800 - -#define SVR_8610 0x80A000 -#define SVR_8641 0x809000 -#define SVR_8641D 0x809001 - -#define SVR_Unknown 0xFFFFFF - -#define _GLOBAL(n)\ - .globl n;\ -n: - -/* Macros for setting and retrieving special purpose registers */ - -#define stringify(s) tostring(s) -#define tostring(s) #s - -#define mfdcr(rn) ({unsigned int rval; \ - asm volatile("mfdcr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) - -#define mfmsr() ({unsigned int rval; \ - asm volatile("mfmsr %0" : "=r" (rval)); rval;}) -#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) - -#define mfspr(rn) ({unsigned int rval; \ - asm volatile("mfspr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) - -#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) - -/* Segment Registers */ - -#define SR0 0 -#define SR1 1 -#define SR2 2 -#define SR3 3 -#define SR4 4 -#define SR5 5 -#define SR6 6 -#define SR7 7 -#define SR8 8 -#define SR9 9 -#define SR10 10 -#define SR11 11 -#define SR12 12 -#define SR13 13 -#define SR14 14 -#define SR15 15 - -#ifndef __ASSEMBLY__ - -struct cpu_type { - char name[15]; - u32 soc_ver; - u32 num_cores; -}; - -struct cpu_type *identify_cpu(u32 ver); - -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) -#define CPU_TYPE_ENTRY(n, v, nc) \ - { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), } -#else -#if defined(CONFIG_MPC83xx) -#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} -#endif -#endif - - -#ifndef CONFIG_MACH_SPECIFIC -extern int _machine; -extern int have_of; -#endif /* CONFIG_MACH_SPECIFIC */ - -/* what kind of prep workstation we are */ -extern int _prep_type; -/* - * This is used to identify the board type from a given PReP board - * vendor. Board revision is also made available. - */ -extern unsigned char ucSystemType; -extern unsigned char ucBoardRev; -extern unsigned char ucBoardRevMaj, ucBoardRevMin; - -struct task_struct; -void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); -void release_thread(struct task_struct *); - -/* - * Create a new kernel thread. - */ -extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -/* - * Bus types - */ -#define EISA_bus 0 -#define EISA_bus__is_a_macro /* for versions in ksyms.c */ -#define MCA_bus 0 -#define MCA_bus__is_a_macro /* for versions in ksyms.c */ - -/* Lazy FPU handling on uni-processor */ -extern struct task_struct *last_task_used_math; -extern struct task_struct *last_task_used_altivec; - -/* - * this is the minimum allowable io space due to the location - * of the io areas on prep (first one at 0x80000000) but - * as soon as I get around to remapping the io areas with the BATs - * to match the mac we can raise this. -- Cort - */ -#define TASK_SIZE (0x80000000UL) - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) - -typedef struct { - unsigned long seg; -} mm_segment_t; - -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ - struct pt_regs *regs; /* Pointer to saved register state */ - mm_segment_t fs; /* for get_fs() validation */ - void *pgdir; /* root of page-table tree */ - signed long last_syscall; - double fpr[32]; /* Complete floating point set */ - unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ - unsigned long fpscr; /* Floating point status */ -#ifdef CONFIG_ALTIVEC - vector128 vr[32]; /* Complete AltiVec set */ - vector128 vscr; /* AltiVec status */ - unsigned long vrsave; -#endif /* CONFIG_ALTIVEC */ -}; - -#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) - -#define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - (struct pt_regs *)INIT_SP - 1, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ -} - -/* - * Note: the vm_start and vm_end fields here should *not* - * be in kernel space. (Could vm_end == vm_start perhaps?) - */ -#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ - PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ - 1, NULL, NULL } - -/* - * Return saved PC of a blocked thread. For now, this is the "user" PC - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return (t->regs) ? t->regs->nip : 0; -} - -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) -#define forget_segments() do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) -#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) - -/* - * NOTE! The task struct and the stack go together - */ -#define THREAD_SIZE (2*PAGE_SIZE) -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) - -/* in process.c - for early bootup debug -- Cort */ -int ll_printk(const char *, ...); -void ll_puts(const char *); - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -/* In misc.c */ -void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); - -#endif /* ndef ASSEMBLY*/ - -#ifdef CONFIG_MACH_SPECIFIC -#if defined(CONFIG_8xx) -#define _machine _MACH_8xx -#define have_of 0 -#elif defined(CONFIG_OAK) -#define _machine _MACH_oak -#define have_of 0 -#elif defined(CONFIG_WALNUT) -#define _machine _MACH_walnut -#define have_of 0 -#elif defined(CONFIG_APUS) -#define _machine _MACH_apus -#define have_of 0 -#elif defined(CONFIG_GEMINI) -#define _machine _MACH_gemini -#define have_of 0 -#elif defined(CONFIG_8260) -#define _machine _MACH_8260 -#define have_of 0 -#elif defined(CONFIG_SANDPOINT) -#define _machine _MACH_sandpoint -#elif defined(CONFIG_HIDDEN_DRAGON) -#define _machine _MACH_hidden_dragon -#define have_of 0 -#else -#error "Machine not defined correctly" -#endif -#endif /* CONFIG_MACH_SPECIFIC */ - -#endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/include/common.h b/include/common.h index a133e3479a..df956bbb41 100644 --- a/include/common.h +++ b/include/common.h @@ -230,7 +230,7 @@ int parse_line (char *, char *[]); void init_cmd_timeout(void); void reset_cmd_timeout(void); -/* lib_$(ARCH)/board.c */ +/* arch/$(ARCH)/lib/board.c */ void board_init_f (ulong) __attribute__ ((noreturn)); void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); int checkboard (void); @@ -604,38 +604,38 @@ ulong vfd_setmem (ulong); /* $(CPU)/.../video.c */ ulong video_setmem (ulong); -/* lib_$(ARCH)/cache.c */ +/* arch/$(ARCH)/lib/cache.c */ void flush_cache (unsigned long, unsigned long); void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); -/* lib_$(ARCH)/ticks.S */ +/* arch/$(ARCH)/lib/ticks.S */ unsigned long long get_ticks(void); void wait_ticks (unsigned long); -/* lib_$(ARCH)/time.c */ +/* arch/$(ARCH)/lib/time.c */ void __udelay (unsigned long); ulong usec2ticks (unsigned long usec); ulong ticks2usec (unsigned long ticks); int init_timebase (void); -/* lib_generic/gunzip.c */ +/* lib/gunzip.c */ int gunzip(void *, int, unsigned char *, unsigned long *); int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, int stoponerr, int offset); -/* lib_generic/net_utils.c */ +/* lib/net_utils.c */ #include static inline IPaddr_t getenv_IPaddr (char *var) { return (string_to_ip(getenv(var))); } -/* lib_generic/time.c */ +/* lib/time.c */ void udelay (unsigned long); -/* lib_generic/vsprintf.c */ +/* lib/vsprintf.c */ ulong simple_strtoul(const char *cp,char **endp,unsigned int base); unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); long simple_strtol(const char *cp,char **endp,unsigned int base); @@ -645,10 +645,10 @@ int sprintf(char * buf, const char *fmt, ...) __attribute__ ((format (__printf__, 2, 3))); int vsprintf(char *buf, const char *fmt, va_list args); -/* lib_generic/strmhz.c */ +/* lib/strmhz.c */ char * strmhz(char *buf, long hz); -/* lib_generic/crc32.c */ +/* lib/crc32.c */ #include /* common/console.c */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 058fdf14fa..746bf18f04 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -15,6 +15,7 @@ #define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */ #define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */ #define CONFIG_CMD_BDI /* bdinfo */ #define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */ #define CONFIG_CMD_BMP /* BMP support */ @@ -33,7 +34,6 @@ #define CONFIG_CMD_EDITENV /* editenv */ #define CONFIG_CMD_EEPROM /* EEPROM read/write support */ #define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */ -#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ @@ -55,6 +55,7 @@ #define CONFIG_CMD_LOADS /* loads */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MFSL /* FSL support for Microblaze */ +#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */ #define CONFIG_CMD_MII /* MII support */ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ #define CONFIG_CMD_MMC /* MMC support */ @@ -70,6 +71,7 @@ #define CONFIG_CMD_REGINFO /* Register dump */ #define CONFIG_CMD_REISER /* Reiserfs support */ #define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SAVES /* save S record dump */ #define CONFIG_CMD_SCSI /* SCSI Support */ #define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ @@ -79,12 +81,12 @@ #define CONFIG_CMD_SOURCE /* "source" command support */ #define CONFIG_CMD_SPI /* SPI utility */ #define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */ +#define CONFIG_CMD_UBI /* UBI Support */ +#define CONFIG_CMD_UBIFS /* UBIFS Support */ #define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */ #define CONFIG_CMD_UNZIP /* unzip from memory to memory */ #define CONFIG_CMD_USB /* USB Support */ #define CONFIG_CMD_VFD /* VFD support (TRAB) */ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ -#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */ -#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */ #endif /* _CONFIG_CMD_ALL_H */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 5cb0f1e28c..4cb805223c 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/B2.h b/include/configs/B2.h index f51a26115c..ca7350dc40 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -207,7 +207,7 @@ */ /* - Linux TAGs (see lib_arm/armlinux.c) + Linux TAGs (see arch/arm/lib/armlinux.c) */ #define CONFIG_CMDLINE_TAG #undef CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 8c5a742290..44befe9edf 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -471,13 +471,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) -# define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -# define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -# define CONFIG_SYS_HID0_INIT 0 -# define CONFIG_SYS_HID0_FINAL 0 -#endif +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index e3e6e75e8d..cdba81d323 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -173,6 +173,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index ae8494d577..2b6786b9dc 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -224,6 +224,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 5c88c47b50..922121173a 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -207,6 +207,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index d131aeaf43..3e7020df89 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -256,6 +256,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 07c4e35995..d3000f6578 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -283,6 +283,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index c78552bbd4..d3763441ef 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -259,6 +259,7 @@ * I2C EEPROM (CAT24WC32) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 59e0778f6a..07acab0c2b 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -278,6 +278,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index b2679e5878..5b50bcf331 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -189,6 +189,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 96bf161aa1..9ab30ecbaf 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -65,6 +65,7 @@ #define CONFIG_ETHADDR 00:40:a6:80:14:5 */ #define CONFIG_HARD_I2C 1 /* hardware support for i2c */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SDRAM_BANK0 1 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 49ecb6f36c..4423f2ab62 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -174,6 +174,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU405.h b/include/configs/DU405.h index cfb3023318..8f1fc78bce 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -212,6 +212,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 65dc2359d0..830466f7a8 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -169,6 +169,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS 1 diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index a0b27a89c4..880cb4ee6b 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -208,6 +208,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index 61d8e20f9b..3920d35264 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -94,7 +94,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -123,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 41e64e6d1b..bfbf8c1119 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -118,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 5b332e40ee..4d905fee38 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -118,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 023f33e1eb..e07f9a1dc5 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -54,6 +54,7 @@ #endif /* total size of a X1240 is 2048 bytes */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 6819c3e362..d2883eb8d7 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -295,6 +295,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 92335239df..01e0bc65ec 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -331,6 +331,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #if 0 /* test-only */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #else diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index ea502d42cd..8c6d5edff7 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 5ef0b7798e..5d3a744fff 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -30,6 +30,7 @@ */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -47,7 +48,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -77,10 +77,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else -#define CONFIG_MII 1 -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -169,7 +165,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ @@ -178,7 +173,6 @@ #else #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif -#endif /* CONFIG_MPC5200 */ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -338,13 +332,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #if defined(CONFIG_LITE5200B) #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 80c70e4886..98f5661a09 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -217,6 +217,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 4b67c9454b..49a7378f27 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -132,6 +132,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 32123d2f54..e6632acbe7 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -158,7 +158,7 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 @@ -207,6 +207,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chipselect bank definitions */ /* * CS0 - NOR Flash diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 1801d9d7d5..6c6b5d6d57 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -302,6 +302,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 2b816ceae2..5c0dc842aa 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -237,6 +237,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index e3830e5369..33ac2859df 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -60,6 +60,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET #define CONFIG_SYS_PROMPT "=> " @@ -165,6 +166,20 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 5e86e4cb90..b5af493b80 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -57,6 +57,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS #define CONFIG_CMD_EXT2 @@ -95,11 +96,6 @@ # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 10.82.121.249 -# define CONFIG_NETMASK 255.255.252.0 -# define CONFIG_SERVERIP 10.82.120.80 -# define CONFIG_GATEWAYIP 10.82.123.254 # define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_EXTRA_ENV_SETTINGS \ @@ -109,9 +105,9 @@ "u-boot=u-boot.bin\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 2ffff;" \ - "era 0 2ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=prot off 0xff800000 0xff82ffff;" \ + "era 0xff800000 0xff82ffff;" \ + "cp.b ${loadaddr} 0xff800000 ${filesize};" \ "save\0" \ "" #endif @@ -231,6 +227,20 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(8) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index df6970cdfa..206d1152ee 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -64,6 +64,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS @@ -179,6 +180,20 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 50b3ab2808..798949cc56 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -72,6 +72,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_NET #define CONFIG_CMD_MII @@ -229,6 +230,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chip Select 0 : Boot Flash */ #define CONFIG_SYS_CS0_BASE 0xFFE00000 #define CONFIG_SYS_CS0_MASK 0x001F0001 diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index f824158a69..f704bb3ff7 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -74,6 +74,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_CMD_PING @@ -211,6 +212,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index b380159812..981670ac06 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -72,6 +72,7 @@ /* Available command configuration */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -121,11 +122,6 @@ #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) -#ifdef CONFIG_MCFFEC -#define CONFIG_ETHADDR 00:06:3b:01:41:55 -#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60 -#endif - #define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -145,6 +141,23 @@ #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_RETRY_COUNT 5 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${uboot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 150000000 @@ -208,6 +221,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 15590cfcd5..6e0aa14d3a 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -64,6 +64,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_MII @@ -209,6 +210,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 30855bdaa2..d983a8fedb 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -69,6 +69,8 @@ # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_TX_ETH_BUFFER 8 +# define CONFIG_SYS_FEC_BUF_USE_SRAM # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_HAS_ETH1 @@ -166,7 +168,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET @@ -180,7 +182,7 @@ #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 @@ -231,6 +233,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 8180c05e67..159b178f40 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -237,6 +237,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 8652a80aa1..af1988ce0a 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -237,6 +237,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index a5acfd2846..a80d33047f 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -309,6 +309,21 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 7737284aab..5b4bba8c26 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -279,7 +279,7 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32) @@ -408,6 +408,21 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 4534002e47..d0077667f3 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -286,6 +286,22 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 971cb67bad..f23b8b0efa 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -272,6 +272,22 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 518173aa5d..e7429dd199 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -194,6 +194,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 7ac9342251..7e6484ee94 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -97,6 +97,7 @@ ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 87901b3af9..da4313ac3a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -413,6 +413,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9b81703741..0c43b2b0c7 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -284,6 +284,9 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1d2d659239..8382e3ca83 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -177,7 +177,7 @@ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ +#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ @@ -341,10 +341,8 @@ * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U +#define CONFIG_SYS_DBAT0L (BATL_PP_RW) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW) /* * BAT1 1G Cache-inhibited, guarded diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 12a8f60390..94e4d243e8 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -482,9 +482,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * BAT0 DDR */ #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) /* * BAT1 LBC (PIXIS/CF) diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h new file mode 100644 index 0000000000..6492068c2f --- /dev/null +++ b/include/configs/MVSMR.h @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2010 + * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_MPC5xxx 1 +#define CONFIG_MPC5200 1 + +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 + +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 +#endif + +#define CONFIG_PSC_CONSOLE 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\ + 230400} + +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#undef CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_SYS_XLB_PIPELINING 1 +#define CONFIG_HIGH_BATS 1 + +#define MV_CI mvSMR +#define MV_VCI mvSMR +#define MV_FPGA_DATA 0xff840000 +#define MV_FPGA_SIZE 0x1ff88 +#define MV_KERNEL_ADDR 0xfff00000 +#define MV_SCRIPT_ADDR 0xff806000 +#define MV_INITRD_ADDR 0xff880000 +#define MV_INITRD_LENGTH 0x00240000 +#define MV_SCRATCH_ADDR 0xffcc0000 +#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define MV_KERNEL_ADDR_RAM 0x00100000 +#define MV_INITRD_ADDR_RAM 0x00400000 + +/* + * Supported commands + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SDRAM + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_RANDOM_DELAY +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_VENDOREX + +/* + * Autoboot + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "abcdefg" +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_BOOTCOMMAND "source ${script_addr}" +#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \ + " allocate=6M" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0" \ + "console=no\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "fpga=0\0" \ + "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ + "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ + "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ + "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ + "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \ + "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ + "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \ + "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \ + "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \ + "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \ + "mv_version=" U_BOOT_VERSION "\0" \ + "dhcp_client_id=" MK_STR(MV_CI) "\0" \ + "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \ + "netretry=no\0" \ + "use_static_ipaddr=no\0" \ + "static_ipaddr=192.168.0.101\0" \ + "static_netmask=255.255.255.0\0" \ + "static_gateway=0.0.0.0\0" \ + "initrd_name=uInitrd.mvsmr-rfs\0" \ + "zcip=yes\0" \ + "netboot=no\0" \ + "" + +#undef XMK_STR +#undef MK_STR + +/* + * IPB Bus clocking configuration. + */ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK + +/* + * Flash configuration + */ +#undef CONFIG_FLASH_16BIT +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_LOWBOOT +#define CONFIG_SYS_FLASH_BASE TEXT_BASE +#define CONFIG_SYS_FLASH_SIZE 0x00800000 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_HAS_UID +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x2000 + +/* used by linker script to wrap code around */ +#define CONFIG_SCRIPT_OFFSET 0x6000 +#define CONFIG_SCRIPT_SECT_SIZE 0x2000 + +/* + * Memory map + */ +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 + +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT 1 +#endif + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 << 10) +#define CONFIG_SYS_MALLOC_LEN (512 << 10) +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_MODULE 1 +#define CONFIG_SYS_I2C_SPEED 86000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * Ethernet configuration + */ +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_MPC5xxx_FEC +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_NETDEV eth0 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#undef CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x02f00000 + +#define CONFIG_SYS_HZ 1000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x02000000 +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x00200000 + +/* + * Various low-level settings + */ +#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044 + +#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) +#define CONFIG_SYS_HID0_FINAL HID0_ICE + +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_BOOTCS_CFG 0x00047800 +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +#define CONFIG_SYS_CS_BURST 0x000000f0 +#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 + +#define CONFIG_SYS_RESET_ADDRESS 0x00000100 + +#undef FPGA_DEBUG +#undef CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2 +#define CONFIG_FPGA_XILINX 1 +#define CONFIG_FPGA_SPARTAN2 1 +#define CONFIG_FPGA_COUNT 1 + +#endif diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 860ec52921..55471af34a 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -210,6 +210,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index b2e2d41f2b..142471362f 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -208,6 +208,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 405e6d5042..a9b4004c36 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -286,6 +286,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 30a5a319bc..66be725c8a 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -238,7 +238,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#ifdef CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull @@ -249,59 +251,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_PWR 0x5 /* PIXIS Power status register */ -#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VSTAT 0x11 /* VELA Status Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ -#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */ -#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */ -#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */ -#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */ -#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */ -#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */ - -#define PIXIS_VWATCH 0x24 /* Watchdog Register */ -#define PIXIS_LED 0x25 /* LED Register */ - -#define PIXIS_SW(x) 0x20 + (x - 1) * 2 -#define PIXIS_EN(x) 0x21 + (x - 1) * 2 -#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */ -#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */ - -/* old pixis referenced names */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 -#define PIXIS_VSPEED2_TSEC1SER 0x8 -#define PIXIS_VSPEED2_TSEC2SER 0x4 -#define PIXIS_VSPEED2_TSEC3SER 0x2 -#define PIXIS_VSPEED2_TSEC4SER 0x1 -#define PIXIS_VCFGEN1_TSEC1SER 0x20 -#define PIXIS_VCFGEN1_TSEC2SER 0x20 -#define PIXIS_VCFGEN1_TSEC3SER 0x20 -#define PIXIS_VCFGEN1_TSEC4SER 0x20 -#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ - | PIXIS_VSPEED2_TSEC2SER \ - | PIXIS_VSPEED2_TSEC3SER \ - | PIXIS_VSPEED2_TSEC4SER) -#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ - | PIXIS_VCFGEN1_TSEC2SER \ - | PIXIS_VCFGEN1_TSEC3SER \ - | PIXIS_VCFGEN1_TSEC4SER) +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x20 +#endif #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 4e397990cc..0d443ea2d4 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -204,6 +204,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 831a60d9a0..c60a9f7bc7 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */ @@ -113,14 +114,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /* diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 962b29e95b..3e57c0b92f 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -86,6 +86,7 @@ * The Atmel EEPROM uses 16Bit addressing. ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index cf6f7a9e8a..874c20b935 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -94,7 +94,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -123,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 3d59454eb9..f917eb5c25 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -278,6 +278,7 @@ * I2C EEPROM (24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PM520.h b/include/configs/PM520.h index f9687d2743..22de2075f9 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -75,7 +74,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #undef CONFIG_NS8382X -#endif /* Partitions */ #define CONFIG_DOS_PARTITION @@ -111,9 +109,7 @@ #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB -#if defined(CONFIG_MPC5200) #define CONFIG_CMD_PCI -#endif /* @@ -147,12 +143,10 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -301,13 +295,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #if defined(CONFIG_BOOT_ROM) #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 87ea7b6d47..00a12fb833 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -235,6 +235,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 7198632c36..2c048dd0dd 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -215,6 +215,7 @@ * I2C EEPROM (24W16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 89799af3f3..c2fb56c6f9 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -226,6 +226,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 8e9d92872a..44f03dc390 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -414,6 +414,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 25f3a26f35..b69f015c7c 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -252,6 +252,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 3438abaeaa..6da18ebca1 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -430,13 +430,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 2154c7870e..107bff19ff 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -633,13 +633,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 1daa5746ee..7510ab10e4 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -41,6 +41,7 @@ */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -73,7 +74,6 @@ #define CONFIG_SPLASH_SCREEN -#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -98,12 +98,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else /* MGT5100 */ - -#define CONFIG_MII 1 - -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -127,9 +121,7 @@ */ #include -#if defined(CONFIG_MPC5200) - #define CONFIG_CMD_PCI -#endif +#define CONFIG_CMD_PCI #define CONFIG_CMD_BMP #define CONFIG_CMD_EEPROM @@ -176,12 +168,10 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration @@ -326,17 +316,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif - -#if defined (CONFIG_MGT5100) -# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */ -#endif #if CONFIG_TOTAL5200_REV==1 # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 38a1d0deca..9c91fccb11 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -277,6 +277,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 4717869dde..871e4c339e 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -203,6 +203,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index c0179150c2..f06bfe5521 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -273,6 +273,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 1d4ad13ed3..be8c9f82ef 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -280,6 +280,7 @@ * I2C EEPROM (ATMEL 24C04N) */ #define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 5c281a1a66..be9ac6261c 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -241,6 +241,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h index 658e9473bc..cf39aeaaf7 100644 --- a/include/configs/XPEDITE1000.h +++ b/include/configs/XPEDITE1000.h @@ -141,6 +141,7 @@ extern void out32(unsigned int, unsigned long); * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/aev.h b/include/configs/aev.h index 2b4826d90e..98958a6237 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -362,13 +362,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 0fed9ad68e..ee0c14d960 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -118,6 +118,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ @@ -235,11 +236,13 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_FPGA #define CONFIG_CMD_I2C +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS #define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_NET -#define CONFIG_CMD_PCI #undef CONFIG_CMD_NFS +#define CONFIG_CMD_PCI #undef CONFIG_WATCHDOG /* watchdog disabled */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 8cd97b86da..13a941ef63 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -40,6 +40,7 @@ * I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* diff --git a/include/configs/aria.h b/include/configs/aria.h index f89fc570aa..06763c5d96 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -190,7 +190,7 @@ /* * Backward compatible definitions, - * so we do not have to change cpu/mpc512x/fixed_sdram.c + * so we do not have to change arch/ppc/cpu/mpc512x/fixed_sdram.c */ #define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) #define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h new file mode 100644 index 0000000000..7c8281cae7 --- /dev/null +++ b/include/configs/astro_mcf5373l.h @@ -0,0 +1,400 @@ +/* + * Configuration settings for the Sentec Cobra Board. + * + * (C) Copyright 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * configuration for ASTRO "Urmel" board. + * Originating from Cobra5272 configuration, messed up by + * Wolfgang Wegner + * Please do not bother the original author with bug reports + * concerning this file. + */ + +#ifndef _CONFIG_ASTRO_MCF5373L_H +#define _CONFIG_ASTRO_MCF5373L_H + +/* + * set the card type to actually compile for; either of + * the possibilities listed below has to be used! + */ +#define CONFIG_ASTRO_V532 1 + +#if CONFIG_ASTRO_V532 +#define ASTRO_ID 0xF8 +#elif CONFIG_ASTRO_V512 +#define ASTRO_ID 0xFA +#elif CONFIG_ASTRO_TWIN7S2 +#define ASTRO_ID 0xF9 +#elif CONFIG_ASTRO_V912 +#define ASTRO_ID 0xFC +#elif CONFIG_ASTRO_COFDMDUOS2 +#define ASTRO_ID 0xFB +#else +#error No card type defined! +#endif + +/* + * Define processor + * possible values for Urmel board: only Coldfire M5373 processor supported + * (please do not change) + */ + +/* it seems not clear yet which processor defines we should use */ +#define CONFIG_MCF537x /* define processor family */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5373 /* define processor type */ +#define CONFIG_ASTRO5373L /* define board type */ + +/* Command line configuration */ +#include + +/* + * CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from + * a different bootloader that has already performed RAM setup) or + * started directly from flash, which is the regular case for production + * boards. + */ +#ifdef CONFIG_MK_RAM +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_TEXT_BASE 0x40020000 +#define ENABLE_JFFS 0 +#else +#define CONFIG_TEXT_BASE 0x00000000 +#define ENABLE_JFFS 1 +#endif + +/* Define which commmands should be available at u-boot command prompt */ + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_XIMG +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#if ENABLE_JFFS +#define CONFIG_CMD_JFFS2 +#endif +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_FPGA +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* + * Defines processor clock - important for correct timings concerning serial + * interface etc. + * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms + */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ + +#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 +#define CONFIG_SYS_CORE_SRAM 0x80000000 + +#define CONFIG_SYS_UNIFY_CACHE + +/* + * Define baudrate for UART1 (console output, tftp, ...) + * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud + * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * in u-boot command interface + */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (2) +#define CONFIG_SYS_UART2_ALT3_GPIO + +/* + * Watchdog configuration; Watchdog is disabled for running from RAM + * and set to highest possible value else. Beware there is no check + * in the watchdog code to validate the timeout value set here! + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ +#endif + +/* + * Configuration for environment + * Environment is located in the last sector of the flash + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_ENV_OFFSET 0x1FF8000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#else +/* + * environment in RAM - This is used to use a single PC-based application + * to load an image, load U-Boot, load an environment and then start U-Boot + * to execute the commands from the environment. Feedback is done via setting + * and reading memory locations. + */ +#define CONFIG_ENV_ADDR 0x40060000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/* here we put our FPGA configuration... */ +#define CONFIG_MISC_INIT_R 1 + +/* Define user parameters that have to be customized most likely */ + +/* AUTOBOOT settings - booting images automatically by u-boot after power on */ + +/* + * used for autoboot, delay in seconds u-boot will wait before starting + * defined (auto-)boot command, setting to -1 disables delay, setting to + * 0 will too prevent access to u-boot command interface: u-boot then has + * to be reflashed + * beware - watchdog is not serviced during autoboot delay time! + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTDELAY 1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +/* + * The following settings will be contained in the environment block ; if you + * want to use a neutral environment all those settings can be manually set in + * u-boot: 'set' command + */ + +#define _QUOTEME(x) #x +#define QUOTEME(x) _QUOTEME(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loaderversion=11\0" \ + "card_id="QUOTEME(ASTRO_ID)"\0" \ + "alterafile=0\0" \ + "xilinxfile=0\0" \ + "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ + "fpga load 0 0x41000000 $filesize\0" \ + "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ + "fpga load 1 0x41000000 $filesize\0" \ + "env_default=1\0" \ + "env_check=if test $env_default -eq 1;"\ + " then setenv env_default 0;saveenv;fi\0" + +/* + * "update" is a non-standard command that has to be supplied + * by external update.c; This is not included in mainline because + * it needs non-blocking CFI routines. + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ +#else +#if CONFIG_ASTRO_V532 +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&run alteraload&&bootm 0x80000;"\ + "update;reset" +#else +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&bootm 0x80000;update;reset" +#endif +#endif + +/* default bootargs that are considered during boot */ +#define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\ + " loaderversion=$loaderversion" + +#define CONFIG_SYS_PROMPT "URMEL > " + +/* default RAM address for user programs */ +#define CONFIG_SYS_LOAD_ADDR 0x20000 + +#define CONFIG_SYS_LONGHELP + +#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 + +/* End of user parameters to be customized */ + +/* Defines memory range for test */ + +#define CONFIG_SYS_MEMTEST_START 0x40020000 +#define CONFIG_SYS_MEMTEST_END 0x41ffffff + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/* Base register address */ + +#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ + +/* System Conf. Reg. & System Protection Reg. */ + +#define CONFIG_SYS_SCR 0x0003; +#define CONFIG_SYS_SPR 0xffff; + +/* + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_END 0x8000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* + * Chipselect bank definitions + * + * CS0 - Flash 32MB (first 16MB) + * CS1 - Flash 32MB (second half) + * CS2 - FPGA + * CS3 - FPGA + * CS4 - unused + * CS5 - unused + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00ff0001 +#define CONFIG_SYS_CS0_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS1_BASE 0x01000000 +#define CONFIG_SYS_CS1_MASK 0x00ff0001 +#define CONFIG_SYS_CS1_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS2_BASE 0x20000000 +#define CONFIG_SYS_CS2_MASK 0x00ff0001 +#define CONFIG_SYS_CS2_CTRL 0x0000fec0 + +#define CONFIG_SYS_CS3_BASE 0x21000000 +#define CONFIG_SYS_CS3_MASK 0x00ff0001 +#define CONFIG_SYS_CS3_CTRL 0x0000fec0 + +#define CONFIG_SYS_FLASH_BASE 0x00000000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE CONFIG_TEXT_BASE +#else +/* This is mainly used during relocation in start.S */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 + +#if ENABLE_JFFS +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + +#endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 083c030179..80c48847e4 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -126,11 +126,11 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 6627a04f59..cf40d06b88 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -112,11 +112,11 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index de2add7595..92ceb3815b 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -122,11 +122,11 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif @@ -277,6 +277,15 @@ #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ #endif +/* These are for board tests */ +#if 0 +#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100" +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "autoboot in %d seconds: press space to stop\n", bootdelay +#define CONFIG_AUTOBOOT_STOP_STR " " +#endif + /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 4ea2300f4b..59e05650ec 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -119,11 +119,11 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 8ab38bbacb..1e3fdef64a 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -96,12 +96,12 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ - lib_generic/zlib.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ + lib/zlib.o (.text .text.*); \ board/bf561-ezkit/bf561-ezkit.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 0d68ebae2a..8d0bc1232f 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -104,11 +104,11 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index c1179b0aee..bbea3ab009 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -105,11 +105,11 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 1741ed4932..c60401c8fe 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -63,14 +63,10 @@ * Network Settings */ #define ADI_CMDS_NETWORK 1 -/* The next 2 lines are for use with DEV-BF5xx */ #define CONFIG_NET_MULTI -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x28000300 -/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */ -/* #define CONFIG_DRIVER_SMC911X 1 */ -/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 /! AMS1 */ -/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */ +#define CONFIG_SMC911X_16_BIT #define CONFIG_HOSTNAME cm-bf561 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */ @@ -94,6 +90,7 @@ #define CONFIG_ENV_OFFSET 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 1c3ea23c77..330e3ac667 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -331,6 +331,19 @@ from which user programs will be started */ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions * diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index 52df16af14..f7290d6eb4 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -59,7 +59,6 @@ #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -90,8 +89,6 @@ #define CONFIG_NS8382X 1 #endif -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -169,8 +166,6 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) - #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000 #define CONFIG_SYS_NVRAM_SIZE 32*1024 @@ -179,7 +174,6 @@ * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -303,13 +297,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/csb272.h b/include/configs/csb272.h index aed6f50f98..9ded330664 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -171,6 +171,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 24b961f3e1..71eb083e33 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -170,6 +170,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 4be28b26a6..44669ea44d 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -141,7 +141,7 @@ #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* - * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this + * The flash size is autoconfigured, but arch/ppc/cpu/mpc5xxx/cpu_init.c needs this * variable defined */ #define CONFIG_SYS_FLASH_SIZE 0x02000000 diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index a81527ebed..f9cdcbc3ce 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -261,13 +261,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 7c9f71e888..2eef5efa78 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -84,12 +84,12 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ - lib_generic/zlib.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ + lib/zlib.o (.text .text.*); \ board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 841affb7cc..61e3bad4f3 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -224,6 +224,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h new file mode 100644 index 0000000000..1da860261a --- /dev/null +++ b/include/configs/imx27lite-common.h @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2010 Heiko Schocher + * + * based on: + * Copyright (C) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX27LITE_COMMON_CONFIG_H +#define __IMX27LITE_COMMON_CONFIG_H + +/* + * SoC Configuration + */ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX27 +#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Lowlevel configuration + */ +#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ + (ESDCFG_TRC(10) | \ + ESDCFG_TRCD(3) | \ + ESDCFG_TCAS(cas) | \ + ESDCFG_TRRD(1) | \ + ESDCFG_TRAS(5) | \ + ESDCFG_TWR | \ + ESDCFG_TMRD(2) | \ + ESDCFG_TRP(2) | \ + ESDCFG_TXP(3)) + +#define SDRAM_ESDCTL_REGISTER_VAL \ + (ESDCTL_PRCT(0) | \ + ESDCTL_BL | \ + ESDCTL_PWDT(0) | \ + ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ_32 | \ + ESDCTL_COL10 | \ + ESDCTL_ROW13 | \ + ESDCTL_SDE) + +#define SDRAM_ALL_VAL 0xf00 + +#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ +#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 + +#define MPCTL0_VAL 0x1ef15d5 + +#define SPCTL0_VAL 0x043a1c09 + +#define CSCR_VAL 0x33f08107 + +#define PCDR0_VAL 0x120470c3 +#define PCDR1_VAL 0x03030303 +#define PCCR0_VAL 0xffffffff +#define PCCR1_VAL 0xfffffffc + +#define AIPI1_PSR0_VAL 0x20040304 +#define AIPI1_PSR1_VAL 0xdffbfcfb +#define AIPI2_PSR0_VAL 0x07ffc200 +#define AIPI2_PSR1_VAL 0xffffffff + +/* + * Memory Info + */ +/* malloc() len */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) +/* reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +/* memtest start address */ +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ +#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ + +/* + * Serial Driver info + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX27_UART1 +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Flash & Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* Use hardware sector protection */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +/* CS2 Base address */ +#define PHYS_FLASH_1 0xc0000000 +/* Flash Base for U-Boot */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ + CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII +#define CONFIG_NET_MULTI + +/* + * MTD + */ +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_DEVICE + +/* + * NAND + */ +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0xd8000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +/* + * SD/MMC + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_DOS_PARTITION + +/* + * MTD partitions + */ +#define CONFIG_CMD_MTDPARTS + +/* + * U-Boot general configuration + */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer sz */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +/* + * U-Boot commands + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "kernel_addr_r=a0800000\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "rootpath=/opt/eldk-4.2-arm/arm\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm\0" \ + "bootcmd=run net_nfs\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};cp.b ${fileaddr} " \ + xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + +#endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h index ee749ecd2f..72f6e80ede 100644 --- a/include/configs/imx27lite.h +++ b/include/configs/imx27lite.h @@ -20,158 +20,31 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* include common defines/options for all imx27lite related boards */ +#include "imx27lite-common.h" /* * SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_MX27 #define CONFIG_IMX27LITE -#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Lowlevel configuration - */ -#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ - (ESDCFG_TRC(10) | \ - ESDCFG_TRCD(3) | \ - ESDCFG_TCAS(cas) | \ - ESDCFG_TRRD(1) | \ - ESDCFG_TRAS(5) | \ - ESDCFG_TWR | \ - ESDCFG_TMRD(2) | \ - ESDCFG_TRP(2) | \ - ESDCFG_TXP(3)) - -#define SDRAM_ESDCTL_REGISTER_VAL \ - (ESDCTL_PRCT(0) | \ - ESDCTL_BL | \ - ESDCTL_PWDT(0) | \ - ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ_32 | \ - ESDCTL_COL10 | \ - ESDCTL_ROW13 | \ - ESDCTL_SDE) - -#define SDRAM_ALL_VAL 0xf00 - -#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ -#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 - -#define MPCTL0_VAL 0x1ef15d5 - -#define SPCTL0_VAL 0x043a1c09 - -#define CSCR_VAL 0x33f08107 - -#define PCDR0_VAL 0x120470c3 -#define PCDR1_VAL 0x03030303 -#define PCCR0_VAL 0xffffffff -#define PCCR1_VAL 0xfffffffc - -#define AIPI1_PSR0_VAL 0x20040304 -#define AIPI1_PSR1_VAL 0xdffbfcfb -#define AIPI2_PSR0_VAL 0x07ffc200 -#define AIPI2_PSR1_VAL 0xffffffff - -/* - * Memory Info - */ -/* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) -/* reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 -/* memtest start address */ -#define CONFIG_SYS_MEMTEST_START 0xA0000000 -#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ -#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ - -/* - * Serial Driver info - */ -#define CONFIG_MXC_UART -#define CONFIG_SYS_MX27_UART1 -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_HOSTNAME imx27 +#define CONFIG_BOARDNAME "LogicPD imx27lite\n" /* * Flash & Environment */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -/* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -/* Use hardware sector protection */ -#define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */ -/* end of flash */ #define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000) -/* CS2 Base address */ -#define PHYS_FLASH_1 0xc0000000 -/* Flash Base for U-Boot */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -/* Flash size 2MB */ #define PHYS_FLASH_SIZE 0x200000 -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ - CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ #define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f -#define CONFIG_MII -#define CONFIG_NET_MULTI - -/* - * MTD - */ -#define CONFIG_FLASH_CFI_MTD -#define CONFIG_MTD_DEVICE - -/* - * NAND - */ -#define CONFIG_NAND_MXC -#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0xd8000000 -#define CONFIG_JFFS2_NAND -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /* * SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_MXC_MMC #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 -#define CONFIG_DOS_PARTITION /* * MTD partitions */ -#define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" #define MTDPARTS_DEFAULT \ "mtdparts=" \ @@ -186,69 +59,4 @@ "22m(rootfs)," \ "-(userfs)" -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Print buffer sz */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP - -/* - * U-Boot commands - */ -#include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define xstr(s) str(s) -#define str(s) #s - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=imx27/u-boot.bin\0" \ - "kernel_addr_r=a0800000\0" \ - "hostname=imx27\0" \ - "bootfile=imx27/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};cp.b ${fileaddr} " \ - xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - #endif /* __CONFIG_H */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 14f7826705..c5b1565e34 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -366,13 +366,8 @@ static inline void tws_data_config_output(unsigned output) /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/ip04.h b/include/configs/ip04.h new file mode 100644 index 0000000000..425a745408 --- /dev/null +++ b/include/configs/ip04.h @@ -0,0 +1,157 @@ +/* + * U-boot - Configuration file for IP04 board (having BF532 processor) + * + * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com + * + * Copyright (c) 2005-2010 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __CONFIG_IP04_H__ +#define __CONFIG_IP04_H__ + +#include + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf532-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 10000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 40 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 3 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x408 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 +#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_HOSTNAME IP04 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_NO_SROM +#define CONFIG_DM9000_BASE 0x20100000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 2) + + +/* + * Flash Settings + */ +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_SYS_NO_FLASH /* we have only NAND */ + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_PREBOOT "echo starting from spi flash" +#define CONFIG_ENV_OFFSET 0x30000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 + + +/* + * NAND Settings + */ +#define CONFIG_NAND_PLAT +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_READY PF10 +#define BFIN_NAND_WRITE(addr, cmd) \ + do { \ + bfin_write8(addr, cmd); \ + SSYNC(); \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY) +#define NAND_PLAT_INIT() \ + do { \ + bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \ + bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \ + bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \ + bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \ + } while (0) + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R /* needed for MAC address */ +#define CONFIG_UART_CONSOLE 0 + +#undef CONFIG_SHOW_BOOT_PROGRESS +/* Enable this if bootretry required; currently it's disabled */ +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOTCOMMAND "run nandboot" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include + +#endif diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index d0cb1e1d60..6903b36146 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -324,13 +324,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/katmai.h b/include/configs/katmai.h index c013ac4b3c..fb8ccae71b 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -37,6 +37,7 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index a79feec16d..e5537da4af 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -230,7 +230,7 @@ * SDRAM Controller DDR autocalibration values and takes a lot longer * to run than Method_B. * (See the Method_A and Method_B algorithm discription in the file: - * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) + * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A * * DDR Autocalibration Method_B is the default. diff --git a/include/configs/korat.h b/include/configs/korat.h index 026dd0854a..f95df684ea 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -153,6 +153,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 16b464cf6d..3958d09eb9 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -290,7 +290,7 @@ * taken from the orignal Linkstation boot code * * Most of the low level configuration setttings are normally used - * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation. + * in arch/ppc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation. * Low level initialisation is done in board/linkstation/early_init.S * The values below are included for reference purpose only */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 011dd5c81a..6461124e56 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -258,6 +258,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/magnesium.h b/include/configs/magnesium.h new file mode 100644 index 0000000000..4fb7744bae --- /dev/null +++ b/include/configs/magnesium.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010 Heiko Schocher + * + * based on: + * Copyright (C) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* include common defines/options for all imx27lite related boards */ +#include "imx27lite-common.h" + +/* + * SoC Configuration + */ +#define CONFIG_MAGNESIUM +#define CONFIG_HOSTNAME magnesium +#define CONFIG_BOARDNAME "Projectiondesign magnesium\n" + +/* + * Flash & Environment + */ +#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */ +#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000) +#define PHYS_FLASH_SIZE 0x800000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */ + +/* + * NAND + */ +#define CONFIG_SYS_NAND_LARGEPAGE + +/* + * SD/MMC + */ +#define CONFIG_MXC_MCI_REGS_BASE 0x10013000 + +/* + * MTD partitions + */ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=" \ + "physmap-flash.0:" \ + "256k(U-Boot)," \ + "7680k(user)," \ + "128k(env1)," \ + "128k(env2);" \ + "mxc_nand.0:" \ + "128k(IPL-SPL)," \ + "4m(kernel)," \ + "22m(rootfs)," \ + "-(userfs)" + +#endif /* __CONFIG_H */ diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index b29ef9b655..d25e093ac6 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -170,13 +170,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 4a93b58885..73405eabb9 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -63,9 +63,6 @@ #endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ - #define CONFIG_MII #if 0 /* test-only !!! */ #define CONFIG_NET_MULTI 1 @@ -74,10 +71,6 @@ #define CONFIG_NS8382X 1 #endif -#else /* MPC5100 */ - -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -152,12 +145,10 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -288,13 +279,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d002b97510..e085f4a47c 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -82,7 +82,6 @@ */ #include #undef CONFIG_CMD_BDI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS diff --git a/include/configs/ml300.h b/include/configs/ml300.h deleted file mode 100644 index 68d0c85e1a..0000000000 --- a/include/configs/ml300.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * ML300.h: ML300 specific config options - * - * http://www.xilinx.com/ml300 - * - * Derived from : ML2.h - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR - * OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * - * - * (c) Copyright 2002 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* #define DEBUG */ -/* #define ET_DEBUG 1 */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_XILINX_405 1 -#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ - -#define CONFIG_SYSTEMACE 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR -#define CONFIG_SYS_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */ - -/* following are used only if env is in EEPROM */ -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR -#define CONFIG_MISC_INIT_R 1 /* used to call out convert_env() */ -#define CONFIG_ENV_OVERWRITE 1 /* allow users to update ethaddr and serial# */ -#endif - -#include "../board/xilinx/ml300/xparameters.h" - -#define CONFIG_SYS_NO_FLASH 1 /* no flash */ -#define CONFIG_ENV_SIZE XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "console=ttyS0,9600 ip=off " \ - "root=/dev/xsysace/disc0/part3 rw" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_NET - -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_IMLS - - -/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */ -/* 300000000 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_DUART_CHAN 0 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_INIT_CHAN1 1 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0x04000000 -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 903fe6da7e..3626df73df 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -160,6 +160,9 @@ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 + /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index 4bed7ae267..cb7efe7abc 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -42,6 +42,7 @@ * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 18e7cc2a9c..bdc0f7944a 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -138,7 +138,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ @@ -154,7 +153,6 @@ */ #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif -#endif /* * I2C configuration @@ -276,13 +274,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 8e27ebae9e..fb0f576f45 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -102,6 +102,7 @@ at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \ at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \ } +#define I2C_SOFT_DECLARATIONS /* Configure data pin as output */ #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0) /* Configure data pin as input */ @@ -130,7 +131,6 @@ * Command line configuration. */ #include -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 729ca6ac7d..d6b92070a9 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -92,6 +92,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 000ae5cd7d..1f744b875d 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -138,6 +138,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 8ca55d78ec..80a0bc609a 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -61,7 +61,6 @@ #endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -87,7 +86,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif -#endif /* Partitions */ #define CONFIG_MAC_PARTITION @@ -121,9 +119,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE -#ifdef CONFIG_MPC5200 #define CONFIG_CMD_PCI -#endif #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ @@ -166,12 +162,10 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -289,13 +283,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 47bb8c09aa..a0b00e9706 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -28,8 +28,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" @@ -51,26 +49,26 @@ /* clocks */ /* CKGR_MOR - enable main osc. */ #define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ + (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ #define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ + (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_PLLXR_OUT(3) | \ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2 | \ + AT91_PMC_MCKR_PLLADIV_1) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2 | \ + AT91_PMC_MCKR_PLLADIV_1) /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 @@ -79,7 +77,7 @@ /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ #define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ @@ -122,32 +120,32 @@ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) #define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) #define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) #define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ #define CONFIG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) + AT91_RSTC_CR_PROCRST | \ + AT91_RSTC_MR_ERSTL(1) | \ + AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ #define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -180,9 +178,9 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PC12 -#define CONFIG_GREEN_LED AT91_PIN_PC13 -#define CONFIG_YELLOW_LED AT91_PIN_PC15 +#define CONFIG_RED_LED AT91_PIO_PORTC, 12 +#define CONFIG_GREEN_LED AT91_PIO_PORTC, 13 +#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15 #define CONFIG_BOOTDELAY 3 @@ -200,7 +198,6 @@ #include #undef CONFIG_CMD_BDI #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS @@ -236,8 +233,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16 /* NOR flash */ #define CONFIG_SYS_FLASH_CFI 1 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 807dba8f42..f854f3874d 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -215,7 +215,6 @@ #include #undef CONFIG_CMD_BDI #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index b08dcd42de..2472187520 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -150,6 +150,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F @@ -232,7 +233,7 @@ * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory (OCM) for temperary stack until sdram is tested */ -/* see ./cpu/ppc4xx/start.S */ +/* see ./arch/ppc/cpu/ppc4xx/start.S */ #define CONFIG_SYS_TEMP_STACK_OCM 1 /* On Chip Memory location */ @@ -250,7 +251,7 @@ * Taken from PPCBoot board/icecube/icecube.h */ -/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ +/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ #define CONFIG_SYS_EBC_PB0AP 0x04002480 /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */ #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 @@ -268,7 +269,7 @@ * * Taken in part from PPCBoot board/icecube/icecube.h */ -/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ +/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ #define CONFIG_SYS_GPIO0_OSRH 0x55555550 #define CONFIG_SYS_GPIO0_OSRL 0x00000110 #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 242f42fdc3..429b11c196 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -166,6 +166,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sc3.h b/include/configs/sc3.h index a5eca39890..7423663a26 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -251,6 +251,7 @@ */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define I2C_INIT #define I2C_ACTIVE 0 @@ -455,7 +456,7 @@ * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR * - Stackpointer will be located to * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF) - * in cpu/ppc4xx/start.S + * in arch/ppc/cpu/ppc4xx/start.S */ #undef CONFIG_SYS_INIT_DCACHE_CS @@ -494,7 +495,7 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ /* ################################################################################### */ -/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */ +/* These defines will be used in arch/ppc/cpu/ppc4xx/cpu_init.c to setup external chip selects */ /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ /* This chip select accesses the boot device */ diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 5a2ef3aa8c..060026bb64 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -358,13 +358,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 27dda253fb..d377e199d8 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -438,13 +438,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 5a5fbddac3..409a042d05 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -105,11 +105,11 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 92bcdb33fb..d462ed0f1e 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -170,12 +170,10 @@ #define CONFIG_BOOTCOMMAND "run net_nfs" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 42f880785e..0b4dfb8e73 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -37,6 +37,7 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define EXTCLK_33_33 33333333 diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 1a77c71968..3b2aede4fd 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -167,6 +167,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/fdt_support.h b/include/fdt_support.h index 0a9dd0dd84..9a453af34b 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -81,5 +81,8 @@ int fdt_resize(void *blob); int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); +void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); +void fdt_del_node_and_alias(void *blob, const char *alias); + #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 01b7dec188..f9ae15ad42 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008, Freescale Semiconductor, Inc + * Copyright 2007-2008,2010 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -39,6 +39,7 @@ #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#define SYSCTL_RSTA 0x01000000 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -132,6 +133,8 @@ #define WML 0x2e044 #define WML_WRITE 0x00010000 +#define WML_RD_WML_MASK 0xff +#define WML_WR_WML_MASK 0xff0000 #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) @@ -148,7 +151,6 @@ struct fsl_esdhc_cfg { u32 esdhc_base; u32 no_snoop; - u32 clk_enable; }; /* Select the correct accessors depending on endianess */ diff --git a/include/i2c.h b/include/i2c.h index 31088b675a..d828964256 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -127,8 +127,6 @@ typedef struct _mux_device { struct _mux_device *next; } I2C_MUX_DEVICE; -int i2c_mux_add_device(I2C_MUX_DEVICE *dev); - I2C_MUX_DEVICE *i2c_mux_search_device(int id); I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf); int i2x_mux_select_mux(int bus); diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h index 8b2720e951..906eb3d3cd 100644 --- a/include/jffs2/load_kernel.h +++ b/include/jffs2/load_kernel.h @@ -78,5 +78,6 @@ struct mtdids { extern int mtdparts_init(void); extern int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part); +extern struct mtd_device *device_find(u8 type, u8 num); #endif /* load_kernel_h */ diff --git a/include/linux/stat.h b/include/linux/stat.h index 2ce1c25ac3..cef636959e 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -68,7 +68,7 @@ struct stat { #endif /* __PPC__ */ #if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\ - defined (__microblaze__) + defined (__microblaze__) || defined (__nios2__) struct stat { unsigned short st_dev; diff --git a/include/lzma/LzmaDec.h b/include/lzma/LzmaDec.h index 967cdd1018..b7ef6d6bc2 100644 --- a/include/lzma/LzmaDec.h +++ b/include/lzma/LzmaDec.h @@ -26,6 +26,6 @@ #ifndef __LZMADEC_H__FAKE__ #define __LZMADEC_H__FAKE__ -#include "../../lib_generic/lzma/LzmaDec.h" +#include "../../lib/lzma/LzmaDec.h" #endif diff --git a/include/lzma/LzmaTools.h b/include/lzma/LzmaTools.h index 87943c0332..48b0af84d4 100644 --- a/include/lzma/LzmaTools.h +++ b/include/lzma/LzmaTools.h @@ -26,6 +26,6 @@ #ifndef __LZMATOOLS_H__FAKE__ #define __LZMATOOLS_H__FAKE__ -#include "../../lib_generic/lzma/LzmaTools.h" +#include "../../lib/lzma/LzmaTools.h" #endif diff --git a/include/lzma/LzmaTypes.h b/include/lzma/LzmaTypes.h index 86160a42b2..740720cfe9 100644 --- a/include/lzma/LzmaTypes.h +++ b/include/lzma/LzmaTypes.h @@ -31,6 +31,6 @@ */ #define Byte LZByte -#include "../../lib_generic/lzma/Types.h" +#include "../../lib/lzma/Types.h" #endif diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 4dcf90c037..2d343c7b08 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -1,7 +1,7 @@ /* * include/asm-ppc/mpc5xxx.h * - * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx + * Prototypes, etc. for the Motorola MPC5xxx * embedded cpu chips * * 2003 (c) MontaVista, Software, Inc. @@ -33,24 +33,15 @@ #include /* Processor name */ -#if defined(CONFIG_MPC5200) #define CPU_ID_STR "MPC5200" -#elif defined(CONFIG_MGT5100) -#define CPU_ID_STR "MGT5100" -#endif /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 #define _START_OFFSET EXC_OFF_SYS_RESET /* useful macros for manipulating CSx_START/STOP */ -#if defined(CONFIG_MGT5100) -#define START_REG(start) ((start) >> 15) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 15) -#elif defined(CONFIG_MPC5200) #define START_REG(start) ((start) >> 16) #define STOP_REG(start, size) (((start) + (size) - 1) >> 16) -#endif /* Internal memory map */ @@ -70,21 +61,12 @@ #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034) -#define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038) -#define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c) -#define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040) -#define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044) -#define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) -#endif #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) @@ -99,18 +81,12 @@ #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) -#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400) -#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) -#endif #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) @@ -118,22 +94,14 @@ #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000) -#define MPC5XXX_SRAM_SIZE (8*1024) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) #define MPC5XXX_SRAM_SIZE (16*1024) -#endif /* SDRAM Controller */ #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010) -#endif #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) /* Clock Distribution Module */ @@ -155,19 +123,15 @@ #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) -#if defined(CONFIG_MPC5200) #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) -#endif -#if defined(CONFIG_MPC5200) /* XLB Arbiter registers */ #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) -#endif /* GPIO registers */ #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) @@ -242,14 +206,6 @@ #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68) -#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c) -#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70) -#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74) -#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78) -#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) @@ -262,7 +218,6 @@ #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) -#endif /* Interrupt Controller registers */ #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) @@ -495,31 +450,16 @@ struct mpc5xxx_mmap_ctl { volatile u32 cs4_stop; volatile u32 cs5_start; /* 0x002c */ volatile u32 cs5_stop; -#if defined(CONFIG_MGT5100) - volatile u32 sdram_start; /* 0x0034 */ - volatile u32 sdram_stop; /* 0x0038 */ - volatile u32 pci1_start; /* 0x003c */ - volatile u32 pci1_stop; /* 0x0040 */ - volatile u32 pci2_start; /* 0x0044 */ - volatile u32 pci2_stop; /* 0x0048 */ -#elif defined(CONFIG_MPC5200) volatile u32 sdram0; /* 0x0034 */ volatile u32 sdram1; /* 0x0038 */ volatile u32 dummy1[4]; /* 0x003c */ -#endif volatile u32 boot_start; /* 0x004c */ volatile u32 boot_stop; -#if defined(CONFIG_MGT5100) - volatile u32 addecr; /* 0x0054 */ -#elif defined(CONFIG_MPC5200) volatile u32 ipbi_ws_ctrl; /* 0x0054 */ -#endif -#if defined(CONFIG_MPC5200) volatile u32 cs6_start; /* 0x0058 */ volatile u32 cs6_stop; volatile u32 cs7_start; /* 0x0060 */ volatile u32 cs7_stop; -#endif }; /* Clock distribution module */ @@ -546,12 +486,7 @@ struct mpc5xxx_sdram { volatile u32 ctrl; volatile u32 config1; volatile u32 config2; -#if defined(CONFIG_MGT5100) - volatile u32 xlbsel; - volatile u32 dummy[31]; -#else volatile u32 dummy[32]; -#endif volatile u32 sdelay; }; @@ -564,12 +499,10 @@ struct mpc5xxx_lpb { volatile u32 cs5_cfg; volatile u32 cs_ctrl; volatile u32 cs_status; -#if defined(CONFIG_MPC5200) volatile u32 cs6_cfg; volatile u32 cs7_cfg; volatile u32 cs_burst; volatile u32 cs_deadcycle; -#endif }; diff --git a/include/mpc86xx.h b/include/mpc86xx.h index c6f30f9fd5..eb85d60cad 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -83,5 +83,7 @@ static __inline__ unsigned long get_l2cr (void) return l2cr_val; } +void setup_ddr_bat(phys_addr_t dram_size); + #endif /* _ASMLANGUAGE */ #endif /* __MPC86xx_H__ */ diff --git a/include/mtd_node.h b/include/mtd_node.h new file mode 100644 index 0000000000..5aae0859da --- /dev/null +++ b/include/mtd_node.h @@ -0,0 +1,11 @@ +#ifndef _NODE_INFO +#define _NODE_INFO + +/* + * Info we use to search for a flash node in DTB. + */ +struct node_info { + const char *compat; /* compatible string */ + int type; /* mtd flash type */ +}; +#endif diff --git a/include/post.h b/include/post.h index 9fcd3cec2f..ff83bce6b4 100644 --- a/include/post.h +++ b/include/post.h @@ -53,6 +53,11 @@ #define POST_FAIL_SAVE 0x80 +#define POST_BEFORE 1 +#define POST_AFTER 0 +#define POST_PASSED 1 +#define POST_FAILED 0 + #ifndef __ASSEMBLY__ struct post_test { diff --git a/include/ppc440.h b/include/ppc440.h index e60fa13905..5f87d2c600 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -68,6 +68,12 @@ #define CPR0_SPCID 0x0120 #define CPR0_ICFG 0x0140 +/* 440EPX boot strap options */ +#define BOOT_STRAP_OPTION_A 0x00000000 +#define BOOT_STRAP_OPTION_B 0x00000001 +#define BOOT_STRAP_OPTION_D 0x00000003 +#define BOOT_STRAP_OPTION_E 0x00000004 + /* 440gx sdr register definations */ #define SDR0_SDSTP0 0x0020 /* */ #define SDR0_SDSTP1 0x0021 /* */ diff --git a/include/spartan3.h b/include/spartan3.h index 30b1c2d62d..d5a589d099 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -57,6 +57,7 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; + Xilinx_bwr_fn bwr; /* block write function */ } Xilinx_Spartan3_Slave_Serial_fns; /* Device Image Sizes diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index 61bce67914..07badbfc5a 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -25,7 +25,7 @@ #ifndef _UBOOT_CRC_H #define _UBOOT_CRC_H -/* lib_generic/crc32.c */ +/* lib/crc32.c */ uint32_t crc32 (uint32_t, const unsigned char *, uint); uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); diff --git a/include/xilinx.h b/include/xilinx.h index d0799bc572..2cb2e5b6aa 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -100,5 +100,6 @@ typedef int (*Xilinx_busy_fn)( int cookie ); typedef int (*Xilinx_abort_fn)( int cookie ); typedef int (*Xilinx_pre_fn)( int cookie ); typedef int (*Xilinx_post_fn)( int cookie ); +typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie ); #endif /* _XILINX_H_ */ diff --git a/lib_generic/Makefile b/lib/Makefile similarity index 100% rename from lib_generic/Makefile rename to lib/Makefile diff --git a/lib_generic/addr_map.c b/lib/addr_map.c similarity index 100% rename from lib_generic/addr_map.c rename to lib/addr_map.c diff --git a/lib_generic/bzlib.c b/lib/bzlib.c similarity index 100% rename from lib_generic/bzlib.c rename to lib/bzlib.c diff --git a/lib_generic/bzlib_crctable.c b/lib/bzlib_crctable.c similarity index 100% rename from lib_generic/bzlib_crctable.c rename to lib/bzlib_crctable.c diff --git a/lib_generic/bzlib_decompress.c b/lib/bzlib_decompress.c similarity index 100% rename from lib_generic/bzlib_decompress.c rename to lib/bzlib_decompress.c diff --git a/lib_generic/bzlib_huffman.c b/lib/bzlib_huffman.c similarity index 100% rename from lib_generic/bzlib_huffman.c rename to lib/bzlib_huffman.c diff --git a/lib_generic/bzlib_private.h b/lib/bzlib_private.h similarity index 100% rename from lib_generic/bzlib_private.h rename to lib/bzlib_private.h diff --git a/lib_generic/bzlib_randtable.c b/lib/bzlib_randtable.c similarity index 100% rename from lib_generic/bzlib_randtable.c rename to lib/bzlib_randtable.c diff --git a/lib_generic/circbuf.c b/lib/circbuf.c similarity index 100% rename from lib_generic/circbuf.c rename to lib/circbuf.c diff --git a/lib_generic/crc16.c b/lib/crc16.c similarity index 100% rename from lib_generic/crc16.c rename to lib/crc16.c diff --git a/lib_generic/crc32.c b/lib/crc32.c similarity index 100% rename from lib_generic/crc32.c rename to lib/crc32.c diff --git a/lib_generic/ctype.c b/lib/ctype.c similarity index 100% rename from lib_generic/ctype.c rename to lib/ctype.c diff --git a/lib_generic/display_options.c b/lib/display_options.c similarity index 100% rename from lib_generic/display_options.c rename to lib/display_options.c diff --git a/lib_generic/div64.c b/lib/div64.c similarity index 100% rename from lib_generic/div64.c rename to lib/div64.c diff --git a/lib_generic/gunzip.c b/lib/gunzip.c similarity index 100% rename from lib_generic/gunzip.c rename to lib/gunzip.c diff --git a/lib_generic/ldiv.c b/lib/ldiv.c similarity index 100% rename from lib_generic/ldiv.c rename to lib/ldiv.c diff --git a/libfdt/Makefile b/lib/libfdt/Makefile similarity index 100% rename from libfdt/Makefile rename to lib/libfdt/Makefile diff --git a/libfdt/README b/lib/libfdt/README similarity index 100% rename from libfdt/README rename to lib/libfdt/README diff --git a/libfdt/fdt.c b/lib/libfdt/fdt.c similarity index 100% rename from libfdt/fdt.c rename to lib/libfdt/fdt.c diff --git a/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c similarity index 100% rename from libfdt/fdt_ro.c rename to lib/libfdt/fdt_ro.c diff --git a/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c similarity index 100% rename from libfdt/fdt_rw.c rename to lib/libfdt/fdt_rw.c diff --git a/libfdt/fdt_strerror.c b/lib/libfdt/fdt_strerror.c similarity index 100% rename from libfdt/fdt_strerror.c rename to lib/libfdt/fdt_strerror.c diff --git a/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c similarity index 100% rename from libfdt/fdt_sw.c rename to lib/libfdt/fdt_sw.c diff --git a/libfdt/fdt_wip.c b/lib/libfdt/fdt_wip.c similarity index 100% rename from libfdt/fdt_wip.c rename to lib/libfdt/fdt_wip.c diff --git a/libfdt/libfdt_internal.h b/lib/libfdt/libfdt_internal.h similarity index 100% rename from libfdt/libfdt_internal.h rename to lib/libfdt/libfdt_internal.h diff --git a/lib_generic/lmb.c b/lib/lmb.c similarity index 100% rename from lib_generic/lmb.c rename to lib/lmb.c diff --git a/lib_generic/lzma/LzmaDec.c b/lib/lzma/LzmaDec.c similarity index 100% rename from lib_generic/lzma/LzmaDec.c rename to lib/lzma/LzmaDec.c diff --git a/lib_generic/lzma/LzmaDec.h b/lib/lzma/LzmaDec.h similarity index 100% rename from lib_generic/lzma/LzmaDec.h rename to lib/lzma/LzmaDec.h diff --git a/lib_generic/lzma/LzmaTools.c b/lib/lzma/LzmaTools.c similarity index 100% rename from lib_generic/lzma/LzmaTools.c rename to lib/lzma/LzmaTools.c diff --git a/lib_generic/lzma/LzmaTools.h b/lib/lzma/LzmaTools.h similarity index 100% rename from lib_generic/lzma/LzmaTools.h rename to lib/lzma/LzmaTools.h diff --git a/lib_generic/lzma/Makefile b/lib/lzma/Makefile similarity index 100% rename from lib_generic/lzma/Makefile rename to lib/lzma/Makefile diff --git a/lib_generic/lzma/README.txt b/lib/lzma/README.txt similarity index 100% rename from lib_generic/lzma/README.txt rename to lib/lzma/README.txt diff --git a/lib_generic/lzma/Types.h b/lib/lzma/Types.h similarity index 100% rename from lib_generic/lzma/Types.h rename to lib/lzma/Types.h diff --git a/lib_generic/lzma/history.txt b/lib/lzma/history.txt similarity index 100% rename from lib_generic/lzma/history.txt rename to lib/lzma/history.txt diff --git a/lib_generic/lzma/import_lzmasdk.sh b/lib/lzma/import_lzmasdk.sh similarity index 100% rename from lib_generic/lzma/import_lzmasdk.sh rename to lib/lzma/import_lzmasdk.sh diff --git a/lib_generic/lzma/license.txt b/lib/lzma/license.txt similarity index 100% rename from lib_generic/lzma/license.txt rename to lib/lzma/license.txt diff --git a/lib_generic/lzma/lzma.txt b/lib/lzma/lzma.txt similarity index 100% rename from lib_generic/lzma/lzma.txt rename to lib/lzma/lzma.txt diff --git a/lib_generic/lzo/Makefile b/lib/lzo/Makefile similarity index 100% rename from lib_generic/lzo/Makefile rename to lib/lzo/Makefile diff --git a/lib_generic/lzo/lzo1x_decompress.c b/lib/lzo/lzo1x_decompress.c similarity index 100% rename from lib_generic/lzo/lzo1x_decompress.c rename to lib/lzo/lzo1x_decompress.c diff --git a/lib_generic/lzo/lzodefs.h b/lib/lzo/lzodefs.h similarity index 100% rename from lib_generic/lzo/lzodefs.h rename to lib/lzo/lzodefs.h diff --git a/lib_generic/md5.c b/lib/md5.c similarity index 100% rename from lib_generic/md5.c rename to lib/md5.c diff --git a/lib_generic/net_utils.c b/lib/net_utils.c similarity index 100% rename from lib_generic/net_utils.c rename to lib/net_utils.c diff --git a/lib_generic/rbtree.c b/lib/rbtree.c similarity index 100% rename from lib_generic/rbtree.c rename to lib/rbtree.c diff --git a/lib_generic/sha1.c b/lib/sha1.c similarity index 100% rename from lib_generic/sha1.c rename to lib/sha1.c diff --git a/lib_generic/sha256.c b/lib/sha256.c similarity index 100% rename from lib_generic/sha256.c rename to lib/sha256.c diff --git a/lib_generic/string.c b/lib/string.c similarity index 100% rename from lib_generic/string.c rename to lib/string.c diff --git a/lib_generic/strmhz.c b/lib/strmhz.c similarity index 100% rename from lib_generic/strmhz.c rename to lib/strmhz.c diff --git a/lib_generic/time.c b/lib/time.c similarity index 100% rename from lib_generic/time.c rename to lib/time.c diff --git a/lib_generic/vsprintf.c b/lib/vsprintf.c similarity index 100% rename from lib_generic/vsprintf.c rename to lib/vsprintf.c diff --git a/lib_generic/zlib.c b/lib/zlib.c similarity index 100% rename from lib_generic/zlib.c rename to lib/zlib.c diff --git a/lib_arm/config.mk b/lib_arm/config.mk deleted file mode 100644 index 3c078df3c1..0000000000 --- a/lib_arm/config.mk +++ /dev/null @@ -1,66 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -CROSS_COMPILE ?= arm-linux- - -ifeq ($(BOARD),omap2420h4) -STANDALONE_LOAD_ADDR = 0x80300000 -else -ifeq ($(SOC),omap3) -STANDALONE_LOAD_ADDR = 0x80300000 -else -STANDALONE_LOAD_ADDR = 0xc100000 -endif -endif - -PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ - -# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: -PLATFORM_CPPFLAGS += $(call cc-option,-marm,) - -# Try if EABI is supported, else fall back to old API, -# i. e. for example: -# - with ELDK 4.2 (EABI supported), use: -# -mabi=aapcs-linux -mno-thumb-interwork -# - with ELDK 4.1 (gcc 4.x, no EABI), use: -# -mabi=apcs-gnu -mno-thumb-interwork -# - with ELDK 3.1 (gcc 3.x), use: -# -mapcs-32 -mno-thumb-interwork -PLATFORM_CPPFLAGS += $(call cc-option,\ - -mabi=aapcs-linux -mno-thumb-interwork,\ - $(call cc-option,\ - -mapcs-32,\ - $(call cc-option,\ - -mabi=apcs-gnu,\ - )\ - ) $(call cc-option,-mno-thumb-interwork,)\ - ) - -# For EABI, make sure to provide raise() -ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) -# This file is parsed several times; make sure to add only once. -ifeq (,$(findstring lib_arm/eabi_compat.o,$(PLATFORM_LIBS))) -PLATFORM_LIBS += $(OBJTREE)/lib_arm/eabi_compat.o -endif -endif -LDSCRIPT := $(SRCTREE)/cpu/$(CPU)/u-boot.lds diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c deleted file mode 100644 index 21fff334a0..0000000000 --- a/lib_blackfin/board.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * U-boot - board.c First C file to be called contains init routines - * - * Copyright (c) 2005-2008 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_CMD_NAND -#include /* cannot even include nand.h if it isnt configured */ -#endif - -#ifdef CONFIG_BITBANGMII -#include -#endif - -#if defined(CONFIG_POST) -#include -int post_flag; -#endif - -DECLARE_GLOBAL_DATA_PTR; - -const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")"; - -__attribute__((always_inline)) -static inline void serial_early_puts(const char *s) -{ -#ifdef CONFIG_DEBUG_EARLY_SERIAL - serial_puts("Early: "); - serial_puts(s); -#endif -} - -static int display_banner(void) -{ - printf("\n\n%s\n\n", version_string); - printf("CPU: ADSP " MK_STR(CONFIG_BFIN_CPU) " " - "(Detected Rev: 0.%d) " - "(%s boot)\n", - bfin_revid(), - get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE)); - return 0; -} - -static int init_baudrate(void) -{ - char baudrate[15]; - int i = getenv_r("baudrate", baudrate, sizeof(baudrate)); - gd->bd->bi_baudrate = gd->baudrate = (i > 0) - ? simple_strtoul(baudrate, NULL, 10) - : CONFIG_BAUDRATE; - return 0; -} - -static void display_global_data(void) -{ -#ifdef CONFIG_DEBUG_EARLY_SERIAL - bd_t *bd; - bd = gd->bd; - printf(" gd: %p\n", gd); - printf(" |-flags: %lx\n", gd->flags); - printf(" |-board_type: %lx\n", gd->board_type); - printf(" |-baudrate: %lu\n", gd->baudrate); - printf(" |-have_console: %lx\n", gd->have_console); - printf(" |-ram_size: %lx\n", gd->ram_size); - printf(" |-reloc_off: %lx\n", gd->reloc_off); - printf(" |-env_addr: %lx\n", gd->env_addr); - printf(" |-env_valid: %lx\n", gd->env_valid); - printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt)); - printf(" \\-bd: %p\n", gd->bd); - printf(" |-bi_baudrate: %x\n", bd->bi_baudrate); - printf(" |-bi_ip_addr: %lx\n", bd->bi_ip_addr); - printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); - printf(" |-bi_memstart: %lx\n", bd->bi_memstart); - printf(" |-bi_memsize: %lx\n", bd->bi_memsize); - printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart); - printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize); - printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset); -#endif -} - -#define CPLB_PAGE_SIZE (4 * 1024 * 1024) -#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) -void init_cplbtables(void) -{ - volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; - volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA; - uint32_t extern_memory; - size_t i; - - void icplb_add(uint32_t addr, uint32_t data) - { - *(ICPLB_ADDR + i) = addr; - *(ICPLB_DATA + i) = data; - } - void dcplb_add(uint32_t addr, uint32_t data) - { - *(DCPLB_ADDR + i) = addr; - *(DCPLB_DATA + i) = data; - } - - /* populate a few common entries ... we'll let - * the memory map and cplb exception handler do - * the rest of the work. - */ - i = 0; - ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0; - ICPLB_DATA = (uint32_t *)ICPLB_DATA0; - DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0; - DCPLB_DATA = (uint32_t *)DCPLB_DATA0; - - icplb_add(0xFFA00000, L1_IMEMORY); - dcplb_add(0xFF800000, L1_DMEMORY); - ++i; - - if (CONFIG_MEM_SIZE) { - uint32_t mbase = CONFIG_SYS_MONITOR_BASE; - uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN; - mbase &= CPLB_PAGE_MASK; - mend &= CPLB_PAGE_MASK; - - icplb_add(mbase, SDRAM_IKERNEL); - dcplb_add(mbase, SDRAM_DKERNEL); - ++i; - - /* - * If the monitor crosses a 4 meg boundary, we'll need - * to lock two entries for it. We assume it doesn't - * cross two 4 meg boundaries ... - */ - if (mbase != mend) { - icplb_add(mend, SDRAM_IKERNEL); - dcplb_add(mend, SDRAM_DKERNEL); - ++i; - } - } - - icplb_add(0x20000000, SDRAM_INON_CHBL); - dcplb_add(0x20000000, SDRAM_EBIU); - ++i; - - /* Add entries for the rest of external RAM up to the bootrom */ - extern_memory = 0; - -#ifdef CONFIG_DEBUG_NULL_PTR - icplb_add(extern_memory, (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB); - dcplb_add(extern_memory, (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB); - ++i; - icplb_add(extern_memory, SDRAM_IKERNEL); - dcplb_add(extern_memory, SDRAM_DKERNEL); - extern_memory += CPLB_PAGE_SIZE; - ++i; -#endif - - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) { - icplb_add(extern_memory, SDRAM_IGENERIC); - dcplb_add(extern_memory, SDRAM_DGENERIC); - extern_memory += CPLB_PAGE_SIZE; - ++i; - } - while (i < 16) { - icplb_add(0, 0); - dcplb_add(0, 0); - ++i; - } -} - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - -extern int exception_init(void); -extern int irq_init(void); -extern int timer_init(void); - -void board_init_f(ulong bootflag) -{ - ulong addr; - bd_t *bd; - char buf[32]; - -#ifdef CONFIG_BOARD_EARLY_INIT_F - serial_early_puts("Board early init flash\n"); - board_early_init_f(); -#endif - - serial_early_puts("Init CPLB tables\n"); - init_cplbtables(); - - serial_early_puts("Exceptions setup\n"); - exception_init(); - -#ifndef CONFIG_ICACHE_OFF - serial_early_puts("Turn on ICACHE\n"); - icache_enable(); -#endif -#ifndef CONFIG_DCACHE_OFF - serial_early_puts("Turn on DCACHE\n"); - dcache_enable(); -#endif - -#ifdef DEBUG - if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd)) - hang(); -#endif - serial_early_puts("Init global data\n"); - gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR); - memset((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE); - - /* Board data initialization */ - addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t)); - - /* Align to 4 byte boundary */ - addr &= ~(4 - 1); - bd = (bd_t *) addr; - gd->bd = bd; - memset((void *)bd, 0, sizeof(bd_t)); - - bd->bi_r_version = version_string; - bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU); - bd->bi_board_name = BFIN_BOARD_NAME; - bd->bi_vco = get_vco(); - bd->bi_cclk = get_cclk(); - bd->bi_sclk = get_sclk(); - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - - /* Initialize */ - serial_early_puts("IRQ init\n"); - irq_init(); - serial_early_puts("Environment init\n"); - env_init(); - serial_early_puts("Baudrate init\n"); - init_baudrate(); - serial_early_puts("Serial init\n"); - serial_init(); - serial_early_puts("Console init flash\n"); - console_init_f(); - serial_early_puts("End of early debugging\n"); - display_banner(); - - checkboard(); - timer_init(); - - printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco())); - printf("Core: %s MHz, ", strmhz(buf, get_cclk())); - printf("System: %s MHz\n", strmhz(buf, get_sclk())); - - printf("RAM: "); - print_size(bd->bi_memsize, "\n"); -#if defined(CONFIG_POST) - post_init_f(); - post_bootmode_init(); - post_run(NULL, POST_ROM | post_bootmode_get(0)); -#endif - - board_init_r((gd_t *) gd, 0x20000010); -} - -static void board_net_init_r(bd_t *bd) -{ -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#ifdef CONFIG_CMD_NET - char *s; - - if ((s = getenv("bootfile")) != NULL) - copy_filename(BootFile, s, sizeof(BootFile)); - - bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - - printf("Net: "); - eth_initialize(gd->bd); -#endif -} - -void board_init_r(gd_t * id, ulong dest_addr) -{ - char *s; - bd_t *bd; - gd = id; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - bd = gd->bd; - -#if defined(CONFIG_POST) - post_output_backlog(); - post_reloc(); -#endif - - /* initialize malloc() area */ - mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); - -#if !defined(CONFIG_SYS_NO_FLASH) - /* Initialize the flash and protect u-boot by default */ - extern flash_info_t flash_info[]; - puts("Flash: "); - ulong size = flash_init(); - print_size(size, "\n"); - flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - bd->bi_flashsize = size; - bd->bi_flashoffset = 0; -#else - bd->bi_flashstart = 0; - bd->bi_flashsize = 0; - bd->bi_flashoffset = 0; -#endif - -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); /* go init the NAND */ -#endif - -#ifdef CONFIG_GENERIC_MMC - puts("MMC: "); - mmc_initialize(bd); -#endif - - /* relocate environment function pointers etc. */ - env_relocate(); - - /* Initialize stdio devices */ - stdio_init(); - jumptable_init(); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r(); - -#ifdef CONFIG_CMD_KGDB - puts("KGDB: "); - kgdb_init(); -#endif - -#ifdef CONFIG_STATUS_LED - status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); - status_led_set(STATUS_LED_CRASH, STATUS_LED_OFF); -#endif - - /* Initialize from environment */ - if ((s = getenv("loadaddr")) != NULL) - load_addr = simple_strtoul(s, NULL, 16); - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r(); -#endif - - board_net_init_r(bd); - - display_global_data(); - -#if defined(CONFIG_POST) - if (post_flag) - post_run(NULL, POST_RAM | post_bootmode_get(0)); -#endif - - if (bfin_os_log_check()) { - puts("\nLog buffer from operating system:\n"); - bfin_os_log_dump(); - puts("\n"); - } - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) - main_loop(); -} - -void hang(void) -{ -#ifdef CONFIG_STATUS_LED - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - status_led_set(STATUS_LED_CRASH, STATUS_LED_BLINKING); -#endif - puts("### ERROR ### Please RESET the board ###\n"); - while (1) - /* If a JTAG emulator is hooked up, we'll automatically trigger - * a breakpoint in it. If one isn't, this is just a NOP. - */ - asm("emuexcpt;"); -} diff --git a/lib_blackfin/config.mk b/lib_blackfin/config.mk deleted file mode 100644 index 323d28f068..0000000000 --- a/lib_blackfin/config.mk +++ /dev/null @@ -1,72 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -CROSS_COMPILE ?= bfin-uclinux- - -STANDALONE_LOAD_ADDR = 0x1000 - -CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) -CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) -CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET))) -CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE))) - -PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic -PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN - -LDFLAGS += --gc-sections -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections - -ifneq (,$(CONFIG_BFIN_CPU)) -PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) -endif - -ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) -ALL += $(obj)u-boot.ldr -endif -ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) -CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o -else -CREATE_LDR_ENV = -endif - -SYM_PREFIX = _ - -LDR_FLAGS-y := -LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J - -LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE)) -LDR_FLAGS += --use-vmas -LDR_FLAGS += --initcode $(obj)cpu/$(CPU)/initcode.o -ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART) -LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \ - --punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o -endif -ifneq (,$(findstring s,$(MAKEFLAGS))) -LDR_FLAGS += --quiet -endif - -LDR_FLAGS += $(LDR_FLAGS-y) - -ifeq ($(wildcard $(TOPDIR)/board/$(BOARD)/u-boot.lds*),) -LDSCRIPT = $(obj)lib_$(ARCH)/u-boot.lds.S -endif diff --git a/lib_blackfin/u-boot.lds.S b/lib_blackfin/u-boot.lds.S deleted file mode 100644 index 3be341fad0..0000000000 --- a/lib_blackfin/u-boot.lds.S +++ /dev/null @@ -1,154 +0,0 @@ -/* - * U-boot - u-boot.lds.S - * - * Copyright (c) 2005-2008 Analog Device Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#undef ALIGN -#undef ENTRY -#undef bfin - -#ifndef LDS_BOARD_TEXT -# define LDS_BOARD_TEXT -#endif - -/* If we don't actually load anything into L1 data, this will avoid - * a syntax error. If we do actually load something into L1 data, - * we'll get a linker memory load error (which is what we'd want). - * This is here in the first place so we can quickly test building - * for different CPU's which may lack non-cache L1 data. - */ -#ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 -#endif - -/* The 0xC offset is so we don't clobber the tiny LDR jump block. */ -#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 -# define L1_CODE_ORIGIN L1_INST_SRAM -#else -# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC -#endif - -OUTPUT_ARCH(bfin) - -MEMORY -{ -#if CONFIG_MEM_SIZE - ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN -# define ram_code ram -# define ram_data ram -#else -# define ram_code l1_code -# define ram_data l1_data -#endif - l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE - l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE -} - -ENTRY(_start) -SECTIONS -{ - .text.pre : - { - cpu/blackfin/start.o (.text .text.*) - - LDS_BOARD_TEXT - } >ram_code - - .text.init : - { - cpu/blackfin/initcode.o (.text .text.*) - } >ram_code - __initcode_lma = LOADADDR(.text.init); - __initcode_len = SIZEOF(.text.init); - - .text : - { - *(.text .text.*) - } >ram_code - - .rodata : - { - . = ALIGN(4); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } >ram_data - - .data : - { - . = ALIGN(256); - *(.data .data.*) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } >ram_data - - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram_data - - .text_l1 : - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text) - . = ALIGN(4); - __etext_l1 = .; - } >l1_code AT>ram_code - __text_l1_lma = LOADADDR(.text_l1); - __text_l1_len = SIZEOF(.text_l1); - ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!") - - .data_l1 : - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - *(.l1.bss) - . = ALIGN(4); - __edata_l1 = .; - } >l1_data AT>ram_data - __data_l1_lma = LOADADDR(.data_l1); - __data_l1_len = SIZEOF(.data_l1); - ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!") - - .bss : - { - . = ALIGN(4); - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss .bss.*) - *(COMMON) - } >ram_data - __bss_vma = ADDR(.bss); - __bss_len = SIZEOF(.bss); -} diff --git a/lib_m68k/cache.c b/lib_m68k/cache.c deleted file mode 100644 index 84fb6c2fbc..0000000000 --- a/lib_m68k/cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -void flush_cache (ulong start_addr, ulong size) -{ - /* Must be implemented for all M68k processors with copy-back data cache */ -} diff --git a/lib_nios2/board.c b/lib_nios2/board.c deleted file mode 100644 index 41d3297190..0000000000 --- a/lib_nios2/board.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif -#if defined(CONFIG_SYS_NIOS_EPCSBASE) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - - -typedef int (init_fnc_t) (void); - - -/************************************************************************ - * Initialization sequence * - ***********************************************************************/ - -init_fnc_t *init_sequence[] = { - -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, /* Call board-specific init code early.*/ -#endif -#if defined(CONFIG_SYS_NIOS_EPCSBASE) - epcs_reset, -#endif - - env_init, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, - NULL, /* Terminate this list */ -}; - - -/***********************************************************************/ -void board_init (void) -{ - bd_t *bd; - init_fnc_t **init_fnc_ptr; - - /* Pointer is writable since we allocated a register for it. - * Nios treats CONFIG_SYS_GBL_DATA_OFFSET as an address. - */ - gd = (gd_t *)CONFIG_SYS_GBL_DATA_OFFSET; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - - memset( gd, 0, CONFIG_SYS_GBL_DATA_SIZE ); - - gd->bd = (bd_t *)(gd+1); /* At end of global data */ - gd->baudrate = CONFIG_BAUDRATE; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; -#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) - bd->bi_sramstart= CONFIG_SYS_SRAM_BASE; - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -#endif - bd->bi_baudrate = CONFIG_BAUDRATE; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - WATCHDOG_RESET (); - if ((*init_fnc_ptr) () != 0) { - hang (); - } - } - - WATCHDOG_RESET (); - - /* The Malloc area is immediately below the monitor copy in RAM */ - mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); - - WATCHDOG_RESET (); - bd->bi_flashsize = flash_init(); - - WATCHDOG_RESET (); - env_relocate(); - - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - - WATCHDOG_RESET (); - stdio_init(); - jumptable_init(); - console_init_r(); - - WATCHDOG_RESET (); - interrupt_init (); - -#if defined(CONFIG_BOARD_LATE_INIT) - board_late_init (); -#endif - - /* main_loop */ - for (;;) { - WATCHDOG_RESET (); - main_loop (); - } -} - - -/***********************************************************************/ - -void hang (void) -{ - disable_interrupts (); - puts("### ERROR ### Please reset board ###\n"); - for (;;); -} diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c deleted file mode 100644 index 675bfac63a..0000000000 --- a/lib_nios2/bootm.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) -{ - void (*kernel)(void) = (void (*)(void))images->ep; - - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - - /* flushes data and instruction caches before calling the kernel */ - flush_dcache (0,CONFIG_SYS_DCACHE_SIZE); - flush_icache (0,CONFIG_SYS_ICACHE_SIZE); - - /* For now we assume the Microtronix linux ... which only - * needs to be called ;-) - */ - kernel (); - /* does not return */ - - return 1; -} diff --git a/lib_sh/config.mk b/lib_sh/config.mk deleted file mode 100644 index fa5369fd08..0000000000 --- a/lib_sh/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -CROSS_COMPILE ?= sh4-linux- - -STANDALONE_LOAD_ADDR = 0x8C000000 -ifeq ($(CPU),sh2) -STANDALONE_LOAD_ADDR += -EB -endif - -PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ -PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE) - -LDSCRIPT := $(SRCTREE)/cpu/$(CPU)/u-boot.lds diff --git a/mkconfig b/mkconfig index 0f7f13e3a4..d3109e412c 100755 --- a/mkconfig +++ b/mkconfig @@ -42,30 +42,28 @@ if [ "$SRCTREE" != "$OBJTREE" ] ; then mkdir -p ${OBJTREE}/include2 cd ${OBJTREE}/include2 rm -f asm - ln -s ${SRCTREE}/include/asm-$2 asm - LNPREFIX="../../include2/asm/" + ln -s ${SRCTREE}/arch/$2/include/asm asm + LNPREFIX=${SRCTREE}/arch/$2/include/asm/ cd ../include - rm -rf asm-$2 rm -f asm - mkdir asm-$2 - ln -s asm-$2 asm + ln -s ${SRCTREE}/arch/$2/include/asm asm else cd ./include rm -f asm - ln -s asm-$2 asm + ln -s ../arch/$2/include/asm asm fi -rm -f asm-$2/arch +rm -f asm/arch if [ -z "$6" -o "$6" = "NULL" ] ; then - ln -s ${LNPREFIX}arch-$3 asm-$2/arch + ln -s ${LNPREFIX}arch-$3 asm/arch else - ln -s ${LNPREFIX}arch-$6 asm-$2/arch + ln -s ${LNPREFIX}arch-$6 asm/arch fi if [ "$2" = "arm" ] ; then - rm -f asm-$2/proc - ln -s ${LNPREFIX}proc-armv asm-$2/proc + rm -f asm/proc + ln -s ${LNPREFIX}proc-armv asm/proc fi # diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index f37425eba1..fce4582c25 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -68,11 +68,11 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)cache.S: @rm -f $(obj)cache.S - ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/cache.S $(obj)cache.S $(obj)gpio.c: @rm -f $(obj)gpio.c - ln -s $(SRCTREE)/cpu/ppc4xx/gpio.c $(obj)gpio.c + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/gpio.c $(obj)gpio.c $(obj)ndfc.c: @rm -f $(obj)ndfc.c @@ -80,11 +80,11 @@ $(obj)ndfc.c: $(obj)resetvec.S: @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S $(obj)start.S: @rm -f $(obj)start.S - ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S # from board directory $(obj)memory.c: diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile index 5fcf2905af..48fde1d1da 100644 --- a/nand_spl/board/amcc/bamboo/Makefile +++ b/nand_spl/board/amcc/bamboo/Makefile @@ -66,11 +66,11 @@ $(obj)ndfc.c: $(obj)resetvec.S: @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S $(obj)start.S: @rm -f $(obj)start.S - ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S # from board directory $(obj)init.S: diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile index f77e459448..0012a9c99b 100644 --- a/nand_spl/board/amcc/canyonlands/Makefile +++ b/nand_spl/board/amcc/canyonlands/Makefile @@ -71,11 +71,11 @@ $(obj)ndfc.c: $(obj)resetvec.S: @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S $(obj)start.S: @rm -f $(obj)start.S - ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S # from board directory $(obj)init.S: diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index bc21744019..de4980a55c 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -62,15 +62,15 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)44x_spd_ddr2.c: $(obj)ecc.h @rm -f $(obj)44x_spd_ddr2.c - ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c $(obj)cache.S: @rm -f $(obj)cache.S - ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/cache.S $(obj)cache.S $(obj)ecc.h: @rm -f $(obj)ecc.h - ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/ecc.h $(obj)ecc.h $(obj)ndfc.c: @rm -f $(obj)ndfc.c @@ -78,11 +78,11 @@ $(obj)ndfc.c: $(obj)resetvec.S: @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S $(obj)start.S: @rm -f $(obj)start.S - ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S # from nand_spl directory $(obj)nand_boot.c: diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile index 54ea7c7e51..e6f96fd3bc 100644 --- a/nand_spl/board/amcc/sequoia/Makefile +++ b/nand_spl/board/amcc/sequoia/Makefile @@ -62,7 +62,7 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)denali_data_eye.c: @rm -f $(obj)denali_data_eye.c - ln -s $(SRCTREE)/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c $(obj)ndfc.c: @rm -f $(obj)ndfc.c @@ -70,11 +70,11 @@ $(obj)ndfc.c: $(obj)resetvec.S: @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S $(obj)start.S: @rm -f $(obj)start.S - ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S # from board directory $(obj)init.S: diff --git a/nand_spl/board/freescale/mpc8313erdb/Makefile b/nand_spl/board/freescale/mpc8313erdb/Makefile index a13e7e2f1f..a23176c78a 100644 --- a/nand_spl/board/freescale/mpc8313erdb/Makefile +++ b/nand_spl/board/freescale/mpc8313erdb/Makefile @@ -65,7 +65,7 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files $(obj)start.S: - ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $(obj)start.S $(obj)nand_boot_fsl_elbc.c: ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ @@ -81,16 +81,16 @@ $(obj)ns16550.c: ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c $(obj)nand_init.c: - ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c $(obj)cache.c: - ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c $(obj)time.c: - ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c + ln -sf $(SRCTREE)/arch/ppc/lib/time.c $(obj)time.c $(obj)ticks.S: - ln -sf $(SRCTREE)/lib_ppc/ticks.S $(obj)ticks.S + ln -sf $(SRCTREE)/arch/ppc/lib/ticks.S $(obj)ticks.S ######################################################################### diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile index a13e7e2f1f..a23176c78a 100644 --- a/nand_spl/board/freescale/mpc8315erdb/Makefile +++ b/nand_spl/board/freescale/mpc8315erdb/Makefile @@ -65,7 +65,7 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files $(obj)start.S: - ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $(obj)start.S $(obj)nand_boot_fsl_elbc.c: ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ @@ -81,16 +81,16 @@ $(obj)ns16550.c: ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c $(obj)nand_init.c: - ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c $(obj)cache.c: - ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c $(obj)time.c: - ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c + ln -sf $(SRCTREE)/arch/ppc/lib/time.c $(obj)time.c $(obj)ticks.S: - ln -sf $(SRCTREE)/lib_ppc/ticks.S $(obj)ticks.S + ln -sf $(SRCTREE)/arch/ppc/lib/ticks.S $(obj)ticks.S ######################################################################### diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index 7ed9d619dc..7f75afcb50 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -29,7 +29,7 @@ PAD_TO := 0xfff01000 include $(TOPDIR)/config.mk -LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL @@ -64,15 +64,15 @@ $(nandobj)u-boot-spl: $(OBJS) $(obj)cache.c: @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c $(obj)cpu_init_nand.c: @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c @@ -93,19 +93,19 @@ $(obj)ns16550.c: $(obj)resetvec.S: @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S $(obj)fixed_ivor.S: @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S $(obj)start.S: $(obj)fixed_ivor.S @rm -f $(obj)start.S - ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S $(obj)tlb.c: @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c $(obj)tlb_table.c: @rm -f $(obj)tlb_table.c diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index 7ed9d619dc..7f75afcb50 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -29,7 +29,7 @@ PAD_TO := 0xfff01000 include $(TOPDIR)/config.mk -LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL @@ -64,15 +64,15 @@ $(nandobj)u-boot-spl: $(OBJS) $(obj)cache.c: @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c $(obj)cpu_init_nand.c: @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c @@ -93,19 +93,19 @@ $(obj)ns16550.c: $(obj)resetvec.S: @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S $(obj)fixed_ivor.S: @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S $(obj)start.S: $(obj)fixed_ivor.S @rm -f $(obj)start.S - ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S $(obj)tlb.c: @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c $(obj)tlb_table.c: @rm -f $(obj)tlb_table.c diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c index e03065699c..047da3470f 100644 --- a/nand_spl/board/freescale/mpc8569mds/nand_boot.c +++ b/nand_spl/board/freescale/mpc8569mds/nand_boot.c @@ -20,7 +20,7 @@ */ #include #include -#include +#include #include #include #include diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile index 0e13d5de26..c1dcf05f3b 100644 --- a/nand_spl/board/freescale/mx31pdk/Makefile +++ b/nand_spl/board/freescale/mx31pdk/Makefile @@ -12,7 +12,7 @@ SOBJS = start.o lowlevel_init.o COBJS = nand_boot_fsl_nfc.o SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c -SRCS += $(SRCTREE)/cpu/arm1136/start.S +SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) @@ -40,7 +40,7 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) ######################################################################### -$(obj)%.o: $(SRCTREE)/cpu/arm1136/%.S +$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S $(CC) $(AFLAGS) -c -o $@ $< $(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index 7ed9d619dc..7f75afcb50 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -29,7 +29,7 @@ PAD_TO := 0xfff01000 include $(TOPDIR)/config.mk -LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL @@ -64,15 +64,15 @@ $(nandobj)u-boot-spl: $(OBJS) $(obj)cache.c: @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c $(obj)cpu_init_nand.c: @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c @@ -93,19 +93,19 @@ $(obj)ns16550.c: $(obj)resetvec.S: @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S $(obj)fixed_ivor.S: @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S $(obj)start.S: $(obj)fixed_ivor.S @rm -f $(obj)start.S - ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S $(obj)tlb.c: @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c + ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c $(obj)tlb_table.c: @rm -f $(obj)tlb_table.c diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c index af442ea270..16a756c386 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c @@ -20,7 +20,7 @@ */ #include #include -#include +#include #include #include #include diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile index ae71f6695f..62aa58351c 100644 --- a/nand_spl/board/karo/tx25/Makefile +++ b/nand_spl/board/karo/tx25/Makefile @@ -33,7 +33,7 @@ SOBJS = start.o lowlevel_init.o COBJS = nand_boot_fsl_nfc.o SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c -SRCS += $(SRCTREE)/cpu/arm926ejs/start.S +SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) @@ -61,7 +61,7 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) ######################################################################### -$(obj)%.o: $(SRCTREE)/cpu/arm926ejs/%.S +$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S $(CC) $(AFLAGS) -c -o $@ $< $(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S diff --git a/nand_spl/board/samsung/smdk6400/Makefile b/nand_spl/board/samsung/smdk6400/Makefile index 0fdda25ac5..9cb4853318 100644 --- a/nand_spl/board/samsung/smdk6400/Makefile +++ b/nand_spl/board/samsung/smdk6400/Makefile @@ -67,12 +67,12 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)start.S: @rm -f $@ - @ln -s $(TOPDIR)/cpu/arm1176/start.S $@ + @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@ # from SoC directory $(obj)cpu_init.S: @rm -f $@ - @ln -s $(TOPDIR)/cpu/arm1176/s3c64xx/cpu_init.S $@ + @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@ # from board directory $(obj)lowlevel_init.S: diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile index 6920fe886b..3ad6250db5 100644 --- a/nand_spl/board/sheldon/simpc8313/Makefile +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -66,7 +66,7 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(obj)start.S: @rm -f $@ - ln -s $(SRCTREE)/cpu/mpc83xx/start.S $@ + ln -s $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $@ $(obj)nand_boot_fsl_elbc.c: @rm -f $@ @@ -86,19 +86,19 @@ $(obj)ns16550.c: $(obj)nand_init.c: @rm -f $@ - ln -s $(SRCTREE)/cpu/mpc83xx/nand_init.c $@ + ln -s $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $@ $(obj)cache.c: @rm -f $@ - ln -s $(SRCTREE)/lib_ppc/cache.c $@ + ln -s $(SRCTREE)/arch/ppc/lib/cache.c $@ $(obj)time.c: @rm -f $@ - ln -s $(SRCTREE)/lib_ppc/time.c $@ + ln -s $(SRCTREE)/arch/ppc/lib/time.c $@ $(obj)ticks.S: @rm -f $@ - ln -s $(SRCTREE)/lib_ppc/ticks.S $@ + ln -s $(SRCTREE)/arch/ppc/lib/ticks.S $@ ######################################################################### diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index f4040a7cf9..bfae30e460 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -27,9 +27,9 @@ #include #include #ifdef CONFIG_MX31 -#include +#include #else -#include +#include #endif #include #include diff --git a/onenand_ipl/board/apollon/Makefile b/onenand_ipl/board/apollon/Makefile index 193efffb56..6f1df01135 100644 --- a/onenand_ipl/board/apollon/Makefile +++ b/onenand_ipl/board/apollon/Makefile @@ -46,7 +46,7 @@ $(onenandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)start.S: @rm -f $@ - ln -s $(SRCTREE)/cpu/$(CPU)/start.S $@ + ln -s $(SRCTREE)/$(CPUDIR)/start.S $@ # from onenand_ipl directory $(obj)onenand_ipl.h: diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c index ecb87b53ac..6ff5c79aa9 100644 --- a/post/cpu/ppc4xx/spr.c +++ b/post/cpu/ppc4xx/spr.c @@ -69,7 +69,7 @@ static struct { /* Additional Special-Purpose Registers. * The values must match the initialization - * values from cpu/ppc4xx/start.S + * values from arch/ppc/cpu/ppc4xx/start.S */ {0x30, "PID", 0x00000000, 0x00000000}, {0x3a, "CSRR0", 0x00000000, 0x00000000}, diff --git a/post/post.c b/post/post.c index b29eb87fc2..00e835325c 100644 --- a/post/post.c +++ b/post/post.c @@ -231,6 +231,12 @@ static void post_get_flags (int *test_flags) } } +void __show_post_progress (unsigned int test_num, int before, int result) +{ +} +void show_post_progress (unsigned int, int, int) + __attribute__((weak, alias("__show_post_progress"))); + static int post_run_single (struct post_test *test, int test_flags, int flags, unsigned int i) { @@ -248,13 +254,18 @@ static int post_run_single (struct post_test *test, if (test_flags & POST_PREREL) post_log_mark_start ( test->testid ); else - post_log ("POST %s ", test->cmd); + post_log ("POST %s ", test->cmd); } + show_post_progress(i, POST_BEFORE, POST_FAILED); + if (test_flags & POST_PREREL) { - if ((*test->test) (flags) == 0) + if ((*test->test) (flags) == 0) { post_log_mark_succ ( test->testid ); + show_post_progress(i, POST_AFTER, POST_PASSED); + } else { + show_post_progress(i, POST_AFTER, POST_FAILED); if (test_flags & POST_CRITICAL) gd->flags |= GD_FLG_POSTFAIL; if (test_flags & POST_STOP) @@ -264,6 +275,7 @@ static int post_run_single (struct post_test *test, if ((*test->test) (flags) != 0) { post_log ("FAILED\n"); show_boot_progress (-32); + show_post_progress(i, POST_AFTER, POST_FAILED); if (test_flags & POST_CRITICAL) gd->flags |= GD_FLG_POSTFAIL; if (test_flags & POST_STOP) @@ -271,6 +283,7 @@ static int post_run_single (struct post_test *test, } else post_log ("PASSED\n"); + show_post_progress(i, POST_AFTER, POST_PASSED); } if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) { diff --git a/tools/Makefile b/tools/Makefile index 743505f929..749d994230 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -68,9 +68,9 @@ BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) # Source files which exist outside the tools directory EXT_OBJ_FILES-y += common/env_embedded.o EXT_OBJ_FILES-y += common/image.o -EXT_OBJ_FILES-y += lib_generic/crc32.o -EXT_OBJ_FILES-y += lib_generic/md5.o -EXT_OBJ_FILES-y += lib_generic/sha1.o +EXT_OBJ_FILES-y += lib/crc32.o +EXT_OBJ_FILES-y += lib/md5.o +EXT_OBJ_FILES-y += lib/sha1.o # Source files located in the tools directory OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o @@ -122,7 +122,7 @@ endif # now $(obj) is defined HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) +HOSTSRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y))) LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y)) @@ -136,7 +136,7 @@ NOPEDOBJS := $(addprefix $(obj),$(NOPED_OBJ_FILES-y)) HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \ -idirafter $(OBJTREE)/include2 \ -idirafter $(OBJTREE)/include \ - -I $(SRCTREE)/libfdt \ + -I $(SRCTREE)/lib/libfdt \ -I $(SRCTREE)/tools \ -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC \ -D__KERNEL_STRICT_NAMES @@ -196,10 +196,10 @@ $(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o $(obj)%.o: $(SRCTREE)/common/%.c $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< -$(obj)%.o: $(SRCTREE)/lib_generic/%.c +$(obj)%.o: $(SRCTREE)/lib/%.c $(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $< -$(obj)%.o: $(SRCTREE)/libfdt/%.c +$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< subdirs: diff --git a/tools/env/Makefile b/tools/env/Makefile index 9629ee58ef..2df631e98a 100644 --- a/tools/env/Makefile +++ b/tools/env/Makefile @@ -41,7 +41,7 @@ clean: rm -f $(obj)fw_printenv $(obj)crc32.c $(obj)crc32.c: - ln -s $(src)../../lib_generic/crc32.c $(obj)crc32.c + ln -s $(src)../../lib/crc32.c $(obj)crc32.c ######################################################################### diff --git a/tools/imls/Makefile b/tools/imls/Makefile index 9b2afb0762..8407277071 100644 --- a/tools/imls/Makefile +++ b/tools/imls/Makefile @@ -23,9 +23,9 @@ include $(TOPDIR)/config.mk BIN_FILES-y += imls # Source files which exist outside the tools/imls directory -EXT_OBJ_FILES-y += lib_generic/crc32.o -EXT_OBJ_FILES-y += lib_generic/md5.o -EXT_OBJ_FILES-y += lib_generic/sha1.o +EXT_OBJ_FILES-y += lib/crc32.o +EXT_OBJ_FILES-y += lib/md5.o +EXT_OBJ_FILES-y += lib/sha1.o EXT_OBJ_FILES-y += common/image.o # Source files located in the tools/imls directory @@ -41,7 +41,7 @@ LIBFDT_OBJ_FILES-y += fdt_wip.o # now $(obj) is defined SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) SRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) +SRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y))) LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y)) @@ -52,7 +52,7 @@ LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y)) HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \ -idirafter $(OBJTREE)/include2 \ -idirafter $(OBJTREE)/include \ - -I $(SRCTREE)/libfdt \ + -I $(SRCTREE)/lib/libfdt \ -I $(SRCTREE)/tools \ -DUSE_HOSTCC -D__KERNEL_STRICT_NAMES @@ -78,10 +78,10 @@ $(obj)imls.o: $(SRCTREE)/tools/imls/imls.c $(obj)%.o: $(SRCTREE)/common/%.c $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< -$(obj)%.o: $(SRCTREE)/lib_generic/%.c +$(obj)%.o: $(SRCTREE)/lib/%.c $(CC) -g $(HOSTCFLAGS) -c -o $@ $< -$(obj)%.o: $(SRCTREE)/libfdt/%.c +$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< clean: diff --git a/tools/mkimage.c b/tools/mkimage.c index f71f8e732b..f5859d7764 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -37,6 +37,7 @@ struct mkimage_params params = { .type = IH_TYPE_KERNEL, .comp = IH_COMP_GZIP, .dtc = MKIMAGE_DEFAULT_DTC_OPTIONS, + .imagename = "", }; /* @@ -144,7 +145,7 @@ main (int argc, char **argv) { int ifd = -1; struct stat sbuf; - unsigned char *ptr; + char *ptr; int retval = 0; struct image_type_params *tparams = NULL; @@ -200,8 +201,7 @@ main (int argc, char **argv) case 'a': if (--argc <= 0) usage (); - params.addr = strtoul (*++argv, - (char **)&ptr, 16); + params.addr = strtoul (*++argv, &ptr, 16); if (*ptr) { fprintf (stderr, "%s: invalid load address %s\n", @@ -218,8 +218,7 @@ main (int argc, char **argv) case 'e': if (--argc <= 0) usage (); - params.ep = strtoul (*++argv, - (char **)&ptr, 16); + params.ep = strtoul (*++argv, &ptr, 16); if (*ptr) { fprintf (stderr, "%s: invalid entry point %s\n",