mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 00:49:43 +00:00
Merge tag 'u-boot-rockchip-20230814' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add board: rk3568 EmbedFire Lubancat 2 - Fixes for rk3568 clock and pinctrl; - Fixes for rk3308 clock and uart; - rk3328 rock64 updates; - Video fix on veyron board;
This commit is contained in:
Tom Rini
commit
832148f675
25 changed files with 1085 additions and 119 deletions
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@ -178,6 +178,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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rk3566-soquartz-cm4.dtb \
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rk3566-soquartz-model-a.dtb \
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rk3568-evb.dtb \
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rk3568-lubancat-2.dtb \
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rk3568-nanopi-r5c.dtb \
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rk3568-nanopi-r5s.dtb \
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rk3568-odroid-m1.dtb \
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@ -12,6 +12,31 @@
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&uart0 {
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bootph-all;
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clock-frequency = <24000000>;
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status = "okay";
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};
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&pinctrl {
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bootph-some-ram;
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uart0 {
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bootph-some-ram;
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};
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rtc {
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bootph-some-ram;
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};
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};
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&uart0_xfer {
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bootph-some-ram;
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};
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&uart0_cts {
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bootph-some-ram;
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};
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&uart0_rts {
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bootph-some-ram;
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};
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&rtc_32k {
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bootph-some-ram;
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};
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@ -54,7 +54,7 @@
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};
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&spi0 {
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spi_flash: spiflash@0 {
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spi_flash: flash@0 {
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bootph-all;
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};
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};
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@ -345,7 +345,7 @@
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&spi0 {
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status = "okay";
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spiflash@0 {
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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@ -26,6 +26,12 @@
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0x0 0xff720000 0x0 0x1000
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0x0 0xff798000 0x0 0x1000>;
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};
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rng: rng@ff060000 {
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compatible = "rockchip,cryptov1-rng";
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reg = <0x0 0xff060000 0x0 0x4000>;
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status = "okay";
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};
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};
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&cru {
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27
arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
Normal file
27
arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
Normal file
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@ -0,0 +1,27 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2023 Rockchip Electronics Co., Ltd
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* (C) Copyright 2023 Andy Yan <andyshrk@163.com>
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*/
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#include "rk356x-u-boot.dtsi"
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/ {
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chosen {
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stdout-path = &uart2;
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};
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};
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&sdhci {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
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};
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&uart2 {
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bootph-all;
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clock-frequency = <24000000>;
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status = "okay";
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};
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733
arch/arm/dts/rk3568-lubancat-2.dts
Normal file
733
arch/arm/dts/rk3568-lubancat-2.dts
Normal file
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@ -0,0 +1,733 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,vop2.h>
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#include "rk3568.dtsi"
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/ {
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model = "EmbedFire LubanCat 2";
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compatible = "embedfire,lubancat-2", "rockchip,rk3568";
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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mmc0 = &sdmmc0;
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mmc1 = &sdhci;
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};
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chosen: chosen {
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stdout-path = "serial2:1500000n8";
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};
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leds {
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compatible = "gpio-leds";
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user_led: user-led {
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label = "user_led";
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linux,default-trigger = "heartbeat";
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default-state = "on";
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gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&user_led_pin>;
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};
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};
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hdmi-con {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi_out_con>;
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};
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};
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};
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dc_5v: dc-5v-regulator {
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compatible = "regulator-fixed";
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regulator-name = "dc_5v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vcc3v3_sys: vcc3v3-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc5v0_sys>;
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};
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vcc5v0_sys: vcc5v0-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_5v>;
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};
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vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
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compatible = "regulator-fixed";
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regulator-name = "m2_pcie_3v3";
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enable-active-high;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&vcc3v3_m2_pcie_en>;
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pinctrl-names = "default";
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startup-delay-us = <200000>;
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vin-supply = <&vcc5v0_sys>;
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};
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vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator {
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compatible = "regulator-fixed";
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regulator-name = "minipcie_3v3";
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enable-active-high;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&vcc3v3_mini_pcie_en>;
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pinctrl-names = "default";
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startup-delay-us = <5000>;
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vin-supply = <&vcc5v0_sys>;
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};
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vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb20_host";
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enable-active-high;
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gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&vcc5v0_usb20_host_en>;
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pinctrl-names = "default";
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};
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vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb30_host";
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enable-active-high;
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gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&vcc5v0_usb30_host_en>;
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pinctrl-names = "default";
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};
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vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_otg_vbus";
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enable-active-high;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&vcc5v0_otg_vbus_en>;
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pinctrl-names = "default";
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};
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};
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&combphy0 {
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status = "okay";
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};
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&combphy1 {
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status = "okay";
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};
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&combphy2 {
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status = "okay";
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};
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&cpu0 {
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cpu-supply = <&vdd_cpu>;
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};
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&cpu1 {
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cpu-supply = <&vdd_cpu>;
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};
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&cpu2 {
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cpu-supply = <&vdd_cpu>;
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};
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&cpu3 {
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cpu-supply = <&vdd_cpu>;
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};
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&gpu {
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mali-supply = <&vdd_gpu>;
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status = "okay";
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};
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&hdmi {
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avdd-0v9-supply = <&vdda0v9_image>;
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avdd-1v8-supply = <&vcca1v8_image>;
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status = "okay";
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};
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&hdmi_in {
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hdmi_in_vp0: endpoint {
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remote-endpoint = <&vp0_out_hdmi>;
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};
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};
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&hdmi_out {
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hdmi_out_con: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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&hdmi_sound {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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vdd_cpu: regulator@1c {
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compatible = "tcs,tcs4525";
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reg = <0x1c>;
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fcs,suspend-voltage-selector = <1>;
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regulator-name = "vdd_cpu";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1150000>;
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regulator-ramp-delay = <2300>;
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vin-supply = <&vcc5v0_sys>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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rk809: pmic@20 {
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compatible = "rockchip,rk809";
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reg = <0x20>;
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interrupt-parent = <&gpio0>;
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interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
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assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
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||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
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||||
#clock-cells = <1>;
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clock-names = "mclk";
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clocks = <&cru I2S1_MCLKOUT_TX>;
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pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
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||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
wakeup-source;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
|
||||
tx_delay = <0x22>;
|
||||
rx_delay = <0x0e>;
|
||||
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
|
||||
tx_delay = <0x21>;
|
||||
rx_delay = <0x0e>;
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gic {
|
||||
mbi-ranges = <94 31>, <229 31>, <289 31>;
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_m2_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_mini_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm10 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm14 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&spi3 {
|
||||
pinctrl-0 = <&spi3m1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m1_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
|
||||
assigned-clock-rates = <200000000>, <24000000>, <200000000>;
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
supports-emmc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
max-frequency = <150000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB OTG/USB Host_1 USB 2.0 Comb */
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb30_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_otg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB Host_2/USB Host_3 USB 2.0 Comb */
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb20_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */
|
||||
&usb_host0_xhci {
|
||||
phys = <&usb2phy0_otg>;
|
||||
phy-names = "usb2-phy";
|
||||
extcon = <&usb2phy0>;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB3.0 Host */
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
user_led_pin: user-status-led-pin {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
|
||||
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -126,12 +126,11 @@
|
|||
|
||||
&sdhci {
|
||||
bootph-pre-ram;
|
||||
status = "okay";
|
||||
max-frequency = <200000000>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bootph-pre-ram;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
|
||||
|
|
|
|||
|
|
@ -189,6 +189,21 @@ enum {
|
|||
DCLK_VOP_DIV_SHIFT = 0,
|
||||
DCLK_VOP_DIV_MASK = 0xff,
|
||||
|
||||
/* CRU_CLKSEL_CON10 */
|
||||
/* CRU_CLKSEL_CON13 */
|
||||
/* CRU_CLKSEL_CON16 */
|
||||
/* CRU_CLKSEL_CON19 */
|
||||
/* CRU_CLKSEL_CON22 */
|
||||
CLK_UART_PLL_SEL_SHIFT = 13,
|
||||
CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT,
|
||||
CLK_UART_PLL_SEL_DPLL = 0,
|
||||
CLK_UART_PLL_SEL_VPLL0,
|
||||
CLK_UART_PLL_SEL_VPLL1,
|
||||
CLK_UART_PLL_SEL_480M,
|
||||
CLK_UART_PLL_SEL_24M,
|
||||
CLK_UART_DIV_CON_SHIFT = 0,
|
||||
CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL25_CON */
|
||||
/* CRU_CLK_SEL26_CON */
|
||||
/* CRU_CLK_SEL27_CON */
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
# include <asm/arch-rockchip/cru_rk3288.h>
|
||||
#elif defined(CONFIG_ROCKCHIP_RK3399)
|
||||
# include <asm/arch-rockchip/cru_rk3399.h>
|
||||
#elif defined(CONFIG_ROCKCHIP_RK3568)
|
||||
#include <asm/arch-rockchip/cru_rk3568.h>
|
||||
#endif
|
||||
|
||||
/* CRU_GLB_RST_ST */
|
||||
|
|
|
|||
|
|
@ -106,6 +106,8 @@ struct rk3568_cru {
|
|||
unsigned int emmc_con[2];/* Address Offset: 0x0598 */
|
||||
};
|
||||
|
||||
#define rockchip_cru rk3568_cru
|
||||
|
||||
check_member(rk3568_cru, mode_con00, 0xc0);
|
||||
check_member(rk3568_cru, softrst_con[0], 0x400);
|
||||
|
||||
|
|
@ -493,7 +495,7 @@ enum {
|
|||
|
||||
/* CRU_CLK_SEL81_CON */
|
||||
CPLL_25M_DIV_SHIFT = 8,
|
||||
CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT,
|
||||
CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT,
|
||||
CPLL_50M_DIV_SHIFT = 0,
|
||||
CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT,
|
||||
|
||||
|
|
|
|||
|
|
@ -359,6 +359,7 @@ config ROCKCHIP_RV1126
|
|||
select PMIC_RK8XX
|
||||
select BOARD_LATE_INIT
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply OF_LIBFDT_OVERLAY
|
||||
imply TPL_DM
|
||||
imply TPL_LIBCOMMON_SUPPORT
|
||||
imply TPL_LIBGENERIC_SUPPORT
|
||||
|
|
|
|||
|
|
@ -280,15 +280,5 @@ void spl_board_init(void)
|
|||
if (cru->glb_rst_st != 0)
|
||||
rk3399_force_power_on_reset();
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) {
|
||||
/*
|
||||
* Turning the eMMC and SPI back on (if disabled via the Qseven
|
||||
* BIOS_ENABLE) signal is done through a always-on regulator).
|
||||
*/
|
||||
if (regulators_enable_boot_on(false))
|
||||
debug("%s: Cannot enable boot on regulator\n",
|
||||
__func__);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -112,19 +112,6 @@ void board_init_f(ulong dummy)
|
|||
{
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_DEBUG_UART
|
||||
/*
|
||||
* Debug UART can be used from here if required:
|
||||
*
|
||||
* debug_uart_init();
|
||||
* printch('a');
|
||||
* printhex8(0x1234);
|
||||
* printascii("string");
|
||||
*/
|
||||
debug_uart_init();
|
||||
debug("\nspl:debug uart enabled in %s\n", __func__);
|
||||
#endif
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
ret = spl_early_init();
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ F: configs/orangepi-rk3399_defconfig
|
|||
F: arch/arm/dts/rk3399-u-boot.dtsi
|
||||
F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
|
||||
|
||||
RADXA ROCK 4C+
|
||||
ROCK-4C+
|
||||
M: FUKAUMI Naoki <naoki@radxa.com>
|
||||
S: Maintained
|
||||
F: configs/rock-4c-plus-rk3399_defconfig
|
||||
|
|
|
|||
|
|
@ -7,6 +7,13 @@ F: configs/evb-rk3568_defconfig
|
|||
F: arch/arm/dts/rk3568-evb-boot.dtsi
|
||||
F: arch/arm/dts/rk3568-evb.dts
|
||||
|
||||
Lubancat-2
|
||||
M: Andy Yan <andyshrk@163.com>
|
||||
S: Maintained
|
||||
F: configs/lubancat-2-rk3568_defconfig
|
||||
F: arch/arm/dts/rk3568-lubancat-2.dts
|
||||
F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
|
||||
|
||||
NANOPI-R5C
|
||||
M: Tianling Shen <cnsztl@gmail.com>
|
||||
S: Maintained
|
||||
|
|
|
|||
85
configs/lubancat-2-rk3568_defconfig
Normal file
85
configs/lubancat-2-rk3568_defconfig
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00a00000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
# CONFIG_SPI_FLASH is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
CONFIG_EFI_VAR_BUF_SIZE=16384
|
||||
|
|
@ -72,8 +72,11 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
|||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
|
|
|
|||
|
|
@ -95,6 +95,7 @@ List of mainline supported Rockchip boards:
|
|||
|
||||
* rk3568
|
||||
- Rockchip Evb-RK3568 (evb-rk3568)
|
||||
- EmbedFire Lubancat 2 (lubancat-2-rk3568_defconfig)
|
||||
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
|
||||
- Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig)
|
||||
- Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ static ulong rk3308_i2c_get_clk(struct clk *clk)
|
|||
}
|
||||
|
||||
con = readl(&cru->clksel_con[con_id]);
|
||||
div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
|
||||
div = (con & CLK_I2C_DIV_CON_MASK) >> CLK_I2C_DIV_CON_SHIFT;
|
||||
|
||||
return DIV_TO_RATE(priv->dpll_hz, div);
|
||||
}
|
||||
|
|
@ -314,7 +314,7 @@ static ulong rk3308_saradc_get_clk(struct clk *clk)
|
|||
u32 div, con;
|
||||
|
||||
con = readl(&cru->clksel_con[34]);
|
||||
div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
|
||||
div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
|
||||
|
||||
return DIV_TO_RATE(OSC_HZ, div);
|
||||
}
|
||||
|
|
@ -342,7 +342,7 @@ static ulong rk3308_tsadc_get_clk(struct clk *clk)
|
|||
u32 div, con;
|
||||
|
||||
con = readl(&cru->clksel_con[33]);
|
||||
div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
|
||||
div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
|
||||
|
||||
return DIV_TO_RATE(OSC_HZ, div);
|
||||
}
|
||||
|
|
@ -385,7 +385,7 @@ static ulong rk3308_spi_get_clk(struct clk *clk)
|
|||
}
|
||||
|
||||
con = readl(&cru->clksel_con[con_id]);
|
||||
div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
|
||||
div = (con & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
|
||||
|
||||
return DIV_TO_RATE(priv->dpll_hz, div);
|
||||
}
|
||||
|
|
@ -429,7 +429,7 @@ static ulong rk3308_pwm_get_clk(struct clk *clk)
|
|||
u32 div, con;
|
||||
|
||||
con = readl(&cru->clksel_con[29]);
|
||||
div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
|
||||
div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
|
||||
|
||||
return DIV_TO_RATE(priv->dpll_hz, div);
|
||||
}
|
||||
|
|
@ -451,6 +451,58 @@ static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz)
|
|||
return rk3308_pwm_get_clk(clk);
|
||||
}
|
||||
|
||||
static ulong rk3308_uart_get_clk(struct clk *clk)
|
||||
{
|
||||
struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
struct rk3308_cru *cru = priv->cru;
|
||||
u32 div, pll_sel, con, con_id, parent;
|
||||
|
||||
switch (clk->id) {
|
||||
case SCLK_UART0:
|
||||
con_id = 10;
|
||||
break;
|
||||
case SCLK_UART1:
|
||||
con_id = 13;
|
||||
break;
|
||||
case SCLK_UART2:
|
||||
con_id = 16;
|
||||
break;
|
||||
case SCLK_UART3:
|
||||
con_id = 19;
|
||||
break;
|
||||
case SCLK_UART4:
|
||||
con_id = 22;
|
||||
break;
|
||||
default:
|
||||
printf("do not support this uart interface\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
con = readl(&cru->clksel_con[con_id]);
|
||||
pll_sel = (con & CLK_UART_PLL_SEL_MASK) >> CLK_UART_PLL_SEL_SHIFT;
|
||||
div = (con & CLK_UART_DIV_CON_MASK) >> CLK_UART_DIV_CON_SHIFT;
|
||||
|
||||
switch (pll_sel) {
|
||||
case CLK_UART_PLL_SEL_DPLL:
|
||||
parent = priv->dpll_hz;
|
||||
break;
|
||||
case CLK_UART_PLL_SEL_VPLL0:
|
||||
parent = priv->vpll0_hz;
|
||||
break;
|
||||
case CLK_UART_PLL_SEL_VPLL1:
|
||||
parent = priv->vpll0_hz;
|
||||
break;
|
||||
case CLK_UART_PLL_SEL_24M:
|
||||
parent = OSC_HZ;
|
||||
break;
|
||||
default:
|
||||
printf("do not support this uart pll sel\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return DIV_TO_RATE(parent, div);
|
||||
}
|
||||
|
||||
static ulong rk3308_vop_get_clk(struct clk *clk)
|
||||
{
|
||||
struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
|
@ -813,6 +865,13 @@ static ulong rk3308_clk_get_rate(struct clk *clk)
|
|||
case SCLK_EMMC_SAMPLE:
|
||||
rate = rk3308_mmc_get_clk(clk);
|
||||
break;
|
||||
case SCLK_UART0:
|
||||
case SCLK_UART1:
|
||||
case SCLK_UART2:
|
||||
case SCLK_UART3:
|
||||
case SCLK_UART4:
|
||||
rate = rk3308_uart_get_clk(clk);
|
||||
break;
|
||||
case SCLK_I2C0:
|
||||
case SCLK_I2C1:
|
||||
case SCLK_I2C2:
|
||||
|
|
|
|||
|
|
@ -702,7 +702,10 @@ static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,
|
|||
}
|
||||
|
||||
div = DIV_ROUND_UP(priv->cpll_hz, rate);
|
||||
assert(div - 1 <= 31);
|
||||
if (clk_id == CPLL_25M)
|
||||
assert(div - 1 <= 63);
|
||||
else
|
||||
assert(div - 1 <= 31);
|
||||
rk_clrsetreg(&cru->clksel_con[con],
|
||||
mask, (div - 1) << shift);
|
||||
return rk3568_cpll_div_get_rate(priv, clk_id);
|
||||
|
|
@ -1142,7 +1145,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
|
|||
|
||||
switch (clk_id) {
|
||||
case CLK_PWM1:
|
||||
sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
|
||||
sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
|
||||
break;
|
||||
case CLK_PWM2:
|
||||
sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
|
||||
|
|
@ -2186,6 +2189,7 @@ static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv,
|
|||
|
||||
return rk3568_rkvdec_get_clk(priv, clk_id);
|
||||
}
|
||||
#endif
|
||||
|
||||
static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
|
||||
{
|
||||
|
|
@ -2321,7 +2325,6 @@ static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv,
|
|||
|
||||
return rk3568_uart_get_rate(priv, clk_id);
|
||||
}
|
||||
#endif
|
||||
|
||||
static ulong rk3568_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
|
|
@ -2460,6 +2463,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
|
|||
case TCLK_WDT_NS:
|
||||
rate = OSC_HZ;
|
||||
break;
|
||||
#endif
|
||||
case SCLK_UART1:
|
||||
case SCLK_UART2:
|
||||
case SCLK_UART3:
|
||||
|
|
@ -2471,7 +2475,6 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
|
|||
case SCLK_UART9:
|
||||
rate = rk3568_uart_get_rate(priv, clk->id);
|
||||
break;
|
||||
#endif
|
||||
case ACLK_SECURE_FLASH:
|
||||
case ACLK_CRYPTO_NS:
|
||||
case HCLK_SECURE_FLASH:
|
||||
|
|
@ -2645,6 +2648,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
|
|||
case TCLK_WDT_NS:
|
||||
ret = OSC_HZ;
|
||||
break;
|
||||
#endif
|
||||
case SCLK_UART1:
|
||||
case SCLK_UART2:
|
||||
case SCLK_UART3:
|
||||
|
|
@ -2656,7 +2660,6 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
|
|||
case SCLK_UART9:
|
||||
ret = rk3568_uart_set_rate(priv, clk->id, rate);
|
||||
break;
|
||||
#endif
|
||||
case ACLK_SECURE_FLASH:
|
||||
case ACLK_CRYPTO_NS:
|
||||
case HCLK_SECURE_FLASH:
|
||||
|
|
@ -2840,6 +2843,10 @@ static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
|
|||
case CLK_RKVDEC_CORE:
|
||||
return rk3568_rkvdec_set_parent(clk, parent);
|
||||
case I2S1_MCLKOUT_TX:
|
||||
case SCLK_GMAC0_RGMII_SPEED:
|
||||
case SCLK_GMAC0_RMII_SPEED:
|
||||
case SCLK_GMAC1_RGMII_SPEED:
|
||||
case SCLK_GMAC1_RMII_SPEED:
|
||||
break;
|
||||
default:
|
||||
return -ENOENT;
|
||||
|
|
|
|||
|
|
@ -12,23 +12,15 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <generic-phy.h>
|
||||
#include <pci.h>
|
||||
#include <power-domain.h>
|
||||
#include <power/regulator.h>
|
||||
#include <reset.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
|
||||
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
|
||||
|
||||
|
|
@ -383,41 +375,38 @@ static int rockchip_pcie_set_vpcie(struct udevice *dev)
|
|||
struct rockchip_pcie *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
if (priv->vpcie3v3) {
|
||||
ret = regulator_set_enable(priv->vpcie3v3, true);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
ret = regulator_set_enable_if_allowed(priv->vpcie12v, true);
|
||||
if (ret && ret != -ENOSYS) {
|
||||
dev_err(dev, "failed to enable vpcie12v (ret=%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (priv->vpcie1v8) {
|
||||
ret = regulator_set_enable(priv->vpcie1v8, true);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n",
|
||||
ret);
|
||||
goto err_disable_3v3;
|
||||
}
|
||||
ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
|
||||
if (ret && ret != -ENOSYS) {
|
||||
dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
|
||||
goto err_disable_12v;
|
||||
}
|
||||
|
||||
if (priv->vpcie0v9) {
|
||||
ret = regulator_set_enable(priv->vpcie0v9, true);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n",
|
||||
ret);
|
||||
goto err_disable_1v8;
|
||||
}
|
||||
ret = regulator_set_enable_if_allowed(priv->vpcie1v8, true);
|
||||
if (ret && ret != -ENOSYS) {
|
||||
dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);
|
||||
goto err_disable_3v3;
|
||||
}
|
||||
|
||||
ret = regulator_set_enable_if_allowed(priv->vpcie0v9, true);
|
||||
if (ret && ret != -ENOSYS) {
|
||||
dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);
|
||||
goto err_disable_1v8;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_1v8:
|
||||
if (priv->vpcie1v8)
|
||||
regulator_set_enable(priv->vpcie1v8, false);
|
||||
regulator_set_enable_if_allowed(priv->vpcie1v8, false);
|
||||
err_disable_3v3:
|
||||
if (priv->vpcie3v3)
|
||||
regulator_set_enable(priv->vpcie3v3, false);
|
||||
regulator_set_enable_if_allowed(priv->vpcie3v3, false);
|
||||
err_disable_12v:
|
||||
regulator_set_enable_if_allowed(priv->vpcie12v, false);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -427,19 +416,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
|
|||
int ret;
|
||||
|
||||
priv->axi_base = dev_read_addr_name(dev, "axi-base");
|
||||
if (!priv->axi_base)
|
||||
return -ENODEV;
|
||||
if (priv->axi_base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
priv->apb_base = dev_read_addr_name(dev, "apb-base");
|
||||
if (!priv->axi_base)
|
||||
return -ENODEV;
|
||||
|
||||
ret = gpio_request_by_name(dev, "ep-gpios", 0,
|
||||
&priv->ep_gpio, GPIOD_IS_OUT);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to find ep-gpios property\n");
|
||||
return ret;
|
||||
}
|
||||
if (priv->apb_base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
ret = reset_get_by_name(dev, "core", &priv->core_rst);
|
||||
if (ret) {
|
||||
|
|
@ -483,6 +465,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = device_get_supply_regulator(dev, "vpcie12v-supply",
|
||||
&priv->vpcie12v);
|
||||
if (ret && ret != -ENOENT) {
|
||||
dev_err(dev, "failed to get vpcie12v supply (ret=%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
|
||||
&priv->vpcie3v3);
|
||||
if (ret && ret != -ENOENT) {
|
||||
|
|
@ -510,6 +499,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = gpio_request_by_name(dev, "ep-gpios", 0,
|
||||
&priv->ep_gpio, GPIOD_IS_OUT);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to find ep-gpios property\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -529,16 +525,26 @@ static int rockchip_pcie_probe(struct udevice *dev)
|
|||
|
||||
ret = rockchip_pcie_set_vpcie(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto err_gpio_free;
|
||||
|
||||
ret = rockchip_pcie_init_port(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto err_disable_vpcie;
|
||||
|
||||
dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
|
||||
dev_seq(dev), hose->first_busno);
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_vpcie:
|
||||
regulator_set_enable_if_allowed(priv->vpcie0v9, false);
|
||||
regulator_set_enable_if_allowed(priv->vpcie1v8, false);
|
||||
regulator_set_enable_if_allowed(priv->vpcie3v3, false);
|
||||
regulator_set_enable_if_allowed(priv->vpcie12v, false);
|
||||
err_gpio_free:
|
||||
if (dm_gpio_is_valid(&priv->ep_gpio))
|
||||
dm_gpio_free(dev, &priv->ep_gpio);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops rockchip_pcie_ops = {
|
||||
|
|
@ -552,10 +558,10 @@ static const struct udevice_id rockchip_pcie_ids[] = {
|
|||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_pcie) = {
|
||||
.name = "rockchip_pcie",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = rockchip_pcie_ids,
|
||||
.ops = &rockchip_pcie_ops,
|
||||
.probe = rockchip_pcie_probe,
|
||||
.name = "rockchip_pcie",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = rockchip_pcie_ids,
|
||||
.ops = &rockchip_pcie_ops,
|
||||
.probe = rockchip_pcie_probe,
|
||||
.priv_auto = sizeof(struct rockchip_pcie),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -113,11 +113,9 @@ static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
|||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
int iomux_num = (pin / 8);
|
||||
struct regmap *regmap;
|
||||
int reg, ret, mask;
|
||||
int reg, mask;
|
||||
u8 bit;
|
||||
u32 data;
|
||||
|
||||
debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
|
||||
u32 data, rmask;
|
||||
|
||||
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
|
||||
regmap = priv->regmap_pmu;
|
||||
|
|
@ -131,10 +129,10 @@ static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
|||
mask = 0xf;
|
||||
|
||||
data = (mask << (bit + 16));
|
||||
rmask = data | (data >> 16);
|
||||
data |= (mux & mask) << bit;
|
||||
ret = regmap_write(regmap, reg, data);
|
||||
|
||||
return ret;
|
||||
return regmap_update_bits(regmap, reg, rmask, data);
|
||||
}
|
||||
|
||||
#define RK3568_PULL_PMU_OFFSET 0x20
|
||||
|
|
@ -225,7 +223,7 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank,
|
|||
struct regmap *regmap;
|
||||
int reg, ret;
|
||||
u8 bit, type;
|
||||
u32 data;
|
||||
u32 data, rmask;
|
||||
|
||||
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
|
||||
return -ENOTSUPP;
|
||||
|
|
@ -249,52 +247,59 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank,
|
|||
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
|
||||
rmask = data | (data >> 16);
|
||||
data |= (ret << bit);
|
||||
ret = regmap_write(regmap, reg, data);
|
||||
|
||||
return ret;
|
||||
return regmap_update_bits(regmap, reg, rmask, data);
|
||||
}
|
||||
|
||||
#define GRF_GPIO1C5_DS 0x0840
|
||||
#define GRF_GPIO2A2_DS 0x0844
|
||||
#define GRF_GPIO2B0_DS 0x0848
|
||||
#define GRF_GPIO3A0_DS 0x084c
|
||||
#define GRF_GPIO3A6_DS 0x0850
|
||||
#define GRF_GPIO4A0_DS 0x0854
|
||||
|
||||
static int rk3568_set_drive(struct rockchip_pin_bank *bank,
|
||||
int pin_num, int strength)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int reg;
|
||||
u32 data;
|
||||
int reg, ret;
|
||||
u32 data, rmask;
|
||||
u8 bit;
|
||||
int drv = (1 << (strength + 1)) - 1;
|
||||
int ret = 0;
|
||||
|
||||
rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
rmask = data | (data >> 16);
|
||||
data |= (drv << bit);
|
||||
|
||||
ret = regmap_write(regmap, reg, data);
|
||||
ret = regmap_update_bits(regmap, reg, rmask, data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (bank->bank_num == 1 && pin_num == 21)
|
||||
reg = 0x0840;
|
||||
reg = GRF_GPIO1C5_DS;
|
||||
else if (bank->bank_num == 2 && pin_num == 2)
|
||||
reg = 0x0844;
|
||||
reg = GRF_GPIO2A2_DS;
|
||||
else if (bank->bank_num == 2 && pin_num == 8)
|
||||
reg = 0x0848;
|
||||
reg = GRF_GPIO2B0_DS;
|
||||
else if (bank->bank_num == 3 && pin_num == 0)
|
||||
reg = 0x084c;
|
||||
reg = GRF_GPIO3A0_DS;
|
||||
else if (bank->bank_num == 3 && pin_num == 6)
|
||||
reg = 0x0850;
|
||||
reg = GRF_GPIO3A6_DS;
|
||||
else if (bank->bank_num == 4 && pin_num == 0)
|
||||
reg = 0x0854;
|
||||
reg = GRF_GPIO4A0_DS;
|
||||
else
|
||||
return 0;
|
||||
|
||||
data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
|
||||
data |= drv;
|
||||
rmask = data | (data >> 16);
|
||||
data |= drv >> 6;
|
||||
|
||||
return regmap_write(regmap, reg, data);
|
||||
return regmap_update_bits(regmap, reg, rmask, data);
|
||||
}
|
||||
|
||||
static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
|
||||
|
|
@ -302,16 +307,17 @@ static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
|
|||
{
|
||||
struct regmap *regmap;
|
||||
int reg;
|
||||
u32 data;
|
||||
u32 data, rmask;
|
||||
u8 bit;
|
||||
|
||||
rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
data |= (enable << bit);
|
||||
rmask = data | (data >> 16);
|
||||
data |= ((enable ? 0x2 : 0x1) << bit);
|
||||
|
||||
return regmap_write(regmap, reg, data);
|
||||
return regmap_update_bits(regmap, reg, rmask, data);
|
||||
}
|
||||
|
||||
static struct rockchip_pin_bank rk3568_pin_banks[] = {
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <pwm.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/math64.h>
|
||||
#include <power/regulator.h>
|
||||
|
||||
/**
|
||||
|
|
@ -59,12 +60,14 @@ struct pwm_backlight_priv {
|
|||
|
||||
static int set_pwm(struct pwm_backlight_priv *priv)
|
||||
{
|
||||
u64 width;
|
||||
uint duty_cycle;
|
||||
int ret;
|
||||
|
||||
if (priv->period_ns) {
|
||||
duty_cycle = (u64)priv->period_ns * (priv->cur_level - priv->min_level) /
|
||||
(priv->max_level - priv->min_level);
|
||||
width = priv->period_ns * (priv->cur_level - priv->min_level);
|
||||
duty_cycle = div_u64(width,
|
||||
(priv->max_level - priv->min_level));
|
||||
ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns,
|
||||
duty_cycle);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
"scriptaddr=0x00000000\0" \
|
||||
"pxefile_addr_r=0x00100000\0" \
|
||||
"fdt_addr_r=0x08300000\0" \
|
||||
"fdtoverlay_addr_r=0x02000000\0" \
|
||||
"kernel_addr_r=0x02008000\0" \
|
||||
"ramdisk_addr_r=0x0a200000\0"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue