mirror of
https://github.com/AsahiLinux/u-boot
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Support for the Philips ISP116x HCD (Host Controller Driver)
Signed-off-by: Rodolfo Giometti <giometti@enneenne.com>
This commit is contained in:
Rodolfo Giometti
Markus Klotzbuecher
parent
edf5851be6
commit
822af351ad
4 changed files with 1906 additions and 2 deletions
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@ -31,7 +31,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \
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bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
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cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
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e1000.o eepro100.o \
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i8042.o inca-ip_sw.o keyboard.o \
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i8042.o inca-ip_sw.o isp116x-hcd.o keyboard.o \
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lan91c96.o \
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natsemi.o ne2000.o netarm_eth.o netconsole.o \
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ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \
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1412
drivers/isp116x-hcd.c
Normal file
1412
drivers/isp116x-hcd.c
Normal file
File diff suppressed because it is too large
Load diff
489
drivers/isp116x.h
Normal file
489
drivers/isp116x.h
Normal file
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@ -0,0 +1,489 @@
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/*
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* ISP116x register declarations and HCD data structures
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*
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* Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
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* Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
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* Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
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* Portions:
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* Copyright (C) 2004 Lothar Wassmann
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* Copyright (C) 2004 Psion Teklogix
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* Copyright (C) 2004 David Brownell
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifdef DEBUG
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#define DBG(fmt, args...) \
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printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
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#else
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#define DBG(fmt, args...) do {} while (0)
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#endif
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#ifdef VERBOSE
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# define VDBG DBG
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#else
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# define VDBG(fmt, args...) do {} while (0)
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#endif
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#define ERR(fmt, args...) \
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printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
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#define WARN(fmt, args...) \
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printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
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#define INFO(fmt, args...) \
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printf("isp116x: " fmt "\n" , ## args)
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/* ------------------------------------------------------------------------- */
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/* us of 1ms frame */
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#define MAX_LOAD_LIMIT 850
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/* Full speed: max # of bytes to transfer for a single urb
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at a time must be < 1024 && must be multiple of 64.
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832 allows transfering 4kiB within 5 frames. */
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#define MAX_TRANSFER_SIZE_FULLSPEED 832
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/* Low speed: there is no reason to schedule in very big
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chunks; often the requested long transfers are for
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string descriptors containing short strings. */
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#define MAX_TRANSFER_SIZE_LOWSPEED 64
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/* Bytetime (us), a rough indication of how much time it
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would take to transfer a byte of useful data over USB */
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#define BYTE_TIME_FULLSPEED 1
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#define BYTE_TIME_LOWSPEED 20
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/* Buffer sizes */
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#define ISP116x_BUF_SIZE 4096
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#define ISP116x_ITL_BUFSIZE 0
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#define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
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#define ISP116x_WRITE_OFFSET 0x80
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/* --- ISP116x registers/bits ---------------------------------------------- */
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#define HCREVISION 0x00
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#define HCCONTROL 0x01
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#define HCCONTROL_HCFS (3 << 6) /* host controller
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functional state */
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#define HCCONTROL_USB_RESET (0 << 6)
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#define HCCONTROL_USB_RESUME (1 << 6)
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#define HCCONTROL_USB_OPER (2 << 6)
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#define HCCONTROL_USB_SUSPEND (3 << 6)
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#define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */
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#define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */
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#define HCCMDSTAT 0x02
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#define HCCMDSTAT_HCR (1 << 0) /* host controller reset */
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#define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */
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#define HCINTSTAT 0x03
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#define HCINT_SO (1 << 0) /* scheduling overrun */
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#define HCINT_WDH (1 << 1) /* writeback of done_head */
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#define HCINT_SF (1 << 2) /* start frame */
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#define HCINT_RD (1 << 3) /* resume detect */
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#define HCINT_UE (1 << 4) /* unrecoverable error */
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#define HCINT_FNO (1 << 5) /* frame number overflow */
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#define HCINT_RHSC (1 << 6) /* root hub status change */
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#define HCINT_OC (1 << 30) /* ownership change */
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#define HCINT_MIE (1 << 31) /* master interrupt enable */
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#define HCINTENB 0x04
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#define HCINTDIS 0x05
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#define HCFMINTVL 0x0d
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#define HCFMREM 0x0e
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#define HCFMNUM 0x0f
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#define HCLSTHRESH 0x11
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#define HCRHDESCA 0x12
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#define RH_A_NDP (0x3 << 0) /* # downstream ports */
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#define RH_A_PSM (1 << 8) /* power switching mode */
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#define RH_A_NPS (1 << 9) /* no power switching */
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#define RH_A_DT (1 << 10) /* device type (mbz) */
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#define RH_A_OCPM (1 << 11) /* overcurrent protection
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mode */
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#define RH_A_NOCP (1 << 12) /* no overcurrent protection */
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#define RH_A_POTPGT (0xff << 24) /* power on -> power good
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time */
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#define HCRHDESCB 0x13
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#define RH_B_DR (0xffff << 0) /* device removable flags */
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#define RH_B_PPCM (0xffff << 16) /* port power control mask */
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#define HCRHSTATUS 0x14
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#define RH_HS_LPS (1 << 0) /* local power status */
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#define RH_HS_OCI (1 << 1) /* over current indicator */
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#define RH_HS_DRWE (1 << 15) /* device remote wakeup
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enable */
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#define RH_HS_LPSC (1 << 16) /* local power status change */
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#define RH_HS_OCIC (1 << 17) /* over current indicator
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change */
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#define RH_HS_CRWE (1 << 31) /* clear remote wakeup
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enable */
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#define HCRHPORT1 0x15
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#define RH_PS_CCS (1 << 0) /* current connect status */
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#define RH_PS_PES (1 << 1) /* port enable status */
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#define RH_PS_PSS (1 << 2) /* port suspend status */
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#define RH_PS_POCI (1 << 3) /* port over current
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indicator */
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#define RH_PS_PRS (1 << 4) /* port reset status */
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#define RH_PS_PPS (1 << 8) /* port power status */
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#define RH_PS_LSDA (1 << 9) /* low speed device attached */
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#define RH_PS_CSC (1 << 16) /* connect status change */
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#define RH_PS_PESC (1 << 17) /* port enable status change */
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#define RH_PS_PSSC (1 << 18) /* port suspend status
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change */
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#define RH_PS_OCIC (1 << 19) /* over current indicator
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change */
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#define RH_PS_PRSC (1 << 20) /* port reset status change */
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#define HCRHPORT_CLRMASK (0x1f << 16)
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#define HCRHPORT2 0x16
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#define HCHWCFG 0x20
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#define HCHWCFG_15KRSEL (1 << 12)
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#define HCHWCFG_CLKNOTSTOP (1 << 11)
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#define HCHWCFG_ANALOG_OC (1 << 10)
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#define HCHWCFG_DACK_MODE (1 << 8)
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#define HCHWCFG_EOT_POL (1 << 7)
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#define HCHWCFG_DACK_POL (1 << 6)
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#define HCHWCFG_DREQ_POL (1 << 5)
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#define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
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#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
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#define HCHWCFG_INT_POL (1 << 2)
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#define HCHWCFG_INT_TRIGGER (1 << 1)
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#define HCHWCFG_INT_ENABLE (1 << 0)
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#define HCDMACFG 0x21
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#define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
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#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
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#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
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#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
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#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
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#define HCDMACFG_DMA_ENABLE (1 << 4)
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#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
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#define HCDMACFG_CTR_SEL (1 << 2)
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#define HCDMACFG_ITLATL_SEL (1 << 1)
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#define HCDMACFG_DMA_RW_SELECT (1 << 0)
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#define HCXFERCTR 0x22
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#define HCuPINT 0x24
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#define HCuPINT_SOF (1 << 0)
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#define HCuPINT_ATL (1 << 1)
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#define HCuPINT_AIIEOT (1 << 2)
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#define HCuPINT_OPR (1 << 4)
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#define HCuPINT_SUSP (1 << 5)
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#define HCuPINT_CLKRDY (1 << 6)
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#define HCuPINTENB 0x25
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#define HCCHIPID 0x27
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#define HCCHIPID_MASK 0xff00
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#define HCCHIPID_MAGIC 0x6100
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#define HCSCRATCH 0x28
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#define HCSWRES 0x29
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#define HCSWRES_MAGIC 0x00f6
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#define HCITLBUFLEN 0x2a
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#define HCATLBUFLEN 0x2b
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#define HCBUFSTAT 0x2c
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#define HCBUFSTAT_ITL0_FULL (1 << 0)
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#define HCBUFSTAT_ITL1_FULL (1 << 1)
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#define HCBUFSTAT_ATL_FULL (1 << 2)
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#define HCBUFSTAT_ITL0_DONE (1 << 3)
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#define HCBUFSTAT_ITL1_DONE (1 << 4)
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#define HCBUFSTAT_ATL_DONE (1 << 5)
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#define HCRDITL0LEN 0x2d
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#define HCRDITL1LEN 0x2e
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#define HCITLPORT 0x40
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#define HCATLPORT 0x41
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/* PTD accessor macros. */
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#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
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#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
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#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
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#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
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#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
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#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
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#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
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#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
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#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
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#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
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#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
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#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
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#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
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#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
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#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
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#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
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#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
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#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
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#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
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#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
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#define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13)
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#define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK)
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#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
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#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
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#define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7)
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#define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK)
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/* Hardware transfer status codes -- CC from ptd->count */
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#define TD_CC_NOERROR 0x00
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#define TD_CC_CRC 0x01
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#define TD_CC_BITSTUFFING 0x02
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#define TD_CC_DATATOGGLEM 0x03
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#define TD_CC_STALL 0x04
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#define TD_DEVNOTRESP 0x05
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#define TD_PIDCHECKFAIL 0x06
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#define TD_UNEXPECTEDPID 0x07
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#define TD_DATAOVERRUN 0x08
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#define TD_DATAUNDERRUN 0x09
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/* 0x0A, 0x0B reserved for hardware */
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#define TD_BUFFEROVERRUN 0x0C
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#define TD_BUFFERUNDERRUN 0x0D
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/* 0x0E, 0x0F reserved for HCD */
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#define TD_NOTACCESSED 0x0F
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/* ------------------------------------------------------------------------- */
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#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
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#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
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/* Philips transfer descriptor */
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struct ptd {
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u16 count;
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#define PTD_COUNT_MSK (0x3ff << 0)
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#define PTD_TOGGLE_MSK (1 << 10)
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#define PTD_ACTIVE_MSK (1 << 11)
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#define PTD_CC_MSK (0xf << 12)
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u16 mps;
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#define PTD_MPS_MSK (0x3ff << 0)
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#define PTD_SPD_MSK (1 << 10)
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#define PTD_LAST_MSK (1 << 11)
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#define PTD_EP_MSK (0xf << 12)
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u16 len;
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#define PTD_LEN_MSK (0x3ff << 0)
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#define PTD_DIR_MSK (3 << 10)
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#define PTD_DIR_SETUP (0)
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#define PTD_DIR_OUT (1)
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#define PTD_DIR_IN (2)
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#define PTD_B5_5_MSK (1 << 13)
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u16 faddr;
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#define PTD_FA_MSK (0x7f << 0)
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#define PTD_FMT_MSK (1 << 7)
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} __attribute__ ((packed, aligned(2)));
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struct isp116x_ep {
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struct usb_device *udev;
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struct ptd ptd;
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u8 maxpacket;
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u8 epnum;
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u8 nextpid;
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u16 length; /* of current packet */
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unsigned char *data; /* to databuf */
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u16 error_count;
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};
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/* URB struct */
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#define N_URB_TD 48
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#define URB_DEL 1
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typedef struct {
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struct isp116x_ep *ed;
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void *transfer_buffer; /* (in) associated data buffer */
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int actual_length; /* (return) actual transfer length */
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unsigned long pipe; /* (in) pipe information */
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#if 0
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int state;
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#endif
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} urb_priv_t;
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struct isp116x_platform_data {
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/* Enable internal resistors on downstream ports */
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unsigned sel15Kres:1;
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/* On-chip overcurrent detection */
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unsigned oc_enable:1;
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/* Enable wakeup by devices on usb bus (e.g. wakeup
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by attachment/detachment or by device activity
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such as moving a mouse). When chosen, this option
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prevents stopping internal clock, increasing
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thereby power consumption in suspended state. */
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unsigned remote_wakeup_enable:1;
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};
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struct isp116x {
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u16 *addr_reg;
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u16 *data_reg;
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struct isp116x_platform_data *board;
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struct dentry *dentry;
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unsigned long stat1, stat2, stat4, stat8, stat16;
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/* Status flags */
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unsigned disabled:1;
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unsigned sleeping:1;
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/* Root hub registers */
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u32 rhdesca;
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u32 rhdescb;
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u32 rhstatus;
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u32 rhport[2];
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/* Schedule for the current frame */
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struct isp116x_ep *atl_active;
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int atl_buflen;
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int atl_bufshrt;
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int atl_last_dir;
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int atl_finishing;
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};
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/* ------------------------------------------------- */
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/* Inter-io delay (ns). The chip is picky about access timings; it
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* expects at least:
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* 150ns delay between consecutive accesses to DATA_REG,
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* 300ns delay between access to ADDR_REG and DATA_REG
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* OE, WE MUST NOT be changed during these intervals
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*/
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#if defined(UDELAY)
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#define isp116x_delay(h,d) udelay(d)
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#else
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#define isp116x_delay(h,d) do {} while (0)
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#endif
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static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
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{
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writew(reg & 0xff, isp116x->addr_reg);
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isp116x_delay(isp116x, UDELAY);
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}
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static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
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{
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writew(val, isp116x->data_reg);
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isp116x_delay(isp116x, UDELAY);
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}
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static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
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{
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||||
__raw_writew(val, isp116x->data_reg);
|
||||
isp116x_delay(isp116x, UDELAY);
|
||||
}
|
||||
|
||||
static inline u16 isp116x_read_data16(struct isp116x *isp116x)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
val = readw(isp116x->data_reg);
|
||||
isp116x_delay(isp116x, UDELAY);
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
val = __raw_readw(isp116x->data_reg);
|
||||
isp116x_delay(isp116x, UDELAY);
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
|
||||
{
|
||||
writew(val & 0xffff, isp116x->data_reg);
|
||||
isp116x_delay(isp116x, UDELAY);
|
||||
writew(val >> 16, isp116x->data_reg);
|
||||
isp116x_delay(isp116x, UDELAY);
|
||||
}
|
||||
|
||||
static inline u32 isp116x_read_data32(struct isp116x *isp116x)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = (u32) readw(isp116x->data_reg);
|
||||
isp116x_delay(isp116x, UDELAY);
|
||||
val |= ((u32) readw(isp116x->data_reg)) << 16;
|
||||
isp116x_delay(isp116x, UDELAY);
|
||||
return val;
|
||||
}
|
||||
|
||||
/* Let's keep register access functions out of line. Hint:
|
||||
we wait at least 150 ns at every access.
|
||||
*/
|
||||
static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
|
||||
{
|
||||
isp116x_write_addr(isp116x, reg);
|
||||
return isp116x_read_data16(isp116x);
|
||||
}
|
||||
|
||||
static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
|
||||
{
|
||||
isp116x_write_addr(isp116x, reg);
|
||||
return isp116x_read_data32(isp116x);
|
||||
}
|
||||
|
||||
static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
|
||||
unsigned val)
|
||||
{
|
||||
isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
|
||||
isp116x_write_data16(isp116x, (u16) (val & 0xffff));
|
||||
}
|
||||
|
||||
static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
|
||||
unsigned val)
|
||||
{
|
||||
isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
|
||||
isp116x_write_data32(isp116x, (u32) val);
|
||||
}
|
||||
|
||||
/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
|
||||
|
||||
/* destination of request */
|
||||
#define RH_INTERFACE 0x01
|
||||
#define RH_ENDPOINT 0x02
|
||||
#define RH_OTHER 0x03
|
||||
|
||||
#define RH_CLASS 0x20
|
||||
#define RH_VENDOR 0x40
|
||||
|
||||
/* Requests: bRequest << 8 | bmRequestType */
|
||||
#define RH_GET_STATUS 0x0080
|
||||
#define RH_CLEAR_FEATURE 0x0100
|
||||
#define RH_SET_FEATURE 0x0300
|
||||
#define RH_SET_ADDRESS 0x0500
|
||||
#define RH_GET_DESCRIPTOR 0x0680
|
||||
#define RH_SET_DESCRIPTOR 0x0700
|
||||
#define RH_GET_CONFIGURATION 0x0880
|
||||
#define RH_SET_CONFIGURATION 0x0900
|
||||
#define RH_GET_STATE 0x0280
|
||||
#define RH_GET_INTERFACE 0x0A80
|
||||
#define RH_SET_INTERFACE 0x0B00
|
||||
#define RH_SYNC_FRAME 0x0C80
|
||||
/* Our Vendor Specific Request */
|
||||
#define RH_SET_EP 0x2000
|
||||
|
||||
/* Hub port features */
|
||||
#define RH_PORT_CONNECTION 0x00
|
||||
#define RH_PORT_ENABLE 0x01
|
||||
#define RH_PORT_SUSPEND 0x02
|
||||
#define RH_PORT_OVER_CURRENT 0x03
|
||||
#define RH_PORT_RESET 0x04
|
||||
#define RH_PORT_POWER 0x08
|
||||
#define RH_PORT_LOW_SPEED 0x09
|
||||
|
||||
#define RH_C_PORT_CONNECTION 0x10
|
||||
#define RH_C_PORT_ENABLE 0x11
|
||||
#define RH_C_PORT_SUSPEND 0x12
|
||||
#define RH_C_PORT_OVER_CURRENT 0x13
|
||||
#define RH_C_PORT_RESET 0x14
|
||||
|
||||
/* Hub features */
|
||||
#define RH_C_HUB_LOCAL_POWER 0x00
|
||||
#define RH_C_HUB_OVER_CURRENT 0x01
|
||||
|
||||
#define RH_DEVICE_REMOTE_WAKEUP 0x00
|
||||
#define RH_ENDPOINT_STALL 0x01
|
||||
|
||||
#define RH_ACK 0x01
|
||||
#define RH_REQ_ERR -1
|
||||
#define RH_NACK 0x00
|
||||
|
|
@ -169,7 +169,10 @@ struct usb_device {
|
|||
* this is how the lowlevel part communicate with the outer world
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined (CONFIG_USB_SL811HS) || defined(CONFIG_USB_OHCI_NEW)
|
||||
#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
|
||||
defined(CONFIG_USB_OHCI_NEW) || defined (CONFIG_USB_SL811HS) || \
|
||||
defined(CONFIG_USB_ISP116X_HCD)
|
||||
|
||||
int usb_lowlevel_init(void);
|
||||
int usb_lowlevel_stop(void);
|
||||
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len);
|
||||
|
|
|
|||
Loading…
Reference in a new issue