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arm64: zynqmp: Disable Tri-state for MIO38 Pin

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gpio38 is used in SOM's kv260 to reset the Ethernet PHY.
At present, HW reset is not working properly as Tri-state 
is enabled for MIO38, causing inappropriate PHY register reads.

Disabled Tri-state for MIO38 to make HW reset work.

Tri-state disable :
ZynqMP> md 0xFF180208 2
ff180208: 00bfe7a3 00000540

Tri-state enable :
ZynqMP> md 0xFF180208 2
ff180208: 00bfe7e3 00000540

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Link: https://lore.kernel.org/r/20231020050622.972750-1-tejas.arvind.bhumkar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Tejas Bhumkar 2023-10-20 10:36:22 +05:30 • committed by Michal Simek
parent 3e89144892
commit 820bad0271
2 changed files with 50 additions and 0 deletions
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25
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
View file

@ -190,6 +190,25 @@
&pinctrl0 {
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@ -345,6 +364,12 @@
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";

25
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
View file

@ -178,6 +178,25 @@
&pinctrl0 {
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@ -333,6 +352,12 @@
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";