arm: mvebu: Move SoC selection (A38X vs AXP) into Kconfig

Until now, the SoC selection for the ARCH_MVEBU platforms has been done
in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As
it needed to get selected for AXP and A38x based boards. This patch
now changes this to move the SoC selection to Kconfig. And also
uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x.
This makes things a bit clearer - especially for new board additions.

Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and
CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available
CONFIG_ARMADA_38X and CONFIG_ARMADA_XP.

And CONFIG_DDR3 is removed, as its not referenced anywhere.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Stefan Roese 2015-12-21 13:56:33 +01:00
parent b322c83aa4
commit 81e33f4b65
15 changed files with 33 additions and 38 deletions

View file

@ -49,7 +49,7 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARMADA_XP) += mvebu
machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x

View file

@ -1,20 +1,30 @@
if ARCH_MVEBU
config ARMADA_38X
bool
config ARMADA_XP
bool
choice
prompt "Marvell MVEBU (Armada XP/38x) board select"
optional
config TARGET_CLEARFOG
bool "Support ClearFog"
select ARMADA_38X
config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
select ARMADA_38X
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
select ARMADA_XP
config TARGET_MAXBCM
bool "Support maxbcm"
select ARMADA_XP
endchoice

View file

@ -15,8 +15,8 @@ else
obj-y = cpu.o
obj-y += dram.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
endif
obj-y += gpio.o
obj-y += mbus.o
@ -24,7 +24,7 @@ obj-y += timer.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += serdes/a38x/
obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += serdes/axp/
obj-$(CONFIG_ARMADA_38X) += serdes/a38x/
obj-$(CONFIG_ARMADA_XP) += serdes/axp/
endif

View file

@ -12,11 +12,8 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_SYS_MVEBU_DDR_A38X
#include "../../../drivers/ddr/marvell/axp/xor.h"
#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
#endif
#ifdef CONFIG_SYS_MVEBU_DDR_AXP
#if defined(CONFIG_ARCH_MVEBU)
/* Use common XOR definitions for A3x and AXP */
#include "../../../drivers/ddr/marvell/axp/xor.h"
#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
#endif
@ -112,7 +109,7 @@ void mvebu_sdram_size_adjust(enum memory_bank bank)
mvebu_sdram_bs_set(bank, size);
}
#if defined(CONFIG_SYS_MVEBU_DDR_A38X) || defined(CONFIG_SYS_MVEBU_DDR_AXP)
#if defined(CONFIG_ARCH_MVEBU)
static u32 xor_ctrl_save;
static u32 xor_base_save;
static u32 xor_mask_save;
@ -292,7 +289,7 @@ void dram_init_banksize(void)
}
}
#if defined(CONFIG_ARMADA_XP)
#if defined(CONFIG_ARCH_MVEBU)
void board_add_ram_info(int use_default)
{
struct sar_freq_modes sar_freq;

View file

@ -17,7 +17,11 @@
#include <asm/arch/soc.h>
#if defined(CONFIG_ARMADA_XP)
#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X)
/*
* Set this for the common xor register definitions needed in dram.c
* for A38x as well here.
*/
#define MV88F78X60 /* for the DDR training bin_hdr code */
#endif

View file

@ -491,7 +491,7 @@ int mvebu_mbus_probe(struct mbus_win windows[], int count)
#if defined(CONFIG_KIRKWOOD)
mbus_state.soc = &kirkwood_mbus_data;
#endif
#if defined(CONFIG_ARMADA_XP)
#if defined(CONFIG_ARCH_MVEBU)
mbus_state.soc = &armada_370_xp_mbus_data;
#endif

View file

@ -31,7 +31,7 @@ int timer_init(void)
writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10);
writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14);
#if defined(CONFIG_ARMADA_XP)
#if defined(CONFIG_ARCH_MVEBU)
/* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */
setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11));
#endif

View file

@ -14,8 +14,8 @@ obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ddr/marvell/a38x/
obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ddr/marvell/axp/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/

View file

@ -13,7 +13,7 @@
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_KIRKWOOD)
#include <asm/arch/soc.h>
#elif defined(CONFIG_ARMADA_XP)
#elif defined(CONFIG_ARCH_MVEBU)
#include <linux/mbus.h>
#endif
@ -102,7 +102,7 @@ struct mvsata_port_registers {
* Initialize SATA memory windows for Armada XP
*/
#ifdef CONFIG_ARMADA_XP
#ifdef CONFIG_ARCH_MVEBU
static void mvsata_ide_conf_mbus_windows(void)
{
const struct mbus_dram_target_info *dram;
@ -174,7 +174,7 @@ int ide_preinit(void)
int ret = MVSATA_STATUS_TIMEOUT;
int status;
#ifdef CONFIG_ARMADA_XP
#ifdef CONFIG_ARCH_MVEBU
mvsata_ide_conf_mbus_windows();
#endif

View file

@ -20,7 +20,7 @@
#if defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP))
#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
#include <asm/arch/soc.h>
#elif defined(CONFIG_SUNXI)
#include <asm/arch/i2c.h>

View file

@ -10,8 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_ARMADA_XP /* SOC Family Name */
#define CONFIG_ARMADA_38X
#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
#define CONFIG_DISPLAY_BOARDINFO_LATE
@ -170,10 +168,6 @@
#endif
#endif
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_A38X
#define CONFIG_DDR3
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros

View file

@ -10,8 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_ARMADA_XP /* SOC Family Name */
#define CONFIG_ARMADA_38X
#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
#define CONFIG_DISPLAY_BOARDINFO_LATE
@ -170,10 +168,6 @@
#endif
#endif
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_A38X
#define CONFIG_DDR3
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros

View file

@ -10,7 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_ARMADA_XP /* SOC Family Name */
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
#define CONFIG_DISPLAY_BOARDINFO_LATE
@ -144,7 +143,6 @@
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM 0x4e
#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */

View file

@ -10,7 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_ARMADA_XP /* SOC Family Name */
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
@ -106,7 +105,6 @@
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */

View file

@ -156,7 +156,7 @@ ubsha1-objs := os_support.o ubsha1.o lib/sha1.o
HOSTCFLAGS_ubsha1.o := -pedantic
hostprogs-$(CONFIG_KIRKWOOD) += kwboot
hostprogs-$(CONFIG_ARMADA_XP) += kwboot
hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot
hostprogs-y += proftool
hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela