Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2025-03-16 23:07:00 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'master' of ssh://mercury/home/wd/git/u-boot/master

Browse source
This commit is contained in:
Wolfgang Denk 2008-06-05 01:12:30 +02:00
commit 8155efbd7a
207 changed files with 8591 additions and 1280 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
CHANGELOG
View file

@ -7221,7 +7221,7 @@ Date: Mon Mar 3 11:57:23 2008 +0000
Originally pointed out by Laurent Pinchart <laurent.pinchart@tbox.biz>,
see http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/22846
Signed-off-by: Bernhard Nemec <bnemec <at> ganssloser.com>
Signed-off-by: Bernhard Nemec <bnemec@ganssloser.com>
commit 84d0c2f1e39caff58bf765a7ab7c72da23c25ec8
Author: Kim B. Heino <Kim.Heino@bluegiga.com>
@ -8451,7 +8451,7 @@ Date: Mon Feb 18 14:01:56 2008 -0600
86xx: Convert sbc8641d to use libfdt.
This is the proper fix for a missing closing brace in the function
ft_cpu_setup() noticed by joe.hamman <at> embeddedspecialties.com.
ft_cpu_setup() noticed by joe.hamman@embeddedspecialties.com.
The ft_cpu_setup() function in mpc8641hpcn.c should have been
removed earlier as it was under the obsolete CONFIG_OF_FLAT_TREE,
but was missed. Only, the sbc8641d was nominally still using it.
@ -8846,7 +8846,7 @@ Date: Fri Feb 22 11:40:50 2008 +0000
We already have a vendor subdir for Atmel, so we should use it.
Signed-off-by: Haavard Skinnemoen <hskinnemoen <at> atmel.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
commit 6d0943a6be99977d6d853d51749e9963d68eb192
Author: Andreas Engel <andreas.engel@ericsson.com>
@ -8896,8 +8896,8 @@ Date: Thu Jan 3 21:15:56 2008 +0000
AT91CAP9 support : MACB changes
Signed-off-by: Stelian Pop <stelian <at> popies.net>
Acked-by: Haavard Skinnemoen <hskinnemoen <at> atmel.com>
Signed-off-by: Stelian Pop <stelian@popies.net>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
commit 6afcabf11d7321850f4feaadfee841488ace54c5
Author: Stelian Pop <stelian@popies.net>
@ -8913,7 +8913,7 @@ Date: Wed Jan 30 21:15:54 2008 +0000
AT91CAP9 support : cpu/ files
Signed-off-by: Stelian Pop <stelian <at> popies.net>
Signed-off-by: Stelian Pop <stelian@popies.net>
commit fa506a926cec348805143576c941f8e61b333cc0
Author: Stelian Pop <stelian@popies.net>

8
MAINTAINERS
View file

@ -204,6 +204,10 @@ Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
KUP4X MPC859
Gary Jennejohn <garyj@denx.de>
quad100hd PPC405EP
Murray Jensen <Murray.Jensen@csiro.au>
cogent_mpc8xx MPC8xx
@ -538,6 +542,9 @@ Stelian Pop <stelian.pop@leadtechdesign.com>
at91cap9adk ARM926EJS (AT91CAP9 SoC)
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
Stefan Roese <sr@denx.de>
@ -695,6 +702,7 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
ATSTK1002 AT32AP7000
ATSTK1003 AT32AP7001
ATSTK1004 AT32AP7002
ATSTK1006 AT32AP7000
ATNGW100 AT32AP7000
#########################################################################

25
MAKEALL
View file

@ -219,6 +219,7 @@ LIST_4xx=" \
PMC405 \
PMC440 \
PPChameleonEVB \
quad100hd \
rainier \
sbc405 \
sc3 \
@ -461,6 +462,9 @@ LIST_ARM9=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9rlek \
cmc_pu2 \
ap920t \
ap922_XA10 \
@ -520,6 +524,24 @@ LIST_ARM11=" \
mx31ads \
"
#########################################################################
## AT91 Systems
#########################################################################
LIST_at91=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9rlek \
cmc_pu2 \
csb637 \
kb9202 \
mp2usb \
m501sk \
"
#########################################################################
## Xscale Systems
#########################################################################
@ -697,6 +719,7 @@ LIST_avr32=" \
atstk1002 \
atstk1003 \
atstk1004 \
atstk1006 \
atngw100 \
"
@ -765,7 +788,7 @@ build_target() {
for arg in $@
do
case "$arg" in
arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa \
arm|SA|ARM7|ARM9|ARM10|ARM11|at91|ixp|pxa \
|avr32 \
|blackfin \
|coldfire \

17
Makefile
View file

@ -224,6 +224,7 @@ LIBS += drivers/mtd/libmtd.a
LIBS += drivers/mtd/nand/libnand.a
LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
LIBS += drivers/mtd/onenand/libonenand.a
LIBS += drivers/mtd/spi/libspi_flash.a
LIBS += drivers/net/libnet.a
LIBS += drivers/net/sk98lin/libsk98lin.a
LIBS += drivers/pci/libpci.a
@ -390,6 +391,7 @@ TAG_SUBDIRS += drivers/mtd
TAG_SUBDIRS += drivers/mtd/nand
TAG_SUBDIRS += drivers/mtd/nand_legacy
TAG_SUBDIRS += drivers/mtd/onenand
TAG_SUBDIRS += drivers/mtd/spi
TAG_SUBDIRS += drivers/net
TAG_SUBDIRS += drivers/net/sk98lin
TAG_SUBDIRS += drivers/pci
@ -1391,6 +1393,9 @@ PPChameleonEVB_HI_33_config: unconfig
}
@$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
quad100hd_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd
sbc405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
@ -2335,6 +2340,15 @@ shannon_config : unconfig
at91rm9200dk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
at91sam9261ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9
at91sam9263ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
at91sam9rlek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
@ -2879,6 +2893,9 @@ atstk1003_config : unconfig
atstk1004_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
atstk1006_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
atngw100_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x

4
README
View file

@ -961,6 +961,10 @@ The following options need to be configured:
display); also select one of the supported displays
by defining one of these:
CONFIG_ATMEL_LCD:
HITACHI TX09D70VM1CCA, 3.5", 240x320.
CONFIG_NEC_NL6448AC33:
NEC NL6448AC33-18. Active, color, single scan.

16
board/amcc/taihu/taihu.c
View file

@ -165,16 +165,20 @@ unsigned char spi_read(void)
return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
}
void taihu_spi_chipsel(int cs)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
gpio_write_bit(SPI_CS_GPIO0, cs);
return bus == 0 && cs == 0;
}
spi_chipsel_type spi_chipsel[]= {
taihu_spi_chipsel
};
void spi_cs_activate(struct spi_slave *slave)
{
gpio_write_bit(SPI_CS_GPIO0, 1);
}
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
void spi_cs_deactivate(struct spi_slave *slave)
{
gpio_write_bit(SPI_CS_GPIO0, 0);
}
#ifdef CONFIG_PCI
static unsigned char int_lines[32] = {

4
board/atmel/at91cap9adk/Makefile
View file

@ -2,6 +2,10 @@
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#

100
board/atmel/at91cap9adk/at91cap9adk.c
View file

@ -30,6 +30,8 @@
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
@ -70,6 +72,33 @@ static void at91cap9_serial_hw_init(void)
#endif
}
static void at91cap9_slowclock_hw_init(void)
{
/*
* On AT91CAP9 revC CPUs, the slow clock can be based on an
* internal impreciseRC oscillator or an external 32kHz oscillator.
* Switch to the latter.
*/
#define ARCH_ID_AT91CAP9_REVB 0x399
#define ARCH_ID_AT91CAP9_REVC 0x601
if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
unsigned i, tmp = at91_sys_read(AT91_SCKCR);
if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
extern void timer_init(void);
timer_init();
tmp |= AT91CAP9_SCKCR_OSC32EN;
at91_sys_write(AT91_SCKCR, tmp);
for (i = 0; i < 1200; i++)
udelay(1000);
tmp |= AT91CAP9_SCKCR_OSCSEL_32;
at91_sys_write(AT91_SCKCR, tmp);
udelay(200);
tmp &= ~AT91CAP9_SCKCR_RCEN;
at91_sys_write(AT91_SCKCR, tmp);
}
}
}
static void at91cap9_nor_hw_init(void)
{
unsigned long csa;
@ -116,7 +145,12 @@ static void at91cap9_nand_hw_init(void)
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
@ -228,6 +262,65 @@ static void at91cap9_uhp_hw_init(void)
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91CAP9_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
}
static void at91cap9_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
gd->fb_base = 0;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
@ -239,6 +332,7 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91cap9_serial_hw_init();
at91cap9_slowclock_hw_init();
at91cap9_nor_hw_init();
#ifdef CONFIG_CMD_NAND
at91cap9_nand_hw_init();
@ -252,7 +346,9 @@ int board_init(void)
#ifdef CONFIG_USB_OHCI_NEW
at91cap9_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
at91cap9_lcd_hw_init();
#endif
return 0;
}

3
board/atmel/at91cap9adk/nand.c
View file

@ -63,6 +63,9 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91cap9adk_nand_hwcontrol;
nand->chip_delay = 20;

4
board/atmel/at91sam9260ek/Makefile
View file

@ -2,6 +2,10 @@
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#

7
board/atmel/at91sam9260ek/at91sam9260ek.c
View file

@ -90,7 +90,12 @@ static void at91sam9260ek_nand_hw_init(void)
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);

3
board/atmel/at91sam9260ek/nand.c
View file

@ -68,6 +68,9 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
nand->dev_ready = at91sam9260ek_nand_ready;
nand->chip_delay = 20;

57
board/atmel/at91sam9260ek/u-boot.lds
View file

@ -1,57 +0,0 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm926ejs/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

57
board/atmel/at91sam9261ek/Makefile Normal file
View file

@ -0,0 +1,57 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9261ek.o
COBJS-y += led.o
COBJS-y += partition.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

258
board/atmel/at91sam9261ek/at91sam9261ek.c Normal file
View file

@ -0,0 +1,258 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9261ek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9261ek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PC15, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PC14, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9261ek_spi_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
}
#endif
#ifdef CONFIG_DRIVER_DM9000
static void at91sam9261ek_dm9000_hw_init(void)
{
/* Configure SMC CS2 for DM9000 */
at91_sys_write(AT91_SMC_SETUP(2),
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(2),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
at91_sys_write(AT91_SMC_CYCLE(2),
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
at91_sys_write(AT91_SMC_MODE(2),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
AT91_SMC_TDF_(1));
/* Configure Reset signal as output */
at91_set_gpio_output(AT91_PIN_PC10, 0);
/* Configure Interrupt pin as input, no pull-up */
at91_set_gpio_input(AT91_PIN_PC11, 0);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9261_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
}
static void at91sam9261ek_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
gd->fb_base = AT91SAM9261_SRAM_BASE;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9261EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9261ek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9261ek_spi_hw_init();
#endif
#ifdef CONFIG_DRIVER_DM9000
at91sam9261ek_dm9000_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9261ek_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

1
board/atmel/at91sam9261ek/config.mk Normal file
View file

@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

78
board/atmel/at91sam9261ek/led.c Normal file
View file

@ -0,0 +1,78 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91_PIN_PA23 /* this is the power led */
#define GREEN_LED AT91_PIN_PA13 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */
void red_LED_on(void)
{
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
at91_set_gpio_value(YELLOW_LED, 1);
}

79
board/atmel/at91sam9261ek/nand.c Normal file
View file

@ -0,0 +1,79 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
#define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */
static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PC14, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PC14, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(AT91_PIN_PC15);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9261ek_nand_hwcontrol;
nand->dev_ready = at91sam9261ek_nand_ready;
nand->chip_delay = 20;
return 0;
}

40
board/atmel/at91sam9261ek/partition.c Normal file
View file

@ -0,0 +1,40 @@
/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};

57
board/atmel/at91sam9263ek/Makefile Normal file
View file

@ -0,0 +1,57 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9263ek.o
COBJS-y += led.o
COBJS-y += partition.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

305
board/atmel/at91sam9263ek/at91sam9263ek.c Normal file
View file

@ -0,0 +1,305 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9263ek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9263ek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA,
csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
1 << AT91SAM9263_ID_PIOCDE);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PA22, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PD15, 1);
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9263ek_spi_hw_init(void)
{
at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
}
#endif
#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
/*
* Disable pull-up on:
* RXDV (PC25) => PHY normal mode (not Test mode)
* ERX0 (PE25) => PHY ADDR0
* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
#endif
}
#endif
#ifdef CONFIG_USB_OHCI_NEW
static void at91sam9263ek_uhp_hw_init(void)
{
/* Enable VBus on UHP ports */
at91_set_gpio_output(AT91_PIN_PA21, 0);
at91_set_gpio_output(AT91_PIN_PA24, 0);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9263_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
}
static void at91sam9263ek_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
gd->fb_base = AT91SAM9263_SRAM0_BASE;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9263ek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9263ek_spi_hw_init();
#endif
#ifdef CONFIG_MACB
at91sam9263ek_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
at91sam9263ek_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9263ek_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

1
board/atmel/at91sam9263ek/config.mk Normal file
View file

@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

78
board/atmel/at91sam9263ek/led.c Normal file
View file

@ -0,0 +1,78 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91_PIN_PB7 /* this is the power led */
#define GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */
void red_LED_on(void)
{
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
1 << AT91SAM9263_ID_PIOCDE);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
at91_set_gpio_value(YELLOW_LED, 1);
}

79
board/atmel/at91sam9263ek/nand.c Normal file
View file

@ -0,0 +1,79 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PD15, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PD15, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(AT91_PIN_PA22);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9263ek_nand_hwcontrol;
nand->dev_ready = at91sam9263ek_nand_ready;
nand->chip_delay = 20;
return 0;
}

39
cpu/at32ap/pm.c → board/atmel/at91sam9263ek/partition.c
View file

@ -1,8 +1,6 @@
/*
* Copyright (C) 2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -18,25 +16,24 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
#ifdef CFG_POWER_MANAGER
#include <asm/errno.h>
#include <asm/io.h>
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
#include <asm/arch/memory-map.h>
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
};
#include "sm.h"
#ifdef CONFIG_PLL
#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
#else
#define MAIN_CLK_RATE (CFG_OSC0_HZ)
#endif
DECLARE_GLOBAL_DATA_PTR;
#endif /* CFG_POWER_MANAGER */
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};

57
board/atmel/at91sam9rlek/Makefile Normal file
View file

@ -0,0 +1,57 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9rlek.o
COBJS-y += led.o
COBJS-y += partition.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

215
board/atmel/at91sam9rlek/at91sam9rlek.c Normal file
View file

@ -0,0 +1,215 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91sam9rl_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9rlek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9rlek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PD17, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PB6, 1);
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9rlek_spi_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA28, 0); /* SPI0_NPCS0 */
at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9RL_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
}
static void at91sam9rlek_lcd_hw_init(void)
{
at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
gd->fb_base = 0;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9RLEK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9rlek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9rlek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9rlek_spi_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9rlek_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}

1
board/atmel/at91sam9rlek/config.mk Normal file
View file

@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

77
board/atmel/at91sam9rlek/led.c Normal file
View file

@ -0,0 +1,77 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91_PIN_PD14 /* this is the power led */
#define GREEN_LED AT91_PIN_PD15 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */
void red_LED_on(void)
{
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
at91_set_gpio_value(YELLOW_LED, 1);
}

79
board/atmel/at91sam9rlek/nand.c Normal file
View file

@ -0,0 +1,79 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PB6, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PB6, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(AT91_PIN_PD17);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9rlek_nand_hwcontrol;
nand->dev_ready = at91sam9rlek_nand_ready;
nand->chip_delay = 20;
return 0;
}

39
board/atmel/at91sam9rlek/partition.c Normal file
View file

@ -0,0 +1,39 @@
/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};

27
board/atmel/atngw100/atngw100.c
View file

@ -25,12 +25,12 @@
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
#include <asm/arch/hmatrix.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct sdram_info sdram = {
.phys_addr = CFG_SDRAM_BASE,
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_16BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
@ -47,8 +47,8 @@ static const struct sdram_info sdram = {
int board_early_init_f(void)
{
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
hmatrix2_writel(SFR4, 1 << 1);
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
gpio_enable_ebi();
gpio_enable_usart1();
@ -66,7 +66,22 @@ int board_early_init_f(void)
long int initdram(int board_type)
{
return sdram_init(&sdram);
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
if (expected_size != actual_size)
printf("Warning: Only %u of %u MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
void board_init_info(void)

9
board/atmel/atngw100/u-boot.lds
View file

@ -29,17 +29,10 @@ SECTIONS
. = 0;
_text = .;
.text : {
*(.exception.text)
*(.text)
*(.text.*)
}
. = ALIGN(32);
__flashprog_start = .;
.flashprog : {
*(.flashprog)
}
. = ALIGN(32);
__flashprog_end = .;
_etext = .;
.rodata : {

54
board/atmel/atstk1000/atstk1000.c
View file

@ -25,13 +25,39 @@
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
#include <asm/arch/hmatrix.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct sdram_info sdram = {
.phys_addr = CFG_SDRAM_BASE,
static const struct sdram_config sdram_config = {
#if defined(CONFIG_ATSTK1006)
/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.cas = 2,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 4,
.txsr = 7,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
#else
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
#ifdef CONFIG_ATSTK1004
.data_bits = SDRAM_DATA_16BIT,
#else
.data_bits = SDRAM_DATA_32BIT,
#endif
#ifdef CONFIG_ATSTK1000_16MB_SDRAM
/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
.row_bits = 12,
#else
.row_bits = 11,
#endif
.col_bits = 8,
.bank_bits = 2,
.cas = 3,
@ -43,12 +69,13 @@ static const struct sdram_info sdram = {
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
#endif
};
int board_early_init_f(void)
{
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
hmatrix2_writel(SFR4, 1 << 1);
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
gpio_enable_ebi();
gpio_enable_usart1();
@ -65,7 +92,22 @@ int board_early_init_f(void)
long int initdram(int board_type)
{
return sdram_init(&sdram);
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
if (expected_size != actual_size)
printf("Warning: Only %u of %u MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
void board_init_info(void)

6
board/atmel/atstk1000/flash.c
View file

@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
flash_info_t flash_info[1];
static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
static void flash_identify(uint16_t *flash, flash_info_t *info)
{
unsigned long flags;
@ -76,7 +76,7 @@ void flash_print_info(flash_info_t *info)
info->size >> 10, info->sector_count);
}
int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
unsigned long flags;
unsigned long start_time;
@ -154,7 +154,7 @@ int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
return ERR_OK;
}
int __flashprog write_buff(flash_info_t *info, uchar *src,
int write_buff(flash_info_t *info, uchar *src,
ulong addr, ulong count)
{
unsigned long flags;

9
board/atmel/atstk1000/u-boot.lds
View file

@ -29,17 +29,10 @@ SECTIONS
. = 0;
_text = .;
.text : {
*(.exception.text)
*(.text)
*(.text.*)
}
. = ALIGN(32);
__flashprog_start = .;
.flashprog : {
*(.flashprog)
}
. = ALIGN(32);
__flashprog_end = .;
_etext = .;
.rodata : {

2
board/dbau1x00/dbau1x00.c
View file

@ -52,7 +52,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
proc_id = read_c0_prid();
switch (proc_id >> 24) {
case 0:

25
board/freescale/mpc8349emds/mpc8349emds.c
View file

@ -257,25 +257,24 @@ void sdram_init(void)
#define SPI_CS_MASK 0x80000000
void spi_eeprom_chipsel(int cs)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
if (cs)
iopd->dat &= ~SPI_CS_MASK;
else
iopd->dat |= SPI_CS_MASK;
iopd->dat &= ~SPI_CS_MASK;
}
/*
* The SPI command uses this table of functions for controlling the SPI
* chip selects.
*/
spi_chipsel_type spi_chipsel[] = {
spi_eeprom_chipsel,
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
iopd->dat |= SPI_CS_MASK;
}
#endif /* CONFIG_HARD_SPI */
#if defined(CONFIG_OF_BOARD_SETUP)

2
board/gth2/gth2.c
View file

@ -135,7 +135,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
proc_id = read_c0_prid();
switch (proc_id >> 24) {
case 0:

2
board/pb1x00/pb1x00.c
View file

@ -51,7 +51,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
proc_id = read_c0_prid();
switch (proc_id >> 24) {
case 0:

6
board/qemu-mips/qemu-mips.c
View file

@ -38,7 +38,7 @@ int checkboard(void)
u32 proc_id;
u32 config1;
proc_id = read_32bit_cp0_register(CP0_PRID);
proc_id = read_c0_prid();
printf("Board: Qemu -M mips CPU: ");
switch (proc_id) {
case 0x00018000:
@ -51,7 +51,7 @@ int checkboard(void)
printf("4KEc");
break;
case 0x00019300:
config1 = read_mips32_cp0_config1();
config1 = read_c0_config1();
if (config1 & 1)
printf("24Kf");
else
@ -64,7 +64,7 @@ int checkboard(void)
printf("R4000");
break;
case 0x00018100:
config1 = read_mips32_cp0_config1();
config1 = read_c0_config1();
if (config1 & 1)
printf("5Kf");
else

51
board/quad100hd/Makefile Normal file
View file

@ -0,0 +1,51 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o nand.o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

24
board/quad100hd/config.mk Normal file
View file

@ -0,0 +1,24 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000

79
board/quad100hd/nand.c Normal file
View file

@ -0,0 +1,79 @@
/*
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#if defined(CONFIG_CMD_NAND)
#include <asm/gpio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd)
{
switch(cmd) {
case NAND_CTL_SETCLE:
gpio_write_bit(CFG_NAND_CLE, 1);
break;
case NAND_CTL_CLRCLE:
gpio_write_bit(CFG_NAND_CLE, 0);
break;
case NAND_CTL_SETALE:
gpio_write_bit(CFG_NAND_ALE, 1);
break;
case NAND_CTL_CLRALE:
gpio_write_bit(CFG_NAND_ALE, 0);
break;
case NAND_CTL_SETNCE:
gpio_write_bit(CFG_NAND_CE, 0);
break;
case NAND_CTL_CLRNCE:
gpio_write_bit(CFG_NAND_CE, 1);
break;
}
}
static int quad100hd_nand_ready(struct mtd_info *mtd)
{
return gpio_read_in_bit(CFG_NAND_RDY);
}
/*
* Main initialization routine
*/
int board_nand_init(struct nand_chip *nand)
{
/* Set address of hardware control function */
nand->hwcontrol = quad100hd_hwcontrol;
nand->dev_ready = quad100hd_nand_ready;
nand->eccmode = NAND_ECC_SOFT;
/* 15 us command delay time */
nand->chip_delay = 20;
/* Return happy */
return 0;
}
#endif /* CONFIG_CMD_NAND */

93
board/quad100hd/quad100hd.c Normal file
View file

@ -0,0 +1,93 @@
/*
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
* Based in part on board/icecube/icecube.c from PPCBoot
* (C) Copyright 2003 Intrinsyc Software
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <environment.h>
#include <logbuff.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* taken from PPCBoot */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7FFE); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
#ifdef DISPLAY_BOARD_INFO
sys_info_t sysinfo;
#endif
puts("Board: Quad100hd");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef DISPLAY_BOARD_INFO
/* taken from ppcboot */
get_sys_info(&sysinfo);
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
1000000));
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
#endif
return 0;
}
long int initdram(int board_type)
{
return CFG_SDRAM_SIZE;
}

133
board/quad100hd/u-boot.lds Normal file
View file

@ -0,0 +1,133 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

51
board/sacsng/sacsng.c
View file

@ -842,36 +842,29 @@ void show_boot_progress (int status)
#define SPI_ADC_CS_MASK 0x00000800
#define SPI_DAC_CS_MASK 0x00001000
void spi_adc_chipsel(int cs)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
if(cs)
iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */
else
iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */
}
void spi_dac_chipsel(int cs)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
if(cs)
iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */
else
iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */
}
/*
* The SPI command uses this table of functions for controlling the SPI
* chip selects: it calls the appropriate function to control the SPI
* chip selects.
*/
spi_chipsel_type spi_chipsel[] = {
spi_adc_chipsel,
spi_dac_chipsel
static const u32 cs_mask[] = {
SPI_ADC_CS_MASK,
SPI_DAC_CS_MASK,
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
iopd->pdat &= ~cs_mask[slave->cs];
}
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
iopd->pdat |= cs_mask[slave->cs];
}
#endif

27
board/ssv/adnpesc1/adnpesc1.c
View file

@ -69,25 +69,24 @@ long int initdram (int board_type)
#define SPI_RTC_CS_MASK 0x00000001
void spi_rtc_chipsel(int cs)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
if (cs)
spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */
else
spi->slaveselect = 0; /* deactivate (0) */
spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */
}
/*
* The SPI command uses this table of functions for controlling the SPI
* chip selects: it calls the appropriate function to control the SPI
* chip selects.
*/
spi_chipsel_type spi_chipsel[] = {
spi_rtc_chipsel
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
void spi_cs_deactivate(struct spi_slave *slave)
{
nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
spi->slaveselect = 0; /* deactivate (0) */
}
#endif

2
common/Makefile
View file

@ -113,6 +113,7 @@ COBJS-y += env_dataflash.o
COBJS-y += env_flash.o
COBJS-y += env_eeprom.o
COBJS-y += env_onenand.o
COBJS-y += env_sf.o
COBJS-y += env_nvram.o
COBJS-y += env_nowhere.o
COBJS-y += exports.o
@ -143,6 +144,7 @@ COBJS-y += xyzModem.o
COBJS-y += cmd_mac.o
COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
COBJS-$(CONFIG_MP) += cmd_mp.o
COBJS-$(CONFIG_CMD_SF) += cmd_sf.o
COBJS := $(COBJS-y)
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)

37
common/cmd_df.c Normal file
View file

@ -0,0 +1,37 @@
/*
* Command for accessing DataFlash.
*
* Copyright (C) 2008 Atmel Corporation
*/
#include <common.h>
#include <df.h>
static int do_df(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
const char *cmd;
/* need at least two arguments */
if (argc < 2)
goto usage;
cmd = argv[1];
if (strcmp(cmd, "init") == 0) {
df_init(0, 0, 1000000);
return 0;
}
if (strcmp(cmd, "info") == 0) {
df_show_info();
return 0;
}
usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
sf, 2, 1, do_serial_flash,
"sf - Serial flash sub-system\n",
"probe [bus:]cs - init flash device on given SPI bus and CS\n")

8
common/cmd_log.c
View file

@ -66,6 +66,12 @@ static logbuff_t *log;
#endif
static char *lbuf;
unsigned long __logbuffer_base(void)
{
return CFG_SDRAM_BASE + gd->bd->bi_memsize - LOGBUFF_LEN;
}
unsigned long logbuffer_base (void) __attribute__((weak, alias("__logbuffer_base")));
void logbuff_init_ptrs (void)
{
unsigned long tag, post_word;
@ -75,7 +81,7 @@ void logbuff_init_ptrs (void)
log = (logbuff_t *)CONFIG_ALT_LH_ADDR;
lbuf = (char *)CONFIG_ALT_LB_ADDR;
#else
log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1;
log = (logbuff_t *)(logbuffer_base ()) - 1;
lbuf = (char *)log->buf;
#endif

2
common/cmd_nand.c
View file

@ -37,8 +37,6 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
u8 *part_num, struct part_info **part);
#endif
extern nand_info_t nand_info[]; /* info for NAND chips */
static int nand_dump_oob(nand_info_t *nand, ulong off)
{
return 0;

3
common/cmd_nvedit.c
View file

@ -58,8 +58,9 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CFG_ENV_IS_IN_DATAFLASH) && \
!defined(CFG_ENV_IS_IN_NAND) && \
!defined(CFG_ENV_IS_IN_ONENAND) && \
!defined(CFG_ENV_IS_IN_SPI_FLASH) && \
!defined(CFG_ENV_IS_NOWHERE)
# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE}
# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|SPI_FLASH|NOWHERE}
#endif
#define XMK_STR(x) #x

191
common/cmd_sf.c Normal file
View file

@ -0,0 +1,191 @@
/*
* Command for accessing SPI flash.
*
* Copyright (C) 2008 Atmel Corporation
*/
#include <common.h>
#include <spi_flash.h>
#include <asm/io.h>
#ifndef CONFIG_SF_DEFAULT_SPEED
# define CONFIG_SF_DEFAULT_SPEED 1000000
#endif
#ifndef CONFIG_SF_DEFAULT_MODE
# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#endif
static struct spi_flash *flash;
static int do_spi_flash_probe(int argc, char *argv[])
{
unsigned int bus = 0;
unsigned int cs;
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
struct spi_flash *new;
if (argc < 2)
goto usage;
cs = simple_strtoul(argv[1], &endp, 0);
if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
goto usage;
if (*endp == ':') {
if (endp[1] == 0)
goto usage;
bus = cs;
cs = simple_strtoul(endp + 1, &endp, 0);
if (*endp != 0)
goto usage;
}
if (argc >= 3) {
speed = simple_strtoul(argv[2], &endp, 0);
if (*argv[2] == 0 || *endp != 0)
goto usage;
}
if (argc >= 4) {
mode = simple_strtoul(argv[3], &endp, 0);
if (*argv[3] == 0 || *endp != 0)
goto usage;
}
new = spi_flash_probe(bus, cs, speed, mode);
if (!new) {
printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
if (flash)
spi_flash_free(flash);
flash = new;
printf("%u KiB %s at %u:%u is now current device\n",
flash->size >> 10, flash->name, bus, cs);
return 0;
usage:
puts("Usage: sf probe [bus:]cs [hz] [mode]\n");
return 1;
}
static int do_spi_flash_read_write(int argc, char *argv[])
{
unsigned long addr;
unsigned long offset;
unsigned long len;
void *buf;
char *endp;
int ret;
if (argc < 4)
goto usage;
addr = simple_strtoul(argv[1], &endp, 16);
if (*argv[1] == 0 || *endp != 0)
goto usage;
offset = simple_strtoul(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
goto usage;
len = simple_strtoul(argv[3], &endp, 16);
if (*argv[3] == 0 || *endp != 0)
goto usage;
buf = map_physmem(addr, len, MAP_WRBACK);
if (!buf) {
puts("Failed to map physical memory\n");
return 1;
}
if (strcmp(argv[0], "read") == 0)
ret = spi_flash_read(flash, offset, len, buf);
else
ret = spi_flash_write(flash, offset, len, buf);
unmap_physmem(buf, len);
if (ret) {
printf("SPI flash %s failed\n", argv[0]);
return 1;
}
return 0;
usage:
printf("Usage: sf %s addr offset len\n", argv[0]);
return 1;
}
static int do_spi_flash_erase(int argc, char *argv[])
{
unsigned long offset;
unsigned long len;
char *endp;
int ret;
if (argc < 3)
goto usage;
offset = simple_strtoul(argv[1], &endp, 16);
if (*argv[1] == 0 || *endp != 0)
goto usage;
len = simple_strtoul(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
goto usage;
ret = spi_flash_erase(flash, offset, len);
if (ret) {
printf("SPI flash %s failed\n", argv[0]);
return 1;
}
return 0;
usage:
puts("Usage: sf erase offset len\n");
return 1;
}
static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
const char *cmd;
/* need at least two arguments */
if (argc < 2)
goto usage;
cmd = argv[1];
if (strcmp(cmd, "probe") == 0)
return do_spi_flash_probe(argc - 1, argv + 1);
/* The remaining commands require a selected device */
if (!flash) {
puts("No SPI flash selected. Please run `sf probe'\n");
return 1;
}
if (strcmp(cmd, "read") == 0 || strcmp(cmd, "write") == 0)
return do_spi_flash_read_write(argc - 1, argv + 1);
if (strcmp(cmd, "erase") == 0)
return do_spi_flash_erase(argc - 1, argv + 1);
usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
sf, 5, 1, do_spi_flash,
"sf - SPI flash sub-system\n",
"probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n"
" and chip select\n"
"sf read addr offset len - read `len' bytes starting at\n"
" `offset' to memory at `addr'\n"
"sf write addr offset len - write `len' bytes from memory\n"
" at `addr' to flash at `offset'\n"
"sf erase offset len - erase `len' bytes from `offset'\n");

42
common/cmd_spi.c
View file

@ -37,20 +37,20 @@
# define MAX_SPI_BYTES 32 /* Maximum number of bytes we can handle */
#endif
/*
* External table of chip select functions (see the appropriate board
* support for the actual definition of the table).
*/
extern spi_chipsel_type spi_chipsel[];
extern int spi_chipsel_cnt;
#ifndef CONFIG_DEFAULT_SPI_BUS
# define CONFIG_DEFAULT_SPI_BUS 0
#endif
#ifndef CONFIG_DEFAULT_SPI_MODE
# define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
#endif
/*
* Values from last command.
*/
static int device;
static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
static unsigned int device;
static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
/*
* SPI read/write
@ -65,6 +65,7 @@ static uchar din[MAX_SPI_BYTES];
int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
struct spi_slave *slave;
char *cp = 0;
uchar tmp;
int j;
@ -101,19 +102,24 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
}
if ((device < 0) || (device >= spi_chipsel_cnt)) {
printf("Invalid device %d, giving up.\n", device);
return 1;
}
if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) {
printf("Invalid bitlen %d, giving up.\n", bitlen);
return 1;
}
debug ("spi_chipsel[%d] = %08X\n",
device, (uint)spi_chipsel[device]);
/* FIXME: Make these parameters run-time configurable */
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000,
CONFIG_DEFAULT_SPI_MODE);
if (!slave) {
printf("Invalid device %d, giving up.\n", device);
return 1;
}
if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) {
debug ("spi chipsel = %08X\n", device);
spi_claim_bus(slave);
if(spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
printf("Error with the SPI transaction.\n");
rcode = 1;
} else {
@ -123,6 +129,8 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf("\n");
}
spi_release_bus(slave);
spi_free_slave(slave);
return rcode;
}

3
common/dlmalloc.c
View file

@ -1,3 +1,5 @@
#include <common.h>
#if 0 /* Moved to malloc.h */
/* ---------- To make a malloc.h, start cutting here ------------ */
@ -947,7 +949,6 @@ void malloc_stats();
#endif /* 0 */
#endif /* 0 */ /* Moved to malloc.h */
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;

3
common/env_common.c
View file

@ -134,7 +134,8 @@ uchar default_environment[] = {
"\0"
};
#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */
#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ \
|| defined(CFG_ENV_IS_IN_SPI_FLASH)
int default_environment_size = sizeof(default_environment);
#endif

3
common/env_nand.c
View file

@ -57,9 +57,6 @@ int nand_legacy_rw (struct nand_chip* nand, int cmd,
size_t start, size_t len,
size_t * retlen, u_char * buf);
/* info for NAND chips, defined in drivers/mtd/nand/nand.c */
extern nand_info_t nand_info[];
/* references to names in env_common.c */
extern uchar default_environment[];
extern int default_environment_size;

131
common/env_sf.c Normal file
View file

@ -0,0 +1,131 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* (C) Copyright 2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#ifdef CFG_ENV_IS_IN_SPI_FLASH
#include <environment.h>
#include <spi_flash.h>
#ifndef CFG_ENV_SPI_BUS
# define CFG_ENV_SPI_BUS 0
#endif
#ifndef CFG_ENV_SPI_CS
# define CFG_ENV_SPI_CS 0
#endif
#ifndef CFG_ENV_SPI_MAX_HZ
# define CFG_ENV_SPI_MAX_HZ 1000000
#endif
#ifndef CFG_ENV_SPI_MODE
# define CFG_ENV_SPI_MODE SPI_MODE_3
#endif
DECLARE_GLOBAL_DATA_PTR;
/* references to names in env_common.c */
extern uchar default_environment[];
extern int default_environment_size;
char * env_name_spec = "SPI Flash";
env_t *env_ptr;
static struct spi_flash *env_flash;
uchar env_get_char_spec(int index)
{
return *((uchar *)(gd->env_addr + index));
}
int saveenv(void)
{
if (!env_flash) {
puts("Environment SPI flash not initialized\n");
return 1;
}
puts("Erasing SPI flash...");
if (spi_flash_erase(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE))
return 1;
puts("Writing to SPI flash...");
if (spi_flash_write(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE, env_ptr))
return 1;
puts("done\n");
return 0;
}
void env_relocate_spec(void)
{
int ret;
env_flash = spi_flash_probe(CFG_ENV_SPI_BUS, CFG_ENV_SPI_CS,
CFG_ENV_SPI_MAX_HZ, CFG_ENV_SPI_MODE);
if (!env_flash)
goto err_probe;
ret = spi_flash_read(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE, env_ptr);
if (ret)
goto err_read;
if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc)
goto err_crc;
gd->env_valid = 1;
return;
err_read:
spi_flash_free(env_flash);
env_flash = NULL;
err_probe:
err_crc:
puts("*** Warning - bad CRC, using default environment\n\n");
if (default_environment_size > CFG_ENV_SIZE) {
gd->env_valid = 0;
puts("*** Error - default environment is too large\n\n");
return;
}
memset(env_ptr, 0, sizeof(env_t));
memcpy(env_ptr->data, default_environment, default_environment_size);
env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
gd->env_valid = 1;
}
int env_init(void)
{
/* SPI flash isn't usable before relocation */
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 1;
return 0;
}
#endif /* CFG_ENV_IS_IN_SPI_FLASH */

10
common/image.c
View file

@ -35,6 +35,10 @@
#include <dataflash.h>
#endif
#ifdef CONFIG_LOGBUFFER
#include <logbuff.h>
#endif
#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
#include <rtc.h>
#endif
@ -1013,6 +1017,12 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len,
initrd_high = ~0;
}
#ifdef CONFIG_LOGBUFFER
/* Prevent initrd from overwriting logbuffer */
lmb_reserve(lmb, logbuffer_base() - LOGBUFF_OVERHEAD, LOGBUFF_RESERVE);
#endif
debug ("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
initrd_high, initrd_copy_to_ram);

78
common/lcd.c
View file

@ -50,6 +50,11 @@
#include <lcdvideo.h>
#endif
#if defined(CONFIG_ATMEL_LCD)
#include <atmel_lcdc.h>
#include <nand.h>
#endif
#ifdef CONFIG_LCD
/************************************************************************/
@ -474,14 +479,22 @@ ulong lcd_setmem (ulong addr)
static void lcd_setfgcolor (int color)
{
#ifdef CONFIG_ATMEL_LCD
lcd_color_fg = color;
#else
lcd_color_fg = color & 0x0F;
#endif
}
/*----------------------------------------------------------------------*/
static void lcd_setbgcolor (int color)
{
#ifdef CONFIG_ATMEL_LCD
lcd_color_bg = color;
#else
lcd_color_bg = color & 0x0F;
#endif
}
/*----------------------------------------------------------------------*/
@ -508,7 +521,11 @@ static int lcd_getbgcolor (void)
#ifdef CONFIG_LCD_LOGO
void bitmap_plot (int x, int y)
{
#ifdef CONFIG_ATMEL_LCD
uint *cmap;
#else
ushort *cmap;
#endif
ushort i, j;
uchar *bmap;
uchar *fb;
@ -533,6 +550,8 @@ void bitmap_plot (int x, int y)
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
#elif defined(CONFIG_ATMEL_LCD)
cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
#endif
WATCHDOG_RESET();
@ -540,11 +559,26 @@ void bitmap_plot (int x, int y)
/* Set color map */
for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) {
ushort colreg = bmp_logo_palette[i];
#ifdef CONFIG_ATMEL_LCD
uint lut_entry;
#ifdef CONFIG_ATMEL_LCD_BGR555
lut_entry = ((colreg & 0x000F) << 11) |
((colreg & 0x00F0) << 2) |
((colreg & 0x0F00) >> 7);
#else /* CONFIG_ATMEL_LCD_RGB565 */
lut_entry = ((colreg & 0x000F) << 1) |
((colreg & 0x00F0) << 3) |
((colreg & 0x0F00) << 4);
#endif
*(cmap + BMP_LOGO_OFFSET) = lut_entry;
cmap++;
#else /* !CONFIG_ATMEL_LCD */
#ifdef CFG_INVERT_COLORS
*cmap++ = 0xffff - colreg;
#else
*cmap++ = colreg;
#endif
#endif /* CONFIG_ATMEL_LCD */
}
WATCHDOG_RESET();
@ -578,7 +612,9 @@ void bitmap_plot (int x, int y)
*/
int lcd_display_bitmap(ulong bmp_image, int x, int y)
{
#if !defined(CONFIG_MCC200)
#ifdef CONFIG_ATMEL_LCD
uint *cmap;
#elif !defined(CONFIG_MCC200)
ushort *cmap;
#endif
ushort i, j;
@ -633,6 +669,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
#elif defined(CONFIG_ATMEL_LCD)
cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
#else
# error "Don't know location of color map"
#endif
@ -708,6 +746,10 @@ static void *lcd_logo (void)
#ifdef CONFIG_LCD_INFO
char info[80];
char temp[32];
#ifdef CONFIG_ATMEL_LCD
int i;
ulong dram_size, nand_size;
#endif
#endif /* CONFIG_LCD_INFO */
#ifdef CONFIG_SPLASH_SCREEN
@ -765,6 +807,40 @@ static void *lcd_logo (void)
# endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_ATMEL_LCD
# ifdef CONFIG_LCD_INFO
sprintf (info, "%s", U_BOOT_VERSION);
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info));
sprintf (info, "(C) 2008 ATMEL Corp");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT,
(uchar *)info, strlen(info));
sprintf (info, "at91support@atmel.com");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2,
(uchar *)info, strlen(info));
sprintf (info, "%s CPU at %s MHz",
AT91_CPU_NAME,
strmhz(temp, AT91_MAIN_CLOCK));
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3,
(uchar *)info, strlen(info));
dram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CFG_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
sprintf (info, " %ld MB SDRAM, %ld MB NAND",
dram_size >> 20,
nand_size >> 20 );
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
(uchar *)info, strlen(info));
# endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_ATMEL_LCD */
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length));
#else

6
common/main.c
View file

@ -940,12 +940,6 @@ int readline_into_buffer (const char *const prompt, char * buffer)
int rc;
static int initted = 0;
if (!initted) {
hist_init();
initted = 1;
}
/*
* History uses a global array which is not
* writable until after relocation to RAM.

1
common/soft_i2c.c
View file

@ -252,6 +252,7 @@ static uchar read_byte(int ack)
* Read 8 bits, MSB first.
*/
I2C_TRISTATE;
I2C_SDA(1);
data = 0;
for(j = 0; j < 8; j++) {
I2C_SCL(0);

124
common/soft_spi.c
View file

@ -29,6 +29,8 @@
#if defined(CONFIG_SOFT_SPI)
#include <malloc.h>
/*-----------------------------------------------------------------------
* Definitions
*/
@ -39,6 +41,15 @@
#define PRINTD(fmt,args...)
#endif
struct soft_spi_slave {
struct spi_slave slave;
unsigned int mode;
};
static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave)
{
return container_of(slave, struct soft_spi_slave, slave);
}
/*=====================================================================*/
/* Public Functions */
@ -56,6 +67,57 @@ void spi_init (void)
#endif
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct soft_spi_slave *ss;
if (!spi_cs_is_valid(bus, cs))
return NULL;
ss = malloc(sizeof(struct soft_spi_slave));
if (!ss)
return NULL;
ss->slave.bus = bus;
ss->slave.cs = cs;
ss->mode = mode;
/* TODO: Use max_hz to limit the SCK rate */
return &ss->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct soft_spi_slave *ss = to_soft_spi(slave);
free(ss);
}
int spi_claim_bus(struct spi_slave *slave)
{
#ifdef CFG_IMMR
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
struct soft_spi_slave *ss = to_soft_spi(slave);
/*
* Make sure the SPI clock is in idle state as defined for
* this slave.
*/
if (ss->mode & SPI_CPOL)
SPI_SCL(1);
else
SPI_SCL(0);
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
/* Nothing to do */
}
/*-----------------------------------------------------------------------
* SPI transfer
@ -68,50 +130,54 @@ void spi_init (void)
* and "din" can point to the same memory location, in which case the
* input data overwrites the output data (since both are buffered by
* temporary variables, this is OK).
*
* If the chipsel() function is not NULL, it is called with a parameter
* of '1' (chip select active) at the start of the transfer and again with
* a parameter of '0' at the end of the transfer.
*
* If the chipsel() function _is_ NULL, it the responsibility of the
* caller to make the appropriate chip select active before calling
* spi_xfer() and making it inactive after spi_xfer() returns.
*/
int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
#ifdef CFG_IMMR
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
uchar tmpdin = 0;
uchar tmpdout = 0;
int j;
struct soft_spi_slave *ss = to_soft_spi(slave);
uchar tmpdin = 0;
uchar tmpdout = 0;
const u8 *txd = dout;
u8 *rxd = din;
int cpol = ss->mode & SPI_CPOL;
int cpha = ss->mode & SPI_CPHA;
unsigned int j;
PRINTD("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
(int)chipsel, *(uint *)dout, *(uint *)din, bitlen);
PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen);
if(chipsel != NULL) {
(*chipsel)(1); /* select the target chip */
}
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
for(j = 0; j < bitlen; j++) {
/*
* Check if it is time to work on a new byte.
*/
if((j % 8) == 0) {
tmpdout = *dout++;
tmpdout = *txd++;
if(j != 0) {
*din++ = tmpdin;
*rxd++ = tmpdin;
}
tmpdin = 0;
}
SPI_SCL(0);
if (!cpha)
SPI_SCL(!cpol);
SPI_SDA(tmpdout & 0x80);
SPI_DELAY;
SPI_SCL(1);
if (cpha)
SPI_SCL(!cpol);
else
SPI_SCL(cpol);
tmpdin <<= 1;
tmpdin |= SPI_READ;
tmpdout <<= 1;
SPI_DELAY;
tmpdin <<= 1;
tmpdin |= SPI_READ;
tmpdout <<= 1;
if (cpha)
SPI_SCL(cpol);
}
/*
* If the number of bits isn't a multiple of 8, shift the last
@ -120,14 +186,10 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
*/
if((bitlen % 8) != 0)
tmpdin <<= 8 - (bitlen % 8);
*din++ = tmpdin;
*rxd++ = tmpdin;
SPI_SCL(0); /* SPI wants the clock left low for idle */
if(chipsel != NULL) {
(*chipsel)(0); /* deselect the target chip */
}
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
return(0);
}

6
cpu/74xx_7xx/start.S
View file

@ -316,7 +316,7 @@ invalidate_bats:
mtspr IBAT1U, r0
mtspr IBAT2U, r0
mtspr IBAT3U, r0
#ifdef CONFIG_750FX
#ifdef CONFIG_HIGH_BATS
mtspr IBAT4U, r0
mtspr IBAT5U, r0
mtspr IBAT6U, r0
@ -327,7 +327,7 @@ invalidate_bats:
mtspr DBAT1U, r0
mtspr DBAT2U, r0
mtspr DBAT3U, r0
#ifdef CONFIG_750FX
#ifdef CONFIG_HIGH_BATS
mtspr DBAT4U, r0
mtspr DBAT5U, r0
mtspr DBAT6U, r0
@ -414,7 +414,7 @@ setup_bats:
mtspr DBAT3U, r3
isync
#ifdef CONFIG_750FX
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
addis r4, r0, CFG_IBAT4L@h
ori r4, r4, CFG_IBAT4L@l

1
cpu/arm926ejs/at91sam9/config.mk
View file

@ -1,2 +1,3 @@
PLATFORM_CPPFLAGS += -march=armv5te
PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91sam9/u-boot.lds

0
board/atmel/at91cap9adk/u-boot.lds → cpu/arm926ejs/at91sam9/u-boot.lds
View file

8
cpu/arm926ejs/at91sam9/usb.c
View file

@ -33,7 +33,11 @@ int usb_cpu_init(void)
{
/* Enable USB host clock. */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
#ifdef CONFIG_AT91SAM9261
at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0);
#else
at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP);
#endif
return 0;
}
@ -42,7 +46,11 @@ int usb_cpu_stop(void)
{
/* Disable USB host clock. */
at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP);
#ifdef CONFIG_AT91SAM9261
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0);
#else
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
#endif
return 0;
}

20
cpu/at32ap/Makefile
View file

@ -27,13 +27,19 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(CPU).a
START := start.o
SOBJS := entry.o
COBJS := cpu.o hsdramc.o exception.o cache.o
COBJS += interrupts.o pio.o atmel_mci.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
START-y += start.o
COBJS-y += cpu.o
COBJS-y += hsdramc.o
COBJS-y += exception.o
COBJS-y += cache.o
COBJS-y += interrupts.o
COBJS-y += pio.o
COBJS-$(CONFIG_MMC) += atmel_mci.o
SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
START := $(addprefix $(obj),$(START-y))
all: $(obj).depend $(START) $(LIB)

2
cpu/at32ap/at32ap700x/Makefile
View file

@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(SOC).a
COBJS := gpio.o
COBJS := gpio.o clk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

68
cpu/at32ap/at32ap700x/clk.c Normal file
View file

@ -0,0 +1,68 @@
/*
* Copyright (C) 2005-2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/memory-map.h>
#include "sm.h"
void clk_init(void)
{
uint32_t cksel;
/* in case of soft resets, disable watchdog */
sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
#ifdef CONFIG_PLL
/* Initialize the PLL */
sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
| SM_BF(PLLOPT, CFG_PLL0_OPT)
| SM_BF(PLLOSC, 0)
| SM_BIT(PLLEN)));
/* Wait for lock */
while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
#endif
/* Set up clocks for the CPU and all peripheral buses */
cksel = 0;
if (CFG_CLKDIV_CPU)
cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
if (CFG_CLKDIV_HSB)
cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
if (CFG_CLKDIV_PBA)
cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
if (CFG_CLKDIV_PBB)
cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
sm_writel(PM_CKSEL, cksel);
#ifdef CONFIG_PLL
/* Use PLL0 as main clock */
sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
#endif
}

43
cpu/at32ap/at32ap700x/gpio.c
View file

@ -21,8 +21,11 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/chip-features.h>
#include <asm/arch/gpio.h>
#include <asm/arch/memory-map.h>
/*
* Lots of small functions here. We depend on --gc-sections getting
@ -142,3 +145,43 @@ void gpio_enable_mmci(void)
gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */
}
#endif
#ifdef AT32AP700x_CHIP_HAS_SPI
void gpio_enable_spi0(unsigned long cs_mask)
{
u32 pa_mask = 0;
gpio_select_periph_A(GPIO_PIN_PA0, 0); /* MISO */
gpio_select_periph_A(GPIO_PIN_PA1, 0); /* MOSI */
gpio_select_periph_A(GPIO_PIN_PA2, 0); /* SCK */
if (cs_mask & (1 << 0))
pa_mask |= 1 << 3; /* NPCS0 */
if (cs_mask & (1 << 1))
pa_mask |= 1 << 4; /* NPCS1 */
if (cs_mask & (1 << 2))
pa_mask |= 1 << 5; /* NPCS2 */
if (cs_mask & (1 << 3))
pa_mask |= 1 << 20; /* NPCS3 */
__raw_writel(pa_mask, PIOA_BASE + 0x00);
__raw_writel(pa_mask, PIOA_BASE + 0x30);
__raw_writel(pa_mask, PIOA_BASE + 0x10);
}
void gpio_enable_spi1(unsigned long cs_mask)
{
gpio_select_periph_B(GPIO_PIN_PA0, 0); /* MISO */
gpio_select_periph_B(GPIO_PIN_PB1, 0); /* MOSI */
gpio_select_periph_B(GPIO_PIN_PB5, 0); /* SCK */
if (cs_mask & (1 << 0))
gpio_select_periph_B(GPIO_PIN_PB2, 0); /* NPCS0 */
if (cs_mask & (1 << 1))
gpio_select_periph_B(GPIO_PIN_PB3, 0); /* NPCS1 */
if (cs_mask & (1 << 2))
gpio_select_periph_B(GPIO_PIN_PB4, 0); /* NPCS2 */
if (cs_mask & (1 << 3))
gpio_select_periph_A(GPIO_PIN_PA27, 0); /* NPCS3 */
}
#endif

0
cpu/at32ap/sm.h → cpu/at32ap/at32ap700x/sm.h
View file

12
cpu/at32ap/atmel_mci.c
View file

@ -21,8 +21,6 @@
*/
#include <common.h>
#ifdef CONFIG_MMC
#include <part.h>
#include <mmc.h>
@ -139,7 +137,7 @@ mmc_cmd(unsigned long cmd, unsigned long arg,
pr_debug("mmc: status 0x%08lx\n", status);
if (status & ERROR_FLAGS) {
if (status & error_flags) {
printf("mmc: command %lu failed (status: 0x%08lx)\n",
cmd, status);
return -EIO;
@ -182,12 +180,13 @@ static int mmc_acmd(unsigned long cmd, unsigned long arg,
static unsigned long
mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
unsigned long *buffer)
void *buffer)
{
int ret, i = 0;
unsigned long resp[4];
unsigned long card_status, data;
unsigned long wordcount;
u32 *p = buffer;
u32 status;
if (blkcnt == 0)
@ -225,7 +224,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
if (status & MMCI_BIT(RXRDY)) {
data = mmci_readl(RDR);
/* pr_debug("%x\n", data); */
*buffer++ = data;
*p++ = data;
wordcount++;
}
} while(wordcount < (mmc_blkdev.blksz / 4));
@ -443,6 +442,7 @@ static void mci_set_data_timeout(struct mmc_csd *csd)
dtocyc = timeout_clks;
dtomul = 0;
shift = 0;
while (dtocyc > 15 && dtomul < 8) {
dtomul++;
shift = dtomul_to_shift[dtomul];
@ -546,5 +546,3 @@ int mmc2info(ulong addr)
{
return 0;
}
#endif /* CONFIG_MMC */

50
cpu/at32ap/cpu.c
View file

@ -30,7 +30,6 @@
#include <asm/arch/memory-map.h>
#include "hsmc3.h"
#include "sm.h"
/* Sanity checks */
#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
@ -44,47 +43,9 @@
DECLARE_GLOBAL_DATA_PTR;
static void pm_init(void)
{
uint32_t cksel;
#ifdef CONFIG_PLL
/* Initialize the PLL */
sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
| SM_BF(PLLOPT, CFG_PLL0_OPT)
| SM_BF(PLLOSC, 0)
| SM_BIT(PLLEN)));
/* Wait for lock */
while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
#endif
/* Set up clocks for the CPU and all peripheral buses */
cksel = 0;
if (CFG_CLKDIV_CPU)
cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
if (CFG_CLKDIV_HSB)
cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
if (CFG_CLKDIV_PBA)
cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
if (CFG_CLKDIV_PBB)
cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
sm_writel(PM_CKSEL, cksel);
gd->cpu_hz = get_cpu_clk_rate();
#ifdef CONFIG_PLL
/* Use PLL0 as main clock */
sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
#endif
}
int cpu_init(void)
{
extern void _evba(void);
char *p;
gd->cpu_hz = CFG_OSC0_HZ;
@ -95,16 +56,15 @@ int cpu_init(void)
hsmc3_writel(PULSE0, 0x0b0a0906);
hsmc3_writel(SETUP0, 0x00010002);
pm_init();
clk_init();
/* Update the CPU speed according to the PLL configuration */
gd->cpu_hz = get_cpu_clk_rate();
/* Set up the exception handler table and enable exceptions */
sysreg_write(EVBA, (unsigned long)&_evba);
asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
/* Lock everything that mess with the flash in the icache */
for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
p += CFG_ICACHE_LINESZ)
asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
return 0;
}

64
cpu/at32ap/entry.S
View file

@ -1,64 +0,0 @@
/*
* Copyright (C) 2004-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/sysreg.h>
#include <asm/ptrace.h>
.section .text.exception,"ax"
.global _evba
.type _evba,@function
.align 10
_evba:
.irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
.align 2
rjmp unknown_exception
.endr
.global timer_interrupt_handler
.type timer_interrupt_handler,@function
.align 2
timer_interrupt_handler:
/*
* Increment timer_overflow and re-write COMPARE with 0xffffffff.
*
* We're running at interrupt level 3, so we don't need to save
* r8-r12 or lr to the stack.
*/
lda.w r8, timer_overflow
ld.w r9, r8[0]
mov r10, -1
mtsr SYSREG_COMPARE, r10
sub r9, -1
st.w r8[0], r9
rete
.type unknown_exception, @function
unknown_exception:
pushm r0-r12
sub r8, sp, REG_R12 - REG_R0 - 4
mov r9, lr
mfsr r10, SYSREG_RAR_EX
mfsr r11, SYSREG_RSR_EX
pushm r8-r11
mfsr r12, SYSREG_ECR
mov r11, sp
rcall do_unknown_exception
1: rjmp 1b

3
cpu/at32ap/exception.c
View file

@ -111,7 +111,8 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
printf("CPU Mode: %s\n", cpu_modes[mode]);
/* Avoid exception loops */
if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end)
if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE)
|| regs->sp >= gd->stack_end)
printf("\nStack pointer seems bogus, won't do stack dump\n");
else
dump_mem("\nStack: ", regs->sp, gd->stack_end);

94
cpu/at32ap/hsdramc.c
View file

@ -30,39 +30,32 @@
#include "hsdramc1.h"
unsigned long sdram_init(const struct sdram_info *info)
unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
{
unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
unsigned long sdram_size;
unsigned long tmp;
unsigned long bus_hz;
uint32_t cfgreg;
unsigned int i;
if (!info->refresh_period)
panic("ERROR: SDRAM refresh period == 0. "
"Please update the board code\n");
cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
| HSDRAMC1_BF(NR, config->row_bits - 11)
| HSDRAMC1_BF(NB, config->bank_bits - 1)
| HSDRAMC1_BF(CAS, config->cas)
| HSDRAMC1_BF(TWR, config->twr)
| HSDRAMC1_BF(TRC, config->trc)
| HSDRAMC1_BF(TRP, config->trp)
| HSDRAMC1_BF(TRCD, config->trcd)
| HSDRAMC1_BF(TRAS, config->tras)
| HSDRAMC1_BF(TXSR, config->txsr));
tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
| HSDRAMC1_BF(NR, info->row_bits - 11)
| HSDRAMC1_BF(NB, info->bank_bits - 1)
| HSDRAMC1_BF(CAS, info->cas)
| HSDRAMC1_BF(TWR, info->twr)
| HSDRAMC1_BF(TRC, info->trc)
| HSDRAMC1_BF(TRP, info->trp)
| HSDRAMC1_BF(TRCD, info->trcd)
| HSDRAMC1_BF(TRAS, info->tras)
| HSDRAMC1_BF(TXSR, info->txsr));
if (config->data_bits == SDRAM_DATA_16BIT)
cfgreg |= HSDRAMC1_BIT(DBW);
#ifdef CFG_SDRAM_16BIT
tmp |= HSDRAMC1_BIT(DBW);
sdram_size = 1 << (info->row_bits + info->col_bits
+ info->bank_bits + 1);
#else
sdram_size = 1 << (info->row_bits + info->col_bits
+ info->bank_bits + 2);
#endif
hsdramc1_writel(CR, cfgreg);
hsdramc1_writel(CR, tmp);
/* Send a NOP to turn on the clock (necessary on some chips) */
hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
hsdramc1_readl(MR);
writel(0, sdram_base);
/*
* Initialization sequence for SDRAM, from the data sheet:
@ -77,7 +70,7 @@ unsigned long sdram_init(const struct sdram_info *info)
*/
hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
hsdramc1_readl(MR);
writel(0, sdram);
writel(0, sdram_base);
/*
* 3. Eight auto-refresh (CBR) cycles are provided
@ -85,58 +78,41 @@ unsigned long sdram_init(const struct sdram_info *info)
hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
hsdramc1_readl(MR);
for (i = 0; i < 8; i++)
writel(0, sdram);
writel(0, sdram_base);
/*
* 4. A mode register set (MRS) cycle is issued to program
* SDRAM parameters, in particular CAS latency and burst
* length.
*
* CAS from info struct, burst length 1, serial burst type
* The address will be chosen by the SDRAMC automatically; we
* just have to make sure BA[1:0] are set to 0.
*/
hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
hsdramc1_readl(MR);
writel(0, sdram + (info->cas << 4));
writel(0, sdram_base);
/*
* 5. A Normal Mode command is provided, 3 clocks after tMRD
* is met.
*
* From the timing diagram, it looks like tMRD is 3
* cycles...try a dummy read from the peripheral bus.
* 5. The application must go into Normal Mode, setting Mode
* to 0 in the Mode Register and performing a write access
* at any location in the SDRAM.
*/
hsdramc1_readl(MR);
hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
hsdramc1_readl(MR);
writel(0, sdram);
writel(0, sdram_base);
/*
* 6. Write refresh rate into SDRAMC refresh timer count
* register (refresh rate = timing between refresh cycles).
*
* 15.6 us is a typical value for a burst of length one
*/
bus_hz = get_sdram_clk_rate();
hsdramc1_writel(TR, info->refresh_period);
hsdramc1_writel(TR, config->refresh_period);
printf("SDRAM: %u MB at address 0x%08lx\n",
sdram_size >> 20, info->phys_addr);
printf("Testing SDRAM...");
for (i = 0; i < sdram_size / 4; i++)
sdram[i] = i;
for (i = 0; i < sdram_size / 4; i++) {
tmp = sdram[i];
if (tmp != i) {
printf("FAILED at address 0x%08lx\n",
info->phys_addr + i * 4);
printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
return 0;
}
}
puts("OK\n");
if (config->data_bits == SDRAM_DATA_16BIT)
sdram_size = 1 << (config->row_bits + config->col_bits
+ config->bank_bits + 1);
else
sdram_size = 1 << (config->row_bits + config->col_bits
+ config->bank_bits + 2);
return sdram_size;
}

16
cpu/at32ap/interrupts.c
View file

@ -98,18 +98,16 @@ void set_timer(unsigned long t)
*/
void udelay(unsigned long usec)
{
unsigned long now, end;
unsigned long cycles;
unsigned long base;
unsigned long now;
now = sysreg_read(COUNT);
base = sysreg_read(COUNT);
cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100;
end = ((usec * (get_tbclk() / 10000)) + 50) / 100;
end += now;
while (now > end)
now = sysreg_read(COUNT);
while (now < end)
do {
now = sysreg_read(COUNT);
} while ((now - base) < cycles);
}
static int set_interrupt_handler(unsigned int nr, void (*handler)(void),

129
cpu/at32ap/start.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2005-2006 Atmel Corporation
* Copyright (C) 2005-2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
@ -20,12 +20,9 @@
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/ptrace.h>
#include <asm/sysreg.h>
#ifndef PART_SPECIFIC_BOOTSTRAP
# define PART_SPECIFIC_BOOTSTRAP
#endif
#define SYSREG_MMUCR_I_OFFSET 2
#define SYSREG_MMUCR_S_OFFSET 4
@ -34,11 +31,115 @@
| SYSREG_BIT(FE) | SYSREG_BIT(RE) \
| SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
.text
/*
* To save some space, we use the same entry point for
* exceptions and reset. This avoids lots of alignment padding
* since the reset vector is always suitably aligned.
*/
.section .exception.text, "ax", @progbits
.global _start
.global _evba
.type _start, @function
.type _evba, @function
_start:
PART_SPECIFIC_BOOTSTRAP
.size _start, 0
_evba:
.org 0x00
rjmp unknown_exception /* Unrecoverable exception */
.org 0x04
rjmp unknown_exception /* TLB multiple hit */
.org 0x08
rjmp unknown_exception /* Bus error data fetch */
.org 0x0c
rjmp unknown_exception /* Bus error instruction fetch */
.org 0x10
rjmp unknown_exception /* NMI */
.org 0x14
rjmp unknown_exception /* Instruction address */
.org 0x18
rjmp unknown_exception /* ITLB protection */
.org 0x1c
rjmp unknown_exception /* Breakpoint */
.org 0x20
rjmp unknown_exception /* Illegal opcode */
.org 0x24
rjmp unknown_exception /* Unimplemented instruction */
.org 0x28
rjmp unknown_exception /* Privilege violation */
.org 0x2c
rjmp unknown_exception /* Floating-point */
.org 0x30
rjmp unknown_exception /* Coprocessor absent */
.org 0x34
rjmp unknown_exception /* Data Address (read) */
.org 0x38
rjmp unknown_exception /* Data Address (write) */
.org 0x3c
rjmp unknown_exception /* DTLB Protection (read) */
.org 0x40
rjmp unknown_exception /* DTLB Protection (write) */
.org 0x44
rjmp unknown_exception /* DTLB Modified */
.org 0x50
rjmp unknown_exception /* ITLB Miss */
.org 0x60
rjmp unknown_exception /* DTLB Miss (read) */
.org 0x70
rjmp unknown_exception /* DTLB Miss (write) */
.size _evba, . - _evba
.align 2
.type unknown_exception, @function
unknown_exception:
/* Figure out whether we're handling an exception (Exception
* mode) or just booting (Supervisor mode). */
csrfcz SYSREG_M1_OFFSET
brcc at32ap_cpu_bootstrap
/* This is an exception. Complain. */
pushm r0-r12
sub r8, sp, REG_R12 - REG_R0 - 4
mov r9, lr
mfsr r10, SYSREG_RAR_EX
mfsr r11, SYSREG_RSR_EX
pushm r8-r11
mfsr r12, SYSREG_ECR
mov r11, sp
rcall do_unknown_exception
1: rjmp 1b
/* The COUNT/COMPARE timer interrupt handler */
.global timer_interrupt_handler
.type timer_interrupt_handler,@function
.align 2
timer_interrupt_handler:
/*
* Increment timer_overflow and re-write COMPARE with 0xffffffff.
*
* We're running at interrupt level 3, so we don't need to save
* r8-r12 or lr to the stack.
*/
lda.w r8, timer_overflow
ld.w r9, r8[0]
mov r10, -1
mtsr SYSREG_COMPARE, r10
sub r9, -1
st.w r8[0], r9
rete
/*
* CPU bootstrap after reset is handled here. SoC code may
* override this in case they need to initialize oscillators,
* etc.
*/
.section .text.at32ap_cpu_bootstrap, "ax", @progbits
.global at32ap_cpu_bootstrap
.weak at32ap_cpu_bootstrap
.type at32ap_cpu_bootstrap, @function
.align 2
at32ap_cpu_bootstrap:
/* Reset the Status Register */
mov r0, lo(SR_INIT)
orh r0, hi(SR_INIT)
@ -66,9 +167,16 @@ _start:
lddpc pc, 1f
.align 2
1: .long 2f
1: .long at32ap_low_level_init
.size _start, . - _start
2: lddpc sp, sp_init
/* Common CPU bootstrap code after oscillator/cache/etc. init */
.section .text.avr32ap_low_level_init, "ax", @progbits
.global at32ap_low_level_init
.type at32ap_low_level_init, @function
.align 2
at32ap_low_level_init:
lddpc sp, sp_init
/* Initialize the GOT pointer */
lddpc r6, got_init
@ -90,6 +198,7 @@ got_init:
* Relocate the u-boot image into RAM and continue from there.
* Does not return.
*/
.section .text.relocate_code,"ax",@progbits
.global relocate_code
.type relocate_code,@function
relocate_code:
@ -162,3 +271,5 @@ in_ram:
.align 2
got_init_reloc:
.long 3b - _GLOBAL_OFFSET_TABLE_
.size relocate_code, . - relocate_code

10
cpu/mips/cpu.c
View file

@ -66,10 +66,10 @@ void flush_cache(ulong start_addr, ulong size)
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
write_32bit_cp0_register(CP0_ENTRYLO1, low1);
write_32bit_cp0_register(CP0_ENTRYHI, hi);
write_32bit_cp0_register(CP0_INDEX, index);
write_c0_entrylo0(low0);
write_c0_pagemask(pagemask);
write_c0_entrylo1(low1);
write_c0_entryhi(hi);
write_c0_index(index);
tlb_write_indexed();
}

8
cpu/mpc512x/traps.c
View file

@ -34,7 +34,13 @@ DECLARE_GLOBAL_DATA_PTR;
extern unsigned long search_exception_table(unsigned long);
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
/*
* End of addressable memory. This may be less than the actual
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
extern ulong get_effective_memsize(void);
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
/*
* Trap & Exception support

6
cpu/mpc83xx/start.S
View file

@ -557,7 +557,7 @@ invalidate_bats:
mtspr IBAT1U, r0
mtspr IBAT2U, r0
mtspr IBAT3U, r0
#if (CFG_HID2 & HID2_HBE)
#ifdef CONFIG_HIGH_BATS
mtspr IBAT4U, r0
mtspr IBAT5U, r0
mtspr IBAT6U, r0
@ -568,7 +568,7 @@ invalidate_bats:
mtspr DBAT1U, r0
mtspr DBAT2U, r0
mtspr DBAT3U, r0
#if (CFG_HID2 & HID2_HBE)
#ifdef CONFIG_HIGH_BATS
mtspr DBAT4U, r0
mtspr DBAT5U, r0
mtspr DBAT6U, r0
@ -655,7 +655,7 @@ setup_bats:
mtspr DBAT3U, r3
isync
#if (CFG_HID2 & HID2_HBE)
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
addis r4, r0, CFG_IBAT4L@h
ori r4, r4, CFG_IBAT4L@l

4
cpu/mpc86xx/cpu.c
View file

@ -26,6 +26,7 @@
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <mpc86xx.h>
#include <asm/fsl_law.h>
@ -268,13 +269,14 @@ dma_xfer(void *dest, uint count, void *src)
/*
* Print out the state of various machine registers.
* Currently prints out LAWs and BR0/OR0
* Currently prints out LAWs, BR0/OR0, and BATs
*/
void mpc86xx_reginfo(void)
{
immap_t *immap = (immap_t *)CFG_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
print_bats();
print_laws();
printf ("Local Bus Controller Registers\n"

79
cpu/nios/spi.c
View file

@ -63,10 +63,10 @@ static char quickhex (int i)
return hex_digit[i];
}
static void memdump (void *pv, int num)
static void memdump (const void *pv, int num)
{
int i;
unsigned char *pc = (unsigned char *) pv;
const unsigned char *pc = (const unsigned char *) pv;
for (i = 0; i < num; i++)
printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
@ -83,26 +83,64 @@ static void memdump (void *pv, int num)
#endif /* DEBUG */
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct spi_slave *slave;
if (!spi_cs_is_valid(bus, cs))
return NULL;
slave = malloc(sizeof(struct spi_slave));
if (!slave)
return NULL;
slave->bus = bus;
slave->cs = cs;
/* TODO: Add support for different modes and speeds */
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
free(slave);
}
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
/*
* SPI transfer:
*
* See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf
* for more informations.
*/
int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout,
void *din, unsigned long flags)
{
const u8 *txd = dout;
u8 *rxd = din;
int j;
DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
(int)chipsel, *(uint *)dout, *(uint *)din, bitlen));
DPRINT(("spi_xfer: slave %u:%u dout %08X din %08X bitlen %d\n",
slave->bus, slave->cs, *(uint *)dout, *(uint *)din, bitlen));
memdump((void*)dout, (bitlen + 7) / 8);
memdump(dout, (bitlen + 7) / 8);
if(chipsel != NULL) {
chipsel(1); /* select the target chip */
}
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
if (bitlen > CFG_NIOS_SPIBITS) { /* leave chip select active */
if (!(flags & SPI_XFER_END) || bitlen > CFG_NIOS_SPIBITS) {
/* leave chip select active */
spi->control |= NIOS_SPI_SSO;
}
@ -114,11 +152,11 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
while ((spi->status & NIOS_SPI_TRDY) == 0)
;
spi->txdata = (unsigned)(dout[j]);
spi->txdata = (unsigned)(txd[j]);
while ((spi->status & NIOS_SPI_RRDY) == 0)
;
din[j] = (unsigned char)(spi->rxdata & 0xff);
rxd[j] = (unsigned char)(spi->rxdata & 0xff);
#elif (CFG_NIOS_SPIBITS == 16)
j++, j++) {
@ -126,15 +164,15 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
while ((spi->status & NIOS_SPI_TRDY) == 0)
;
if ((j+1) < ((bitlen + 7) / 8))
spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]);
spi->txdata = (unsigned)((txd[j] << 8) | txd[j+1]);
else
spi->txdata = (unsigned)(dout[j] << 8);
spi->txdata = (unsigned)(txd[j] << 8);
while ((spi->status & NIOS_SPI_RRDY) == 0)
;
din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff);
rxd[j] = (unsigned char)((spi->rxdata >> 8) & 0xff);
if ((j+1) < ((bitlen + 7) / 8))
din[j+1] = (unsigned char)(spi->rxdata & 0xff);
rxd[j+1] = (unsigned char)(spi->rxdata & 0xff);
#else
#error "*** unsupported value of CFG_NIOS_SPIBITS ***"
@ -142,15 +180,14 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
}
if (bitlen > CFG_NIOS_SPIBITS) {
if (bitlen > CFG_NIOS_SPIBITS && (flags & SPI_XFER_END)) {
spi->control &= ~NIOS_SPI_SSO;
}
if(chipsel != NULL) {
chipsel(0); /* deselect the target chip */
}
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
memdump((void*)din, (bitlen + 7) / 8);
memdump(din, (bitlen + 7) / 8);
return 0;
}

26
cpu/ppc4xx/commproc.c
View file

@ -30,29 +30,25 @@
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
#if defined(CFG_POST_ALT_WORD_ADDR)
#if defined(CFG_POST_WORD_ADDR)
# define _POST_ADDR ((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR))
#elif defined(CFG_POST_ALT_WORD_ADDR)
# define _POST_ADDR (CFG_POST_ALT_WORD_ADDR)
#endif
void post_word_store (ulong a)
{
out_be32((void *)CFG_POST_ALT_WORD_ADDR, a);
volatile void *save_addr = (volatile void *)(_POST_ADDR);
out_be32(save_addr, a);
}
ulong post_word_load (void)
{
return in_be32((void *)CFG_POST_ALT_WORD_ADDR);
}
#else /* CFG_POST_ALT_WORD_ADDR */
void post_word_store (ulong a)
{
volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
*(volatile ulong *) save_addr = a;
}
volatile void *save_addr = (volatile void *)(_POST_ADDR);
ulong post_word_load (void)
{
volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
return *(volatile ulong *) save_addr;
return in_be32(save_addr);
}
#endif /* CFG_POST_ALT_WORD_ADDR */
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/

4
disk/part.c
View file

@ -109,7 +109,7 @@ void dev_print (block_dev_desc_t *dev_desc)
lbaint_t lba512;
#endif
switch (dev_desc->type) {
switch (dev_desc->if_type) {
case IF_TYPE_SCSI:
printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n",
dev_desc->target,dev_desc->lun,
@ -124,7 +124,7 @@ void dev_print (block_dev_desc_t *dev_desc)
dev_desc->revision,
dev_desc->product);
break;
case DEV_TYPE_UNKNOWN:
case IF_TYPE_UNKNOWN:
default:
puts ("not available\n");
return;

13
drivers/hwmon/lm75.c
View file

@ -47,6 +47,19 @@ int dtt_read(int sensor, int reg)
int dlen;
uchar data[2];
#ifdef CONFIG_DTT_AD7414
/*
* On AD7414 the first value upon bootup is not read correctly.
* This is most likely because of the 800ms update time of the
* temp register in normal update mode. To get current values
* each time we issue the "dtt" command including upon powerup
* we switch into one-short mode.
*
* Issue one-shot mode command
*/
dtt_write(sensor, DTT_CONFIG, 0x64);
#endif
/*
* Validate 'reg' param
*/

2
drivers/mtd/cfi_flash.c
View file

@ -1720,6 +1720,8 @@ ulong flash_get_size (ulong base, int banknum)
int erase_region_count;
struct cfi_qry qry;
memset(&qry, 0, sizeof(qry));
info->ext_addr = 0;
info->cfi_version = 0;
#ifdef CFG_FLASH_PROTECTION

7
drivers/mtd/nand/nand_util.c
View file

@ -153,6 +153,13 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
priv_nand->bbt = NULL;
}
if (erase_length < meminfo->erasesize) {
printf("Warning: Erase size 0x%08x smaller than one " \
"erase block 0x%08x\n",erase_length, meminfo->erasesize);
printf(" Erasing 0x%08x instead\n", meminfo->erasesize);
erase_length = meminfo->erasesize;
}
for (;
erase.addr < opts->offset + erase_length;
erase.addr += meminfo->erasesize) {

47
drivers/mtd/spi/Makefile Normal file
View file

@ -0,0 +1,47 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libspi_flash.a
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

362
drivers/mtd/spi/atmel.c Normal file
View file

@ -0,0 +1,362 @@
/*
* Atmel SPI DataFlash support
*
* Copyright (C) 2008 Atmel Corporation
*/
#define DEBUG
#include <common.h>
#include <malloc.h>
#include <spi_flash.h>
#include "spi_flash_internal.h"
/* AT45-specific commands */
#define CMD_AT45_READ_STATUS 0xd7
#define CMD_AT45_ERASE_PAGE 0x81
#define CMD_AT45_LOAD_PROG_BUF1 0x82
#define CMD_AT45_LOAD_BUF1 0x84
#define CMD_AT45_LOAD_PROG_BUF2 0x85
#define CMD_AT45_LOAD_BUF2 0x87
#define CMD_AT45_PROG_BUF1 0x88
#define CMD_AT45_PROG_BUF2 0x89
/* AT45 status register bits */
#define AT45_STATUS_P2_PAGE_SIZE (1 << 0)
#define AT45_STATUS_READY (1 << 7)
/* DataFlash family IDs, as obtained from the second idcode byte */
#define DF_FAMILY_AT26F 0
#define DF_FAMILY_AT45 1
#define DF_FAMILY_AT26DF 2 /* AT25DF and AT26DF */
struct atmel_spi_flash_params {
u8 idcode1;
/* Log2 of page size in power-of-two mode */
u8 l2_page_size;
u8 pages_per_block;
u8 blocks_per_sector;
u8 nr_sectors;
const char *name;
};
struct atmel_spi_flash {
const struct atmel_spi_flash_params *params;
struct spi_flash flash;
};
static inline struct atmel_spi_flash *
to_atmel_spi_flash(struct spi_flash *flash)
{
return container_of(flash, struct atmel_spi_flash, flash);
}
static const struct atmel_spi_flash_params atmel_spi_flash_table[] = {
{
.idcode1 = 0x28,
.l2_page_size = 10,
.pages_per_block = 8,
.blocks_per_sector = 32,
.nr_sectors = 32,
.name = "AT45DB642D",
},
};
static int at45_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
struct spi_slave *spi = flash->spi;
unsigned long timebase;
int ret;
u8 cmd = CMD_AT45_READ_STATUS;
u8 status;
timebase = get_timer(0);
ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
if (ret)
return -1;
do {
ret = spi_xfer(spi, 8, NULL, &status, 0);
if (ret)
return -1;
if (status & AT45_STATUS_READY)
break;
} while (get_timer(timebase) < timeout);
/* Deactivate CS */
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
if (status & AT45_STATUS_READY)
return 0;
/* Timed out */
return -1;
}
/*
* Assemble the address part of a command for AT45 devices in
* non-power-of-two page size mode.
*/
static void at45_build_address(struct atmel_spi_flash *asf, u8 *cmd, u32 offset)
{
unsigned long page_addr;
unsigned long byte_addr;
unsigned long page_size;
unsigned int page_shift;
/*
* The "extra" space per page is the power-of-two page size
* divided by 32.
*/
page_shift = asf->params->l2_page_size;
page_size = (1 << page_shift) + (1 << (page_shift - 5));
page_shift++;
page_addr = offset / page_size;
byte_addr = offset % page_size;
cmd[0] = page_addr >> (16 - page_shift);
cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8);
cmd[2] = byte_addr;
}
static int dataflash_read_fast_p2(struct spi_flash *flash,
u32 offset, size_t len, void *buf)
{
u8 cmd[5];
cmd[0] = CMD_READ_ARRAY_FAST;
cmd[1] = offset >> 16;
cmd[2] = offset >> 8;
cmd[3] = offset;
cmd[4] = 0x00;
return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
}
static int dataflash_read_fast_at45(struct spi_flash *flash,
u32 offset, size_t len, void *buf)
{
struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
u8 cmd[5];
cmd[0] = CMD_READ_ARRAY_FAST;
at45_build_address(asf, cmd + 1, offset);
cmd[4] = 0x00;
return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
}
static int dataflash_write_at45(struct spi_flash *flash,
u32 offset, size_t len, const void *buf)
{
struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
unsigned long page_addr;
unsigned long byte_addr;
unsigned long page_size;
unsigned int page_shift;
size_t chunk_len;
size_t actual;
int ret;
u8 cmd[4];
page_shift = asf->params->l2_page_size;
page_size = (1 << page_shift) + (1 << (page_shift - 5));
page_shift++;
page_addr = offset / page_size;
byte_addr = offset % page_size;
ret = spi_claim_bus(flash->spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
}
for (actual = 0; actual < len; actual += chunk_len) {
chunk_len = min(len - actual, page_size - byte_addr);
/* Use the same address bits for both commands */
cmd[0] = CMD_AT45_LOAD_BUF1;
cmd[1] = page_addr >> (16 - page_shift);
cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8);
cmd[3] = byte_addr;
ret = spi_flash_cmd_write(flash->spi, cmd, 4,
buf + actual, chunk_len);
if (ret < 0) {
debug("SF: Loading AT45 buffer failed\n");
goto out;
}
cmd[0] = CMD_AT45_PROG_BUF1;
ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0);
if (ret < 0) {
debug("SF: AT45 page programming failed\n");
goto out;
}
ret = at45_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret < 0) {
debug("SF: AT45 page programming timed out\n");
goto out;
}
page_addr++;
byte_addr = 0;
}
debug("SF: AT45: Successfully programmed %u bytes @ 0x%x\n",
len, offset);
ret = 0;
out:
spi_release_bus(flash->spi);
return ret;
}
int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len)
{
struct atmel_spi_flash *asf = to_atmel_spi_flash(flash);
unsigned long page_addr;
unsigned long page_size;
unsigned int page_shift;
size_t actual;
int ret;
u8 cmd[4];
/*
* TODO: This function currently uses page erase only. We can
* probably speed things up by using block and/or sector erase
* when possible.
*/
page_shift = asf->params->l2_page_size;
page_size = (1 << page_shift) + (1 << (page_shift - 5));
page_shift++;
page_addr = offset / page_size;
if (offset % page_size || len % page_size) {
debug("SF: Erase offset/length not multiple of page size\n");
return -1;
}
cmd[0] = CMD_AT45_ERASE_PAGE;
cmd[3] = 0x00;
ret = spi_claim_bus(flash->spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
}
for (actual = 0; actual < len; actual += page_size) {
cmd[1] = page_addr >> (16 - page_shift);
cmd[2] = page_addr << (page_shift - 8);
ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0);
if (ret < 0) {
debug("SF: AT45 page erase failed\n");
goto out;
}
ret = at45_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
if (ret < 0) {
debug("SF: AT45 page erase timed out\n");
goto out;
}
page_addr++;
}
debug("SF: AT45: Successfully erased %u bytes @ 0x%x\n",
len, offset);
ret = 0;
out:
spi_release_bus(flash->spi);
return ret;
}
struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode)
{
const struct atmel_spi_flash_params *params;
unsigned long page_size;
unsigned int family;
struct atmel_spi_flash *asf;
unsigned int i;
int ret;
u8 status;
for (i = 0; i < ARRAY_SIZE(atmel_spi_flash_table); i++) {
params = &atmel_spi_flash_table[i];
if (params->idcode1 == idcode[1])
break;
}
if (i == ARRAY_SIZE(atmel_spi_flash_table)) {
debug("SF: Unsupported DataFlash ID %02x\n",
idcode[1]);
return NULL;
}
asf = malloc(sizeof(struct atmel_spi_flash));
if (!asf) {
debug("SF: Failed to allocate memory\n");
return NULL;
}
asf->params = params;
asf->flash.spi = spi;
asf->flash.name = params->name;
/* Assuming power-of-two page size initially. */
page_size = 1 << params->l2_page_size;
family = idcode[1] >> 5;
switch (family) {
case DF_FAMILY_AT45:
/*
* AT45 chips have configurable page size. The status
* register indicates which configuration is active.
*/
ret = spi_flash_cmd(spi, CMD_AT45_READ_STATUS, &status, 1);
if (ret)
goto err;
debug("SF: AT45 status register: %02x\n", status);
if (!(status & AT45_STATUS_P2_PAGE_SIZE)) {
asf->flash.read = dataflash_read_fast_at45;
asf->flash.write = dataflash_write_at45;
asf->flash.erase = dataflash_erase_at45;
page_size += 1 << (params->l2_page_size - 5);
} else {
asf->flash.read = dataflash_read_fast_p2;
}
break;
case DF_FAMILY_AT26F:
case DF_FAMILY_AT26DF:
asf->flash.read = dataflash_read_fast_p2;
break;
default:
debug("SF: Unsupported DataFlash family %u\n", family);
goto err;
}
asf->flash.size = page_size * params->pages_per_block
* params->blocks_per_sector
* params->nr_sectors;
debug("SF: Detected %s with page size %u, total %u bytes\n",
params->name, page_size, asf->flash.size);
return &asf->flash;
err:
free(asf);
return NULL;
}

162
drivers/mtd/spi/spi_flash.c Normal file
View file

@ -0,0 +1,162 @@
/*
* SPI flash interface
*
* Copyright (C) 2008 Atmel Corporation
*/
#define DEBUG
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <spi_flash.h>
#include "spi_flash_internal.h"
int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
{
unsigned long flags = SPI_XFER_BEGIN;
int ret;
if (len == 0)
flags |= SPI_XFER_END;
ret = spi_xfer(spi, 8, &cmd, NULL, flags);
if (ret) {
debug("SF: Failed to send command %02x: %d\n", cmd, ret);
return ret;
}
if (len) {
ret = spi_xfer(spi, len * 8, NULL, response, SPI_XFER_END);
if (ret)
debug("SF: Failed to read response (%zu bytes): %d\n",
len, ret);
}
return ret;
}
int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len)
{
unsigned long flags = SPI_XFER_BEGIN;
int ret;
if (data_len == 0)
flags |= SPI_XFER_END;
ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
if (ret) {
debug("SF: Failed to send read command (%zu bytes): %d\n",
cmd_len, ret);
} else if (data_len != 0) {
ret = spi_xfer(spi, data_len * 8, NULL, data, SPI_XFER_END);
if (ret)
debug("SF: Failed to read %zu bytes of data: %d\n",
data_len, ret);
}
return ret;
}
int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
const void *data, size_t data_len)
{
unsigned long flags = SPI_XFER_BEGIN;
int ret;
if (data_len == 0)
flags |= SPI_XFER_END;
ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
if (ret) {
debug("SF: Failed to send read command (%zu bytes): %d\n",
cmd_len, ret);
} else if (data_len != 0) {
ret = spi_xfer(spi, data_len * 8, data, NULL, SPI_XFER_END);
if (ret)
debug("SF: Failed to read %zu bytes of data: %d\n",
data_len, ret);
}
return ret;
}
int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len)
{
struct spi_slave *spi = flash->spi;
int ret;
spi_claim_bus(spi);
ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
spi_release_bus(spi);
return ret;
}
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
struct spi_flash *flash;
int ret;
u8 idcode[3];
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
debug("SF: Failed to set up slave\n");
return NULL;
}
ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Failed to claim SPI bus: %d\n", ret);
goto err_claim_bus;
}
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, &idcode, sizeof(idcode));
if (ret)
goto err_read_id;
debug("SF: Got idcode %02x %02x %02x\n", idcode[0],
idcode[1], idcode[2]);
switch (idcode[0]) {
#ifdef CONFIG_SPI_FLASH_SPANSION
case 0x01:
flash = spi_flash_probe_spansion(spi, idcode);
break;
#endif
#ifdef CONFIG_SPI_FLASH_ATMEL
case 0x1F:
flash = spi_flash_probe_atmel(spi, idcode);
break;
#endif
default:
debug("SF: Unsupported manufacturer %02X\n", idcode[0]);
flash = NULL;
break;
}
if (!flash)
goto err_manufacturer_probe;
spi_release_bus(spi);
return flash;
err_manufacturer_probe:
err_read_id:
spi_release_bus(spi);
err_claim_bus:
spi_free_slave(spi);
return NULL;
}
void spi_flash_free(struct spi_flash *flash)
{
spi_free_slave(flash->spi);
free(flash);
}

45
drivers/mtd/spi/spi_flash_internal.h Normal file
View file

@ -0,0 +1,45 @@
/*
* SPI flash internal definitions
*
* Copyright (C) 2008 Atmel Corporation
*/
/* Common parameters */
#define SPI_FLASH_PROG_TIMEOUT ((10 * CFG_HZ) / 1000)
#define SPI_FLASH_PAGE_ERASE_TIMEOUT ((50 * CFG_HZ) / 1000)
#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CFG_HZ)
/* Common commands */
#define CMD_READ_ID 0x9f
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
#define CMD_READ_ARRAY_LEGACY 0xe8
/* Send a single-byte command to the device and read the response */
int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
/*
* Send a multi-byte command to the device and read the response. Used
* for flash array reads, etc.
*/
int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len);
/*
* Send a multi-byte command to the device followed by (optional)
* data. Used for programming the flash array, etc.
*/
int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
const void *data, size_t data_len);
/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the ->read() operation.
*/
int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len);
/* Manufacturer-specific probe functions */
struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode);

2
drivers/net/dm9000x.c
View file

@ -300,8 +300,10 @@ eth_init(bd_t * bd)
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
/* Set Node address */
#ifndef CONFIG_AT91SAM9261EK
for (i = 0; i < 6; i++)
((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
#endif
if (is_zero_ether_addr(bd->bi_enetaddr) ||
is_multicast_ether_addr(bd->bi_enetaddr)) {

6
drivers/net/macb.c
View file

@ -417,13 +417,15 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263)
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, 0);
#endif
#else
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263)
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(MII));

67
drivers/rtc/ds1306.c
View file

@ -62,13 +62,6 @@
#define RTC_USER_RAM_BASE 0x20
/*
* External table of chip select functions (see the appropriate board
* support for the actual definition of the table).
*/
extern spi_chipsel_type spi_chipsel[];
extern int spi_chipsel_cnt;
static unsigned int bin2bcd (unsigned int n);
static unsigned char bcd2bin (unsigned char c);
@ -305,11 +298,29 @@ void rtc_reset (void)
static unsigned char rtc_read (unsigned char reg);
static void rtc_write (unsigned char reg, unsigned char val);
static struct spi_slave *slave;
/* read clock time from DS1306 and return it in *tmp */
int rtc_get (struct rtc_time *tmp)
{
unsigned char sec, min, hour, mday, wday, mon, year;
/*
* Assuming Vcc = 2.0V (lowest speed)
*
* REVISIT: If we add an rtc_init() function we can do this
* step just once.
*/
if (!slave) {
slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
sec = rtc_read (RTC_SECONDS);
min = rtc_read (RTC_MINUTES);
hour = rtc_read (RTC_HOURS);
@ -318,6 +329,8 @@ int rtc_get (struct rtc_time *tmp)
mon = rtc_read (RTC_MONTH);
year = rtc_read (RTC_YEAR);
spi_release_bus(slave);
debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
@ -360,6 +373,17 @@ int rtc_get (struct rtc_time *tmp)
/* set clock time from *tmp in DS1306 RTC */
void rtc_set (struct rtc_time *tmp)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
@ -371,6 +395,8 @@ void rtc_set (struct rtc_time *tmp)
rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
spi_release_bus(slave);
}
/* ------------------------------------------------------------------------- */
@ -378,6 +404,17 @@ void rtc_set (struct rtc_time *tmp)
/* reset the DS1306 */
void rtc_reset (void)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
/* clear the control register */
rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
@ -391,22 +428,18 @@ void rtc_reset (void)
rtc_write (RTC_HOURS_ALARM1, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
spi_release_bus(slave);
}
/* ------------------------------------------------------------------------- */
static unsigned char rtc_read (unsigned char reg)
{
unsigned char dout[2]; /* SPI Output Data Bytes */
unsigned char din[2]; /* SPI Input Data Bytes */
int ret;
dout[0] = reg;
if (spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din) != 0) {
return 0;
} else {
return din[1];
}
ret = spi_w8r8(slave, reg);
return ret < 0 ? 0 : ret;
}
/* ------------------------------------------------------------------------- */
@ -419,7 +452,7 @@ static void rtc_write (unsigned char reg, unsigned char val)
dout[0] = 0x80 | reg;
dout[1] = val;
spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din);
spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
}
#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */

43
drivers/rtc/mc13783-rtc.c
View file

@ -24,34 +24,50 @@
#include <rtc.h>
#include <spi.h>
static struct spi_slave *slave;
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
u32 reg;
int err, tim, i = 0;
spi_select(1, 0, SPI_MODE_2 | SPI_CS_HIGH);
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(1, 0, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return -1;
}
if (spi_claim_bus(slave))
return -1;
do {
reg = 0x2c000000;
err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day1);
err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day1,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
reg = 0x28000000;
err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&time);
err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&time,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
reg = 0x2c000000;
err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day2);
err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day2,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
} while (day1 != day2 && i++ < 3);
spi_release_bus(slave);
tim = day1 * 86400 + time;
to_tm(tim, rtc);
@ -65,16 +81,31 @@ void rtc_set(struct rtc_time *rtc)
{
u32 time, day, reg;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(1, 0, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return;
}
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400;
time %= 86400;
if (spi_claim_bus(slave))
return;
reg = 0x2c000000 | day | 0x80000000;
spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day);
spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day,
SPI_XFER_BEGIN | SPI_XFER_END);
reg = 0x28000000 | time | 0x80000000;
spi_xfer(0, 32, (uchar *)&reg, (uchar *)&time);
spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&time,
SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
}
void rtc_reset(void)

1
drivers/spi/Makefile
View file

@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libspi.a
COBJS-y += mpc8xxx_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS := $(COBJS-y)

210
drivers/spi/atmel_spi.c Normal file
View file

@ -0,0 +1,210 @@
/*
* Copyright (C) 2007 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spi.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/memory-map.h>
#include "atmel_spi.h"
void spi_init()
{
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct atmel_spi_slave *as;
unsigned int scbr;
u32 csrx;
void *regs;
if (cs > 3 || !spi_cs_is_valid(bus, cs))
return NULL;
switch (bus) {
case 0:
regs = (void *)SPI0_BASE;
break;
#ifdef SPI1_BASE
case 1:
regs = (void *)SPI1_BASE;
break;
#endif
#ifdef SPI2_BASE
case 2:
regs = (void *)SPI2_BASE;
break;
#endif
#ifdef SPI3_BASE
case 3:
regs = (void *)SPI3_BASE;
break;
#endif
default:
return NULL;
}
scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
/* Too low max SCK rate */
return NULL;
if (scbr < 1)
scbr = 1;
csrx = ATMEL_SPI_CSRx_SCBR(scbr);
csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
if (!(mode & SPI_CPHA))
csrx |= ATMEL_SPI_CSRx_NCPHA;
if (mode & SPI_CPOL)
csrx |= ATMEL_SPI_CSRx_CPOL;
as = malloc(sizeof(struct atmel_spi_slave));
if (!as)
return NULL;
as->slave.bus = bus;
as->slave.cs = cs;
as->regs = regs;
as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
| ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
spi_writel(as, CSR(cs), csrx);
return &as->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct atmel_spi_slave *as = to_atmel_spi(slave);
free(as);
}
int spi_claim_bus(struct spi_slave *slave)
{
struct atmel_spi_slave *as = to_atmel_spi(slave);
/* Enable the SPI hardware */
spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
/*
* Select the slave. This should set SCK to the correct
* initial state, etc.
*/
spi_writel(as, MR, as->mr);
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
struct atmel_spi_slave *as = to_atmel_spi(slave);
/* Disable the SPI hardware */
spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct atmel_spi_slave *as = to_atmel_spi(slave);
unsigned int len_tx;
unsigned int len_rx;
unsigned int len;
int ret;
u32 status;
const u8 *txp = dout;
u8 *rxp = din;
u8 value;
ret = 0;
if (bitlen == 0)
/* Finish any previously submitted transfers */
goto out;
/*
* TODO: The controller can do non-multiple-of-8 bit
* transfers, but this driver currently doesn't support it.
*
* It's also not clear how such transfers are supposed to be
* represented as a stream of bytes...this is a limitation of
* the current SPI interface.
*/
if (bitlen % 8) {
/* Errors always terminate an ongoing transfer */
flags |= SPI_XFER_END;
goto out;
}
len = bitlen / 8;
/*
* The controller can do automatic CS control, but it is
* somewhat quirky, and it doesn't really buy us much anyway
* in the context of U-Boot.
*/
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
for (len_tx = 0, len_rx = 0; len_rx < len; ) {
status = spi_readl(as, SR);
if (status & ATMEL_SPI_SR_OVRES)
return -1;
if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
if (txp)
value = *txp++;
else
value = 0;
spi_writel(as, TDR, value);
len_tx++;
}
if (status & ATMEL_SPI_SR_RDRF) {
value = spi_readl(as, RDR);
if (rxp)
*rxp++ = value;
len_rx++;
}
}
out:
if (flags & SPI_XFER_END) {
/*
* Wait until the transfer is completely done before
* we deactivate CS.
*/
do {
status = spi_readl(as, SR);
} while (!(status & ATMEL_SPI_SR_TXEMPTY));
spi_cs_deactivate(slave);
}
return 0;
}

Some files were not shown because too many files have changed in this diff Show more