From ff0005b56a7fd822cf32b3d9ce4e5bace8d63ac2 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 13 Mar 2019 11:03:35 +0800 Subject: [PATCH 1/2] ARM: dts: socfpga: Add missing altr,sysmgr-syscon for EMAC Syscon register is required in dts to select correct PHY interface. Fix error below: Net: Failed to get syscon: -2 Signed-off-by: Ley Foon Tan --- arch/arm/dts/socfpga_stratix10.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ccd3f32301..ee93725d64 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -95,6 +95,7 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; status = "disabled"; }; @@ -106,6 +107,7 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; status = "disabled"; }; @@ -117,6 +119,7 @@ mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth"; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; status = "disabled"; }; From 92a47459bb85ba3e835b11ddbdcdfb571280614f Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Fri, 15 Mar 2019 20:44:32 +0100 Subject: [PATCH 2/2] arm: socfpga: make SPL_TEXT_BASE overridable To boot from fpga on socfpga gen5, we need to set CONFIG_SPL_TEXT_BASE to 0xC0000000 (hps2fpgaslaves base address). Since converting CONFIG_SPL_TEXT_BASE to Kconfig hasn't been successful so far, let's make this value overridable in socfpga_common.h, so that we can have different board configs override this in socfpga_common.h. Signed-off-by: Simon Goldschmidt --- include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 181af9b646..191204b27b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -248,8 +248,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * 0xFFEz_zzzz ...... Malloc area (grows up to top) * 0xFFE3_FFFF ...... End of SRAM (top) */ +#ifndef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#endif #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) /* SPL memory allocation configuration, this is for FAT implementation */