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arm: Remove ts4800 board

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This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Lucile Quirion <lucile.quirion@savoirfairelinux.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-02-20 20:06:13 -05:00
parent 4d24862848
commit 80b386abe3
8 changed files with 0 additions and 472 deletions
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5
arch/arm/mach-imx/mx5/Kconfig
View file

@ -63,10 +63,6 @@ config TARGET_MX53PPD
help
Enable support for the GE Healthcare PPD.
config TARGET_TS4800
bool "Support TS4800"
select MX51
config TARGET_USBARMORY
bool "Support USB armory"
select MX53
@ -83,6 +79,5 @@ source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
source "board/k+p/kp_imx53/Kconfig"
source "board/menlo/m53menlo/Kconfig"
source "board/technologic/ts4800/Kconfig"
endif

15
board/technologic/ts4800/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_TS4800
config SYS_BOARD
default "ts4800"
config SYS_VENDOR
default "technologic"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "ts4800"
endif

6
board/technologic/ts4800/MAINTAINERS
View file

@ -1,6 +0,0 @@
TS4800 BOARD
M: Lucile Quirion <lucile.quirion@savoirfairelinux.com>
S: Maintained
F: board/ts/ts4800/
F: include/configs/ts4800.h
F: configs/ts4800_defconfig

5
board/technologic/ts4800/Makefile
View file

@ -1,5 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2015 Savoir-faire Linux
obj-y += ts4800.o

263
board/technologic/ts4800/ts4800.c
View file

@ -1,263 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015 Savoir-faire Linux Inc.
*
* Derived from MX51EVK code by
* Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx51.h>
#include <env.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/mx5_video.h>
#include <mmc.h>
#include <input.h>
#include <fsl_esdhc_imx.h>
#include <mc13892.h>
#include <malloc.h>
#include <netdev.h>
#include <phy.h>
#include "ts4800.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
};
#endif
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
u32 get_board_rev(void)
{
u32 rev = get_cpu_rev();
if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
return rev;
}
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
static void setup_iomux_uart(void)
{
static const iomux_v3_cfg_t uart_pads[] = {
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
PAD_CTL_HYS |
PAD_CTL_PUS_22K_UP |
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
MX51_PAD_EIM_EB3__FEC_RDATA1,
NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
MX51_PAD_EIM_CS3__FEC_RDATA3,
MX51_PAD_NANDF_CS2__FEC_TX_ER,
MX51_PAD_EIM_CS5__FEC_CRS,
MX51_PAD_EIM_CS4__FEC_RX_ER,
/* PAD used on TS4800 */
MX51_PAD_DI2_PIN2__FEC_MDC,
MX51_PAD_DISP2_DAT14__FEC_RDAT0,
MX51_PAD_DISP2_DAT10__FEC_COL,
MX51_PAD_DISP2_DAT11__FEC_RXCLK,
MX51_PAD_DISP2_DAT15__FEC_TDAT0,
MX51_PAD_DISP2_DAT6__FEC_TDAT1,
MX51_PAD_DISP2_DAT7__FEC_TDAT2,
MX51_PAD_DISP2_DAT8__FEC_TDAT3,
MX51_PAD_DISP2_DAT9__FEC_TX_EN,
MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
MX51_PAD_DISP2_DAT12__FEC_RX_DV,
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 0));
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 6));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
else
ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
return ret;
}
int board_mmc_init(struct bd_info *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
};
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
/*
* Read the MAC address from FEC's registers PALR PAUR.
* User is supposed to configure these registers when MAC address is known
* from another source (fuse), but on TS4800, MAC address is not fused and
* the bootrom configure these registers on startup.
*/
static int fec_get_mac_from_register(uint32_t base_addr)
{
unsigned char ethaddr[6];
u32 reg_mac[2];
int i;
reg_mac[0] = in_be32(base_addr + 0xE4);
reg_mac[1] = in_be32(base_addr + 0xE8);
for(i = 0; i < 6; i++)
ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
if (is_valid_ethaddr(ethaddr)) {
eth_env_set_enetaddr("ethaddr", ethaddr);
return 0;
}
return -1;
}
#define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14)
int board_eth_init(struct bd_info *bd)
{
int dev_id = -1;
int phy_id = 0xFF;
uint32_t addr = IMX_FEC_BASE;
uint32_t base_mii;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
/* reset FEC phy */
imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
mdelay(1);
gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
mdelay(1);
base_mii = addr;
debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
bus = fec_get_miibus(base_mii, dev_id);
if (!bus)
return -ENOMEM;
phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
if (!phydev) {
free(bus);
return -ENOMEM;
}
if (fec_get_mac_from_register(addr))
printf("eth_init: failed to get MAC address\n");
ret = fec_probe(bd, dev_id, addr, bus, phydev);
if (ret) {
free(phydev);
free(bus);
}
return ret;
}
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int checkboard(void)
{
puts("Board: TS4800\n");
return 0;
}
void hw_watchdog_reset(void)
{
struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
/* feed the watchdog for another 10s */
writew(0x2, &wtd->feed);
}
void hw_watchdog_init(void)
{
return;
}

15
board/technologic/ts4800/ts4800.h
View file

@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015 Savoir-faire Linux Inc.
*/
#ifndef _TS4800_H
#define _TS4800_H
#define TS4800_SYSCON_BASE 0xb0010000
struct ts4800_wtd_regs {
u16 feed;
};
#endif

30
configs/ts4800_defconfig
View file

@ -1,30 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x90008000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_TS4800=y
# CONFIG_CMD_BMODE is not set
CONFIG_BOOTDELAY=1
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y

133
include/configs/ts4800.h
View file

@ -1,133 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015, Savoir-faire Linux Inc.
*
* Derived from MX51EVK code by
* Guennadi Liakhovetski <lg@denx.de>
* Freescale Semiconductor, Inc.
*
* Configuration settings for the TS4800 Board
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */
#define CONFIG_HW_WATCHDOG
#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
/* text base address used when linking */
#include <asm/arch/imx-regs.h>
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/*
* Hardware drivers
*/
#define CONFIG_MXC_UART_BASE UART1_BASE
/*
* MMC Configs
* */
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
/*
* Eth Configs
*/
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
/***********************************************************
* Command definition
***********************************************************/
/* Environment variables */
#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"fdt_file=imx51-ts4800.dtb\0" \
"fdt_addr=0x90fe0000\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
"mmcargs=setenv bootargs root=${mmcroot}\0" \
"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs addtty; " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo ERR: cannot load FDT; " \
"fi; "
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"fi; " \
"fi; " \
"fi; "
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Low level init */
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
#define CONFIG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* Environment organization
*/
#endif