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ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access

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The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.

The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Thor Thayer 2019-12-06 13:47:32 -06:00 committed by Marek Vasut
parent 62079b2211
commit 8097aee3ab
2 changed files with 6 additions and 6 deletions
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6
drivers/ddr/altera/sdram_agilex.c
View file

@ -143,9 +143,6 @@ int sdram_mmr_init_full(struct udevice *dev)
setbits_le32(plat->hmc + ERRINTEN,
DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
if (!cpu_has_been_warmreset())
sdram_init_ecc_bits(&bd);
} else {
@ -158,6 +155,9 @@ int sdram_mmr_init_full(struct udevice *dev)
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
}
/* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
sdram_size_check(&bd);
priv->info.base = bd.bi_dram[0].start;

6
drivers/ddr/altera/sdram_s10.c
View file

@ -307,9 +307,6 @@ int sdram_mmr_init_full(struct udevice *dev)
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
/* Initialize memory content if not from warm reset */
if (!cpu_has_been_warmreset())
sdram_init_ecc_bits(&bd);
@ -323,6 +320,9 @@ int sdram_mmr_init_full(struct udevice *dev)
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
}
/* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
sdram_size_check(&bd);
priv->info.base = bd.bi_dram[0].start;