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https://github.com/AsahiLinux/u-boot
synced 2024-11-26 14:40:41 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
This commit is contained in:
commit
804f1d9938
7 changed files with 18 additions and 36 deletions
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@ -276,19 +276,3 @@
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rx_delay = <0x10>;
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status = "okay";
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};
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&gmac {
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phy-supply = <&vcc_phy>;
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phy-mode = "rgmii";
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clock_in_out = "input";
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snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 50000>;
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assigned-clocks = <&cru SCLK_RMII_SRC>;
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assigned-clock-parents = <&clkin_gmac>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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tx_delay = <0x10>;
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rx_delay = <0x10>;
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status = "okay";
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};
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@ -211,8 +211,8 @@
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snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 50000>;
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tx_delay = <0x28>;
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rx_delay = <0x11>;
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tx_delay = <0x33>;
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rx_delay = <0x45>;
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status = "okay";
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};
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@ -162,20 +162,17 @@ enum {
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/* CRU_CLKSEL11_CON */
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EMMC_PLL_SHIFT = 12,
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EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
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EMMC_SEL_APLL = 0,
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EMMC_SEL_DPLL,
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EMMC_SEL_CPLL = 0,
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EMMC_SEL_GPLL,
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EMMC_SEL_24M,
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SDIO_PLL_SHIFT = 10,
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SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
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SDIO_SEL_APLL = 0,
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SDIO_SEL_DPLL,
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SDIO_SEL_CPLL = 0,
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SDIO_SEL_GPLL,
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SDIO_SEL_24M,
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MMC0_PLL_SHIFT = 8,
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MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
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MMC0_SEL_APLL = 0,
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MMC0_SEL_DPLL,
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MMC0_SEL_CPLL = 0,
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MMC0_SEL_GPLL,
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MMC0_SEL_24M,
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MMC0_DIV_SHIFT = 0,
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@ -72,11 +72,13 @@ int board_init(void)
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int dram_init_banksize(void)
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{
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/* Reserve 0x200000 for OPTEE */
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gd->bd->bi_dram[0].start = 0x60000000;
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = 0x8400000;
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gd->bd->bi_dram[1].start = 0x6a400000;
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gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].start;
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/* Reserve 0x200000 for OPTEE */
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gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
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+ gd->bd->bi_dram[0].size + 0x200000;
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gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
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+ gd->ram_size - gd->bd->bi_dram[1].start;
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return 0;
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}
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@ -7,7 +7,6 @@
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/gpio.h>
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@ -12,9 +12,9 @@ ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
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obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
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obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o
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obj-$(CONFIG_$(SPL_TPL_)SPL_NOR_SUPPORT) += spl_nor.o
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obj-$(CONFIG_$(SPL_TPL_)SPL_XIP_SUPPORT) += spl_xip.o
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obj-$(CONFIG_$(SPL_TPL_)SPL_YMODEM_SUPPORT) += spl_ymodem.o
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obj-$(CONFIG_$(SPL_TPL_)NOR_SUPPORT) += spl_nor.o
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obj-$(CONFIG_$(SPL_TPL_)XIP_SUPPORT) += spl_xip.o
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obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += spl_ymodem.o
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ifndef CONFIG_SPL_UBI
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obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += spl_nand.o
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obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o
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@ -168,7 +168,7 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B6_MASK | GPIO1B7_MASK,
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GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
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GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT);
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GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
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rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
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GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
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GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
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@ -279,12 +279,12 @@ static int rk322x_pinctrl_probe(struct udevice *dev)
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}
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static const struct udevice_id rk322x_pinctrl_ids[] = {
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{ .compatible = "rockchip,rk322x-pinctrl" },
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{ .compatible = "rockchip,rk3228-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk322x) = {
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.name = "pinctrl_rk322x",
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U_BOOT_DRIVER(pinctrl_rk3228) = {
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.name = "pinctrl_rk3228",
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.id = UCLASS_PINCTRL,
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.of_match = rk322x_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
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