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m68k: rename CONFIG_MCFTMR to CFG_MCFTMR

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This is not a Kconfig option so changing to _CFG.

Signed-off-by: Angelo Durgehello <angelo@kernel-space.org>
This commit is contained in:
Angelo Dureghello 2023-02-25 23:25:26 +01:00
parent 12f5489297
commit 7ff7b46e6c
41 changed files with 55 additions and 44 deletions
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2
arch/m68k/cpu/mcf523x/interrupts.c
View file

@ -22,7 +22,7 @@ int interrupt_init(void)
return 0; return 0;
} }
#if defined(CONFIG_MCFTMR) #if defined(CFG_MCFTMR)
void dtimer_intr_setup(void) void dtimer_intr_setup(void)
{ {
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

12
arch/m68k/cpu/mcf52x2/interrupts.c
View file

@ -34,7 +34,7 @@ int interrupt_init(void)
return 0; return 0;
} }
#if defined(CONFIG_MCFTMR) #if defined(CFG_MCFTMR)
void dtimer_intr_setup(void) void dtimer_intr_setup(void)
{ {
intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE); intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
@ -42,7 +42,7 @@ void dtimer_intr_setup(void)
clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI); setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
} }
#endif /* CONFIG_MCFTMR */ #endif /* CFG_MCFTMR */
#endif /* CONFIG_M5272 */ #endif /* CONFIG_M5272 */
#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \ #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
@ -63,7 +63,7 @@ int interrupt_init(void)
return 0; return 0;
} }
#if defined(CONFIG_MCFTMR) #if defined(CFG_MCFTMR)
void dtimer_intr_setup(void) void dtimer_intr_setup(void)
{ {
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
@ -72,7 +72,7 @@ void dtimer_intr_setup(void)
clrbits_be32(&intp->imrl0, 0x00000001); clrbits_be32(&intp->imrl0, 0x00000001);
clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK); clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
} }
#endif /* CONFIG_MCFTMR */ #endif /* CFG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@ -83,11 +83,11 @@ int interrupt_init(void)
return 0; return 0;
} }
#if defined(CONFIG_MCFTMR) #if defined(CFG_MCFTMR)
void dtimer_intr_setup(void) void dtimer_intr_setup(void)
{ {
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI); mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
} }
#endif /* CONFIG_MCFTMR */ #endif /* CFG_MCFTMR */
#endif /* CONFIG_M5249 || CONFIG_M5253 */ #endif /* CONFIG_M5249 || CONFIG_M5253 */

2
arch/m68k/cpu/mcf532x/interrupts.c
View file

@ -23,7 +23,7 @@ int interrupt_init(void)
return 0; return 0;
} }
#if defined(CONFIG_MCFTMR) #if defined(CFG_MCFTMR)
void dtimer_intr_setup(void) void dtimer_intr_setup(void)
{ {
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

2
arch/m68k/cpu/mcf5445x/interrupts.c
View file

@ -26,7 +26,7 @@ int interrupt_init(void)
return 0; return 0;
} }
#if defined(CONFIG_MCFTMR) #if defined(CFG_MCFTMR)
void dtimer_intr_setup(void) void dtimer_intr_setup(void)
{ {
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);

24
arch/m68k/include/asm/immap.h
View file

@ -16,7 +16,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@ -38,7 +38,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3) #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@ -63,7 +63,7 @@
#define CFG_SYS_NUM_IRQS (64) #define CFG_SYS_NUM_IRQS (64)
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
@ -86,7 +86,7 @@
#define CFG_SYS_NUM_IRQS (64) #define CFG_SYS_NUM_IRQS (64)
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
@ -105,7 +105,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3) #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@ -130,7 +130,7 @@
#define CFG_SYS_NUM_IRQS (64) #define CFG_SYS_NUM_IRQS (64)
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_TMR0) #define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
#define CFG_SYS_TMR_BASE (MMAP_TMR3) #define CFG_SYS_TMR_BASE (MMAP_TMR3)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr) #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
@ -152,7 +152,7 @@
#define CFG_SYS_NUM_IRQS (192) #define CFG_SYS_NUM_IRQS (192)
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3) #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@ -174,7 +174,7 @@
#define CFG_SYS_NUM_IRQS (128) #define CFG_SYS_NUM_IRQS (128)
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3) #define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@ -196,7 +196,7 @@
#define CFG_SYS_NUM_IRQS (64) #define CFG_SYS_NUM_IRQS (64)
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \ #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
@ -217,7 +217,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@ -239,7 +239,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@ -269,7 +269,7 @@
#define MMAP_DSPI MMAP_DSPI0 #define MMAP_DSPI MMAP_DSPI0
/* Timer */ /* Timer */
#ifdef CONFIG_MCFTMR #ifdef CFG_MCFTMR
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0) #define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)

4
arch/m68k/lib/time.c
View file

@ -25,7 +25,7 @@ static volatile ulong timestamp = 0;
#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) #define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif #endif
#if defined(CONFIG_MCFTMR) #if defined(CFG_MCFTMR)
#ifndef CFG_SYS_UDELAY_BASE #ifndef CFG_SYS_UDELAY_BASE
# error "uDelay base not defined!" # error "uDelay base not defined!"
#endif #endif
@ -111,7 +111,7 @@ ulong get_timer(ulong base)
return (timestamp - base); return (timestamp - base);
} }
#endif /* CONFIG_MCFTMR */ #endif /* CFG_MCFTMR */
/* /*
* This function is derived from PowerPC code (read timebase as long long). * This function is derived from PowerPC code (read timebase as long long).

2
board/freescale/m53017evb/README
View file

@ -87,7 +87,7 @@ CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_MCFTMR -- define to use DMA timer CFG_MCFTMR -- define to use DMA timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged

2
board/freescale/m5373evb/README
View file

@ -86,7 +86,7 @@ CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
MCFFEC_TOUT_LOOP -- set FEC timeout loop MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_MCFTMR -- define to use DMA timer CFG_MCFTMR -- define to use DMA timer
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged

1
configs/M5208EVBE_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x2000 CONFIG_ENV_ADDR=0x2000
CONFIG_TARGET_M5208EVBE=y CONFIG_TARGET_M5208EVBE=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/M5235EVB_Flash32_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000 CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y CONFIG_TARGET_M5235EVB=y
CONFIG_NORFLASH_PS32BIT=y CONFIG_NORFLASH_PS32BIT=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFFC00400 CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/M5235EVB_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000 CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y CONFIG_TARGET_M5235EVB=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/M5249EVB_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
CONFIG_SYS_LOAD_ADDR=0x200000 CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_ENV_ADDR=0xFFE04000 CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5249EVB=y CONFIG_TARGET_M5249EVB=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_SYS_MONITOR_BASE=0xFFE00400
# CONFIG_AUTOBOOT is not set # CONFIG_AUTOBOOT is not set

1
configs/M5253DEMO_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_ENV_ADDR=0xFF804000 CONFIG_ENV_ADDR=0xFF804000
CONFIG_TARGET_M5253DEMO=y CONFIG_TARGET_M5253DEMO=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFF800400 CONFIG_SYS_MONITOR_BASE=0xFF800400
CONFIG_BOOTDELAY=5 CONFIG_BOOTDELAY=5

1
configs/M5272C3_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000 CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5272C3=y CONFIG_TARGET_M5272C3=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5 CONFIG_BOOTDELAY=5

1
configs/M5275EVB_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0xFFE04000 CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5275EVB=y CONFIG_TARGET_M5275EVB=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5 CONFIG_BOOTDELAY=5

1
configs/M5282EVB_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000 CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5282EVB=y CONFIG_TARGET_M5282EVB=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5 CONFIG_BOOTDELAY=5

1
configs/M53017EVB_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x40000 CONFIG_ENV_ADDR=0x40000
CONFIG_TARGET_M53017EVB=y CONFIG_TARGET_M53017EVB=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/M5329AFEE_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000 CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y CONFIG_TARGET_M5329EVB=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/M5329BFEE_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000 CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y CONFIG_TARGET_M5329EVB=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/M5373EVB_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_ENV_ADDR=0x4000 CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5373EVB=y CONFIG_TARGET_M5373EVB=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/amcore_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_SYS_PROMPT="amcore $ "
CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFC1F000 CONFIG_ENV_ADDR=0xFFC1F000
CONFIG_TARGET_AMCORE=y CONFIG_TARGET_AMCORE=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=126976 CONFIG_SYS_MONITOR_LEN=126976
CONFIG_SYS_MONITOR_BASE=0xFFC00400 CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/astro_mcf5373l_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="URMEL > "
CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0x1FF8000 CONFIG_ENV_ADDR=0x1FF8000
CONFIG_TARGET_ASTRO_MCF5373L=y CONFIG_TARGET_ASTRO_MCF5373L=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1 CONFIG_BOOTDELAY=1

1
configs/cobra5272_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="COBRA > "
CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFFE04000 CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_COBRA5272=y CONFIG_TARGET_COBRA5272=y
CONFIG_MCFTMR=y
CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5 CONFIG_BOOTDELAY=5

1
configs/eb_cpu5282_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_SYS_PROMPT="\nEB+CPU5282> "
CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFF040000 CONFIG_ENV_ADDR=0xFF040000
CONFIG_TARGET_EB_CPU5282=y CONFIG_TARGET_EB_CPU5282=y
CONFIG_MCFTMR=y
CONFIG_SYS_BARGSIZE=1024 CONFIG_SYS_BARGSIZE=1024
CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFF000400 CONFIG_SYS_MONITOR_BASE=0xFF000400

1
configs/eb_cpu5282_internal_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_SYS_LOAD_ADDR=0x20000
CONFIG_ENV_ADDR=0xFF040000 CONFIG_ENV_ADDR=0xFF040000
CONFIG_TARGET_EB_CPU5282=y CONFIG_TARGET_EB_CPU5282=y
CONFIG_MCFTMR=y
CONFIG_SYS_BARGSIZE=1024 CONFIG_SYS_BARGSIZE=1024
CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xF0000418 CONFIG_SYS_MONITOR_BASE=0xF0000418

1
configs/stmark2_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="stmark2"
CONFIG_SYS_PROMPT="stmark2 $ " CONFIG_SYS_PROMPT="stmark2 $ "
CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_SYS_LOAD_ADDR=0x40010000
CONFIG_TARGET_STMARK2=y CONFIG_TARGET_STMARK2=y
CONFIG_MCFTMR=y
CONFIG_SYS_BARGSIZE=256 CONFIG_SYS_BARGSIZE=256
CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_LEN=262144
CONFIG_TIMESTAMP=y CONFIG_TIMESTAMP=y

2
include/configs/M5208EVBE.h
View file

@ -111,4 +111,6 @@
#define CFG_SYS_CS0_MASK 0x007F0001 #define CFG_SYS_CS0_MASK 0x007F0001
#define CFG_SYS_CS0_CTRL 0x00001FA0 #define CFG_SYS_CS0_CTRL 0x00001FA0
#define CFG_MCFTMR
#endif /* _M5208EVBE_H */ #endif /* _M5208EVBE_H */

2
include/configs/M5235EVB.h
View file

@ -130,4 +130,6 @@
# define CFG_SYS_CS0_CTRL 0x00001D80 # define CFG_SYS_CS0_CTRL 0x00001D80
#endif #endif
#define CFG_MCFTMR
#endif /* _M5329EVB_H */ #endif /* _M5329EVB_H */

2
include/configs/M5249EVB.h
View file

@ -120,4 +120,6 @@
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ #define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ #define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_MCFTMR
#endif /* M5249 */ #endif /* M5249 */

2
include/configs/M5253DEMO.h
View file

@ -132,4 +132,6 @@
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ #define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ #define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_MCFTMR
#endif /* _M5253DEMO_H */ #endif /* _M5253DEMO_H */

3
include/configs/M5272C3.h
View file

@ -106,4 +106,7 @@
#define CFG_SYS_PBDDR 0x0000 #define CFG_SYS_PBDDR 0x0000
#define CFG_SYS_PBDAT 0x0000 #define CFG_SYS_PBDAT 0x0000
#define CFG_SYS_PDCNT 0x00000000 #define CFG_SYS_PDCNT 0x00000000
#define CFG_MCFTMR
#endif /* _M5272C3_H */ #endif /* _M5272C3_H */

2
include/configs/M5275EVB.h
View file

@ -116,4 +116,6 @@
#define CFG_SYS_CS1_CTRL 0x00001900 #define CFG_SYS_CS1_CTRL 0x00001900
#define CFG_SYS_CS1_MASK 0x00070001 #define CFG_SYS_CS1_MASK 0x00070001
#define CFG_MCFTMR
#endif /* _M5275EVB_H */ #endif /* _M5275EVB_H */

2
include/configs/M5282EVB.h
View file

@ -127,4 +127,6 @@
#define CFG_SYS_DDRUA 0x05 #define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF #define CFG_SYS_PJPAR 0xFF
#define CFG_MCFTMR
#endif /* _CONFIG_M5282EVB_H */ #endif /* _CONFIG_M5282EVB_H */

2
include/configs/M53017EVB.h
View file

@ -132,4 +132,6 @@
#define CFG_SYS_CS1_MASK 0x00070001 #define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x00001FA0 #define CFG_SYS_CS1_CTRL 0x00001FA0
#define CFG_MCFTMR
#endif /* _M53017EVB_H */ #endif /* _M53017EVB_H */

2
include/configs/M5329EVB.h
View file

@ -138,4 +138,6 @@
#define CFG_SYS_CS2_CTRL 0x00001f60 #define CFG_SYS_CS2_CTRL 0x00001f60
#endif #endif
#define CFG_MCFTMR
#endif /* _M5329EVB_H */ #endif /* _M5329EVB_H */

2
include/configs/M5373EVB.h
View file

@ -136,4 +136,6 @@
#define CFG_SYS_CS2_MASK (16 << 20) #define CFG_SYS_CS2_MASK (16 << 20)
#define CFG_SYS_CS2_CTRL 0x00001f60 #define CFG_SYS_CS2_CTRL 0x00001f60
#define CFG_MCFTMR
#endif /* _M5373EVB_H */ #endif /* _M5373EVB_H */

2
include/configs/amcore.h
View file

@ -10,7 +10,7 @@
#define CFG_SYS_UART_PORT 0 #define CFG_SYS_UART_PORT 0
#define CONFIG_MCFTMR #define CFG_MCFTMR
#define CONFIG_MCFUART #define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT 0 #define CONFIG_SYS_UART_PORT 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }

2
include/configs/astro_mcf5373l.h
View file

@ -184,4 +184,6 @@
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ #define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P) CF_CACR_DCM_P)
#define CFG_MCFTMR
#endif /* _CONFIG_ASTRO_MCF5373L_H */ #endif /* _CONFIG_ASTRO_MCF5373L_H */

2
include/configs/cobra5272.h
View file

@ -184,4 +184,6 @@ configuration */
#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */ #define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */ #define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
#define CFG_MCFTMR
#endif /* _CONFIG_COBRA5272_H */ #endif /* _CONFIG_COBRA5272_H */

2
include/configs/eb_cpu5282.h
View file

@ -138,5 +138,7 @@
#define CFG_SYS_DDRUA 0x05 #define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF #define CFG_SYS_PJPAR 0xFF
#define CFG_MCFTMR
#endif /* _CONFIG_M5282EVB_H */ #endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/ /*---------------------------------------------------------------------*/

2
include/configs/stmark2.h
View file

@ -95,4 +95,6 @@
#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \ #define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 12) CFG_SYS_INIT_RAM_SIZE - 12)
#define CFG_MCFTMR
#endif /* __STMARK2_CONFIG_H */ #endif /* __STMARK2_CONFIG_H */