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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

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This commit is contained in:
Tom Rini 2013-04-22 09:11:25 -04:00
commit 7fbf93e6b8
11 changed files with 343 additions and 10 deletions
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12
Makefile
View file

@ -554,6 +554,18 @@ endif
$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@
# PPC4xx needs the SPL at the end of the image, since the reset vector
# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
# and need to introduce a new build target with the full blown U-Boot
# at the start padded up to the start of the SPL image. And then concat
# the SPL image to the end.
$(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_UBOOT_PAD_TO) \
of=$(obj)u-boot-pad.img 2>/dev/null
dd if=$(obj)u-boot.img of=$(obj)u-boot-pad.img \
conv=notrunc 2>/dev/null
cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \

4
arch/powerpc/cpu/ppc4xx/Makefile
View file

@ -68,6 +68,10 @@ COBJS += miiphy.o
COBJS += uic.o
endif
ifdef CONFIG_SPL_BUILD
COBJS-y += spl_boot.o
endif
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
START := $(addprefix $(obj),$(START))

72
arch/powerpc/cpu/ppc4xx/spl_boot.c Normal file
View file

@ -0,0 +1,72 @@
/*
* Copyright (C) 2013 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Return selected boot device. On PPC4xx its only NOR flash right now.
*/
u32 spl_boot_device(void)
{
return BOOT_DEVICE_NOR;
}
/*
* SPL version of board_init_f()
*/
void board_init_f(ulong bootflag)
{
/*
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
initdram(0);
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
/*
* Init global_data pointer. Has to be done before calling
* get_clocks(), as it stores some clock values into gd needed
* later on in the serial driver.
*/
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset((void *)gd, 0, sizeof(gd_t));
/*
* get_clocks() needs to be called so that the serial driver
* works correctly
*/
get_clocks();
/*
* Do rudimental console / serial setup
*/
preloader_console_init();
/*
* Call board_init_r() (SPL framework version) to load and boot
* real U-Boot or OS
*/
board_init_r(NULL, 0);
/* Does not return!!! */
}

37
arch/powerpc/cpu/ppc4xx/start.S
View file

@ -232,7 +232,7 @@
*
* Use r12 to access the GOT
*/
#if !defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
@ -248,7 +248,8 @@
END_GOT
#endif /* CONFIG_NAND_SPL */
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SPL_BUILD)
/*
* NAND U-Boot image is started from offset 0
*/
@ -270,6 +271,18 @@
bl _start_440
#endif
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
/*
* This is the entry of the real U-Boot from a board port
* that supports SPL booting on the PPC4xx. We only need
* to call board_init_f() here. Everything else has already
* been done in the SPL u-boot version.
*/
GET_GOT /* initialize GOT access */
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
#endif
/*
* 440 Startup -- on reset only the top 4k of the effective
* address space is mapped in by an entry in the instruction
@ -539,7 +552,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
#ifndef CONFIG_NAND_SPL
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
@ -612,6 +625,18 @@ _end_of_vectors:
.globl _start
_start:
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
/*
* This is the entry of the real U-Boot from a board port
* that supports SPL booting on the PPC4xx. We only need
* to call board_init_f() here. Everything else has already
* been done in the SPL u-boot version.
*/
GET_GOT /* initialize GOT access */
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
#endif
/*****************************************************************************/
#if defined(CONFIG_440)
@ -796,7 +821,9 @@ _start:
#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
#ifndef CONFIG_SPL_BUILD
GET_GOT
#endif
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
@ -1080,7 +1107,7 @@ _start:
/*----------------------------------------------------------------------- */
#ifndef CONFIG_NAND_SPL
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
@ -1262,6 +1289,7 @@ in32r:
lwbrx r3,r0,r3
blr
#if !defined(CONFIG_SPL_BUILD)
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@ -1626,6 +1654,7 @@ __440_msr_continue:
mtlr r4 /* restore link register */
blr
#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_440)
/*----------------------------------------------------------------------------+

74
arch/powerpc/cpu/ppc4xx/u-boot-spl.lds Normal file
View file

@ -0,0 +1,74 @@
/*
* Copyright 2012-2013 Stefan Roese <sr@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
MEMORY
{
sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
LENGTH = CONFIG_SPL_BSS_MAX_SIZE
flash : ORIGIN = CONFIG_SPL_TEXT_BASE,
LENGTH = CONFIG_SYS_SPL_MAX_LEN
}
OUTPUT_ARCH(powerpc)
ENTRY(_start)
SECTIONS
{
#ifdef CONFIG_440
.bootpg 0xfffff000 :
{
arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
/*
* PPC440 board need a board specific object with the
* TLB definitions. This needs to get included right after
* start.o, since the first shadow TLB only covers 4k
* of address space.
*/
CONFIG_BOARDDIR/init.o (.bootpg)
} > flash
#endif
.resetvec 0xFFFFFFFC :
{
KEEP(*(.resetvec))
} > flash
.text :
{
__start = .;
arch/powerpc/cpu/ppc4xx/start.o (.text)
CONFIG_BOARDDIR/init.o (.text)
*(.text*)
} > flash
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} > sdram
}

2
arch/powerpc/cpu/ppc4xx/u-boot.lds
View file

@ -96,6 +96,7 @@ SECTIONS
. = ALIGN(256);
__init_end = .;
#ifndef CONFIG_SPL
#ifdef CONFIG_440
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
@ -132,6 +133,7 @@ SECTIONS
#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
. |= 0x10;
#endif
#endif /* CONFIG_SPL */
__bss_start = .;
.bss (NOLOAD) :

75
board/lwmon5/lwmon5.c
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2007-2010
* (C) Copyright 2007-2013
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
@ -200,9 +200,11 @@ int misc_init_r(void)
u32 pbcr;
int size_val = 0;
u32 reg;
#ifndef CONFIG_LCD4_LWMON5
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1, sdr0_srst;
#endif
/*
* FLASH stuff...
@ -233,6 +235,7 @@ int misc_init_r(void)
CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
&flash_info[cfi_flash_num_flash_banks - 1]);
#ifndef CONFIG_LCD4_LWMON5
/*
* USB suff...
*/
@ -306,6 +309,7 @@ int misc_init_r(void)
/* 7. Reassert internal PHY reset: */
mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
udelay(1000);
#endif
/*
* Clear resets
@ -313,7 +317,9 @@ int misc_init_r(void)
mtsdr(SDR0_SRST1, 0x00000000);
mtsdr(SDR0_SRST0, 0x00000000);
#ifndef CONFIG_LCD4_LWMON5
printf("USB: Host(int phy) Device(ext phy)\n");
#endif
/*
* Clear PLB4A0_ACR[WRP]
@ -323,10 +329,12 @@ int misc_init_r(void)
reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
mtdcr(PLB4A0_ACR, reg);
#ifndef CONFIG_LCD4_LWMON5
/*
* Init matrix keyboard
*/
misc_init_r_kbd();
#endif
return 0;
}
@ -336,7 +344,7 @@ int checkboard(void)
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
puts("Board: lwmon5");
printf("Board: %s", __stringify(CONFIG_HOSTNAME));
if (i > 0) {
puts(", serial# ");
@ -495,3 +503,66 @@ void board_reset(void)
{
gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
}
#ifdef CONFIG_SPL_OS_BOOT
/*
* lwmon5 specific implementation of spl_start_uboot()
*
* RETURN
* 0 if booting into OS is selected (default)
* 1 if booting into U-Boot is selected
*/
int spl_start_uboot(void)
{
char s[8];
env_init();
getenv_f("boot_os", s, sizeof(s));
if ((s != NULL) && (strcmp(s, "yes") == 0))
return 0;
return 1;
}
/*
* This function is called from the SPL U-Boot version for
* early init stuff, that needs to be done for OS (e.g. Linux)
* booting. Doing it later in the real U-Boot would not work
* in case that the SPL U-Boot boots Linux directly.
*/
void spl_board_init(void)
{
const gdc_regs *regs = board_get_regs();
/*
* Setup PFC registers, mainly for ethernet support
* later on in Linux
*/
board_early_init_f();
/*
* Clear resets
*/
mtsdr(SDR0_SRST1, 0x00000000);
mtsdr(SDR0_SRST0, 0x00000000);
/*
* Reset Lime controller
*/
gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
udelay(500);
gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
udelay(300);
out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
while (regs->index) {
out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
regs->index, regs->value);
regs++;
}
board_backlight_brightness(DEFAULT_BRIGHTNESS);
}
#endif

4
board/lwmon5/sdram.c
View file

@ -6,7 +6,7 @@
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* (C) Copyright 2007-2008
* (C) Copyright 2007-2013
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
@ -160,6 +160,7 @@ static void program_ecc(u32 start_address,
************************************************************************/
phys_size_t initdram (int board_type)
{
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5)
/* CL=4 */
mtsdram(DDR0_02, 0x00000000);
@ -253,6 +254,7 @@ phys_size_t initdram (int board_type)
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
#endif /* CONFIG_SPL_BUILD */
return (CONFIG_SYS_MBYTES_SDRAM << 20);
}

1
boards.cfg
View file

@ -1010,6 +1010,7 @@ JSE powerpc ppc4xx jse
korat powerpc ppc4xx
korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT
lwmon5 powerpc ppc4xx
lcd4_lwmon5 powerpc ppc4xx lwmon5 - - lwmon5:LCD4_LWMON5
pcs440ep powerpc ppc4xx
quad100hd powerpc ppc4xx
sbc405 powerpc ppc4xx

4
config.mk
View file

@ -222,6 +222,10 @@ ifneq ($(CONFIG_SPL_PAD_TO),)
CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO)
endif
ifneq ($(CONFIG_UBOOT_PAD_TO),)
CPPFLAGS += -DCONFIG_UBOOT_PAD_TO=$(CONFIG_UBOOT_PAD_TO)
endif
ifeq ($(CONFIG_SPL_BUILD),y)
CPPFLAGS += -DCONFIG_SPL_BUILD
endif

68
include/configs/lwmon5.h
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2007-2010
* (C) Copyright 2007-2013
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
@ -37,8 +37,12 @@
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#ifndef CONFIG_SYS_TEXT_BASE
#ifdef CONFIG_LCD4_LWMON5
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
#define CONFIG_HOSTNAME lcd4_lwmon5
#else
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_HOSTNAME lwmon5
#endif
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
@ -56,7 +60,7 @@
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
#define CONFIG_SYS_MONITOR_LEN 0x80000
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
@ -75,9 +79,11 @@
#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
#endif
/*
* Initial RAM & stack pointer
@ -87,12 +93,20 @@
* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
* for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
*/
#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#else
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#endif
/* unused GPT0 COMP reg */
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
#define CONFIG_SYS_OCM_SIZE (16 << 10)
@ -166,8 +180,11 @@
#define CONFIG_SYS_MBYTES_SDRAM 256
#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_DDR_ECC /* enable ECC */
#endif
#ifndef CONFIG_LCD4_LWMON5
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
CONFIG_SYS_POST_CPU | \
@ -276,6 +293,7 @@
#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#endif
/*
* I2C
@ -395,6 +413,7 @@
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#ifndef CONFIG_LCD4_LWMON5
/*
* USB/EHCI
*/
@ -410,6 +429,7 @@
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#endif
/*
* BOOTP options
@ -444,9 +464,11 @@
#define CONFIG_CMD_BMP
#endif
#ifndef CONFIG_LCD4_LWMON5
#ifdef CONFIG_440EPX
#define CONFIG_CMD_USB
#endif
#endif
/*
* Miscellaneous configurable options
@ -480,11 +502,15 @@
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
#ifndef CONFIG_LCD4_LWMON5
#ifndef DEBUG
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
#endif
#define CONFIG_WD_PERIOD 40000 /* in usec */
#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
#endif
/*
* For booting Linux, the board info and command line data
@ -644,4 +670,40 @@
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* SPL related defines
*/
#ifdef CONFIG_LCD4_LWMON5
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
#define CONFIG_SPL_SERIAL_SUPPORT
/* Place BSS for SPL near end of SDRAM */
#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
#define CONFIG_SPL_OS_BOOT
/* Place patched DT blob (fdt) at this address */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
/* Settings for real U-Boot to be loaded from NOR flash */
#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_UBOOT_START 0x01002100
#define CONFIG_SYS_OS_BASE 0xf8000000
#define CONFIG_SYS_FDT_BASE 0xf87c0000
#endif
#endif /* __CONFIG_H */