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arm64: versal-net: Add DTSes for mini qspi/ospi configuration

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Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which ospi/qspi can
be that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a99a8d72201a782fc811715942dea97fb5ab583b.1698329087.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-10-26 16:04:52 +02:00
parent 0274447bae
commit 7faa6b9069
8 changed files with 153 additions and 0 deletions
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7
arch/arm/dts/Makefile
View file

@ -493,7 +493,14 @@ dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
versal-net-mini-emmc.dtb \
versal-net-mini-ospi-single.dtb \
versal-net-mini-ospi-stacked.dtb \
versal-net-mini-qspi-single.dtb \
versal-net-mini-qspi-parallel.dtb \
versal-net-mini-qspi-stacked.dtb \
versal-net-mini-qspi-x1-single.dtb \
versal-net-mini-qspi-x1-stacked.dtb \
versal-net-mini-qspi-x2-single.dtb \
versal-net-mini-qspi-x2-stacked.dtb \
xilinx-versal-net-virt.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb

22
arch/arm/dts/versal-net-mini-ospi-stacked.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET OSPI Quad Stacked DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-ospi.dtsi"
/ {
model = "Xilinx Versal NET MINI OSPI STACKED";
};
&ospi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <8>;
};

22
arch/arm/dts/versal-net-mini-qspi-parallel.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI Quad Parallel DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI PARALLEL";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <4>;
};

22
arch/arm/dts/versal-net-mini-qspi-stacked.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI Quad Stacked DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <4>;
};

17
arch/arm/dts/versal-net-mini-qspi-x1-single.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI x1 Single DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI X1 SINGLE";
};
&flash0 {
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};

23
arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts Normal file
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@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI x1 Stacked DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI X1 STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};

17
arch/arm/dts/versal-net-mini-qspi-x2-single.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI x2 Single DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI X2 SINGLE";
};
&flash0 {
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};

23
arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI x2 Stacked DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI X2 STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};