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am33xx/omap: Allow cache enable for all Sitara/OMAP

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Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined.
This speeds up the Beaglebone Black boot considerable.

(Tested only on Beaglebone Black with SD card boot)

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2014-06-02 22:04:48 -06:00 committed by Tom Rini
parent 89742924c8
commit 7e4154a553
5 changed files with 60 additions and 58 deletions
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8
arch/arm/cpu/armv7/am33xx/board.c
View file

@ -255,11 +255,3 @@ void s_init(void)
#endif
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif /* !CONFIG_SYS_DCACHE_OFF */

4
arch/arm/cpu/armv7/omap-common/Makefile
View file

@ -22,6 +22,10 @@ obj-y += pipe3-phy.o
obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
endif
ifeq ($(CONFIG_SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
ifeq ($(CONFIG_OMAP34XX),)
obj-y += boot-common.o
obj-y += lowlevel_init.o

42
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View file

@ -18,13 +18,8 @@
#include <asm/emif.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>
#include <asm/cache.h>
#include <asm/system.h>
#define ARMV7_DCACHE_WRITEBACK 0xe
#define ARMV7_DOMAIN_CLIENT 1
#define ARMV7_DOMAIN_MASK (0x3 << 0)
DECLARE_GLOBAL_DATA_PTR;
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@ -263,40 +258,3 @@ int print_cpuinfo(void)
return 0;
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
int i;
u32 start = bd->bi_dram[bank].start >> 20;
u32 size = bd->bi_dram[bank].size >> 20;
u32 end = start + size;
debug("%s: bank: %d\n", __func__, bank);
for (i = start; i < end; i++)
set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
}
void arm_init_domains(void)
{
u32 reg;
reg = get_dacr();
/*
* Set DOMAIN to client access so that all permissions
* set in pagetables are validated by the mmu.
*/
reg &= ~ARMV7_DOMAIN_MASK;
reg |= ARMV7_DOMAIN_CLIENT;
set_dacr(reg);
}
#endif

56
arch/arm/cpu/armv7/omap-common/omap-cache.c Normal file
View file

@ -0,0 +1,56 @@
/*
*
* Common functions for OMAP4/5 based boards
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/cache.h>
DECLARE_GLOBAL_DATA_PTR;
#define ARMV7_DCACHE_WRITEBACK 0xe
#define ARMV7_DOMAIN_CLIENT 1
#define ARMV7_DOMAIN_MASK (0x3 << 0)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
int i;
u32 start = bd->bi_dram[bank].start >> 20;
u32 size = bd->bi_dram[bank].size >> 20;
u32 end = start + size;
debug("%s: bank: %d\n", __func__, bank);
for (i = start; i < end; i++)
set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
}
void arm_init_domains(void)
{
u32 reg;
reg = get_dacr();
/*
* Set DOMAIN to client access so that all permissions
* set in pagetables are validated by the mmu.
*/
reg &= ~ARMV7_DOMAIN_MASK;
reg |= ARMV7_DOMAIN_CLIENT;
set_dacr(reg);
}

8
arch/arm/cpu/armv7/omap3/board.c
View file

@ -478,11 +478,3 @@ void omap3_outer_cache_disable(void)
omap3_update_aux_cr(0, 0x2);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif /* !CONFIG_SYS_DCACHE_OFF */