mirror of
https://github.com/AsahiLinux/u-boot
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xtensa: add support for the 'xtfpga' evaluation board
The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Chris Zankel
Tom Rini
parent
28b48a0710
commit
7e270ec3af
18 changed files with 884 additions and 0 deletions
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@ -11,8 +11,11 @@ config SYS_CPU
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choice
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prompt "Target select"
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config TARGET_XTFPGA
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bool "Support XTFPGA"
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endchoice
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source "board/cadence/xtfpga/Kconfig"
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endmenu
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@ -2,6 +2,8 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb
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targets += $(dtb-y)
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DTC_FLAGS +=
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15
arch/xtensa/dts/kc705.dts
Normal file
15
arch/xtensa/dts/kc705.dts
Normal file
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@ -0,0 +1,15 @@
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/dts-v1/;
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/include/ "xtfpga.dtsi"
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/include/ "xtfpga-flash-128m.dtsi"
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/ {
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compatible = "cdns,xtensa-kc705";
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chosen {
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bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
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stdout-path = &serial0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x38000000>;
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};
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};
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17
arch/xtensa/dts/kc705_nommu.dts
Normal file
17
arch/xtensa/dts/kc705_nommu.dts
Normal file
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@ -0,0 +1,17 @@
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/dts-v1/;
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/include/ "xtfpga.dtsi"
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/include/ "xtfpga-flash-128m.dtsi"
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/ {
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compatible = "cdns,xtensa-kc705";
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chosen {
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bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x60000000 0x10000000>;
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};
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soc {
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ranges = <0x00000000 0x90000000 0x10000000>;
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};
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};
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15
arch/xtensa/dts/ml605.dts
Normal file
15
arch/xtensa/dts/ml605.dts
Normal file
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@ -0,0 +1,15 @@
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/dts-v1/;
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/include/ "xtfpga.dtsi"
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/include/ "xtfpga-flash-16m.dtsi"
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/ {
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compatible = "cdns,xtensa-ml605";
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chosen {
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bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
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stdout-path = &serial0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x18000000>;
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};
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};
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18
arch/xtensa/dts/ml605_nommu.dts
Normal file
18
arch/xtensa/dts/ml605_nommu.dts
Normal file
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@ -0,0 +1,18 @@
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/dts-v1/;
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/include/ "xtfpga.dtsi"
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/include/ "xtfpga-flash-16m.dtsi"
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/ {
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compatible = "cdns,xtensa-ml605";
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chosen {
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bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
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stdout-path = &serial0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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soc {
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ranges = <0x00000000 0x90000000 0x10000000>;
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};
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};
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28
arch/xtensa/dts/xtfpga-flash-128m.dtsi
Normal file
28
arch/xtensa/dts/xtfpga-flash-128m.dtsi
Normal file
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@ -0,0 +1,28 @@
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/ {
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soc {
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flash: flash@00000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x00000000 0x08000000>;
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bank-width = <2>;
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device-width = <2>;
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partition@0x0 {
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label = "data";
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reg = <0x00000000 0x06000000>;
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};
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partition@0x6000000 {
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label = "boot loader area";
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reg = <0x06000000 0x00800000>;
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};
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partition@0x6800000 {
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label = "kernel image";
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reg = <0x06800000 0x017e0000>;
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};
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partition@0x7fe0000 {
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label = "boot environment";
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reg = <0x07fe0000 0x00020000>;
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};
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};
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};
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};
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28
arch/xtensa/dts/xtfpga-flash-16m.dtsi
Normal file
28
arch/xtensa/dts/xtfpga-flash-16m.dtsi
Normal file
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@ -0,0 +1,28 @@
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/ {
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soc {
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flash: flash@08000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x08000000 0x01000000>;
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bank-width = <2>;
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device-width = <2>;
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partition@0x0 {
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label = "boot loader area";
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reg = <0x00000000 0x00400000>;
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};
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partition@0x400000 {
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label = "kernel image";
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reg = <0x00400000 0x00600000>;
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};
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partition@0xa00000 {
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label = "data";
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reg = <0x00a00000 0x005e0000>;
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};
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partition@0xfe0000 {
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label = "boot environment";
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reg = <0x00fe0000 0x00020000>;
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};
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};
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};
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};
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137
arch/xtensa/dts/xtfpga.dtsi
Normal file
137
arch/xtensa/dts/xtfpga.dtsi
Normal file
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@ -0,0 +1,137 @@
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/ {
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compatible = "cdns,xtensa-xtfpga";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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chosen {
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bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x06000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "cdns,xtensa-cpu";
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reg = <0>;
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/* Filled in by platform_setup from FPGA register
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* clock-frequency = <100000000>;
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*/
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};
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};
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pic: pic {
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compatible = "cdns,xtensa-pic";
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/* one cell: internal irq number,
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* two cells: second cell == 0: internal irq number
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* second cell == 1: external irq number
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*/
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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clocks {
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osc: main-oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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clk54: clk54 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <54000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x00000000 0xf0000000 0x10000000>;
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serial0: serial@0d050020 {
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device_type = "serial";
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compatible = "ns16550a";
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no-loopback-test;
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reg = <0x0d050020 0x20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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native-endian;
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interrupts = <0 1>; /* external irq 0 */
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clocks = <&osc>;
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};
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enet0: ethoc@0d030000 {
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compatible = "opencores,ethoc";
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reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
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native-endian;
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interrupts = <1 1>; /* external irq 1 */
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local-mac-address = [00 50 c2 13 6f 00];
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clocks = <&osc>;
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};
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i2s0: xtfpga-i2s@0d080000 {
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#sound-dai-cells = <0>;
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compatible = "cdns,xtfpga-i2s";
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reg = <0x0d080000 0x40>;
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interrupts = <2 1>; /* external irq 2 */
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clocks = <&cdce706 4>;
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};
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i2c0: i2c-master@0d090000 {
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compatible = "opencores,i2c-ocores";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0d090000 0x20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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native-endian;
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interrupts = <4 1>;
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clocks = <&osc>;
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cdce706: clock-synth@69 {
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compatible = "ti,cdce706";
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#clock-cells = <1>;
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reg = <0x69>;
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clocks = <&clk54>;
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clock-names = "clk_in0";
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};
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};
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spi0: spi-master@0d0a0000 {
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compatible = "cdns,xtfpga-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0d0a0000 0xc>;
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tlv320aic23: sound-codec@0 {
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#sound-dai-cells = <0>;
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compatible = "tlv320aic23";
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reg = <0>;
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spi-max-frequency = <12500000>;
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};
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};
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,cpu {
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sound-dai = <&i2s0>;
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};
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simple-audio-card,codec {
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sound-dai = <&tlv320aic23>;
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simple-audio-card,bitclock-master = <0>;
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simple-audio-card,frame-master = <0>;
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clocks = <&cdce706 4>;
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};
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};
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};
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39
board/cadence/xtfpga/Kconfig
Normal file
39
board/cadence/xtfpga/Kconfig
Normal file
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@ -0,0 +1,39 @@
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if TARGET_XTFPGA
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choice
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prompt "XTFPGA board type select"
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config XTFPGA_LX60
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bool "Support Avnet LX60"
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config XTFPGA_LX110
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bool "Support Avnet LX110"
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config XTFPGA_LX200
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bool "Support Avnet LX200"
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config XTFPGA_ML605
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bool "Support Xilinx ML605"
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config XTFPGA_KC705
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bool "Support Xilinx KC705"
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endchoice
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config SYS_BOARD
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string
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default "xtfpga"
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config SYS_VENDOR
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string
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default "cadence"
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config SYS_CONFIG_NAME
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string
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default "xtfpga"
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config BOARD_SDRAM_SIZE
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hex
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default 0x04000000 if XTFPGA_LX60
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default 0x03000000 if XTFPGA_LX110
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default 0x06000000 if XTFPGA_LX200
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default 0x18000000 if XTFPGA_ML605
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default 0x38000000 if XTFPGA_KC705
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endif
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7
board/cadence/xtfpga/MAINTAINERS
Normal file
7
board/cadence/xtfpga/MAINTAINERS
Normal file
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@ -0,0 +1,7 @@
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XTFPGA BOARD
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M: Max Filippov <jcmvbkbc@gmail.com>
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S: Maintained
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F: board/cadence/xtfpga/
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F: include/configs/xtfpga.h
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F: configs/xtfpga_defconfig
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F: drivers/sysreset/sysreset_xtfpga.c
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7
board/cadence/xtfpga/Makefile
Normal file
7
board/cadence/xtfpga/Makefile
Normal file
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@ -0,0 +1,7 @@
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#
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# (C) Copyright 2007 - 2013, Tensilica Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += ${BOARD}.o
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125
board/cadence/xtfpga/README
Normal file
125
board/cadence/xtfpga/README
Normal file
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@ -0,0 +1,125 @@
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Tensilica 'xtfpga' Evaluation Boards
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====================================
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Tensilica's 'xtfpga' evaluation boards are actually a set of different
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boards that share configurations. The following is a list of supported
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hardware by this board type:
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- XT-AV60 / LX60
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- XT-AV110 / LX110
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- XT-AV200 / LX200
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- ML605
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- KC705
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All boards provide the following common configurations:
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- An Xtensa or Diamond processor core.
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- An on-chip-debug (OCD) JTAG interface.
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- A 16550 compatible UART and serial port.
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- An OpenCores Wishbone 10/100-base-T ethernet interface.
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- A 32 char two line LCD display. (except for the LX200)
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LX60/LX110/LX200:
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- Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110)
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- 128MB / 64MB (LX60) memory
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- 16MB / 4MB (LX60) Linear Flash
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ML605
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- Virtex-6 (XC6VLX240T)
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- 512MB DDR3 memory
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- 16MB Linear BPI Flash
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KC705 (Xilinx)
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- Kintex-7 XC7K325T FPGA
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- 1GB DDR3 memory
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- 128MB Linear BPI Flash
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Setting up the Board
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--------------------
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The serial port defaults to 115200 baud, no parity and 1 stop bit.
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A terminal emulator must be set accordingly to see the U-Boot prompt.
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Board Configurations LX60/LX110/LX200/ML605/KC705
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-------------------------------------------------
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The LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls
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the boot mapping and selects from a range of default ethernet MAC
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addresses.
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Boot Mapping (DIP switch 8):
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DIP switch 8 maps the system ROM address space (in which the
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reset vector resides) to either SRAM (off, 0, down) or Flash
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(on, 1, up). This mapping is implemented in the FPGA bitstream
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and cannot be disabled by software, therefore DIP switch 8 is no
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available for application use. Note DIP switch 7 is reserved by
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Tensilica for future possible hardware use.
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Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG
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tool such as the Xtensa OCD Daemon connected via a suppored probe.
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See the tools documentation for supported probes and how to
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connect them. Be aware that the board has only 128 KB of SRAM,
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therefore U-Boot must fit within this space to debug an image
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intended for the Flash. This issues is discussed in a separate
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section toward the end.
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Mapping to flash allows U-Boot to start on reset, provided it
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has been programmed into the first two 64 KB sectors of the Flash.
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The Flash is always mapped at a device (memory mapped I/O) address
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(the address is board specific and is expressed as CFG_FLASH_BASE).
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The device address is used by U-Boot to program the flash, and may
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be used to specify an application to run or U-Boot image to boot.
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Default MAC Address (DIP switches 1-6):
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When the board is first powered on, or after the environment has
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been reinitialized, the ethernet MAC address receives a default
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value whose least significant 6 bits come from DIP switches 1-6.
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The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F
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according to the DIP switches, where "on"==1 and "off"==0, and
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switch 1 is the least-significant bit.
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After initial startup, the MAC address is stored in the U-Boot
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environment variable 'ethaddr'. The user may change this to any
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other address with the "setenv" comamnd. After the environment
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has been saved to Flash by the "saveenv" command, this will be
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used and the DIP switches no longer consulted. DIP swithes 1-6
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may then be used for application purposes.
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The KC705 board contains 4-way DIP switch, way 1 is the boot mapping
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switch and ways 2-4 control the low three bits of the MAC address.
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Limitation of SDRAM Size for OCD Debugging on the LX60
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------------------------------------------------------
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The XT-AV60 board has only 128 KB of SDRAM that can be mapped
|
||||
to the system ROM address space for debugging a ROM image under
|
||||
OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000)
|
||||
or the first 2 sectors of the flash.
|
||||
|
||||
This can pose a problem if all the sources are compiled with -O0
|
||||
for debugging. The code size is then too large, in which case it
|
||||
would be necessary to temporarily alter the linker script to place
|
||||
the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot
|
||||
directly there and does not unpack. In practice this is not really
|
||||
necessary as long as only a limited set of sources need to be
|
||||
debugged, because the image can still fit into the 128 KB SRAM.
|
||||
|
||||
The recommended procedure for debugging is to first build U-Boot
|
||||
with the default optimization level (-Os), and then touch and
|
||||
rebuild incrementally with -O0 so that only the touched sources
|
||||
are recompiled with -O0. To build with -O0, pass it in the KCFLAGS
|
||||
variable to make.
|
||||
|
||||
Because this problem is easy to fall into and difficult to debug
|
||||
if one doesn't expect it, the linker script provides a link-time
|
||||
check and fatal error message if the image size exceeds 128 KB.
|
||||
|
||||
115
board/cadence/xtfpga/xtfpga.c
Normal file
115
board/cadence/xtfpga/xtfpga.c
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* (C) Copyright 2007 - 2013 Tensilica Inc.
|
||||
* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <dm/platdata.h>
|
||||
#include <dm/platform_data/net_ethoc.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/global_data.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Check board idendity.
|
||||
* (Print information about the board to stdout.)
|
||||
*/
|
||||
|
||||
|
||||
#if defined(CONFIG_XTFPGA_LX60)
|
||||
const char *board = "XT_AV60";
|
||||
const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
|
||||
#elif defined(CONFIG_XTFPGA_LX110)
|
||||
const char *board = "XT_AV110";
|
||||
const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
|
||||
#elif defined(CONFIG_XTFPGA_LX200)
|
||||
const char *board = "XT_AV200";
|
||||
const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
|
||||
#elif defined(CONFIG_XTFPGA_ML605)
|
||||
const char *board = "XT_ML605";
|
||||
const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
|
||||
#elif defined(CONFIG_XTFPGA_KC705)
|
||||
const char *board = "XT_KC705";
|
||||
const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
|
||||
#else
|
||||
const char *board = "<unknown>";
|
||||
const char *description = "";
|
||||
#endif
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Board: %s: %sTensilica bitstream\n", board, description);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
|
||||
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
|
||||
}
|
||||
|
||||
int board_postclk_init(void)
|
||||
{
|
||||
/*
|
||||
* Obtain CPU clock frequency from board and cache in global
|
||||
* data structure (Hz). Return 0 on success (OK to continue),
|
||||
* else non-zero (hang).
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_FPGAREG_FREQ
|
||||
gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
|
||||
#else
|
||||
/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
|
||||
gd->cpu_clk = 50000000UL;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Miscellaneous late initializations.
|
||||
* The environment has been set up, so we can set the Ethernet address.
|
||||
*/
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_NET
|
||||
/*
|
||||
* Initialize ethernet environment variables and board info.
|
||||
* Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
|
||||
*/
|
||||
|
||||
char *s = getenv("ethaddr");
|
||||
if (s == 0) {
|
||||
unsigned int x;
|
||||
char s[] = __stringify(CONFIG_ETHBASE);
|
||||
x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
|
||||
& FPGAREG_MAC_MASK;
|
||||
sprintf(&s[15], "%02x", x);
|
||||
setenv("ethaddr", s);
|
||||
}
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DEVICE(sysreset) = {
|
||||
.name = "xtfpga_sysreset",
|
||||
};
|
||||
|
||||
static struct ethoc_eth_pdata ethoc_pdata = {
|
||||
.eth_pdata = {
|
||||
.iobase = CONFIG_SYS_ETHOC_BASE,
|
||||
},
|
||||
.packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(ethoc) = {
|
||||
.name = "ethoc",
|
||||
.platdata = ðoc_pdata,
|
||||
};
|
||||
22
configs/xtfpga_defconfig
Normal file
22
configs/xtfpga_defconfig
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
CONFIG_XTENSA=y
|
||||
CONFIG_SYS_CPU="dc233c"
|
||||
CONFIG_XTFPGA_KC705=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_PROMPT="U-Boot> "
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press <SPACE> to stop\n"
|
||||
CONFIG_AUTOBOOT_STOP_STR=" "
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_DM_WARN is not set
|
||||
# CONFIG_DM_DEVICE_REMOVE is not set
|
||||
# CONFIG_DM_STDIO is not set
|
||||
# CONFIG_DM_SEQ_ALIAS is not set
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_ETHOC=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -13,3 +13,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
|
|||
obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
|
||||
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
|
||||
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
|
||||
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
|
||||
|
|
|
|||
37
drivers/sysreset/sysreset_xtfpga.c
Normal file
37
drivers/sysreset/sysreset_xtfpga.c
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Cadence Tensilica xtfpga system reset driver.
|
||||
*
|
||||
* (C) Copyright 2016 Cadence Design Systems Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <sysreset.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static int xtfpga_reset_request(struct udevice *dev, enum sysreset_t type)
|
||||
{
|
||||
switch (type) {
|
||||
case SYSRESET_COLD:
|
||||
writel(CONFIG_SYS_FPGAREG_RESET_CODE,
|
||||
CONFIG_SYS_FPGAREG_RESET);
|
||||
break;
|
||||
default:
|
||||
return -EPROTONOSUPPORT;
|
||||
}
|
||||
|
||||
return -EINPROGRESS;
|
||||
}
|
||||
|
||||
static struct sysreset_ops xtfpga_sysreset_ops = {
|
||||
.request = xtfpga_reset_request,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(xtfpga_sysreset) = {
|
||||
.name = "xtfpga_sysreset",
|
||||
.id = UCLASS_SYSRESET,
|
||||
.ops = &xtfpga_sysreset_ops,
|
||||
};
|
||||
268
include/configs/xtfpga.h
Normal file
268
include/configs/xtfpga.h
Normal file
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* Copyright (C) 2007-2013 Tensilica, Inc.
|
||||
* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/core.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/config.h>
|
||||
|
||||
/*
|
||||
* The 'xtfpga' board describes a set of very similar boards with only minimal
|
||||
* differences.
|
||||
*/
|
||||
|
||||
/*=====================*/
|
||||
/* Board and Processor */
|
||||
/*=====================*/
|
||||
|
||||
#define CONFIG_XTFPGA
|
||||
|
||||
/* FPGA CPU freq after init */
|
||||
#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk)
|
||||
|
||||
/*===================*/
|
||||
/* RAM Layout */
|
||||
/*===================*/
|
||||
|
||||
#if XCHAL_HAVE_PTP_MMU
|
||||
#define CONFIG_SYS_MEMORY_BASE \
|
||||
(XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
|
||||
#define CONFIG_SYS_IO_BASE 0xf0000000
|
||||
#else
|
||||
#define CONFIG_SYS_MEMORY_BASE 0x60000000
|
||||
#define CONFIG_SYS_IO_BASE 0x90000000
|
||||
#define CONFIG_MAX_MEM_MAPPED 0x10000000
|
||||
#endif
|
||||
|
||||
/* Onboard RAM sizes:
|
||||
*
|
||||
* LX60 0x04000000 64 MB
|
||||
* LX110 0x03000000 48 MB
|
||||
* LX200 0x06000000 96 MB
|
||||
* ML605 0x18000000 384 MB
|
||||
* KC705 0x38000000 896 MB
|
||||
*
|
||||
* noMMU configurations can only see first 256MB of onboard memory.
|
||||
*/
|
||||
|
||||
#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
|
||||
#else
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
|
||||
|
||||
/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
|
||||
#ifdef CONFIG_XTFPGA_LX60
|
||||
# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */
|
||||
#else
|
||||
# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_STACKSIZE (512 << 10) /* stack 512KB */
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */
|
||||
|
||||
/* Linux boot param area in RAM (used only when booting linux) */
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10)
|
||||
|
||||
/* Memory test is destructive so default must not overlap vectors or U-Boot*/
|
||||
#define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000)
|
||||
#define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000)
|
||||
|
||||
/* Load address for stand-alone applications.
|
||||
* MEMADDR cannot be used here, because the definition needs to be
|
||||
* a plain number as it's used as -Ttext argument for ld in standalone
|
||||
* example makefile.
|
||||
* Handle noMMU vs MMUv2 vs MMUv3 distinction here manually.
|
||||
*/
|
||||
#if XCHAL_HAVE_PTP_MMU
|
||||
#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
|
||||
#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000
|
||||
#else
|
||||
#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MAX_MEM_MAPPED) && \
|
||||
CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
|
||||
#define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED
|
||||
#else
|
||||
#define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMORY_TOP MEMADDR(CONFIG_SYS_MEMORY_SIZE)
|
||||
#define CONFIG_SYS_TEXT_ADDR \
|
||||
(CONFIG_SYS_MEMORY_TOP - CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/* Used by tftpboot; env var 'loadaddr' */
|
||||
#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000)
|
||||
|
||||
/*==============================*/
|
||||
/* U-Boot general configuration */
|
||||
/*==============================*/
|
||||
|
||||
#undef CONFIG_USE_IRQ /* Keep it simple, poll only */
|
||||
#define CONFIG_BOARD_POSTCLK_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
/* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
/* Prt buf */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
/* max number of command args */
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/*=================*/
|
||||
/* U-Boot commands */
|
||||
/*=================*/
|
||||
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_SAVES
|
||||
|
||||
/*==============================*/
|
||||
/* U-Boot autoboot configuration */
|
||||
/*==============================*/
|
||||
|
||||
#define CONFIG_BOOT_RETRY_TIME 60 /* retry after 60 secs */
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#define CONFIG_AUTO_COMPLETE /* Support tab autocompletion */
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_CRC32_VERIFY
|
||||
#define CONFIG_MX_CYCLIC
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
#ifdef DEBUG
|
||||
#define CONFIG_PANIC_HANG 1 /* Require manual reboot */
|
||||
#endif
|
||||
|
||||
|
||||
/*=========================================*/
|
||||
/* FPGA Registers (board info and control) */
|
||||
/*=========================================*/
|
||||
|
||||
/*
|
||||
* These assume FPGA bitstreams from Tensilica release RB and up. Earlier
|
||||
* releases may not provide any/all of these registers or at these offsets.
|
||||
* Some of the FPGA registers are broken down into bitfields described by
|
||||
* SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
|
||||
*/
|
||||
|
||||
/* Date of FPGA bitstream build in binary coded decimal (BCD) */
|
||||
#define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000)
|
||||
#define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */
|
||||
#define FPGAREG_MTH_WIDTH 8
|
||||
#define FPGAREG_MTH_MASK 0xFF000000
|
||||
#define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */
|
||||
#define FPGAREG_DAY_WIDTH 8
|
||||
#define FPGAREG_DAY_MASK 0x00FF0000
|
||||
#define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/
|
||||
#define FPGAREG_YEAR_WIDTH 16
|
||||
#define FPGAREG_YEAR_MASK 0x0000FFFF
|
||||
|
||||
/* FPGA core clock frequency in Hz (also input to UART) */
|
||||
#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
|
||||
|
||||
/*
|
||||
* DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
|
||||
* Bits 0..5 set the lower 6 bits of the default ethernet MAC.
|
||||
* Bit 6 is reserved for future use by Tensilica.
|
||||
* Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
|
||||
* the base of flash * (when on/1) or to the base of RAM (when off/0).
|
||||
*/
|
||||
#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
|
||||
#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
|
||||
#define FPGAREG_MAC_WIDTH 6
|
||||
#define FPGAREG_MAC_MASK 0x3f
|
||||
#define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */
|
||||
#define FPGAREG_BOOT_WIDTH 1
|
||||
#define FPGAREG_BOOT_MASK 0x80
|
||||
#define FPGAREG_BOOT_RAM 0
|
||||
#define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
|
||||
|
||||
/* Force hard reset of board by writing a code to this register */
|
||||
#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
|
||||
#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
|
||||
|
||||
/*====================*/
|
||||
/* Serial Driver Info */
|
||||
/*====================*/
|
||||
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
|
||||
|
||||
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
|
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*======================*/
|
||||
/* Ethernet Driver Info */
|
||||
/*======================*/
|
||||
|
||||
#define CONFIG_ETHBASE 00:50:C2:13:6f:00
|
||||
#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
|
||||
#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
|
||||
|
||||
/*=====================*/
|
||||
/* Flash & Environment */
|
||||
/*=====================*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* use generic CFI driver */
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#ifdef CONFIG_XTFPGA_LX60
|
||||
# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
|
||||
# define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */
|
||||
# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
|
||||
# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
|
||||
# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#elif defined(CONFIG_XTFPGA_KC705)
|
||||
# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
|
||||
# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
|
||||
# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
|
||||
# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
|
||||
# define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000)
|
||||
#else
|
||||
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
|
||||
# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
|
||||
# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
|
||||
# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
|
||||
# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT \
|
||||
(CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
|
||||
CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
|
||||
#define CONFIG_SYS_FLASH_PROTECTION /* hw flash protection */
|
||||
|
||||
/*
|
||||
* Put environment in top block (64kB)
|
||||
* Another option would be to put env. in 2nd param block offs 8KB, size 8KB
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ)
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ
|
||||
|
||||
/* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue