xtensa: add support for the 'xtfpga' evaluation board

The 'xtfpga' board is actually a set of FPGA evaluation boards that
can be configured to run an Xtensa processor.

 - Avnet Xilinx LX60
 - Avnet Xilinx LX110
 - Avnet Xilinx LX200
 - Xilinx ML605
 - Xilinx KC705

These boards share the same components (open-ethernet, ns16550 serial,
lcd display, flash, etc.).

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

arch/xtensa/Kconfig

@@ -11,8 +11,11 @@ config SYS_CPU
 choice
 	prompt "Target select"
 
+config TARGET_XTFPGA
+	bool "Support XTFPGA"
 
 endchoice
 
+source "board/cadence/xtfpga/Kconfig"
 
 endmenu

arch/xtensa/dts/Makefile

@@ -2,6 +2,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS +=

arch/xtensa/dts/kc705.dts

@@ -0,0 +1,15 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-128m.dtsi"
+
+/ {
+	compatible = "cdns,xtensa-kc705";
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
+		stdout-path = &serial0;
+	};
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x38000000>;
+	};
+};

arch/xtensa/dts/kc705_nommu.dts

@@ -0,0 +1,17 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-128m.dtsi"
+
+/ {
+	compatible = "cdns,xtensa-kc705";
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
+	};
+	memory@0 {
+		device_type = "memory";
+		reg = <0x60000000 0x10000000>;
+	};
+	soc {
+		ranges = <0x00000000 0x90000000 0x10000000>;
+	};
+};

arch/xtensa/dts/ml605.dts

@@ -0,0 +1,15 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-16m.dtsi"
+
+/ {
+	compatible = "cdns,xtensa-ml605";
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
+		stdout-path = &serial0;
+	};
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x18000000>;
+	};
+};

arch/xtensa/dts/ml605_nommu.dts

@@ -0,0 +1,18 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-16m.dtsi"
+
+/ {
+	compatible = "cdns,xtensa-ml605";
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
+		stdout-path = &serial0;
+	};
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+	soc {
+		ranges = <0x00000000 0x90000000 0x10000000>;
+	};
+};

arch/xtensa/dts/xtfpga-flash-128m.dtsi

@@ -0,0 +1,28 @@
+/ {
+	soc {
+		flash: flash@00000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x00000000 0x08000000>;
+			bank-width = <2>;
+			device-width = <2>;
+			partition@0x0 {
+				label = "data";
+				reg = <0x00000000 0x06000000>;
+			};
+			partition@0x6000000 {
+				label = "boot loader area";
+				reg = <0x06000000 0x00800000>;
+			};
+			partition@0x6800000 {
+				label = "kernel image";
+				reg = <0x06800000 0x017e0000>;
+			};
+			partition@0x7fe0000 {
+				label = "boot environment";
+				reg = <0x07fe0000 0x00020000>;
+			};
+		};
+        };
+};

arch/xtensa/dts/xtfpga-flash-16m.dtsi

@@ -0,0 +1,28 @@
+/ {
+	soc {
+		flash: flash@08000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x08000000 0x01000000>;
+			bank-width = <2>;
+			device-width = <2>;
+			partition@0x0 {
+				label = "boot loader area";
+				reg = <0x00000000 0x00400000>;
+			};
+			partition@0x400000 {
+				label = "kernel image";
+				reg = <0x00400000 0x00600000>;
+			};
+			partition@0xa00000 {
+				label = "data";
+				reg = <0x00a00000 0x005e0000>;
+			};
+			partition@0xfe0000 {
+				label = "boot environment";
+				reg = <0x00fe0000 0x00020000>;
+			};
+		};
+	};
+};

arch/xtensa/dts/xtfpga.dtsi

@@ -0,0 +1,137 @@
+/ {
+	compatible = "cdns,xtensa-xtfpga";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&pic>;
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x06000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "cdns,xtensa-cpu";
+			reg = <0>;
+			/* Filled in by platform_setup from FPGA register
+			 * clock-frequency = <100000000>;
+			 */
+		};
+	};
+
+	pic: pic {
+		compatible = "cdns,xtensa-pic";
+		/* one cell: internal irq number,
+		 * two cells: second cell == 0: internal irq number
+		 *            second cell == 1: external irq number
+		 */
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	clocks {
+		osc: main-oscillator {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+		};
+
+		clk54: clk54 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <54000000>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x00000000 0xf0000000 0x10000000>;
+
+		serial0: serial@0d050020 {
+			device_type = "serial";
+			compatible = "ns16550a";
+			no-loopback-test;
+			reg = <0x0d050020 0x20>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			native-endian;
+			interrupts = <0 1>; /* external irq 0 */
+			clocks = <&osc>;
+		};
+
+		enet0: ethoc@0d030000 {
+			compatible = "opencores,ethoc";
+			reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
+			native-endian;
+			interrupts = <1 1>; /* external irq 1 */
+			local-mac-address = [00 50 c2 13 6f 00];
+			clocks = <&osc>;
+		};
+
+		i2s0: xtfpga-i2s@0d080000 {
+			#sound-dai-cells = <0>;
+			compatible = "cdns,xtfpga-i2s";
+			reg = <0x0d080000 0x40>;
+			interrupts = <2 1>; /* external irq 2 */
+			clocks = <&cdce706 4>;
+		};
+
+		i2c0: i2c-master@0d090000 {
+			compatible = "opencores,i2c-ocores";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0d090000 0x20>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			native-endian;
+			interrupts = <4 1>;
+			clocks = <&osc>;
+
+			cdce706: clock-synth@69 {
+				compatible = "ti,cdce706";
+				#clock-cells = <1>;
+				reg = <0x69>;
+				clocks = <&clk54>;
+				clock-names = "clk_in0";
+			};
+		};
+
+		spi0: spi-master@0d0a0000 {
+			compatible = "cdns,xtfpga-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0d0a0000 0xc>;
+
+			tlv320aic23: sound-codec@0 {
+				#sound-dai-cells = <0>;
+				compatible = "tlv320aic23";
+				reg = <0>;
+				spi-max-frequency = <12500000>;
+			};
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&tlv320aic23>;
+			simple-audio-card,bitclock-master = <0>;
+			simple-audio-card,frame-master = <0>;
+			clocks = <&cdce706 4>;
+		};
+	};
+};

board/cadence/xtfpga/Kconfig

@@ -0,0 +1,39 @@
+if TARGET_XTFPGA
+
+choice
+	prompt "XTFPGA board type select"
+
+config XTFPGA_LX60
+	bool "Support Avnet LX60"
+config XTFPGA_LX110
+	bool "Support Avnet LX110"
+config XTFPGA_LX200
+	bool "Support Avnet LX200"
+config XTFPGA_ML605
+	bool "Support Xilinx ML605"
+config XTFPGA_KC705
+	bool "Support Xilinx KC705"
+
+endchoice
+
+config SYS_BOARD
+	string
+	default "xtfpga"
+
+config SYS_VENDOR
+	string
+	default "cadence"
+
+config SYS_CONFIG_NAME
+	string
+	default "xtfpga"
+
+config BOARD_SDRAM_SIZE
+	hex
+	default 0x04000000 if XTFPGA_LX60
+	default 0x03000000 if XTFPGA_LX110
+	default 0x06000000 if XTFPGA_LX200
+	default 0x18000000 if XTFPGA_ML605
+	default 0x38000000 if XTFPGA_KC705
+
+endif

board/cadence/xtfpga/MAINTAINERS

@@ -0,0 +1,7 @@
+XTFPGA BOARD
+M:	Max Filippov <jcmvbkbc@gmail.com>
+S:	Maintained
+F:	board/cadence/xtfpga/
+F:	include/configs/xtfpga.h
+F:	configs/xtfpga_defconfig
+F:	drivers/sysreset/sysreset_xtfpga.c

board/cadence/xtfpga/Makefile

@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2007 - 2013, Tensilica Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y				+= ${BOARD}.o

board/cadence/xtfpga/README

@@ -0,0 +1,125 @@
+		Tensilica 'xtfpga' Evaluation Boards
+		====================================
+
+Tensilica's 'xtfpga' evaluation boards are actually a set of different
+boards that share configurations. The following is a list of supported
+hardware by this board type:
+
+- XT-AV60  / LX60
+- XT-AV110 / LX110
+- XT-AV200 / LX200
+- ML605
+- KC705
+
+All boards provide the following common configurations:
+
+- An Xtensa or Diamond processor core.
+- An on-chip-debug (OCD) JTAG interface.
+- A 16550 compatible UART and serial port.
+- An OpenCores Wishbone 10/100-base-T ethernet interface.
+- A 32 char two line LCD display. (except for the LX200)
+
+LX60/LX110/LX200:
+
+- Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110)
+- 128MB / 64MB (LX60) memory
+- 16MB / 4MB (LX60) Linear Flash
+
+ML605
+
+- Virtex-6 (XC6VLX240T)
+- 512MB DDR3 memory
+- 16MB Linear BPI Flash
+
+KC705 (Xilinx)
+
+- Kintex-7 XC7K325T FPGA
+- 1GB DDR3 memory
+- 128MB Linear BPI Flash
+
+
+Setting up the Board
+--------------------
+
+The serial port defaults to 115200 baud, no parity and 1 stop bit.
+A terminal emulator must be set accordingly to see the U-Boot prompt.
+
+
+Board Configurations LX60/LX110/LX200/ML605/KC705
+-------------------------------------------------
+
+The LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls
+the boot mapping and selects from a range of default ethernet MAC
+addresses.
+
+Boot Mapping (DIP switch 8):
+
+    DIP switch 8 maps the system ROM address space (in which the
+    reset vector resides) to either SRAM (off, 0, down) or Flash
+    (on, 1, up).  This mapping is implemented in the FPGA bitstream
+    and cannot be disabled by software, therefore DIP switch 8 is no
+    available for application use. Note DIP switch 7 is reserved by
+    Tensilica for future possible hardware use.
+
+    Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG
+    tool such as the Xtensa OCD Daemon connected via a suppored probe.
+    See the tools documentation for supported probes and how to
+    connect them.  Be aware that the board has only 128 KB of SRAM,
+    therefore U-Boot must fit within this space to debug an image
+    intended for the Flash.  This issues is discussed in a separate
+    section toward the end.
+
+    Mapping to flash allows U-Boot to start on reset, provided it
+    has been programmed into the first two 64 KB sectors of the Flash.
+
+    The Flash is always mapped at a device (memory mapped I/O) address
+    (the address is board specific and is expressed as CFG_FLASH_BASE).
+    The device address is used by U-Boot to program the flash, and may
+    be used to specify an application to run or U-Boot image to boot.
+
+Default MAC Address (DIP switches 1-6):
+
+    When the board is first powered on, or after the environment has
+    been reinitialized, the ethernet MAC address receives a default
+    value whose least significant 6 bits come from DIP switches 1-6.
+    The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F
+    according to the DIP switches, where "on"==1 and "off"==0, and
+    switch 1 is the least-significant bit.
+
+    After initial startup, the MAC address is stored in the U-Boot
+    environment variable 'ethaddr'. The user may change this to any
+    other address with the "setenv" comamnd. After the environment
+    has been saved to Flash by the "saveenv" command, this will be
+    used and the DIP switches no longer consulted. DIP swithes 1-6
+    may then be used for application purposes.
+
+The KC705 board contains 4-way DIP switch, way 1 is the boot mapping
+switch and ways 2-4 control the low three bits of the MAC address.
+
+
+Limitation of SDRAM Size for OCD Debugging on the LX60
+------------------------------------------------------
+
+The XT-AV60 board has only 128 KB of SDRAM that can be mapped
+to the system ROM address space for debugging a ROM image under
+OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000)
+or the first 2 sectors of the flash.
+
+This can pose a problem if all the sources are compiled with -O0
+for debugging. The code size is then too large, in which case it
+would be necessary to temporarily alter the linker script to place
+the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot
+directly there and does not unpack. In practice this is not really
+necessary as long as only a limited set of sources need to be
+debugged, because the image can still fit into the 128 KB SRAM.
+
+The recommended procedure for debugging is to first build U-Boot
+with the default optimization level (-Os), and then touch and
+rebuild incrementally with -O0 so that only the touched sources
+are recompiled with -O0. To build with -O0, pass it in the KCFLAGS
+variable to make.
+
+Because this problem is easy to fall into and difficult to debug
+if one doesn't expect it, the linker script provides a link-time
+check and fatal error message if the image size exceeds 128 KB.
+

board/cadence/xtfpga/xtfpga.c

@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2007 - 2013 Tensilica Inc.
+ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/net_ethoc.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/stringify.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Check board idendity.
+ * (Print information about the board to stdout.)
+ */
+
+
+#if defined(CONFIG_XTFPGA_LX60)
+const char *board = "XT_AV60";
+const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
+#elif defined(CONFIG_XTFPGA_LX110)
+const char *board = "XT_AV110";
+const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
+#elif defined(CONFIG_XTFPGA_LX200)
+const char *board = "XT_AV200";
+const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
+#elif defined(CONFIG_XTFPGA_ML605)
+const char *board = "XT_ML605";
+const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
+#elif defined(CONFIG_XTFPGA_KC705)
+const char *board = "XT_KC705";
+const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
+#else
+const char *board = "<unknown>";
+const char *description = "";
+#endif
+
+int checkboard(void)
+{
+	printf("Board: %s: %sTensilica bitstream\n", board, description);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+}
+
+int board_postclk_init(void)
+{
+	/*
+	 * Obtain CPU clock frequency from board and cache in global
+	 * data structure (Hz). Return 0 on success (OK to continue),
+	 * else non-zero (hang).
+	 */
+
+#ifdef CONFIG_SYS_FPGAREG_FREQ
+	gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
+#else
+	/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
+	gd->cpu_clk = 50000000UL;
+#endif
+	return 0;
+}
+
+/*
+ *  Miscellaneous late initializations.
+ *  The environment has been set up, so we can set the Ethernet address.
+ */
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_NET
+	/*
+	 * Initialize ethernet environment variables and board info.
+	 * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
+	 */
+
+	char *s = getenv("ethaddr");
+	if (s == 0) {
+		unsigned int x;
+		char s[] = __stringify(CONFIG_ETHBASE);
+		x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
+			& FPGAREG_MAC_MASK;
+		sprintf(&s[15], "%02x", x);
+		setenv("ethaddr", s);
+	}
+#endif /* CONFIG_CMD_NET */
+
+	return 0;
+}
+
+U_BOOT_DEVICE(sysreset) = {
+	.name = "xtfpga_sysreset",
+};
+
+static struct ethoc_eth_pdata ethoc_pdata = {
+	.eth_pdata = {
+		.iobase = CONFIG_SYS_ETHOC_BASE,
+	},
+	.packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
+};
+
+U_BOOT_DEVICE(ethoc) = {
+	.name = "ethoc",
+	.platdata = &ethoc_pdata,
+};

configs/xtfpga_defconfig

@@ -0,0 +1,22 @@
+CONFIG_XTENSA=y
+CONFIG_SYS_CPU="dc233c"
+CONFIG_XTFPGA_KC705=y
+CONFIG_BOOTDELAY=10
+CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press <SPACE> to stop\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_DM=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_DM_STDIO is not set
+# CONFIG_DM_SEQ_ALIAS is not set
+CONFIG_SYSRESET=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_ETHOC=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y

drivers/sysreset/Makefile

@@ -13,3 +13,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
+obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o

drivers/sysreset/sysreset_xtfpga.c

@@ -0,0 +1,37 @@
+/*
+ * Cadence Tensilica xtfpga system reset driver.
+ *
+ * (C) Copyright 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+
+static int xtfpga_reset_request(struct udevice *dev, enum sysreset_t type)
+{
+	switch (type) {
+	case SYSRESET_COLD:
+		writel(CONFIG_SYS_FPGAREG_RESET_CODE,
+		       CONFIG_SYS_FPGAREG_RESET);
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops xtfpga_sysreset_ops = {
+	.request	= xtfpga_reset_request,
+};
+
+U_BOOT_DRIVER(xtfpga_sysreset) = {
+	.name	= "xtfpga_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &xtfpga_sysreset_ops,
+};

include/configs/xtfpga.h

@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2007-2013 Tensilica, Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/core.h>
+#include <asm/addrspace.h>
+#include <asm/config.h>
+
+/*
+ * The 'xtfpga' board describes a set of very similar boards with only minimal
+ * differences.
+ */
+
+/*=====================*/
+/* Board and Processor */
+/*=====================*/
+
+#define CONFIG_XTFPGA
+
+/* FPGA CPU freq after init */
+#define CONFIG_SYS_CLK_FREQ		(gd->cpu_clk)
+
+/*===================*/
+/* RAM Layout        */
+/*===================*/
+
+#if XCHAL_HAVE_PTP_MMU
+#define CONFIG_SYS_MEMORY_BASE		\
+	(XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
+#define CONFIG_SYS_IO_BASE		0xf0000000
+#else
+#define CONFIG_SYS_MEMORY_BASE		0x60000000
+#define CONFIG_SYS_IO_BASE		0x90000000
+#define CONFIG_MAX_MEM_MAPPED		0x10000000
+#endif
+
+/* Onboard RAM sizes:
+ *
+ * LX60		0x04000000		  64 MB
+ * LX110	0x03000000		  48 MB
+ * LX200	0x06000000		  96 MB
+ * ML605	0x18000000		 384 MB
+ * KC705	0x38000000		 896 MB
+ *
+ * noMMU configurations can only see first 256MB of onboard memory.
+ */
+
+#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
+#define CONFIG_SYS_SDRAM_SIZE		CONFIG_BOARD_SDRAM_SIZE
+#else
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		MEMADDR(0x00000000)
+
+/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
+#ifdef CONFIG_XTFPGA_LX60
+# define CONFIG_SYS_MONITOR_LEN		0x00020000	/* 128KB */
+#else
+# define CONFIG_SYS_MONITOR_LEN		0x00040000	/* 256KB */
+#endif
+
+#define CONFIG_SYS_STACKSIZE		(512 << 10)	/* stack 512KB */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* heap  256KB */
+
+/* Linux boot param area in RAM (used only when booting linux) */
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64  << 10)
+
+/* Memory test is destructive so default must not overlap vectors or U-Boot*/
+#define CONFIG_SYS_MEMTEST_START	MEMADDR(0x01000000)
+#define CONFIG_SYS_MEMTEST_END		MEMADDR(0x02000000)
+
+/* Load address for stand-alone applications.
+ * MEMADDR cannot be used here, because the definition needs to be
+ * a plain number as it's used as -Ttext argument for ld in standalone
+ * example makefile.
+ * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually.
+ */
+#if XCHAL_HAVE_PTP_MMU
+#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
+#define CONFIG_STANDALONE_LOAD_ADDR	0x00800000
+#else
+#define CONFIG_STANDALONE_LOAD_ADDR	0xd0800000
+#endif
+#else
+#define CONFIG_STANDALONE_LOAD_ADDR	0x60800000
+#endif
+
+#if defined(CONFIG_MAX_MEM_MAPPED) && \
+	CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_MEMORY_SIZE		CONFIG_MAX_MEM_MAPPED
+#else
+#define CONFIG_SYS_MEMORY_SIZE		CONFIG_SYS_SDRAM_SIZE
+#endif
+
+#define CONFIG_SYS_MEMORY_TOP		MEMADDR(CONFIG_SYS_MEMORY_SIZE)
+#define CONFIG_SYS_TEXT_ADDR		\
+	(CONFIG_SYS_MEMORY_TOP - CONFIG_SYS_MONITOR_LEN)
+
+/* Used by tftpboot; env var 'loadaddr' */
+#define CONFIG_SYS_LOAD_ADDR		MEMADDR(0x02000000)
+
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+
+#undef	CONFIG_USE_IRQ			/* Keep it simple, poll only */
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTFILE			"uImage"
+	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024
+	/* Prt buf */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+	/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_SAVES
+
+/*==============================*/
+/* U-Boot autoboot configuration */
+/*==============================*/
+
+#define CONFIG_BOOT_RETRY_TIME		60	/* retry after 60 secs */
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE			/* Support tab autocompletion */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG		1	/* Require manual reboot */
+#endif
+
+
+/*=========================================*/
+/* FPGA Registers (board info and control) */
+/*=========================================*/
+
+/*
+ * These assume FPGA bitstreams from Tensilica release RB and up. Earlier
+ * releases may not provide any/all of these registers or at these offsets.
+ * Some of the FPGA registers are broken down into bitfields described by
+ * SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
+ */
+
+/* Date of FPGA bitstream build in binary coded decimal (BCD) */
+#define CONFIG_SYS_FPGAREG_DATE		IOADDR(0x0D020000)
+#define FPGAREG_MTH_SHIFT		24		/* BCD month 1..12 */
+#define FPGAREG_MTH_WIDTH		8
+#define FPGAREG_MTH_MASK		0xFF000000
+#define FPGAREG_DAY_SHIFT		16		/* BCD day 1..31 */
+#define FPGAREG_DAY_WIDTH		8
+#define FPGAREG_DAY_MASK		0x00FF0000
+#define FPGAREG_YEAR_SHIFT		0		/* BCD year 2001..9999*/
+#define FPGAREG_YEAR_WIDTH		16
+#define FPGAREG_YEAR_MASK		0x0000FFFF
+
+/* FPGA core clock frequency in Hz (also input to UART) */
+#define CONFIG_SYS_FPGAREG_FREQ	IOADDR(0x0D020004)	/* CPU clock frequency*/
+
+/*
+ * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
+ *   Bits 0..5 set the lower 6 bits of the default ethernet MAC.
+ *   Bit 6 is reserved for future use by Tensilica.
+ *   Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
+ *   the base of flash * (when on/1) or to the base of RAM (when off/0).
+ */
+#define CONFIG_SYS_FPGAREG_DIPSW	IOADDR(0x0D02000C)
+#define FPGAREG_MAC_SHIFT		0	/* Ethernet MAC bits 0..5 */
+#define FPGAREG_MAC_WIDTH		6
+#define FPGAREG_MAC_MASK		0x3f
+#define FPGAREG_BOOT_SHIFT		7	/* Boot ROM addr mapping */
+#define FPGAREG_BOOT_WIDTH		1
+#define FPGAREG_BOOT_MASK		0x80
+#define FPGAREG_BOOT_RAM		0
+#define FPGAREG_BOOT_FLASH		(1<<FPGAREG_BOOT_SHIFT)
+
+/* Force hard reset of board by writing a code to this register */
+#define CONFIG_SYS_FPGAREG_RESET	IOADDR(0x0D020010) /* Reset board .. */
+#define CONFIG_SYS_FPGAREG_RESET_CODE	0x0000DEAD   /*  by writing this code */
+
+/*====================*/
+/* Serial Driver Info */
+/*====================*/
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_COM1		IOADDR(0x0D050020) /* Base address */
+
+/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_CLK_FREQ
+#define CONFIG_CONS_INDEX		1	/* use UART0 for console */
+#define CONFIG_BAUDRATE			115200	/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*======================*/
+/* Ethernet Driver Info */
+/*======================*/
+
+#define CONFIG_ETHBASE			00:50:C2:13:6f:00
+#define CONFIG_SYS_ETHOC_BASE		IOADDR(0x0d030000)
+#define CONFIG_SYS_ETHOC_BUFFER_ADDR	IOADDR(0x0D800000)
+
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER			/* use generic CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#ifdef CONFIG_XTFPGA_LX60
+# define CONFIG_SYS_FLASH_SIZE		0x0040000	/* 4MB */
+# define CONFIG_SYS_FLASH_SECT_SZ	0x10000		/* block size 64KB */
+# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x2000		/* param size  8KB */
+# define CONFIG_SYS_FLASH_BASE		IOADDR(0x08000000)
+# define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#elif defined(CONFIG_XTFPGA_KC705)
+# define CONFIG_SYS_FLASH_SIZE		0x8000000	/* 128MB */
+# define CONFIG_SYS_FLASH_SECT_SZ	0x20000		/* block size 128KB */
+# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x8000		/* param size 32KB */
+# define CONFIG_SYS_FLASH_BASE		IOADDR(0x00000000)
+# define CONFIG_SYS_MONITOR_BASE	IOADDR(0x06000000)
+#else
+# define CONFIG_SYS_FLASH_SIZE		0x1000000	/* 16MB */
+# define CONFIG_SYS_FLASH_SECT_SZ	0x20000		/* block size 128KB */
+# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x8000		/* param size 32KB */
+# define CONFIG_SYS_FLASH_BASE		IOADDR(0x08000000)
+# define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#endif
+#define CONFIG_SYS_MAX_FLASH_SECT	\
+	(CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
+	 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
+#define CONFIG_SYS_FLASH_PROTECTION		/* hw flash protection */
+
+/*
+ * Put environment in top block (64kB)
+ * Another option would be to put env. in 2nd param block offs 8KB, size 8KB
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET    (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SIZE	     CONFIG_SYS_FLASH_SECT_SZ
+
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#endif /* __CONFIG_H */