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https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
85xx: Get ride of old TLB setup code
Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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parent
3b558e26a5
commit
7dc358bb0d
19 changed files with 0 additions and 39 deletions
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@ -149,27 +149,7 @@ void cpu_init_early_f(void)
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init_laws();
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invalidate_tlb(0);
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#ifdef CONFIG_FSL_INIT_TLBS
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init_tlbs();
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#else
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{
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extern u32 tlb1_entry;
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u32 *tmp = &tlb1_entry;
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int i;
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int num = tmp[2];
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/* skip to actual table */
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tmp += 3;
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for (i = 0; i < num; i++, tmp += 4) {
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mtspr(MAS0, tmp[0]);
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mtspr(MAS1, tmp[1]);
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mtspr(MAS2, tmp[2]);
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mtspr(MAS3, tmp[3]);
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asm volatile("isync;msync;tlbwe;isync");
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}
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}
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#endif
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}
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/*
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@ -79,7 +79,6 @@ void invalidate_tlb(u8 tlb)
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void init_tlbs(void)
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{
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#ifdef CONFIG_FSL_INIT_TLBS
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int i;
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for (i = 0; i < num_tlb_entries; i++) {
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@ -88,7 +87,6 @@ void init_tlbs(void)
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tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
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tlb_table[i].iprot);
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}
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#endif
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return ;
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}
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@ -64,7 +64,6 @@
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
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@ -56,7 +56,6 @@
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* sysclk for MPC85xx
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@ -44,7 +44,6 @@
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/* Using Localbus SDRAM to emulate flash before we can program the flash,
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* normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
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@ -48,7 +48,6 @@
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@ -43,7 +43,6 @@
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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@ -56,7 +56,6 @@
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@ -48,7 +48,6 @@
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@ -53,7 +53,6 @@
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* sysclk for MPC85xx
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@ -50,7 +50,6 @@
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@ -52,7 +52,6 @@
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#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* sysclk for MPC85xx
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@ -52,7 +52,6 @@
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#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* sysclk for MPC85xx
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@ -57,7 +57,6 @@
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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@ -51,7 +51,6 @@
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#endif
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/*
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* sysclk for MPC85xx
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@ -57,7 +57,6 @@
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
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@ -51,7 +51,6 @@
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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@ -52,7 +52,6 @@
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#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/* sysclk for MPC85xx
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*/
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@ -52,7 +52,6 @@
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#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
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/* sysclk for MPC85xx
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*/
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