mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-20 14:41:58 +00:00
board: presidio-asic: Add basic G3 engr. development board support
Add basic Presidio G3 engineering board support Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
This commit is contained in:
parent
0de653d8cf
commit
7d706a886f
11 changed files with 438 additions and 0 deletions
|
@ -1675,6 +1675,10 @@ config TARGET_DURIAN
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Support for durian platform.
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It has 2GB Sdram, uart and pcie.
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config TARGET_PRESIDIO_ASIC
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bool "Support Cortina Presidio ASIC Platform"
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select ARM64
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endchoice
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config ARCH_SUPPORT_TFABOOT
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@ -1823,6 +1827,7 @@ source "board/Marvell/gplugd/Kconfig"
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source "board/armadeus/apf27/Kconfig"
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source "board/armltd/vexpress/Kconfig"
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source "board/armltd/vexpress64/Kconfig"
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source "board/cortina/presidio-asic/Kconfig"
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source "board/broadcom/bcm23550_w1d/Kconfig"
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source "board/broadcom/bcm28155_ap/Kconfig"
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source "board/broadcom/bcm963158/Kconfig"
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@ -909,6 +909,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
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dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
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dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
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targets += $(dtb-y)
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# Add any required device tree compiler flags here
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69
arch/arm/dts/ca-presidio-engboard.dts
Normal file
69
arch/arm/dts/ca-presidio-engboard.dts
Normal file
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@ -0,0 +1,69 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020, Cortina Access Inc.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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mmc0: mmc@f4400000 {
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compatible = "snps,dw-cortina";
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reg = <0x0 0xf4400000 0x1000>;
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bus-width = <4>;
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io_ds = <0x77>;
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fifo-mode;
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sd_dll_ctrl = <0xf43200e8>;
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io_drv_ctrl = <0xf432004c>;
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};
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gpio0: gpio-controller@0xf4329280 {
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compatible = "cortina,ca-gpio";
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reg = <0x0 0xf4329280 0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "okay";
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};
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gpio1: gpio-controller@0xf43292a4 {
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compatible = "cortina,ca-gpio";
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reg = <0x0 0xf43292a4 0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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watchdog: watchdog@0xf432901c {
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compatible = "cortina,ca-wdt";
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reg = <0x0 0xf432901c 0x34>,
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<0x0 0xf4320020 0x04>;
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status = "okay";
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};
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uart0: serial@0xf4329148 {
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u-boot,dm-pre-reloc;
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compatible = "cortina,ca-uart";
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reg = <0x0 0xf4329148 0x30>;
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status = "okay";
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};
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i2c: i2c@f4329120 {
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compatible = "cortina,ca-i2c";
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reg = <0x0 0xf4329120 0x28>;
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clock-frequency = <400000>;
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};
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sflash: sflash-controller@f4324000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "cortina,ca-sflash";
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reg = <0x0 0xf4324000 0x50>;
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reg-names = "sflash-regs";
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-rx-bus-width = <1>;
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spi-max-frequency = <108000000>;
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};
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};
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};
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5
arch/arm/mach-cortina/Makefile
Normal file
5
arch/arm/mach-cortina/Makefile
Normal file
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2020 Cortina Access Inc.
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#
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obj-y += lowlevel_init.o
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18
board/cortina/presidio-asic/Kconfig
Normal file
18
board/cortina/presidio-asic/Kconfig
Normal file
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@ -0,0 +1,18 @@
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if TARGET_PRESIDIO_ASIC
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config BIT64
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bool
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default y
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select SOC_CA7774
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config SYS_BOARD
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default "presidio-asic"
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config SYS_VENDOR
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default "cortina"
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config SYS_CONFIG_NAME
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default "presidio_asic"
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source "board/cortina/common/Kconfig"
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endif
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6
board/cortina/presidio-asic/MAINTAINERS
Normal file
6
board/cortina/presidio-asic/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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Cortina Presidio ASIC G3 Engineering BOARD
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M: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
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S: Supported
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F: board/cortina/presidio-asic/
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F: include/configs/presidio_asic.h
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F: configs/cortina_presidio-asic*defconfig
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8
board/cortina/presidio-asic/Makefile
Normal file
8
board/cortina/presidio-asic/Makefile
Normal file
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2020 Cortina-Access.Inc.
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#
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#
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obj-y := presidio.o
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obj-y += lowlevel_init.o
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87
board/cortina/presidio-asic/lowlevel_init.S
Normal file
87
board/cortina/presidio-asic/lowlevel_init.S
Normal file
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@ -0,0 +1,87 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Cortina-Access
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*
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/armv8/mmu.h>
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.globl lowlevel_init
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lowlevel_init:
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mov x29, lr /* Save LR */
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#if defined(CONFIG_SOC_CA7774)
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/* Enable SMPEN in CPUECTLR */
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mrs x0, s3_1_c15_c2_1
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tst x0, #0x40
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b.ne skip_smp_setup
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orr x0, x0, #0x40
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msr s3_1_c15_c2_1, x0
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skip_smp_setup:
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#endif
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#if defined(CONFIG_SOC_CA8277B)
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/* Enable CPU Timer */
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ldr x0, =CONFIG_SYS_TIMER_BASE
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mov x1, #1
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str w1, [x0]
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#endif
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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#ifndef CONFIG_TARGET_VENUS
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ldr x0, =GICD_BASE
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bl gic_init_secure
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#endif
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1:
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#if defined(CONFIG_GICV3)
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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#endif
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#endif
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#ifdef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, x1, 2f
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/*
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* Slave should wait for master clearing spin table.
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* This sync prevent salves observing incorrect
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* value of spin table and jumping to wrong place.
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*/
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#ifdef CONFIG_GICV2
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ldr x0, =GICC_BASE
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#endif
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bl gic_wait_for_interrupt
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#endif
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/*
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* All slaves will enter EL2 and optionally EL1.
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*/
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adr x4, lowlevel_in_el2
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ldr x5, =ES_TO_AARCH64
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bl armv8_switch_to_el2
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lowlevel_in_el2:
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x4, lowlevel_in_el1
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ldr x5, =ES_TO_AARCH64
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bl armv8_switch_to_el1
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lowlevel_in_el1:
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#endif
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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2:
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mov lr, x29 /* Restore LR */
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ret
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134
board/cortina/presidio-asic/presidio.c
Normal file
134
board/cortina/presidio-asic/presidio.c
Normal file
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@ -0,0 +1,134 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020 - Cortina Access Inc.
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <configs/presidio_asic.h>
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#include <linux/psci.h>
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#include <asm/psci.h>
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#include <cpu_func.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CA_PERIPH_BASE 0xE0000000UL
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#define CA_PERIPH_SIZE 0x20000000UL
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#define CA_GLOBAL_BASE 0xf4320000
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#define CA_GLOBAL_JTAG_ID 0xf4320000
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#define CA_GLOBAL_BLOCK_RESET 0xf4320004
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#define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16)
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#define CA_DMA_SEC_SSP_BAUDRATE_CTRL 0xf7001b94
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#define CA_DMA_SEC_SSP_ID 0xf7001b80
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int print_cpuinfo(void)
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{
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printf("CPU: Cortina Presidio G3\n");
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return 0;
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}
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static struct mm_region presidio_mem_map[] = {
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{
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.virt = DDR_BASE,
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.phys = DDR_BASE,
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.size = PHYS_SDRAM_1_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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},
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{
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.virt = CA_PERIPH_BASE,
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.phys = CA_PERIPH_BASE,
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.size = CA_PERIPH_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = presidio_mem_map;
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static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
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u64 arg2)
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{
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asm volatile("mov x0, %0\n"
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"mov x1, %1\n"
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"mov x2, %2\n"
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"mov x3, %3\n"
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"smc #0\n"
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: "+r" (function_id)
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: "r" (arg0), "r" (arg1), "r" (arg2)
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);
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return function_id;
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}
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int board_early_init_r(void)
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{
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dcache_disable();
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return 0;
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}
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int board_init(void)
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{
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unsigned int reg_data, jtag_id;
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/* Enable timer */
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writel(1, CONFIG_SYS_TIMER_BASE);
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/* Enable snoop in CCI400 slave port#4 */
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writel(3, 0xF5595000);
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jtag_id = readl(CA_GLOBAL_JTAG_ID);
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/* If this is HGU variant then do not use
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* the Saturn daughter card ref. clk
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*/
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if (jtag_id == 0x1010D8F3) {
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reg_data = readl(0xF3100064);
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/* change multifunc. REF CLK pin to
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* a simple GPIO pin
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*/
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reg_data |= (1 << 1);
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writel(reg_data, 0xf3100064);
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}
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return 0;
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}
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int dram_init(void)
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{
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unsigned int ddr_size;
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ddr_size = readl(0x111100c);
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gd->ram_size = ddr_size * 0x100000;
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
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}
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#ifdef CONFIG_LAST_STAGE_INIT
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int last_stage_init(void)
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{
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u32 val;
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val = readl(CA_GLOBAL_BLOCK_RESET);
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val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA;
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writel(val, CA_GLOBAL_BLOCK_RESET);
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/* reduce output pclk ~3.7Hz to save power consumption */
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writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL);
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return 0;
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}
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#endif
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29
configs/cortina_presidio-asic-base_defconfig
Normal file
29
configs/cortina_presidio-asic-base_defconfig
Normal file
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@ -0,0 +1,29 @@
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CONFIG_ARM=y
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# CONFIG_SYS_ARCH_TIMER is not set
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CONFIG_TARGET_PRESIDIO_ASIC=y
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CONFIG_SYS_TEXT_BASE=0x04000000
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CONFIG_DM_GPIO=y
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CONFIG_ENV_SIZE=0x20000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_IDENT_STRING="Presidio-SoC"
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CONFIG_SHOW_BOOT_PROGRESS=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_SYS_PROMPT="G3#"
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CONFIG_CMD_WDT=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIMER=y
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CONFIG_CMD_SMC=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
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# CONFIG_NET is not set
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CONFIG_DM=y
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CONFIG_CORTINA_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_DM_SERIAL=y
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CONFIG_CORTINA_UART=y
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CONFIG_WDT=y
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CONFIG_WDT_CORTINA=y
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75
include/configs/presidio_asic.h
Normal file
75
include/configs/presidio_asic.h
Normal file
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@ -0,0 +1,75 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Cortina Access Inc.
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*
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* Configuration for Cortina-Access Presidio board.
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*/
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#ifndef __PRESIDIO_ASIC_H
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#define __PRESIDIO_ASIC_H
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#define CONFIG_REMAKE_ELF
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
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#define CONFIG_SYS_BOOTM_LEN 0x00c00000
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 25000000
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#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY
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#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
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/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
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* does not yet support DT. Thus define it here.
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*/
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#define CONFIG_GICV2
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#define GICD_BASE 0xf7011000
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#define GICC_BASE 0xf7012000
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#define CONFIG_SYS_MEMTEST_SCRATCH 0x00100000
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#define CONFIG_SYS_MEMTEST_START 0x05000000
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#define CONFIG_SYS_MEMTEST_END 0x0D000000
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
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#define CONFIG_SYS_TIMER_BASE 0xf4321000
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/* Use external clock source */
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#define PRESIDIO_APB_CLK 125000000
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#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK
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/* Cortina Serial Configuration */
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#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
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#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
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(void *)CONFIG_SYS_SERIAL1}
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
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#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000)
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#define CONFIG_LAST_STAGE_INIT
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/* SDRAM Bank #1 */
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#define DDR_BASE 0x00000000
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#define PHYS_SDRAM_1 DDR_BASE
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#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
/* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/* max command args */
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
|
||||
|
||||
#endif /* __PRESIDIO_ASIC_H */
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Reference in a new issue