mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
NAND support for zylonite board + some minor cleanup.
This commit is contained in:
Markus Klotzbuecher
Markus Klotzbuecher
parent
71ae411a63
commit
7c93b2443c
5 changed files with 654 additions and 96 deletions
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@ -1,4 +1,3 @@
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#
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#
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# (C) Copyright 2000
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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@ -21,12 +20,11 @@
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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# MA 02111-1307 USA
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#
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#
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include $(TOPDIR)/config.mk
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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LIB = lib$(BOARD).a
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OBJS := zylonite.o flash.o
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OBJS := zylonite.o nand.o
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SOBJS := lowlevel_init.o
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SOBJS := lowlevel_init.o
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$(LIB): $(OBJS) $(SOBJS)
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$(LIB): $(OBJS) $(SOBJS)
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@ -2,3 +2,5 @@
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#TEXT_BASE = 0xa1700000
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#TEXT_BASE = 0xa1700000
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#TEXT_BASE = 0xa3080000
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#TEXT_BASE = 0xa3080000
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TEXT_BASE = 0xa3008000
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TEXT_BASE = 0xa3008000
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BOARDLIBS = drivers/nand/libnand.a
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@ -235,6 +235,7 @@ mem_init:
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orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
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orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
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str r1, [r0]
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str r1, [r0]
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#ifndef CFG_SKIP_DRAM_SCRUB
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/* scrub/init SDRAM if enabled/present */
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/* scrub/init SDRAM if enabled/present */
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/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
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/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
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/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
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/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
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@ -254,6 +255,7 @@ mem_init:
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stmia r8!, {r0-r7}
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stmia r8!, {r0-r7}
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beq 15f
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beq 15f
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b 10b
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b 10b
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#endif /* CFG_SKIP_DRAM_SCRUB */
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15:
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15:
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/* Mask all interrupts */
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/* Mask all interrupts */
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584
board/zylonite/nand.c
Normal file
584
board/zylonite/nand.c
Normal file
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@ -0,0 +1,584 @@
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/*
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* (C) Copyright 2006 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#ifdef CONFIG_NEW_NAND_CODE
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#include <nand.h>
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#include <asm/arch/pxa-regs.h>
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#ifdef CFG_DFC_DEBUG1
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# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
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#else
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# define DFC_DEBUG1(fmt, args...)
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#endif
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#ifdef CFG_DFC_DEBUG2
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# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
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#else
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# define DFC_DEBUG2(fmt, args...)
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#endif
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#ifdef CFG_DFC_DEBUG3
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# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
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#else
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# define DFC_DEBUG3(fmt, args...)
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#endif
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#define MIN(x, y) ((x < y) ? x : y)
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/* These really don't belong here, as they are specific to the NAND Model */
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static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
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static struct nand_bbt_descr delta_bbt_descr = {
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.options = 0,
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.offs = 0,
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.len = 2,
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.pattern = scan_ff_pattern
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};
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static struct nand_oobinfo delta_oob = {
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.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
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.eccbytes = 6,
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.eccpos = {2, 3, 4, 5, 6, 7},
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.oobfree = { {8, 2}, {12, 4} }
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};
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/*
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* not required for Monahans DFC
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*/
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static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
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{
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return;
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}
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#if 0
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/* read device ready pin */
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static int dfc_device_ready(struct mtd_info *mtdinfo)
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{
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if(NDSR & NDSR_RDY)
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return 1;
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else
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return 0;
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return 0;
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}
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#endif
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/*
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* Write buf to the DFC Controller Data Buffer
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*/
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static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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unsigned long bytes_multi = len & 0xfffffffc;
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unsigned long rest = len & 0x3;
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unsigned long *long_buf;
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int i;
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DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
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if(bytes_multi) {
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for(i=0; i<bytes_multi; i+=4) {
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long_buf = (unsigned long*) &buf[i];
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NDDB = *long_buf;
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}
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}
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if(rest) {
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printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
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}
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return;
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}
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/*
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* These functions are quite problematic for the DFC. Luckily they are
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* not used in the current nand code, except for nand_command, which
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* we've defined our own anyway. The problem is, that we always need
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* to write 4 bytes to the DFC Data Buffer, but in these functions we
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* don't know if to buffer the bytes/half words until we've gathered 4
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* bytes or if to send them straight away.
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*
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* Solution: Don't use these with Mona's DFC and complain loudly.
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*/
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static void dfc_write_word(struct mtd_info *mtd, u16 word)
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{
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printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
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}
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static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
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{
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printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
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}
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/* The original:
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* static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
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*
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* Shouldn't this be "u_char * const buf" ?
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*/
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static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
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{
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int i=0, j;
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/* we have to be carefull not to overflow the buffer if len is
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* not a multiple of 4 */
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unsigned long bytes_multi = len & 0xfffffffc;
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unsigned long rest = len & 0x3;
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unsigned long *long_buf;
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DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
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/* if there are any, first copy multiple of 4 bytes */
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if(bytes_multi) {
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for(i=0; i<bytes_multi; i+=4) {
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long_buf = (unsigned long*) &buf[i];
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*long_buf = NDDB;
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}
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}
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/* ...then the rest */
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if(rest) {
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unsigned long rest_data = NDDB;
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for(j=0;j<rest; j++)
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buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
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}
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return;
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}
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/*
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* read a word. Not implemented as not used in NAND code.
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*/
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static u16 dfc_read_word(struct mtd_info *mtd)
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{
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printf("dfc_write_byte: UNIMPLEMENTED.\n");
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return 0;
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}
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/* global var, too bad: mk@tbd: move to ->priv pointer */
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static unsigned long read_buf = 0;
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static int bytes_read = -1;
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/*
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* read a byte from NDDB Because we can only read 4 bytes from NDDB at
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* a time, we buffer the remaining bytes. The buffer is reset when a
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* new command is sent to the chip.
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*
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* WARNING:
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* This function is currently only used to read status and id
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* bytes. For these commands always 8 bytes need to be read from
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* NDDB. So we read and discard these bytes right now. In case this
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* function is used for anything else in the future, we must check
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* what was the last command issued and read the appropriate amount of
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* bytes respectively.
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*/
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static u_char dfc_read_byte(struct mtd_info *mtd)
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{
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unsigned char byte;
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unsigned long dummy;
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if(bytes_read < 0) {
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read_buf = NDDB;
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dummy = NDDB;
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bytes_read = 0;
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}
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byte = (unsigned char) (read_buf>>(8 * bytes_read++));
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if(bytes_read >= 4)
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bytes_read = -1;
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DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
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return byte;
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}
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/* calculate delta between OSCR values start and now */
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static unsigned long get_delta(unsigned long start)
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{
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unsigned long cur = OSCR;
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if(cur < start) /* OSCR overflowed */
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return (cur + (start^0xffffffff));
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else
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return (cur - start);
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}
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/* delay function, this doesn't belong here */
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static void wait_us(unsigned long us)
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{
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unsigned long start = OSCR;
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us *= OSCR_CLK_FREQ;
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while (get_delta(start) < us) {
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/* do nothing */
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}
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}
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static void dfc_clear_nddb(void)
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{
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NDCR &= ~NDCR_ND_RUN;
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wait_us(CFG_NAND_OTHER_TO);
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}
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/* wait_event with timeout */
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static unsigned long dfc_wait_event(unsigned long event)
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{
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unsigned long ndsr, timeout, start = OSCR;
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if(!event)
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return 0xff000000;
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else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
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timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
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else
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timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
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while(1) {
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ndsr = NDSR;
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if(ndsr & event) {
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NDSR |= event;
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break;
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}
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if(get_delta(start) > timeout) {
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DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
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return 0xff000000;
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}
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}
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return ndsr;
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}
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/* we don't always wan't to do this */
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static void dfc_new_cmd(void)
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{
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int retry = 0;
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unsigned long status;
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while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
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/* Clear NDSR */
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NDSR = 0xFFF;
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/* set NDCR[NDRUN] */
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if(!(NDCR & NDCR_ND_RUN))
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NDCR |= NDCR_ND_RUN;
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status = dfc_wait_event(NDSR_WRCMDREQ);
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if(status & NDSR_WRCMDREQ)
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return;
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DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
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dfc_clear_nddb();
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}
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DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
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}
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/* this function is called after Programm and Erase Operations to
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* check for success or failure */
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static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
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{
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unsigned long ndsr=0, event=0;
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if(state == FL_WRITING) {
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event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
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} else if(state == FL_ERASING) {
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event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
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}
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ndsr = dfc_wait_event(event);
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if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
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return(0x1); /* Status Read error */
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return 0;
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}
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/* cmdfunc send commands to the DFC */
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static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
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int column, int page_addr)
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{
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/* register struct nand_chip *this = mtd->priv; */
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unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
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/* clear the ugly byte read buffer */
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bytes_read = -1;
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read_buf = 0;
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switch (command) {
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case NAND_CMD_READ0:
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DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
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dfc_new_cmd();
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ndcb0 = (NAND_CMD_READ0 | (4<<16));
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column >>= 1; /* adjust for 16 bit bus */
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ndcb1 = (((column>>1) & 0xff) |
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((page_addr<<8) & 0xff00) |
|
||||||
|
((page_addr<<8) & 0xff0000) |
|
||||||
|
((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
|
||||||
|
event = NDSR_RDDREQ;
|
||||||
|
goto write_cmd;
|
||||||
|
case NAND_CMD_READ1:
|
||||||
|
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
|
||||||
|
goto end;
|
||||||
|
case NAND_CMD_READOOB:
|
||||||
|
DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
|
||||||
|
goto end;
|
||||||
|
case NAND_CMD_READID:
|
||||||
|
dfc_new_cmd();
|
||||||
|
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
|
||||||
|
ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
|
||||||
|
event = NDSR_RDDREQ;
|
||||||
|
goto write_cmd;
|
||||||
|
case NAND_CMD_PAGEPROG:
|
||||||
|
/* sent as a multicommand in NAND_CMD_SEQIN */
|
||||||
|
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
|
||||||
|
goto end;
|
||||||
|
case NAND_CMD_ERASE1:
|
||||||
|
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
|
||||||
|
dfc_new_cmd();
|
||||||
|
ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
|
||||||
|
ndcb1 = (page_addr & 0x00ffffff);
|
||||||
|
goto write_cmd;
|
||||||
|
case NAND_CMD_ERASE2:
|
||||||
|
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
|
||||||
|
goto end;
|
||||||
|
case NAND_CMD_SEQIN:
|
||||||
|
/* send PAGE_PROG command(0x1080) */
|
||||||
|
dfc_new_cmd();
|
||||||
|
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
|
||||||
|
ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
|
||||||
|
column >>= 1; /* adjust for 16 bit bus */
|
||||||
|
ndcb1 = (((column>>1) & 0xff) |
|
||||||
|
((page_addr<<8) & 0xff00) |
|
||||||
|
((page_addr<<8) & 0xff0000) |
|
||||||
|
((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
|
||||||
|
event = NDSR_WRDREQ;
|
||||||
|
goto write_cmd;
|
||||||
|
case NAND_CMD_STATUS:
|
||||||
|
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
|
||||||
|
dfc_new_cmd();
|
||||||
|
ndcb0 = NAND_CMD_STATUS | (4<<21);
|
||||||
|
event = NDSR_RDDREQ;
|
||||||
|
goto write_cmd;
|
||||||
|
case NAND_CMD_RESET:
|
||||||
|
DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
|
||||||
|
ndcb0 = NAND_CMD_RESET | (5<<21);
|
||||||
|
event = NDSR_CS0_CMDD;
|
||||||
|
goto write_cmd;
|
||||||
|
default:
|
||||||
|
printk("dfc_cmdfunc: error, unsupported command.\n");
|
||||||
|
goto end;
|
||||||
|
}
|
||||||
|
|
||||||
|
write_cmd:
|
||||||
|
NDCB0 = ndcb0;
|
||||||
|
NDCB0 = ndcb1;
|
||||||
|
NDCB0 = ndcb2;
|
||||||
|
|
||||||
|
/* wait_event: */
|
||||||
|
dfc_wait_event(event);
|
||||||
|
end:
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void dfc_gpio_init(void)
|
||||||
|
{
|
||||||
|
DFC_DEBUG2("Setting up DFC GPIO's.\n");
|
||||||
|
|
||||||
|
/* no idea what is done here, see zylonite.c */
|
||||||
|
GPIO4 = 0x1;
|
||||||
|
|
||||||
|
DF_ALE_WE1 = 0x00000001;
|
||||||
|
DF_ALE_WE2 = 0x00000001;
|
||||||
|
DF_nCS0 = 0x00000001;
|
||||||
|
DF_nCS1 = 0x00000001;
|
||||||
|
DF_nWE = 0x00000001;
|
||||||
|
DF_nRE = 0x00000001;
|
||||||
|
DF_IO0 = 0x00000001;
|
||||||
|
DF_IO8 = 0x00000001;
|
||||||
|
DF_IO1 = 0x00000001;
|
||||||
|
DF_IO9 = 0x00000001;
|
||||||
|
DF_IO2 = 0x00000001;
|
||||||
|
DF_IO10 = 0x00000001;
|
||||||
|
DF_IO3 = 0x00000001;
|
||||||
|
DF_IO11 = 0x00000001;
|
||||||
|
DF_IO4 = 0x00000001;
|
||||||
|
DF_IO12 = 0x00000001;
|
||||||
|
DF_IO5 = 0x00000001;
|
||||||
|
DF_IO13 = 0x00000001;
|
||||||
|
DF_IO6 = 0x00000001;
|
||||||
|
DF_IO14 = 0x00000001;
|
||||||
|
DF_IO7 = 0x00000001;
|
||||||
|
DF_IO15 = 0x00000001;
|
||||||
|
|
||||||
|
DF_nWE = 0x1901;
|
||||||
|
DF_nRE = 0x1901;
|
||||||
|
DF_CLE_NOE = 0x1900;
|
||||||
|
DF_ALE_WE1 = 0x1901;
|
||||||
|
DF_INT_RnB = 0x1900;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Board-specific NAND initialization. The following members of the
|
||||||
|
* argument are board-specific (per include/linux/mtd/nand_new.h):
|
||||||
|
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
|
||||||
|
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
|
||||||
|
* - hwcontrol: hardwarespecific function for accesing control-lines
|
||||||
|
* - dev_ready: hardwarespecific function for accesing device ready/busy line
|
||||||
|
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
|
||||||
|
* only be provided if a hardware ECC is available
|
||||||
|
* - eccmode: mode of ecc, see defines
|
||||||
|
* - chip_delay: chip dependent delay for transfering data from array to
|
||||||
|
* read regs (tR)
|
||||||
|
* - options: various chip options. They can partly be set to inform
|
||||||
|
* nand_scan about special functionality. See the defines for further
|
||||||
|
* explanation
|
||||||
|
* Members with a "?" were not set in the merged testing-NAND branch,
|
||||||
|
* so they are not set here either.
|
||||||
|
*/
|
||||||
|
void board_nand_init(struct nand_chip *nand)
|
||||||
|
{
|
||||||
|
unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
|
||||||
|
|
||||||
|
/* set up GPIO Control Registers */
|
||||||
|
dfc_gpio_init();
|
||||||
|
|
||||||
|
/* turn on the NAND Controller Clock (104 MHz @ D0) */
|
||||||
|
CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
|
||||||
|
|
||||||
|
#undef CFG_TIMING_TIGHT
|
||||||
|
#ifndef CFG_TIMING_TIGHT
|
||||||
|
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tCH);
|
||||||
|
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tCS);
|
||||||
|
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tWH);
|
||||||
|
tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tWP);
|
||||||
|
tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tRH);
|
||||||
|
tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tRP);
|
||||||
|
tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tR);
|
||||||
|
tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tWHR);
|
||||||
|
tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
|
||||||
|
DFC_MAX_tAR);
|
||||||
|
#else /* this is the tight timing */
|
||||||
|
|
||||||
|
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
|
||||||
|
DFC_MAX_tCH);
|
||||||
|
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
|
||||||
|
DFC_MAX_tCS);
|
||||||
|
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
|
||||||
|
DFC_MAX_tWH);
|
||||||
|
tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
|
||||||
|
DFC_MAX_tWP);
|
||||||
|
tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
|
||||||
|
DFC_MAX_tRH);
|
||||||
|
tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
|
||||||
|
DFC_MAX_tRP);
|
||||||
|
tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
|
||||||
|
DFC_MAX_tR);
|
||||||
|
tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
|
||||||
|
DFC_MAX_tWHR);
|
||||||
|
tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
|
||||||
|
DFC_MAX_tAR);
|
||||||
|
#endif /* CFG_TIMING_TIGHT */
|
||||||
|
|
||||||
|
|
||||||
|
DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
|
||||||
|
|
||||||
|
/* tRP value is split in the register */
|
||||||
|
if(tRP & (1 << 4)) {
|
||||||
|
tRP_high = 1;
|
||||||
|
tRP &= ~(1 << 4);
|
||||||
|
} else {
|
||||||
|
tRP_high = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
NDTR0CS0 = (tCH << 19) |
|
||||||
|
(tCS << 16) |
|
||||||
|
(tWH << 11) |
|
||||||
|
(tWP << 8) |
|
||||||
|
(tRP_high << 6) |
|
||||||
|
(tRH << 3) |
|
||||||
|
(tRP << 0);
|
||||||
|
|
||||||
|
NDTR1CS0 = (tR << 16) |
|
||||||
|
(tWHR << 4) |
|
||||||
|
(tAR << 0);
|
||||||
|
|
||||||
|
/* If it doesn't work (unlikely) think about:
|
||||||
|
* - ecc enable
|
||||||
|
* - chip select don't care
|
||||||
|
* - read id byte count
|
||||||
|
*
|
||||||
|
* Intentionally enabled by not setting bits:
|
||||||
|
* - dma (DMA_EN)
|
||||||
|
* - page size = 512
|
||||||
|
* - cs don't care, see if we can enable later!
|
||||||
|
* - row address start position (after second cycle)
|
||||||
|
* - pages per block = 32
|
||||||
|
* - ND_RDY : clears command buffer
|
||||||
|
*/
|
||||||
|
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
|
||||||
|
|
||||||
|
NDCR = (NDCR_SPARE_EN | /* use the spare area */
|
||||||
|
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
|
||||||
|
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
|
||||||
|
(2 << 16) | /* read id count = 7 ???? mk@tbd */
|
||||||
|
NDCR_ND_ARB_EN | /* enable bus arbiter */
|
||||||
|
NDCR_RDYM | /* flash device ready ir masked */
|
||||||
|
NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
|
||||||
|
NDCR_CS1_PAGEDM |
|
||||||
|
NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
|
||||||
|
NDCR_CS1_CMDDM |
|
||||||
|
NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
|
||||||
|
NDCR_CS1_BBDM |
|
||||||
|
NDCR_DBERRM | /* double bit error ir masked */
|
||||||
|
NDCR_SBERRM | /* single bit error ir masked */
|
||||||
|
NDCR_WRDREQM | /* write data request ir masked */
|
||||||
|
NDCR_RDDREQM | /* read data request ir masked */
|
||||||
|
NDCR_WRCMDREQM); /* write command request ir masked */
|
||||||
|
|
||||||
|
|
||||||
|
/* wait 10 us due to cmd buffer clear reset */
|
||||||
|
/* wait(10); */
|
||||||
|
|
||||||
|
|
||||||
|
nand->hwcontrol = dfc_hwcontrol;
|
||||||
|
/* nand->dev_ready = dfc_device_ready; */
|
||||||
|
nand->eccmode = NAND_ECC_SOFT;
|
||||||
|
nand->options = NAND_BUSWIDTH_16;
|
||||||
|
nand->waitfunc = dfc_wait;
|
||||||
|
nand->read_byte = dfc_read_byte;
|
||||||
|
nand->write_byte = dfc_write_byte;
|
||||||
|
nand->read_word = dfc_read_word;
|
||||||
|
nand->write_word = dfc_write_word;
|
||||||
|
nand->read_buf = dfc_read_buf;
|
||||||
|
nand->write_buf = dfc_write_buf;
|
||||||
|
|
||||||
|
nand->cmdfunc = dfc_cmdfunc;
|
||||||
|
nand->autooob = &delta_oob;
|
||||||
|
nand->badblock_pattern = &delta_bbt_descr;
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error "U-Boot legacy NAND support not available for Monahans DFC."
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
@ -76,14 +76,17 @@
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
|
|
||||||
#ifdef TURN_ON_ETHERNET
|
#ifdef TURN_ON_ETHERNET
|
||||||
# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
|
# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
|
||||||
#else
|
#else
|
||||||
# define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
|
# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
|
||||||
|
| CFG_CMD_ENV \
|
||||||
|
| CFG_CMD_NAND) \
|
||||||
|
& ~(CFG_CMD_NET \
|
||||||
|
| CFG_CMD_FLASH \
|
||||||
|
| CFG_CMD_IMLS))
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
#include <cmd_confdefs.h>
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
|
|
@ -127,8 +130,11 @@
|
||||||
|
|
||||||
#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
|
#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
|
||||||
|
|
||||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */
|
||||||
#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
|
|
||||||
|
/* Monahans Core Frequency */
|
||||||
|
#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
|
||||||
|
#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
|
||||||
|
|
||||||
/* valid baudrates */
|
/* valid baudrates */
|
||||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||||
|
|
@ -159,98 +165,64 @@
|
||||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
||||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||||
|
|
||||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
#define CFG_DRAM_BASE 0x80000000 /* at CS0 */
|
||||||
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
|
#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
|
||||||
#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
|
|
||||||
#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
|
|
||||||
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
|
|
||||||
|
|
||||||
#define CFG_DRAM_BASE 0xa0000000
|
#undef CFG_SKIP_DRAM_SCRUB
|
||||||
#define CFG_DRAM_SIZE 0x04000000
|
|
||||||
|
|
||||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
|
||||||
|
|
||||||
#define FPGA_REGS_BASE_PHYSICAL 0x08000000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* GPIO settings
|
|
||||||
*/
|
|
||||||
#define CFG_GPSR0_VAL 0x00008000
|
|
||||||
#define CFG_GPSR1_VAL 0x00FC0382
|
|
||||||
#define CFG_GPSR2_VAL 0x0001FFFF
|
|
||||||
#define CFG_GPCR0_VAL 0x00000000
|
|
||||||
#define CFG_GPCR1_VAL 0x00000000
|
|
||||||
#define CFG_GPCR2_VAL 0x00000000
|
|
||||||
#define CFG_GPDR0_VAL 0x0060A800
|
|
||||||
#define CFG_GPDR1_VAL 0x00FF0382
|
|
||||||
#define CFG_GPDR2_VAL 0x0001C000
|
|
||||||
#define CFG_GAFR0_L_VAL 0x98400000
|
|
||||||
#define CFG_GAFR0_U_VAL 0x00002950
|
|
||||||
#define CFG_GAFR1_L_VAL 0x000A9558
|
|
||||||
#define CFG_GAFR1_U_VAL 0x0005AAAA
|
|
||||||
#define CFG_GAFR2_L_VAL 0xA0000000
|
|
||||||
#define CFG_GAFR2_U_VAL 0x00000002
|
|
||||||
|
|
||||||
#define CFG_PSSR_VAL 0x20
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory settings
|
|
||||||
*/
|
|
||||||
#define CFG_MSC0_VAL 0x23F223F2
|
|
||||||
#define CFG_MSC1_VAL 0x3FF1A441
|
|
||||||
#define CFG_MSC2_VAL 0x7FF97FF1
|
|
||||||
#define CFG_MDCNFG_VAL 0x00001AC9
|
|
||||||
#define CFG_MDREFR_VAL 0x00018018
|
|
||||||
#define CFG_MDMRS_VAL 0x00000000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PCMCIA and CF Interfaces
|
|
||||||
*/
|
|
||||||
#define CFG_MECR_VAL 0x00000000
|
|
||||||
#define CFG_MCMEM0_VAL 0x00010504
|
|
||||||
#define CFG_MCMEM1_VAL 0x00010504
|
|
||||||
#define CFG_MCATT0_VAL 0x00010504
|
|
||||||
#define CFG_MCATT1_VAL 0x00010504
|
|
||||||
#define CFG_MCIO0_VAL 0x00004715
|
|
||||||
#define CFG_MCIO1_VAL 0x00004715
|
|
||||||
|
|
||||||
#define _LED 0x08000010
|
|
||||||
#define LED_BLANK 0x08000040
|
|
||||||
|
|
||||||
/*
|
|
||||||
* FLASH and environment organization
|
|
||||||
*/
|
|
||||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
|
||||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
|
||||||
|
|
||||||
/* timeout values are in ticks */
|
|
||||||
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
|
|
||||||
#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
|
|
||||||
|
|
||||||
/* NOTE: many default partitioning schemes assume the kernel starts at the
|
|
||||||
* second sector, not an environment. You have been warned!
|
|
||||||
*/
|
|
||||||
#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
|
|
||||||
|
|
||||||
#define CFG_ENV_IS_IN_FLASH 1
|
|
||||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
|
|
||||||
#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
|
|
||||||
#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* FPGA Offsets
|
* NAND Flash
|
||||||
*/
|
*/
|
||||||
#define WHOAMI_OFFSET 0x00
|
/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
|
||||||
#define HEXLED_OFFSET 0x10
|
#define CONFIG_NEW_NAND_CODE
|
||||||
#define BLANKLED_OFFSET 0x40
|
#define CFG_NAND0_BASE 0x0
|
||||||
#define DISCRETELED_OFFSET 0x40
|
#undef CFG_NAND1_BASE
|
||||||
#define CNFG_SWITCHES_OFFSET 0x50
|
|
||||||
#define USER_SWITCHES_OFFSET 0x60
|
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
|
||||||
#define MISC_WR_OFFSET 0x80
|
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||||
#define MISC_RD_OFFSET 0x90
|
|
||||||
#define INT_MASK_OFFSET 0xC0
|
/* nand timeout values */
|
||||||
#define INT_CLEAR_OFFSET 0xD0
|
#define CFG_NAND_PROG_ERASE_TO 3000
|
||||||
#define GP_OFFSET 0x100
|
#define CFG_NAND_OTHER_TO 100
|
||||||
|
#define CFG_NAND_SENDCMD_RETRY 3
|
||||||
|
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
|
||||||
|
|
||||||
|
/* NAND Timing Parameters (in ns) */
|
||||||
|
#define NAND_TIMING_tCH 10
|
||||||
|
#define NAND_TIMING_tCS 0
|
||||||
|
#define NAND_TIMING_tWH 20
|
||||||
|
#define NAND_TIMING_tWP 40
|
||||||
|
|
||||||
|
#define NAND_TIMING_tRH 20
|
||||||
|
#define NAND_TIMING_tRP 40
|
||||||
|
|
||||||
|
#define NAND_TIMING_tR 11123
|
||||||
|
#define NAND_TIMING_tWHR 100
|
||||||
|
#define NAND_TIMING_tAR 10
|
||||||
|
|
||||||
|
/* NAND debugging */
|
||||||
|
#define CFG_DFC_DEBUG1 /* usefull */
|
||||||
|
#undef CFG_DFC_DEBUG2 /* noisy */
|
||||||
|
#undef CFG_DFC_DEBUG3 /* extremly noisy */
|
||||||
|
|
||||||
|
#define CONFIG_MTD_DEBUG
|
||||||
|
#define CONFIG_MTD_DEBUG_VERBOSE 1
|
||||||
|
|
||||||
|
#define ADDR_COLUMN 1
|
||||||
|
#define ADDR_PAGE 2
|
||||||
|
#define ADDR_COLUMN_PAGE 3
|
||||||
|
|
||||||
|
#define NAND_ChipID_UNKNOWN 0x00
|
||||||
|
#define NAND_MAX_FLOORS 1
|
||||||
|
#define NAND_MAX_CHIPS 1
|
||||||
|
|
||||||
|
#define CFG_NO_FLASH 1
|
||||||
|
|
||||||
|
#define CFG_ENV_IS_IN_NAND 1
|
||||||
|
#define CFG_ENV_OFFSET 0x40000
|
||||||
|
#define CFG_ENV_OFFSET_REDUND 0x44000
|
||||||
|
#define CFG_ENV_SIZE 0x4000
|
||||||
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
#endif /* __CONFIG_H */
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue