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ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7

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Mildly reorder the function so that the reg_file_set*() calls are
in the same place. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2015-07-18 03:15:34 +02:00
parent c336ca3e5b
commit 7c0a9df365
1 changed files with 6 additions and 8 deletions
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14
drivers/ddr/altera/sequencer.c
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@ -2211,19 +2211,17 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
/* update info for sims */
/* Update info for sims */
reg_file_set_group(rw_group);
reg_file_set_stage(CAL_STAGE_VFIFO);
reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
/* USER Determine number of delay taps for each phase tap */
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
/* USER Determine number of delay taps for each phase tap. */
dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
/* update info for sims */
reg_file_set_group(rw_group);
reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
for (d = 0; d <= dtaps_per_ptap; d += 2) {
/*
* In RLDRAMX we may be messing the delay of pins in