mirror of
https://github.com/AsahiLinux/u-boot
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arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Yao Yuan
York Sun
parent
b1f6be5ac8
commit
7ba0261810
5 changed files with 83 additions and 87 deletions
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@ -8,6 +8,7 @@ obj-y += cpu.o
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obj-y += clock.o
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obj-y += timer.o
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obj-y += fsl_epu.o
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obj-y += soc.o
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obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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66
arch/arm/cpu/armv7/ls102xa/soc.c
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66
arch/arm/cpu/armv7/ls102xa/soc.c
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@ -0,0 +1,66 @@
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/ls102xa_soc.h>
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unsigned int get_soc_major_rev(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int svr, major;
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svr = in_be32(&gur->svr);
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major = SVR_MAJ(svr);
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return major;
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}
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int arch_soc_init(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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unsigned int major;
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#ifdef CONFIG_FSL_QSPI
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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#ifdef CONFIG_FSL_DCU_FB
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out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
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#endif
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/* Configure Little endian for SAI, ASRC and SPDIF */
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out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
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/*
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* Enable snoop requests and DVM message requests for
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* Slave insterface S4 (A7 core cluster)
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*/
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out_le32(&cci->slave[4].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0) {
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/*
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* Set CCI-400 Slave interface S1, S2 Shareable Override
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* Register All transactions are treated as non-shareable
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*/
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out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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/* Workaround for the issue that DDR could not respond to
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* barrier transaction which is generated by executing DSB/ISB
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* instruction. Set CCI-400 control override register to
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* terminate the barrier transaction. After DDR is initialized,
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* allow barrier transaction to DDR again */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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}
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return 0;
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}
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12
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
Normal file
12
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
Normal file
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@ -0,0 +1,12 @@
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_LS102XA_SOC_H
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#define __FSL_LS102XA_SOC_H
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unsigned int get_soc_major_rev(void);
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int arch_soc_init(void);
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#endif /* __FSL_LS102XA_SOC_H */
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@ -11,6 +11,7 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_sata.h>
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#include <hwconfig.h>
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@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void)
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return 66666666;
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}
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unsigned int get_soc_major_rev(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int svr, major;
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svr = in_be32(&gur->svr);
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major = SVR_MAJ(svr);
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return major;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis)
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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unsigned int major;
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#ifdef CONFIG_TSEC_ENET
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/* clear BD & FR bits for BE BD's and frame data */
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@ -205,40 +193,7 @@ int board_early_init_f(void)
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init_early_memctl_regs();
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#endif
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#ifdef CONFIG_FSL_QSPI
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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#ifdef CONFIG_FSL_DCU_FB
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out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
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#endif
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/* Configure Little endian for SAI, ASRC and SPDIF */
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out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
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/*
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* Enable snoop requests and DVM message requests for
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* Slave insterface S4 (A7 core cluster)
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*/
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out_le32(&cci->slave[4].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0) {
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/*
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* Set CCI-400 Slave interface S1, S2 Shareable Override
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* Register All transactions are treated as non-shareable
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*/
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out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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/* Workaround for the issue that DDR could not respond to
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* barrier transaction which is generated by executing DSB/ISB
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* instruction. Set CCI-400 control override register to
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* terminate the barrier transaction. After DDR is initialized,
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* allow barrier transaction to DDR again */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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}
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arch_soc_init();
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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@ -12,6 +12,7 @@
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_sata.h>
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#include <hwconfig.h>
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#include <mmc.h>
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@ -138,17 +139,6 @@ int checkboard(void)
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return 0;
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}
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unsigned int get_soc_major_rev(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int svr, major;
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svr = in_be32(&gur->svr);
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major = SVR_MAJ(svr);
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return major;
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}
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void ddrmc_init(void)
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{
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struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
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@ -394,8 +384,6 @@ conflict:
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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unsigned int major;
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#ifdef CONFIG_TSEC_ENET
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/* clear BD & FR bits for BE BD's and frame data */
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@ -407,33 +395,7 @@ int board_early_init_f(void)
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init_early_memctl_regs();
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#endif
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#ifdef CONFIG_FSL_DCU_FB
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out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
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#endif
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#ifdef CONFIG_FSL_QSPI
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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/* Configure Little endian for SAI, ASRC and SPDIF */
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out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
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/*
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* Enable snoop requests and DVM message requests for
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* Slave insterface S4 (A7 core cluster)
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*/
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out_le32(&cci->slave[4].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0) {
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/*
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* Set CCI-400 Slave interface S1, S2 Shareable Override
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* Register All transactions are treated as non-shareable
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*/
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out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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}
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arch_soc_init();
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot()) {
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