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https://github.com/AsahiLinux/u-boot
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arm: stm32mp: bsec: add permanent lock support in bsec driver
Add BSEC lock access (read / write) at 0xC0000000 offset of misc driver.
The write access only available for Trusted boot mode, based on new
SMC STM32_SMC_WRLOCK_OTP.
With the fuse command, the permanent lock status is accessed with
0x10000000 offset (0xC0000000 - 0x8000000 for OTP sense/program
divided by u32 size), for example:
Read lock status of fuse 57 (0x39)
STM32MP> fuse sense 0 0x10000039 1
Sensing bank 0:
Word 0x10000039: 00000000
Set permanent lock of fuse 57 (0x39)
STM32MP> fuse prog 0 0x10000039 1
Sensing bank 0:
Word 0x10000039: 00000000
WARNING: the OTP lock is updated only after reboot
WARING: Programming lock or fuses is an irreversible operation!
This may brick your system.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrick Delaunay
parent
df2d1b8fc4
commit
7ae22d7278
5 changed files with 96 additions and 44 deletions
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@ -12,8 +12,6 @@
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#include <linux/iopoll.h>
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#define BSEC_OTP_MAX_VALUE 95
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#ifndef CONFIG_STM32MP1_TRUSTED
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#define BSEC_TIMEOUT_US 10000
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/* BSEC REGISTER OFFSET (base relative) */
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@ -24,9 +22,10 @@
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#define BSEC_OTP_LOCK_OFF 0x010
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#define BSEC_DISTURBED_OFF 0x01C
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#define BSEC_ERROR_OFF 0x034
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#define BSEC_SPLOCK_OFF 0x064 /* Program safmem sticky lock */
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#define BSEC_SWLOCK_OFF 0x07C /* write in OTP sticky lock */
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#define BSEC_SRLOCK_OFF 0x094 /* shadowing sticky lock */
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#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
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#define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */
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#define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */
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#define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */
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#define BSEC_OTP_DATA_OFF 0x200
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/* BSEC_CONFIGURATION Register MASK */
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@ -52,6 +51,24 @@
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*/
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#define BSEC_LOCK_PROGRAM 0x04
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/**
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* bsec_lock() - manage lock for each type SR/SP/SW
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* @address: address of bsec IP register
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
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* Return: true if locked else false
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*/
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static bool bsec_read_lock(u32 address, u32 otp)
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{
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u32 bit;
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u32 bank;
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bit = 1 << (otp & OTP_LOCK_MASK);
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bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
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return !!(readl(address + bank) & bit);
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}
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#ifndef CONFIG_STM32MP1_TRUSTED
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/**
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* bsec_check_error() - Check status of one otp
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* @base: base address of bsec IP
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@ -74,23 +91,6 @@ static u32 bsec_check_error(u32 base, u32 otp)
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return 0;
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}
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/**
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* bsec_lock() - manage lock for each type SR/SP/SW
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* @address: address of bsec IP register
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* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
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* Return: true if locked else false
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*/
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static bool bsec_read_lock(u32 address, u32 otp)
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{
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u32 bit;
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u32 bank;
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bit = 1 << (otp & OTP_LOCK_MASK);
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bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
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return !!(readl(address + bank) & bit);
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}
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/**
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* bsec_read_SR_lock() - read SR lock (Shadowing)
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* @base: base address of bsec IP
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@ -324,6 +324,16 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
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#endif
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}
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static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
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{
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struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
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/* return OTP permanent write lock status */
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*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
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return 0;
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}
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static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
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{
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#ifdef CONFIG_STM32MP1_TRUSTED
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@ -350,17 +360,36 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
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#endif
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}
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static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
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{
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#ifdef CONFIG_STM32MP1_TRUSTED
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if (val == 1)
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return stm32_smc_exec(STM32_SMC_BSEC,
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STM32_SMC_WRLOCK_OTP,
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otp, 0);
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if (val == 0)
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return 0; /* nothing to do */
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return -EINVAL;
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#else
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return -ENOTSUPP;
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#endif
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}
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static int stm32mp_bsec_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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int ret;
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int i;
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bool shadow = true;
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bool shadow = true, lock = false;
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int nb_otp = size / sizeof(u32);
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int otp;
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unsigned int offs = offset;
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if (offs >= STM32_BSEC_OTP_OFFSET) {
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if (offs >= STM32_BSEC_LOCK_OFFSET) {
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offs -= STM32_BSEC_LOCK_OFFSET;
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lock = true;
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} else if (offs >= STM32_BSEC_OTP_OFFSET) {
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offs -= STM32_BSEC_OTP_OFFSET;
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shadow = false;
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}
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@ -373,7 +402,9 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset,
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for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
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u32 *addr = &((u32 *)buf)[i - otp];
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if (shadow)
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if (lock)
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ret = stm32mp_bsec_read_lock(dev, addr, i);
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else if (shadow)
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ret = stm32mp_bsec_read_shadow(dev, addr, i);
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else
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ret = stm32mp_bsec_read_otp(dev, addr, i);
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@ -392,12 +423,15 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset,
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{
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int ret = 0;
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int i;
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bool shadow = true;
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bool shadow = true, lock = false;
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int nb_otp = size / sizeof(u32);
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int otp;
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unsigned int offs = offset;
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if (offs >= STM32_BSEC_OTP_OFFSET) {
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if (offs >= STM32_BSEC_LOCK_OFFSET) {
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offs -= STM32_BSEC_LOCK_OFFSET;
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lock = true;
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} else if (offs >= STM32_BSEC_OTP_OFFSET) {
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offs -= STM32_BSEC_OTP_OFFSET;
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shadow = false;
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}
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@ -410,7 +444,9 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset,
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for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
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u32 *val = &((u32 *)buf)[i - otp];
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if (shadow)
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if (lock)
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ret = stm32mp_bsec_write_lock(dev, *val, i);
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else if (shadow)
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ret = stm32mp_bsec_write_shadow(dev, *val, i);
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else
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ret = stm32mp_bsec_write_otp(dev, *val, i);
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@ -61,12 +61,6 @@
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#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
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#define BOOTROM_INSTANCE_SHIFT 16
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/* BSEC OTP index */
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#define BSEC_OTP_RPN 1
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#define BSEC_OTP_SERIAL 13
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#define BSEC_OTP_PKG 16
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#define BSEC_OTP_MAC 57
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/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
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#define RPN_SHIFT 0
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#define RPN_MASK GENMASK(7, 0)
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@ -119,7 +119,14 @@ enum forced_boot_mode {
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#define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
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#define STM32_BSEC_OTP_OFFSET 0x80000000
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#define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4)
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#define STM32_BSEC_LOCK_OFFSET 0xC0000000
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#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
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/* BSEC OTP index */
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#define BSEC_OTP_RPN 1
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#define BSEC_OTP_SERIAL 13
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#define BSEC_OTP_PKG 16
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#define BSEC_OTP_MAC 57
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#define BSEC_OTP_BOARD 59
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#endif /* __ASSEMBLY__*/
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@ -27,6 +27,7 @@
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#define STM32_SMC_READ_OTP 0x04
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#define STM32_SMC_READ_ALL 0x05
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#define STM32_SMC_WRITE_ALL 0x06
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#define STM32_SMC_WRLOCK_OTP 0x07
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/* SMC error codes */
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#define STM32_SMC_OK 0x0
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@ -416,20 +416,26 @@ For STMicroelectonics board, it is retrieved in STM32MP15x OTP :
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- OTP_58[15:0] = MAC_ADDR[47:32]
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To program a MAC address on virgin OTP words above, you can use the fuse command
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on bank 0 to access to internal OTP:
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on bank 0 to access to internal OTP and lock them:
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Prerequisite: check if a MAC address isn't yet programmed in OTP
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1) check OTP: their value must be equal to 0
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1) check OTP: their value must be equal to 0::
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STM32MP> fuse sense 0 57 2
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Sensing bank 0:
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Word 0x00000039: 00000000 00000000
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STM32MP> fuse sense 0 57 2
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Sensing bank 0:
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Word 0x00000039: 00000000 00000000
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2) check environment variable
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2) check environment variable::
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STM32MP> env print ethaddr
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## Error: "ethaddr" not defined
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STM32MP> env print ethaddr
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## Error: "ethaddr" not defined
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3) check lock status of fuse 57 & 58 (at 0x39, 0=unlocked, 1=locked)::
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STM32MP> fuse sense 0 0x10000039 2
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Sensing bank 0:
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Word 0x10000039: 00000000 00000000
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Example to set mac address "12:34:56:78:9a:bc"
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@ -443,11 +449,19 @@ Example to set mac address "12:34:56:78:9a:bc"
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Sensing bank 0:
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Word 0x00000039: 78563412 0000bc9a
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3) next REBOOT, in the trace::
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3) Lock OTP::
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STM32MP> fuse prog 0 0x10000039 1 1
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STM32MP> fuse sense 0 0x10000039 2
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Sensing bank 0:
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Word 0x10000039: 00000001 00000001
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4) next REBOOT, in the trace::
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### Setting environment from OTP MAC address = "12:34:56:78:9a:bc"
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4) check env update::
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5) check env update::
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STM32MP> env print ethaddr
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ethaddr=12:34:56:78:9a:bc
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