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mtd: rawnand: stm32_fmc2: cosmetic change to use nfc instead of fmc2 where relevant
This patch renames functions and local variables. This cleanup is done to get all functions starting by stm32_fmc2_nfc in the FMC2 raw NAND driver when all functions will start by stm32_fmc2_ebi in the FMC2 EBI driver. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Christophe Kerello
Patrice Chotard
parent
4a470044e1
commit
7a6b328841
1 changed files with 131 additions and 132 deletions
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@ -181,12 +181,12 @@ static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
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return container_of(base, struct stm32_fmc2_nfc, base);
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}
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static void stm32_fmc2_timings_init(struct nand_chip *chip)
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static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
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struct stm32_fmc2_timings *timings = &nand->timings;
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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u32 pcr = readl(nfc->io_base + FMC2_PCR);
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u32 pmem, patt;
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/* Set tclr/tar timings */
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@ -207,15 +207,15 @@ static void stm32_fmc2_timings_init(struct nand_chip *chip)
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patt |= FMC2_PATT_ATTHOLD(timings->thold_att);
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patt |= FMC2_PATT_ATTHIZ(timings->thiz);
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writel(pcr, fmc2->io_base + FMC2_PCR);
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writel(pmem, fmc2->io_base + FMC2_PMEM);
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writel(patt, fmc2->io_base + FMC2_PATT);
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writel(pcr, nfc->io_base + FMC2_PCR);
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writel(pmem, nfc->io_base + FMC2_PMEM);
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writel(patt, nfc->io_base + FMC2_PATT);
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}
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static void stm32_fmc2_setup(struct nand_chip *chip)
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static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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u32 pcr = readl(nfc->io_base + FMC2_PCR);
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/* Configure ECC algorithm (default configuration is Hamming) */
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pcr &= ~FMC2_PCR_ECCALG;
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@ -236,95 +236,96 @@ static void stm32_fmc2_setup(struct nand_chip *chip)
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pcr &= ~FMC2_PCR_ECCSS_MASK;
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pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
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writel(pcr, fmc2->io_base + FMC2_PCR);
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writel(pcr, nfc->io_base + FMC2_PCR);
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}
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static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr)
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static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
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if (chipnr < 0 || chipnr >= nand->ncs)
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return;
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if (nand->cs_used[chipnr] == fmc2->cs_sel)
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if (nand->cs_used[chipnr] == nfc->cs_sel)
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return;
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fmc2->cs_sel = nand->cs_used[chipnr];
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chip->IO_ADDR_R = fmc2->data_base[fmc2->cs_sel];
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chip->IO_ADDR_W = fmc2->data_base[fmc2->cs_sel];
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nfc->cs_sel = nand->cs_used[chipnr];
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chip->IO_ADDR_R = nfc->data_base[nfc->cs_sel];
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chip->IO_ADDR_W = nfc->data_base[nfc->cs_sel];
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stm32_fmc2_setup(chip);
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stm32_fmc2_timings_init(chip);
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stm32_fmc2_nfc_setup(chip);
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stm32_fmc2_nfc_timings_init(chip);
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}
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static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
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static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc,
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bool set)
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{
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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u32 pcr = readl(nfc->io_base + FMC2_PCR);
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pcr &= ~FMC2_PCR_PWID_MASK;
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if (set)
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pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
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writel(pcr, fmc2->io_base + FMC2_PCR);
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writel(pcr, nfc->io_base + FMC2_PCR);
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}
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static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
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static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
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{
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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u32 pcr = readl(nfc->io_base + FMC2_PCR);
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pcr &= ~FMC2_PCR_ECCEN;
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if (enable)
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pcr |= FMC2_PCR_ECCEN;
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writel(pcr, fmc2->io_base + FMC2_PCR);
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writel(pcr, nfc->io_base + FMC2_PCR);
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}
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static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
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static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
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{
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writel(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
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writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
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}
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static void stm32_fmc2_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE) {
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writeb(cmd, fmc2->cmd_base[fmc2->cs_sel]);
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writeb(cmd, nfc->cmd_base[nfc->cs_sel]);
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return;
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}
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writeb(cmd, fmc2->addr_base[fmc2->cs_sel]);
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writeb(cmd, nfc->addr_base[nfc->cs_sel]);
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}
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/*
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* Enable ECC logic and reset syndrome/parity bits previously calculated
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* Syndrome/parity bits is cleared by setting the ECCEN bit to 0
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*/
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static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode)
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static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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stm32_fmc2_set_ecc(fmc2, false);
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stm32_fmc2_nfc_set_ecc(nfc, false);
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if (chip->ecc.strength != FMC2_ECC_HAM) {
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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u32 pcr = readl(nfc->io_base + FMC2_PCR);
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if (mode == NAND_ECC_WRITE)
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pcr |= FMC2_PCR_WEN;
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else
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pcr &= ~FMC2_PCR_WEN;
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writel(pcr, fmc2->io_base + FMC2_PCR);
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writel(pcr, nfc->io_base + FMC2_PCR);
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stm32_fmc2_clear_bch_irq(fmc2);
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stm32_fmc2_nfc_clear_bch_irq(nfc);
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}
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stm32_fmc2_set_ecc(fmc2, true);
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stm32_fmc2_nfc_set_ecc(nfc, true);
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}
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/*
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@ -332,34 +333,34 @@ static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode)
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* ECC is 3 bytes for 512 bytes of data (supports error correction up to
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* max of 1-bit)
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*/
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static int stm32_fmc2_ham_calculate(struct mtd_info *mtd, const u8 *data,
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u8 *ecc)
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static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data,
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u8 *ecc)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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u32 heccr, sr;
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int ret;
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ret = readl_poll_timeout(fmc2->io_base + FMC2_SR, sr,
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ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
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sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
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if (ret < 0) {
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pr_err("Ham timeout\n");
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return ret;
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}
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heccr = readl(fmc2->io_base + FMC2_HECCR);
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heccr = readl(nfc->io_base + FMC2_HECCR);
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ecc[0] = heccr;
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ecc[1] = heccr >> 8;
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ecc[2] = heccr >> 16;
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stm32_fmc2_set_ecc(fmc2, false);
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stm32_fmc2_nfc_set_ecc(nfc, false);
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return 0;
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}
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static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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u8 bit_position = 0, b0, b1, b2;
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u32 byte_addr = 0, b;
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@ -416,16 +417,16 @@ static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat,
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* max of 4-bit/8-bit)
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*/
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static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data,
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u8 *ecc)
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static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data,
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u8 *ecc)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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u32 bchpbr, bchisr;
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int ret;
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/* Wait until the BCH code is ready */
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ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
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ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
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bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
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if (ret < 0) {
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pr_err("Bch timeout\n");
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@ -433,13 +434,13 @@ static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data,
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}
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/* Read parity bits */
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bchpbr = readl(fmc2->io_base + FMC2_BCHPBR1);
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bchpbr = readl(nfc->io_base + FMC2_BCHPBR1);
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ecc[0] = bchpbr;
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ecc[1] = bchpbr >> 8;
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ecc[2] = bchpbr >> 16;
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ecc[3] = bchpbr >> 24;
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bchpbr = readl(fmc2->io_base + FMC2_BCHPBR2);
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bchpbr = readl(nfc->io_base + FMC2_BCHPBR2);
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ecc[4] = bchpbr;
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ecc[5] = bchpbr >> 8;
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ecc[6] = bchpbr >> 16;
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@ -447,46 +448,46 @@ static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data,
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if (chip->ecc.strength == FMC2_ECC_BCH8) {
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ecc[7] = bchpbr >> 24;
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bchpbr = readl(fmc2->io_base + FMC2_BCHPBR3);
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bchpbr = readl(nfc->io_base + FMC2_BCHPBR3);
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ecc[8] = bchpbr;
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ecc[9] = bchpbr >> 8;
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ecc[10] = bchpbr >> 16;
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ecc[11] = bchpbr >> 24;
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bchpbr = readl(fmc2->io_base + FMC2_BCHPBR4);
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bchpbr = readl(nfc->io_base + FMC2_BCHPBR4);
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ecc[12] = bchpbr;
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}
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stm32_fmc2_set_ecc(fmc2, false);
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stm32_fmc2_nfc_set_ecc(nfc, false);
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return 0;
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}
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static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
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u16 pos[8];
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int i, ret, den, eccsize = chip->ecc.size;
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unsigned int nb_errs = 0;
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/* Wait until the decoding error is ready */
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ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
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ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
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bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
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if (ret < 0) {
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pr_err("Bch timeout\n");
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return ret;
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}
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bchdsr0 = readl(fmc2->io_base + FMC2_BCHDSR0);
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bchdsr1 = readl(fmc2->io_base + FMC2_BCHDSR1);
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bchdsr2 = readl(fmc2->io_base + FMC2_BCHDSR2);
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bchdsr3 = readl(fmc2->io_base + FMC2_BCHDSR3);
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bchdsr4 = readl(fmc2->io_base + FMC2_BCHDSR4);
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bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0);
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bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1);
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bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2);
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bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3);
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bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4);
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stm32_fmc2_set_ecc(fmc2, false);
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stm32_fmc2_nfc_set_ecc(nfc, false);
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/* No errors found */
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if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
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@ -516,9 +517,9 @@ static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat,
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return nb_errs;
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}
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static int stm32_fmc2_read_page(struct mtd_info *mtd,
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struct nand_chip *chip, u8 *buf,
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int oob_required, int page)
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static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd,
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struct nand_chip *chip, u8 *buf,
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int oob_required, int page)
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{
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int i, s, stat, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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@ -567,13 +568,13 @@ static int stm32_fmc2_read_page(struct mtd_info *mtd,
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return max_bitflips;
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}
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static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
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static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
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{
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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u32 bcr1 = readl(fmc2->io_base + FMC2_BCR1);
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u32 pcr = readl(nfc->io_base + FMC2_PCR);
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u32 bcr1 = readl(nfc->io_base + FMC2_BCR1);
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/* Set CS used to undefined */
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fmc2->cs_sel = -1;
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nfc->cs_sel = -1;
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/* Enable wait feature and nand flash memory bank */
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pcr |= FMC2_PCR_PWAITEN;
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@ -603,19 +604,19 @@ static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
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/* Enable FMC2 controller */
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bcr1 |= FMC2_BCR1_FMC2EN;
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||||
|
||||
writel(bcr1, fmc2->io_base + FMC2_BCR1);
|
||||
writel(pcr, fmc2->io_base + FMC2_PCR);
|
||||
writel(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM);
|
||||
writel(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
|
||||
writel(bcr1, nfc->io_base + FMC2_BCR1);
|
||||
writel(pcr, nfc->io_base + FMC2_PCR);
|
||||
writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
|
||||
writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
|
||||
}
|
||||
|
||||
static void stm32_fmc2_calc_timings(struct nand_chip *chip,
|
||||
const struct nand_sdr_timings *sdrt)
|
||||
static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
|
||||
const struct nand_sdr_timings *sdrt)
|
||||
{
|
||||
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
|
||||
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
|
||||
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
|
||||
struct stm32_fmc2_timings *tims = &nand->timings;
|
||||
unsigned long hclk = clk_get_rate(&fmc2->clk);
|
||||
unsigned long hclk = clk_get_rate(&nfc->clk);
|
||||
unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
|
||||
unsigned long timing, tar, tclr, thiz, twait;
|
||||
unsigned long tset_mem, tset_att, thold_mem, thold_att;
|
||||
|
|
@ -739,29 +740,28 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip,
|
|||
tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
|
||||
}
|
||||
|
||||
static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr,
|
||||
const struct nand_data_interface *conf)
|
||||
static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr,
|
||||
const struct nand_data_interface *cf)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
const struct nand_sdr_timings *sdrt;
|
||||
|
||||
sdrt = nand_get_sdr_timings(conf);
|
||||
sdrt = nand_get_sdr_timings(cf);
|
||||
if (IS_ERR(sdrt))
|
||||
return PTR_ERR(sdrt);
|
||||
|
||||
if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
|
||||
return 0;
|
||||
|
||||
stm32_fmc2_calc_timings(chip, sdrt);
|
||||
|
||||
stm32_fmc2_timings_init(chip);
|
||||
stm32_fmc2_nfc_calc_timings(chip, sdrt);
|
||||
stm32_fmc2_nfc_timings_init(chip);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
|
||||
static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
|
||||
{
|
||||
chip->ecc.hwctl = stm32_fmc2_hwctl;
|
||||
chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
|
||||
|
||||
/*
|
||||
* Specific callbacks to read/write a page depending on
|
||||
|
|
@ -769,17 +769,17 @@ static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
|
|||
*/
|
||||
if (chip->ecc.strength == FMC2_ECC_HAM) {
|
||||
/* Hamming is used */
|
||||
chip->ecc.calculate = stm32_fmc2_ham_calculate;
|
||||
chip->ecc.correct = stm32_fmc2_ham_correct;
|
||||
chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
|
||||
chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
|
||||
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
|
||||
chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
|
||||
return;
|
||||
}
|
||||
|
||||
/* BCH is used */
|
||||
chip->ecc.read_page = stm32_fmc2_read_page;
|
||||
chip->ecc.calculate = stm32_fmc2_bch_calculate;
|
||||
chip->ecc.correct = stm32_fmc2_bch_correct;
|
||||
chip->ecc.read_page = stm32_fmc2_nfc_read_page;
|
||||
chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
|
||||
chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
|
||||
|
||||
if (chip->ecc.strength == FMC2_ECC_BCH8)
|
||||
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
|
||||
|
|
@ -787,7 +787,7 @@ static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
|
|||
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
|
||||
}
|
||||
|
||||
static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
|
||||
static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
|
||||
{
|
||||
/* Hamming */
|
||||
if (strength == FMC2_ECC_HAM)
|
||||
|
|
@ -801,14 +801,13 @@ static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
|
|||
return 8;
|
||||
}
|
||||
|
||||
NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
|
||||
NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
|
||||
FMC2_ECC_STEP_SIZE,
|
||||
FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
|
||||
|
||||
static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
|
||||
ofnode node)
|
||||
static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node)
|
||||
{
|
||||
struct stm32_fmc2_nand *nand = &fmc2->nand;
|
||||
struct stm32_fmc2_nand *nand = &nfc->nand;
|
||||
u32 cs[FMC2_MAX_CE];
|
||||
int ret, i;
|
||||
|
||||
|
|
@ -834,13 +833,13 @@ static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (fmc2->cs_assigned & BIT(cs[i])) {
|
||||
if (nfc->cs_assigned & BIT(cs[i])) {
|
||||
pr_err("Cs already assigned: %d\n",
|
||||
nand->cs_used[i]);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
fmc2->cs_assigned |= BIT(cs[i]);
|
||||
nfc->cs_assigned |= BIT(cs[i]);
|
||||
nand->cs_used[i] = cs[i];
|
||||
}
|
||||
|
||||
|
|
@ -849,8 +848,8 @@ static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_fmc2_parse_dt(struct udevice *dev,
|
||||
struct stm32_fmc2_nfc *fmc2)
|
||||
static int stm32_fmc2_nfc_parse_dt(struct udevice *dev,
|
||||
struct stm32_fmc2_nfc *nfc)
|
||||
{
|
||||
ofnode child;
|
||||
int ret, nchips = 0;
|
||||
|
|
@ -869,7 +868,7 @@ static int stm32_fmc2_parse_dt(struct udevice *dev,
|
|||
}
|
||||
|
||||
dev_for_each_subnode(child, dev) {
|
||||
ret = stm32_fmc2_parse_child(fmc2, child);
|
||||
ret = stm32_fmc2_nfc_parse_child(nfc, child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -877,10 +876,10 @@ static int stm32_fmc2_parse_dt(struct udevice *dev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_fmc2_probe(struct udevice *dev)
|
||||
static int stm32_fmc2_nfc_probe(struct udevice *dev)
|
||||
{
|
||||
struct stm32_fmc2_nfc *fmc2 = dev_get_priv(dev);
|
||||
struct stm32_fmc2_nand *nand = &fmc2->nand;
|
||||
struct stm32_fmc2_nfc *nfc = dev_get_priv(dev);
|
||||
struct stm32_fmc2_nand *nand = &nfc->nand;
|
||||
struct nand_chip *chip = &nand->chip;
|
||||
struct mtd_info *mtd = &chip->mtd;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
|
|
@ -889,10 +888,10 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
int oob_index, chip_cs, mem_region, ret;
|
||||
unsigned int i;
|
||||
|
||||
spin_lock_init(&fmc2->controller.lock);
|
||||
init_waitqueue_head(&fmc2->controller.wq);
|
||||
spin_lock_init(&nfc->controller.lock);
|
||||
init_waitqueue_head(&nfc->controller.wq);
|
||||
|
||||
ret = stm32_fmc2_parse_dt(dev, fmc2);
|
||||
ret = stm32_fmc2_nfc_parse_dt(dev, nfc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -902,11 +901,11 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
pr_err("Resource io_base not found");
|
||||
return ret;
|
||||
}
|
||||
fmc2->io_base = (void __iomem *)resource.start;
|
||||
nfc->io_base = (void __iomem *)resource.start;
|
||||
|
||||
for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
|
||||
chip_cs++, mem_region += 3) {
|
||||
if (!(fmc2->cs_assigned & BIT(chip_cs)))
|
||||
if (!(nfc->cs_assigned & BIT(chip_cs)))
|
||||
continue;
|
||||
|
||||
ret = dev_read_resource(dev, mem_region, &resource);
|
||||
|
|
@ -915,7 +914,7 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
chip_cs);
|
||||
return ret;
|
||||
}
|
||||
fmc2->data_base[chip_cs] = (void __iomem *)resource.start;
|
||||
nfc->data_base[chip_cs] = (void __iomem *)resource.start;
|
||||
|
||||
ret = dev_read_resource(dev, mem_region + 1, &resource);
|
||||
if (ret) {
|
||||
|
|
@ -923,7 +922,7 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
chip_cs);
|
||||
return ret;
|
||||
}
|
||||
fmc2->cmd_base[chip_cs] = (void __iomem *)resource.start;
|
||||
nfc->cmd_base[chip_cs] = (void __iomem *)resource.start;
|
||||
|
||||
ret = dev_read_resource(dev, mem_region + 2, &resource);
|
||||
if (ret) {
|
||||
|
|
@ -931,15 +930,15 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
chip_cs);
|
||||
return ret;
|
||||
}
|
||||
fmc2->addr_base[chip_cs] = (void __iomem *)resource.start;
|
||||
nfc->addr_base[chip_cs] = (void __iomem *)resource.start;
|
||||
}
|
||||
|
||||
/* Enable the clock */
|
||||
ret = clk_get_by_index(dev, 0, &fmc2->clk);
|
||||
ret = clk_get_by_index(dev, 0, &nfc->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(&fmc2->clk);
|
||||
ret = clk_enable(&nfc->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -951,12 +950,12 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
reset_deassert(&reset);
|
||||
}
|
||||
|
||||
stm32_fmc2_init(fmc2);
|
||||
stm32_fmc2_nfc_init(nfc);
|
||||
|
||||
chip->controller = &fmc2->base;
|
||||
chip->select_chip = stm32_fmc2_select_chip;
|
||||
chip->setup_data_interface = stm32_fmc2_setup_interface;
|
||||
chip->cmd_ctrl = stm32_fmc2_cmd_ctrl;
|
||||
chip->controller = &nfc->base;
|
||||
chip->select_chip = stm32_fmc2_nfc_select_chip;
|
||||
chip->setup_data_interface = stm32_fmc2_nfc_setup_interface;
|
||||
chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl;
|
||||
chip->chip_delay = FMC2_RB_DELAY_US;
|
||||
chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
|
||||
NAND_USE_BOUNCE_BUFFER;
|
||||
|
|
@ -982,7 +981,7 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = nand_check_ecc_caps(chip, &stm32_fmc2_ecc_caps,
|
||||
ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
|
||||
mtd->oobsize - FMC2_BBM_LEN);
|
||||
if (ret) {
|
||||
pr_err("No valid ECC settings set\n");
|
||||
|
|
@ -992,10 +991,10 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
if (chip->bbt_options & NAND_BBT_USE_FLASH)
|
||||
chip->bbt_options |= NAND_BBT_NO_OOB;
|
||||
|
||||
stm32_fmc2_nand_callbacks_setup(chip);
|
||||
stm32_fmc2_nfc_nand_callbacks_setup(chip);
|
||||
|
||||
/* Define ECC layout */
|
||||
ecclayout = &fmc2->ecclayout;
|
||||
ecclayout = &nfc->ecclayout;
|
||||
ecclayout->eccbytes = chip->ecc.bytes *
|
||||
(mtd->writesize / chip->ecc.size);
|
||||
oob_index = FMC2_BBM_LEN;
|
||||
|
|
@ -1006,7 +1005,7 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
chip->ecc.layout = ecclayout;
|
||||
|
||||
if (chip->options & NAND_BUSWIDTH_16)
|
||||
stm32_fmc2_set_buswidth_16(fmc2, true);
|
||||
stm32_fmc2_nfc_set_buswidth_16(nfc, true);
|
||||
|
||||
ret = nand_scan_tail(mtd);
|
||||
if (ret)
|
||||
|
|
@ -1015,16 +1014,16 @@ static int stm32_fmc2_probe(struct udevice *dev)
|
|||
return nand_register(0, mtd);
|
||||
}
|
||||
|
||||
static const struct udevice_id stm32_fmc2_match[] = {
|
||||
static const struct udevice_id stm32_fmc2_nfc_match[] = {
|
||||
{ .compatible = "st,stm32mp15-fmc2" },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stm32_fmc2_nand) = {
|
||||
.name = "stm32_fmc2_nand",
|
||||
U_BOOT_DRIVER(stm32_fmc2_nfc) = {
|
||||
.name = "stm32_fmc2_nfc",
|
||||
.id = UCLASS_MTD,
|
||||
.of_match = stm32_fmc2_match,
|
||||
.probe = stm32_fmc2_probe,
|
||||
.of_match = stm32_fmc2_nfc_match,
|
||||
.probe = stm32_fmc2_nfc_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc),
|
||||
};
|
||||
|
||||
|
|
@ -1034,9 +1033,9 @@ void board_nand_init(void)
|
|||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MTD,
|
||||
DM_GET_DRIVER(stm32_fmc2_nand),
|
||||
DM_GET_DRIVER(stm32_fmc2_nfc),
|
||||
&dev);
|
||||
if (ret && ret != -ENODEV)
|
||||
pr_err("Failed to initialize STM32 FMC2 NAND controller. (error %d)\n",
|
||||
pr_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
|
||||
ret);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue