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sunxi: sun4i: improve cpu clock selection method

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clock_set_pll1 would pick the next highest available cpu clock speed if
a value not in the pre defined table was selected. this potentially
results in overclocking the soc.

reverse the selection method so that we select the next lowest speed
and add the missing 912Mhz setting that's requested by sun7i which also
uses the sun4i clock code.

Signed-off-by: Iain Paton <ipaton0@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Iain Paton 2015-03-28 10:25:28 +00:00 committed by Hans de Goede
parent 246e3b8787
commit 7a140117ef
1 changed files with 19 additions and 16 deletions
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35
arch/arm/cpu/armv7/sunxi/clock_sun4i.c
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@ -100,22 +100,23 @@ static struct {
unsigned int freq; unsigned int freq;
} pll1_para[] = { } pll1_para[] = {
/* This array must be ordered by frequency. */ /* This array must be ordered by frequency. */
{ PLL1_CFG(16, 0, 0, 0), 384000000 },
{ PLL1_CFG(16, 1, 0, 0), 768000000 },
{ PLL1_CFG(20, 1, 0, 0), 960000000 },
{ PLL1_CFG(21, 1, 0, 0), 1008000000},
{ PLL1_CFG(22, 1, 0, 0), 1056000000},
{ PLL1_CFG(23, 1, 0, 0), 1104000000},
{ PLL1_CFG(24, 1, 0, 0), 1152000000},
{ PLL1_CFG(25, 1, 0, 0), 1200000000},
{ PLL1_CFG(26, 1, 0, 0), 1248000000},
{ PLL1_CFG(27, 1, 0, 0), 1296000000},
{ PLL1_CFG(28, 1, 0, 0), 1344000000},
{ PLL1_CFG(29, 1, 0, 0), 1392000000},
{ PLL1_CFG(30, 1, 0, 0), 1440000000},
{ PLL1_CFG(31, 1, 0, 0), 1488000000}, { PLL1_CFG(31, 1, 0, 0), 1488000000},
/* Final catchall entry */ { PLL1_CFG(30, 1, 0, 0), 1440000000},
{ PLL1_CFG(31, 1, 0, 0), ~0}, { PLL1_CFG(29, 1, 0, 0), 1392000000},
{ PLL1_CFG(28, 1, 0, 0), 1344000000},
{ PLL1_CFG(27, 1, 0, 0), 1296000000},
{ PLL1_CFG(26, 1, 0, 0), 1248000000},
{ PLL1_CFG(25, 1, 0, 0), 1200000000},
{ PLL1_CFG(24, 1, 0, 0), 1152000000},
{ PLL1_CFG(23, 1, 0, 0), 1104000000},
{ PLL1_CFG(22, 1, 0, 0), 1056000000},
{ PLL1_CFG(21, 1, 0, 0), 1008000000},
{ PLL1_CFG(20, 1, 0, 0), 960000000 },
{ PLL1_CFG(19, 1, 0, 0), 912000000 },
{ PLL1_CFG(16, 1, 0, 0), 768000000 },
/* Final catchall entry 384MHz*/
{ PLL1_CFG(16, 0, 0, 0), 0 },
}; };
void clock_set_pll1(unsigned int hz) void clock_set_pll1(unsigned int hz)
@ -126,10 +127,12 @@ void clock_set_pll1(unsigned int hz)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Find target frequency */ /* Find target frequency */
while (pll1_para[i].freq < hz) while (pll1_para[i].freq > hz)
i++; i++;
hz = pll1_para[i].freq; hz = pll1_para[i].freq;
if (! hz)
hz = 384000000;
/* Calculate system clock divisors */ /* Calculate system clock divisors */
axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */