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powerpc, 8xx: Simplify brgclk calculation and remove get_brgclk()
divider is calculated based on SCCR_DFBRG, with: SCCR_DFBRG 00 => divider 1 = 1 << 0 SCCR_DFBRG 01 => divider 4 = 1 << 2 SCCR_DFBRG 10 => divider 16 = 1 << 4 SCCR_DFBRG 11 => divider 64 = 1 << 6 This can be easily converted to a single shift operation: divider = 1 << (SCCR_DFBRG * 2) Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
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b2f2c7be34
commit
7a0a550c7f
1 changed files with 3 additions and 22 deletions
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@ -12,27 +12,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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void get_brgclk(uint sccr)
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{
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uint divider = 0;
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switch ((sccr & SCCR_DFBRG11) >> 11) {
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case 0:
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divider = 1;
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break;
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case 1:
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divider = 4;
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break;
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case 2:
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divider = 16;
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break;
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case 3:
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divider = 64;
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break;
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}
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gd->arch.brg_clk = gd->cpu_clk / divider;
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}
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/*
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* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
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*/
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@ -41,6 +20,8 @@ int get_clocks(void)
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uint immr = get_immr(0); /* Return full IMMR contents */
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immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
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uint sccr = in_be32(&immap->im_clkrst.car_sccr);
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uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2);
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/*
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* If for some reason measuring the gclk frequency won't
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* work, we return the hardwired value.
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@ -57,7 +38,7 @@ int get_clocks(void)
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gd->bus_clk = gd->cpu_clk / 2;
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}
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get_brgclk(sccr);
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gd->arch.brg_clk = gd->cpu_clk / divider;
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return 0;
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}
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