Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-26 22:52:18 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge git://git.denx.de/u-boot-socfpga

Browse source
This commit is contained in:
Tom Rini 2018-02-16 13:55:51 -05:00
commit 7961b9f6db
17 changed files with 8 additions and 31 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
arch/arm/Kconfig
View file

@ -698,16 +698,17 @@ config ARCH_SOCFPGA
select OF_CONTROL
select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
select ENABLE_ARM_SOC_BOOT0_HOOK
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
select SYS_THUMB_BUILD
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
imply HW_WATCHDOG
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"

2
arch/arm/dts/socfpga_arria5_socdk.dts
View file

@ -88,7 +88,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00";
compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <50000000>;
m25p,fast-read;

2
arch/arm/dts/socfpga_cyclone5_is1.dts
View file

@ -87,7 +87,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00";
compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;

2
arch/arm/dts/socfpga_cyclone5_socdk.dts
View file

@ -98,7 +98,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00";
compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;

2
arch/arm/dts/socfpga_cyclone5_socrates.dts
View file

@ -68,7 +68,7 @@
flash0: n25q00@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00";
compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <50000000>;
m25p,fast-read;

2
include/configs/socfpga_arria10_socdk.h
View file

@ -9,8 +9,6 @@
#include <asm/arch/base_addr_a10.h>
#define CONFIG_HW_WATCHDOG
/* Booting Linux */
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

2
include/configs/socfpga_arria5_socdk.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */

2
include/configs/socfpga_cyclone5_socdk.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */

2
include/configs/socfpga_de0_nano_soc.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */

2
include/configs/socfpga_de10_nano.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */

2
include/configs/socfpga_de1_soc.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */

2
include/configs/socfpga_is1.h
View file

@ -9,8 +9,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x10000000

2
include/configs/socfpga_mcvevk.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */

2
include/configs/socfpga_sockit.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */

2
include/configs/socfpga_socrates.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */

2
include/configs/socfpga_sr1500.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */

2
include/configs/socfpga_vining_fpga.h
View file

@ -8,8 +8,6 @@
#include <asm/arch/base_addr_ac5.h>
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */