mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch '2021-01-29-assorted-fixes'
- Assorted test fixes - Assorted minor FAT fixes - Assorted Kconfig dependency fixes - MediaTek, vexpress_aemv8a improvements - Other assorted minor fixes
This commit is contained in:
Tom Rini
commit
79382e9766
22 changed files with 677 additions and 52 deletions
|
|
@ -19,7 +19,7 @@
|
|||
};
|
||||
|
||||
aliases {
|
||||
spi0 = &snfi;
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||||
spi0 = &snor;
|
||||
};
|
||||
|
||||
memory@40000000 {
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||||
|
|
@ -165,11 +165,25 @@
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|||
pinctrl-names = "default", "snfi";
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||||
pinctrl-0 = <&snor_pins>;
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pinctrl-1 = <&snfi_pins>;
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status = "disabled";
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||||
|
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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&snor {
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pinctrl-names = "default";
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pinctrl-0 = <&snor_pins>;
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status = "okay";
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|
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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u-boot,dm-pre-reloc;
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||||
};
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};
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|
|
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|||
|
|
@ -53,6 +53,17 @@
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#size-cells = <0>;
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};
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snor: snor@11014000 {
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compatible = "mediatek,mtk-snor";
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reg = <0x11014000 0x1000>;
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clocks = <&pericfg CLK_PERI_FLASH_PD>,
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<&topckgen CLK_TOP_FLASH_SEL>;
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clock-names = "spi", "sf";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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|
|
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|||
|
|
@ -14,7 +14,7 @@
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compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
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aliases {
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spi0 = &snfi;
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spi0 = &snor;
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};
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chosen {
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|
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@ -69,11 +69,25 @@
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pinctrl-names = "default", "snfi";
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pinctrl-0 = <&snor_pins>;
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pinctrl-1 = <&snfi_pins>;
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status = "disabled";
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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&snor {
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pinctrl-names = "default";
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pinctrl-0 = <&snor_pins>;
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status = "okay";
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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u-boot,dm-pre-reloc;
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};
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};
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|
|
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@ -223,6 +223,17 @@
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#size-cells = <0>;
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};
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snor: snor@11014000 {
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compatible = "mediatek,mtk-snor";
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reg = <0x11014000 0x1000>;
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clocks = <&pericfg CLK_PERI_FLASH_PD>,
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<&topckgen CLK_TOP_FLASH_SEL>;
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clock-names = "spi", "sf";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ssusbsys: ssusbsys@1a000000 {
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compatible = "mediatek,mt7629-ssusbsys", "syscon";
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reg = <0x1a000000 0x1000>;
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|
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@ -9,11 +9,25 @@
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#include <command.h>
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#include <asm/sbi.h>
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struct sbi_imp {
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const long id;
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const char *name;
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};
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struct sbi_ext {
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const u32 id;
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const char *name;
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};
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static struct sbi_imp implementations[] = {
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{ 0, "Berkeley Boot Loader (BBL)" },
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{ 1, "OpenSBI" },
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{ 2, "Xvisor" },
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{ 3, "KVM" },
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{ 4, "RustSBI" },
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{ 5, "Diosix" },
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};
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static struct sbi_ext extensions[] = {
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{ 0x00000000, "sbi_set_timer" },
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{ 0x00000001, "sbi_console_putchar" },
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@ -42,23 +56,14 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
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printf("SBI %ld.%ld\n", ret >> 24, ret & 0xffffff);
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ret = sbi_get_impl_id();
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if (ret >= 0) {
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switch (ret) {
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case 0:
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printf("Berkeley Boot Loader (BBL)\n");
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break;
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case 1:
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printf("OpenSBI\n");
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break;
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case 2:
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printf("Xvisor\n");
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break;
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case 3:
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printf("KVM\n");
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break;
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default:
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printf("Unknown implementation\n");
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break;
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for (i = 0; i < ARRAY_SIZE(implementations); ++i) {
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if (ret == implementations[i].id) {
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printf("%s\n", implementations[i].name);
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break;
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}
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}
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if (i == ARRAY_SIZE(implementations))
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printf("Unknown implementation ID %ld\n", ret);
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}
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printf("Extensions:\n");
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for (i = 0; i < ARRAY_SIZE(extensions); ++i) {
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|
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@ -561,6 +561,7 @@ config HASH
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config AVB_VERIFY
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bool "Build Android Verified Boot operations"
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depends on LIBAVB
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depends on MMC
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depends on PARTITION_UUIDS
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help
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This option enables compilation of bootloader-dependent operations,
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|
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@ -49,7 +49,8 @@ CONFIG_DM_SERIAL=y
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CONFIG_MTK_SERIAL=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_MTK_SNFI_SPI=y
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# CONFIG_MTK_SNFI_SPI is not set
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CONFIG_MTK_SNOR=y
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CONFIG_SYSRESET_WATCHDOG=y
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CONFIG_TIMER=y
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CONFIG_MTK_TIMER=y
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|
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|
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@ -75,7 +75,8 @@ CONFIG_DM_SERIAL=y
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CONFIG_MTK_SERIAL=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_MTK_SNFI_SPI=y
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# CONFIG_MTK_SNFI_SPI is not set
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CONFIG_MTK_SNOR=y
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CONFIG_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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CONFIG_SYSRESET_WATCHDOG=y
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|
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@ -225,6 +225,13 @@ config MT7621_SPI
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the SPI NOR flash on platforms embedding this Ralink / MediaTek
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SPI core, like MT7621/7628/7688.
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config MTK_SNOR
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bool "Mediatek SPI-NOR controller driver"
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depends on SPI_MEM
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help
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Enable the Mediatek SPINOR controller driver. This driver has
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better read/write performance with NOR.
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config MTK_SNFI_SPI
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bool "Mediatek SPI memory controller driver"
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depends on SPI_MEM
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|
|
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|||
|
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@ -37,6 +37,7 @@ obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
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obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
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obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
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obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
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obj-$(CONFIG_MTK_SNOR) += mtk_snor.o
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obj-$(CONFIG_MT7620_SPI) += mt7620_spi.o
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obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
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obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
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|
|
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563
drivers/spi/mtk_snor.c
Normal file
563
drivers/spi/mtk_snor.c
Normal file
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@ -0,0 +1,563 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Mediatek SPI-NOR controller driver
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//
|
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// Copyright (C) 2020 SkyLake Huang <SkyLake.Huang@mediatek.com>
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//
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// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version
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|
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#include <clk.h>
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/device.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include <linux/completion.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <stdbool.h>
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#include <watchdog.h>
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#include <linux/dma-mapping.h>
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#define DRIVER_NAME "mtk-spi-nor"
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#define MTK_NOR_REG_CMD 0x00
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#define MTK_NOR_CMD_WRSR BIT(5)
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#define MTK_NOR_CMD_WRITE BIT(4)
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#define MTK_NOR_CMD_PROGRAM BIT(2)
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#define MTK_NOR_CMD_RDSR BIT(1)
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#define MTK_NOR_CMD_READ BIT(0)
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#define MTK_NOR_CMD_MASK GENMASK(5, 0)
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#define MTK_NOR_REG_PRG_CNT 0x04
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#define MTK_NOR_REG_RDSR 0x08
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#define MTK_NOR_REG_RDATA 0x0c
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|
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#define MTK_NOR_REG_RADR0 0x10
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#define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n))
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#define MTK_NOR_REG_RADR3 0xc8
|
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|
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#define MTK_NOR_REG_WDATA 0x1c
|
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|
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#define MTK_NOR_REG_PRGDATA0 0x20
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#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n))
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#define MTK_NOR_REG_PRGDATA_MAX 5
|
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|
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#define MTK_NOR_REG_SHIFT0 0x38
|
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#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n))
|
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#define MTK_NOR_REG_SHIFT_MAX 9
|
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|
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#define MTK_NOR_REG_CFG1 0x60
|
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#define MTK_NOR_FAST_READ BIT(0)
|
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|
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#define MTK_NOR_REG_CFG2 0x64
|
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#define MTK_NOR_WR_CUSTOM_OP_EN BIT(4)
|
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#define MTK_NOR_WR_BUF_EN BIT(0)
|
||||
|
||||
#define MTK_NOR_REG_PP_DATA 0x98
|
||||
|
||||
#define MTK_NOR_REG_IRQ_STAT 0xa8
|
||||
#define MTK_NOR_REG_IRQ_EN 0xac
|
||||
#define MTK_NOR_IRQ_DMA BIT(7)
|
||||
#define MTK_NOR_IRQ_WRSR BIT(5)
|
||||
#define MTK_NOR_IRQ_MASK GENMASK(7, 0)
|
||||
|
||||
#define MTK_NOR_REG_CFG3 0xb4
|
||||
#define MTK_NOR_DISABLE_WREN BIT(7)
|
||||
#define MTK_NOR_DISABLE_SR_POLL BIT(5)
|
||||
|
||||
#define MTK_NOR_REG_WP 0xc4
|
||||
#define MTK_NOR_ENABLE_SF_CMD 0x30
|
||||
|
||||
#define MTK_NOR_REG_BUSCFG 0xcc
|
||||
#define MTK_NOR_4B_ADDR BIT(4)
|
||||
#define MTK_NOR_QUAD_ADDR BIT(3)
|
||||
#define MTK_NOR_QUAD_READ BIT(2)
|
||||
#define MTK_NOR_DUAL_ADDR BIT(1)
|
||||
#define MTK_NOR_DUAL_READ BIT(0)
|
||||
#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)
|
||||
|
||||
#define MTK_NOR_REG_DMA_CTL 0x718
|
||||
#define MTK_NOR_DMA_START BIT(0)
|
||||
|
||||
#define MTK_NOR_REG_DMA_FADR 0x71c
|
||||
#define MTK_NOR_REG_DMA_DADR 0x720
|
||||
#define MTK_NOR_REG_DMA_END_DADR 0x724
|
||||
|
||||
#define MTK_NOR_PRG_MAX_SIZE 6
|
||||
// Reading DMA src/dst addresses have to be 16-byte aligned
|
||||
#define MTK_NOR_DMA_ALIGN 16
|
||||
#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
|
||||
// and we allocate a bounce buffer if destination address isn't aligned.
|
||||
#define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE
|
||||
|
||||
// Buffered page program can do one 128-byte transfer
|
||||
#define MTK_NOR_PP_SIZE 128
|
||||
|
||||
#define CLK_TO_US(priv, clkcnt) DIV_ROUND_UP(clkcnt, (priv)->spi_freq / 1000000)
|
||||
|
||||
#define MTK_NOR_UNLOCK_ALL 0x0
|
||||
|
||||
struct mtk_snor_priv {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
u8 *buffer;
|
||||
struct clk spi_clk;
|
||||
struct clk ctlr_clk;
|
||||
unsigned int spi_freq;
|
||||
bool wbuf_en;
|
||||
};
|
||||
|
||||
static inline void mtk_snor_rmw(struct mtk_snor_priv *priv, u32 reg, u32 set,
|
||||
u32 clr)
|
||||
{
|
||||
u32 val = readl(priv->base + reg);
|
||||
|
||||
val &= ~clr;
|
||||
val |= set;
|
||||
writel(val, priv->base + reg);
|
||||
}
|
||||
|
||||
static inline int mtk_snor_cmd_exec(struct mtk_snor_priv *priv, u32 cmd,
|
||||
ulong clk)
|
||||
{
|
||||
unsigned long long delay = CLK_TO_US(priv, clk);
|
||||
u32 reg;
|
||||
int ret;
|
||||
|
||||
writel(cmd, priv->base + MTK_NOR_REG_CMD);
|
||||
delay = (delay + 1) * 200;
|
||||
ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CMD, reg,
|
||||
!(reg & cmd), delay);
|
||||
if (ret < 0)
|
||||
dev_err(priv->dev, "command %u timeout.\n", cmd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mtk_snor_set_addr(struct mtk_snor_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
u32 addr = op->addr.val;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR(i));
|
||||
addr >>= 8;
|
||||
}
|
||||
if (op->addr.nbytes == 4) {
|
||||
writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR3);
|
||||
mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
|
||||
} else {
|
||||
mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
|
||||
}
|
||||
}
|
||||
|
||||
static bool need_bounce(const struct spi_mem_op *op)
|
||||
{
|
||||
return ((uintptr_t)op->data.buf.in & MTK_NOR_DMA_ALIGN_MASK);
|
||||
}
|
||||
|
||||
static int mtk_snor_adjust_op_size(struct spi_slave *slave,
|
||||
struct spi_mem_op *op)
|
||||
{
|
||||
if (!op->data.nbytes)
|
||||
return 0;
|
||||
|
||||
if (op->addr.nbytes == 3 || op->addr.nbytes == 4) {
|
||||
if (op->data.dir == SPI_MEM_DATA_IN) { //&&
|
||||
// limit size to prevent timeout calculation overflow
|
||||
if (op->data.nbytes > 0x400000)
|
||||
op->data.nbytes = 0x400000;
|
||||
if (op->addr.val & MTK_NOR_DMA_ALIGN_MASK ||
|
||||
op->data.nbytes < MTK_NOR_DMA_ALIGN)
|
||||
op->data.nbytes = 1;
|
||||
else if (!need_bounce(op))
|
||||
op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK;
|
||||
else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE)
|
||||
op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE;
|
||||
return 0;
|
||||
} else if (op->data.dir == SPI_MEM_DATA_OUT) {
|
||||
if (op->data.nbytes >= MTK_NOR_PP_SIZE)
|
||||
op->data.nbytes = MTK_NOR_PP_SIZE;
|
||||
else
|
||||
op->data.nbytes = 1;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool mtk_snor_supports_op(struct spi_slave *slave,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
/* This controller only supports 1-1-1 write mode */
|
||||
if (op->data.dir == SPI_MEM_DATA_OUT &&
|
||||
(op->cmd.buswidth != 1 || op->data.buswidth != 1))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void mtk_snor_setup_bus(struct mtk_snor_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
u32 reg = 0;
|
||||
|
||||
if (op->addr.nbytes == 4)
|
||||
reg |= MTK_NOR_4B_ADDR;
|
||||
|
||||
if (op->data.buswidth == 4) {
|
||||
reg |= MTK_NOR_QUAD_READ;
|
||||
writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(4));
|
||||
if (op->addr.buswidth == 4)
|
||||
reg |= MTK_NOR_QUAD_ADDR;
|
||||
} else if (op->data.buswidth == 2) {
|
||||
reg |= MTK_NOR_DUAL_READ;
|
||||
writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(3));
|
||||
if (op->addr.buswidth == 2)
|
||||
reg |= MTK_NOR_DUAL_ADDR;
|
||||
} else {
|
||||
if (op->cmd.opcode == 0x0b)
|
||||
mtk_snor_rmw(priv, MTK_NOR_REG_CFG1, MTK_NOR_FAST_READ,
|
||||
0);
|
||||
else
|
||||
mtk_snor_rmw(priv, MTK_NOR_REG_CFG1, 0,
|
||||
MTK_NOR_FAST_READ);
|
||||
}
|
||||
mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK);
|
||||
}
|
||||
|
||||
static int mtk_snor_dma_exec(struct mtk_snor_priv *priv, u32 from,
|
||||
unsigned int length, dma_addr_t dma_addr)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong delay;
|
||||
u32 reg;
|
||||
|
||||
writel(from, priv->base + MTK_NOR_REG_DMA_FADR);
|
||||
writel(dma_addr, priv->base + MTK_NOR_REG_DMA_DADR);
|
||||
writel(dma_addr + length, priv->base + MTK_NOR_REG_DMA_END_DADR);
|
||||
|
||||
mtk_snor_rmw(priv, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
|
||||
|
||||
delay = CLK_TO_US(priv, (length + 5) * BITS_PER_BYTE);
|
||||
|
||||
delay = (delay + 1) * 100;
|
||||
ret = readl_poll_timeout(priv->base + MTK_NOR_REG_DMA_CTL, reg,
|
||||
!(reg & MTK_NOR_DMA_START), delay);
|
||||
|
||||
if (ret < 0)
|
||||
dev_err(priv->dev, "dma read timeout.\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_snor_read_bounce(struct mtk_snor_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
unsigned int rdlen;
|
||||
int ret;
|
||||
|
||||
if (op->data.nbytes & MTK_NOR_DMA_ALIGN_MASK)
|
||||
rdlen = (op->data.nbytes + MTK_NOR_DMA_ALIGN) &
|
||||
~MTK_NOR_DMA_ALIGN_MASK;
|
||||
else
|
||||
rdlen = op->data.nbytes;
|
||||
|
||||
ret = mtk_snor_dma_exec(priv, op->addr.val, rdlen,
|
||||
(dma_addr_t)priv->buffer);
|
||||
|
||||
if (!ret)
|
||||
memcpy(op->data.buf.in, priv->buffer, op->data.nbytes);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_snor_read_dma(struct mtk_snor_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
int ret;
|
||||
dma_addr_t dma_addr;
|
||||
|
||||
if (need_bounce(op))
|
||||
return mtk_snor_read_bounce(priv, op);
|
||||
|
||||
dma_addr = dma_map_single(op->data.buf.in, op->data.nbytes,
|
||||
DMA_FROM_DEVICE);
|
||||
|
||||
if (dma_mapping_error(priv->dev, dma_addr))
|
||||
return -EINVAL;
|
||||
|
||||
ret = mtk_snor_dma_exec(priv, op->addr.val, op->data.nbytes, dma_addr);
|
||||
|
||||
dma_unmap_single(dma_addr, op->data.nbytes, DMA_FROM_DEVICE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_snor_read_pio(struct mtk_snor_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
u8 *buf = op->data.buf.in;
|
||||
int ret;
|
||||
|
||||
ret = mtk_snor_cmd_exec(priv, MTK_NOR_CMD_READ, 6 * BITS_PER_BYTE);
|
||||
if (!ret)
|
||||
buf[0] = readb(priv->base + MTK_NOR_REG_RDATA);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_snor_write_buffer_enable(struct mtk_snor_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
if (priv->wbuf_en)
|
||||
return 0;
|
||||
|
||||
val = readl(priv->base + MTK_NOR_REG_CFG2);
|
||||
writel(val | MTK_NOR_WR_BUF_EN, priv->base + MTK_NOR_REG_CFG2);
|
||||
ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CFG2, val,
|
||||
val & MTK_NOR_WR_BUF_EN, 10000);
|
||||
if (!ret)
|
||||
priv->wbuf_en = true;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_snor_write_buffer_disable(struct mtk_snor_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
if (!priv->wbuf_en)
|
||||
return 0;
|
||||
val = readl(priv->base + MTK_NOR_REG_CFG2);
|
||||
writel(val & ~MTK_NOR_WR_BUF_EN, priv->base + MTK_NOR_REG_CFG2);
|
||||
ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CFG2, val,
|
||||
!(val & MTK_NOR_WR_BUF_EN), 10000);
|
||||
if (!ret)
|
||||
priv->wbuf_en = false;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_snor_pp_buffered(struct mtk_snor_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
const u8 *buf = op->data.buf.out;
|
||||
u32 val;
|
||||
int ret, i;
|
||||
|
||||
ret = mtk_snor_write_buffer_enable(priv);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < op->data.nbytes; i += 4) {
|
||||
val = buf[i + 3] << 24 | buf[i + 2] << 16 | buf[i + 1] << 8 |
|
||||
buf[i];
|
||||
writel(val, priv->base + MTK_NOR_REG_PP_DATA);
|
||||
}
|
||||
mtk_snor_cmd_exec(priv, MTK_NOR_CMD_WRITE,
|
||||
(op->data.nbytes + 5) * BITS_PER_BYTE);
|
||||
return mtk_snor_write_buffer_disable(priv);
|
||||
}
|
||||
|
||||
static int mtk_snor_pp_unbuffered(struct mtk_snor_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
const u8 *buf = op->data.buf.out;
|
||||
int ret;
|
||||
|
||||
ret = mtk_snor_write_buffer_disable(priv);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
writeb(buf[0], priv->base + MTK_NOR_REG_WDATA);
|
||||
return mtk_snor_cmd_exec(priv, MTK_NOR_CMD_WRITE, 6 * BITS_PER_BYTE);
|
||||
}
|
||||
|
||||
static int mtk_snor_cmd_program(struct mtk_snor_priv *priv,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
u32 tx_len = 0;
|
||||
u32 trx_len = 0;
|
||||
int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
|
||||
void __iomem *reg;
|
||||
u8 *txbuf;
|
||||
int tx_cnt = 0;
|
||||
u8 *rxbuf = op->data.buf.in;
|
||||
int i = 0;
|
||||
|
||||
tx_len = 1 + op->addr.nbytes + op->dummy.nbytes;
|
||||
trx_len = tx_len + op->data.nbytes;
|
||||
if (op->data.dir == SPI_MEM_DATA_OUT)
|
||||
tx_len += op->data.nbytes;
|
||||
|
||||
txbuf = kmalloc_array(tx_len, sizeof(u8), GFP_KERNEL);
|
||||
memset(txbuf, 0x0, tx_len * sizeof(u8));
|
||||
|
||||
/* Join all bytes to be transferred */
|
||||
txbuf[tx_cnt] = op->cmd.opcode;
|
||||
tx_cnt++;
|
||||
for (i = op->addr.nbytes; i > 0; i--, tx_cnt++)
|
||||
txbuf[tx_cnt] = ((u8 *)&op->addr.val)[i - 1];
|
||||
for (i = op->dummy.nbytes; i > 0; i--, tx_cnt++)
|
||||
txbuf[tx_cnt] = 0x0;
|
||||
if (op->data.dir == SPI_MEM_DATA_OUT)
|
||||
for (i = op->data.nbytes; i > 0; i--, tx_cnt++)
|
||||
txbuf[tx_cnt] = ((u8 *)op->data.buf.out)[i - 1];
|
||||
|
||||
for (i = MTK_NOR_REG_PRGDATA_MAX; i >= 0; i--)
|
||||
writeb(0, priv->base + MTK_NOR_REG_PRGDATA(i));
|
||||
|
||||
for (i = 0; i < tx_len; i++, reg_offset--)
|
||||
writeb(txbuf[i], priv->base + MTK_NOR_REG_PRGDATA(reg_offset));
|
||||
|
||||
kfree(txbuf);
|
||||
|
||||
writel(trx_len * BITS_PER_BYTE, priv->base + MTK_NOR_REG_PRG_CNT);
|
||||
|
||||
mtk_snor_cmd_exec(priv, MTK_NOR_CMD_PROGRAM, trx_len * BITS_PER_BYTE);
|
||||
|
||||
reg_offset = op->data.nbytes - 1;
|
||||
for (i = 0; i < op->data.nbytes; i++, reg_offset--) {
|
||||
reg = priv->base + MTK_NOR_REG_SHIFT(reg_offset);
|
||||
rxbuf[i] = readb(reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_snor_exec_op(struct spi_slave *slave,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
struct udevice *bus = dev_get_parent(slave->dev);
|
||||
struct mtk_snor_priv *priv = dev_get_priv(bus);
|
||||
int ret;
|
||||
|
||||
if (op->data.dir == SPI_MEM_NO_DATA || op->addr.nbytes == 0) {
|
||||
return mtk_snor_cmd_program(priv, op);
|
||||
} else if (op->data.dir == SPI_MEM_DATA_OUT) {
|
||||
mtk_snor_set_addr(priv, op);
|
||||
writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA0);
|
||||
if (op->data.nbytes == MTK_NOR_PP_SIZE)
|
||||
return mtk_snor_pp_buffered(priv, op);
|
||||
return mtk_snor_pp_unbuffered(priv, op);
|
||||
} else if (op->data.dir == SPI_MEM_DATA_IN) {
|
||||
ret = mtk_snor_write_buffer_disable(priv);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
mtk_snor_setup_bus(priv, op);
|
||||
if (op->data.nbytes == 1) {
|
||||
mtk_snor_set_addr(priv, op);
|
||||
return mtk_snor_read_pio(priv, op);
|
||||
} else {
|
||||
return mtk_snor_read_dma(priv, op);
|
||||
}
|
||||
}
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int mtk_snor_probe(struct udevice *bus)
|
||||
{
|
||||
struct mtk_snor_priv *priv = dev_get_priv(bus);
|
||||
u8 *buffer;
|
||||
int ret;
|
||||
u32 reg;
|
||||
|
||||
priv->base = (void __iomem *)devfdt_get_addr(bus);
|
||||
if (!priv->base)
|
||||
return -EINVAL;
|
||||
|
||||
ret = clk_get_by_name(bus, "spi", &priv->spi_clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = clk_get_by_name(bus, "sf", &priv->ctlr_clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
buffer = devm_kmalloc(bus, MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
|
||||
GFP_KERNEL);
|
||||
if (!buffer)
|
||||
return -ENOMEM;
|
||||
if ((ulong)buffer & MTK_NOR_DMA_ALIGN_MASK)
|
||||
buffer = (u8 *)(((ulong)buffer + MTK_NOR_DMA_ALIGN) &
|
||||
~MTK_NOR_DMA_ALIGN_MASK);
|
||||
priv->buffer = buffer;
|
||||
|
||||
clk_enable(&priv->spi_clk);
|
||||
clk_enable(&priv->ctlr_clk);
|
||||
|
||||
priv->spi_freq = clk_get_rate(&priv->spi_clk);
|
||||
printf("spi frequency: %d Hz\n", priv->spi_freq);
|
||||
|
||||
/* With this setting, we issue one command at a time to
|
||||
* accommodate to SPI-mem framework.
|
||||
*/
|
||||
writel(MTK_NOR_ENABLE_SF_CMD, priv->base + MTK_NOR_REG_WP);
|
||||
mtk_snor_rmw(priv, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0);
|
||||
mtk_snor_rmw(priv, MTK_NOR_REG_CFG3,
|
||||
MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0);
|
||||
|
||||
/* Unlock all blocks using write status command.
|
||||
* SPI-MEM hasn't implemented unlock procedure on MXIC devices.
|
||||
* We may remove this later.
|
||||
*/
|
||||
writel(2 * BITS_PER_BYTE, priv->base + MTK_NOR_REG_PRG_CNT);
|
||||
writel(MTK_NOR_UNLOCK_ALL, priv->base + MTK_NOR_REG_PRGDATA(5));
|
||||
writel(MTK_NOR_IRQ_WRSR, priv->base + MTK_NOR_REG_IRQ_EN);
|
||||
writel(MTK_NOR_CMD_WRSR, priv->base + MTK_NOR_REG_CMD);
|
||||
ret = readl_poll_timeout(priv->base + MTK_NOR_REG_IRQ_STAT, reg,
|
||||
!(reg & MTK_NOR_IRQ_WRSR),
|
||||
((3 * BITS_PER_BYTE) + 1) * 200);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_snor_set_speed(struct udevice *bus, uint speed)
|
||||
{
|
||||
/* MTK's SNOR controller does not have a bus clock divider.
|
||||
* We setup maximum bus clock in dts.
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_snor_set_mode(struct udevice *bus, uint mode)
|
||||
{
|
||||
/* We set up mode later for each transmission.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct spi_controller_mem_ops mtk_snor_mem_ops = {
|
||||
.adjust_op_size = mtk_snor_adjust_op_size,
|
||||
.supports_op = mtk_snor_supports_op,
|
||||
.exec_op = mtk_snor_exec_op
|
||||
};
|
||||
|
||||
static const struct dm_spi_ops mtk_snor_ops = {
|
||||
.mem_ops = &mtk_snor_mem_ops,
|
||||
.set_speed = mtk_snor_set_speed,
|
||||
.set_mode = mtk_snor_set_mode,
|
||||
};
|
||||
|
||||
static const struct udevice_id mtk_snor_ids[] = {
|
||||
{ .compatible = "mediatek,mtk-snor" },
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mtk_snor) = {
|
||||
.name = "mtk_snor",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = mtk_snor_ids,
|
||||
.ops = &mtk_snor_ops,
|
||||
.priv_auto = sizeof(struct mtk_snor_priv),
|
||||
.probe = mtk_snor_probe,
|
||||
};
|
||||
4
env/sf.c
vendored
4
env/sf.c
vendored
|
|
@ -139,7 +139,7 @@ static int env_sf_save(void)
|
|||
|
||||
printf("Valid environment: %d\n", (int)gd->env_valid);
|
||||
|
||||
done:
|
||||
done:
|
||||
if (saved_buffer)
|
||||
free(saved_buffer);
|
||||
|
||||
|
|
@ -236,7 +236,7 @@ static int env_sf_save(void)
|
|||
ret = 0;
|
||||
puts("done\n");
|
||||
|
||||
done:
|
||||
done:
|
||||
if (saved_buffer)
|
||||
free(saved_buffer);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ config FS_BTRFS
|
|||
select LZO
|
||||
select ZSTD
|
||||
select RBTREE
|
||||
select SHA256
|
||||
help
|
||||
This provides a single-device read-only BTRFS support. BTRFS is a
|
||||
next-generation Linux file system based on the copy-on-write
|
||||
|
|
|
|||
|
|
@ -248,7 +248,6 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry)
|
|||
static int
|
||||
get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size)
|
||||
{
|
||||
__u32 idx = 0;
|
||||
__u32 startsect;
|
||||
int ret;
|
||||
|
||||
|
|
@ -277,6 +276,8 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size)
|
|||
size -= mydata->sect_size;
|
||||
}
|
||||
} else {
|
||||
__u32 idx;
|
||||
|
||||
idx = size / mydata->sect_size;
|
||||
if (idx == 0)
|
||||
ret = 0;
|
||||
|
|
|
|||
|
|
@ -108,10 +108,7 @@ static int set_name(fat_itr *itr, const char *filename, char *shortname)
|
|||
char buf[13];
|
||||
int i;
|
||||
int ret;
|
||||
struct {
|
||||
char name[8];
|
||||
char ext[3];
|
||||
} dirent;
|
||||
struct nameext dirent;
|
||||
|
||||
if (!filename)
|
||||
return -EIO;
|
||||
|
|
@ -185,7 +182,7 @@ static int set_name(fat_itr *itr, const char *filename, char *shortname)
|
|||
}
|
||||
return -EIO;
|
||||
out:
|
||||
memcpy(shortname, dirent.name, SHORT_NAME_SIZE);
|
||||
memcpy(shortname, &dirent, SHORT_NAME_SIZE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -576,7 +573,6 @@ static __u32 determine_fatent(fsdata *mydata, __u32 entry)
|
|||
static int
|
||||
set_sectors(fsdata *mydata, u32 startsect, u8 *buffer, u32 size)
|
||||
{
|
||||
u32 nsects = 0;
|
||||
int ret;
|
||||
|
||||
debug("startsect: %d\n", startsect);
|
||||
|
|
@ -598,6 +594,8 @@ set_sectors(fsdata *mydata, u32 startsect, u8 *buffer, u32 size)
|
|||
size -= mydata->sect_size;
|
||||
}
|
||||
} else if (size >= mydata->sect_size) {
|
||||
u32 nsects;
|
||||
|
||||
nsects = size / mydata->sect_size;
|
||||
ret = disk_write(startsect, nsects, buffer);
|
||||
if (ret != nsects) {
|
||||
|
|
@ -788,7 +786,6 @@ get_set_cluster(fsdata *mydata, __u32 clustnum, loff_t pos, __u8 *buffer,
|
|||
}
|
||||
|
||||
size -= wsize;
|
||||
buffer += wsize;
|
||||
*gotsize += wsize;
|
||||
}
|
||||
|
||||
|
|
@ -1485,10 +1482,10 @@ static int delete_single_dentry(fat_itr *itr)
|
|||
*/
|
||||
static int delete_long_name(fat_itr *itr)
|
||||
{
|
||||
struct dir_entry *dent = itr->dent;
|
||||
int seqn = itr->dent->nameext.name[0] & ~LAST_LONG_ENTRY_MASK;
|
||||
|
||||
while (seqn--) {
|
||||
struct dir_entry *dent;
|
||||
int ret;
|
||||
|
||||
ret = delete_single_dentry(itr);
|
||||
|
|
|
|||
|
|
@ -137,6 +137,7 @@
|
|||
"fdt_alt_name=juno\0" \
|
||||
"fdt_addr_r=0x80000000\0" \
|
||||
|
||||
#ifndef CONFIG_BOOTCOMMAND
|
||||
/* Copy the kernel and FDT to DRAM memory and boot */
|
||||
#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr_r} ;"\
|
||||
"if test $? -eq 1; then "\
|
||||
|
|
@ -157,6 +158,7 @@
|
|||
" else setenv ramdisk_param -; "\
|
||||
"fi ; " \
|
||||
"booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}"
|
||||
#endif
|
||||
|
||||
|
||||
#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
|
||||
|
|
@ -170,6 +172,7 @@
|
|||
"boot_name=boot.img\0" \
|
||||
"boot_addr=0x8007f800\0"
|
||||
|
||||
#ifndef CONFIG_BOOTCOMMAND
|
||||
#define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \
|
||||
" set bootargs; " \
|
||||
" abootimg addr ${boot_addr}; " \
|
||||
|
|
@ -187,8 +190,7 @@
|
|||
" fdt chosen ${initrd_addr} ${initrd_end}; " \
|
||||
" booti $kernel_addr - $fdt_addr; " \
|
||||
"fi"
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
|
||||
ifneq ($(CONFIG_$(SPL_)BLOBLIST),)
|
||||
obj-$(CONFIG_$(SPL_)CMDLINE) += bloblist.o
|
||||
endif
|
||||
obj-$(CONFIG_$(SPL_)CMDLINE) += bootm.o
|
||||
endif
|
||||
obj-$(CONFIG_$(SPL_)CMDLINE) += cmd/
|
||||
obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_ut.o
|
||||
obj-$(CONFIG_$(SPL_)CMDLINE) += command_ut.o
|
||||
|
|
|
|||
|
|
@ -89,9 +89,8 @@ static struct cmd_tbl cmd_ut_sub[] = {
|
|||
U_BOOT_CMD_MKENT(bloblist, CONFIG_SYS_MAXARGS, 1, do_ut_bloblist,
|
||||
"", ""),
|
||||
U_BOOT_CMD_MKENT(bootm, CONFIG_SYS_MAXARGS, 1, do_ut_bootm, "", ""),
|
||||
U_BOOT_CMD_MKENT(str, CONFIG_SYS_MAXARGS, 1, do_ut_str,
|
||||
"", ""),
|
||||
#endif
|
||||
U_BOOT_CMD_MKENT(str, CONFIG_SYS_MAXARGS, 1, do_ut_str, "", ""),
|
||||
};
|
||||
|
||||
static int do_ut_all(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ obj-$(CONFIG_CMD_LOG) += log_filter.o
|
|||
ifdef CONFIG_UT_LOG
|
||||
|
||||
obj-y += test-main.o
|
||||
obj-y += pr_cont_test.o
|
||||
|
||||
ifdef CONFIG_SANDBOX
|
||||
obj-$(CONFIG_LOG_SYSLOG) += syslog_test.o
|
||||
|
|
@ -16,6 +15,7 @@ obj-$(CONFIG_LOG_SYSLOG) += syslog_test_ndebug.o
|
|||
endif
|
||||
|
||||
ifdef CONFIG_LOG
|
||||
obj-y += pr_cont_test.o
|
||||
obj-$(CONFIG_CONSOLE_RECORD) += cont_test.o
|
||||
else
|
||||
obj-$(CONFIG_CONSOLE_RECORD) += nolog_test.o
|
||||
|
|
|
|||
|
|
@ -10,11 +10,11 @@
|
|||
import os
|
||||
import os.path
|
||||
import sys
|
||||
import pytest
|
||||
from pkg_resources import load_entry_point
|
||||
|
||||
# argv; py.test test_directory_name user-supplied-arguments
|
||||
args = [os.path.dirname(__file__) + '/tests']
|
||||
args.extend(sys.argv)
|
||||
|
||||
if __name__ == '__main__':
|
||||
sys.exit(load_entry_point('pytest', 'console_scripts', 'pytest')(args))
|
||||
# argv; py.test test_directory_name user-supplied-arguments
|
||||
args = [os.path.dirname(__file__) + '/tests']
|
||||
args.extend(sys.argv)
|
||||
sys.exit(pytest.main(args))
|
||||
|
|
|
|||
|
|
@ -243,8 +243,7 @@ def umount_fs(mount_point):
|
|||
# Fixture for basic fs test
|
||||
# derived from test/fs/fs-test.sh
|
||||
#
|
||||
# NOTE: yield_fixture was deprecated since pytest-3.0
|
||||
@pytest.yield_fixture()
|
||||
@pytest.fixture()
|
||||
def fs_obj_basic(request, u_boot_config):
|
||||
"""Set up a file system to be used in basic fs test.
|
||||
|
||||
|
|
@ -352,8 +351,7 @@ def fs_obj_basic(request, u_boot_config):
|
|||
#
|
||||
# Fixture for extended fs test
|
||||
#
|
||||
# NOTE: yield_fixture was deprecated since pytest-3.0
|
||||
@pytest.yield_fixture()
|
||||
@pytest.fixture()
|
||||
def fs_obj_ext(request, u_boot_config):
|
||||
"""Set up a file system to be used in extended fs test.
|
||||
|
||||
|
|
@ -439,8 +437,7 @@ def fs_obj_ext(request, u_boot_config):
|
|||
#
|
||||
# Fixture for mkdir test
|
||||
#
|
||||
# NOTE: yield_fixture was deprecated since pytest-3.0
|
||||
@pytest.yield_fixture()
|
||||
@pytest.fixture()
|
||||
def fs_obj_mkdir(request, u_boot_config):
|
||||
"""Set up a file system to be used in mkdir test.
|
||||
|
||||
|
|
@ -472,8 +469,7 @@ def fs_obj_mkdir(request, u_boot_config):
|
|||
#
|
||||
# Fixture for unlink test
|
||||
#
|
||||
# NOTE: yield_fixture was deprecated since pytest-3.0
|
||||
@pytest.yield_fixture()
|
||||
@pytest.fixture()
|
||||
def fs_obj_unlink(request, u_boot_config):
|
||||
"""Set up a file system to be used in unlink test.
|
||||
|
||||
|
|
@ -538,8 +534,7 @@ def fs_obj_unlink(request, u_boot_config):
|
|||
#
|
||||
# Fixture for symlink fs test
|
||||
#
|
||||
# NOTE: yield_fixture was deprecated since pytest-3.0
|
||||
@pytest.yield_fixture()
|
||||
@pytest.fixture()
|
||||
def fs_obj_symlink(request, u_boot_config):
|
||||
"""Set up a file system to be used in symlink fs test.
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
import pytest
|
||||
import u_boot_utils as util
|
||||
|
||||
@pytest.mark.boardspec('sandbox')
|
||||
@pytest.mark.buildconfigspec('spl_of_platdata')
|
||||
def test_spl_devicetree(u_boot_console):
|
||||
"""Test content of spl device-tree"""
|
||||
|
|
|
|||
Loading…
Reference in a new issue