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mkimage: sunxi_egon: add support for riscv

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There's now a sun20i family in sunxi, which uses RISC-V CPU.

Add support for making eGON.BT0 image for RISC-V.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Icenowy Zheng 2021-10-14 20:53:06 -05:00 committed by Andre Przywara
parent 82ae151aee
commit 78ac2c0fd0
1 changed files with 23 additions and 0 deletions
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23
tools/sunxi_egon.c
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@ -31,6 +31,7 @@ static int egon_check_params(struct image_tool_params *params)
*/
switch (egon_get_arch(params)) {
case IH_ARCH_ARM:
case IH_ARCH_RISCV:
break;
default:
return EXIT_FAILURE;
@ -55,6 +56,10 @@ static int egon_verify_header(unsigned char *ptr, int image_size,
if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000)
return EXIT_FAILURE;
break;
case IH_ARCH_RISCV:
if ((le32_to_cpu(header->b_instruction) & 0x00000fff) != 0x0000006f)
return EXIT_FAILURE;
break;
default:
return EXIT_FAILURE; /* Unknown architecture */
}
@ -116,6 +121,24 @@ static void egon_set_header(void *buf, struct stat *sbuf, int infd,
value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2);
header->b_instruction = cpu_to_le32(value);
break;
case IH_ARCH_RISCV:
/*
* Generate a RISC-V JAL instruction with rd=x0
* (pseudo instruction J, jump without side effects).
*
* The following weird bit operation maps imm[20]
* to inst[31], imm[10:1] to inst[30:21],
* imm[11] to inst[20], imm[19:12] to inst[19:12],
* and imm[0] is dropped (because 1-byte RISC-V instruction
* is not allowed).
*/
value = 0x0000006f |
((sizeof(struct boot_file_head) & 0x00100000) << 11) |
((sizeof(struct boot_file_head) & 0x000007fe) << 20) |
((sizeof(struct boot_file_head) & 0x00000800) << 9) |
((sizeof(struct boot_file_head) & 0x000ff000) << 0);
header->b_instruction = cpu_to_le32(value);
break;
}
memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));