Xilinx changes for v2024.04-rc3

zynqmp:
 - Cover missing _SE chip variants to fix fpga programming
 
 versal:
 - Enable LTO for mini configurations
 
 versal-net:
 - Enable LTO for mini configurations
 - Fix GIC address to aligned with real silicon
 
 xilinx:
 - DTs cleanup and fixups
 - Enable HTTP boot
 - Add missing spl header to zynqmp.c
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Merge tag 'xilinx-for-v2024.04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2024.04-rc3

zynqmp:
- Cover missing _SE chip variants to fix fpga programming

versal:
- Enable LTO for mini configurations

versal-net:
- Enable LTO for mini configurations
- Fix GIC address to aligned with real silicon

xilinx:
- DTs cleanup and fixups
- Enable HTTP boot
- Add missing spl header to zynqmp.c

arch/arm/dts/zynq-7000.dtsi

@@ -44,7 +44,7 @@
 		};
 	};
 
-	fpga_full: fpga-full {
+	fpga_full: fpga-region {
 		compatible = "fpga-region";
 		fpga-mgr = <&devcfg>;
 		#address-cells = <1>;

arch/arm/dts/zynqmp-e-a2197-00-revA.dts

@@ -449,6 +449,7 @@
 				factory-fout = <156250000>;
 				clock-frequency = <156250000>;
 				clock-output-names = "si570_zsfp_clk";
+				silabs,skip-recall;
 			};
 		};
 		i2c@6 { /* USER_SI570_1 */
@@ -463,6 +464,7 @@
 				factory-fout = <100000000>;
 				clock-frequency = <100000000>;
 				clock-output-names = "si570_user1";
+				silabs,skip-recall;
 			};
 
 		};
@@ -560,6 +562,7 @@
 				factory-fout = <200000000>;
 				clock-frequency = <200000000>;
 				clock-output-names = "si570_lpddr4_clk2";
+				silabs,skip-recall;
 			};
 		};
 		i2c@5 { /* LPDDR4_SI570_CLK1 */
@@ -574,6 +577,7 @@
 				factory-fout = <200000000>;
 				clock-frequency = <200000000>;
 				clock-output-names = "si570_lpddr4_clk1";
+				silabs,skip-recall;
 			};
 		};
 		i2c@6 { /* HSDP_SI570 */
@@ -588,6 +592,7 @@
 				factory-fout = <156250000>;
 				clock-frequency = <156250000>;
 				clock-output-names = "si570_hsdp_clk";
+				silabs,skip-recall;
 			};
 		};
 		i2c@7 { /* 8A34001 - U219B and J310 connector */

arch/arm/dts/zynqmp-sck-kd-g-revA.dtso

@@ -32,6 +32,18 @@
 		#clock-cells = <0>;
 		clock-frequency = <26000000>;
 	};
+
+	clk_25_0: clock4 { /* u92/u91 - GEM2 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	clk_25_1: clock5 { /* u92/u91 - GEM3 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
 };
 
 &can0 {
@@ -354,3 +366,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1_default>;
 };
+
+&zynqmp_dpsub {
+	status = "disabled";
+};

arch/arm/dts/zynqmp-sck-kr-g-revA.dtso

@@ -25,37 +25,43 @@
 		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
 	};
 
-	si5332_0: si5332-0 { /* u17 - GEM0/1 */
+	clk_27: clock0 { /* u86 - DP */
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <125000000>;
-	};
-
-	si5332_1: si5332-1 { /* u17 - DP */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <27000000>;
 	};
 
-	si5332_2: si5332-2 { /* u17 - USB */
+	clk_125: si5332-0 { /* u17 - GEM0/1 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	clk_74: si5332-5 { /* u17 - SLVC-EC */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <74250000>;
+	};
+
+	clk_26: si5332-2 { /* u17 - USB */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <26000000>;
 	};
 
-	si5332_3: si5332-3 { /* u17 - SFP+ */
+	clk_156: si5332-3 { /* u17 - SFP+ */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <156250000>;
 	};
 
-	si5332_4: si5332-4 { /* u17 - GEM2 */
+	clk_25_0: si5332-1 { /* u17 - GEM2 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <25000000>;
 	};
 
-	si5332_5: si5332-5 { /* u17 - GEM3 */
+	clk_25_1: si5332-4 { /* u17 - GEM3 */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <25000000>;
@@ -115,7 +121,7 @@
 &psgtr {
 	status = "okay";
 	/* gem0/1, dp, usb */
-	clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>;
+	clocks = <&clk_125>, <&clk_27>, <&clk_26>;
 	clock-names = "ref0", "ref1", "ref2";
 };
 
@@ -168,12 +174,13 @@
 	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
 	reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
 	assigned-clock-rates = <250000000>, <20000000>;
-
+#if 0
 	usbhub1: usb-hub { /* u84 */
 		i2c-bus = <&usbhub_i2c1>;
 		compatible = "microchip,usb5744";
 		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
 	};
+#endif
 };
 
 &dwc3_1 {

arch/arm/dts/zynqmp-sck-kr-g-revB.dtso

@@ -60,6 +60,12 @@
 		#clock-cells = <0>;
 		clock-frequency = <25000000>;
 	};
+
+	clk_74: clock6 { /* u88 - SLVC-EC */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <74250000>;
+	};
 };
 
 &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -169,11 +175,13 @@
 	reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
 	assigned-clock-rates = <250000000>, <20000000>;
 
+#if 0
 	usbhub1: usb-hub { /* u84 */
 		i2c-bus = <&usbhub_i2c1>;
 		compatible = "microchip,usb5744";
 		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
 	};
+#endif
 };
 
 &dwc3_1 {

arch/arm/dts/zynqmp.dtsi

@@ -207,68 +207,71 @@
 				mbox-names = "tx", "rx";
 			};
 
-			nvmem-firmware {
+			soc-nvmem {
 				compatible = "xlnx,zynqmp-nvmem-fw";
-				#address-cells = <1>;
+				nvmem-layout {
-				#size-cells = <1>;
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
 
-				soc_revision: soc-revision@0 {
+					soc_revision: soc-revision@0 {
-					reg = <0x0 0x4>;
+						reg = <0x0 0x4>;
-				};
+					};
-				/* efuse access */
+					/* efuse access */
-				efuse_dna: efuse-dna@c {
+					efuse_dna: efuse-dna@c {
-					reg = <0xc 0xc>;
+						reg = <0xc 0xc>;
-				};
+					};
-				efuse_usr0: efuse-usr0@20 {
+					efuse_usr0: efuse-usr0@20 {
-					reg = <0x20 0x4>;
+						reg = <0x20 0x4>;
-				};
+					};
-				efuse_usr1: efuse-usr1@24 {
+					efuse_usr1: efuse-usr1@24 {
-					reg = <0x24 0x4>;
+						reg = <0x24 0x4>;
-				};
+					};
-				efuse_usr2: efuse-usr2@28 {
+					efuse_usr2: efuse-usr2@28 {
-					reg = <0x28 0x4>;
+						reg = <0x28 0x4>;
-				};
+					};
-				efuse_usr3: efuse-usr3@2c {
+					efuse_usr3: efuse-usr3@2c {
-					reg = <0x2c 0x4>;
+						reg = <0x2c 0x4>;
-				};
+					};
-				efuse_usr4: efuse-usr4@30 {
+					efuse_usr4: efuse-usr4@30 {
-					reg = <0x30 0x4>;
+						reg = <0x30 0x4>;
-				};
+					};
-				efuse_usr5: efuse-usr5@34 {
+					efuse_usr5: efuse-usr5@34 {
-					reg = <0x34 0x4>;
+						reg = <0x34 0x4>;
-				};
+					};
-				efuse_usr6: efuse-usr6@38 {
+					efuse_usr6: efuse-usr6@38 {
-					reg = <0x38 0x4>;
+						reg = <0x38 0x4>;
-				};
+					};
-				efuse_usr7: efuse-usr7@3c {
+					efuse_usr7: efuse-usr7@3c {
-					reg = <0x3c 0x4>;
+						reg = <0x3c 0x4>;
-				};
+					};
-				efuse_miscusr: efuse-miscusr@40 {
+					efuse_miscusr: efuse-miscusr@40 {
-					reg = <0x40 0x4>;
+						reg = <0x40 0x4>;
-				};
+					};
-				efuse_chash: efuse-chash@50 {
+					efuse_chash: efuse-chash@50 {
-					reg = <0x50 0x4>;
+						reg = <0x50 0x4>;
-				};
+					};
-				efuse_pufmisc: efuse-pufmisc@54 {
+					efuse_pufmisc: efuse-pufmisc@54 {
-					reg = <0x54 0x4>;
+						reg = <0x54 0x4>;
-				};
+					};
-				efuse_sec: efuse-sec@58 {
+					efuse_sec: efuse-sec@58 {
-					reg = <0x58 0x4>;
+						reg = <0x58 0x4>;
-				};
+					};
-				efuse_spkid: efuse-spkid@5c {
+					efuse_spkid: efuse-spkid@5c {
-					reg = <0x5c 0x4>;
+						reg = <0x5c 0x4>;
-				};
+					};
-				efuse_aeskey: efuse-aeskey@60 {
+					efuse_aeskey: efuse-aeskey@60 {
-					reg = <0x60 0x20>;
+						reg = <0x60 0x20>;
-				};
+					};
-				efuse_ppk0hash: efuse-ppk0hash@a0 {
+					efuse_ppk0hash: efuse-ppk0hash@a0 {
-					reg = <0xa0 0x30>;
+						reg = <0xa0 0x30>;
-				};
+					};
-				efuse_ppk1hash: efuse-ppk1hash@d0 {
+					efuse_ppk1hash: efuse-ppk1hash@d0 {
-					reg = <0xd0 0x30>;
+						reg = <0xd0 0x30>;
-				};
+					};
-				efuse_pufuser: efuse-pufuser@100 {
+					efuse_pufuser: efuse-pufuser@100 {
-					reg = <0x100 0x7F>;
+						reg = <0x100 0x7F>;
+					};
 				};
 			};
 
@@ -303,11 +306,7 @@
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	edac {
+	fpga_full: fpga-region {
-		compatible = "arm,cortex-a53-edac";
-	};
-
-	fpga_full: fpga-full {
 		compatible = "fpga-region";
 		fpga-mgr = <&zynqmp_pcap>;
 		#address-cells = <2>;

board/xilinx/zynqmp/zynqmp.c

@@ -18,6 +18,7 @@
 #include <ahci.h>
 #include <scsi.h>
 #include <soc.h>
+#include <spl.h>
 #include <malloc.h>
 #include <memalign.h>
 #include <wdt.h>

configs/xilinx_versal_mini_ospi_defconfig

@@ -16,6 +16,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_VERSAL_NO_DDR=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_LTO=y
 # CONFIG_EXPERT is not set
 CONFIG_REMAKE_ELF=y
 # CONFIG_AUTOBOOT is not set

configs/xilinx_versal_mini_qspi_defconfig

@@ -14,6 +14,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_VERSAL_NO_DDR=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_LTO=y
 # CONFIG_EXPERT is not set
 CONFIG_REMAKE_ELF=y
 # CONFIG_AUTOBOOT is not set

configs/xilinx_versal_net_mini_ospi_defconfig

@@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single"
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_SYS_LOAD_ADDR=0xBBF80000
+CONFIG_LTO=y
 # CONFIG_EXPERT is not set
 CONFIG_REMAKE_ELF=y
 # CONFIG_AUTOBOOT is not set

configs/xilinx_versal_net_mini_qspi_defconfig

@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single"
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_SYS_LOAD_ADDR=0xBBF80000
+CONFIG_LTO=y
 # CONFIG_EXPERT is not set
 CONFIG_REMAKE_ELF=y
 # CONFIG_AUTOBOOT is not set

configs/xilinx_versal_net_virt_defconfig

@@ -146,3 +146,4 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_NET=y
 CONFIG_VIRTIO_BLK=y
 CONFIG_TPM=y
+CONFIG_EFI_HTTP_BOOT=y

configs/xilinx_versal_virt_defconfig

@@ -153,3 +153,4 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_NET=y
 CONFIG_VIRTIO_BLK=y
 CONFIG_TPM=y
+CONFIG_EFI_HTTP_BOOT=y

configs/xilinx_zynqmp_kria_defconfig

@@ -224,3 +224,4 @@ CONFIG_EFI_SET_TIME=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_HTTP_BOOT=y

configs/xilinx_zynqmp_virt_defconfig

@@ -242,3 +242,4 @@ CONFIG_EFI_SET_TIME=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_HTTP_BOOT=y

drivers/soc/soc_xilinx_zynqmp.c

@@ -35,13 +35,15 @@ static const char zynqmp_family[] = "ZynqMP";
 #define IDCODE2_PL_INIT_SHIFT	9
 #define IDCODE2_PL_INIT_MASK	BIT(IDCODE2_PL_INIT_SHIFT)
 
-#define ZYNQMP_VERSION_SIZE	7
+#define ZYNQMP_VERSION_SIZE	10
 
 enum {
 	ZYNQMP_VARIANT_EG = BIT(0),
 	ZYNQMP_VARIANT_EV = BIT(1),
 	ZYNQMP_VARIANT_CG = BIT(2),
 	ZYNQMP_VARIANT_DR = BIT(3),
+	ZYNQMP_VARIANT_DR_SE = BIT(4),
+	ZYNQMP_VARIANT_EG_SE = BIT(5),
 };
 
 struct zynqmp_device {
@@ -105,6 +107,11 @@ static const struct zynqmp_device zynqmp_devices[] = {
 		.device = 11,
 		.variants = ZYNQMP_VARIANT_EG,
 	},
+	{
+		.id = 0x04741093,
+		.device = 11,
+		.variants = ZYNQMP_VARIANT_EG_SE,
+	},
 	{
 		.id = 0x04750093,
 		.device = 15,
@@ -120,6 +127,11 @@ static const struct zynqmp_device zynqmp_devices[] = {
 		.device = 19,
 		.variants = ZYNQMP_VARIANT_EG,
 	},
+	{
+		.id = 0x0475C093,
+		.device = 19,
+		.variants = ZYNQMP_VARIANT_EG_SE,
+	},
 	{
 		.id = 0x047E1093,
 		.device = 21,
@@ -170,6 +182,11 @@ static const struct zynqmp_device zynqmp_devices[] = {
 		.device = 47,
 		.variants = ZYNQMP_VARIANT_DR,
 	},
+	{
+		.id = 0x047FA093,
+		.device = 47,
+		.variants = ZYNQMP_VARIANT_DR_SE,
+	},
 	{
 		.id = 0x047FB093,
 		.device = 48,
@@ -185,6 +202,11 @@ static const struct zynqmp_device zynqmp_devices[] = {
 		.device = 67,
 		.variants = ZYNQMP_VARIANT_DR,
 	},
+	{
+		.id = 0x046d7093,
+		.device = 67,
+		.variants = ZYNQMP_VARIANT_DR_SE,
+	},
 	{
 		.id = 0x04712093,
 		.device = 24,
@@ -271,8 +293,12 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
 			"cg" : "eg", sizeof(priv->machine));
 	} else if (device->variants & ZYNQMP_VARIANT_EG) {
 		strlcat(priv->machine, "eg", sizeof(priv->machine));
+	} else if (device->variants & ZYNQMP_VARIANT_EG_SE) {
+		strlcat(priv->machine, "eg_SE", sizeof(priv->machine));
 	} else if (device->variants & ZYNQMP_VARIANT_DR) {
 		strlcat(priv->machine, "dr", sizeof(priv->machine));
+	} else if (device->variants & ZYNQMP_VARIANT_DR_SE) {
+		strlcat(priv->machine, "dr_SE", sizeof(priv->machine));
 	}
 
 	return 0;

include/configs/xilinx_versal_net.h

@@ -16,8 +16,8 @@
 /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
 
 /* Generic Interrupt Controller Definitions */
-#define GICD_BASE	0xF9000000
+#define GICD_BASE	0xe2000000
-#define GICR_BASE	0xF9060000
+#define GICR_BASE	0xe2060000
 
 /* Serial setup */
 #define CFG_SYS_BAUDRATE_TABLE \