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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

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This commit is contained in:
Tom Rini 2018-06-22 13:12:53 -04:00
commit 77b5ba5d2b
13 changed files with 60 additions and 54 deletions
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4
arch/arm/dts/uniphier-ld11.dtsi
View file

@ -124,7 +124,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <58820000>;
resets = <&peri_rst 0>;
};
@ -136,7 +135,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <58820000>;
resets = <&peri_rst 1>;
};
@ -148,7 +146,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <58820000>;
resets = <&peri_rst 2>;
};
@ -160,7 +157,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <58820000>;
resets = <&peri_rst 3>;
};

4
arch/arm/dts/uniphier-ld20.dtsi
View file

@ -230,7 +230,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <58820000>;
resets = <&peri_rst 0>;
};
@ -242,7 +241,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <58820000>;
resets = <&peri_rst 1>;
};
@ -254,7 +252,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <58820000>;
resets = <&peri_rst 2>;
};
@ -266,7 +263,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <58820000>;
resets = <&peri_rst 3>;
};

4
arch/arm/dts/uniphier-ld4.dtsi
View file

@ -71,7 +71,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <36864000>;
resets = <&peri_rst 0>;
};
@ -83,7 +82,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <36864000>;
resets = <&peri_rst 1>;
};
@ -95,7 +93,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <36864000>;
resets = <&peri_rst 2>;
};
@ -107,7 +104,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <36864000>;
resets = <&peri_rst 3>;
};

6
arch/arm/dts/uniphier-pro4.dtsi
View file

@ -79,7 +79,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <73728000>;
resets = <&peri_rst 0>;
};
@ -91,7 +90,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <73728000>;
resets = <&peri_rst 1>;
};
@ -103,7 +101,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <73728000>;
resets = <&peri_rst 2>;
};
@ -115,7 +112,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <73728000>;
resets = <&peri_rst 3>;
};
@ -429,7 +425,7 @@
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "gio", "ether", "ether-gb", "ether-phy";
clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
<&sys_clk 10>;
<&sys_clk 10>;
reset-names = "gio", "ether";
resets = <&sys_rst 12>, <&sys_rst 6>;
phy-mode = "rgmii";

4
arch/arm/dts/uniphier-pro5.dtsi
View file

@ -164,7 +164,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <73728000>;
resets = <&peri_rst 0>;
};
@ -176,7 +175,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <73728000>;
resets = <&peri_rst 1>;
};
@ -188,7 +186,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <73728000>;
resets = <&peri_rst 2>;
};
@ -200,7 +197,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <73728000>;
resets = <&peri_rst 3>;
};

4
arch/arm/dts/uniphier-pxs2.dtsi
View file

@ -172,7 +172,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <88900000>;
resets = <&peri_rst 0>;
};
@ -184,7 +183,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <88900000>;
resets = <&peri_rst 1>;
};
@ -196,7 +194,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <88900000>;
resets = <&peri_rst 2>;
};
@ -208,7 +205,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <88900000>;
resets = <&peri_rst 3>;
};

4
arch/arm/dts/uniphier-pxs3-ref.dts
View file

@ -75,6 +75,10 @@
status = "okay";
};
&sd {
status = "okay";
};
&eth0 {
status = "okay";
phy-handle = <&ethphy0>;

4
arch/arm/dts/uniphier-pxs3.dtsi
View file

@ -152,7 +152,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <58820000>;
resets = <&peri_rst 0>;
};
@ -164,7 +163,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <58820000>;
resets = <&peri_rst 1>;
};
@ -176,7 +174,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <58820000>;
resets = <&peri_rst 2>;
};
@ -188,7 +185,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <58820000>;
resets = <&peri_rst 3>;
};

4
arch/arm/dts/uniphier-sld8.dtsi
View file

@ -71,7 +71,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <80000000>;
resets = <&peri_rst 0>;
};
@ -83,7 +82,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <80000000>;
resets = <&peri_rst 1>;
};
@ -95,7 +93,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <80000000>;
resets = <&peri_rst 2>;
};
@ -107,7 +104,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <80000000>;
resets = <&peri_rst 3>;
};

6
configs/uniphier_v7_defconfig
View file

@ -42,10 +42,8 @@ CONFIG_NAND=y
CONFIG_NAND_DENALI_DT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x0
CONFIG_SMC911X_32_BIT=y
CONFIG_DM_ETH=y
CONFIG_SNI_AVE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y

6
configs/uniphier_v8_defconfig
View file

@ -39,10 +39,8 @@ CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_NAND=y
CONFIG_NAND_DENALI_DT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x0
CONFIG_SMC911X_32_BIT=y
CONFIG_DM_ETH=y
CONFIG_SNI_AVE=y
CONFIG_PINCONF=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y

13
drivers/reset/reset-uniphier.c
View file

@ -71,7 +71,7 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
UNIPHIER_RESETX(6, 0x200c, 6), /* ETHER */
UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */
UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */
UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
@ -85,10 +85,13 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
UNIPHIER_RESETX(6, 0x200c, 9), /* ETHER0 */
UNIPHIER_RESETX(7, 0x200c, 10), /* ETHER1 */
UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
UNIPHIER_RESETX(12, 0x200c, 5), /* USB30 (GIO0) */
UNIPHIER_RESETX(13, 0x200c, 6), /* USB31 (GIO1) */
UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY */
UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY */
UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */
UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */
UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */
UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */
UNIPHIER_RESET_END,
};

51
drivers/serial/serial_uniphier.c
View file

@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
#include <linux/bug.h>
#include <linux/io.h>
#include <linux/serial_reg.h>
#include <linux/sizes.h>
@ -33,17 +34,17 @@ struct uniphier_serial {
u32 dlr; /* Divisor Latch Register */
};
struct uniphier_serial_private_data {
struct uniphier_serial_priv {
struct uniphier_serial __iomem *membase;
unsigned int uartclk;
};
#define uniphier_serial_port(dev) \
((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase
((struct uniphier_serial_priv *)dev_get_priv(dev))->membase
static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
{
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial_priv *priv = dev_get_priv(dev);
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
const unsigned int mode_x_div = 16;
unsigned int divisor;
@ -87,11 +88,34 @@ static int uniphier_serial_pending(struct udevice *dev, bool input)
return !(readl(&port->lsr) & UART_LSR_THRE);
}
/*
* SPL does not have enough memory footprint for the clock driver.
* Hardcode clock frequency for each SoC.
*/
struct uniphier_serial_clk_data {
const char *compatible;
unsigned int clk_rate;
};
static const struct uniphier_serial_clk_data uniphier_serial_clk_data[] = {
{ .compatible = "socionext,uniphier-ld4", .clk_rate = 36864000 },
{ .compatible = "socionext,uniphier-pro4", .clk_rate = 73728000 },
{ .compatible = "socionext,uniphier-sld8", .clk_rate = 80000000 },
{ .compatible = "socionext,uniphier-pro5", .clk_rate = 73728000 },
{ .compatible = "socionext,uniphier-pxs2", .clk_rate = 88888888 },
{ .compatible = "socionext,uniphier-ld6b", .clk_rate = 88888888 },
{ .compatible = "socionext,uniphier-ld11", .clk_rate = 58823529 },
{ .compatible = "socionext,uniphier-ld20", .clk_rate = 58823529 },
{ .compatible = "socionext,uniphier-pxs3", .clk_rate = 58823529 },
{ /* sentinel */ },
};
static int uniphier_serial_probe(struct udevice *dev)
{
DECLARE_GLOBAL_DATA_PTR;
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial_priv *priv = dev_get_priv(dev);
struct uniphier_serial __iomem *port;
const struct uniphier_serial_clk_data *clk_data;
ofnode root_node;
fdt_addr_t base;
u32 tmp;
@ -105,8 +129,19 @@ static int uniphier_serial_probe(struct udevice *dev)
priv->membase = port;
priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
root_node = ofnode_path("/");
clk_data = uniphier_serial_clk_data;
while (clk_data->compatible) {
if (ofnode_device_is_compatible(root_node,
clk_data->compatible))
break;
clk_data++;
}
if (WARN_ON(!clk_data->compatible))
return -ENOTSUPP;
priv->uartclk = clk_data->clk_rate;
tmp = readl(&port->lcr_mcr);
tmp &= ~LCR_MASK;
@ -133,6 +168,6 @@ U_BOOT_DRIVER(uniphier_serial) = {
.id = UCLASS_SERIAL,
.of_match = uniphier_uart_of_match,
.probe = uniphier_serial_probe,
.priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data),
.priv_auto_alloc_size = sizeof(struct uniphier_serial_priv),
.ops = &uniphier_serial_ops,
};