mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-01-11 20:59:01 +00:00
- stm32mp: fix command stboard
- stm32mp: update kernel device tree according the part number - stm32mp: add 800 MHz profile support = stm32mp15xd and stm32mp15xf - stm32mp: set cp15 frequency in psci cpu on - stm32mp: DT alignment with Linux 5.6-rc1 - stm32mp: clk: add SPI5 support and correct CKSELR masks - stm32mp: ram: fixes on LPDDR2/LPDDR3 support and on tuning - stm32: i2c: allows for any bus frequency - sti: timer: livetree and clk API conversion -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAl56C0cACgkQ4rK92eCq k3VlEwgAgOnfIG1WLj+WSUUHmPrglfw0WfoP2Uh7ReZEzaUfuyRfw4/65rtKJri+ 4WhT+Az+GO8oblL7557U0QCFYHCw97WpTHu/uQ0CZzr72JWRnArlWwwgQq2vFok5 CBfJ/BDCK72RYUcvNHPOh1wRpS+JIRO8d6HdwbiahBHfxP4J+yWII63VpE4K1Zd7 IDXK3H20jVCTG7jdrHNCaScHWme1qsh8HH132oGRlnf6sxtApxJO7dbV0etY15XF U1mipAxMoJMIF7utc9GoNia2Tvyi+ZYDjiKCljKwdMW+ebvTulUcikOcXO/aufGo 3nsyv7W6iMfxcK/4aFkQUOCLADY96Q== =OXic -----END PGP SIGNATURE----- Merge tag 'u-boot-stm32-20200324' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm into next - stm32mp: fix command stboard - stm32mp: update kernel device tree according the part number - stm32mp: add 800 MHz profile support = stm32mp15xd and stm32mp15xf - stm32mp: set cp15 frequency in psci cpu on - stm32mp: DT alignment with Linux 5.6-rc1 - stm32mp: clk: add SPI5 support and correct CKSELR masks - stm32mp: ram: fixes on LPDDR2/LPDDR3 support and on tuning - stm32: i2c: allows for any bus frequency - sti: timer: livetree and clk API conversion
This commit is contained in:
Tom Rini
commit
779e6dc6a4
51 changed files with 3143 additions and 2205 deletions
|
|
@ -133,6 +133,7 @@
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|||
DDR_MR3
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||||
>;
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||||
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#ifdef DDR_PHY_CAL_SKIP
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st,phy-cal = <
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DDR_DX0DLLCR
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||||
DDR_DX0DQTR
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||||
|
|
@ -148,6 +149,8 @@
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DDR_DX3DQSTR
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>;
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#endif
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status = "okay";
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};
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};
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|
|
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1114
arch/arm/dts/stm32mp15-pinctrl.dtsi
Normal file
1114
arch/arm/dts/stm32mp15-pinctrl.dtsi
Normal file
File diff suppressed because it is too large
Load diff
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@ -20,12 +20,6 @@
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device_type = "cpu";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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psci {
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@ -155,6 +149,11 @@
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reg = <1>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers3: timer@40001000 {
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@ -184,6 +183,11 @@
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reg = <2>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers4: timer@40002000 {
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@ -211,6 +215,11 @@
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reg = <3>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers5: timer@40003000 {
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@ -240,6 +249,11 @@
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reg = <4>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers6: timer@40004000 {
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@ -596,6 +610,11 @@
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reg = <0>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers8: timer@44001000 {
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@ -627,6 +646,11 @@
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reg = <7>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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usart6: serial@44003000 {
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@ -930,33 +954,7 @@
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};
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};
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m_can1: can@4400e000 {
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compatible = "bosch,m_can";
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reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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m_can2: can@4400f000 {
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compatible = "bosch,m_can";
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reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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dma1: dma@48000000 {
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dma1: dma-controller@48000000 {
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compatible = "st,stm32-dma";
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reg = <0x48000000 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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@ -973,7 +971,7 @@
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dma-requests = <8>;
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};
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dma2: dma@48001000 {
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dma2: dma-controller@48001000 {
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compatible = "st,stm32-dma";
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reg = <0x48001000 0x400>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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@ -1041,8 +1039,8 @@
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x10153180>;
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reg = <0x48004000 0x400>;
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reg-names = "sdmmc";
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interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&rcc SDMMC3_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC3_R>;
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@ -1273,15 +1271,6 @@
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status = "disabled";
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};
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cryp1: cryp@54001000 {
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compatible = "st,stm32mp1-cryp";
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reg = <0x54001000 0x400>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc CRYP1>;
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resets = <&rcc CRYP1_R>;
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status = "disabled";
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};
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hash1: hash@54002000 {
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compatible = "st,stm32f756-hash";
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reg = <0x54002000 0x400>;
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@ -1302,7 +1291,7 @@
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status = "disabled";
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};
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mdma1: dma@58000000 {
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mdma1: dma-controller@58000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x58000000 0x1000>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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@ -1349,20 +1338,22 @@
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arm,primecell-periphid = <0x10153180>;
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reg = <0x58005000 0x1000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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interrupt-names = "cmd_irq";
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clocks = <&rcc SDMMC1_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC1_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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sdmmc2: sdmmc@58007000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x10153180>;
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reg = <0x58007000 0x1000>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&rcc SDMMC2_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC2_R>;
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@ -1406,6 +1397,7 @@
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st,syscon = <&syscfg 0x4>;
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snps,mixed-burst;
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snps,pbl = <2>;
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snps,en-tx-lpi-clockgating;
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snps,axi-config = <&stmmac_axi_config_0>;
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snps,tso;
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status = "disabled";
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@ -1430,26 +1422,6 @@
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status = "disabled";
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};
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gpu: gpu@59000000 {
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compatible = "vivante,gc";
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reg = <0x59000000 0x800>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc GPU>, <&rcc GPU_K>;
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clock-names = "bus" ,"core";
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resets = <&rcc GPU_R>;
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status = "disabled";
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};
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dsi: dsi@5a000000 {
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compatible = "st,stm32-dsi";
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reg = <0x5a000000 0x800>;
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clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
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clock-names = "pclk", "ref", "px_clk";
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resets = <&rcc DSI_R>;
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reset-names = "apb";
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status = "disabled";
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};
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ltdc: display-controller@5a001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x5a001000 0x400>;
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@ -1535,7 +1507,7 @@
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status = "disabled";
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};
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bsec: nvmem@5c005000 {
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bsec: efuse@5c005000 {
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compatible = "st,stm32mp15-bsec";
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reg = <0x5c005000 0x400>;
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#address-cells = <1>;
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@ -1560,12 +1532,172 @@
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#size-cells = <0>;
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status = "disabled";
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};
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/*
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* Break node order to solve dependency probe issue between
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* pinctrl and exti.
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*/
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pinctrl: pin-controller@50002000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp157-pinctrl";
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ranges = <0 0x50002000 0xa400>;
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interrupt-parent = <&exti>;
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st,syscfg = <&exti 0x60 0xff>;
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hwlocks = <&hwspinlock 0>;
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pins-are-numbered;
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gpioa: gpio@50002000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc GPIOA>;
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st,bank-name = "GPIOA";
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status = "disabled";
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};
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gpiob: gpio@50003000 {
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gpio-controller;
|
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc GPIOB>;
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st,bank-name = "GPIOB";
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status = "disabled";
|
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};
|
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|
||||
gpioc: gpio@50004000 {
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
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interrupt-controller;
|
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#interrupt-cells = <2>;
|
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reg = <0x2000 0x400>;
|
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clocks = <&rcc GPIOC>;
|
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st,bank-name = "GPIOC";
|
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status = "disabled";
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x400>;
|
||||
clocks = <&rcc GPIOD>;
|
||||
st,bank-name = "GPIOD";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x400>;
|
||||
clocks = <&rcc GPIOE>;
|
||||
st,bank-name = "GPIOE";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x400>;
|
||||
clocks = <&rcc GPIOF>;
|
||||
st,bank-name = "GPIOF";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x6000 0x400>;
|
||||
clocks = <&rcc GPIOG>;
|
||||
st,bank-name = "GPIOG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7000 0x400>;
|
||||
clocks = <&rcc GPIOH>;
|
||||
st,bank-name = "GPIOH";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x8000 0x400>;
|
||||
clocks = <&rcc GPIOI>;
|
||||
st,bank-name = "GPIOI";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x9000 0x400>;
|
||||
clocks = <&rcc GPIOJ>;
|
||||
st,bank-name = "GPIOJ";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xa000 0x400>;
|
||||
clocks = <&rcc GPIOK>;
|
||||
st,bank-name = "GPIOK";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-z-pinctrl";
|
||||
ranges = <0 0x54004000 0x400>;
|
||||
pins-are-numbered;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&exti 0x60 0xff>;
|
||||
hwlocks = <&hwspinlock 0>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x400>;
|
||||
clocks = <&rcc GPIOZ>;
|
||||
st,bank-name = "GPIOZ";
|
||||
st,bank-ioport = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mlahb {
|
||||
compatible = "simple-bus";
|
||||
mlahb: ahb {
|
||||
compatible = "st,mlahb", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges = <0x00000000 0x38000000 0x10000>,
|
||||
<0x10000000 0x10000000 0x60000>,
|
||||
<0x30000000 0x30000000 0x60000>;
|
||||
45
arch/arm/dts/stm32mp153.dtsi
Normal file
45
arch/arm/dts/stm32mp153.dtsi
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp151.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a7";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
m_can1: can@4400e000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m_can2: can@4400f000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load diff
31
arch/arm/dts/stm32mp157.dtsi
Normal file
31
arch/arm/dts/stm32mp157.dtsi
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp153.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
gpu: gpu@59000000 {
|
||||
compatible = "vivante,gc";
|
||||
reg = <0x59000000 0x800>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc GPU>, <&rcc GPU_K>;
|
||||
clock-names = "bus" ,"core";
|
||||
resets = <&rcc GPU_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi: dsi@5a000000 {
|
||||
compatible = "st,stm32-dsi";
|
||||
reg = <0x5a000000 0x800>;
|
||||
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
||||
clock-names = "pclk", "ref", "px_clk";
|
||||
resets = <&rcc DSI_R>;
|
||||
reset-names = "apb";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp157-u-boot.dtsi"
|
||||
#include "stm32mp15-u-boot.dtsi"
|
||||
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -145,7 +145,10 @@
|
|||
|
||||
&sdmmc1_b4_pins_a {
|
||||
u-boot,dm-spl;
|
||||
pins {
|
||||
pins1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
pins2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
|
@ -196,7 +199,3 @@
|
|||
u-boot,force-b-session-valid;
|
||||
hnp-srp-disable;
|
||||
};
|
||||
|
||||
&v3v3 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,8 +6,9 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157xac-pinctrl.dtsi"
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/st,stpmic1.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp157-u-boot.dtsi"
|
||||
#include "stm32mp15-u-boot.dtsi"
|
||||
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -164,7 +164,10 @@
|
|||
|
||||
&sdmmc1_b4_pins_a {
|
||||
u-boot,dm-spl;
|
||||
pins {
|
||||
pins1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
pins2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,10 +6,10 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157xac-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/st,stpmic1.h>
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include "stm32mp15xx-dkx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
|
||||
|
|
@ -23,537 +23,4 @@
|
|||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mcuram2: mcuram2@10000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring0: vdev0vring0@10040000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10040000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring1: vdev0vring1@10041000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10041000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0buffer: vdev0buffer@10042000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10042000 0x4000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcuram: mcuram@30000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x30000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
retram: retram@38000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x38000000 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
gpu_reserved: gpu@d4000000 {
|
||||
reg = <0xd4000000 0x4000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
led {
|
||||
compatible = "gpio-leds";
|
||||
blue {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "STM32MP1-DK";
|
||||
routing =
|
||||
"Playback" , "MCLK",
|
||||
"Capture" , "MCLK",
|
||||
"MICL" , "Mic Bias";
|
||||
dais = <&sai2a_port &sai2b_port &i2s2_port>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
|
||||
vdd-supply = <&vdd>;
|
||||
vdda-supply = <&vdd>;
|
||||
vref-supply = <&vrefbuf>;
|
||||
status = "disabled";
|
||||
adc1: adc@0 {
|
||||
/*
|
||||
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
|
||||
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
|
||||
* 5 * (56 + 47kOhms) * 5pF => 2.5us.
|
||||
* Use arbitrary margin here (e.g. 5us).
|
||||
*/
|
||||
st,min-sample-time-nsecs = <5000>;
|
||||
/* AIN connector, USB Type-C CC1 & CC2 */
|
||||
st,adc-channels = <0 1 6 13 18 19>;
|
||||
status = "okay";
|
||||
};
|
||||
adc2: adc@100 {
|
||||
/* AIN connector, USB Type-C CC1 & CC2 */
|
||||
st,adc-channels = <0 1 2 6 18 19>;
|
||||
st,min-sample-time-nsecs = <5000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&cec {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cec_pins_b>;
|
||||
pinctrl-1 = <&cec_pins_sleep_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
||||
pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
phy-mode = "rgmii-id";
|
||||
max-speed = <1000>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
contiguous-area = <&gpu_reserved>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
pinctrl-1 = <&i2c1_pins_sleep_a>;
|
||||
i2c-scl-rising-time-ns = <100>;
|
||||
i2c-scl-falling-time-ns = <7>;
|
||||
status = "okay";
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
hdmi-transmitter@39 {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
iovcc-supply = <&v3v3_hdmi>;
|
||||
cvcc12-supply = <&v1v2_hdmi>;
|
||||
reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpiog>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
sii9022_in: endpoint {
|
||||
remote-endpoint = <<dc_ep0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
sii9022_tx_endpoint: endpoint {
|
||||
remote-endpoint = <&i2s2_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cs42l51: cs42l51@4a {
|
||||
compatible = "cirrus,cs42l51";
|
||||
reg = <0x4a>;
|
||||
#sound-dai-cells = <0>;
|
||||
VL-supply = <&v3v3>;
|
||||
VD-supply = <&v1v8_audio>;
|
||||
VA-supply = <&v1v8_audio>;
|
||||
VAHP-supply = <&v1v8_audio>;
|
||||
reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&sai2a>;
|
||||
clock-names = "MCLK";
|
||||
status = "okay";
|
||||
|
||||
cs42l51_port: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cs42l51_tx_endpoint: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&sai2a_endpoint>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
|
||||
cs42l51_rx_endpoint: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&sai2b_endpoint>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
typec: stusb1600@28 {
|
||||
compatible = "st,stusb1600";
|
||||
reg = <0x28>;
|
||||
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&stusb1600_pins_a>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
typec_con: connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
power-role = "sink";
|
||||
power-opmode = "default";
|
||||
};
|
||||
};
|
||||
|
||||
pmic: stpmic@33 {
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_ddr: buck2 {
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd: buck3 {
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
v3v3: buck4 {
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
};
|
||||
|
||||
v1v8_audio: ldo1 {
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO1 0>;
|
||||
};
|
||||
|
||||
v3v3_hdmi: ldo2 {
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO2 0>;
|
||||
};
|
||||
|
||||
vtt_ddr: ldo3 {
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_usb: ldo4 {
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
interrupts = <IT_CURLIM_LDO4 0>;
|
||||
};
|
||||
|
||||
vdda: ldo5 {
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
interrupts = <IT_CURLIM_LDO5 0>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v2_hdmi: ldo6 {
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO6 0>;
|
||||
};
|
||||
|
||||
vref_ddr: vref_ddr {
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
bst_out: boost {
|
||||
regulator-name = "bst_out";
|
||||
interrupts = <IT_OCP_BOOST 0>;
|
||||
};
|
||||
|
||||
vbus_otg: pwr_sw1 {
|
||||
regulator-name = "vbus_otg";
|
||||
interrupts = <IT_OCP_OTG 0>;
|
||||
};
|
||||
|
||||
vbus_sw: pwr_sw2 {
|
||||
regulator-name = "vbus_sw";
|
||||
interrupts = <IT_OCP_SWOUT 0>;
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
onkey {
|
||||
compatible = "st,stpmic1-onkey";
|
||||
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
||||
interrupt-names = "onkey-falling", "onkey-rising";
|
||||
power-off-time-sec = <10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "st,stpmic1-wdt";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
||||
clock-names = "pclk", "i2sclk", "x8k", "x11k";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2s2_pins_a>;
|
||||
pinctrl-1 = <&i2s2_pins_sleep_a>;
|
||||
status = "okay";
|
||||
|
||||
i2s2_port: port {
|
||||
i2s2_endpoint: endpoint {
|
||||
remote-endpoint = <&sii9022_tx_endpoint>;
|
||||
format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
<dc {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <<dc_pins_a>;
|
||||
pinctrl-1 = <<dc_pins_sleep_a>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ltdc_ep0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&sii9022_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&m4_rproc {
|
||||
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
||||
<&vdev0vring1>, <&vdev0buffer>;
|
||||
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
||||
mbox-names = "vq0", "vq1", "shutdown";
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <68 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwr_regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
||||
clock-names = "pclk", "x8k", "x11k";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
|
||||
pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
|
||||
status = "okay";
|
||||
|
||||
sai2a: audio-controller@4400b004 {
|
||||
#clock-cells = <0>;
|
||||
dma-names = "tx";
|
||||
clocks = <&rcc SAI2_K>;
|
||||
clock-names = "sai_ck";
|
||||
status = "okay";
|
||||
|
||||
sai2a_port: port {
|
||||
sai2a_endpoint: endpoint {
|
||||
remote-endpoint = <&cs42l51_tx_endpoint>;
|
||||
format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sai2b: audio-controller@4400b024 {
|
||||
dma-names = "rx";
|
||||
st,sync = <&sai2a 2>;
|
||||
clocks = <&rcc SAI2_K>, <&sai2a>;
|
||||
clock-names = "sai_ck", "MCLK";
|
||||
status = "okay";
|
||||
|
||||
sai2b_port: port {
|
||||
sai2b_endpoint: endpoint {
|
||||
remote-endpoint = <&cs42l51_rx_endpoint>;
|
||||
format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>;
|
||||
phy-names = "usb";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
dr_mode = "peripheral";
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&vrefbuf {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vdda-supply = <&vdd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,9 +4,3 @@
|
|||
*/
|
||||
|
||||
#include "stm32mp157a-dk1-u-boot.dtsi"
|
||||
|
||||
&i2c1 {
|
||||
hdmi-transmitter@39 {
|
||||
reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,11 +6,24 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157a-dk1.dts"
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15xc.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include "stm32mp15xx-dkx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
|
||||
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ðernet0;
|
||||
serial0 = &uart4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&dsi {
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp157-u-boot.dtsi"
|
||||
#include "stm32mp15-u-boot.dtsi"
|
||||
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -161,7 +161,10 @@
|
|||
|
||||
&sdmmc1_b4_pins_a {
|
||||
u-boot,dm-spl;
|
||||
pins {
|
||||
pins1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
pins2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,8 +5,10 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157xaa-pinctrl.dtsi"
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15xc.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxaa-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/st,stpmic1.h>
|
||||
|
||||
|
|
@ -89,6 +91,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
/* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
|
||||
pinctrl-0 = <&adc1_in6_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
vdd-supply = <&vdd>;
|
||||
vdda-supply = <&vdda>;
|
||||
vref-supply = <&vdda>;
|
||||
status = "disabled";
|
||||
adc1: adc@0 {
|
||||
st,adc-channels = <0 1 6>;
|
||||
/* 16.5 ck_cycles sampling time */
|
||||
st,min-sample-time-nsecs = <400>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&dac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
|
||||
|
|
|
|||
|
|
@ -182,8 +182,6 @@
|
|||
|
||||
ov5640: camera@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ov5640_pins>;
|
||||
reg = <0x3c>;
|
||||
clocks = <&clk_ext_camera>;
|
||||
clock-names = "xclk";
|
||||
|
|
@ -224,12 +222,6 @@
|
|||
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
ov5640_pins: camera {
|
||||
pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */
|
||||
drive-push-pull;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -291,6 +283,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
&sdmmc3 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
|
|
@ -304,7 +308,8 @@
|
|||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm2_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-1 = <&pwm2_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@1 {
|
||||
|
|
@ -318,7 +323,8 @@
|
|||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm8_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-1 = <&pwm8_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@7 {
|
||||
|
|
@ -332,7 +338,8 @@
|
|||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm12_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-1 = <&pwm12_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@11 {
|
||||
|
|
@ -348,6 +355,7 @@
|
|||
&usbotg_hs {
|
||||
dr_mode = "peripheral";
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,90 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@50002000 {
|
||||
st,package = <STM32MP_PKG_AA>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
st,package = <STM32MP_PKG_AA>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@50002000 {
|
||||
st,package = <STM32MP_PKG_AB>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <6>;
|
||||
gpio-ranges = <&pinctrl 6 86 6>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl 6 102 10>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <2>;
|
||||
gpio-ranges = <&pinctrl 0 112 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@50002000 {
|
||||
st,package = <STM32MP_PKG_AC>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
st,package = <STM32MP_PKG_AC>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@50002000 {
|
||||
st,package = <STM32MP_PKG_AD>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <6>;
|
||||
gpio-ranges = <&pinctrl 6 86 6>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl 6 102 10>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <2>;
|
||||
gpio-ranges = <&pinctrl 0 112 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
18
arch/arm/dts/stm32mp15xc.dtsi
Normal file
18
arch/arm/dts/stm32mp15xc.dtsi
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp1: cryp@54001000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54001000 0x400>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp157-u-boot.dtsi"
|
||||
#include "stm32mp15-u-boot.dtsi"
|
||||
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -196,7 +196,10 @@
|
|||
|
||||
&sdmmc1_b4_pins_a {
|
||||
u-boot,dm-spl;
|
||||
pins {
|
||||
pins1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
pins2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,8 +4,10 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157xaa-pinctrl.dtsi"
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15xc.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxaa-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/st,stpmic1.h>
|
||||
|
||||
|
|
|
|||
639
arch/arm/dts/stm32mp15xx-dkx.dtsi
Normal file
639
arch/arm/dts/stm32mp15xx-dkx.dtsi
Normal file
|
|
@ -0,0 +1,639 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/st,stpmic1.h>
|
||||
|
||||
/ {
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mcuram2: mcuram2@10000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring0: vdev0vring0@10040000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10040000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring1: vdev0vring1@10041000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10041000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0buffer: vdev0buffer@10042000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10042000 0x4000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcuram: mcuram@30000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x30000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
retram: retram@38000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x38000000 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
gpu_reserved: gpu@d4000000 {
|
||||
reg = <0xd4000000 0x4000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
led {
|
||||
compatible = "gpio-leds";
|
||||
blue {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "STM32MP1-DK";
|
||||
routing =
|
||||
"Playback" , "MCLK",
|
||||
"Capture" , "MCLK",
|
||||
"MICL" , "Mic Bias";
|
||||
dais = <&sai2a_port &sai2b_port &i2s2_port>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
|
||||
vdd-supply = <&vdd>;
|
||||
vdda-supply = <&vdd>;
|
||||
vref-supply = <&vrefbuf>;
|
||||
status = "disabled";
|
||||
adc1: adc@0 {
|
||||
/*
|
||||
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
|
||||
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
|
||||
* 5 * (56 + 47kOhms) * 5pF => 2.5us.
|
||||
* Use arbitrary margin here (e.g. 5us).
|
||||
*/
|
||||
st,min-sample-time-nsecs = <5000>;
|
||||
/* AIN connector, USB Type-C CC1 & CC2 */
|
||||
st,adc-channels = <0 1 6 13 18 19>;
|
||||
status = "okay";
|
||||
};
|
||||
adc2: adc@100 {
|
||||
/* AIN connector, USB Type-C CC1 & CC2 */
|
||||
st,adc-channels = <0 1 2 6 18 19>;
|
||||
st,min-sample-time-nsecs = <5000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&cec {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cec_pins_b>;
|
||||
pinctrl-1 = <&cec_pins_sleep_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
||||
pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
phy-mode = "rgmii-id";
|
||||
max-speed = <1000>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
contiguous-area = <&gpu_reserved>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
pinctrl-1 = <&i2c1_pins_sleep_a>;
|
||||
i2c-scl-rising-time-ns = <100>;
|
||||
i2c-scl-falling-time-ns = <7>;
|
||||
status = "okay";
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
hdmi-transmitter@39 {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
iovcc-supply = <&v3v3_hdmi>;
|
||||
cvcc12-supply = <&v1v2_hdmi>;
|
||||
reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpiog>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
sii9022_in: endpoint {
|
||||
remote-endpoint = <<dc_ep0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
sii9022_tx_endpoint: endpoint {
|
||||
remote-endpoint = <&i2s2_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cs42l51: cs42l51@4a {
|
||||
compatible = "cirrus,cs42l51";
|
||||
reg = <0x4a>;
|
||||
#sound-dai-cells = <0>;
|
||||
VL-supply = <&v3v3>;
|
||||
VD-supply = <&v1v8_audio>;
|
||||
VA-supply = <&v1v8_audio>;
|
||||
VAHP-supply = <&v1v8_audio>;
|
||||
reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&sai2a>;
|
||||
clock-names = "MCLK";
|
||||
status = "okay";
|
||||
|
||||
cs42l51_port: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cs42l51_tx_endpoint: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&sai2a_endpoint>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
|
||||
cs42l51_rx_endpoint: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&sai2b_endpoint>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
typec: stusb1600@28 {
|
||||
compatible = "st,stusb1600";
|
||||
reg = <0x28>;
|
||||
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&stusb1600_pins_a>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
typec_con: connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
power-role = "sink";
|
||||
power-opmode = "default";
|
||||
};
|
||||
};
|
||||
|
||||
pmic: stpmic@33 {
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_ddr: buck2 {
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd: buck3 {
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
v3v3: buck4 {
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
};
|
||||
|
||||
v1v8_audio: ldo1 {
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO1 0>;
|
||||
};
|
||||
|
||||
v3v3_hdmi: ldo2 {
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO2 0>;
|
||||
};
|
||||
|
||||
vtt_ddr: ldo3 {
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_usb: ldo4 {
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
interrupts = <IT_CURLIM_LDO4 0>;
|
||||
};
|
||||
|
||||
vdda: ldo5 {
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
interrupts = <IT_CURLIM_LDO5 0>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v2_hdmi: ldo6 {
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO6 0>;
|
||||
};
|
||||
|
||||
vref_ddr: vref_ddr {
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
bst_out: boost {
|
||||
regulator-name = "bst_out";
|
||||
interrupts = <IT_OCP_BOOST 0>;
|
||||
};
|
||||
|
||||
vbus_otg: pwr_sw1 {
|
||||
regulator-name = "vbus_otg";
|
||||
interrupts = <IT_OCP_OTG 0>;
|
||||
};
|
||||
|
||||
vbus_sw: pwr_sw2 {
|
||||
regulator-name = "vbus_sw";
|
||||
interrupts = <IT_OCP_SWOUT 0>;
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
onkey {
|
||||
compatible = "st,stpmic1-onkey";
|
||||
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
||||
interrupt-names = "onkey-falling", "onkey-rising";
|
||||
power-off-time-sec = <10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "st,stpmic1-wdt";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
||||
clock-names = "pclk", "i2sclk", "x8k", "x11k";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2s2_pins_a>;
|
||||
pinctrl-1 = <&i2s2_pins_sleep_a>;
|
||||
status = "okay";
|
||||
|
||||
i2s2_port: port {
|
||||
i2s2_endpoint: endpoint {
|
||||
remote-endpoint = <&sii9022_tx_endpoint>;
|
||||
format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
<dc {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <<dc_pins_a>;
|
||||
pinctrl-1 = <<dc_pins_sleep_a>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ltdc_ep0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&sii9022_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&m4_rproc {
|
||||
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
||||
<&vdev0vring1>, <&vdev0buffer>;
|
||||
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
||||
mbox-names = "vq0", "vq1", "shutdown";
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <68 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwr_regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
||||
clock-names = "pclk", "x8k", "x11k";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
|
||||
pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
|
||||
status = "okay";
|
||||
|
||||
sai2a: audio-controller@4400b004 {
|
||||
#clock-cells = <0>;
|
||||
dma-names = "tx";
|
||||
clocks = <&rcc SAI2_K>;
|
||||
clock-names = "sai_ck";
|
||||
status = "okay";
|
||||
|
||||
sai2a_port: port {
|
||||
sai2a_endpoint: endpoint {
|
||||
remote-endpoint = <&cs42l51_tx_endpoint>;
|
||||
format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sai2b: audio-controller@4400b024 {
|
||||
dma-names = "rx";
|
||||
st,sync = <&sai2a 2>;
|
||||
clocks = <&rcc SAI2_K>, <&sai2a>;
|
||||
clock-names = "sai_ck", "MCLK";
|
||||
status = "okay";
|
||||
|
||||
sai2b_port: port {
|
||||
sai2b_endpoint: endpoint {
|
||||
remote-endpoint = <&cs42l51_rx_endpoint>;
|
||||
format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc3 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers1 {
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm1_pins_a>;
|
||||
pinctrl-1 = <&pwm1_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers3 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm3_pins_a>;
|
||||
pinctrl-1 = <&pwm3_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@2 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers4 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
|
||||
pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@3 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers5 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm5_pins_a>;
|
||||
pinctrl-1 = <&pwm5_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@4 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers6 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
timer@5 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers12 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm12_pins_a>;
|
||||
pinctrl-1 = <&pwm12_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@11 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
dr_mode = "peripheral";
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&vrefbuf {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vdda-supply = <&vdd>;
|
||||
status = "okay";
|
||||
};
|
||||
85
arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
Normal file
85
arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AA>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
st,package = <STM32MP_PKG_AA>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
57
arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
Normal file
57
arch/arm/dts/stm32mp15xxab-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AB>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <6>;
|
||||
gpio-ranges = <&pinctrl 6 86 6>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl 6 102 10>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <2>;
|
||||
gpio-ranges = <&pinctrl 0 112 2>;
|
||||
};
|
||||
};
|
||||
73
arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
Normal file
73
arch/arm/dts/stm32mp15xxac-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AC>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
st,package = <STM32MP_PKG_AC>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
57
arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
Normal file
57
arch/arm/dts/stm32mp15xxad-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AD>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <6>;
|
||||
gpio-ranges = <&pinctrl 6 86 6>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl 6 102 10>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <2>;
|
||||
gpio-ranges = <&pinctrl 0 112 2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -12,8 +12,6 @@
|
|||
#include <linux/iopoll.h>
|
||||
|
||||
#define BSEC_OTP_MAX_VALUE 95
|
||||
|
||||
#ifndef CONFIG_STM32MP1_TRUSTED
|
||||
#define BSEC_TIMEOUT_US 10000
|
||||
|
||||
/* BSEC REGISTER OFFSET (base relative) */
|
||||
|
|
@ -24,9 +22,10 @@
|
|||
#define BSEC_OTP_LOCK_OFF 0x010
|
||||
#define BSEC_DISTURBED_OFF 0x01C
|
||||
#define BSEC_ERROR_OFF 0x034
|
||||
#define BSEC_SPLOCK_OFF 0x064 /* Program safmem sticky lock */
|
||||
#define BSEC_SWLOCK_OFF 0x07C /* write in OTP sticky lock */
|
||||
#define BSEC_SRLOCK_OFF 0x094 /* shadowing sticky lock */
|
||||
#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
|
||||
#define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */
|
||||
#define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */
|
||||
#define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */
|
||||
#define BSEC_OTP_DATA_OFF 0x200
|
||||
|
||||
/* BSEC_CONFIGURATION Register MASK */
|
||||
|
|
@ -52,6 +51,24 @@
|
|||
*/
|
||||
#define BSEC_LOCK_PROGRAM 0x04
|
||||
|
||||
/**
|
||||
* bsec_lock() - manage lock for each type SR/SP/SW
|
||||
* @address: address of bsec IP register
|
||||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: true if locked else false
|
||||
*/
|
||||
static bool bsec_read_lock(u32 address, u32 otp)
|
||||
{
|
||||
u32 bit;
|
||||
u32 bank;
|
||||
|
||||
bit = 1 << (otp & OTP_LOCK_MASK);
|
||||
bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
|
||||
|
||||
return !!(readl(address + bank) & bit);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_STM32MP1_TRUSTED
|
||||
/**
|
||||
* bsec_check_error() - Check status of one otp
|
||||
* @base: base address of bsec IP
|
||||
|
|
@ -74,23 +91,6 @@ static u32 bsec_check_error(u32 base, u32 otp)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* bsec_lock() - manage lock for each type SR/SP/SW
|
||||
* @address: address of bsec IP register
|
||||
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
|
||||
* Return: true if locked else false
|
||||
*/
|
||||
static bool bsec_read_lock(u32 address, u32 otp)
|
||||
{
|
||||
u32 bit;
|
||||
u32 bank;
|
||||
|
||||
bit = 1 << (otp & OTP_LOCK_MASK);
|
||||
bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
|
||||
|
||||
return !!(readl(address + bank) & bit);
|
||||
}
|
||||
|
||||
/**
|
||||
* bsec_read_SR_lock() - read SR lock (Shadowing)
|
||||
* @base: base address of bsec IP
|
||||
|
|
@ -324,6 +324,16 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
|
|||
#endif
|
||||
}
|
||||
|
||||
static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
|
||||
{
|
||||
struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
|
||||
|
||||
/* return OTP permanent write lock status */
|
||||
*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
|
||||
{
|
||||
#ifdef CONFIG_STM32MP1_TRUSTED
|
||||
|
|
@ -350,22 +360,41 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
|
|||
#endif
|
||||
}
|
||||
|
||||
static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
|
||||
{
|
||||
#ifdef CONFIG_STM32MP1_TRUSTED
|
||||
if (val == 1)
|
||||
return stm32_smc_exec(STM32_SMC_BSEC,
|
||||
STM32_SMC_WRLOCK_OTP,
|
||||
otp, 0);
|
||||
if (val == 0)
|
||||
return 0; /* nothing to do */
|
||||
|
||||
return -EINVAL;
|
||||
#else
|
||||
return -ENOTSUPP;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int stm32mp_bsec_read(struct udevice *dev, int offset,
|
||||
void *buf, int size)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
bool shadow = true;
|
||||
bool shadow = true, lock = false;
|
||||
int nb_otp = size / sizeof(u32);
|
||||
int otp;
|
||||
unsigned int offs = offset;
|
||||
|
||||
if (offs >= STM32_BSEC_OTP_OFFSET) {
|
||||
if (offs >= STM32_BSEC_LOCK_OFFSET) {
|
||||
offs -= STM32_BSEC_LOCK_OFFSET;
|
||||
lock = true;
|
||||
} else if (offs >= STM32_BSEC_OTP_OFFSET) {
|
||||
offs -= STM32_BSEC_OTP_OFFSET;
|
||||
shadow = false;
|
||||
}
|
||||
|
||||
if (offs < 0 || (offs % 4) || (size % 4))
|
||||
if ((offs % 4) || (size % 4))
|
||||
return -EINVAL;
|
||||
|
||||
otp = offs / sizeof(u32);
|
||||
|
|
@ -373,7 +402,9 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset,
|
|||
for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
|
||||
u32 *addr = &((u32 *)buf)[i - otp];
|
||||
|
||||
if (shadow)
|
||||
if (lock)
|
||||
ret = stm32mp_bsec_read_lock(dev, addr, i);
|
||||
else if (shadow)
|
||||
ret = stm32mp_bsec_read_shadow(dev, addr, i);
|
||||
else
|
||||
ret = stm32mp_bsec_read_otp(dev, addr, i);
|
||||
|
|
@ -392,17 +423,20 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset,
|
|||
{
|
||||
int ret = 0;
|
||||
int i;
|
||||
bool shadow = true;
|
||||
bool shadow = true, lock = false;
|
||||
int nb_otp = size / sizeof(u32);
|
||||
int otp;
|
||||
unsigned int offs = offset;
|
||||
|
||||
if (offs >= STM32_BSEC_OTP_OFFSET) {
|
||||
if (offs >= STM32_BSEC_LOCK_OFFSET) {
|
||||
offs -= STM32_BSEC_LOCK_OFFSET;
|
||||
lock = true;
|
||||
} else if (offs >= STM32_BSEC_OTP_OFFSET) {
|
||||
offs -= STM32_BSEC_OTP_OFFSET;
|
||||
shadow = false;
|
||||
}
|
||||
|
||||
if (offs < 0 || (offs % 4) || (size % 4))
|
||||
if ((offs % 4) || (size % 4))
|
||||
return -EINVAL;
|
||||
|
||||
otp = offs / sizeof(u32);
|
||||
|
|
@ -410,7 +444,9 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset,
|
|||
for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
|
||||
u32 *val = &((u32 *)buf)[i - otp];
|
||||
|
||||
if (shadow)
|
||||
if (lock)
|
||||
ret = stm32mp_bsec_write_lock(dev, *val, i);
|
||||
else if (shadow)
|
||||
ret = stm32mp_bsec_write_shadow(dev, *val, i);
|
||||
else
|
||||
ret = stm32mp_bsec_write_otp(dev, *val, i);
|
||||
|
|
|
|||
|
|
@ -61,12 +61,6 @@
|
|||
#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
|
||||
#define BOOTROM_INSTANCE_SHIFT 16
|
||||
|
||||
/* BSEC OTP index */
|
||||
#define BSEC_OTP_RPN 1
|
||||
#define BSEC_OTP_SERIAL 13
|
||||
#define BSEC_OTP_PKG 16
|
||||
#define BSEC_OTP_MAC 57
|
||||
|
||||
/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
|
||||
#define RPN_SHIFT 0
|
||||
#define RPN_MASK GENMASK(7, 0)
|
||||
|
|
@ -285,25 +279,42 @@ u32 get_cpu_package(void)
|
|||
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
int print_cpuinfo(void)
|
||||
void get_soc_name(char name[SOC_NAME_SIZE])
|
||||
{
|
||||
char *cpu_s, *cpu_r, *pkg;
|
||||
|
||||
/* MPUs Part Numbers */
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_STM32MP157Fxx:
|
||||
cpu_s = "157F";
|
||||
break;
|
||||
case CPU_STM32MP157Dxx:
|
||||
cpu_s = "157D";
|
||||
break;
|
||||
case CPU_STM32MP157Cxx:
|
||||
cpu_s = "157C";
|
||||
break;
|
||||
case CPU_STM32MP157Axx:
|
||||
cpu_s = "157A";
|
||||
break;
|
||||
case CPU_STM32MP153Fxx:
|
||||
cpu_s = "153F";
|
||||
break;
|
||||
case CPU_STM32MP153Dxx:
|
||||
cpu_s = "153D";
|
||||
break;
|
||||
case CPU_STM32MP153Cxx:
|
||||
cpu_s = "153C";
|
||||
break;
|
||||
case CPU_STM32MP153Axx:
|
||||
cpu_s = "153A";
|
||||
break;
|
||||
case CPU_STM32MP151Fxx:
|
||||
cpu_s = "151F";
|
||||
break;
|
||||
case CPU_STM32MP151Dxx:
|
||||
cpu_s = "151D";
|
||||
break;
|
||||
case CPU_STM32MP151Cxx:
|
||||
cpu_s = "151C";
|
||||
break;
|
||||
|
|
@ -350,7 +361,16 @@ int print_cpuinfo(void)
|
|||
break;
|
||||
}
|
||||
|
||||
printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
|
||||
snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
char name[SOC_NAME_SIZE];
|
||||
|
||||
get_soc_name(name);
|
||||
printf("CPU: %s\n", name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,6 +23,12 @@
|
|||
|
||||
#define ETZPC_RESERVED 0xffffffff
|
||||
|
||||
#define STM32_FDCAN_BASE 0x4400e000
|
||||
#define STM32_CRYP2_BASE 0x4c005000
|
||||
#define STM32_CRYP1_BASE 0x54001000
|
||||
#define STM32_GPU_BASE 0x59000000
|
||||
#define STM32_DSI_BASE 0x5a000000
|
||||
|
||||
static const u32 stm32mp1_ip_addr[] = {
|
||||
0x5c008000, /* 00 stgenc */
|
||||
0x54000000, /* 01 bkpsram */
|
||||
|
|
@ -33,7 +39,7 @@ static const u32 stm32mp1_ip_addr[] = {
|
|||
ETZPC_RESERVED, /* 06 reserved */
|
||||
0x54003000, /* 07 rng1 */
|
||||
0x54002000, /* 08 hash1 */
|
||||
0x54001000, /* 09 cryp1 */
|
||||
STM32_CRYP1_BASE, /* 09 cryp1 */
|
||||
0x5a003000, /* 0A ddrctrl */
|
||||
0x5a004000, /* 0B ddrphyc */
|
||||
0x5c009000, /* 0C i2c6 */
|
||||
|
|
@ -86,7 +92,7 @@ static const u32 stm32mp1_ip_addr[] = {
|
|||
0x4400b000, /* 3B sai2 */
|
||||
0x4400c000, /* 3C sai3 */
|
||||
0x4400d000, /* 3D dfsdm */
|
||||
0x4400e000, /* 3E tt_fdcan */
|
||||
STM32_FDCAN_BASE, /* 3E tt_fdcan */
|
||||
ETZPC_RESERVED, /* 3F reserved */
|
||||
0x50021000, /* 40 lptim2 */
|
||||
0x50022000, /* 41 lptim3 */
|
||||
|
|
@ -99,7 +105,7 @@ static const u32 stm32mp1_ip_addr[] = {
|
|||
0x48003000, /* 48 adc */
|
||||
0x4c002000, /* 49 hash2 */
|
||||
0x4c003000, /* 4A rng2 */
|
||||
0x4c005000, /* 4B cryp2 */
|
||||
STM32_CRYP2_BASE, /* 4B cryp2 */
|
||||
ETZPC_RESERVED, /* 4C reserved */
|
||||
ETZPC_RESERVED, /* 4D reserved */
|
||||
ETZPC_RESERVED, /* 4E reserved */
|
||||
|
|
@ -126,11 +132,13 @@ static const u32 stm32mp1_ip_addr[] = {
|
|||
static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
|
||||
{
|
||||
int node;
|
||||
fdt_addr_t regs;
|
||||
|
||||
for (node = fdt_first_subnode(fdt, offset);
|
||||
node >= 0;
|
||||
node = fdt_next_subnode(fdt, node)) {
|
||||
if (addr == (u32)fdt_getprop(fdt, node, "reg", 0)) {
|
||||
regs = fdtdec_get_addr(fdt, node, "reg");
|
||||
if (addr == regs) {
|
||||
if (fdtdec_get_is_enabled(fdt, node)) {
|
||||
fdt_status_disabled(fdt, node);
|
||||
|
||||
|
|
@ -143,11 +151,11 @@ static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
|
|||
return false;
|
||||
}
|
||||
|
||||
static int stm32_fdt_fixup_etzpc(void *fdt)
|
||||
static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
|
||||
{
|
||||
const u32 *array;
|
||||
int array_size, i;
|
||||
int soc_node, offset, shift;
|
||||
int offset, shift;
|
||||
u32 addr, status, decprot[ETZPC_DECPROT_NB];
|
||||
|
||||
array = stm32mp1_ip_addr;
|
||||
|
|
@ -156,10 +164,6 @@ static int stm32_fdt_fixup_etzpc(void *fdt)
|
|||
for (i = 0; i < ETZPC_DECPROT_NB; i++)
|
||||
decprot[i] = readl(ETZPC_DECPROT(i));
|
||||
|
||||
soc_node = fdt_path_offset(fdt, "/soc");
|
||||
if (soc_node < 0)
|
||||
return soc_node;
|
||||
|
||||
for (i = 0; i < array_size; i++) {
|
||||
offset = i / NB_PROT_PER_REG;
|
||||
shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
|
||||
|
|
@ -180,6 +184,40 @@ static int stm32_fdt_fixup_etzpc(void *fdt)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* deactivate all the cpu except core 0 */
|
||||
static void stm32_fdt_fixup_cpu(void *blob, char *name)
|
||||
{
|
||||
int off;
|
||||
u32 reg;
|
||||
|
||||
off = fdt_path_offset(blob, "/cpus");
|
||||
if (off < 0) {
|
||||
printf("%s: couldn't find /cpus node\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
|
||||
while (off != -FDT_ERR_NOTFOUND) {
|
||||
reg = fdtdec_get_addr(blob, off, "reg");
|
||||
if (reg != 0) {
|
||||
fdt_del_node(blob, off);
|
||||
printf("FDT: cpu %d node remove for %s\n", reg, name);
|
||||
/* after delete we can't trust the offsets anymore */
|
||||
off = -1;
|
||||
}
|
||||
off = fdt_node_offset_by_prop_value(blob, off,
|
||||
"device_type", "cpu", 4);
|
||||
}
|
||||
}
|
||||
|
||||
static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
|
||||
const char *string, const char *name)
|
||||
{
|
||||
if (fdt_disable_subnode_by_address(fdt, offset, addr))
|
||||
printf("FDT: %s@%08x node disabled for %s\n",
|
||||
string, addr, name);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is called right before the kernel is booted. "blob" is the
|
||||
* device tree that will be passed to the kernel.
|
||||
|
|
@ -187,14 +225,59 @@ static int stm32_fdt_fixup_etzpc(void *fdt)
|
|||
int ft_system_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 pkg;
|
||||
int soc;
|
||||
u32 pkg, cpu;
|
||||
char name[SOC_NAME_SIZE];
|
||||
|
||||
soc = fdt_path_offset(blob, "/soc");
|
||||
if (soc < 0)
|
||||
return soc;
|
||||
|
||||
if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
|
||||
ret = stm32_fdt_fixup_etzpc(blob);
|
||||
ret = stm32_fdt_fixup_etzpc(blob, soc);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* MPUs Part Numbers and name*/
|
||||
cpu = get_cpu_type();
|
||||
get_soc_name(name);
|
||||
|
||||
switch (cpu) {
|
||||
case CPU_STM32MP151Fxx:
|
||||
case CPU_STM32MP151Dxx:
|
||||
case CPU_STM32MP151Cxx:
|
||||
case CPU_STM32MP151Axx:
|
||||
stm32_fdt_fixup_cpu(blob, name);
|
||||
/* after cpu delete we can't trust the soc offsets anymore */
|
||||
soc = fdt_path_offset(blob, "/soc");
|
||||
stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
|
||||
/* fall through */
|
||||
case CPU_STM32MP153Fxx:
|
||||
case CPU_STM32MP153Dxx:
|
||||
case CPU_STM32MP153Cxx:
|
||||
case CPU_STM32MP153Axx:
|
||||
stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
|
||||
stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (cpu) {
|
||||
case CPU_STM32MP157Dxx:
|
||||
case CPU_STM32MP157Axx:
|
||||
case CPU_STM32MP153Dxx:
|
||||
case CPU_STM32MP153Axx:
|
||||
case CPU_STM32MP151Dxx:
|
||||
case CPU_STM32MP151Axx:
|
||||
stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
|
||||
stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (get_cpu_package()) {
|
||||
case PKG_AA_LBGA448:
|
||||
pkg = STM32MP_PKG_AA;
|
||||
|
|
|
|||
|
|
@ -9,8 +9,10 @@
|
|||
/* DDR power initializations */
|
||||
enum ddr_type {
|
||||
STM32MP_DDR3,
|
||||
STM32MP_LPDDR2,
|
||||
STM32MP_LPDDR3,
|
||||
STM32MP_LPDDR2_16,
|
||||
STM32MP_LPDDR2_32,
|
||||
STM32MP_LPDDR3_16,
|
||||
STM32MP_LPDDR3_32,
|
||||
};
|
||||
|
||||
int board_ddr_power_init(enum ddr_type ddr_type);
|
||||
|
|
|
|||
|
|
@ -119,7 +119,14 @@ enum forced_boot_mode {
|
|||
#define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
|
||||
#define STM32_BSEC_OTP_OFFSET 0x80000000
|
||||
#define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4)
|
||||
#define STM32_BSEC_LOCK_OFFSET 0xC0000000
|
||||
#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
|
||||
|
||||
/* BSEC OTP index */
|
||||
#define BSEC_OTP_RPN 1
|
||||
#define BSEC_OTP_SERIAL 13
|
||||
#define BSEC_OTP_PKG 16
|
||||
#define BSEC_OTP_MAC 57
|
||||
#define BSEC_OTP_BOARD 59
|
||||
|
||||
#endif /* __ASSEMBLY__*/
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#define STM32_SMC_READ_OTP 0x04
|
||||
#define STM32_SMC_READ_ALL 0x05
|
||||
#define STM32_SMC_WRITE_ALL 0x06
|
||||
#define STM32_SMC_WRLOCK_OTP 0x07
|
||||
|
||||
/* SMC error codes */
|
||||
#define STM32_SMC_OK 0x0
|
||||
|
|
@ -45,8 +46,8 @@ static inline u32 stm32_smc(u32 svc, u8 op, u32 data1, u32 data2, u32 *result)
|
|||
arm_smccc_smc(svc, op, data1, data2, 0, 0, 0, 0, &res);
|
||||
|
||||
if (res.a0) {
|
||||
pr_err("%s: Failed to exec in secure mode (err = %ld)\n",
|
||||
__func__, res.a0);
|
||||
pr_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n",
|
||||
__func__, svc, op, res.a0);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (result)
|
||||
|
|
|
|||
|
|
@ -3,13 +3,19 @@
|
|||
* Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/
|
||||
/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */
|
||||
#define CPU_STM32MP157Cxx 0x05000000
|
||||
#define CPU_STM32MP157Axx 0x05000001
|
||||
#define CPU_STM32MP153Cxx 0x05000024
|
||||
#define CPU_STM32MP153Axx 0x05000025
|
||||
#define CPU_STM32MP151Cxx 0x0500002E
|
||||
#define CPU_STM32MP151Axx 0x0500002F
|
||||
#define CPU_STM32MP157Fxx 0x05000080
|
||||
#define CPU_STM32MP157Dxx 0x05000081
|
||||
#define CPU_STM32MP153Fxx 0x050000A4
|
||||
#define CPU_STM32MP153Dxx 0x050000A5
|
||||
#define CPU_STM32MP151Fxx 0x050000AE
|
||||
#define CPU_STM32MP151Dxx 0x050000AF
|
||||
|
||||
/* return CPU_STMP32MP...Xxx constants */
|
||||
u32 get_cpu_type(void);
|
||||
|
|
@ -29,6 +35,10 @@ u32 get_cpu_package(void);
|
|||
#define PKG_AC_TFBGA361 2
|
||||
#define PKG_AD_TFBGA257 1
|
||||
|
||||
/* Get SOC name */
|
||||
#define SOC_NAME_SIZE 20
|
||||
void get_soc_name(char name[SOC_NAME_SIZE]);
|
||||
|
||||
/* return boot mode */
|
||||
u32 get_bootmode(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -30,6 +30,22 @@ u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
|
|||
PSCI_AFFINITY_LEVEL_ON,
|
||||
PSCI_AFFINITY_LEVEL_OFF};
|
||||
|
||||
static u32 __secure_data cntfrq;
|
||||
|
||||
static u32 __secure cp15_read_cntfrq(void)
|
||||
{
|
||||
u32 frq;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
|
||||
|
||||
return frq;
|
||||
}
|
||||
|
||||
static void __secure cp15_write_cntfrq(u32 frq)
|
||||
{
|
||||
asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
|
||||
}
|
||||
|
||||
static inline void psci_set_state(int cpu, u8 state)
|
||||
{
|
||||
psci_state[cpu] = state;
|
||||
|
|
@ -63,6 +79,9 @@ void __secure psci_arch_cpu_entry(void)
|
|||
|
||||
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
|
||||
|
||||
/* write the saved cntfrq */
|
||||
cp15_write_cntfrq(cntfrq);
|
||||
|
||||
/* reset magic in TAMP register */
|
||||
writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
|
||||
}
|
||||
|
|
@ -130,6 +149,9 @@ s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
|
|||
if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
|
||||
return ARM_PSCI_RET_ALREADY_ON;
|
||||
|
||||
/* read and save cntfrq of current cpu to write on target cpu */
|
||||
cntfrq = cp15_read_cntfrq();
|
||||
|
||||
/* reset magic in TAMP register */
|
||||
if (readl(TAMP_BACKUP_MAGIC_NUMBER))
|
||||
writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,32 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* the st command stboard supports the STMicroelectronics board identification
|
||||
* saved in OTP 59.
|
||||
*
|
||||
* The ST product codification have several element
|
||||
* - "Commercial Product Name" (CPN): type of product board (DKX, EVX)
|
||||
* associated to the board ID "MBxxxx"
|
||||
* - "Finished Good" or "Finish Good" (FG):
|
||||
* effective content of the product without chip STM32MP1xx (LCD, Wifi,…)
|
||||
* - BOM: cost variant for same FG (for example, several provider of the same
|
||||
* component)
|
||||
*
|
||||
* For example
|
||||
* - commercial product = STM32MP157C-EV1 for board MB1263
|
||||
* - Finished Good = EVA32MP157A1$AU1
|
||||
*
|
||||
* Both information are written on board and these information are also saved
|
||||
* in OTP59, with:
|
||||
* bit [31:16] (hex) => Board id, MBxxxx
|
||||
* bit [15:12] (dec) => Variant CPN (1....15)
|
||||
* bit [11:8] (dec) => Revision board (index with A = 1, Z = 26)
|
||||
* bit [7:4] (dec) => Variant FG : finished good index
|
||||
* bit [3:0] (dec) => BOM (01, .... 255)
|
||||
*
|
||||
* and displayed with the format:
|
||||
* Board: MB<Board> Var<VarCPN>.<VarFG> Rev.<Revision>-<BOM>
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
|
@ -13,6 +39,7 @@
|
|||
static bool check_stboard(u16 board)
|
||||
{
|
||||
unsigned int i;
|
||||
/* list of supported ST boards */
|
||||
const u16 st_board_id[] = {
|
||||
0x1272,
|
||||
0x1263,
|
||||
|
|
@ -31,9 +58,11 @@ static bool check_stboard(u16 board)
|
|||
|
||||
static void display_stboard(u32 otp)
|
||||
{
|
||||
printf("Board: MB%04x Var%d Rev.%c-%02d\n",
|
||||
/* display board indentification with OPT coding */
|
||||
printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
|
||||
otp >> 16,
|
||||
(otp >> 12) & 0xF,
|
||||
(otp >> 4) & 0xF,
|
||||
((otp >> 8) & 0xF) - 1 + 'A',
|
||||
otp & 0xF);
|
||||
}
|
||||
|
|
@ -42,23 +71,23 @@ static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||
char * const argv[])
|
||||
{
|
||||
int ret;
|
||||
u32 otp;
|
||||
u32 otp, lock;
|
||||
u8 revision;
|
||||
unsigned long board, variant, bom;
|
||||
unsigned long board, var_cpn, var_fg, bom;
|
||||
struct udevice *dev;
|
||||
int confirmed = argc == 6 && !strcmp(argv[1], "-y");
|
||||
int confirmed = argc == 7 && !strcmp(argv[1], "-y");
|
||||
|
||||
argc -= 1 + confirmed;
|
||||
argv += 1 + confirmed;
|
||||
|
||||
if (argc != 0 && argc != 4)
|
||||
if (argc != 0 && argc != 5)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stm32mp_bsec),
|
||||
&dev);
|
||||
|
||||
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
|
||||
ret = misc_read(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD),
|
||||
&otp, sizeof(otp));
|
||||
|
||||
if (ret < 0) {
|
||||
|
|
@ -66,11 +95,20 @@ static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD),
|
||||
&lock, sizeof(lock));
|
||||
if (ret < 0) {
|
||||
puts("LOCK read error");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
if (argc == 0) {
|
||||
if (!otp)
|
||||
puts("Board : OTP board FREE\n");
|
||||
else
|
||||
display_stboard(otp);
|
||||
printf(" OTP %d %s locked !\n", BSEC_OTP_BOARD,
|
||||
lock == 1 ? "" : "NOT");
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -86,8 +124,8 @@ static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
if (strict_strtoul(argv[1], 10, &variant) < 0 ||
|
||||
variant == 0 || variant > 15) {
|
||||
if (strict_strtoul(argv[1], 10, &var_cpn) < 0 ||
|
||||
var_cpn == 0 || var_cpn > 15) {
|
||||
printf("argument %d invalid: %s\n", 2, argv[1]);
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
|
@ -98,13 +136,21 @@ static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
if (strict_strtoul(argv[3], 10, &bom) < 0 ||
|
||||
if (strict_strtoul(argv[3], 10, &var_fg) < 0 ||
|
||||
var_fg > 15) {
|
||||
printf("argument %d invalid: %s\n", 4, argv[3]);
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
if (strict_strtoul(argv[4], 10, &bom) < 0 ||
|
||||
bom == 0 || bom > 15) {
|
||||
printf("argument %d invalid: %s\n", 4, argv[3]);
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
otp = (board << 16) | (variant << 12) | (revision << 8) | bom;
|
||||
/* st board indentification value */
|
||||
otp = (board << 16) | (var_cpn << 12) | (revision << 8) |
|
||||
(var_fg << 4) | bom;
|
||||
display_stboard(otp);
|
||||
printf("=> OTP[%d] = %08X\n", BSEC_OTP_BOARD, otp);
|
||||
|
||||
|
|
@ -125,24 +171,35 @@ static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||
ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD),
|
||||
&otp, sizeof(otp));
|
||||
|
||||
if (ret) {
|
||||
if (ret < 0) {
|
||||
puts("BOARD programming error\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
/* write persistent lock */
|
||||
otp = 1;
|
||||
ret = misc_write(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD),
|
||||
&otp, sizeof(otp));
|
||||
if (ret < 0) {
|
||||
puts("BOARD lock error\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
puts("BOARD programming done\n");
|
||||
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(stboard, 6, 0, do_stboard,
|
||||
U_BOOT_CMD(stboard, 7, 0, do_stboard,
|
||||
"read/write board reference in OTP",
|
||||
"\n"
|
||||
" Print current board information\n"
|
||||
"stboard [-y] <Board> <Variant> <Revision> <BOM>\n"
|
||||
"stboard [-y] <Board> <VarCPN> <Revision> <VarFG> <BOM>\n"
|
||||
" Write board information\n"
|
||||
" - Board: xxxx, example 1264 for MB1264\n"
|
||||
" - Variant: 1 ... 15\n"
|
||||
" - VarCPN: 1...15\n"
|
||||
" - Revision: A...O\n"
|
||||
" - VarFG: 0...15\n"
|
||||
" - BOM: 1...15\n");
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ int board_ddr_power_init(enum ddr_type ddr_type)
|
|||
struct udevice *dev;
|
||||
bool buck3_at_1800000v = false;
|
||||
int ret;
|
||||
u32 buck2;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_PMIC,
|
||||
DM_GET_DRIVER(pmic_stpmic1), &dev);
|
||||
|
|
@ -102,8 +103,10 @@ int board_ddr_power_init(enum ddr_type ddr_type)
|
|||
|
||||
break;
|
||||
|
||||
case STM32MP_LPDDR2:
|
||||
case STM32MP_LPDDR3:
|
||||
case STM32MP_LPDDR2_16:
|
||||
case STM32MP_LPDDR2_32:
|
||||
case STM32MP_LPDDR3_16:
|
||||
case STM32MP_LPDDR3_32:
|
||||
/*
|
||||
* configure VDD_DDR1 = LDO3
|
||||
* Set LDO3 to 1.8V
|
||||
|
|
@ -133,11 +136,23 @@ int board_ddr_power_init(enum ddr_type ddr_type)
|
|||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* VDD_DDR2 : Set BUCK2 to 1.2V */
|
||||
/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
|
||||
switch (ddr_type) {
|
||||
case STM32MP_LPDDR2_32:
|
||||
case STM32MP_LPDDR3_32:
|
||||
buck2 = STPMIC1_BUCK2_1250000V;
|
||||
break;
|
||||
default:
|
||||
case STM32MP_LPDDR2_16:
|
||||
case STM32MP_LPDDR3_16:
|
||||
buck2 = STPMIC1_BUCK2_1200000V;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = pmic_clrsetbits(dev,
|
||||
STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
|
||||
STPMIC1_BUCK_VOUT_MASK,
|
||||
STPMIC1_BUCK2_1200000V);
|
||||
buck2);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -104,19 +104,21 @@ int checkboard(void)
|
|||
printf(" (%s)", fdt_compat);
|
||||
puts("\n");
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stm32mp_bsec),
|
||||
&dev);
|
||||
|
||||
if (!ret)
|
||||
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
|
||||
&otp, sizeof(otp));
|
||||
if (ret > 0 && otp) {
|
||||
printf("Board: MB%04x Var%d Rev.%c-%02d\n",
|
||||
otp >> 16,
|
||||
(otp >> 12) & 0xF,
|
||||
((otp >> 8) & 0xF) - 1 + 'A',
|
||||
otp & 0xF);
|
||||
/* display the STMicroelectronics board identification */
|
||||
if (CONFIG_IS_ENABLED(CMD_STBOARD)) {
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stm32mp_bsec),
|
||||
&dev);
|
||||
if (!ret)
|
||||
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
|
||||
&otp, sizeof(otp));
|
||||
if (ret > 0 && otp)
|
||||
printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
|
||||
otp >> 16,
|
||||
(otp >> 12) & 0xF,
|
||||
(otp >> 4) & 0xF,
|
||||
((otp >> 8) & 0xF) - 1 + 'A',
|
||||
otp & 0xF);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -25,6 +25,14 @@ It features:
|
|||
- Standard connectivity, widely inherited from the STM32 MCU family
|
||||
- Comprehensive security support
|
||||
|
||||
Each line comes with a security option (cryptography & secure boot) and
|
||||
a Cortex-A frequency option:
|
||||
|
||||
- A : Cortex-A7 @ 650 MHz
|
||||
- C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
|
||||
- D : Cortex-A7 @ 800 MHz
|
||||
- F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
|
||||
|
||||
Everything is supported in Linux but U-Boot is limited to:
|
||||
|
||||
1. UART
|
||||
|
|
@ -416,20 +424,26 @@ For STMicroelectonics board, it is retrieved in STM32MP15x OTP :
|
|||
- OTP_58[15:0] = MAC_ADDR[47:32]
|
||||
|
||||
To program a MAC address on virgin OTP words above, you can use the fuse command
|
||||
on bank 0 to access to internal OTP:
|
||||
on bank 0 to access to internal OTP and lock them:
|
||||
|
||||
Prerequisite: check if a MAC address isn't yet programmed in OTP
|
||||
|
||||
1) check OTP: their value must be equal to 0
|
||||
1) check OTP: their value must be equal to 0::
|
||||
|
||||
STM32MP> fuse sense 0 57 2
|
||||
Sensing bank 0:
|
||||
Word 0x00000039: 00000000 00000000
|
||||
STM32MP> fuse sense 0 57 2
|
||||
Sensing bank 0:
|
||||
Word 0x00000039: 00000000 00000000
|
||||
|
||||
2) check environment variable
|
||||
2) check environment variable::
|
||||
|
||||
STM32MP> env print ethaddr
|
||||
## Error: "ethaddr" not defined
|
||||
STM32MP> env print ethaddr
|
||||
## Error: "ethaddr" not defined
|
||||
|
||||
3) check lock status of fuse 57 & 58 (at 0x39, 0=unlocked, 1=locked)::
|
||||
|
||||
STM32MP> fuse sense 0 0x10000039 2
|
||||
Sensing bank 0:
|
||||
Word 0x10000039: 00000000 00000000
|
||||
|
||||
Example to set mac address "12:34:56:78:9a:bc"
|
||||
|
||||
|
|
@ -443,11 +457,19 @@ Example to set mac address "12:34:56:78:9a:bc"
|
|||
Sensing bank 0:
|
||||
Word 0x00000039: 78563412 0000bc9a
|
||||
|
||||
3) next REBOOT, in the trace::
|
||||
3) Lock OTP::
|
||||
|
||||
STM32MP> fuse prog 0 0x10000039 1 1
|
||||
|
||||
STM32MP> fuse sense 0 0x10000039 2
|
||||
Sensing bank 0:
|
||||
Word 0x10000039: 00000001 00000001
|
||||
|
||||
4) next REBOOT, in the trace::
|
||||
|
||||
### Setting environment from OTP MAC address = "12:34:56:78:9a:bc"
|
||||
|
||||
4) check env update::
|
||||
5) check env update::
|
||||
|
||||
STM32MP> env print ethaddr
|
||||
ethaddr=12:34:56:78:9a:bc
|
||||
|
|
|
|||
|
|
@ -129,6 +129,8 @@ phyc attributes:
|
|||
MR3
|
||||
|
||||
- st,phy-cal : phy cal depending of calibration or tuning of DDR
|
||||
This parameter is optional; when it is absent the built-in PHY
|
||||
calibration is done.
|
||||
for STM32MP15x: 12 values are requested in this order
|
||||
DX0DLLCR
|
||||
DX0DQTR
|
||||
|
|
|
|||
|
|
@ -95,6 +95,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define RCC_I2C12CKSELR 0x8C0
|
||||
#define RCC_I2C35CKSELR 0x8C4
|
||||
#define RCC_SPI2S1CKSELR 0x8D8
|
||||
#define RCC_SPI45CKSELR 0x8E0
|
||||
#define RCC_UART6CKSELR 0x8E4
|
||||
#define RCC_UART24CKSELR 0x8E8
|
||||
#define RCC_UART35CKSELR 0x8EC
|
||||
|
|
@ -304,6 +305,7 @@ enum stm32mp1_parent_sel {
|
|||
_DSI_SEL,
|
||||
_ADC12_SEL,
|
||||
_SPI1_SEL,
|
||||
_SPI45_SEL,
|
||||
_RTC_SEL,
|
||||
_PARENT_SEL_NB,
|
||||
_UNKNOWN_SEL = 0xff,
|
||||
|
|
@ -527,6 +529,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
|
|||
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
|
||||
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
|
||||
|
||||
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
|
||||
|
|
@ -603,6 +606,8 @@ static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
|
|||
static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
|
||||
static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
|
||||
_PLL3_R};
|
||||
static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
|
||||
_HSE_KER};
|
||||
static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
|
||||
|
||||
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
|
||||
|
|
@ -621,14 +626,15 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
|
|||
STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
|
||||
sdmmc3_parents),
|
||||
STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
|
||||
STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
|
||||
STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
|
||||
STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
|
||||
STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
|
||||
STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
|
||||
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
|
||||
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
|
||||
STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
|
||||
STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
|
||||
STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
|
||||
STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
|
||||
STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
|
||||
STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
|
||||
(RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
|
||||
rtc_parents),
|
||||
|
|
@ -747,6 +753,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
|
|||
[_DSI_SEL] = "DSI",
|
||||
[_ADC12_SEL] = "ADC12",
|
||||
[_SPI1_SEL] = "SPI1",
|
||||
[_SPI45_SEL] = "SPI45",
|
||||
[_RTC_SEL] = "RTC",
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -7,10 +7,10 @@
|
|||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <malloc.h>
|
||||
#include <reset.h>
|
||||
|
||||
#include <dm/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
/* STM32 I2C registers */
|
||||
|
|
@ -145,7 +145,6 @@ struct stm32_i2c_spec {
|
|||
|
||||
/**
|
||||
* struct stm32_i2c_setup - private I2C timing setup parameters
|
||||
* @speed: I2C speed mode (standard, Fast Plus)
|
||||
* @speed_freq: I2C speed frequency (Hz)
|
||||
* @clock_src: I2C clock source frequency (Hz)
|
||||
* @rise_time: Rise time (ns)
|
||||
|
|
@ -154,7 +153,6 @@ struct stm32_i2c_spec {
|
|||
* @analog_filter: Analog filter delay (On/Off)
|
||||
*/
|
||||
struct stm32_i2c_setup {
|
||||
enum i2c_speed_mode speed;
|
||||
u32 speed_freq;
|
||||
u32 clock_src;
|
||||
u32 rise_time;
|
||||
|
|
@ -184,10 +182,11 @@ struct stm32_i2c_priv {
|
|||
struct stm32_i2c_regs *regs;
|
||||
struct clk clk;
|
||||
struct stm32_i2c_setup *setup;
|
||||
int speed;
|
||||
u32 speed;
|
||||
};
|
||||
|
||||
static const struct stm32_i2c_spec i2c_specs[] = {
|
||||
/* Standard speed - 100 KHz */
|
||||
[IC_SPEED_MODE_STANDARD] = {
|
||||
.rate = I2C_SPEED_STANDARD_RATE,
|
||||
.rate_min = 8000,
|
||||
|
|
@ -200,6 +199,7 @@ static const struct stm32_i2c_spec i2c_specs[] = {
|
|||
.l_min = 4700,
|
||||
.h_min = 4000,
|
||||
},
|
||||
/* Fast speed - 400 KHz */
|
||||
[IC_SPEED_MODE_FAST] = {
|
||||
.rate = I2C_SPEED_FAST_RATE,
|
||||
.rate_min = 320000,
|
||||
|
|
@ -212,6 +212,7 @@ static const struct stm32_i2c_spec i2c_specs[] = {
|
|||
.l_min = 1300,
|
||||
.h_min = 600,
|
||||
},
|
||||
/* Fast Plus Speed - 1 MHz */
|
||||
[IC_SPEED_MODE_FAST_PLUS] = {
|
||||
.rate = I2C_SPEED_FAST_PLUS_RATE,
|
||||
.rate_min = 800000,
|
||||
|
|
@ -474,6 +475,7 @@ static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
|
|||
}
|
||||
|
||||
static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
|
||||
const struct stm32_i2c_spec *specs,
|
||||
struct list_head *solutions)
|
||||
{
|
||||
struct stm32_i2c_timings *v;
|
||||
|
|
@ -490,13 +492,13 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
|
|||
af_delay_max = setup->analog_filter ?
|
||||
STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
|
||||
|
||||
sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
|
||||
sdadel_min = specs->hddat_min + setup->fall_time -
|
||||
af_delay_min - (setup->dnf + 3) * i2cclk;
|
||||
|
||||
sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
|
||||
sdadel_max = specs->vddat_max - setup->rise_time -
|
||||
af_delay_max - (setup->dnf + 4) * i2cclk;
|
||||
|
||||
scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
|
||||
scldel_min = setup->rise_time + specs->sudat_min;
|
||||
|
||||
if (sdadel_min < 0)
|
||||
sdadel_min = 0;
|
||||
|
|
@ -548,6 +550,7 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
|
|||
}
|
||||
|
||||
static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
|
||||
const struct stm32_i2c_spec *specs,
|
||||
struct list_head *solutions,
|
||||
struct stm32_i2c_timings *s)
|
||||
{
|
||||
|
|
@ -570,8 +573,8 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
|
|||
dnf_delay = setup->dnf * i2cclk;
|
||||
|
||||
tsync = af_delay_min + dnf_delay + (2 * i2cclk);
|
||||
clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
|
||||
clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
|
||||
clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
|
||||
clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
|
||||
|
||||
/*
|
||||
* Among Prescaler possibilities discovered above figures out SCL Low
|
||||
|
|
@ -589,7 +592,7 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
|
|||
for (l = 0; l < STM32_SCLL_MAX; l++) {
|
||||
u32 tscl_l = (l + 1) * prescaler + tsync;
|
||||
|
||||
if ((tscl_l < i2c_specs[setup->speed].l_min) ||
|
||||
if (tscl_l < specs->l_min ||
|
||||
(i2cclk >=
|
||||
((tscl_l - af_delay_min - dnf_delay) / 4))) {
|
||||
continue;
|
||||
|
|
@ -601,7 +604,7 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
|
|||
setup->rise_time + setup->fall_time;
|
||||
|
||||
if ((tscl >= clk_min) && (tscl <= clk_max) &&
|
||||
(tscl_h >= i2c_specs[setup->speed].h_min) &&
|
||||
(tscl_h >= specs->h_min) &&
|
||||
(i2cclk < tscl_h)) {
|
||||
u32 clk_error;
|
||||
|
||||
|
|
@ -630,26 +633,40 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static const struct stm32_i2c_spec *get_specs(u32 rate)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
|
||||
if (rate <= i2c_specs[i].rate)
|
||||
return &i2c_specs[i];
|
||||
|
||||
/* NOT REACHED */
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
|
||||
struct stm32_i2c_setup *setup,
|
||||
struct stm32_i2c_timings *output)
|
||||
{
|
||||
const struct stm32_i2c_spec *specs;
|
||||
struct stm32_i2c_timings *v, *_v;
|
||||
struct list_head solutions;
|
||||
int ret;
|
||||
|
||||
if (setup->speed >= ARRAY_SIZE(i2c_specs)) {
|
||||
pr_err("%s: speed out of bound {%d/%d}\n", __func__,
|
||||
setup->speed, ARRAY_SIZE(i2c_specs) - 1);
|
||||
specs = get_specs(setup->speed_freq);
|
||||
if (specs == ERR_PTR(-EINVAL)) {
|
||||
pr_err("%s: speed out of bound {%d}\n", __func__,
|
||||
setup->speed_freq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
|
||||
(setup->fall_time > i2c_specs[setup->speed].fall_max)) {
|
||||
if (setup->rise_time > specs->rise_max ||
|
||||
setup->fall_time > specs->fall_max) {
|
||||
pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
|
||||
__func__,
|
||||
setup->rise_time, i2c_specs[setup->speed].rise_max,
|
||||
setup->fall_time, i2c_specs[setup->speed].fall_max);
|
||||
setup->rise_time, specs->rise_max,
|
||||
setup->fall_time, specs->fall_max);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -659,18 +676,12 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (setup->speed_freq > i2c_specs[setup->speed].rate) {
|
||||
pr_err("%s: Freq {%d/%d}\n", __func__,
|
||||
setup->speed_freq, i2c_specs[setup->speed].rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&solutions);
|
||||
ret = stm32_i2c_compute_solutions(setup, &solutions);
|
||||
ret = stm32_i2c_compute_solutions(setup, specs, &solutions);
|
||||
if (ret)
|
||||
goto exit;
|
||||
|
||||
ret = stm32_i2c_choose_solution(setup, &solutions, output);
|
||||
ret = stm32_i2c_choose_solution(setup, specs, &solutions, output);
|
||||
if (ret)
|
||||
goto exit;
|
||||
|
||||
|
|
@ -689,14 +700,24 @@ exit:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static u32 get_lower_rate(u32 rate)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--)
|
||||
if (rate > i2c_specs[i].rate)
|
||||
return i2c_specs[i].rate;
|
||||
|
||||
return i2c_specs[0].rate;
|
||||
}
|
||||
|
||||
static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
|
||||
struct stm32_i2c_timings *timing)
|
||||
{
|
||||
struct stm32_i2c_setup *setup = i2c_priv->setup;
|
||||
int ret = 0;
|
||||
|
||||
setup->speed = i2c_priv->speed;
|
||||
setup->speed_freq = i2c_specs[setup->speed].rate;
|
||||
setup->speed_freq = i2c_priv->speed;
|
||||
setup->clock_src = clk_get_rate(&i2c_priv->clk);
|
||||
|
||||
if (!setup->clock_src) {
|
||||
|
|
@ -709,13 +730,11 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
|
|||
if (ret) {
|
||||
debug("%s: failed to compute I2C timings.\n",
|
||||
__func__);
|
||||
if (i2c_priv->speed > IC_SPEED_MODE_STANDARD) {
|
||||
i2c_priv->speed--;
|
||||
setup->speed = i2c_priv->speed;
|
||||
if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
|
||||
setup->speed_freq =
|
||||
i2c_specs[setup->speed].rate;
|
||||
get_lower_rate(setup->speed_freq);
|
||||
debug("%s: downgrade I2C Speed Freq to (%i)\n",
|
||||
__func__, i2c_specs[setup->speed].rate);
|
||||
__func__, setup->speed_freq);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
|
|
@ -727,13 +746,15 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
|
|||
return ret;
|
||||
}
|
||||
|
||||
debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__,
|
||||
setup->speed, setup->speed_freq, setup->clock_src);
|
||||
debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
|
||||
setup->speed_freq, setup->clock_src);
|
||||
debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
|
||||
setup->rise_time, setup->fall_time);
|
||||
debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
|
||||
setup->analog_filter ? "On" : "Off", setup->dnf);
|
||||
|
||||
i2c_priv->speed = setup->speed_freq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -773,21 +794,13 @@ static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
|
|||
{
|
||||
struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
|
||||
|
||||
switch (speed) {
|
||||
case I2C_SPEED_STANDARD_RATE:
|
||||
i2c_priv->speed = IC_SPEED_MODE_STANDARD;
|
||||
break;
|
||||
case I2C_SPEED_FAST_RATE:
|
||||
i2c_priv->speed = IC_SPEED_MODE_FAST;
|
||||
break;
|
||||
case I2C_SPEED_FAST_PLUS_RATE:
|
||||
i2c_priv->speed = IC_SPEED_MODE_FAST_PLUS;
|
||||
break;
|
||||
default:
|
||||
if (speed > I2C_SPEED_FAST_PLUS_RATE) {
|
||||
debug("%s: Speed %d not supported\n", __func__, speed);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
i2c_priv->speed = speed;
|
||||
|
||||
return stm32_i2c_hw_config(i2c_priv);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -639,7 +639,8 @@ void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
|
|||
start_sw_done(ctl);
|
||||
/* quasi-dynamic register update*/
|
||||
setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
|
||||
clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
|
||||
clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN |
|
||||
DDRCTRL_PWRCTL_SELFREF_EN);
|
||||
clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
||||
wait_sw_done_ack(ctl);
|
||||
}
|
||||
|
|
@ -652,6 +653,8 @@ void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
|
|||
clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
|
||||
if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
|
||||
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
|
||||
if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN))
|
||||
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
|
||||
setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
||||
wait_sw_done_ack(ctl);
|
||||
}
|
||||
|
|
@ -668,14 +671,34 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
|
|||
{
|
||||
u32 pir;
|
||||
int ret = -EINVAL;
|
||||
char bus_width;
|
||||
|
||||
switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
|
||||
case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
|
||||
bus_width = 8;
|
||||
break;
|
||||
case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
|
||||
bus_width = 16;
|
||||
break;
|
||||
default:
|
||||
bus_width = 32;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
|
||||
ret = board_ddr_power_init(STM32MP_DDR3);
|
||||
else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2)
|
||||
ret = board_ddr_power_init(STM32MP_LPDDR2);
|
||||
else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3)
|
||||
ret = board_ddr_power_init(STM32MP_LPDDR3);
|
||||
|
||||
else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) {
|
||||
if (bus_width == 32)
|
||||
ret = board_ddr_power_init(STM32MP_LPDDR2_32);
|
||||
else
|
||||
ret = board_ddr_power_init(STM32MP_LPDDR2_16);
|
||||
} else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) {
|
||||
if (bus_width == 32)
|
||||
ret = board_ddr_power_init(STM32MP_LPDDR3_32);
|
||||
else
|
||||
ret = board_ddr_power_init(STM32MP_LPDDR3_16);
|
||||
}
|
||||
if (ret)
|
||||
panic("ddr power init failed\n");
|
||||
|
||||
|
|
@ -746,7 +769,8 @@ start:
|
|||
*/
|
||||
set_reg(priv, REGPHY_REG, &config->p_reg);
|
||||
set_reg(priv, REGPHY_TIMING, &config->p_timing);
|
||||
set_reg(priv, REGPHY_CAL, &config->p_cal);
|
||||
if (config->p_cal_present)
|
||||
set_reg(priv, REGPHY_CAL, &config->p_cal);
|
||||
|
||||
if (INTERACTIVE(STEP_PHY_INIT))
|
||||
goto start;
|
||||
|
|
@ -781,13 +805,16 @@ start:
|
|||
|
||||
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
|
||||
|
||||
debug("DDR DQS training : ");
|
||||
if (config->p_cal_present) {
|
||||
debug("DDR DQS training skipped.\n");
|
||||
} else {
|
||||
debug("DDR DQS training : ");
|
||||
/* 8. Disable Auto refresh and power down by setting
|
||||
* - RFSHCTL3.dis_au_refresh = 1
|
||||
* - PWRCTL.powerdown_en = 0
|
||||
* - DFIMISC.dfiinit_complete_en = 0
|
||||
*/
|
||||
stm32mp1_refresh_disable(priv->ctl);
|
||||
stm32mp1_refresh_disable(priv->ctl);
|
||||
|
||||
/* 9. Program PUBL PGCR to enable refresh during training and rank to train
|
||||
* not done => keep the programed value in PGCR
|
||||
|
|
@ -795,14 +822,15 @@ start:
|
|||
|
||||
/* 10. configure PUBL PIR register to specify which training step to run */
|
||||
/* warning : RVTRN is not supported by this PUBL */
|
||||
stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
|
||||
stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
|
||||
|
||||
/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
|
||||
ddrphy_idone_wait(priv->phy);
|
||||
ddrphy_idone_wait(priv->phy);
|
||||
|
||||
/* 12. set back registers in step 8 to the orginal values if desidered */
|
||||
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
|
||||
config->c_reg.pwrctl);
|
||||
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
|
||||
config->c_reg.pwrctl);
|
||||
} /* if (config->p_cal_present) */
|
||||
|
||||
/* enable uMCTL2 AXI port 0 and 1 */
|
||||
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
|
||||
|
|
|
|||
|
|
@ -170,6 +170,7 @@ struct stm32mp1_ddr_config {
|
|||
struct stm32mp1_ddrphy_reg p_reg;
|
||||
struct stm32mp1_ddrphy_timing p_timing;
|
||||
struct stm32mp1_ddrphy_cal p_cal;
|
||||
bool p_cal_present;
|
||||
};
|
||||
|
||||
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
|
||||
|
|
|
|||
|
|
@ -260,6 +260,7 @@ struct stm32mp1_ddrphy {
|
|||
|
||||
#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0)
|
||||
|
||||
#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
|
||||
#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
|
||||
#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
|
||||
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ static void stm32mp1_do_usage(void)
|
|||
"help displays help\n"
|
||||
"info displays DDR information\n"
|
||||
"info <param> <val> changes DDR information\n"
|
||||
" with <param> = step, name, size or speed\n"
|
||||
" with <param> = step, name, size, speed or cal\n"
|
||||
"freq displays the DDR PHY frequency in kHz\n"
|
||||
"freq <freq> changes the DDR PHY frequency\n"
|
||||
"param [type|reg] prints input parameters\n"
|
||||
|
|
@ -160,6 +160,7 @@ static void stm32mp1_do_info(struct ddr_info *priv,
|
|||
printf("name = %s\n", config->info.name);
|
||||
printf("size = 0x%x\n", config->info.size);
|
||||
printf("speed = %d kHz\n", config->info.speed);
|
||||
printf("cal = %d\n", config->p_cal_present);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -208,6 +209,16 @@ static void stm32mp1_do_info(struct ddr_info *priv,
|
|||
}
|
||||
return;
|
||||
}
|
||||
if (!strcmp(argv[1], "cal")) {
|
||||
if (strict_strtoul(argv[2], 10, &value) < 0 ||
|
||||
(value != 0 && value != 1)) {
|
||||
printf("invalid value %s\n", argv[2]);
|
||||
} else {
|
||||
config->p_cal_present = value;
|
||||
printf("cal = %d\n", config->p_cal_present);
|
||||
}
|
||||
return;
|
||||
}
|
||||
printf("argument %s invalid\n", argv[1]);
|
||||
}
|
||||
|
||||
|
|
@ -367,7 +378,6 @@ bool stm32mp1_ddr_interactive(void *priv,
|
|||
enum stm32mp1_ddr_interact_step step,
|
||||
const struct stm32mp1_ddr_config *config)
|
||||
{
|
||||
const char *prompt = "DDR>";
|
||||
char buffer[CONFIG_SYS_CBSIZE];
|
||||
char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
|
||||
int argc;
|
||||
|
|
@ -403,13 +413,12 @@ bool stm32mp1_ddr_interactive(void *priv,
|
|||
}
|
||||
|
||||
printf("%d:%s\n", step, step_str[step]);
|
||||
printf("%s\n", prompt);
|
||||
|
||||
if (next_step > step)
|
||||
return false;
|
||||
|
||||
while (next_step == step) {
|
||||
cli_readline_into_buffer(prompt, buffer, 0);
|
||||
cli_readline_into_buffer("DDR>", buffer, 0);
|
||||
argc = cli_simple_parse_line(buffer, argv);
|
||||
if (!argc)
|
||||
continue;
|
||||
|
|
|
|||
|
|
@ -65,18 +65,22 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
|
|||
struct clk axidcg;
|
||||
struct stm32mp1_ddr_config config;
|
||||
|
||||
#define PARAM(x, y) \
|
||||
{ x,\
|
||||
offsetof(struct stm32mp1_ddr_config, y),\
|
||||
sizeof(config.y) / sizeof(u32)}
|
||||
#define PARAM(x, y, z) \
|
||||
{ .name = x, \
|
||||
.offset = offsetof(struct stm32mp1_ddr_config, y), \
|
||||
.size = sizeof(config.y) / sizeof(u32), \
|
||||
.present = z, \
|
||||
}
|
||||
|
||||
#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
|
||||
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
|
||||
#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
|
||||
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
|
||||
#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
|
||||
|
||||
const struct {
|
||||
const char *name; /* name in DT */
|
||||
const u32 offset; /* offset in config struct */
|
||||
const u32 size; /* size of parameters */
|
||||
bool * const present; /* presence indication for opt */
|
||||
} param[] = {
|
||||
CTL_PARAM(reg),
|
||||
CTL_PARAM(timing),
|
||||
|
|
@ -84,7 +88,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
|
|||
CTL_PARAM(perf),
|
||||
PHY_PARAM(reg),
|
||||
PHY_PARAM(timing),
|
||||
PHY_PARAM(cal)
|
||||
PHY_PARAM_OPT(cal)
|
||||
};
|
||||
|
||||
config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
|
||||
|
|
@ -103,11 +107,25 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
|
|||
param[idx].size);
|
||||
debug("%s: %s[0x%x] = %d\n", __func__,
|
||||
param[idx].name, param[idx].size, ret);
|
||||
if (ret) {
|
||||
if (ret &&
|
||||
(ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
|
||||
pr_err("%s: Cannot read %s, error=%d\n",
|
||||
__func__, param[idx].name, ret);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (param[idx].present) {
|
||||
/* save presence of optional parameters */
|
||||
*param[idx].present = true;
|
||||
if (ret == -FDT_ERR_NOTFOUND) {
|
||||
*param[idx].present = false;
|
||||
#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
|
||||
/* reset values if used later */
|
||||
memset((void *)((u32)&config +
|
||||
param[idx].offset),
|
||||
0, param[idx].size * sizeof(u32));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "axidcg", &axidcg);
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@
|
|||
#include <ram.h>
|
||||
#include <reset.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
#include "stm32mp1_ddr_regs.h"
|
||||
#include "stm32mp1_ddr.h"
|
||||
|
|
@ -75,6 +77,133 @@ static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl)
|
|||
return nb_bytes;
|
||||
}
|
||||
|
||||
static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl)
|
||||
{
|
||||
/* Count bank address bits */
|
||||
u8 bits = 0;
|
||||
u32 reg, val;
|
||||
|
||||
reg = readl(&ctl->addrmap1);
|
||||
/* addrmap1.addrmap_bank_b1 */
|
||||
val = (reg & GENMASK(5, 0)) >> 0;
|
||||
if (val <= 31)
|
||||
bits++;
|
||||
/* addrmap1.addrmap_bank_b2 */
|
||||
val = (reg & GENMASK(13, 8)) >> 8;
|
||||
if (val <= 31)
|
||||
bits++;
|
||||
/* addrmap1.addrmap_bank_b3 */
|
||||
val = (reg & GENMASK(21, 16)) >> 16;
|
||||
if (val <= 31)
|
||||
bits++;
|
||||
|
||||
return bits;
|
||||
}
|
||||
|
||||
static u8 get_nb_col(struct stm32mp1_ddrctl *ctl)
|
||||
{
|
||||
u8 bits;
|
||||
u32 reg, val;
|
||||
|
||||
/* Count column address bits, start at 2 for b0 and b1 (fixed) */
|
||||
bits = 2;
|
||||
|
||||
reg = readl(&ctl->addrmap2);
|
||||
/* addrmap2.addrmap_col_b2 */
|
||||
val = (reg & GENMASK(3, 0)) >> 0;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap2.addrmap_col_b3 */
|
||||
val = (reg & GENMASK(11, 8)) >> 8;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap2.addrmap_col_b4 */
|
||||
val = (reg & GENMASK(19, 16)) >> 16;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap2.addrmap_col_b5 */
|
||||
val = (reg & GENMASK(27, 24)) >> 24;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
|
||||
reg = readl(&ctl->addrmap3);
|
||||
/* addrmap3.addrmap_col_b6 */
|
||||
val = (reg & GENMASK(3, 0)) >> 0;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap3.addrmap_col_b7 */
|
||||
val = (reg & GENMASK(11, 8)) >> 8;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap3.addrmap_col_b8 */
|
||||
val = (reg & GENMASK(19, 16)) >> 16;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap3.addrmap_col_b9 */
|
||||
val = (reg & GENMASK(27, 24)) >> 24;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
|
||||
reg = readl(&ctl->addrmap4);
|
||||
/* addrmap4.addrmap_col_b10 */
|
||||
val = (reg & GENMASK(3, 0)) >> 0;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap4.addrmap_col_b11 */
|
||||
val = (reg & GENMASK(11, 8)) >> 8;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
|
||||
return bits;
|
||||
}
|
||||
|
||||
static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
|
||||
{
|
||||
/* Count row address bits */
|
||||
u8 bits = 0;
|
||||
u32 reg, val;
|
||||
|
||||
reg = readl(&ctl->addrmap5);
|
||||
/* addrmap5.addrmap_row_b0 */
|
||||
val = (reg & GENMASK(3, 0)) >> 0;
|
||||
if (val <= 11)
|
||||
bits++;
|
||||
/* addrmap5.addrmap_row_b1 */
|
||||
val = (reg & GENMASK(11, 8)) >> 8;
|
||||
if (val <= 11)
|
||||
bits++;
|
||||
/* addrmap5.addrmap_row_b2_10 */
|
||||
val = (reg & GENMASK(19, 16)) >> 16;
|
||||
if (val <= 11)
|
||||
bits += 9;
|
||||
else
|
||||
printf("warning: addrmap5.addrmap_row_b2_10 not supported\n");
|
||||
/* addrmap5.addrmap_row_b11 */
|
||||
val = (reg & GENMASK(27, 24)) >> 24;
|
||||
if (val <= 11)
|
||||
bits++;
|
||||
|
||||
reg = readl(&ctl->addrmap6);
|
||||
/* addrmap6.addrmap_row_b12 */
|
||||
val = (reg & GENMASK(3, 0)) >> 0;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap6.addrmap_row_b13 */
|
||||
val = (reg & GENMASK(11, 8)) >> 8;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap6.addrmap_row_b14 */
|
||||
val = (reg & GENMASK(19, 16)) >> 16;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
/* addrmap6.addrmap_row_b15 */
|
||||
val = (reg & GENMASK(27, 24)) >> 24;
|
||||
if (val <= 7)
|
||||
bits++;
|
||||
|
||||
return bits;
|
||||
}
|
||||
|
||||
static void itm_soft_reset(struct stm32mp1_ddrphy *phy)
|
||||
{
|
||||
stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
|
||||
|
|
@ -169,8 +298,13 @@ static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy,
|
|||
}
|
||||
|
||||
/* Basic BIST configuration for data lane tests. */
|
||||
static void config_BIST(struct stm32mp1_ddrphy *phy)
|
||||
static void config_BIST(struct stm32mp1_ddrctl *ctl,
|
||||
struct stm32mp1_ddrphy *phy)
|
||||
{
|
||||
u8 nb_bank = get_nb_bank(ctl);
|
||||
u8 nb_row = get_nb_row(ctl);
|
||||
u8 nb_col = get_nb_col(ctl);
|
||||
|
||||
/* Selects the SDRAM bank address to be used during BIST. */
|
||||
u32 bbank = 0;
|
||||
/* Selects the SDRAM row address to be used during BIST. */
|
||||
|
|
@ -190,18 +324,20 @@ static void config_BIST(struct stm32mp1_ddrphy *phy)
|
|||
* must be 0 with single rank
|
||||
*/
|
||||
u32 brank = 0;
|
||||
|
||||
/* Specifies the maximum SDRAM bank address to be used during
|
||||
* BIST before the address & increments to the next rank.
|
||||
*/
|
||||
u32 bmbank = 1;
|
||||
u32 bmbank = (1 << nb_bank) - 1;
|
||||
/* Specifies the maximum SDRAM row address to be used during
|
||||
* BIST before the address & increments to the next bank.
|
||||
*/
|
||||
u32 bmrow = 0x7FFF; /* To check */
|
||||
u32 bmrow = (1 << nb_row) - 1;
|
||||
/* Specifies the maximum SDRAM column address to be used during
|
||||
* BIST before the address & increments to the next row.
|
||||
*/
|
||||
u32 bmcol = 0x3FF; /* To check */
|
||||
u32 bmcol = (1 << nb_col) - 1;
|
||||
|
||||
u32 bmode_conf = 0x00000001; /* DRam mode */
|
||||
u32 bdxen_conf = 0x00000001; /* BIST on Data byte */
|
||||
u32 bdpat_conf = 0x00000002; /* Select LFSR pattern */
|
||||
|
|
@ -223,8 +359,6 @@ static void config_BIST(struct stm32mp1_ddrphy *phy)
|
|||
|
||||
writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0);
|
||||
writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1);
|
||||
|
||||
/* To check this line : */
|
||||
writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2);
|
||||
}
|
||||
|
||||
|
|
@ -246,6 +380,8 @@ static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte,
|
|||
bool result = true; /* BIST_SUCCESS */
|
||||
u32 cnt = 0;
|
||||
u32 error = 0;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
bist->test_result = true;
|
||||
|
||||
|
|
@ -266,7 +402,7 @@ run:
|
|||
writel(rand(), &phy->bistlsr);
|
||||
|
||||
/* some delay to reset BIST */
|
||||
mdelay(1);
|
||||
udelay(10);
|
||||
|
||||
/*Perform BIST Run*/
|
||||
clrsetbits_le32(&phy->bistrr,
|
||||
|
|
@ -274,27 +410,29 @@ run:
|
|||
0x00000001);
|
||||
/* Write BISTRR.BINST = 3?b001; */
|
||||
|
||||
/* Wait for a number of CTL clocks before reading BIST register*/
|
||||
/* Wait 300 ctl_clk cycles; ... IS it really needed?? */
|
||||
/* Perform BIST Instruction Stop*/
|
||||
/* Write BISTRR.BINST = 3?b010;*/
|
||||
/* poll on BISTGSR.BDONE and wait max 1000 us */
|
||||
ret = readl_poll_timeout(&phy->bistgsr, val,
|
||||
val & DDRPHYC_BISTGSR_BDDONE, 1000);
|
||||
|
||||
/* poll on BISTGSR.BDONE. If 0, wait. ++TODO Add timeout */
|
||||
while (!(readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDDONE))
|
||||
;
|
||||
|
||||
/*Check if received correct number of words*/
|
||||
/* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
|
||||
if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) ==
|
||||
readl(&phy->bistwcr)) {
|
||||
/*Determine if there is a data comparison error*/
|
||||
/* if (Read BISTGSR.BDXERR = 1?b0) */
|
||||
if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
|
||||
result = false; /* BIST_FAIL; */
|
||||
else
|
||||
result = true; /* BIST_SUCCESS; */
|
||||
} else {
|
||||
if (ret < 0) {
|
||||
printf("warning: BIST timeout\n");
|
||||
result = false; /* BIST_FAIL; */
|
||||
/*Perform BIST Stop */
|
||||
clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002);
|
||||
} else {
|
||||
/*Check if received correct number of words*/
|
||||
/* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
|
||||
if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT)
|
||||
== readl(&phy->bistwcr)) {
|
||||
/*Determine if there is a data comparison error*/
|
||||
/* if (Read BISTGSR.BDXERR = 1?b0) */
|
||||
if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
|
||||
result = false; /* BIST_FAIL; */
|
||||
else
|
||||
result = true; /* BIST_SUCCESS; */
|
||||
} else {
|
||||
result = false; /* BIST_FAIL; */
|
||||
}
|
||||
}
|
||||
|
||||
/* loop while success */
|
||||
|
|
@ -394,7 +532,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
|
||||
|
||||
/* Config the BIST block */
|
||||
config_BIST(phy);
|
||||
config_BIST(ctl, phy);
|
||||
pr_debug("BIST Config done.\n");
|
||||
|
||||
/* Train each byte */
|
||||
|
|
@ -807,7 +945,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
|
|||
clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
|
||||
|
||||
/* Config the BIST block */
|
||||
config_BIST(phy);
|
||||
config_BIST(ctl, phy);
|
||||
|
||||
for (byte = 0; byte < nb_bytes; byte++) {
|
||||
if (ctrlc()) {
|
||||
|
|
@ -1182,15 +1320,17 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
|
|||
dqs_gate_values[byte][0],
|
||||
dqs_gate_values[byte][1]);
|
||||
pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
|
||||
set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
|
||||
set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
|
||||
}
|
||||
} else {
|
||||
/* if intermitant, restore defaut values */
|
||||
pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
|
||||
set_r0dgsl_delay(phy, byte, 0);
|
||||
set_r0dgps_delay(phy, byte, 2);
|
||||
dqs_gate_values[byte][0] = 0;
|
||||
dqs_gate_values[byte][1] = 2;
|
||||
}
|
||||
set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
|
||||
set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
|
||||
printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n",
|
||||
byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]);
|
||||
|
||||
/* return 0 if intermittent or if both left_bound
|
||||
* and right_bound are not found
|
||||
|
|
@ -1227,7 +1367,7 @@ static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl,
|
|||
clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
|
||||
|
||||
/* config the bist block */
|
||||
config_BIST(phy);
|
||||
config_BIST(ctl, phy);
|
||||
|
||||
for (byte = 0; byte < nb_bytes; byte++) {
|
||||
if (ctrlc()) {
|
||||
|
|
@ -1281,11 +1421,16 @@ static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl,
|
|||
{
|
||||
u32 rfshctl3 = readl(&ctl->rfshctl3);
|
||||
u32 pwrctl = readl(&ctl->pwrctl);
|
||||
u32 derateen = readl(&ctl->derateen);
|
||||
enum test_result res;
|
||||
|
||||
writel(0x0, &ctl->derateen);
|
||||
stm32mp1_refresh_disable(ctl);
|
||||
|
||||
res = read_dqs_gating(ctl, phy, string);
|
||||
|
||||
stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
|
||||
writel(derateen, &ctl->derateen);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
|
@ -1296,11 +1441,16 @@ static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl,
|
|||
{
|
||||
u32 rfshctl3 = readl(&ctl->rfshctl3);
|
||||
u32 pwrctl = readl(&ctl->pwrctl);
|
||||
u32 derateen = readl(&ctl->derateen);
|
||||
enum test_result res;
|
||||
|
||||
writel(0x0, &ctl->derateen);
|
||||
stm32mp1_refresh_disable(ctl);
|
||||
|
||||
res = bit_deskew(ctl, phy, string);
|
||||
|
||||
stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
|
||||
writel(derateen, &ctl->derateen);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
|
@ -1311,11 +1461,16 @@ static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl,
|
|||
{
|
||||
u32 rfshctl3 = readl(&ctl->rfshctl3);
|
||||
u32 pwrctl = readl(&ctl->pwrctl);
|
||||
u32 derateen = readl(&ctl->derateen);
|
||||
enum test_result res;
|
||||
|
||||
writel(0x0, &ctl->derateen);
|
||||
stm32mp1_refresh_disable(ctl);
|
||||
|
||||
res = eye_training(ctl, phy, string);
|
||||
|
||||
stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
|
||||
writel(derateen, &ctl->derateen);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,14 +6,13 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <fdtdec.h>
|
||||
#include <clk.h>
|
||||
#include <timer.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-armv7/globaltimer.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct sti_timer_priv {
|
||||
struct globaltimer *global_timer;
|
||||
};
|
||||
|
|
@ -44,13 +43,24 @@ static int sti_timer_probe(struct udevice *dev)
|
|||
{
|
||||
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
struct sti_timer_priv *priv = dev_get_priv(dev);
|
||||
fdt_addr_t addr;
|
||||
|
||||
uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
|
||||
struct clk clk;
|
||||
int err;
|
||||
ulong ret;
|
||||
|
||||
/* get arm global timer base address */
|
||||
addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
|
||||
priv->global_timer = (struct globaltimer *)addr;
|
||||
priv->global_timer = (struct globaltimer *)dev_read_addr_ptr(dev);
|
||||
if (!priv->global_timer)
|
||||
return -ENOENT;
|
||||
|
||||
err = clk_get_by_index(dev, 0, &clk);
|
||||
if (!err) {
|
||||
ret = clk_get_rate(&clk);
|
||||
if (IS_ERR_VALUE(ret))
|
||||
return ret;
|
||||
uc_priv->clock_rate = ret;
|
||||
} else {
|
||||
uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
|
||||
}
|
||||
|
||||
/* init timer */
|
||||
writel(0x01, &priv->global_timer->ctl);
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
#define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT)
|
||||
|
||||
#define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24)
|
||||
#define STPMIC1_BUCK2_1250000V STPMIC1_BUCK_VOUT(26)
|
||||
#define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30)
|
||||
|
||||
#define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39)
|
||||
|
|
|
|||
Loading…
Reference in a new issue