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rockchip: sdhci: rk3568: fix clock setting logic

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mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.

Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.

Fix it by using MAX(mmc->tran_speed, mmc->clock)

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Vasily Khoruzhick 2023-03-07 13:26:46 -08:00 committed by Kever Yang
parent 5db4972a5b
commit 7786710adb
1 changed files with 3 additions and 3 deletions
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6
drivers/mmc/rockchip_sdhci.c
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@ -401,11 +401,11 @@ static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
uint clock = mmc->tran_speed;
uint clock = mmc->clock;
u32 reg, vendor_reg;
if (!clock)
clock = mmc->clock;
if (mmc->tran_speed && mmc->clock > mmc->tran_speed)
clock = mmc->tran_speed;
rk3568_sdhci_emmc_set_clock(host, clock);