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phy: marvell: a3700: add sata comphy on lane 2 with invert option
- This patch moves sata phy powerup from dedicate phy to compphy and adds invert option for sata powerup routine. Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90 Signed-off-by: zachary <zhangzg@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53601 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: Igal Liberman <igall@marvell.com> [a.heider: adapt to mainline] Signed-off-by: Andre Heider <a.heider@gmail.com> Tested-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
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9bfb567e5f
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1 changed files with 14 additions and 19 deletions
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@ -273,16 +273,23 @@ static void reg_set_indirect(u32 reg, u16 data, u16 mask)
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*
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* return: 1 if PLL locked (OK), 0 otherwise (FAIL)
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*/
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static int comphy_sata_power_up(void)
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static int comphy_sata_power_up(u32 invert)
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{
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int ret;
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u32 data = 0;
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debug_enter();
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/*
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* 0. Swap SATA TX lines
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* 0. Check the Polarity invert bits
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*/
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reg_set_indirect(vphy_sync_pattern_reg, bs_txd_inv, bs_txd_inv);
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if (invert & PHY_POLARITY_TXD_INVERT)
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data |= bs_txd_inv;
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if (invert & PHY_POLARITY_RXD_INVERT)
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data |= bs_rxd_inv;
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reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv);
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/*
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* 1. Select 40-bit data width width
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@ -924,22 +931,6 @@ void comphy_dedicated_phys_init(void)
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}
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}
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node = fdt_node_offset_by_compatible(blob, -1,
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"marvell,armada-3700-ahci");
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if (node > 0) {
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if (fdtdec_get_is_enabled(blob, node)) {
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ret = comphy_sata_power_up();
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if (!ret)
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printf("Failed to initialize SATA PHY\n");
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else
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debug("SATA PHY init succeed\n");
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} else {
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debug("SATA node is disabled\n");
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}
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} else {
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debug("No SATA node in DT\n");
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}
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node = fdt_node_offset_by_compatible(blob, -1,
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"marvell,armada-8k-sdhci");
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if (node <= 0) {
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@ -1007,6 +998,10 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
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comphy_map->invert);
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break;
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case PHY_TYPE_SATA0:
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ret = comphy_sata_power_up(comphy_map->invert);
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break;
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default:
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debug("Unknown SerDes type, skip initialize SerDes %d\n",
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lane);
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