mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-17 22:49:02 +00:00
Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
commit
77524d2c9d
47 changed files with 655 additions and 458 deletions
|
|
@ -1,2 +1,3 @@
|
|||
obj-$(CONFIG_AT91FAMILY) += at91-common/
|
||||
obj-$(CONFIG_TEGRA) += $(SOC)-common/
|
||||
obj-$(CONFIG_TEGRA) += tegra-common/
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ obj-y += cache_v7.o
|
|||
obj-y += cpu.o
|
||||
obj-y += syslib.o
|
||||
|
||||
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
|
||||
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
|
||||
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
|
||||
obj-y += lowlevel_init.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
|
||||
unsigned int has_emac()
|
||||
{
|
||||
return cpu_is_sama5d31() || cpu_is_sama5d35();
|
||||
return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
|
||||
}
|
||||
|
||||
unsigned int has_gmac()
|
||||
|
|
@ -42,6 +42,8 @@ char *get_cpu_name()
|
|||
return "SAMA5D34";
|
||||
case ARCH_EXID_SAMA5D35:
|
||||
return "SAMA5D35";
|
||||
case ARCH_EXID_SAMA5D36:
|
||||
return "SAMA5D36";
|
||||
default:
|
||||
return "Unknown CPU type";
|
||||
}
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||||
|
|
@ -82,7 +84,7 @@ void at91_seriald_hw_init(void)
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|||
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
|
||||
|
||||
/* Enable clock */
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||||
at91_periph_clk_enable(ATMEL_ID_SYS);
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||||
at91_periph_clk_enable(ATMEL_ID_DBGU);
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||||
}
|
||||
|
||||
#if defined(CONFIG_ATMEL_SPI)
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ int timer_init(void)
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|||
at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
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||||
|
||||
/* Enable PITC Clock */
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||||
at91_periph_clk_enable(ATMEL_ID_SYS);
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||||
at91_periph_clk_enable(ATMEL_ID_PIT);
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||||
|
||||
/* Enable PITC */
|
||||
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
|
||||
|
|
|
|||
12
arch/arm/cpu/at91-common/Makefile
Normal file
12
arch/arm/cpu/at91-common/Makefile
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# (C) Copyright 2000-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2013 Atmel Corporation
|
||||
# Bo Shen <voice.shen@atmel.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
|
||||
obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
|
||||
124
arch/arm/cpu/at91-common/mpddrc.c
Normal file
124
arch/arm/cpu/at91-common/mpddrc.c
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/atmel_mpddrc.h>
|
||||
|
||||
static inline void atmel_mpddr_op(int mode, u32 ram_address)
|
||||
{
|
||||
struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
|
||||
|
||||
writel(mode, &mpddr->mr);
|
||||
writel(0, ram_address);
|
||||
}
|
||||
|
||||
int ddr2_init(const unsigned int ram_address,
|
||||
const struct atmel_mpddr *mpddr_value)
|
||||
{
|
||||
struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
|
||||
u32 ba_off, cr;
|
||||
|
||||
/* Compute bank offset according to NC in configuration register */
|
||||
ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
|
||||
if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
|
||||
ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
|
||||
|
||||
ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
|
||||
|
||||
/* Program the memory device type into the memory device register */
|
||||
writel(mpddr_value->md, &mpddr->md);
|
||||
|
||||
/* Program the configuration register */
|
||||
writel(mpddr_value->cr, &mpddr->cr);
|
||||
|
||||
/* Program the timing register */
|
||||
writel(mpddr_value->tpr0, &mpddr->tpr0);
|
||||
writel(mpddr_value->tpr1, &mpddr->tpr1);
|
||||
writel(mpddr_value->tpr2, &mpddr->tpr2);
|
||||
|
||||
/* Issue a NOP command */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
|
||||
|
||||
/* A 200 us is provided to precede any signal toggle */
|
||||
udelay(200);
|
||||
|
||||
/* Issue a NOP command */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
|
||||
|
||||
/* Issue an all banks precharge command */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
|
||||
|
||||
/* Issue an extended mode register set(EMRS2) to choose operation */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
|
||||
ram_address + (0x2 << ba_off));
|
||||
|
||||
/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
|
||||
ram_address + (0x3 << ba_off));
|
||||
|
||||
/*
|
||||
* Issue an extended mode register set(EMRS1) to enable DLL and
|
||||
* program D.I.C (output driver impedance control)
|
||||
*/
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
|
||||
ram_address + (0x1 << ba_off));
|
||||
|
||||
/* Enable DLL reset */
|
||||
cr = readl(&mpddr->cr);
|
||||
writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
|
||||
|
||||
/* A mode register set(MRS) cycle is issued to reset DLL */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
|
||||
|
||||
/* Issue an all banks precharge command */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
|
||||
|
||||
/* Two auto-refresh (CBR) cycles are provided */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
|
||||
|
||||
/* Disable DLL reset */
|
||||
cr = readl(&mpddr->cr);
|
||||
writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
|
||||
|
||||
/* A mode register set (MRS) cycle is issued to disable DLL reset */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
|
||||
|
||||
/* Set OCD calibration in default state */
|
||||
cr = readl(&mpddr->cr);
|
||||
writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
|
||||
|
||||
/*
|
||||
* An extended mode register set (EMRS1) cycle is issued
|
||||
* to OCD default value
|
||||
*/
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
|
||||
ram_address + (0x1 << ba_off));
|
||||
|
||||
/* OCD calibration mode exit */
|
||||
cr = readl(&mpddr->cr);
|
||||
writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
|
||||
|
||||
/*
|
||||
* An extended mode register set (EMRS1) cycle is issued
|
||||
* to enable OCD exit
|
||||
*/
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
|
||||
ram_address + (0x1 << ba_off));
|
||||
|
||||
/* A nornal mode command is provided */
|
||||
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
|
||||
|
||||
/* Perform a write access to any DDR2-SDRAM address */
|
||||
writel(0, ram_address);
|
||||
|
||||
/* Write the refresh rate */
|
||||
writel(mpddr_value->rtr, &mpddr->rtr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
57
arch/arm/cpu/at91-common/phy.c
Normal file
57
arch/arm/cpu/at91-common/phy.c
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* Stelian Pop <stelian@popies.net>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
*
|
||||
* (C) Copyright 2012
|
||||
* Markus Hubig <mhubig@imko.de>
|
||||
* IMKO GmbH <www.imko.de>
|
||||
*
|
||||
* Copyright (C) 2013 DENX Software Engineering, hs@denx.de
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
void at91_phy_reset(void)
|
||||
{
|
||||
unsigned long erstl;
|
||||
unsigned long start = get_timer(0);
|
||||
unsigned long const timeout = 1000; /* 1000ms */
|
||||
at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
|
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/*
|
||||
* Need to reset PHY -> 500ms reset
|
||||
* Reset PHY by pulling the NRST line for 500ms to low. To do so
|
||||
* disable user reset for low level on NRST pin and poll the NRST
|
||||
* level in reset status register.
|
||||
*/
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
|
||||
/* Wait for end of hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
|
||||
/* avoid shutdown by watchdog */
|
||||
WATCHDOG_RESET();
|
||||
mdelay(10);
|
||||
|
||||
/* timeout for not getting stuck in an endless loop */
|
||||
if (get_timer(start) >= timeout) {
|
||||
puts("*** ERROR: Timeout waiting for PHY reset!\n");
|
||||
break;
|
||||
}
|
||||
};
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
}
|
||||
90
arch/arm/cpu/at91-common/spl.c
Normal file
90
arch/arm/cpu/at91-common/spl.c
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_wdt.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <spl.h>
|
||||
|
||||
static void at91_disable_wdt(void)
|
||||
{
|
||||
struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
|
||||
|
||||
writel(AT91_WDT_MR_WDDIS, &wdt->mr);
|
||||
}
|
||||
|
||||
void at91_plla_init(u32 pllar)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
|
||||
writel(pllar, &pmc->pllar);
|
||||
while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
|
||||
;
|
||||
}
|
||||
|
||||
void at91_mck_init(u32 mckr)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(&pmc->mckr);
|
||||
tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
|
||||
AT91_PMC_MCKR_MDIV_MASK |
|
||||
AT91_PMC_MCKR_PLLADIV_2);
|
||||
tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
|
||||
AT91_PMC_MCKR_MDIV_MASK |
|
||||
AT91_PMC_MCKR_PLLADIV_2);
|
||||
writel(tmp, &pmc->mckr);
|
||||
|
||||
while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
return BOOT_DEVICE_MMC1;
|
||||
#endif
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
||||
u32 spl_boot_mode(void)
|
||||
{
|
||||
switch (spl_boot_device()) {
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
case BOOT_DEVICE_MMC1:
|
||||
return MMCSD_MODE_FAT;
|
||||
break;
|
||||
#endif
|
||||
case BOOT_DEVICE_NONE:
|
||||
default:
|
||||
hang();
|
||||
}
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
/* disable watchdog */
|
||||
at91_disable_wdt();
|
||||
|
||||
/* PMC configuration */
|
||||
at91_pmc_init();
|
||||
|
||||
at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
|
||||
|
||||
timer_init();
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
mem_init();
|
||||
}
|
||||
50
arch/arm/cpu/at91-common/u-boot-spl.lds
Normal file
50
arch/arm/cpu/at91-common/u-boot-spl.lds
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*
|
||||
* (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
|
||||
LENGTH = CONFIG_SPL_MAX_SIZE }
|
||||
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
|
||||
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__start = .;
|
||||
arch/arm/cpu/armv7/start.o (.text*)
|
||||
*(.text*)
|
||||
} >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
_end = .;
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} >.sdram
|
||||
}
|
||||
|
|
@ -22,5 +22,10 @@ void at91_spi1_hw_init(unsigned long cs_mask);
|
|||
void at91_udp_hw_init(void);
|
||||
void at91_uhp_hw_init(void);
|
||||
void at91_lcd_hw_init(void);
|
||||
void at91_plla_init(u32 pllar);
|
||||
void at91_mck_init(u32 mckr);
|
||||
void at91_pmc_init(void);
|
||||
void mem_init(void);
|
||||
void at91_phy_reset(void);
|
||||
|
||||
#endif /* AT91_COMMON_H */
|
||||
|
|
|
|||
|
|
@ -151,37 +151,4 @@ int at91_get_pio_value(unsigned port, unsigned pin);
|
|||
#define AT91_PIO_PORTD 0x3
|
||||
#define AT91_PIO_PORTE 0x4
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
|
||||
#define PIO_PER 0x00 /* Enable Register */
|
||||
#define PIO_PDR 0x04 /* Disable Register */
|
||||
#define PIO_PSR 0x08 /* Status Register */
|
||||
#define PIO_OER 0x10 /* Output Enable Register */
|
||||
#define PIO_ODR 0x14 /* Output Disable Register */
|
||||
#define PIO_OSR 0x18 /* Output Status Register */
|
||||
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
|
||||
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
|
||||
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
|
||||
#define PIO_SODR 0x30 /* Set Output Data Register */
|
||||
#define PIO_CODR 0x34 /* Clear Output Data Register */
|
||||
#define PIO_ODSR 0x38 /* Output Data Status Register */
|
||||
#define PIO_PDSR 0x3c /* Pin Data Status Register */
|
||||
#define PIO_IER 0x40 /* Interrupt Enable Register */
|
||||
#define PIO_IDR 0x44 /* Interrupt Disable Register */
|
||||
#define PIO_IMR 0x48 /* Interrupt Mask Register */
|
||||
#define PIO_ISR 0x4c /* Interrupt Status Register */
|
||||
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
|
||||
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
|
||||
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
|
||||
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
|
||||
#define PIO_PUER 0x64 /* Pull-up Enable Register */
|
||||
#define PIO_PUSR 0x68 /* Pull-up Status Register */
|
||||
#define PIO_ASR 0x70 /* Peripheral A Select Register */
|
||||
#define PIO_BSR 0x74 /* Peripheral B Select Register */
|
||||
#define PIO_ABSR 0x78 /* AB Status Register */
|
||||
#define PIO_OWER 0xa0 /* Output Write Enable Register */
|
||||
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
|
||||
#define PIO_OWSR 0xa8 /* Output Write Status Register */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,20 +25,4 @@ typedef struct at91_pit {
|
|||
#define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff)
|
||||
#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK)
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
|
||||
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
|
||||
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
|
||||
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
|
||||
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
|
||||
|
||||
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
|
||||
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
|
||||
|
||||
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
|
||||
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
|
||||
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
|
||||
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
|
||||
|
||||
#endif /* CONFIG_AT91_LEGACY */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,13 +14,15 @@
|
|||
#ifndef AT91_PMC_H
|
||||
#define AT91_PMC_H
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
|
||||
#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
|
||||
#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
|
||||
#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
|
||||
#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#else
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
|
|
@ -73,7 +75,11 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
|
||||
#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
|
||||
#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
|
||||
#ifdef CONFIG_SAMA5D3
|
||||
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
|
||||
#else
|
||||
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
|
||||
#endif
|
||||
#define AT91_PMC_PLLAR_29 0x20000000
|
||||
#define AT91_PMC_PLLBR_USBDIV_1 0x00000000
|
||||
#define AT91_PMC_PLLBR_USBDIV_2 0x10000000
|
||||
|
|
@ -124,8 +130,8 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
|
||||
#endif
|
||||
|
||||
#define AT91_PMC_MCKR_PLLADIV_1 0x00001000
|
||||
#define AT91_PMC_MCKR_PLLADIV_2 0x00002000
|
||||
#define AT91_PMC_MCKR_PLLADIV_1 0x00000000
|
||||
#define AT91_PMC_MCKR_PLLADIV_2 0x00001000
|
||||
|
||||
#define AT91_PMC_IXR_MOSCS 0x00000001
|
||||
#define AT91_PMC_IXR_LOCKA 0x00000002
|
||||
|
|
@ -137,13 +143,6 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_IXR_PCKRDY2 0x00000400
|
||||
#define AT91_PMC_IXR_PCKRDY3 0x00000800
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
|
||||
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
|
||||
|
||||
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
|
||||
#endif
|
||||
|
||||
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
||||
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
||||
|
|
@ -159,34 +158,18 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
|
||||
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
|
||||
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
|
||||
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
|
||||
|
||||
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
|
||||
#endif
|
||||
|
||||
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
|
||||
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
|
||||
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
|
||||
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
|
||||
#endif
|
||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
|
||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
||||
#endif
|
||||
|
||||
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
||||
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
|
||||
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
|
||||
#endif
|
||||
|
||||
#define AT91_PMC_DIV (0xff << 0) /* Divider */
|
||||
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
|
||||
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
|
||||
|
|
@ -198,9 +181,6 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
|
||||
#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
|
||||
#endif
|
||||
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
|
||||
#define AT91_PMC_CSS_SLOW (0 << 0)
|
||||
#define AT91_PMC_CSS_MAIN (1 << 0)
|
||||
|
|
@ -228,9 +208,6 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_PDIV_1 (0 << 12)
|
||||
#define AT91_PMC_PDIV_2 (1 << 12)
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */
|
||||
#endif
|
||||
#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
|
||||
#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
|
||||
#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
|
||||
|
|
@ -238,13 +215,6 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
|
||||
#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
|
||||
|
||||
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
|
||||
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
|
||||
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
|
||||
#endif
|
||||
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
|
||||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||
|
|
@ -255,13 +225,6 @@ typedef struct at91_pmc {
|
|||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
|
||||
#endif
|
||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
|
||||
#endif /* CONFIG_AT91_LEGACY */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -118,6 +118,6 @@ typedef struct at91_spi {
|
|||
|
||||
#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
|
||||
|
||||
#endif /* CONFIG_AT91_LEGACY */
|
||||
#endif /* CONFIG_ATMEL_LEGACY */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -40,25 +40,4 @@ typedef struct at91_wdt {
|
|||
#define AT91_WDT_MR_WDDBGHLT 0x10000000
|
||||
#define AT91_WDT_MR_WDIDLEHLT 0x20000000
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
|
||||
#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
|
||||
#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
|
||||
#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
|
||||
|
||||
#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
|
||||
#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
|
||||
#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
|
||||
#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
|
||||
#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
|
||||
#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
|
||||
#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
|
||||
#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
|
||||
#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
|
||||
|
||||
#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
|
||||
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
|
||||
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
|
||||
|
||||
#endif /* CONFIG_AT91_LEGACY */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -55,75 +55,6 @@
|
|||
#define AT91_RSTC_BASE 0xfffffd00
|
||||
#define AT91_PIT_BASE 0xfffffd30
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91CAP9_BASE_UDPHS 0xfff78000
|
||||
#define AT91CAP9_BASE_TCB0 0xfff7c000
|
||||
#define AT91CAP9_BASE_TC0 0xfff7c000
|
||||
#define AT91CAP9_BASE_TC1 0xfff7c040
|
||||
#define AT91CAP9_BASE_TC2 0xfff7c080
|
||||
#define AT91CAP9_BASE_MCI0 0xfff80000
|
||||
#define AT91CAP9_BASE_MCI1 0xfff84000
|
||||
#define AT91CAP9_BASE_TWI 0xfff88000
|
||||
#define AT91CAP9_BASE_US0 0xfff8c000
|
||||
#define AT91CAP9_BASE_US1 0xfff90000
|
||||
#define AT91CAP9_BASE_US2 0xfff94000
|
||||
#define AT91CAP9_BASE_SSC0 0xfff98000
|
||||
#define AT91CAP9_BASE_SSC1 0xfff9c000
|
||||
#define AT91CAP9_BASE_AC97C 0xfffa0000
|
||||
#define AT91CAP9_BASE_SPI0 0xfffa4000
|
||||
#define AT91CAP9_BASE_SPI1 0xfffa8000
|
||||
#define AT91CAP9_BASE_CAN 0xfffac000
|
||||
#define AT91CAP9_BASE_PWMC 0xfffb8000
|
||||
#define AT91CAP9_BASE_EMAC 0xfffbc000
|
||||
#define AT91CAP9_BASE_ADC 0xfffc0000
|
||||
#define AT91CAP9_BASE_ISI 0xfffc4000
|
||||
#define AT91_BASE_SYS 0xffffe200
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
|
||||
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
|
||||
#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
|
||||
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91_USART0 AT91CAP9_BASE_US0
|
||||
#define AT91_USART1 AT91CAP9_BASE_US1
|
||||
#define AT91_USART2 AT91CAP9_BASE_US2
|
||||
|
||||
/*
|
||||
* SCKCR flags
|
||||
*/
|
||||
#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
|
||||
#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
|
||||
#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
|
||||
#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
|
||||
#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
|
||||
#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
|
||||
|
||||
#endif /* CONFIG_AT91_LEGACY */
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -73,64 +73,4 @@ typedef struct at91_smc {
|
|||
#define AT91_SMC_MODE_PS_16 0x20000000
|
||||
#define AT91_SMC_MODE_PS_32 0x30000000
|
||||
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
|
||||
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
|
||||
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
|
||||
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
|
||||
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
|
||||
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
|
||||
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
|
||||
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
|
||||
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
|
||||
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
|
||||
|
||||
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
|
||||
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
|
||||
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
|
||||
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
|
||||
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
|
||||
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
|
||||
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
|
||||
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
|
||||
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
|
||||
|
||||
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
|
||||
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
|
||||
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
|
||||
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
|
||||
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
|
||||
|
||||
#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
|
||||
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
|
||||
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
|
||||
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
|
||||
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
|
||||
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
|
||||
#define AT91_SMC_EXNWMODE_READY (3 << 4)
|
||||
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
|
||||
#define AT91_SMC_BAT_SELECT (0 << 8)
|
||||
#define AT91_SMC_BAT_WRITE (1 << 8)
|
||||
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
|
||||
#define AT91_SMC_DBW_8 (0 << 12)
|
||||
#define AT91_SMC_DBW_16 (1 << 12)
|
||||
#define AT91_SMC_DBW_32 (2 << 12)
|
||||
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
|
||||
#define AT91_SMC_TDF_(x) ((x) << 16)
|
||||
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
|
||||
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
|
||||
#define AT91_SMC_PS (3 << 28) /* Page Size */
|
||||
#define AT91_SMC_PS_4 (0 << 28)
|
||||
#define AT91_SMC_PS_8 (1 << 28)
|
||||
#define AT91_SMC_PS_16 (2 << 28)
|
||||
#define AT91_SMC_PS_32 (3 << 28)
|
||||
|
||||
#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
|
||||
#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
|
||||
#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
|
||||
#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
|
||||
#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
115
arch/arm/include/asm/arch-at91/atmel_mpddrc.h
Normal file
115
arch/arm/include/asm/arch-at91/atmel_mpddrc.h
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ATMEL_MPDDRC_H__
|
||||
#define __ATMEL_MPDDRC_H__
|
||||
|
||||
/*
|
||||
* Only define the needed register in mpddr
|
||||
* If other register needed, will add them later
|
||||
*/
|
||||
struct atmel_mpddr {
|
||||
u32 mr;
|
||||
u32 rtr;
|
||||
u32 cr;
|
||||
u32 tpr0;
|
||||
u32 tpr1;
|
||||
u32 tpr2;
|
||||
u32 reserved[2];
|
||||
u32 md;
|
||||
};
|
||||
|
||||
int ddr2_init(const unsigned int ram_address,
|
||||
const struct atmel_mpddr *mpddr);
|
||||
|
||||
/* Bit field in mode register */
|
||||
#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0
|
||||
#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1
|
||||
#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2
|
||||
#define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3
|
||||
#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4
|
||||
#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5
|
||||
#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6
|
||||
#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7
|
||||
|
||||
/* Bit field in configuration register */
|
||||
#define ATMEL_MPDDRC_CR_NC_MASK 0x3
|
||||
#define ATMEL_MPDDRC_CR_NC_COL_9 0x0
|
||||
#define ATMEL_MPDDRC_CR_NC_COL_10 0x1
|
||||
#define ATMEL_MPDDRC_CR_NC_COL_11 0x2
|
||||
#define ATMEL_MPDDRC_CR_NC_COL_12 0x3
|
||||
#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2)
|
||||
#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2)
|
||||
#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2)
|
||||
#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2)
|
||||
#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2)
|
||||
#define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4)
|
||||
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4)
|
||||
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4)
|
||||
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4)
|
||||
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4)
|
||||
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4)
|
||||
#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7)
|
||||
#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8)
|
||||
#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9)
|
||||
#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12)
|
||||
#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17)
|
||||
#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20)
|
||||
#define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21)
|
||||
#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22)
|
||||
#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23)
|
||||
|
||||
/* Bit field in timing parameter 0 register */
|
||||
#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0
|
||||
#define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4
|
||||
#define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8
|
||||
#define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12
|
||||
#define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16
|
||||
#define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20
|
||||
#define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24
|
||||
#define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7
|
||||
#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27
|
||||
#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1
|
||||
#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28
|
||||
#define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf
|
||||
|
||||
/* Bit field in timing parameter 1 register */
|
||||
#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0
|
||||
#define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f
|
||||
#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8
|
||||
#define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff
|
||||
#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16
|
||||
#define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff
|
||||
#define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24
|
||||
#define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf
|
||||
|
||||
/* Bit field in timing parameter 2 register */
|
||||
#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0
|
||||
#define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4
|
||||
#define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8
|
||||
#define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf
|
||||
#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12
|
||||
#define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7
|
||||
#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16
|
||||
#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf
|
||||
|
||||
/* Bit field in Memory Device Register */
|
||||
#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3
|
||||
#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6
|
||||
#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4)
|
||||
#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4)
|
||||
#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4)
|
||||
|
||||
#endif
|
||||
|
|
@ -79,6 +79,7 @@
|
|||
#define ARCH_EXID_SAMA5D33 0x00414300
|
||||
#define ARCH_EXID_SAMA5D34 0x00414301
|
||||
#define ARCH_EXID_SAMA5D35 0x00584300
|
||||
#define ARCH_EXID_SAMA5D36 0x00004301
|
||||
|
||||
#define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3)
|
||||
#define cpu_is_sama5d31() (cpu_is_sama5d3() && \
|
||||
|
|
@ -89,6 +90,8 @@
|
|||
(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
|
||||
#define cpu_is_sama5d35() (cpu_is_sama5d3() && \
|
||||
(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
|
||||
#define cpu_is_sama5d36() (cpu_is_sama5d3() && \
|
||||
(get_extension_chip_id() == ARCH_EXID_SAMA5D36))
|
||||
|
||||
/*
|
||||
* User Peripherals physical base addresses.
|
||||
|
|
|
|||
20
arch/arm/include/asm/arch-at91/spl.h
Normal file
20
arch/arm/include/asm/arch-at91/spl.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
enum {
|
||||
BOOT_DEVICE_NONE,
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
BOOT_DEVICE_MMC1,
|
||||
BOOT_DEVICE_MMC2,
|
||||
BOOT_DEVICE_MMC2_2,
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -16,7 +16,6 @@
|
|||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_pio.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/at91sam9263.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
|
|
@ -76,25 +75,12 @@ static void vl_ma2sc_nand_hw_init(void)
|
|||
#ifdef CONFIG_MACB
|
||||
static void vl_ma2sc_macb_hw_init(void)
|
||||
{
|
||||
unsigned long erstl;
|
||||
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
||||
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
|
||||
|
||||
/* Enable clock */
|
||||
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
|
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
/* Wait for end hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
|
||||
;
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
at91_phy_reset();
|
||||
|
||||
at91_macb_hw_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
|
@ -67,8 +66,6 @@ static void afeb9260_macb_hw_init(void)
|
|||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
|
||||
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
|
||||
unsigned long erstl;
|
||||
|
||||
|
||||
/* Enable EMAC clock */
|
||||
|
|
@ -94,20 +91,7 @@ static void afeb9260_macb_hw_init(void)
|
|||
pin_to_mask(AT91_PIN_PA28),
|
||||
&pioa->pudr);
|
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
|
||||
/* Wait for end hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
|
||||
;
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
|
||||
&rstc->mr);
|
||||
|
||||
at91_phy_reset();
|
||||
|
||||
/* Re-enable pull-up */
|
||||
writel(pin_to_mask(AT91_PIN_PA14) |
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <atmel_mci.h>
|
||||
|
||||
|
|
@ -73,8 +72,6 @@ static void at91sam9260ek_macb_hw_init(void)
|
|||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
|
||||
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
|
||||
unsigned long erstl;
|
||||
|
||||
/* Enable EMAC clock */
|
||||
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
|
||||
|
|
@ -98,21 +95,7 @@ static void at91sam9260ek_macb_hw_init(void)
|
|||
pin_to_mask(AT91_PIN_PA28),
|
||||
&pioa->pudr);
|
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
|
||||
/* Wait for end hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
|
||||
;
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
|
||||
&rstc->mr);
|
||||
at91_phy_reset();
|
||||
|
||||
/* Re-enable pull-up */
|
||||
writel(pin_to_mask(AT91_PIN_PA14) |
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/at91_matrix.h>
|
||||
#include <asm/arch/at91_pio.h>
|
||||
#include <asm/arch/clk.h>
|
||||
|
|
@ -82,10 +81,9 @@ static void at91sam9263ek_nand_hw_init(void)
|
|||
#ifdef CONFIG_MACB
|
||||
static void at91sam9263ek_macb_hw_init(void)
|
||||
{
|
||||
unsigned long erstl;
|
||||
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
||||
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
|
||||
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
|
||||
|
||||
/* Enable clock */
|
||||
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
|
||||
|
||||
|
|
@ -97,23 +95,10 @@ static void at91sam9263ek_macb_hw_init(void)
|
|||
*
|
||||
* PHY has internal pull-down
|
||||
*/
|
||||
|
||||
writel(1 << 25, &pio->pioc.pudr);
|
||||
writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
|
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
/* Wait for end hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
|
||||
;
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
at91_phy_reset();
|
||||
|
||||
/* Re-enable pull-up */
|
||||
writel(1 << 25, &pio->pioc.puer);
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <lcd.h>
|
||||
|
|
@ -88,8 +87,6 @@ static void at91sam9m10g45ek_macb_hw_init(void)
|
|||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
|
||||
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
|
||||
unsigned long erstl;
|
||||
|
||||
/* Enable clock */
|
||||
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
|
||||
|
|
@ -107,21 +104,7 @@ static void at91sam9m10g45ek_macb_hw_init(void)
|
|||
pin_to_mask(AT91_PIN_PA13),
|
||||
&pioa->pudr);
|
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
|
||||
/* Wait for end hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
|
||||
;
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
|
||||
&rstc->mr);
|
||||
at91_phy_reset();
|
||||
|
||||
/* Re-enable pull-up */
|
||||
writel(pin_to_mask(AT91_PIN_PA15) |
|
||||
|
|
|
|||
|
|
@ -20,6 +20,9 @@
|
|||
#include <micrel.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/atmel_mpddrc.h>
|
||||
#include <asm/arch/at91_wdt.h>
|
||||
|
||||
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
|
||||
#include <asm/arch/atmel_usba_udc.h>
|
||||
|
|
@ -158,6 +161,12 @@ void lcd_show_board_info(void)
|
|||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOA);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOB);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOC);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOD);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOE);
|
||||
|
||||
at91_seriald_hw_init();
|
||||
|
||||
return 0;
|
||||
|
|
@ -290,3 +299,85 @@ void spi_cs_deactivate(struct spi_slave *slave)
|
|||
}
|
||||
}
|
||||
#endif /* CONFIG_ATMEL_SPI */
|
||||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
sama5d3xek_mci_hw_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ddr2_conf(struct atmel_mpddr *ddr2)
|
||||
{
|
||||
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
|
||||
|
||||
ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
|
||||
ATMEL_MPDDRC_CR_NR_ROW_14 |
|
||||
ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
|
||||
ATMEL_MPDDRC_CR_ENRDM_ON |
|
||||
ATMEL_MPDDRC_CR_NB_8BANKS |
|
||||
ATMEL_MPDDRC_CR_NDQS_DISABLED |
|
||||
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
|
||||
ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
|
||||
/*
|
||||
* As the DDR2-SDRAm device requires a refresh time is 7.8125us
|
||||
* when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
|
||||
*/
|
||||
ddr2->rtr = 0x411;
|
||||
|
||||
ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
|
||||
8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
|
||||
|
||||
ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
|
||||
200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
|
||||
28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
|
||||
26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
|
||||
|
||||
ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
|
||||
7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
|
||||
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
|
||||
}
|
||||
|
||||
void mem_init(void)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
struct atmel_mpddr ddr2;
|
||||
|
||||
ddr2_conf(&ddr2);
|
||||
|
||||
/* enable MPDDR clock */
|
||||
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
|
||||
writel(0x4, &pmc->scer);
|
||||
|
||||
/* DDRAM2 Controller initialize */
|
||||
ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
|
||||
}
|
||||
|
||||
void at91_pmc_init(void)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 tmp;
|
||||
|
||||
tmp = AT91_PMC_PLLAR_29 |
|
||||
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
|
||||
AT91_PMC_PLLXR_MUL(43) |
|
||||
AT91_PMC_PLLXR_DIV(1);
|
||||
at91_plla_init(tmp);
|
||||
|
||||
writel(0x3 << 8, &pmc->pllicpr);
|
||||
|
||||
tmp = AT91_PMC_MCKR_MDIV_4 |
|
||||
AT91_PMC_MCKR_CSS_PLLA;
|
||||
at91_mck_init(tmp);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
|
|
@ -31,8 +30,6 @@ static void macb_hw_init(void)
|
|||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
|
||||
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
|
||||
unsigned long erstl;
|
||||
|
||||
/* Enable clock */
|
||||
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
|
||||
|
|
@ -54,18 +51,7 @@ static void macb_hw_init(void)
|
|||
/* Enable ethernet power */
|
||||
pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
|
||||
/* Wait for end hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
|
||||
;
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
at91_phy_reset();
|
||||
|
||||
/* Bring the ethernet out of reset */
|
||||
pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
|
||||
|
|
@ -77,8 +76,6 @@ static void sbc35_a9g20_macb_hw_init(void)
|
|||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
|
||||
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
|
||||
unsigned long erstl;
|
||||
|
||||
/* Enable EMAC clock */
|
||||
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
|
||||
|
|
@ -102,21 +99,7 @@ static void sbc35_a9g20_macb_hw_init(void)
|
|||
pin_to_mask(AT91_PIN_PA28),
|
||||
&pioa->pudr);
|
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
|
||||
/* Wait for end hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
|
||||
;
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
|
||||
&rstc->mr);
|
||||
at91_phy_reset();
|
||||
|
||||
/* Re-enable pull-up */
|
||||
writel(pin_to_mask(AT91_PIN_PA14) |
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@
|
|||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_matrix.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/at91_pio.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
|
@ -89,29 +88,14 @@ static void cpu9260_nand_hw_init(void)
|
|||
#ifdef CONFIG_MACB
|
||||
static void cpu9260_macb_hw_init(void)
|
||||
{
|
||||
unsigned long rstcmr;
|
||||
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
||||
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
|
||||
|
||||
/* Enable clock */
|
||||
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
|
||||
|
||||
at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
|
||||
|
||||
rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
|
||||
AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
|
||||
/* Wait for end hardware reset */
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
|
||||
;
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
|
||||
at91_phy_reset();
|
||||
|
||||
at91_macb_hw_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
#include <asm/arch/at91sam9_smc.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_rstc.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
|
|
@ -67,8 +66,6 @@ static void stamp9G20_nand_hw_init(void)
|
|||
static void stamp9G20_macb_hw_init(void)
|
||||
{
|
||||
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
|
||||
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
|
||||
unsigned long erstl;
|
||||
|
||||
/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
|
||||
at91_set_gpio_output(AT91_PIN_PA26, 0);
|
||||
|
|
@ -91,33 +88,7 @@ static void stamp9G20_macb_hw_init(void)
|
|||
pin_to_mask(AT91_PIN_PA28),
|
||||
&pioa->pudr);
|
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
|
||||
|
||||
/* Need to reset PHY -> 500ms reset */
|
||||
writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) &
|
||||
~AT91_RSTC_MR_URSTEN), &rstc->mr);
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
|
||||
|
||||
/* Wait for end of hardware reset */
|
||||
unsigned long start = get_timer(0);
|
||||
unsigned long timeout = 1000; /* 1000ms */
|
||||
|
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
|
||||
|
||||
/* avoid shutdown by watchdog */
|
||||
WATCHDOG_RESET();
|
||||
mdelay(10);
|
||||
|
||||
/* timeout for not getting stuck in an endless loop */
|
||||
if (get_timer(start) >= timeout) {
|
||||
puts("*** ERROR: Timeout waiting for PHY reset!\n");
|
||||
break;
|
||||
};
|
||||
};
|
||||
|
||||
/* Restore NRST value */
|
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
|
||||
&rstc->mr);
|
||||
at91_phy_reset();
|
||||
|
||||
/* Re-enable pull-up */
|
||||
writel(pin_to_mask(AT91_PIN_PA14) |
|
||||
|
|
|
|||
|
|
@ -39,3 +39,10 @@ The method for updating
|
|||
3. add new structures for SoC access
|
||||
4. Convert arch, driver and boards file to new SoC
|
||||
5. remove legacy code, if all boards and drives are ready
|
||||
|
||||
2013-10-30 Andreas Bießmann <andreas.devel@googlemail.com>:
|
||||
|
||||
The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but
|
||||
remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The
|
||||
AT91 spi driver has also some CONFIG_ATMEL_LEGACY stuff left, so another point
|
||||
to fix until this README can be removed.
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/at91_pio.h>
|
||||
#ifdef CONFIG_AT91_LEGACY
|
||||
#ifdef CONFIG_ATMEL_LEGACY
|
||||
#include <asm/arch/gpio.h>
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -10,19 +10,10 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#ifndef CONFIG_AT91_LEGACY
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/at91_emac.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_pio.h>
|
||||
#else
|
||||
/* remove next 5 lines, if all RM9200 boards convert to at91 arch */
|
||||
#include <asm/arch-at91/at91rm9200.h>
|
||||
#include <asm/arch-at91/hardware.h>
|
||||
#include <asm/arch-at91/at91_emac.h>
|
||||
#include <asm/arch-at91/at91_pmc.h>
|
||||
#include <asm/arch-at91/at91_pio.h>
|
||||
#endif
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <malloc.h>
|
||||
|
|
|
|||
|
|
@ -20,7 +20,6 @@ vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE));
|
|||
#ifndef VCBITMASK
|
||||
#define VCBITMASK(bitno) (0x0001 << (bitno % 16))
|
||||
#endif
|
||||
#ifndef CONFIG_AT91_LEGACY
|
||||
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
|
||||
#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
|
||||
do { \
|
||||
|
|
@ -37,20 +36,6 @@ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
|
|||
#define VCXK_ACKNOWLEDGE \
|
||||
(!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \
|
||||
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
|
||||
#else
|
||||
#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
|
||||
((AT91PS_PIO) PORT)->PIO_PER = PIN; \
|
||||
((AT91PS_PIO) PORT)->DDR = PIN; \
|
||||
((AT91PS_PIO) PORT)->PIO_MDDR = PIN; \
|
||||
if (!I0O1) ((AT91PS_PIO) PORT)->PIO_PPUER = PIN;
|
||||
|
||||
#define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN;
|
||||
#define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN;
|
||||
|
||||
#define VCXK_ACKNOWLEDGE \
|
||||
(!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\
|
||||
PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
|
||||
#endif
|
||||
#elif defined(CONFIG_MCF52x2)
|
||||
#include <asm/m5282.h>
|
||||
#ifndef VCBITMASK
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@
|
|||
/* Ethernet */
|
||||
#define CONFIG_MACB
|
||||
#define CONFIG_RESET_PHY_R
|
||||
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
|
||||
/* USB */
|
||||
|
|
|
|||
|
|
@ -181,6 +181,7 @@
|
|||
#define CONFIG_RMII 1
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R 1
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_ATMEL
|
||||
|
|
|
|||
|
|
@ -275,6 +275,7 @@
|
|||
#define CONFIG_RMII 1
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R 1
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_ATMEL
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x73f00000
|
||||
|
||||
#define CONFIG_AT91_LEGACY
|
||||
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
|
|
@ -77,6 +76,10 @@
|
|||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
|
||||
/* No NOR flash */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
|
|
@ -97,9 +100,6 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* No NOR flash */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
/* NAND flash */
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_ATMEL
|
||||
|
|
@ -120,6 +120,7 @@
|
|||
#define CONFIG_RMII
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_EHCI
|
||||
|
|
|
|||
|
|
@ -310,6 +310,7 @@
|
|||
#define CONFIG_RMII
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_MACB_SEARCH_PHY
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
|
||||
/* LEDS */
|
||||
/* Status LED */
|
||||
|
|
|
|||
|
|
@ -41,10 +41,6 @@
|
|||
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
|
||||
#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000
|
||||
|
||||
#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
|
||||
#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
|
||||
#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
|
||||
|
||||
#define CONFIG_BOOT_RETRY_TIME 30
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
|
|
|
|||
|
|
@ -50,15 +50,13 @@
|
|||
#define CONFIG_SYS_MCKR1_VAL \
|
||||
(AT91_PMC_MCKR_CSS_SLOW | \
|
||||
AT91_PMC_MCKR_PRES_1 | \
|
||||
AT91_PMC_MCKR_MDIV_2 | \
|
||||
AT91_PMC_MCKR_PLLADIV_1)
|
||||
AT91_PMC_MCKR_MDIV_2)
|
||||
|
||||
/* PCK/2 = MCK Master Clock from PLLA */
|
||||
#define CONFIG_SYS_MCKR2_VAL \
|
||||
(AT91_PMC_MCKR_CSS_PLLA | \
|
||||
AT91_PMC_MCKR_PRES_1 | \
|
||||
AT91_PMC_MCKR_MDIV_2 | \
|
||||
AT91_PMC_MCKR_PLLADIV_1)
|
||||
AT91_PMC_MCKR_MDIV_2)
|
||||
|
||||
/* define PDC[31:16] as DATA[31:16] */
|
||||
#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
|
||||
|
|
|
|||
|
|
@ -24,7 +24,10 @@
|
|||
#define CONFIG_AT91FAMILY
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
|
|
@ -93,8 +96,12 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x310000
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
|
||||
#endif
|
||||
|
||||
/* SerialFlash */
|
||||
#define CONFIG_CMD_SF
|
||||
|
|
@ -235,4 +242,31 @@
|
|||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
|
||||
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
|
||||
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@
|
|||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R
|
||||
#define CONFIG_MACB_SEARCH_PHY
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_ATMEL
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@
|
|||
#define CONFIG_RMII
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
#define CONFIG_TFTP_PORT
|
||||
#define CONFIG_TFTP_TSIZE
|
||||
|
||||
|
|
@ -74,7 +75,6 @@
|
|||
#define CONFIG_USB_STORAGE
|
||||
|
||||
/* GPIOs and IO expander */
|
||||
#define CONFIG_AT91_LEGACY
|
||||
#define CONFIG_ATMEL_LEGACY
|
||||
#define CONFIG_AT91_GPIO
|
||||
#define CONFIG_AT91_GPIO_PULLUP 1
|
||||
|
|
|
|||
|
|
@ -145,6 +145,7 @@
|
|||
#ifdef CONFIG_MACB
|
||||
# define CONFIG_RMII /* use reduced MII inteface */
|
||||
# define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
|
||||
/* BOOTP and DHCP options */
|
||||
# define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
|
|
|||
|
|
@ -330,6 +330,7 @@
|
|||
#define CONFIG_RMII
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_RETRY_COUNT 5
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
|
||||
|
|
|
|||
|
|
@ -147,7 +147,7 @@ extern struct i2c_bus_hose i2c_bus[];
|
|||
|
||||
# elif (defined(CONFIG_AT91RM9200) || \
|
||||
defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
|
||||
defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY)
|
||||
defined(CONFIG_AT91SAM9263))
|
||||
# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
|
||||
# else
|
||||
# define I2C_SOFT_DECLARATIONS
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue