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ARM: socfpga: vining_fpga: Update generated headers
Update headers generated by quartus to the latest version. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
parent
4a9f633e3d
commit
76f0f01008
4 changed files with 82 additions and 88 deletions
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@ -139,9 +139,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x07900000,
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0x08020000,
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0x00100000,
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0xC8800000,
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0x00003001,
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0x00C00722,
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0xD4380000,
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0xE0003000,
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0x00C00350,
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0x00000000,
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0x00000021,
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0x82000004,
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@ -153,10 +153,10 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x03C80000,
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0x05400000,
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0x03C80000,
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0xE4400000,
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0x00001800,
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0x00600391,
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0x800E4400,
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0x6A1C0000,
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0x70001800,
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0x006001A8,
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0x8006A1C0,
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0x00000001,
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0x40000002,
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0x02A00000,
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@ -167,11 +167,11 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x01E40000,
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0x02A00000,
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0x01E40000,
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0x72200000,
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0x80000C00,
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0x003001C8,
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0xC0072200,
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0x1C880000,
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0x350E0000,
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0x38000C00,
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0x003000D4,
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0xC00350E0,
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0x0D438000,
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0x20000300,
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0x00040000,
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0x50670000,
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@ -200,9 +200,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x15000000,
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0x0F200000,
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0x01FE0000,
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0x00000000,
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0x01800E44,
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0x00391000,
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0xC0000000,
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0x018006A1,
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0x001A8700,
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0x007F8006,
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0x00000000,
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0x0A800001,
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@ -213,11 +213,11 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x07900000,
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0x08020000,
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0x00100000,
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0xC8800000,
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0x00003001,
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0x00C00722,
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0xD4380000,
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0xE0003000,
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0x00C00350,
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0x00000FF0,
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0x72200000,
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0x350E0000,
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0x80000C00,
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0x05400000,
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0x02480000,
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@ -228,9 +228,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x05400000,
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0x03C80000,
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0x6A1C0000,
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0x00001800,
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0x00600391,
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0x800E4400,
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0x70001800,
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0x006001A8,
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0x8006A1C0,
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0x1A870001,
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0x40000600,
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0x02A00040,
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@ -241,11 +241,11 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x01E40000,
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0x02A00000,
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0x01E40000,
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0x72200000,
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0x80000C00,
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0x003001C8,
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0xC0072200,
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0x1C880000,
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0x350E0000,
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0x38000C00,
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0x003000D4,
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0xC00350E0,
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0x0D438000,
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0x20000300,
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0x00040000,
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0x50670000,
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@ -262,9 +262,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x01A00040,
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0x280D0002,
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0x5140680A,
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0x02490340,
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0xD012481A,
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0x0680A280,
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0x01450340,
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0xD00A281A,
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0x0680E380,
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0x10040000,
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0x00200000,
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0x10040000,
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@ -274,9 +274,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x15000000,
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0x0F200000,
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0x01FE0000,
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0x00000000,
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0x01800E44,
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0x00391000,
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0xC0000000,
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0x018006A1,
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0x001A8700,
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0x007F8006,
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0x00000000,
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0x99300001,
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@ -304,8 +304,8 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x5506A000,
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0x00E1D400,
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0x00000000,
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0xC880090C,
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0x00003001,
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0xD438090C,
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0x00003000,
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0x90400000,
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0x00000000,
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0x2020C243,
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@ -325,22 +325,22 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x00104120,
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0x00000200,
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0xAC0D5F80,
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0x7FFFFFFF,
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0x14F36080,
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0x1A041404,
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0xFFFFFFFF,
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0x14F3690D,
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0x1A041414,
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0x00D00000,
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0x14864000,
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0x59647A05,
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0x8A28A3D5,
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0x8A28A3DD,
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0xF6D1451E,
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0x034AD348,
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0x821A0000,
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0x0000D000,
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0x05140680,
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0xD569A47A,
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0xDD59647A,
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0x1E8A28A3,
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0x48F6D145,
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0x00035292,
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0x00034AD3,
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0x00080200,
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0x00001000,
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0x00080200,
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@ -393,27 +393,27 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x0000F200,
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0x00000000,
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0x00000482,
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0x00120800,
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0x00600391,
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0x70120800,
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0x006001A8,
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0x80000000,
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0x00104120,
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0x00000200,
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0xAC0D5F80,
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0x7FFFFFFF,
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0x14F36080,
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0x1A041404,
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0xFFFFFFFF,
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0x14F3690D,
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0x1A041414,
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0x00D00000,
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0x14864000,
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0x59647A05,
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0x8A28A3D5,
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0xF4D1451E,
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0x8A28A3DD,
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0xF6D1451E,
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0x034AD348,
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0x821A0186,
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0x0000D000,
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0x00000680,
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0xD569A47A,
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0x1EF228A3,
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0x48F4D145,
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0xDD59647A,
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0x1E8A28A3,
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0x48F6D145,
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0x00034AD3,
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0x00080200,
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0x00001000,
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@ -452,8 +452,8 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x5506A000,
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0x00E1D400,
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0x00000000,
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0xC880090C,
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0x00003001,
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0xD438090C,
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0x00003000,
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0x90400000,
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0x00000000,
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0x2020C243,
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@ -473,21 +473,21 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x00104120,
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0x00000200,
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0xAC0D5F80,
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0x7FFFFFFF,
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0x14F36080,
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0x1A041404,
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0xFFFFFFFF,
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0x14F3690D,
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0x1A041414,
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0x00D00000,
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0x0C864000,
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0x59647A03,
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0xCB2CA3DD,
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0xF6D9651E,
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0x14864000,
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0x59647A05,
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0x8A28A3DD,
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0xF6D1451E,
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0x034AD348,
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0x821A0000,
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0x0000D000,
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0x00000680,
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0xDD59647A,
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0x1E8A28A3,
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0x48F6D965,
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0x48F6D145,
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0x00034AD3,
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0x00080200,
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0x00001000,
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@ -547,19 +547,19 @@ const unsigned long iocsr_scan_chain3_table[] = {
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0x00104120,
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0x00000200,
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0xAC0D5F80,
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0x7FFFFFFF,
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0x14F16080,
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0x1A041404,
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0xFFFFFFFF,
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0x14F1690D,
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0x1A041414,
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0x00D00000,
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0x04864000,
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0x69A47A01,
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0xF228A3D5,
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0xF4D1451E,
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0x03529248,
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0x14864000,
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0x59647A05,
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0x8A28A3DD,
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0xF6D1451E,
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0x034AD348,
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0x821A0000,
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0x0000D000,
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0x00000680,
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0xD559647A,
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0xDD59647A,
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0x1E8A28A3,
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0x48F6D145,
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0x00034AD3,
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@ -198,12 +198,12 @@ const u8 sys_mgr_init_table[] = {
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0, /* NANDUSEFPGA */
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0, /* UART0USEFPGA */
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0, /* RGMII1USEFPGA */
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1, /* SPIS0USEFPGA */
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0, /* SPIS0USEFPGA */
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0, /* CAN0USEFPGA */
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0, /* I2C0USEFPGA */
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0, /* SDMMCUSEFPGA */
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0, /* QSPIUSEFPGA */
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1, /* SPIS1USEFPGA */
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0, /* SPIS1USEFPGA */
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1, /* RGMII0USEFPGA */
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0, /* UART1USEFPGA */
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0, /* CAN1USEFPGA */
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@ -211,7 +211,7 @@ const u8 sys_mgr_init_table[] = {
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0, /* I2C3USEFPGA */
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0, /* I2C2USEFPGA */
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0, /* I2C1USEFPGA */
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0, /* SPIM1USEFPGA */
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1, /* SPIM1USEFPGA */
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0, /* USB0USEFPGA */
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0 /* SPIM0USEFPGA */
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};
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@ -13,7 +13,7 @@
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#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
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#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
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#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
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#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
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@ -53,7 +53,7 @@
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
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#define CONFIG_HPS_CLK_OSC1_HZ 25000000
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@ -63,18 +63,12 @@
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#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
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#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
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#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
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#define CONFIG_HPS_CLK_OSC1_HZ 25000000
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#define CONFIG_HPS_CLK_OSC2_HZ 25000000
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#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
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#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
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#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
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#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
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#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
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#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
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#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
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#define CONFIG_HPS_CLK_NAND_HZ 488281
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#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
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#define CONFIG_HPS_CLK_QSPI_HZ 400000000
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#define CONFIG_HPS_CLK_QSPI_HZ 320000000
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#define CONFIG_HPS_CLK_SPIM_HZ 200000000
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#define CONFIG_HPS_CLK_CAN0_HZ 12500000
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#define CONFIG_HPS_CLK_CAN1_HZ 12500000
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@ -47,7 +47,7 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
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#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
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#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
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#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
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@ -149,7 +149,7 @@
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#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
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#define MAX_LATENCY_COUNT_WIDTH 5
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#define READ_VALID_FIFO_SIZE 16
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#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
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#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b4
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#define RW_MGR_MEM_ADDRESS_MIRRORING 0
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#define RW_MGR_MEM_DATA_MASK_WIDTH 4
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#define RW_MGR_MEM_DATA_WIDTH 32
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